Refactorings to prepare for explict cap-auth load/store as-user instr…

…uctions
CTSRD-CHERI · Oct 27, 2021 · 5202ae1 · 5202ae1
1 parent 79baa5b
commit 5202ae1
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Showing 5 changed files with 133 additions and 71 deletions.
diff --git a/Makefile b/Makefile
@@ -67,7 +67,8 @@ SAIL_RV64_VM_SRCS = $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_sv39.sail \
 
 SAIL_VM_SRCS =  $(SAIL_CHERI_MODEL_DIR)/cheri_pte.sail $(SAIL_CHERI_MODEL_DIR)/cheri_ptw.sail \
                 $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_common.sail $(SAIL_RISCV_MODEL_DIR)/riscv_vmem_tlb.sail
-SAIL_VM_SRCS += $(SAIL_$(ARCH)_VM_SRCS)
+SAIL_VM_SRCS += $(SAIL_$(ARCH)_VM_SRCS) \
+                $(SAIL_CHERI_MODEL_DIR)/cheri_ptw_late.sail
 
 # Non-instruction sources
 PRELUDE = $(SAIL_RISCV_MODEL_DIR)/prelude.sail \
@@ -98,6 +99,7 @@ SAIL_ARCH_SRCS = $(PRELUDE) \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_types_common.sail \
                  $(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_types.sail \
+                 $(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types_late.sail \
                  $(SAIL_REGS_SRCS) \
                  $(SAIL_SYS_SRCS) \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_platform.sail \
@@ -111,6 +113,7 @@ SAIL_ARCH_RVFI_SRCS = \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_types_common.sail \
                  $(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types.sail \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_types.sail \
+                 $(SAIL_CHERI_MODEL_DIR)/cheri_riscv_types_late.sail \
                  $(SAIL_REGS_SRCS) \
                  $(SAIL_SYS_SRCS) \
                  $(SAIL_RISCV_MODEL_DIR)/riscv_platform.sail \