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CHERI-RISC-V: slightly rearrange SLTI HINT decoder #180

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@nwf nwf commented Oct 14, 2021

  • Restructure the code under the assumption that there will be HINT consumers
    other than TCG_LOG_INSTR.

  • Document the current and near-term allocations of the opcode space:

    • Move the TCG_LOG_INSTR tests to match rs1 == x0, which is the only form that
      we have emitted, but we were never ignoring rs1.

    • Reserve SLTI x0, x31, 0xNNN forms for software's introspective use until
      (and if) RISC-V upstream defines something for that use case.

XREF https://github.com/CTSRD-CHERI/cheri-architecture/pull/78

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@qwattash qwattash left a comment

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Looks good to me.

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@jrtc27 jrtc27 left a comment

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I guess clang-format and checkpatch don't run on .c.inc... :(

target/riscv/insn_trans/trans_rvi.c.inc Outdated Show resolved Hide resolved
target/riscv/insn_trans/trans_rvi.c.inc Outdated Show resolved Hide resolved
target/riscv/insn_trans/trans_rvi.c.inc Outdated Show resolved Hide resolved
target/riscv/insn_trans/trans_rvi.c.inc Outdated Show resolved Hide resolved
- Restructure the code under the assumption that there will be HINT consumers
  other than TCG_LOG_INSTR.

- Document the current and near-term allocations of the opcode space:

  - Move the TCG_LOG_INSTR tests to match rs1 == x0, which is the only form that
    we have emitted, but we were never ignoring rs1.

  - Reserve `SLTI x0, x31, 0xNNN` forms for software's introspective use until
    (and if) RISC-V upstream defines something for that use case.
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4 participants