diff --git a/CHANGELOG.md b/CHANGELOG.md
index e9b36ff..b10b6e6 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -20,6 +20,8 @@
   declarations after inlining
 * Fixed inlining of interfaces and interface-bound modules containing port
   declarations tagged with an attribute
+* Fixed stray attributes producing invalid nested output when attached to
+  inlined interfaces and interface-bounds modules
 * Fixed `` `resetall `` not resetting the `` `default_nettype ``
 
 ### Other Enhancements
diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index 0b1c46a..1f5880e 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -139,6 +139,8 @@ collectDescriptionsM = mapM_
 breakGenerate :: ModuleItem -> [ModuleItem] -> [ModuleItem]
 breakGenerate (Generate genItems) items =
     foldr breakGenerateStep items genItems
+breakGenerate (MIAttr _ (Generate genItems)) items =
+    foldr breakGenerateStep items genItems
 breakGenerate item items = item : items
 
 breakGenerateStep :: GenItem -> [ModuleItem] -> [ModuleItem]
@@ -1064,8 +1066,14 @@ traverseNestedGenItemsM mapper = fullMapper
 traverseNestedGenItems :: Mapper GenItem -> Mapper GenItem
 traverseNestedGenItems = unmonad traverseNestedGenItemsM
 
+innerGenItems :: ModuleItem -> Maybe [GenItem]
+innerGenItems (MIAttr _ item) = innerGenItems item
+innerGenItems (Generate items) = Just items
+innerGenItems _ = Nothing
+
 flattenGenBlocks :: GenItem -> [GenItem]
-flattenGenBlocks (GenModuleItem (Generate items)) = items
+flattenGenBlocks (GenModuleItem item)
+    | Just items <- innerGenItems item = items
 flattenGenBlocks (GenFor _ _ _ GenNull) = []
 flattenGenBlocks GenNull = []
 flattenGenBlocks other = [other]
diff --git a/test/core/interface_array.sv b/test/core/interface_array.sv
index 11a1d8b..8e167ee 100644
--- a/test/core/interface_array.sv
+++ b/test/core/interface_array.sv
@@ -76,6 +76,7 @@ module ModuleB(is);
         bn.tick;
     endtask
     initial $display("Hello I'm ModuleB %0d!", WIDTH);
+    (* this_attribute_is_ignored *)
     ModuleBNested #(WIDTH) bn(is);
 endmodule
 
@@ -96,6 +97,7 @@ endmodule
 module top;
     logic inp;
 
+    (* this_attribute_is_ignored *)
     Interface intfX[2:0](inp);
 
     ModuleA #(0) xa2(intfX[2]);