soapy: Update drivers for new SPI core

Signed-off-by: João Silva <jgc3silva@gmail.com>

software/soapy/src/AXISPI.cpp

@@ -22,21 +22,28 @@ AXISPI::AXISPI(void *base_address): AXIPeripheral(base_address)
     // Detect max clock divider
     this->writeReg(AXI_SPI_REG_SCK_DIV, 0xFFFFFFFF);
 
-    this->max_sck_div = ((uint64_t)this->readReg(AXI_SPI_REG_SCK_DIV) + 1) << 1;
+    uint32_t sck_div_l = this->readReg(AXI_SPI_REG_SCK_DIV);
+    uint32_t sck_div_h = (sck_div_l & 0xFFFF0000) >> 16;
+    sck_div_l &= 0x0000FFFF;
+
+    if(sck_div_l != sck_div_h)
+        throw std::runtime_error("AXI SPI: SCK divider high and low mismatch");
+
+    this->sck_div_mask = sck_div_l;
 
     // Detect capabilities
     uint32_t reg_restore = this->readReg(AXI_SPI_REG_CTRL);
 
     this->writeReg(AXI_SPI_REG_CTRL, AXI_SPI_REG_CTRL_IO_MODE_DUAL);
 
-    if(this->readReg(AXI_SPI_REG_CTRL) & AXI_SPI_REG_CTRL_IO_MODE_DUAL)
+    if((this->readReg(AXI_SPI_REG_CTRL) & 0x30) == AXI_SPI_REG_CTRL_IO_MODE_DUAL)
         this->capabilities.dual_io_supported = true;
     else
         this->capabilities.dual_io_supported = false;
 
     this->writeReg(AXI_SPI_REG_CTRL, AXI_SPI_REG_CTRL_IO_MODE_QUAD);
 
-    if(this->readReg(AXI_SPI_REG_CTRL) & AXI_SPI_REG_CTRL_IO_MODE_QUAD)
+    if((this->readReg(AXI_SPI_REG_CTRL) & 0x30) == AXI_SPI_REG_CTRL_IO_MODE_QUAD)
         this->capabilities.quad_io_supported = true;
     else
         this->capabilities.quad_io_supported = false;
@@ -143,6 +150,9 @@ void AXISPI::setIOMode(AXISPI::IOMode io_mode)
         case AXISPI::IOMode::SINGLE:
             val = AXI_SPI_REG_CTRL_IO_MODE_SINGLE;
         break;
+        case AXISPI::IOMode::SINGLE_3W:
+            val = AXI_SPI_REG_CTRL_IO_MODE_3W;
+        break;
         case AXISPI::IOMode::DUAL:
             if(!this->capabilities.dual_io_supported)
                 throw std::invalid_argument("AXI SPI: Dual IO mode not supported");
@@ -159,14 +169,16 @@ void AXISPI::setIOMode(AXISPI::IOMode io_mode)
             throw std::invalid_argument("AXI SPI: Invalid IO mode");
     }
 
-    this->writeReg(AXI_SPI_REG_CTRL, (this->readReg(AXI_SPI_REG_CTRL) & ~(AXI_SPI_REG_CTRL_IO_MODE_QUAD | AXI_SPI_REG_CTRL_IO_MODE_DUAL | AXI_SPI_REG_CTRL_IO_MODE_SINGLE)) | val);
+    this->writeReg(AXI_SPI_REG_CTRL, (this->readReg(AXI_SPI_REG_CTRL) & ~0x30) | val);
 }
 AXISPI::IOMode AXISPI::getIOMode()
 {
-    switch(this->readReg(AXI_SPI_REG_CTRL) & (AXI_SPI_REG_CTRL_IO_MODE_QUAD | AXI_SPI_REG_CTRL_IO_MODE_DUAL | AXI_SPI_REG_CTRL_IO_MODE_SINGLE))
+    switch(this->readReg(AXI_SPI_REG_CTRL) & 0x30)
     {
         case AXI_SPI_REG_CTRL_IO_MODE_SINGLE:
             return AXISPI::IOMode::SINGLE;
+        case AXI_SPI_REG_CTRL_IO_MODE_3W:
+            return AXISPI::IOMode::SINGLE_3W;
         case AXI_SPI_REG_CTRL_IO_MODE_DUAL:
             return AXISPI::IOMode::DUAL;
         case AXI_SPI_REG_CTRL_IO_MODE_QUAD:
@@ -192,6 +204,9 @@ void AXISPI::configMMIOMode(AXISPI::MMIOConfig &config)
         case AXISPI::IOMode::SINGLE:
             ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_SINGLE;
         break;
+        case AXISPI::IOMode::SINGLE_3W:
+            ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_3W;
+        break;
         case AXISPI::IOMode::DUAL:
             if(!this->capabilities.dual_io_supported)
                 throw std::invalid_argument("AXI SPI: Dual IO mode not supported");
@@ -215,6 +230,9 @@ void AXISPI::configMMIOMode(AXISPI::MMIOConfig &config)
         case AXISPI::IOMode::SINGLE:
             ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_SINGLE;
         break;
+        case AXISPI::IOMode::SINGLE_3W:
+            ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_3W;
+        break;
         case AXISPI::IOMode::DUAL:
             if(!this->capabilities.dual_io_supported)
                 throw std::invalid_argument("AXI SPI: Dual IO mode not supported");
@@ -244,6 +262,9 @@ void AXISPI::configMMIOMode(AXISPI::MMIOConfig &config)
         case AXISPI::IOMode::SINGLE:
             ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_SINGLE;
         break;
+        case AXISPI::IOMode::SINGLE_3W:
+            ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_3W;
+        break;
         case AXISPI::IOMode::DUAL:
             if(!this->capabilities.dual_io_supported)
                 throw std::invalid_argument("AXI SPI: Dual IO mode not supported");
@@ -270,6 +291,9 @@ void AXISPI::configMMIOMode(AXISPI::MMIOConfig &config)
         case AXISPI::IOMode::SINGLE:
             ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_SINGLE;
         break;
+        case AXISPI::IOMode::SINGLE_3W:
+            ctrl2 |= AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_3W;
+        break;
         case AXISPI::IOMode::DUAL:
             if(!this->capabilities.dual_io_supported)
                 throw std::invalid_argument("AXI SPI: Dual IO mode not supported");
@@ -309,31 +333,45 @@ AXISPI::MMIOStats AXISPI::getMMIOStats()
     return stats;
 }
 
-void AXISPI::setClockDivider(uint64_t sck_div)
+void AXISPI::setClockDivider(uint32_t sck_div)
 {
-    if(sck_div < 4 || sck_div > this->max_sck_div)
-        throw std::invalid_argument("AXI SPI: SCK divider must be between 4 and " + std::to_string(this->max_sck_div));
+    uint32_t max_sck_div = ((this->sck_div_mask + 1) << 1);
 
-    if(sck_div & 1)
-        throw std::invalid_argument("AXI SPI: SCK divider must be even");
+    if(sck_div < 3 || sck_div > max_sck_div)
+        throw std::invalid_argument("AXI SPI: SCK divider must be between 3 and " + std::to_string(max_sck_div));
+
+    uint32_t ctrl = this->readReg(AXI_SPI_REG_CTRL);
 
-    if(this->clockEnabled())
+    if(ctrl & AXI_SPI_REG_CTRL_SCK_DIV_EN)
         throw std::runtime_error("AXI SPI: Cannot configure clock dividers while enabled");
 
-    this->writeReg(AXI_SPI_REG_SCK_DIV, (sck_div >> 1) - 1);
+    sck_div -= 2;
+
+    uint16_t sck_div_l = sck_div >> 1;
+    uint16_t sck_div_h = sck_div_l;
+
+    if(sck_div & 1) // Odd divider, one half (high or low) must be longer than the other
+    {
+        // More margin to propagate the data before the sampling edge
+        if(ctrl & AXI_SPI_REG_CTRL_SPI_MODE(1)) // CPHA == 1
+            sck_div_l++;
+        else
+            sck_div_h++;
+    }
+
+    this->writeReg(AXI_SPI_REG_SCK_DIV, (sck_div_h << 16) | sck_div_l);
 }
-uint64_t AXISPI::getClockDivider()
+uint32_t AXISPI::getClockDivider()
 {
-    return (((uint64_t)this->readReg(AXI_SPI_REG_SCK_DIV) + 1) << 1);
+    uint32_t sck_div_l = this->readReg(AXI_SPI_REG_SCK_DIV);
+    uint32_t sck_div_h = (sck_div_l & 0xFFFF0000) >> 16;
+    sck_div_l &= 0x0000FFFF;
+
+    return sck_div_l + sck_div_h + 2;
 }
 void AXISPI::setClockFrequency(uint64_t input_freq, uint64_t sck_freq)
 {
-    uint64_t sck_div = input_freq / sck_freq;
-
-    if(sck_div & 1)
-        sck_div++; // Round up to nearest even number
-
-    this->setClockDivider(sck_div);
+    this->setClockDivider(input_freq / sck_freq);
 }
 uint64_t AXISPI::getClockFrequency(uint64_t input_freq)
 {

software/soapy/src/IDT8V97003.cpp

@@ -89,7 +89,10 @@ IDT8V97003::IDT8V97003(IDT8V97003::SPIConfig spi, IDT8V97003::GPIOConfig ce_gpio
 
     this->reset();
 
-    this->writeReg(IDT8V97003_REG_INTF_CONFIG, IDT8V97003_REG_INTF_CONFIG_ADDR_ASC | IDT8V97003_REG_INTF_CONFIG_SDO_ACTIVE);
+    if(this->spi.controller->getIOMode() == AXISPI::IOMode::SINGLE_3W)
+        this->writeReg(IDT8V97003_REG_INTF_CONFIG, IDT8V97003_REG_INTF_CONFIG_ADDR_ASC);
+    else
+        this->writeReg(IDT8V97003_REG_INTF_CONFIG, IDT8V97003_REG_INTF_CONFIG_ADDR_ASC | IDT8V97003_REG_INTF_CONFIG_SDO_ACTIVE);
 
     uint8_t chip_type = this->readReg(IDT8V97003_REG_CHIP_TYPE);
 
@@ -118,7 +121,11 @@ void IDT8V97003::init()
 
     this->reset();
 
-    this->writeReg(IDT8V97003_REG_INTF_CONFIG, IDT8V97003_REG_INTF_CONFIG_ADDR_ASC | IDT8V97003_REG_INTF_CONFIG_SDO_ACTIVE);
+    if(this->spi.controller->getIOMode() == AXISPI::IOMode::SINGLE_3W)
+        this->writeReg(IDT8V97003_REG_INTF_CONFIG, IDT8V97003_REG_INTF_CONFIG_ADDR_ASC);
+    else
+        this->writeReg(IDT8V97003_REG_INTF_CONFIG, IDT8V97003_REG_INTF_CONFIG_ADDR_ASC | IDT8V97003_REG_INTF_CONFIG_SDO_ACTIVE);
+
     this->writeReg(IDT8V97003_REG_BUF_READ, 0x00); // Reads target the active register, not the buffer
     this->writeReg(IDT8V97003_REG_DSM_CTL, IDT8V97003_REG_DSM_CTL_SHAPE_DITHER_EN);
     this->writeReg(IDT8V97003_REG_MANUAL_VCO, 0x00);
@@ -367,6 +374,26 @@ void IDT8V97003::enableRFOutput(IDT8V97003::RFOutput output, bool enable)
 
     this->rmwReg(reg, (uint8_t)~IDT8V97003_REG_RFOUTA_ENA_RFOUTA_ENA, enable ? IDT8V97003_REG_RFOUTA_ENA_RFOUTA_ENA : 0);
 }
+bool IDT8V97003::isRFOutputEnabled(IDT8V97003::RFOutput output)
+{
+    uint8_t reg;
+
+    switch(output)
+    {
+        case IDT8V97003::RFOutput::RFOUT_A:
+            reg = IDT8V97003_REG_RFOUTA_ENA;
+            break;
+        case IDT8V97003::RFOutput::RFOUT_B:
+            reg = IDT8V97003_REG_RFOUTB_ENA;
+            break;
+        default:
+            throw std::runtime_error("8V97003: Invalid RF output");
+    }
+
+    std::lock_guard<std::recursive_mutex> lock(this->mutex);
+
+    return !!(this->readReg(reg) & IDT8V97003_REG_RFOUTA_ENA_RFOUTA_ENA);
+}
 void IDT8V97003::setRFOutputPower(IDT8V97003::RFOutput output, uint8_t power)
 {
     if(power > 12)
@@ -511,7 +538,7 @@ void IDT8V97003::configReferenceInput(double freq, bool diff)
 
     std::lock_guard<std::recursive_mutex> lock(this->mutex);
 
-    this->rmwReg(IDT8V97003_REG_RDIV_HIGH, (uint8_t)~(IDT8V97003_REG_RDIV_HIGH_REF_DBL_DELAY | IDT8V97003_REG_RDIV_HIGH_INPUT_TYPE), ((freq < 50000000UL) ? IDT8V97003_REG_RDIV_HIGH_REF_DBL_DELAY : 0) | (diff ? IDT8V97003_REG_RDIV_HIGH_INPUT_TYPE : 0));
+    this->rmwReg(IDT8V97003_REG_RDIV_HIGH, (uint8_t)~(IDT8V97003_REG_RDIV_HIGH_REF_DBL_DELAY | IDT8V97003_REG_RDIV_HIGH_INPUT_TYPE), ((freq < 50e6) ? IDT8V97003_REG_RDIV_HIGH_REF_DBL_DELAY : 0) | (diff ? IDT8V97003_REG_RDIV_HIGH_INPUT_TYPE : 0));
 
     this->ref_freq = freq;
 }
@@ -1086,7 +1113,7 @@ double IDT8V97003::getFeedbackDivider()
 }
 bool IDT8V97003::isFeedbackDividerFractional(double& dist)
 {
-    uint8_t buf[10];
+    uint8_t buf[8];
 
     this->readReg(IDT8V97003_REG_NFRAC_LOW, buf, 8);
 

software/soapy/src/SoapyIcyRadio.cpp

@@ -610,7 +610,7 @@ void SoapyIcyRadio::initPeripheralsPreClocks()
                 bit_order = AXISPI::BitOrder::MSB_FIRST;
                 io_mode = AXISPI::IOMode::SINGLE;
                 input_freq = AXI_ACLK_FREQ;
-                sck_freq = 20000000UL;
+                sck_freq = 31250000UL;
             }
             break;
             case AXI_SPI_TRX_INST:
@@ -619,16 +619,16 @@ void SoapyIcyRadio::initPeripheralsPreClocks()
                 bit_order = AXISPI::BitOrder::MSB_FIRST;
                 io_mode = AXISPI::IOMode::SINGLE;
                 input_freq = AXI_ACLK_FREQ;
-                sck_freq = 20000000UL;
+                sck_freq = 31250000UL;
             }
             break;
             case AXI_SPI_SYNTH_INST:
             {
                 mode = AXISPI::Mode::MODE_0;
                 bit_order = AXISPI::BitOrder::MSB_FIRST;
-                io_mode = AXISPI::IOMode::SINGLE;
+                io_mode = AXISPI::IOMode::SINGLE_3W;
                 input_freq = AXI_ACLK_FREQ;
-                sck_freq = 12500000UL;
+                sck_freq = 20000000UL;
             }
             break;
             default:
@@ -1207,6 +1207,19 @@ void SoapyIcyRadio::initPeripheralsPostClocks()
             DLOGF(SOAPY_SDR_DEBUG, "  Distance to integer boundary: %.6f %%", dist * 100);
         else
             DLOGF(SOAPY_SDR_DEBUG, "  PLL in integer mode");
+
+        DLOGF(SOAPY_SDR_DEBUG, "  PLL band selection is %sdone", this->mmw_synth->isBandSelectDone() ? "" : "NOT ");
+        DLOGF(SOAPY_SDR_DEBUG, "  PLL is %slocked", this->mmw_synth->isPLLLocked() ? "" : "NOT ");
+
+        DLOGF(SOAPY_SDR_DEBUG, "  Output A:");
+        DLOGF(SOAPY_SDR_DEBUG, "    Enabled: %s", this->mmw_synth->isRFOutputEnabled(IDT8V97003::RFOutput::RFOUT_A) ? "yes" : "no");
+        DLOGF(SOAPY_SDR_DEBUG, "    Muted: %s", this->mmw_synth->isMuted(IDT8V97003::RFOutput::RFOUT_A) ? "yes" : "no");
+        DLOGF(SOAPY_SDR_DEBUG, "    Power: %u", this->mmw_synth->getRFOutputPower(IDT8V97003::RFOutput::RFOUT_A));
+
+        DLOGF(SOAPY_SDR_DEBUG, "  Output B:");
+        DLOGF(SOAPY_SDR_DEBUG, "    Enabled: %s", this->mmw_synth->isRFOutputEnabled(IDT8V97003::RFOutput::RFOUT_B) ? "yes" : "no");
+        DLOGF(SOAPY_SDR_DEBUG, "    Muted: %s", this->mmw_synth->isMuted(IDT8V97003::RFOutput::RFOUT_B) ? "yes" : "no");
+        DLOGF(SOAPY_SDR_DEBUG, "    Power: %u", this->mmw_synth->getRFOutputPower(IDT8V97003::RFOutput::RFOUT_B));
     }
 
     this->mmw_synth->powerDown();

software/soapy/src/include/AXISPI.hpp

@@ -29,9 +29,10 @@
 #define AXI_SPI_REG_CTRL_CPHA                       BIT(2)
 #define AXI_SPI_REG_CTRL_CPOL                       BIT(3)
 #define AXI_SPI_REG_CTRL_SPI_MODE(n)                (((uint32_t)(n) & 0x03) << 2)
-#define AXI_SPI_REG_CTRL_IO_MODE_SINGLE             BIT(4)
-#define AXI_SPI_REG_CTRL_IO_MODE_DUAL               BIT(5)
-#define AXI_SPI_REG_CTRL_IO_MODE_QUAD               BIT(6)
+#define AXI_SPI_REG_CTRL_IO_MODE_SINGLE             0x00
+#define AXI_SPI_REG_CTRL_IO_MODE_3W                 0x10
+#define AXI_SPI_REG_CTRL_IO_MODE_DUAL               0x20
+#define AXI_SPI_REG_CTRL_IO_MODE_QUAD               0x30
 #define AXI_SPI_REG_CTRL_LSB_FIRST                  BIT(8)
 #define AXI_SPI_REG_CTRL_MMIO_EN_REQ                BIT(12)
 #define AXI_SPI_REG_CTRL_MMIO_EN                    BIT(13)
@@ -60,18 +61,22 @@
 #define AXI_SPI_REG_MMIO_CTRL_1_CONT_READ_EN        BIT(25)
 #define AXI_SPI_REG_MMIO_CTRL_1_CONT_READ_READY     BIT(26)
 
-#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_SINGLE     BIT(0)
-#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_DUAL       BIT(1)
-#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_QUAD       BIT(2)
-#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_SINGLE         BIT(4)
-#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_DUAL           BIT(5)
-#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_QUAD           BIT(6)
-#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_SINGLE        BIT(8)
-#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_DUAL          BIT(9)
-#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_QUAD          BIT(10)
-#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_SINGLE         BIT(12)
-#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_DUAL           BIT(13)
-#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_QUAD           BIT(14)
+#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_SINGLE     0x00
+#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_3W         0x01
+#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_DUAL       0x02
+#define AXI_SPI_REG_MMIO_CTRL_2_RD_INSTR_IO_MODE_QUAD       0x03
+#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_SINGLE         0x00
+#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_3W             0x04
+#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_DUAL           0x08
+#define AXI_SPI_REG_MMIO_CTRL_2_ADDR_IO_MODE_QUAD           0x0C
+#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_SINGLE        0x00
+#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_3W            0x10
+#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_DUAL          0x20
+#define AXI_SPI_REG_MMIO_CTRL_2_DUMMY_IO_MODE_QUAD          0x30
+#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_SINGLE         0x00
+#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_3W             0x40
+#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_DUAL           0x80
+#define AXI_SPI_REG_MMIO_CTRL_2_DATA_IO_MODE_QUAD           0xC0
 #define AXI_SPI_REG_MMIO_CTRL_2_CS_HIGH_WAIT(n)             (((uint32_t)(n) & 0xFF) << 16)
 #define AXI_SPI_REG_MMIO_CTRL_2_CS_LOW_WAIT(n)              (((uint32_t)(n) & 0xFF) << 24)
 
@@ -97,8 +102,9 @@ class AXISPI: public AXIPeripheral
     enum IOMode : uint8_t
     {
         SINGLE = 0,
-        DUAL = 1,
-        QUAD = 2
+        SINGLE_3W = 1,
+        DUAL = 2,
+        QUAD = 3
     };
     struct Capabilities
     {
@@ -146,8 +152,8 @@ class AXISPI: public AXIPeripheral
     void configMMIOMode(AXISPI::MMIOConfig &config);
     AXISPI::MMIOStats getMMIOStats();
 
-    void setClockDivider(uint64_t sck_div);
-    uint64_t getClockDivider();
+    void setClockDivider(uint32_t sck_div);
+    uint32_t getClockDivider();
     void setClockFrequency(uint64_t input_freq, uint64_t sck_freq);
     uint64_t getClockFrequency(uint64_t input_freq);
 
@@ -216,7 +222,7 @@ class AXISPI: public AXIPeripheral
 private:
     std::mutex mutex;
     AXISPI::Capabilities capabilities;
-    uint64_t max_sck_div;
+    uint32_t sck_div_mask;
     uint32_t ss_mask;
 };
 

software/soapy/src/include/IDT8V97003.hpp

@@ -485,6 +485,7 @@ class IDT8V97003
     {
         this->enableRFOutput(output, false);
     }
+    bool isRFOutputEnabled(IDT8V97003::RFOutput output);
     void setRFOutputPower(IDT8V97003::RFOutput output, uint8_t power);
     uint8_t getRFOutputPower(IDT8V97003::RFOutput output);
 

software/soapy/src/include/SPIFlash.hpp

@@ -118,7 +118,7 @@ class SPIFlash
     std::string getDeviceName();
 
     bool busy();
-    void waitNotBusy(uint32_t timeout_ms = 10000);
+    void waitNotBusy(uint32_t timeout_ms = 1000);
 
     void writeEnable();
     void writeDisable();