High throughput JPEG decoder in Verilog for FPGA

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

UART to AXI Stream interface written in VHDL

Tutorials or projects example to use Vivado 2019.2 and Vitis

This project is designed to delay the output of the video stream in AXI-STREAM format.

Various video processing projects will be shared here

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

Synchronous and Asynchronous FIFO with AXI interface

An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals

A one-position buffer compatible with AXI Stream interface

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

AXI stream protocol checking design

Notes after working with Zynq platform using vivado and petalinux

ASIC for executing vectorized gradient descent on linear regression problems.

vivado design to test the skidbuffer IP

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.

A 2x2 mesh NoC compatible with AXI streaming interface

A one-position buffer compatible with AXI Stream interface