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asic-verification

Here are 20 public repositories matching this topic...

troyguo / awesome-dv

Awesome ASIC design verification

asic verification uvm formal-verification asic-verification

Updated Feb 9, 2022

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Oct 21, 2024
Verilog

kumarrishav14 / AXI

VIP for AXI Protocol

uvm sv asic-verification amba-axi design-verification

Updated May 24, 2022
SystemVerilog

wyvernSemi / vproc

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

Updated Nov 20, 2024
VHDL

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

Lampro-Mellon / Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Updated Apr 13, 2021
Scala

m-kru / go-hdl

Hdl is a tool for easing the work with hardware description languages.

asic fpga vhdl asic-verification

Updated Dec 12, 2022
Go

SalomeDevkule7 / Neural-Network-Layer-Generator

Application Specific Integrated Circuit(ASIC)

neural-networks vlsi systemverilog-hdl asic-verification

Updated Jun 7, 2018
SystemVerilog

abdelazeem201 / LEON2

The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.

arm asic fpga simulation vhdl rtl verilog systemverilog soc asic-verification asic-design

Updated May 6, 2023
VHDL

dhruvildarji / MIPS

Made Million Instruction Per Second Processor

mips vhdl microprocessor vlsi asic-verification

Updated Feb 24, 2018

Aperture-Electronic / Indago.NET

.NET Scripting Engine for Cadence(R) Indago(R) Interactive Verification Enviroment

fpga csharp dotnet vhdl verilog cadence asic-verification indago

Updated Jan 26, 2024
C#

williaml33moore / bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Nov 16, 2024
SystemVerilog

kumarrishav14 / I2C

VIP for I2C

i2c uvm system-verilog asic-verification design-verification

Updated Jun 7, 2022

Prithvish04 / optimized_bnn_asic

High-Performance Binary Neural Networks for MNIST Classification: From Software to ASIC

asic mnist mnist-classification bnn asic-verification tensorflow-lite asic-design

Updated Jun 29, 2024
VHDL

jpm18 / VLSI-Laboratory-NIT-Rourkela

Laboraory manuals and Discussion

asic asic-verification

Updated Oct 19, 2023
Verilog

Datum-Technology-Corporation / mio_demo

Moore.io Demo Project

asic fpga uvm digital-design asic-verification design-verification asic-design uvm-verification

Updated Mar 29, 2023
SystemVerilog

Pritam-Sethuraman / ALU

vhdl asic-verification asic-design

Updated May 19, 2024
VHDL

SKpro-glitch / RISCV-Processor-ASIC

This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.

open-source processor-architecture asic fpga verilog hardware-designs vlsi verilog-hdl risc-v riscv32 asic-verification processor-design vlsi-design asic-design openlane openlane-flow

Updated Nov 15, 2024
Verilog

asicverif / tcl

TCL examples from the Clif Flynt's classic

tcltk tcl tcl-applications asic-verification

Updated Jan 24, 2018

asicverif / sva

A repo for small SVA examples

systemverilog formal-verification sva asic-verification

Updated Jan 8, 2018

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