Skip to content

Latest commit

 

History

History
246 lines (226 loc) · 8.34 KB

Notes.md

File metadata and controls

246 lines (226 loc) · 8.34 KB
Raw

By Saad Khan

S. No Note
0 RISC-V has 5 steps: fetch, decode, execute, memory ops (optional), and writeback (optional).
0.1 Register File:
  • RISC-V has a 32bit-Register File with 32 Registers of different Types(R, I, S, B, U, J).
  • It also acts as tmp registers to work directly with ALU.
  • it has 5 input ports as A1,A2,A3 and WD3,WE3, and 2 output ports as RD1 and RD2. A3 is the address of the register to store the data which is in WD3 register. it also has a flag, as WE3, known as Write enable on active high.
  • A1, A2 are connected to RD1 & RD2 respectively, to be able to read 2 different registers value/data concurrently, whose addresses are in A1 and A2.
  • A3 is usually the destination register, to store the value in case of addition/subtraction, etc
0.2 Instruction Types:
6 types (R, I, S, B, U, J) of instructions in RISC-V:
  • R-Type (Register Type): An operation on registers (x5, x6).
  • I-Type (Load/Load Immediate): Load variables/registers with values or constants from external memory, where a constant is used.
    • x5, x6, 7; // load Immediate
    • lw x8, offset(Base); // load 32-bit word from memory to x8
    • lw x8, 4(x6); // Memory Base stored in X6 register, with 4 byte as an offset
    • Note: offset is in increments of 4 bytes, in hex. i.e., 4, 8, c, etc.
  • S-Type (Store Type): use to store values from registers in register file to the external memory
    • sw rs2, offset(rs1 (aka Base)); // store word from source register to memory
    • sw x9, 8(x6); // store x9 into memory with base in x6 with 8 offset
    • Note: offset is also known as Immediate or Imm.
  • B-Type (Branch Type):
    • beq x8, x9, 8; // branch if equal, compare x8 and x9 if equal, jump to immediate 8, or point PC to immediate.
0.3 Data Memory
  • it has a signle read/write port. if WE (write enable) is 1, it writes data which is in WD into address A on posedge clk. if the WE is 0, it reads Address A onto RD
0.4 PC: The Program Counter is a standard 32-bit register with a read port and a PCNext value, which points to the next instr. It takes a 32-bit address (A) and reads the corresponding 32-bit data from the instruction memory, outputting it to the RD (read) port.
1 RISC-V prefers 5-stage pipelining, but usually, 14 stages are preferred. We will try to achieve at least 10 stages.
2 Pipelining has 3 types of hazards.
3
  • A) Structural Hazard: When hardware cannot execute planned instruction because of hardware limitation in the next clock cycle. When the processor has a single memory, use separate instruction and data memory.
4
  • B) Data Hazard: When data needed to execute an instruction is not yet available, use bypassing/forwarding or Nops(Stalling) to fix this.
5 Note: Load-use data hazard: Using data that isn't loaded yet, bubbles/wasted cycles are used to stall the computer so once the data gets loaded, then to use it.
6
  • C) Control Hazard: Branching hazard, when needed to make a decision based on one instruction while others are executing, basically calculating whether to branch or not, while the next instruction gets executed. One solution is to stall until the branch condition gets calculated, good but slow. The best solution is to predict branches!!! Mostly take branches' condition as false, if you get wrong and the branch is actually true, just add delay to it.
7 Note: Pipelining only improves throughput.
8 Temporal locality: If a data location is referenced, it is likely to be referenced again.
9 Spatial locality: If a data location is referenced, the location with nearby addresses will likely be referenced soon.
10 Memory hierarchy (Speed): SRAM >> DRAM >> Disk.
11 Memory hierarchy is of different levels, but we can only access 2 adjacent levels at a time.
12 Memories: SRAM -> Cache, DRAM -> Main Memory, flash/magnetic -> secondary memory.

By Zaeem Shakir

S. No Note
1

Verilog Basic Code Examples

  1. module ANDGate(input a, input b, output y);
assign y = a & b;
endmodule
  2. module ORGate(input a, input b, output y);
  assign y = a | b;
endmodule
        
  3. module NOTGate(input a, output y);
  assign y = ~a;
endmodule
        
  4. module RippleCarryAdder(input [3:0] A, input [3:0] B, output [3:0] Sum, output Carry);
  assign Carry = 0;
  genvar i;
  generate
    for (i = 0; i < 4; i = i + 1) begin
      assign Sum[i] = A[i] ^ B[i] ^ Carry;
      assign Carry = (A[i] & B[i]) | (Carry & (A[i] ^ B[i]));
    end
  endgenerate
endmodule
        
  5. module SyncCounter(input clk, input rst, output reg [2:0] count);
  always @(posedge clk) begin
    if (rst)
      count <= 0;
    else
      count <= count + 1;
  end
endmodule
  
  6. module RAM(input [1:0] address, input [7:0] data_in, input write_enable,
           output reg [7:0] data_out);
  reg [7:0] mem [3:0];

    always @(address) begin
data_out <= mem[address];
end
    

    always @(posedge clk) begin
if (write_enable)
mem[address] <= data_in;
end
endmodule

2 .

By Mahnoor Maleeka

S. No Note
1

SystemVerilog VS Traditional Verilog

  • Data Types: SystemVerilog introduces additional data types like logic, bit, byte, int, shortint, longint, enum, struct, union, real, and time. These new data types provide more flexibility in representing and handling different types of data.
  • Interfaces: SystemVerilog introduces interfaces, which are collections of signals and methods.
  • Clocking Blocks: SystemVerilog introduces clocking blocks to model clock and reset signal properties more accurately, particularly with regards to multiple clock domains.
  • Constraints and Randomization: SystemVerilog provides upgraded randomization abilities with the `rand` keyword and constraint blocks. These features enable generating random test cases for verification purposes.
  • Assertions: SystemVerilog incorporates support for assertions using the `assert`, `assume`, `cover`, and `restrict` keywords. These constructs enable designers to specify properties and requirements on signals and variables to check the correctness of the design during simulation.