diff --git a/src/mainboard/system76/gaze17/Kconfig b/src/mainboard/system76/gaze17/Kconfig new file mode 100644 index 00000000000..b4382b7479a --- /dev/null +++ b/src/mainboard/system76/gaze17/Kconfig @@ -0,0 +1,75 @@ +if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GFX_NVIDIA + select DRIVERS_I2C_HID + select EC_SYSTEM76_EC + select EC_SYSTEM76_EC_BAT_THRESHOLDS + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE17_3060_B + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_MEASURED_BOOT + select TPM_RDRESP_NEED_DELAY + +config MAINBOARD_DIR + default "system76/gaze17" + +config MAINBOARD_PART_NUMBER + default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050 + default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Gazelle" + +config MAINBOARD_VERSION + default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050 + default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B + +config VARIANT_DIR + default "3050" if BOARD_SYSTEM76_GAZE17_3050 + default "3060" if BOARD_SYSTEM76_GAZE17_3060_B + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 512 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/system76/gaze17/Kconfig.name b/src/mainboard/system76/gaze17/Kconfig.name new file mode 100644 index 00000000000..be1b252c664 --- /dev/null +++ b/src/mainboard/system76/gaze17/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_SYSTEM76_GAZE17_3050 + bool "gaze17 3050" + +config BOARD_SYSTEM76_GAZE17_3060_B + bool "gaze17 3060-b" diff --git a/src/mainboard/system76/gaze17/Makefile.inc b/src/mainboard/system76/gaze17/Makefile.inc new file mode 100644 index 00000000000..ab7df6c275e --- /dev/null +++ b/src/mainboard/system76/gaze17/Makefile.inc @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/gaze17/acpi/backlight.asl b/src/mainboard/system76/gaze17/acpi/backlight.asl new file mode 100644 index 00000000000..f0202344508 --- /dev/null +++ b/src/mainboard/system76/gaze17/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 40, /* default AC */ + 40, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/gaze17/acpi/mainboard.asl b/src/mainboard/system76/gaze17/acpi/mainboard.asl new file mode 100644 index 00000000000..6d00c31c792 --- /dev/null +++ b/src/mainboard/system76/gaze17/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include + +Scope (\_SB) { + #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + Scope (PEG2) { + #include + } + } +} diff --git a/src/mainboard/system76/gaze17/acpi/sleep.asl b/src/mainboard/system76/gaze17/acpi/sleep.asl new file mode 100644 index 00000000000..83888f3e59e --- /dev/null +++ b/src/mainboard/system76/gaze17/acpi/sleep.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} diff --git a/src/mainboard/system76/gaze17/board_info.txt b/src/mainboard/system76/gaze17/board_info.txt new file mode 100644 index 00000000000..6a222e55783 --- /dev/null +++ b/src/mainboard/system76/gaze17/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: gaze17 +Category: laptop +Release year: 2022 +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/gaze17/bootblock.c b/src/mainboard/system76/gaze17/bootblock.c new file mode 100644 index 00000000000..0dc25dd200b --- /dev/null +++ b/src/mainboard/system76/gaze17/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_init(void) +{ + variant_configure_early_gpios(); +} diff --git a/src/mainboard/system76/gaze17/cmos.default b/src/mainboard/system76/gaze17/cmos.default new file mode 100644 index 00000000000..0d376751c17 --- /dev/null +++ b/src/mainboard/system76/gaze17/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/gaze17/cmos.layout b/src/mainboard/system76/gaze17/cmos.layout new file mode 100644 index 00000000000..a53c3f4bbab --- /dev/null +++ b/src/mainboard/system76/gaze17/cmos.layout @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 983 984 diff --git a/src/mainboard/system76/gaze17/devicetree.cb b/src/mainboard/system76/gaze17/devicetree.cb new file mode 100644 index 00000000000..9eaffd8099b --- /dev/null +++ b/src/mainboard/system76/gaze17/devicetree.cb @@ -0,0 +1,192 @@ +chip soc/intel/alderlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/alderlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/alderlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/alderlake/fsp_params.c) + # FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # Thermal + register "tcc_offset" = "10" + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + +# PM Util (soc/intel/alderlake/pmutil.c) + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_R" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_D" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + #From CPU EDS(TODO) + device ref system_agent on end + device ref pcie5 on + # PCIe PEG2 x8, Clock 3 (DGPU) + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_FSP_DEFAULT, + }" + chip drivers/gfx/nvidia + device pci 00.0 on end # VGA controller + device pci 00.1 on end # Audio device + device pci 00.2 on end # USB xHCI Host controller + device pci 00.3 on end # USB Type-C UCSI controller + end + end + device ref igpu on + # DDIA is eDP + register "ddi_portA_config" = "1" + register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD" + end + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_FSP_DEFAULT, + }" + end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + device ref tcss_root_hub on + device ref tcss_usb3_port1 on end + end + end + device ref tcss_dma0 on end + + # From PCH EDS(TODO) + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref heci1 on end + device ref sata on + register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A) + end + device ref pcie_rp5 on + # PCIe root port #5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_FSP_DEFAULT, + }" + end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_FSP_DEFAULT, + }" + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 6 (GLAN) + # Clock source is shared with LAN and hence marked as free running. + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED, + .PcieRpL1Substates = L1_SS_FSP_DEFAULT, + }" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 1 (SSD1) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR, + .PcieRpL1Substates = L1_SS_FSP_DEFAULT, + }" + end + device ref pch_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0E01" # AP/EC command + register "gen3_dec" = "0x00fc0F01" # AP/EC debug + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden end + device ref hda on + #register "PchHdaAudioLinkHdaEnable" = "1" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/system76/gaze17/dsdt.asl b/src/mainboard/system76/gaze17/dsdt.asl new file mode 100644 index 00000000000..cbf9e6a7e99 --- /dev/null +++ b/src/mainboard/system76/gaze17/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/gaze17/ramstage.c b/src/mainboard/system76/gaze17/ramstage.c new file mode 100644 index 00000000000..4d926c855b5 --- /dev/null +++ b/src/mainboard/system76/gaze17/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + variant_configure_gpios(); +} diff --git a/src/mainboard/system76/gaze17/romstage.c b/src/mainboard/system76/gaze17/romstage.c new file mode 100644 index 00000000000..a78e351f9dd --- /dev/null +++ b/src/mainboard/system76/gaze17/romstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +static const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + // Enable audio link + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/gaze17/variants/3050/data.vbt b/src/mainboard/system76/gaze17/variants/3050/data.vbt new file mode 100644 index 00000000000..c0531fde34c Binary files /dev/null and b/src/mainboard/system76/gaze17/variants/3050/data.vbt differ diff --git a/src/mainboard/system76/gaze17/variants/3050/gpio.c b/src/mainboard/system76/gaze17/variants/3050/gpio.c new file mode 100644 index 00000000000..f332193243c --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3050/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD7_REST + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LANPHYPC + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14 + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3# + _PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000), // TP_ATTN# + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH + PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE# + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + //PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_CFG_GPO(GPP_B7, 1, DEEP), // CARD_PWR_EN + PAD_CFG_GPO(GPP_B8, 1, DEEP), // CARD_RTD3_RST# + //PAD_NC(GPP_B9, NONE), + //PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + _PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED# + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18_STRAP + //PAD_NC(GPP_B19, NONE), + //PAD_NC(GPP_B20, NONE), + //PAD_NC(GPP_B21, NONE), + //PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23_STRAP + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2 + PAD_NC(GPP_C3, NONE), // SML0_CLK + PAD_NC(GPP_C4, NONE), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5_STRAP + PAD_NC(GPP_C6, NONE), // TBT_I2C_SCL + PAD_NC(GPP_C7, NONE), // TBT_I2C_SDA + //PAD_NC(GPP_C8, NONE), + //PAD_NC(GPP_C9, NONE), + //PAD_NC(GPP_C10, NONE), + //PAD_NC(GPP_C11, NONE), + //PAD_NC(GPP_C12, NONE), + //PAD_NC(GPP_C13, NONE), + //PAD_NC(GPP_C14, NONE), + //PAD_NC(GPP_C15, NONE), + //PAD_NC(GPP_C16, NONE), + //PAD_NC(GPP_C17, NONE), + //PAD_NC(GPP_C18, NONE), + //PAD_NC(GPP_C19, NONE), + //PAD_NC(GPP_C20, NONE), + //PAD_NC(GPP_C21, NONE), + //PAD_NC(GPP_C22, NONE), + //PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ# + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ# + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ# + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1 + PAD_CFG_GPO(GPP_D15, 1, DEEP), // LANRTD3_WAKE# + PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN# + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + //PAD_CFG_GP0(GPP_E4, 0, DEEP), // DGPU_PWR_EN + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_NC(GPP_E12, NONE), + PAD_CFG_GPO(GPP_E13, 0, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_E18, NONE), + PAD_NC(GPP_E19, NONE), // GPP_E19_STRAP + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), // GPP_E21_STRAP + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F7, NONE), + //PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPO(GPP_F10, 1, DEEP), // PCIE_GLAN_RST# + PAD_NC(GPP_F11, NONE), // ADDS_CODE + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET# + PAD_NC(GPP_F15, NONE), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ# + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1# + PAD_NC(GPP_F21, NONE), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_CFG_GPO(GPP_H1, 1, DEEP), // M.2_PLT_RST_CNTRL2# + PAD_CFG_GPO(GPP_H2, 1, DEEP), // M.2_PLT_RST_CNTRL3# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_GPI(GPP_H6, NONE, DEEP), // PCH_I2C_SDA + PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL + PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX + PAD_NC(GPP_H12, NONE), + _PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1 + //PAD_NC(GPP_H14, NONE), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK + //PAD_NC(GPP_H16, NONE), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN# + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ# + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT_L + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_R5, NONE), + PAD_CFG_GPO(GPP_R6, 0, DEEP), // GPPR_DMIC_CLK + PAD_CFG_GPO(GPP_R7, 0, DEEP), // GPPR_DMIC_DATA + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/gaze17/variants/3050/gpio_early.c b/src/mainboard/system76/gaze17/variants/3050/gpio_early.c new file mode 100644 index 00000000000..ef2e2d7742b --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3050/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_E4, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/gaze17/variants/3050/hda_verb.c b/src/mainboard/system76/gaze17/variants/3050/hda_verb.c new file mode 100644 index 00000000000..db553e31263 --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3050/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x1558866d, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558866d), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze17/variants/3050/include/variant/gpio.h b/src/mainboard/system76/gaze17/variants/3050/include/variant/gpio.h new file mode 100644 index 00000000000..349f9d19b7b --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3050/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_E4 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x866d1558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/gaze17/variants/3050/overridetree.cb b/src/mainboard/system76/gaze17/variants/3050/overridetree.cb new file mode 100644 index 00000000000..b9362f4cf8c --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3050/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device domain 0 on + subsystemid 0x1558 0x866d inherit + end +end diff --git a/src/mainboard/system76/gaze17/variants/3060/data.vbt b/src/mainboard/system76/gaze17/variants/3060/data.vbt new file mode 100644 index 00000000000..4fe5dd0deac Binary files /dev/null and b/src/mainboard/system76/gaze17/variants/3060/data.vbt differ diff --git a/src/mainboard/system76/gaze17/variants/3060/gpio.c b/src/mainboard/system76/gaze17/variants/3060/gpio.c new file mode 100644 index 00000000000..2755514b5db --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3060/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap 16) + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE# + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0 + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1 + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN + //PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + _PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // DP_E_HPD + PAD_NC(GPP_A16, NONE), // USB_OC3# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + _PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE# + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + //PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + //PAD_CFG_GPO(GPP_B9, 0, DEEP), + //PAD_CFG_GPO(GPP_B10, 0, DEEP), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + _PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED# + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), // Strap 2 of 24 + //PAD_CFG_GPO(GPP_B19, 0, DEEP), + //PAD_CFG_GPO(GPP_B20, 0, DEEP), + //PAD_CFG_GPO(GPP_B21, 0, DEEP), + //PAD_CFG_GPO(GPP_B22, 0, DEEP), + PAD_CFG_GPO(GPP_B23, 0, DEEP), // Strap 8 of 24 + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPO(GPP_C2, 1, PLTRST), // SATA_M2_PWR_EN1 + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 0, DEEP), // Strap 4 of 24 + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA + //PAD_NC(GPP_C8, NONE), + //PAD_NC(GPP_C9, NONE), + //PAD_NC(GPP_C10, NONE), + //PAD_NC(GPP_C11, NONE), + //PAD_NC(GPP_C12, NONE), + //PAD_NC(GPP_C13, NONE), + //PAD_NC(GPP_C14, NONE), + //PAD_NC(GPP_C15, NONE), + //PAD_NC(GPP_C16, NONE), + //PAD_NC(GPP_C17, NONE), + //PAD_NC(GPP_C18, NONE), + //PAD_NC(GPP_C19, NONE), + //PAD_NC(GPP_C20, NONE), + //PAD_NC(GPP_C21, NONE), + //PAD_NC(GPP_C22, NONE), + //PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D4, NONE, DEEP), // PS8461_SW + //PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX4_SSD_CLKREQ# + //PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD_CLKREQ# + //PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ# + //PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEQ_CLKREQ# + PAD_NC(GPP_D9, NONE), + PAD_CFG_GPO(GPP_D10, 0, DEEP), // Strap 6 of 24 + PAD_NC(GPP_D11, NONE), + PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // Strap 7 of 24 + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SATA_M2_PWR_EN2 + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPO(GPP_E6, 0, DEEP), // Strap 12 of 24 + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_NC(GPP_E10, NONE), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPO(GPP_E12, 0, DEEP), // TP_ATTN# + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3 + PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD + PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD + PAD_NC(GPP_E20, NONE), + PAD_CFG_GPO(GPP_E21, 0, DEEP), // Strap 14 of 24 + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST# + //PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST# + //PAD_CFG_GPO(GPP_F8, 0, DEEP), + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPO(GPP_F10, 1, DEEP), // CARD_RTD3_RST# + PAD_NC(GPP_F11, NONE), + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT# + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + //PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ# + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_CPU_SSD1_RST# + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, DEEP), // M2_PCH_SSD_RST# + PAD_CFG_GPO(GPP_H1, 0, DEEP), // Strap 22 of 24 + PAD_CFG_GPO(GPP_H2, 1, DEEP), // M2_WLAN_RST# + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL + PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_H10, NONE, DEEP), // UART0_RXD + PAD_CFG_GPI(GPP_H11, NONE, DEEP), // UART0_TXD + PAD_NC(GPP_H12, NONE), + PAD_CFG_GPI(GPP_H13, NONE, DEEP), // DEVSLP1 + //PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + //PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_CFG_GPI(GPP_H20, NONE, DEEP), // BL_PWW_EN_EC + PAD_CFG_GPI(GPP_H21, NONE, DEEP), // PLVDD_RST_EC + PAD_CFG_GPO(GPP_H22, 0, DEEP), // MUX_CTRL_BIOS + //PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ# + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_CFG_GPO(GPP_R6, 0, DEEP), // DMIC_CLK1 + PAD_CFG_GPO(GPP_R7, 0, DEEP), // DMIC_DATA1 + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/gaze17/variants/3060/gpio_early.c b/src/mainboard/system76/gaze17/variants/3060/gpio_early.c new file mode 100644 index 00000000000..a7ebc083eac --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3060/gpio_early.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + + /* CPU PCIe VGPIO for RP0 */ + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, PLTRST, NF1), + + /* CPU PCIe vGPIO for RP1 */ + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, PLTRST, NF1), + //PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, PLTRST, NF1), +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/gaze17/variants/3060/hda_verb.c b/src/mainboard/system76/gaze17/variants/3060/hda_verb.c new file mode 100644 index 00000000000..5b868fbfa19 --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3060/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x1558867c, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558867c), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/gaze17/variants/3060/include/variant/gpio.h b/src/mainboard/system76/gaze17/variants/3060/include/variant/gpio.h new file mode 100644 index 00000000000..ef90a329cb3 --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3060/include/variant/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_B2 +#define DGPU_PWR_EN GPP_A14 +#define DGPU_GC6 GPP_F13 +#define DGPU_SSID 0x867c1558 + +#ifndef __ACPI__ +void variant_configure_early_gpios(void); +void variant_configure_gpios(void); +#endif + +#endif diff --git a/src/mainboard/system76/gaze17/variants/3060/overridetree.cb b/src/mainboard/system76/gaze17/variants/3060/overridetree.cb new file mode 100644 index 00000000000..5329219fc9e --- /dev/null +++ b/src/mainboard/system76/gaze17/variants/3060/overridetree.cb @@ -0,0 +1,7 @@ +chip soc/intel/alderlake + device domain 0 on + subsystemid 0x1558 0x867c inherit + + device ref gbe on end + end +end