From 8a1848f6d4bae2de06b2ebda2296995d311615b7 Mon Sep 17 00:00:00 2001 From: Aki Van Ness Date: Sun, 17 Nov 2024 16:43:39 -0800 Subject: [PATCH] squishy.gateware.platform: updated the pin directions on the `CIPO` and `COPI` signals on the supervisor interface on the rev2 platform --- squishy/gateware/platform/rev2.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/squishy/gateware/platform/rev2.py b/squishy/gateware/platform/rev2.py index a0f70d0f..5098b1a5 100644 --- a/squishy/gateware/platform/rev2.py +++ b/squishy/gateware/platform/rev2.py @@ -221,8 +221,8 @@ class SquishyRev2(SquishyPlatform, ECP5Platform): # NOTE(aki): The clk can be driven by the MCU *or* the FPGA, which # might cause issues, we need to have an interlock Subsignal('clk', Pins('U2', dir = 'io')), - Subsignal('copi', Pins('W2', dir = 'i')), - Subsignal('cipo', Pins('V2', dir = 'o')), + Subsignal('copi', Pins('W2', dir = 'io')), + Subsignal('cipo', Pins('V2', dir = 'io')), Subsignal('attn', PinsN('T2', dir = 'i')), # This is the CS for the FPGA Subsignal('psram', PinsN('Y2', dir = 'o')), # The bitstram cache PSRAM CS from our side Subsignal('su_attn', Pins('W1', dir = 'o')),