fix aarch64 m1 memory barrier asm code

See #98 and #116
rurban · Mar 8, 2024 · 99f6a24 · 99f6a24
1 parent d8ee2bf
commit 99f6a24
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/mem/mem_primitives_lib.h b/src/mem/mem_primitives_lib.h
@@ -143,6 +143,8 @@
 #define MEMORY_BARRIER ASM_VOLATILE("mfence" ::: "memory")
 #elif defined(__GNUC__) && defined(ASM_INLINE) && defined(__i386__)
 #define MEMORY_BARRIER ASM_VOLATILE("lock; addl $0,0(%%esp)" ::: "memory")
+#elif defined(ASM_INLINE) && defined(HAVE_ARM_NEON) && defined(__aarch64__)
+#define MEMORY_BARRIER ASM_VOLATILE("dmb ish" ::: "memory")
 #elif (defined(__GNUC__) && __GNUC__ >= 4) || defined(HAVE___SYNC_SYNCHRONIZE)
 #define MEMORY_BARRIER __sync_synchronize()
 /* new gcc-5 memory_barrier insn for most archs: