Merge pull request #411 from davidharrishmc/master

Restored *32 attributes to RV_TESTCASE for 7 RV32M tests
riscv-non-isa · Nov 19, 2023 · ede040f · ede040f
2 parents 9f9bdd6 + dd74622
commit ede040f
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Showing 8 changed files with 14 additions and 11 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,8 +1,11 @@
 # CHANGELOG
+
+## [3.8.2.2] -- 2013-11-17
+- Restored *RV32 Check ISA attributes to RV32IM test cases where they were dropped in 3.8.2. Missed these on 3.8.2.1.
+
 ## [3.8.2.1] -- 2013-11-15
-- Restored *RV64 Check ISA attributes to RV64IM test \
-cases where they were dropped in 3.8.2.  Similar to 3.7.5
-
+- Restored *RV64 Check ISA attributes to RV64IM test cases where they were dropped in 3.8.2.  Similar to 3.7.5
+
 ## [3.8.2] - 2023-11-14
 - Added "most negative number divided by -1" case for RV64IM and RV32IM in remw, divw, div and rem tests
 

diff --git a/riscv-test-suite/rv32i_m/M/src/divu-01.S b/riscv-test-suite/rv32i_m/M/src/divu-01.S
@@ -28,8 +28,8 @@ RVMODEL_BOOT
 RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
-
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",divu)
+	
+RVTEST_CASE(0,"//check ISA:=regexp(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",divu) 
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/mul-01.S b/riscv-test-suite/rv32i_m/M/src/mul-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mul)
+RVTEST_CASE(0,"//check ISA:=regexp(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mul)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/mulh-01.S b/riscv-test-suite/rv32i_m/M/src/mulh-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulh)
+RVTEST_CASE(0,"//check ISA:=regexp(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulh)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S b/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhsu)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhsu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/mulhu-01.S b/riscv-test-suite/rv32i_m/M/src/mulhu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhu)
+RVTEST_CASE(0,"//check ISA:=regexp(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/rem-01.S b/riscv-test-suite/rv32i_m/M/src/rem-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",rem)
+RVTEST_CASE(0,"//check ISA:=regexp(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",rem)
 
 RVTEST_SIGBASE(x1,signature_x1_1)
 

diff --git a/riscv-test-suite/rv32i_m/M/src/remu-01.S b/riscv-test-suite/rv32i_m/M/src/remu-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",remu)
+RVTEST_CASE(0,"//check ISA:=regexp(.*32.*);check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",remu)
 
 RVTEST_SIGBASE(x1,signature_x1_1)