Merge pull request #447 from davidharrishmc/master

Fized Zfh fcvt RVTEST_CASE macros
riscv-non-isa · Mar 27, 2024 · 8a0cdce · 8a0cdce
2 parents 7553caa + 1f4ea0d
commit 8a0cdce
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Showing 17 changed files with 20 additions and 16 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.8.12] - 2024-03-26
+Corrected missing RV64 strings in RVTEST_CASE macros for Zfh fcvt.h.l and similar tests
+
 ## [3.8.11] - 2024-03-26
 - Added test suites for Zfh extensions.
 - Introduced half word and half width in Nan boxing functionality to accomdate Zfh extensions.

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b1-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b1-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b1)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b1)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b22-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b22-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b22)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b22)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b23-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b23-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b23)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b23)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b24-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b24-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b24)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b24)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b27-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b27-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b27)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b27)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b28-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b28-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b28)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b28)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b29-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b29-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b29)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b29)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b1)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b1)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b22)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b22)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b23)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b23)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b24)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b24)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b27)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b27)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b28)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b28)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b29)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b29)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)