diff --git a/CHANGELOG.md b/CHANGELOG.md
index 429725909..7dac1e836 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # CHANGELOG
 
+## [3.8.15] - 2024-04-20
+Corrected missing 32 string in RVTEST_CASE macros for Zcb rv32i_m/C/clh-01.S
+	
 ## [3.8.14] - 2024-04-16
 Add missing `Zfh` ISA in RVTEST_CASE for `Zfh` fdiv related tests
 
diff --git a/riscv-test-suite/rv32i_m/C/src/clh-01.S b/riscv-test-suite/rv32i_m/C/src/clh-01.S
index eaeb99ad8..cd534a2da 100644
--- a/riscv-test-suite/rv32i_m/C/src/clh-01.S
+++ b/riscv-test-suite/rv32i_m/C/src/clh-01.S
@@ -30,7 +30,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh)
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*I.*Zca.*Zcb.*);def TEST_CASE_1=True;",clh)
 
 RVTEST_SIGBASE(x1,signature_x1_1)