Blitter control register 0 (lower 8 bits) This is to speed up software - the upper bits are often the same.
These two control registers are used together to control blitter operations. There are 2 basic modes, are and line, which are selected by bit 0 of BLTCON1, as show below.
| AREA MODE | LINE MODE |
|---|---|
| Bit | BLTCON0 |
| 15 | ASH3 |
| 14 | ASH2 |
| 13 | ASH1 |
| 12 | ASA0 |
| 11 | USEA |
| 10 | USEB |
| 09 | USEC |
| 08 | USED |
| 07 | LF7 |
| 06 | LF6 |
| 05 | LF5 |
| 04 | LF4 |
| 03 | LF3 |
| 02 | LF2 |
| 01 | LF1 |
| 00 | LF0 |
| Function | Description |
|---|---|
| ASH3-0 | Shift value of A source |
| BSH3-0 | Shift value of B source and line texture |
| USEA | Mode control bit to use source A |
| USEB | Mode control bit to use source B |
| USEC | Mode control bit to use source C |
| USED | Mode control bit to use destination D |
| LF7-0 | Logic function minterm select lines |
| EFE | Exclusive fill enable |
| IFE | Inclusive fill enable |
| FCI | Fill carry input |
| DESC | Descending (dec address)control bit |
| LINE | Line mode control bit |
| SIGN | Line draw sign flag |
| OVF | Line/draw r/l word overflow flag |
| SUD | Line draw, Sometimes up or down (=AUD) |
| SUL | Line draw, Sometimes up or left |
| AUL | Line draw, Always up or left |
| SING | Line draw, Single bit per horiz line |
| DOFF | Disables the D output- for external ALUs The cycle occurs normally, but the data bus is tristate (hires chips only) |