From d192c13ede1c7b380cc7b343abad4f83f9661154 Mon Sep 17 00:00:00 2001 From: Wojciech Olech Date: Mon, 4 Sep 2023 09:28:54 +0200 Subject: [PATCH 1/3] PAC: Regenerated using new version of `svd2rust` --- arch/cortex-m/samv71q21-pac/src/acc.rs | 27 +- arch/cortex-m/samv71q21-pac/src/acc/acr.rs | 70 +- arch/cortex-m/samv71q21-pac/src/acc/cr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/acc/idr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/acc/ier.rs | 32 +- arch/cortex-m/samv71q21-pac/src/acc/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/acc/isr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/acc/mr.rs | 223 ++-- arch/cortex-m/samv71q21-pac/src/acc/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/acc/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/aes.rs | 48 +- .../cortex-m/samv71q21-pac/src/aes/aadlenr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/aes/clenr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/aes/cr.rs | 40 +- arch/cortex-m/samv71q21-pac/src/aes/ctrr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/aes/gcmhr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/aes/ghashr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/aes/idatar.rs | 32 +- arch/cortex-m/samv71q21-pac/src/aes/idr.rs | 40 +- arch/cortex-m/samv71q21-pac/src/aes/ier.rs | 40 +- arch/cortex-m/samv71q21-pac/src/aes/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/aes/isr.rs | 35 +- arch/cortex-m/samv71q21-pac/src/aes/ivr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/aes/keywr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/aes/mr.rs | 204 ++- arch/cortex-m/samv71q21-pac/src/aes/odatar.rs | 23 +- arch/cortex-m/samv71q21-pac/src/aes/tagr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/afec0.rs | 87 +- arch/cortex-m/samv71q21-pac/src/afec0/acr.rs | 61 +- arch/cortex-m/samv71q21-pac/src/afec0/cdr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/afec0/cecr.rs | 97 +- arch/cortex-m/samv71q21-pac/src/afec0/cgr.rs | 97 +- arch/cortex-m/samv71q21-pac/src/afec0/chdr.rs | 76 +- arch/cortex-m/samv71q21-pac/src/afec0/cher.rs | 76 +- arch/cortex-m/samv71q21-pac/src/afec0/chsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/afec0/cocr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/afec0/cosr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/afec0/cr.rs | 36 +- .../cortex-m/samv71q21-pac/src/afec0/cselr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/afec0/cvr.rs | 57 +- arch/cortex-m/samv71q21-pac/src/afec0/cwr.rs | 57 +- .../cortex-m/samv71q21-pac/src/afec0/diffr.rs | 97 +- arch/cortex-m/samv71q21-pac/src/afec0/emr.rs | 151 +-- arch/cortex-m/samv71q21-pac/src/afec0/idr.rs | 92 +- arch/cortex-m/samv71q21-pac/src/afec0/ier.rs | 92 +- arch/cortex-m/samv71q21-pac/src/afec0/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/afec0/isr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/afec0/lcdr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/afec0/mr.rs | 262 ++-- arch/cortex-m/samv71q21-pac/src/afec0/over.rs | 23 +- .../cortex-m/samv71q21-pac/src/afec0/seq1r.rs | 81 +- .../cortex-m/samv71q21-pac/src/afec0/seq2r.rs | 65 +- arch/cortex-m/samv71q21-pac/src/afec0/shmr.rs | 97 +- .../samv71q21-pac/src/afec0/tempcwr.rs | 57 +- .../samv71q21-pac/src/afec0/tempmr.rs | 81 +- arch/cortex-m/samv71q21-pac/src/afec0/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/afec0/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/chipid.rs | 6 +- .../cortex-m/samv71q21-pac/src/chipid/cidr.rs | 131 +- .../cortex-m/samv71q21-pac/src/chipid/exid.rs | 23 +- arch/cortex-m/samv71q21-pac/src/core_debug.rs | 12 +- .../samv71q21-pac/src/core_debug/dcrdr.rs | 49 +- .../samv71q21-pac/src/core_debug/dcrsr.rs | 36 +- .../samv71q21-pac/src/core_debug/demcr.rs | 101 +- .../samv71q21-pac/src/core_debug/dhcsr.rs | 93 +- arch/cortex-m/samv71q21-pac/src/dacc.rs | 42 +- arch/cortex-m/samv71q21-pac/src/dacc/acr.rs | 57 +- arch/cortex-m/samv71q21-pac/src/dacc/cdr.rs | 36 +- arch/cortex-m/samv71q21-pac/src/dacc/chdr.rs | 36 +- arch/cortex-m/samv71q21-pac/src/dacc/cher.rs | 36 +- arch/cortex-m/samv71q21-pac/src/dacc/chsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/dacc/cr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/dacc/idr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/dacc/ier.rs | 44 +- arch/cortex-m/samv71q21-pac/src/dacc/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/dacc/isr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/dacc/mr.rs | 125 +- arch/cortex-m/samv71q21-pac/src/dacc/trigr.rs | 235 ++-- arch/cortex-m/samv71q21-pac/src/dacc/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/dacc/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/efc.rs | 15 +- .../samv71q21-pac/src/efc/eefc_fcr.rs | 96 +- .../samv71q21-pac/src/efc/eefc_fmr.rs | 65 +- .../samv71q21-pac/src/efc/eefc_frr.rs | 23 +- .../samv71q21-pac/src/efc/eefc_fsr.rs | 23 +- .../samv71q21-pac/src/efc/eefc_wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/etm.rs | 120 +- .../samv71q21-pac/src/etm/authstatus.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/ccer.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/ccr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/cidr0.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/cidr1.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/cidr2.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/cidr3.rs | 23 +- .../samv71q21-pac/src/etm/claimclr.rs | 49 +- .../samv71q21-pac/src/etm/claimset.rs | 49 +- .../samv71q21-pac/src/etm/cntrldvr1.rs | 49 +- arch/cortex-m/samv71q21-pac/src/etm/cr.rs | 93 +- .../cortex-m/samv71q21-pac/src/etm/devtype.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/fflr.rs | 49 +- arch/cortex-m/samv71q21-pac/src/etm/idr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/idr2.rs | 23 +- .../samv71q21-pac/src/etm/itatbctr0.rs | 28 +- .../samv71q21-pac/src/etm/itatbctr2.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/itctrl.rs | 53 +- .../samv71q21-pac/src/etm/itmiscin.rs | 23 +- .../samv71q21-pac/src/etm/ittrigout.rs | 28 +- arch/cortex-m/samv71q21-pac/src/etm/lar.rs | 28 +- arch/cortex-m/samv71q21-pac/src/etm/lsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pdsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr0.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr1.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr2.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr3.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr4.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr5.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr6.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/pidr7.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/scr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/sr.rs | 49 +- arch/cortex-m/samv71q21-pac/src/etm/syncfr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/etm/tecr1.rs | 49 +- arch/cortex-m/samv71q21-pac/src/etm/teevr.rs | 49 +- .../samv71q21-pac/src/etm/tesseicr.rs | 49 +- .../samv71q21-pac/src/etm/traceidr.rs | 49 +- .../cortex-m/samv71q21-pac/src/etm/trigger.rs | 49 +- arch/cortex-m/samv71q21-pac/src/etm/tsevt.rs | 49 +- arch/cortex-m/samv71q21-pac/src/generic.rs | 181 +-- .../cortex-m/samv71q21-pac/src/generic/raw.rs | 89 ++ arch/cortex-m/samv71q21-pac/src/gmac.rs | 342 +++-- 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+- arch/cortex-m/samv71q21-pac/src/i2sc0/thr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/icm.rs | 32 +- arch/cortex-m/samv71q21-pac/src/icm/cfg.rs | 99 +- arch/cortex-m/samv71q21-pac/src/icm/ctrl.rs | 52 +- arch/cortex-m/samv71q21-pac/src/icm/dscr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/icm/hash.rs | 53 +- arch/cortex-m/samv71q21-pac/src/icm/idr.rs | 56 +- arch/cortex-m/samv71q21-pac/src/icm/ier.rs | 56 +- arch/cortex-m/samv71q21-pac/src/icm/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/icm/isr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/icm/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/icm/uasr.rs | 33 +- arch/cortex-m/samv71q21-pac/src/icm/uihval.rs | 32 +- arch/cortex-m/samv71q21-pac/src/isi.rs | 75 +- arch/cortex-m/samv71q21-pac/src/isi/cfg1.rs | 115 +- arch/cortex-m/samv71q21-pac/src/isi/cfg2.rs | 130 +- arch/cortex-m/samv71q21-pac/src/isi/cr.rs | 44 +- .../samv71q21-pac/src/isi/dma_c_addr.rs | 53 +- .../samv71q21-pac/src/isi/dma_c_ctrl.rs | 65 +- .../samv71q21-pac/src/isi/dma_c_dscr.rs | 53 +- .../samv71q21-pac/src/isi/dma_chdr.rs | 36 +- .../samv71q21-pac/src/isi/dma_cher.rs | 36 +- .../samv71q21-pac/src/isi/dma_chsr.rs | 23 +- .../samv71q21-pac/src/isi/dma_p_addr.rs | 53 +- .../samv71q21-pac/src/isi/dma_p_ctrl.rs | 65 +- .../samv71q21-pac/src/isi/dma_p_dscr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/isi/idr.rs | 64 +- arch/cortex-m/samv71q21-pac/src/isi/ier.rs | 64 +- arch/cortex-m/samv71q21-pac/src/isi/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/isi/pdecf.rs | 53 +- arch/cortex-m/samv71q21-pac/src/isi/psize.rs | 57 +- .../samv71q21-pac/src/isi/r2y_set0.rs | 65 +- .../samv71q21-pac/src/isi/r2y_set1.rs | 65 +- .../samv71q21-pac/src/isi/r2y_set2.rs | 65 +- arch/cortex-m/samv71q21-pac/src/isi/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/isi/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/isi/wpsr.rs | 23 +- .../samv71q21-pac/src/isi/y2r_set0.rs | 65 +- .../samv71q21-pac/src/isi/y2r_set1.rs | 65 +- arch/cortex-m/samv71q21-pac/src/lib.rs | 1102 ++++++++++++++++- arch/cortex-m/samv71q21-pac/src/lockbit.rs | 12 +- .../samv71q21-pac/src/lockbit/word0.rs | 177 ++- .../samv71q21-pac/src/lockbit/word1.rs | 177 ++- .../samv71q21-pac/src/lockbit/word2.rs | 177 ++- .../samv71q21-pac/src/lockbit/word3.rs | 177 ++- arch/cortex-m/samv71q21-pac/src/matrix.rs | 30 +- .../samv71q21-pac/src/matrix/ccfg_can0.rs | 53 +- .../samv71q21-pac/src/matrix/ccfg_dynckg.rs | 61 +- .../samv71q21-pac/src/matrix/ccfg_pccr.rs | 61 +- .../samv71q21-pac/src/matrix/ccfg_smcnfcs.rs | 65 +- .../samv71q21-pac/src/matrix/ccfg_sysio.rs | 73 +- .../samv71q21-pac/src/matrix/matrix_pr.rs | 6 +- .../src/matrix/matrix_pr/pras.rs | 81 +- .../src/matrix/matrix_pr/prbs.rs | 69 +- .../cortex-m/samv71q21-pac/src/matrix/mcfg.rs | 91 +- .../cortex-m/samv71q21-pac/src/matrix/mrcr.rs | 101 +- .../cortex-m/samv71q21-pac/src/matrix/scfg.rs | 81 +- .../cortex-m/samv71q21-pac/src/matrix/wpmr.rs | 67 +- .../cortex-m/samv71q21-pac/src/matrix/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/mcan0.rs | 141 ++- arch/cortex-m/samv71q21-pac/src/mcan0/cccr.rs | 222 ++-- arch/cortex-m/samv71q21-pac/src/mcan0/crel.rs | 23 +- arch/cortex-m/samv71q21-pac/src/mcan0/cust.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mcan0/dbtp.rs | 82 +- arch/cortex-m/samv71q21-pac/src/mcan0/ecr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/mcan0/endn.rs | 23 +- arch/cortex-m/samv71q21-pac/src/mcan0/gfc.rs | 119 +- arch/cortex-m/samv71q21-pac/src/mcan0/hpms.rs | 31 +- arch/cortex-m/samv71q21-pac/src/mcan0/ie.rs | 161 +-- arch/cortex-m/samv71q21-pac/src/mcan0/ile.rs | 57 +- arch/cortex-m/samv71q21-pac/src/mcan0/ils.rs | 161 +-- arch/cortex-m/samv71q21-pac/src/mcan0/ir.rs | 161 +-- arch/cortex-m/samv71q21-pac/src/mcan0/nbtp.rs | 65 +- .../cortex-m/samv71q21-pac/src/mcan0/ndat1.rs | 177 ++- .../cortex-m/samv71q21-pac/src/mcan0/ndat2.rs | 177 ++- arch/cortex-m/samv71q21-pac/src/mcan0/psr.rs | 47 +- arch/cortex-m/samv71q21-pac/src/mcan0/rwd.rs | 57 +- arch/cortex-m/samv71q21-pac/src/mcan0/rxbc.rs | 53 +- .../cortex-m/samv71q21-pac/src/mcan0/rxesc.rs | 175 ++- .../cortex-m/samv71q21-pac/src/mcan0/rxf0a.rs | 53 +- .../cortex-m/samv71q21-pac/src/mcan0/rxf0c.rs | 65 +- .../cortex-m/samv71q21-pac/src/mcan0/rxf0s.rs | 23 +- .../cortex-m/samv71q21-pac/src/mcan0/rxf1a.rs | 53 +- .../cortex-m/samv71q21-pac/src/mcan0/rxf1c.rs | 65 +- .../cortex-m/samv71q21-pac/src/mcan0/rxf1s.rs | 31 +- .../cortex-m/samv71q21-pac/src/mcan0/sidfc.rs | 57 +- arch/cortex-m/samv71q21-pac/src/mcan0/tdcr.rs | 57 +- arch/cortex-m/samv71q21-pac/src/mcan0/test.rs | 96 +- arch/cortex-m/samv71q21-pac/src/mcan0/tocc.rs | 96 +- arch/cortex-m/samv71q21-pac/src/mcan0/tocv.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mcan0/tscc.rs | 75 +- arch/cortex-m/samv71q21-pac/src/mcan0/tscv.rs | 53 +- .../cortex-m/samv71q21-pac/src/mcan0/txbar.rs | 177 ++- arch/cortex-m/samv71q21-pac/src/mcan0/txbc.rs | 65 +- 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arch/cortex-m/samv71q21-pac/src/mlb/hcmr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mlb/hctl.rs | 61 +- arch/cortex-m/samv71q21-pac/src/mlb/madr.rs | 74 +- arch/cortex-m/samv71q21-pac/src/mlb/mctl.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mlb/mdat.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mlb/mdwe.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mlb/mien.rs | 109 +- arch/cortex-m/samv71q21-pac/src/mlb/mlbc0.rs | 129 +- arch/cortex-m/samv71q21-pac/src/mlb/mlbc1.rs | 61 +- arch/cortex-m/samv71q21-pac/src/mlb/ms0.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mlb/ms1.rs | 53 +- arch/cortex-m/samv71q21-pac/src/mlb/msd.rs | 23 +- arch/cortex-m/samv71q21-pac/src/mlb/mss.rs | 73 +- arch/cortex-m/samv71q21-pac/src/pioa.rs | 162 ++- .../cortex-m/samv71q21-pac/src/pioa/abcdsr.rs | 177 ++- arch/cortex-m/samv71q21-pac/src/pioa/aimdr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/aimer.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/aimmr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/codr.rs | 156 +-- .../cortex-m/samv71q21-pac/src/pioa/driver.rs | 593 +++++---- arch/cortex-m/samv71q21-pac/src/pioa/elsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/esr.rs | 156 +-- .../cortex-m/samv71q21-pac/src/pioa/fellsr.rs | 156 +-- .../cortex-m/samv71q21-pac/src/pioa/frlhsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/idr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/ier.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/ifdr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/ifer.rs | 156 +-- .../cortex-m/samv71q21-pac/src/pioa/ifscdr.rs | 156 +-- .../cortex-m/samv71q21-pac/src/pioa/ifscer.rs | 156 +-- .../cortex-m/samv71q21-pac/src/pioa/ifscsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/ifsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/isr.rs | 23 +- .../cortex-m/samv71q21-pac/src/pioa/locksr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/lsr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/mddr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/mder.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/mdsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/odr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/odsr.rs | 177 ++- arch/cortex-m/samv71q21-pac/src/pioa/oer.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/osr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/owdr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/ower.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/owsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/pcidr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/pioa/pcier.rs | 44 +- arch/cortex-m/samv71q21-pac/src/pioa/pcimr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/pcisr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/pcmr.rs | 87 +- arch/cortex-m/samv71q21-pac/src/pioa/pcrhr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/pdr.rs | 156 +-- arch/cortex-m/samv71q21-pac/src/pioa/pdsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pioa/per.rs | 156 +-- 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arch/cortex-m/samv71q21-pac/src/pmc/fsmr.rs | 155 +-- arch/cortex-m/samv71q21-pac/src/pmc/fspr.rs | 113 +- arch/cortex-m/samv71q21-pac/src/pmc/idr.rs | 92 +- arch/cortex-m/samv71q21-pac/src/pmc/ier.rs | 92 +- arch/cortex-m/samv71q21-pac/src/pmc/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pmc/mckr.rs | 147 +-- arch/cortex-m/samv71q21-pac/src/pmc/ocr.rs | 73 +- arch/cortex-m/samv71q21-pac/src/pmc/pcdr0.rs | 128 +- arch/cortex-m/samv71q21-pac/src/pmc/pcdr1.rs | 128 +- arch/cortex-m/samv71q21-pac/src/pmc/pcer0.rs | 128 +- arch/cortex-m/samv71q21-pac/src/pmc/pcer1.rs | 128 +- arch/cortex-m/samv71q21-pac/src/pmc/pck.rs | 83 +- arch/cortex-m/samv71q21-pac/src/pmc/pcr.rs | 99 +- arch/cortex-m/samv71q21-pac/src/pmc/pcsr0.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pmc/pcsr1.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pmc/pmmr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/pmc/scdr.rs | 64 +- arch/cortex-m/samv71q21-pac/src/pmc/scer.rs | 64 +- arch/cortex-m/samv71q21-pac/src/pmc/scsr.rs | 23 +- .../samv71q21-pac/src/pmc/slpwk_aipr.rs | 23 +- .../samv71q21-pac/src/pmc/slpwk_asr0.rs | 23 +- .../samv71q21-pac/src/pmc/slpwk_asr1.rs | 23 +- .../samv71q21-pac/src/pmc/slpwk_dr0.rs | 128 +- .../samv71q21-pac/src/pmc/slpwk_dr1.rs | 128 +- .../samv71q21-pac/src/pmc/slpwk_er0.rs | 128 +- .../samv71q21-pac/src/pmc/slpwk_er1.rs | 128 +- .../samv71q21-pac/src/pmc/slpwk_sr0.rs | 23 +- .../samv71q21-pac/src/pmc/slpwk_sr1.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pmc/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pmc/usb.rs | 57 +- arch/cortex-m/samv71q21-pac/src/pmc/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/pmc/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0.rs | 129 +- arch/cortex-m/samv71q21-pac/src/pwm0/clk.rs | 193 ++- .../cortex-m/samv71q21-pac/src/pwm0/cmupd0.rs | 36 +- .../cortex-m/samv71q21-pac/src/pwm0/cmupd1.rs | 36 +- .../cortex-m/samv71q21-pac/src/pwm0/cmupd2.rs | 36 +- .../cortex-m/samv71q21-pac/src/pwm0/cmupd3.rs | 36 +- arch/cortex-m/samv71q21-pac/src/pwm0/dis.rs | 44 +- arch/cortex-m/samv71q21-pac/src/pwm0/dmar.rs | 32 +- arch/cortex-m/samv71q21-pac/src/pwm0/elmr.rs | 81 +- arch/cortex-m/samv71q21-pac/src/pwm0/ena.rs | 44 +- arch/cortex-m/samv71q21-pac/src/pwm0/etrg1.rs | 108 +- arch/cortex-m/samv71q21-pac/src/pwm0/etrg2.rs | 108 +- arch/cortex-m/samv71q21-pac/src/pwm0/fcr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/pwm0/fmr.rs | 61 +- arch/cortex-m/samv71q21-pac/src/pwm0/fpe.rs | 65 +- arch/cortex-m/samv71q21-pac/src/pwm0/fpv1.rs | 81 +- arch/cortex-m/samv71q21-pac/src/pwm0/fpv2.rs | 81 +- arch/cortex-m/samv71q21-pac/src/pwm0/fsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0/idr1.rs | 60 +- arch/cortex-m/samv71q21-pac/src/pwm0/idr2.rs | 100 +- arch/cortex-m/samv71q21-pac/src/pwm0/ier1.rs | 60 +- arch/cortex-m/samv71q21-pac/src/pwm0/ier2.rs | 100 +- arch/cortex-m/samv71q21-pac/src/pwm0/imr1.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0/imr2.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0/isr1.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0/isr2.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0/lebr1.rs | 69 +- arch/cortex-m/samv71q21-pac/src/pwm0/lebr2.rs | 69 +- arch/cortex-m/samv71q21-pac/src/pwm0/oov.rs | 81 +- arch/cortex-m/samv71q21-pac/src/pwm0/os.rs | 81 +- arch/cortex-m/samv71q21-pac/src/pwm0/osc.rs | 60 +- .../cortex-m/samv71q21-pac/src/pwm0/oscupd.rs | 60 +- arch/cortex-m/samv71q21-pac/src/pwm0/oss.rs | 60 +- .../cortex-m/samv71q21-pac/src/pwm0/ossupd.rs | 60 +- .../samv71q21-pac/src/pwm0/pwm_ch_num.rs | 24 +- .../samv71q21-pac/src/pwm0/pwm_ch_num/ccnt.rs | 23 +- .../samv71q21-pac/src/pwm0/pwm_ch_num/cdty.rs | 53 +- .../src/pwm0/pwm_ch_num/cdtyupd.rs | 32 +- .../samv71q21-pac/src/pwm0/pwm_ch_num/cmr.rs | 203 ++- .../samv71q21-pac/src/pwm0/pwm_ch_num/cprd.rs | 53 +- .../src/pwm0/pwm_ch_num/cprdupd.rs | 32 +- .../samv71q21-pac/src/pwm0/pwm_ch_num/dt.rs | 57 +- .../src/pwm0/pwm_ch_num/dtupd.rs | 36 +- .../samv71q21-pac/src/pwm0/pwm_cmp.rs | 12 +- .../samv71q21-pac/src/pwm0/pwm_cmp/cmpm.rs | 73 +- .../samv71q21-pac/src/pwm0/pwm_cmp/cmpmupd.rs | 44 +- .../samv71q21-pac/src/pwm0/pwm_cmp/cmpv.rs | 70 +- .../samv71q21-pac/src/pwm0/pwm_cmp/cmpvupd.rs | 36 +- arch/cortex-m/samv71q21-pac/src/pwm0/scm.rs | 95 +- arch/cortex-m/samv71q21-pac/src/pwm0/scuc.rs | 53 +- arch/cortex-m/samv71q21-pac/src/pwm0/scup.rs | 57 +- .../samv71q21-pac/src/pwm0/scupupd.rs | 32 +- arch/cortex-m/samv71q21-pac/src/pwm0/smmr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/pwm0/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/pwm0/sspr.rs | 57 +- arch/cortex-m/samv71q21-pac/src/pwm0/sspup.rs | 32 +- arch/cortex-m/samv71q21-pac/src/pwm0/wpcr.rs | 80 +- arch/cortex-m/samv71q21-pac/src/pwm0/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/qspi.rs | 48 +- arch/cortex-m/samv71q21-pac/src/qspi/cr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/qspi/iar.rs | 53 +- arch/cortex-m/samv71q21-pac/src/qspi/icr.rs | 57 +- arch/cortex-m/samv71q21-pac/src/qspi/idr.rs | 56 +- arch/cortex-m/samv71q21-pac/src/qspi/ier.rs | 56 +- arch/cortex-m/samv71q21-pac/src/qspi/ifr.rs | 193 ++- arch/cortex-m/samv71q21-pac/src/qspi/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/qspi/mr.rs | 148 +-- arch/cortex-m/samv71q21-pac/src/qspi/rdr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/qspi/scr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/qspi/skr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/qspi/smr.rs | 70 +- arch/cortex-m/samv71q21-pac/src/qspi/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/qspi/tdr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/qspi/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/qspi/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/rstc.rs | 9 +- arch/cortex-m/samv71q21-pac/src/rstc/cr.rs | 48 +- arch/cortex-m/samv71q21-pac/src/rstc/mr.rs | 75 +- arch/cortex-m/samv71q21-pac/src/rstc/sr.rs | 33 +- arch/cortex-m/samv71q21-pac/src/rswdt.rs | 9 +- arch/cortex-m/samv71q21-pac/src/rswdt/cr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/rswdt/mr.rs | 77 +- arch/cortex-m/samv71q21-pac/src/rswdt/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/rtc.rs | 36 +- arch/cortex-m/samv71q21-pac/src/rtc/calalr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/rtc/calr.rs | 69 +- arch/cortex-m/samv71q21-pac/src/rtc/cr.rs | 105 +- arch/cortex-m/samv71q21-pac/src/rtc/idr.rs | 52 +- arch/cortex-m/samv71q21-pac/src/rtc/ier.rs | 52 +- arch/cortex-m/samv71q21-pac/src/rtc/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/rtc/mr.rs | 221 ++-- arch/cortex-m/samv71q21-pac/src/rtc/sccr.rs | 52 +- arch/cortex-m/samv71q21-pac/src/rtc/sr.rs | 47 +- arch/cortex-m/samv71q21-pac/src/rtc/timalr.rs | 77 +- arch/cortex-m/samv71q21-pac/src/rtc/timr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/rtc/ver.rs | 23 +- arch/cortex-m/samv71q21-pac/src/rtt.rs | 12 +- arch/cortex-m/samv71q21-pac/src/rtt/ar.rs | 53 +- arch/cortex-m/samv71q21-pac/src/rtt/mr.rs | 73 +- arch/cortex-m/samv71q21-pac/src/rtt/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/rtt/vr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/scn_scb.rs | 6 +- .../samv71q21-pac/src/scn_scb/actlr.rs | 97 +- .../samv71q21-pac/src/scn_scb/ictr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/smc.rs | 15 +- arch/cortex-m/samv71q21-pac/src/smc/key1.rs | 32 +- arch/cortex-m/samv71q21-pac/src/smc/key2.rs | 32 +- arch/cortex-m/samv71q21-pac/src/smc/ocms.rs | 69 +- .../samv71q21-pac/src/smc/smc_cs_number.rs | 12 +- .../src/smc/smc_cs_number/cycle.rs | 57 +- .../src/smc/smc_cs_number/mode.rs | 151 +-- .../src/smc/smc_cs_number/pulse.rs | 65 +- .../src/smc/smc_cs_number/setup.rs | 65 +- arch/cortex-m/samv71q21-pac/src/smc/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/smc/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/spi0.rs | 33 +- arch/cortex-m/samv71q21-pac/src/spi0/cr.rs | 48 +- arch/cortex-m/samv71q21-pac/src/spi0/csr.rs | 149 +-- arch/cortex-m/samv71q21-pac/src/spi0/idr.rs | 56 +- arch/cortex-m/samv71q21-pac/src/spi0/ier.rs | 56 +- arch/cortex-m/samv71q21-pac/src/spi0/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/spi0/mr.rs | 116 +- arch/cortex-m/samv71q21-pac/src/spi0/rdr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/spi0/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/spi0/tdr.rs | 54 +- arch/cortex-m/samv71q21-pac/src/spi0/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/spi0/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/ssc.rs | 54 +- arch/cortex-m/samv71q21-pac/src/ssc/cmr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/ssc/cr.rs | 48 +- arch/cortex-m/samv71q21-pac/src/ssc/idr.rs | 60 +- arch/cortex-m/samv71q21-pac/src/ssc/ier.rs | 60 +- arch/cortex-m/samv71q21-pac/src/ssc/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/ssc/rc0r.rs | 53 +- arch/cortex-m/samv71q21-pac/src/ssc/rc1r.rs | 53 +- arch/cortex-m/samv71q21-pac/src/ssc/rcmr.rs | 177 ++- arch/cortex-m/samv71q21-pac/src/ssc/rfmr.rs | 124 +- arch/cortex-m/samv71q21-pac/src/ssc/rhr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/ssc/rshr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/ssc/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/ssc/tcmr.rs | 169 ++- arch/cortex-m/samv71q21-pac/src/ssc/tfmr.rs | 128 +- arch/cortex-m/samv71q21-pac/src/ssc/thr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/ssc/tshr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/ssc/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/ssc/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/supc.rs | 21 +- arch/cortex-m/samv71q21-pac/src/supc/cr.rs | 66 +- arch/cortex-m/samv71q21-pac/src/supc/mr.rs | 135 +- arch/cortex-m/samv71q21-pac/src/supc/smmr.rs | 117 +- arch/cortex-m/samv71q21-pac/src/supc/sr.rs | 115 +- .../samv71q21-pac/src/supc/sysc_wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/supc/wuir.rs | 525 ++++---- arch/cortex-m/samv71q21-pac/src/supc/wumr.rs | 227 ++-- arch/cortex-m/samv71q21-pac/src/sys_tick.rs | 12 +- .../samv71q21-pac/src/sys_tick/calib.rs | 31 +- .../samv71q21-pac/src/sys_tick/csr.rs | 104 +- .../samv71q21-pac/src/sys_tick/cvr.rs | 53 +- .../samv71q21-pac/src/sys_tick/rvr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/tc0.rs | 24 +- arch/cortex-m/samv71q21-pac/src/tc0/bcr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/tc0/bmr.rs | 167 ++- arch/cortex-m/samv71q21-pac/src/tc0/fmr.rs | 57 +- arch/cortex-m/samv71q21-pac/src/tc0/qidr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/tc0/qier.rs | 44 +- arch/cortex-m/samv71q21-pac/src/tc0/qimr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/tc0/qisr.rs | 23 +- .../samv71q21-pac/src/tc0/tc_channel.rs | 42 +- .../samv71q21-pac/src/tc0/tc_channel/ccr.rs | 40 +- .../src/tc0/tc_channel/cmr_capture_mode.rs | 255 ++-- .../src/tc0/tc_channel/cmr_waveform_mode.rs | 436 +++---- .../samv71q21-pac/src/tc0/tc_channel/cv.rs | 23 +- .../samv71q21-pac/src/tc0/tc_channel/emr.rs | 89 +- .../samv71q21-pac/src/tc0/tc_channel/idr.rs | 60 +- .../samv71q21-pac/src/tc0/tc_channel/ier.rs | 60 +- .../samv71q21-pac/src/tc0/tc_channel/imr.rs | 23 +- .../samv71q21-pac/src/tc0/tc_channel/ra.rs | 53 +- .../samv71q21-pac/src/tc0/tc_channel/rab.rs | 23 +- .../samv71q21-pac/src/tc0/tc_channel/rb.rs | 53 +- .../samv71q21-pac/src/tc0/tc_channel/rc.rs | 53 +- .../samv71q21-pac/src/tc0/tc_channel/smmr.rs | 57 +- .../samv71q21-pac/src/tc0/tc_channel/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/tc0/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/trng.rs | 18 +- arch/cortex-m/samv71q21-pac/src/trng/cr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/trng/idr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/trng/ier.rs | 32 +- arch/cortex-m/samv71q21-pac/src/trng/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/trng/isr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/trng/odata.rs | 23 +- arch/cortex-m/samv71q21-pac/src/twihs0.rs | 48 +- arch/cortex-m/samv71q21-pac/src/twihs0/cr.rs | 116 +- .../cortex-m/samv71q21-pac/src/twihs0/cwgr.rs | 65 +- .../samv71q21-pac/src/twihs0/filtr.rs | 65 +- .../cortex-m/samv71q21-pac/src/twihs0/iadr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/twihs0/idr.rs | 92 +- arch/cortex-m/samv71q21-pac/src/twihs0/ier.rs | 92 +- arch/cortex-m/samv71q21-pac/src/twihs0/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/twihs0/mmr.rs | 83 +- arch/cortex-m/samv71q21-pac/src/twihs0/rhr.rs | 23 +- .../samv71q21-pac/src/twihs0/smbtr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/twihs0/smr.rs | 89 +- arch/cortex-m/samv71q21-pac/src/twihs0/sr.rs | 23 +- .../cortex-m/samv71q21-pac/src/twihs0/swmr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/twihs0/thr.rs | 32 +- .../cortex-m/samv71q21-pac/src/twihs0/wpmr.rs | 67 +- .../cortex-m/samv71q21-pac/src/twihs0/wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/uart0.rs | 33 +- arch/cortex-m/samv71q21-pac/src/uart0/brgr.rs | 53 +- arch/cortex-m/samv71q21-pac/src/uart0/cmpr.rs | 78 +- arch/cortex-m/samv71q21-pac/src/uart0/cr.rs | 60 +- arch/cortex-m/samv71q21-pac/src/uart0/idr.rs | 56 +- arch/cortex-m/samv71q21-pac/src/uart0/ier.rs | 56 +- arch/cortex-m/samv71q21-pac/src/uart0/imr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/uart0/mr.rs | 139 +-- arch/cortex-m/samv71q21-pac/src/uart0/rhr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/uart0/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/uart0/thr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/uart0/wpmr.rs | 67 +- arch/cortex-m/samv71q21-pac/src/usart0.rs | 144 ++- .../samv71q21-pac/src/usart0/us_brgr.rs | 57 +- .../src/usart0/us_cr_lin_mode.rs | 64 +- .../src/usart0/us_cr_spi_mode.rs | 64 +- .../src/usart0/us_cr_usart_mode.rs | 100 +- .../src/usart0/us_csr_lin_mode.rs | 23 +- .../src/usart0/us_csr_lon_mode.rs | 23 +- .../src/usart0/us_csr_spi_mode.rs | 23 +- .../src/usart0/us_csr_usart_mode.rs | 23 +- .../src/usart0/us_fidi_lon_mode.rs | 53 +- .../src/usart0/us_fidi_usart_mode.rs | 54 +- .../samv71q21-pac/src/usart0/us_icdiff.rs | 53 +- .../src/usart0/us_idr_lin_mode.rs | 96 +- .../src/usart0/us_idr_lon_mode.rs | 76 +- .../src/usart0/us_idr_spi_mode.rs | 52 +- .../src/usart0/us_idr_usart_mode.rs | 88 +- .../samv71q21-pac/src/usart0/us_idtrx.rs | 53 +- .../samv71q21-pac/src/usart0/us_idttx.rs | 53 +- .../src/usart0/us_ier_lin_mode.rs | 96 +- .../src/usart0/us_ier_lon_mode.rs | 76 +- .../src/usart0/us_ier_spi_mode.rs | 52 +- .../src/usart0/us_ier_usart_mode.rs | 88 +- .../samv71q21-pac/src/usart0/us_if.rs | 53 +- .../src/usart0/us_imr_lin_mode.rs | 23 +- .../src/usart0/us_imr_lon_mode.rs | 23 +- .../src/usart0/us_imr_spi_mode.rs | 23 +- .../src/usart0/us_imr_usart_mode.rs | 23 +- .../samv71q21-pac/src/usart0/us_linbrr.rs | 23 +- .../samv71q21-pac/src/usart0/us_linir.rs | 53 +- .../samv71q21-pac/src/usart0/us_linmr.rs | 107 +- .../samv71q21-pac/src/usart0/us_lonb1rx.rs | 53 +- .../samv71q21-pac/src/usart0/us_lonb1tx.rs | 53 +- .../samv71q21-pac/src/usart0/us_lonbl.rs | 23 +- .../samv71q21-pac/src/usart0/us_londl.rs | 53 +- .../samv71q21-pac/src/usart0/us_lonl2hdr.rs | 61 +- .../samv71q21-pac/src/usart0/us_lonmr.rs | 77 +- .../samv71q21-pac/src/usart0/us_lonpr.rs | 53 +- .../samv71q21-pac/src/usart0/us_lonprio.rs | 57 +- .../samv71q21-pac/src/usart0/us_man.rs | 129 +- .../src/usart0/us_mr_spi_mode.rs | 178 ++- .../src/usart0/us_mr_usart_mode.rs | 302 +++-- .../samv71q21-pac/src/usart0/us_ner.rs | 23 +- .../samv71q21-pac/src/usart0/us_rhr.rs | 23 +- .../samv71q21-pac/src/usart0/us_rtor.rs | 53 +- .../samv71q21-pac/src/usart0/us_thr.rs | 36 +- .../src/usart0/us_ttgr_lon_mode.rs | 53 +- .../src/usart0/us_ttgr_usart_mode.rs | 53 +- .../samv71q21-pac/src/usart0/us_wpmr.rs | 67 +- .../samv71q21-pac/src/usart0/us_wpsr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/usbhs.rs | 234 ++-- arch/cortex-m/samv71q21-pac/src/usbhs/ctrl.rs | 86 +- .../samv71q21-pac/src/usbhs/devctrl.rs | 112 +- .../samv71q21-pac/src/usbhs/devept.rs | 129 +- .../samv71q21-pac/src/usbhs/deveptcfg.rs | 193 ++- .../src/usbhs/devepticr_blk_mode.rs | 60 +- .../src/usbhs/devepticr_ctrl_mode.rs | 60 +- .../src/usbhs/devepticr_intrpt_mode.rs | 60 +- .../src/usbhs/devepticr_iso_mode.rs | 60 +- .../src/usbhs/deveptidr_blk_mode.rs | 80 +- .../src/usbhs/deveptidr_ctrl_mode.rs | 80 +- .../src/usbhs/deveptidr_intrpt_mode.rs | 80 +- .../src/usbhs/deveptidr_iso_mode.rs | 80 +- .../src/usbhs/deveptier_blk_mode.rs | 88 +- .../src/usbhs/deveptier_ctrl_mode.rs | 88 +- .../src/usbhs/deveptier_intrpt_mode.rs | 88 +- .../src/usbhs/deveptier_iso_mode.rs | 92 +- .../src/usbhs/deveptifr_blk_mode.rs | 64 +- .../src/usbhs/deveptifr_ctrl_mode.rs | 64 +- .../src/usbhs/deveptifr_intrpt_mode.rs | 64 +- .../src/usbhs/deveptifr_iso_mode.rs | 64 +- .../src/usbhs/deveptimr_blk_mode.rs | 23 +- .../src/usbhs/deveptimr_ctrl_mode.rs | 23 +- .../src/usbhs/deveptimr_intrpt_mode.rs | 23 +- .../src/usbhs/deveptimr_iso_mode.rs | 23 +- .../src/usbhs/deveptisr_blk_mode.rs | 45 +- .../src/usbhs/deveptisr_ctrl_mode.rs | 45 +- .../src/usbhs/deveptisr_intrpt_mode.rs | 45 +- .../src/usbhs/deveptisr_iso_mode.rs | 45 +- .../samv71q21-pac/src/usbhs/devfnum.rs | 23 +- .../samv71q21-pac/src/usbhs/devicr.rs | 56 +- .../samv71q21-pac/src/usbhs/devidr.rs | 124 +- .../samv71q21-pac/src/usbhs/devier.rs | 124 +- .../samv71q21-pac/src/usbhs/devifr.rs | 84 +- .../samv71q21-pac/src/usbhs/devimr.rs | 23 +- .../samv71q21-pac/src/usbhs/devisr.rs | 23 +- .../samv71q21-pac/src/usbhs/hstaddr1.rs | 65 +- .../samv71q21-pac/src/usbhs/hstaddr2.rs | 65 +- .../samv71q21-pac/src/usbhs/hstaddr3.rs | 57 +- .../samv71q21-pac/src/usbhs/hstctrl.rs | 88 +- .../samv71q21-pac/src/usbhs/hstfnum.rs | 61 +- .../samv71q21-pac/src/usbhs/hsticr.rs | 56 +- .../samv71q21-pac/src/usbhs/hstidr.rs | 124 +- .../samv71q21-pac/src/usbhs/hstier.rs | 124 +- .../samv71q21-pac/src/usbhs/hstifr.rs | 84 +- .../samv71q21-pac/src/usbhs/hstimr.rs | 23 +- .../samv71q21-pac/src/usbhs/hstisr.rs | 23 +- .../samv71q21-pac/src/usbhs/hstpip.rs | 121 +- .../samv71q21-pac/src/usbhs/hstpipcfg.rs | 177 ++- .../src/usbhs/hstpipcfg_ctrl_bulk_mode.rs | 185 ++- .../samv71q21-pac/src/usbhs/hstpiperr.rs | 73 +- .../src/usbhs/hstpipicr_blk_mode.rs | 56 +- .../src/usbhs/hstpipicr_ctrl_mode.rs | 56 +- .../src/usbhs/hstpipicr_intrpt_mode.rs | 56 +- .../src/usbhs/hstpipicr_iso_mode.rs | 56 +- .../src/usbhs/hstpipidr_blk_mode.rs | 76 +- .../src/usbhs/hstpipidr_ctrl_mode.rs | 76 +- .../src/usbhs/hstpipidr_intrpt_mode.rs | 76 +- .../src/usbhs/hstpipidr_iso_mode.rs | 76 +- .../src/usbhs/hstpipier_blk_mode.rs | 76 +- .../src/usbhs/hstpipier_ctrl_mode.rs | 76 +- .../src/usbhs/hstpipier_intrpt_mode.rs | 76 +- .../src/usbhs/hstpipier_iso_mode.rs | 76 +- .../src/usbhs/hstpipifr_blk_mode.rs | 64 +- .../src/usbhs/hstpipifr_ctrl_mode.rs | 64 +- .../src/usbhs/hstpipifr_intrpt_mode.rs | 64 +- .../src/usbhs/hstpipifr_iso_mode.rs | 64 +- .../src/usbhs/hstpipimr_blk_mode.rs | 23 +- .../src/usbhs/hstpipimr_ctrl_mode.rs | 23 +- .../src/usbhs/hstpipimr_intrpt_mode.rs | 23 +- .../src/usbhs/hstpipimr_iso_mode.rs | 23 +- .../samv71q21-pac/src/usbhs/hstpipinrq.rs | 57 +- .../src/usbhs/hstpipisr_blk_mode.rs | 41 +- .../src/usbhs/hstpipisr_ctrl_mode.rs | 41 +- .../src/usbhs/hstpipisr_intrpt_mode.rs | 41 +- .../src/usbhs/hstpipisr_iso_mode.rs | 41 +- arch/cortex-m/samv71q21-pac/src/usbhs/scr.rs | 32 +- arch/cortex-m/samv71q21-pac/src/usbhs/sfr.rs | 36 +- arch/cortex-m/samv71q21-pac/src/usbhs/sr.rs | 29 +- .../samv71q21-pac/src/usbhs/usbhs_devdma.rs | 12 +- .../src/usbhs/usbhs_devdma/devdmaaddress.rs | 53 +- .../src/usbhs/usbhs_devdma/devdmacontrol.rs | 85 +- .../src/usbhs/usbhs_devdma/devdmanxtdsc.rs | 53 +- .../src/usbhs/usbhs_devdma/devdmastatus.rs | 73 +- .../samv71q21-pac/src/usbhs/usbhs_hstdma.rs | 12 +- .../src/usbhs/usbhs_hstdma/hstdmaaddress.rs | 53 +- .../src/usbhs/usbhs_hstdma/hstdmacontrol.rs | 85 +- .../src/usbhs/usbhs_hstdma/hstdmanxtdsc.rs | 53 +- .../src/usbhs/usbhs_hstdma/hstdmastatus.rs | 73 +- arch/cortex-m/samv71q21-pac/src/utmi.rs | 6 +- .../cortex-m/samv71q21-pac/src/utmi/cktrim.rs | 67 +- .../samv71q21-pac/src/utmi/ohciicr.rs | 65 +- arch/cortex-m/samv71q21-pac/src/wdt.rs | 9 +- arch/cortex-m/samv71q21-pac/src/wdt/cr.rs | 44 +- arch/cortex-m/samv71q21-pac/src/wdt/mr.rs | 77 +- arch/cortex-m/samv71q21-pac/src/wdt/sr.rs | 23 +- arch/cortex-m/samv71q21-pac/src/xdmac.rs | 51 +- arch/cortex-m/samv71q21-pac/src/xdmac/gcfg.rs | 69 +- arch/cortex-m/samv71q21-pac/src/xdmac/gd.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/ge.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/gid.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/gie.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/gim.rs | 23 +- arch/cortex-m/samv71q21-pac/src/xdmac/gis.rs | 23 +- arch/cortex-m/samv71q21-pac/src/xdmac/grs.rs | 145 +-- arch/cortex-m/samv71q21-pac/src/xdmac/grwr.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/grws.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/gs.rs | 23 +- arch/cortex-m/samv71q21-pac/src/xdmac/gswf.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/gswr.rs | 124 +- arch/cortex-m/samv71q21-pac/src/xdmac/gsws.rs | 23 +- .../cortex-m/samv71q21-pac/src/xdmac/gtype.rs | 23 +- arch/cortex-m/samv71q21-pac/src/xdmac/gwac.rs | 65 +- arch/cortex-m/samv71q21-pac/src/xdmac/gws.rs | 145 +-- .../samv71q21-pac/src/xdmac/xdmac_chid.rs | 42 +- .../samv71q21-pac/src/xdmac/xdmac_chid/cbc.rs | 53 +- .../samv71q21-pac/src/xdmac/xdmac_chid/cc.rs | 550 ++++---- .../samv71q21-pac/src/xdmac/xdmac_chid/cda.rs | 53 +- .../src/xdmac/xdmac_chid/cds_msp.rs | 57 +- .../src/xdmac/xdmac_chid/cdus.rs | 53 +- .../samv71q21-pac/src/xdmac/xdmac_chid/cid.rs | 56 +- .../samv71q21-pac/src/xdmac/xdmac_chid/cie.rs | 56 +- .../samv71q21-pac/src/xdmac/xdmac_chid/cim.rs | 23 +- .../samv71q21-pac/src/xdmac/xdmac_chid/cis.rs | 23 +- .../src/xdmac/xdmac_chid/cnda.rs | 57 +- .../src/xdmac/xdmac_chid/cndc.rs | 126 +- .../samv71q21-pac/src/xdmac/xdmac_chid/csa.rs | 53 +- .../src/xdmac/xdmac_chid/csus.rs | 53 +- .../src/xdmac/xdmac_chid/cubc.rs | 53 +- 899 files changed, 20523 insertions(+), 38434 deletions(-) create mode 100644 arch/cortex-m/samv71q21-pac/src/generic/raw.rs diff --git a/arch/cortex-m/samv71q21-pac/src/acc.rs b/arch/cortex-m/samv71q21-pac/src/acc.rs index 62fce42e..28898361 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc.rs @@ -23,39 +23,48 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "ACR (rw) register accessor: an alias for `Reg`"] +#[doc = "ACR (rw) register accessor: Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`acr`] +module"] pub type ACR = crate::Reg; #[doc = "Analog Control Register"] pub mod acr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/acc/acr.rs b/arch/cortex-m/samv71q21-pac/src/acc/acr.rs index a81d934f..75141deb 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/acr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/acr.rs @@ -1,39 +1,7 @@ #[doc = "Register `ACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ISEL` reader - Current Selection"] pub type ISEL_R = crate::BitReader; #[doc = "Current Selection\n\nValue on reset: 0"] @@ -59,35 +27,38 @@ impl ISEL_R { true => ISELSELECT_A::HISP, } } - #[doc = "Checks if the value of the field is `LOPW`"] + #[doc = "Low-power option."] #[inline(always)] pub fn is_lopw(&self) -> bool { *self == ISELSELECT_A::LOPW } - #[doc = "Checks if the value of the field is `HISP`"] + #[doc = "High-speed option."] #[inline(always)] pub fn is_hisp(&self) -> bool { *self == ISELSELECT_A::HISP } } #[doc = "Field `ISEL` writer - Current Selection"] -pub type ISEL_W<'a, const O: u8> = crate::BitWriter<'a, ACR_SPEC, O, ISELSELECT_A>; -impl<'a, const O: u8> ISEL_W<'a, O> { +pub type ISEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ISELSELECT_A>; +impl<'a, REG, const O: u8> ISEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Low-power option."] #[inline(always)] - pub fn lopw(self) -> &'a mut W { + pub fn lopw(self) -> &'a mut crate::W { self.variant(ISELSELECT_A::LOPW) } #[doc = "High-speed option."] #[inline(always)] - pub fn hisp(self) -> &'a mut W { + pub fn hisp(self) -> &'a mut crate::W { self.variant(ISELSELECT_A::HISP) } } #[doc = "Field `HYST` reader - Hysteresis Selection"] pub type HYST_R = crate::FieldReader; #[doc = "Field `HYST` writer - Hysteresis Selection"] -pub type HYST_W<'a, const O: u8> = crate::FieldWriter<'a, ACR_SPEC, 2, O>; +pub type HYST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bit 0 - Current Selection"] #[inline(always)] @@ -104,34 +75,31 @@ impl W { #[doc = "Bit 0 - Current Selection"] #[inline(always)] #[must_use] - pub fn isel(&mut self) -> ISEL_W<0> { + pub fn isel(&mut self) -> ISEL_W { ISEL_W::new(self) } #[doc = "Bits 1:2 - Hysteresis Selection"] #[inline(always)] #[must_use] - pub fn hyst(&mut self) -> HYST_W<1> { + pub fn hyst(&mut self) -> HYST_W { HYST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Analog Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acr](index.html) module"] +#[doc = "Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACR_SPEC; impl crate::RegisterSpec for ACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [acr::R](R) reader structure"] -impl crate::Readable for ACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [acr::W](W) writer structure"] +#[doc = "`read()` method returns [`acr::R`](R) reader structure"] +impl crate::Readable for ACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`acr::W`](W) writer structure"] impl crate::Writable for ACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/acc/cr.rs b/arch/cortex-m/samv71q21-pac/src/acc/cr.rs index 7bbc2331..c8f327a0 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/cr.rs @@ -1,48 +1,28 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<0> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/acc/idr.rs b/arch/cortex-m/samv71q21-pac/src/acc/idr.rs index 82527c17..6d72a60a 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/idr.rs @@ -1,48 +1,28 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CE` writer - Comparison Edge"] -pub type CE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Comparison Edge"] #[inline(always)] #[must_use] - pub fn ce(&mut self) -> CE_W<0> { + pub fn ce(&mut self) -> CE_W { CE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/acc/ier.rs b/arch/cortex-m/samv71q21-pac/src/acc/ier.rs index 9d93e18a..ce5fee33 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/ier.rs @@ -1,48 +1,28 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CE` writer - Comparison Edge"] -pub type CE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Comparison Edge"] #[inline(always)] #[must_use] - pub fn ce(&mut self) -> CE_W<0> { + pub fn ce(&mut self) -> CE_W { CE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/acc/imr.rs b/arch/cortex-m/samv71q21-pac/src/acc/imr.rs index 83f96a78..9691dcb5 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CE` reader - Comparison Edge"] pub type CE_R = crate::BitReader; impl R { @@ -22,15 +9,13 @@ impl R { CE_R::new((self.bits & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/acc/isr.rs b/arch/cortex-m/samv71q21-pac/src/acc/isr.rs index 49742484..2e6e40a2 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CE` reader - Comparison Edge (cleared on read)"] pub type CE_R = crate::BitReader; #[doc = "Field `SCO` reader - Synchronized Comparator Output"] @@ -36,15 +23,13 @@ impl R { MASK_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/acc/mr.rs b/arch/cortex-m/samv71q21-pac/src/acc/mr.rs index a51801f5..1443f564 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SELMINUS` reader - Selection for Minus Comparator Input"] pub type SELMINUS_R = crate::FieldReader; #[doc = "Selection for Minus Comparator Input\n\nValue on reset: 0"] @@ -82,88 +50,92 @@ impl SELMINUS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TS`"] + #[doc = "Select TS"] #[inline(always)] pub fn is_ts(&self) -> bool { *self == SELMINUSSELECT_A::TS } - #[doc = "Checks if the value of the field is `VREFP`"] + #[doc = "Select VREFP"] #[inline(always)] pub fn is_vrefp(&self) -> bool { *self == SELMINUSSELECT_A::VREFP } - #[doc = "Checks if the value of the field is `DAC0`"] + #[doc = "Select DAC0"] #[inline(always)] pub fn is_dac0(&self) -> bool { *self == SELMINUSSELECT_A::DAC0 } - #[doc = "Checks if the value of the field is `DAC1`"] + #[doc = "Select DAC1"] #[inline(always)] pub fn is_dac1(&self) -> bool { *self == SELMINUSSELECT_A::DAC1 } - #[doc = "Checks if the value of the field is `AFE0_AD0`"] + #[doc = "Select AFE0_AD0"] #[inline(always)] pub fn is_afe0_ad0(&self) -> bool { *self == SELMINUSSELECT_A::AFE0_AD0 } - #[doc = "Checks if the value of the field is `AFE0_AD1`"] + #[doc = "Select AFE0_AD1"] #[inline(always)] pub fn is_afe0_ad1(&self) -> bool { *self == SELMINUSSELECT_A::AFE0_AD1 } - #[doc = "Checks if the value of the field is `AFE0_AD2`"] + #[doc = "Select AFE0_AD2"] #[inline(always)] pub fn is_afe0_ad2(&self) -> bool { *self == SELMINUSSELECT_A::AFE0_AD2 } - #[doc = "Checks if the value of the field is `AFE0_AD3`"] + #[doc = "Select AFE0_AD3"] #[inline(always)] pub fn is_afe0_ad3(&self) -> bool { *self == SELMINUSSELECT_A::AFE0_AD3 } } #[doc = "Field `SELMINUS` writer - Selection for Minus Comparator Input"] -pub type SELMINUS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 3, O, SELMINUSSELECT_A>; -impl<'a, const O: u8> SELMINUS_W<'a, O> { +pub type SELMINUS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, SELMINUSSELECT_A>; +impl<'a, REG, const O: u8> SELMINUS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Select TS"] #[inline(always)] - pub fn ts(self) -> &'a mut W { + pub fn ts(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::TS) } #[doc = "Select VREFP"] #[inline(always)] - pub fn vrefp(self) -> &'a mut W { + pub fn vrefp(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::VREFP) } #[doc = "Select DAC0"] #[inline(always)] - pub fn dac0(self) -> &'a mut W { + pub fn dac0(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::DAC0) } #[doc = "Select DAC1"] #[inline(always)] - pub fn dac1(self) -> &'a mut W { + pub fn dac1(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::DAC1) } #[doc = "Select AFE0_AD0"] #[inline(always)] - pub fn afe0_ad0(self) -> &'a mut W { + pub fn afe0_ad0(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::AFE0_AD0) } #[doc = "Select AFE0_AD1"] #[inline(always)] - pub fn afe0_ad1(self) -> &'a mut W { + pub fn afe0_ad1(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::AFE0_AD1) } #[doc = "Select AFE0_AD2"] #[inline(always)] - pub fn afe0_ad2(self) -> &'a mut W { + pub fn afe0_ad2(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::AFE0_AD2) } #[doc = "Select AFE0_AD3"] #[inline(always)] - pub fn afe0_ad3(self) -> &'a mut W { + pub fn afe0_ad3(self) -> &'a mut crate::W { self.variant(SELMINUSSELECT_A::AFE0_AD3) } } @@ -215,88 +187,92 @@ impl SELPLUS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `AFE0_AD0`"] + #[doc = "Select AFE0_AD0"] #[inline(always)] pub fn is_afe0_ad0(&self) -> bool { *self == SELPLUSSELECT_A::AFE0_AD0 } - #[doc = "Checks if the value of the field is `AFE0_AD1`"] + #[doc = "Select AFE0_AD1"] #[inline(always)] pub fn is_afe0_ad1(&self) -> bool { *self == SELPLUSSELECT_A::AFE0_AD1 } - #[doc = "Checks if the value of the field is `AFE0_AD2`"] + #[doc = "Select AFE0_AD2"] #[inline(always)] pub fn is_afe0_ad2(&self) -> bool { *self == SELPLUSSELECT_A::AFE0_AD2 } - #[doc = "Checks if the value of the field is `AFE0_AD3`"] + #[doc = "Select AFE0_AD3"] #[inline(always)] pub fn is_afe0_ad3(&self) -> bool { *self == SELPLUSSELECT_A::AFE0_AD3 } - #[doc = "Checks if the value of the field is `AFE0_AD4`"] + #[doc = "Select AFE0_AD4"] #[inline(always)] pub fn is_afe0_ad4(&self) -> bool { *self == SELPLUSSELECT_A::AFE0_AD4 } - #[doc = "Checks if the value of the field is `AFE0_AD5`"] + #[doc = "Select AFE0_AD5"] #[inline(always)] pub fn is_afe0_ad5(&self) -> bool { *self == SELPLUSSELECT_A::AFE0_AD5 } - #[doc = "Checks if the value of the field is `AFE1_AD0`"] + #[doc = "Select AFE1_AD0"] #[inline(always)] pub fn is_afe1_ad0(&self) -> bool { *self == SELPLUSSELECT_A::AFE1_AD0 } - #[doc = "Checks if the value of the field is `AFE1_AD1`"] + #[doc = "Select AFE1_AD1"] #[inline(always)] pub fn is_afe1_ad1(&self) -> bool { *self == SELPLUSSELECT_A::AFE1_AD1 } } #[doc = "Field `SELPLUS` writer - Selection For Plus Comparator Input"] -pub type SELPLUS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 3, O, SELPLUSSELECT_A>; -impl<'a, const O: u8> SELPLUS_W<'a, O> { +pub type SELPLUS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, SELPLUSSELECT_A>; +impl<'a, REG, const O: u8> SELPLUS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Select AFE0_AD0"] #[inline(always)] - pub fn afe0_ad0(self) -> &'a mut W { + pub fn afe0_ad0(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE0_AD0) } #[doc = "Select AFE0_AD1"] #[inline(always)] - pub fn afe0_ad1(self) -> &'a mut W { + pub fn afe0_ad1(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE0_AD1) } #[doc = "Select AFE0_AD2"] #[inline(always)] - pub fn afe0_ad2(self) -> &'a mut W { + pub fn afe0_ad2(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE0_AD2) } #[doc = "Select AFE0_AD3"] #[inline(always)] - pub fn afe0_ad3(self) -> &'a mut W { + pub fn afe0_ad3(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE0_AD3) } #[doc = "Select AFE0_AD4"] #[inline(always)] - pub fn afe0_ad4(self) -> &'a mut W { + pub fn afe0_ad4(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE0_AD4) } #[doc = "Select AFE0_AD5"] #[inline(always)] - pub fn afe0_ad5(self) -> &'a mut W { + pub fn afe0_ad5(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE0_AD5) } #[doc = "Select AFE1_AD0"] #[inline(always)] - pub fn afe1_ad0(self) -> &'a mut W { + pub fn afe1_ad0(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE1_AD0) } #[doc = "Select AFE1_AD1"] #[inline(always)] - pub fn afe1_ad1(self) -> &'a mut W { + pub fn afe1_ad1(self) -> &'a mut crate::W { self.variant(SELPLUSSELECT_A::AFE1_AD1) } } @@ -325,28 +301,31 @@ impl ACEN_R { true => ACENSELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "Analog comparator disabled."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == ACENSELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "Analog comparator enabled."] #[inline(always)] pub fn is_en(&self) -> bool { *self == ACENSELECT_A::EN } } #[doc = "Field `ACEN` writer - Analog Comparator Enable"] -pub type ACEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, ACENSELECT_A>; -impl<'a, const O: u8> ACEN_W<'a, O> { +pub type ACEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ACENSELECT_A>; +impl<'a, REG, const O: u8> ACEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Analog comparator disabled."] #[inline(always)] - pub fn dis(self) -> &'a mut W { + pub fn dis(self) -> &'a mut crate::W { self.variant(ACENSELECT_A::DIS) } #[doc = "Analog comparator enabled."] #[inline(always)] - pub fn en(self) -> &'a mut W { + pub fn en(self) -> &'a mut crate::W { self.variant(ACENSELECT_A::EN) } } @@ -383,38 +362,42 @@ impl EDGETYP_R { _ => None, } } - #[doc = "Checks if the value of the field is `RISING`"] + #[doc = "Only rising edge of comparator output"] #[inline(always)] pub fn is_rising(&self) -> bool { *self == EDGETYPSELECT_A::RISING } - #[doc = "Checks if the value of the field is `FALLING`"] + #[doc = "Falling edge of comparator output"] #[inline(always)] pub fn is_falling(&self) -> bool { *self == EDGETYPSELECT_A::FALLING } - #[doc = "Checks if the value of the field is `ANY`"] + #[doc = "Any edge of comparator output"] #[inline(always)] pub fn is_any(&self) -> bool { *self == EDGETYPSELECT_A::ANY } } #[doc = "Field `EDGETYP` writer - Edge Type"] -pub type EDGETYP_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 2, O, EDGETYPSELECT_A>; -impl<'a, const O: u8> EDGETYP_W<'a, O> { +pub type EDGETYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, EDGETYPSELECT_A>; +impl<'a, REG, const O: u8> EDGETYP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Only rising edge of comparator output"] #[inline(always)] - pub fn rising(self) -> &'a mut W { + pub fn rising(self) -> &'a mut crate::W { self.variant(EDGETYPSELECT_A::RISING) } #[doc = "Falling edge of comparator output"] #[inline(always)] - pub fn falling(self) -> &'a mut W { + pub fn falling(self) -> &'a mut crate::W { self.variant(EDGETYPSELECT_A::FALLING) } #[doc = "Any edge of comparator output"] #[inline(always)] - pub fn any(self) -> &'a mut W { + pub fn any(self) -> &'a mut crate::W { self.variant(EDGETYPSELECT_A::ANY) } } @@ -443,28 +426,31 @@ impl INV_R { true => INVSELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "Analog comparator output is directly processed."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == INVSELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "Analog comparator output is inverted prior to being processed."] #[inline(always)] pub fn is_en(&self) -> bool { *self == INVSELECT_A::EN } } #[doc = "Field `INV` writer - Invert Comparator Output"] -pub type INV_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, INVSELECT_A>; -impl<'a, const O: u8> INV_W<'a, O> { +pub type INV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INVSELECT_A>; +impl<'a, REG, const O: u8> INV_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Analog comparator output is directly processed."] #[inline(always)] - pub fn dis(self) -> &'a mut W { + pub fn dis(self) -> &'a mut crate::W { self.variant(INVSELECT_A::DIS) } #[doc = "Analog comparator output is inverted prior to being processed."] #[inline(always)] - pub fn en(self) -> &'a mut W { + pub fn en(self) -> &'a mut crate::W { self.variant(INVSELECT_A::EN) } } @@ -493,28 +479,31 @@ impl SELFS_R { true => SELFSSELECT_A::OUTPUT, } } - #[doc = "Checks if the value of the field is `CE`"] + #[doc = "The CE flag is used to drive the FAULT output."] #[inline(always)] pub fn is_ce(&self) -> bool { *self == SELFSSELECT_A::CE } - #[doc = "Checks if the value of the field is `OUTPUT`"] + #[doc = "The output of the analog comparator flag is used to drive the FAULT output."] #[inline(always)] pub fn is_output(&self) -> bool { *self == SELFSSELECT_A::OUTPUT } } #[doc = "Field `SELFS` writer - Selection Of Fault Source"] -pub type SELFS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, SELFSSELECT_A>; -impl<'a, const O: u8> SELFS_W<'a, O> { +pub type SELFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SELFSSELECT_A>; +impl<'a, REG, const O: u8> SELFS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The CE flag is used to drive the FAULT output."] #[inline(always)] - pub fn ce(self) -> &'a mut W { + pub fn ce(self) -> &'a mut crate::W { self.variant(SELFSSELECT_A::CE) } #[doc = "The output of the analog comparator flag is used to drive the FAULT output."] #[inline(always)] - pub fn output(self) -> &'a mut W { + pub fn output(self) -> &'a mut crate::W { self.variant(SELFSSELECT_A::OUTPUT) } } @@ -543,28 +532,31 @@ impl FE_R { true => FESELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The FAULT output is tied to 0."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == FESELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The FAULT output is driven by the signal defined by SELFS."] #[inline(always)] pub fn is_en(&self) -> bool { *self == FESELECT_A::EN } } #[doc = "Field `FE` writer - Fault Enable"] -pub type FE_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, FESELECT_A>; -impl<'a, const O: u8> FE_W<'a, O> { +pub type FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FESELECT_A>; +impl<'a, REG, const O: u8> FE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The FAULT output is tied to 0."] #[inline(always)] - pub fn dis(self) -> &'a mut W { + pub fn dis(self) -> &'a mut crate::W { self.variant(FESELECT_A::DIS) } #[doc = "The FAULT output is driven by the signal defined by SELFS."] #[inline(always)] - pub fn en(self) -> &'a mut W { + pub fn en(self) -> &'a mut crate::W { self.variant(FESELECT_A::EN) } } @@ -609,64 +601,61 @@ impl W { #[doc = "Bits 0:2 - Selection for Minus Comparator Input"] #[inline(always)] #[must_use] - pub fn selminus(&mut self) -> SELMINUS_W<0> { + pub fn selminus(&mut self) -> SELMINUS_W { SELMINUS_W::new(self) } #[doc = "Bits 4:6 - Selection For Plus Comparator Input"] #[inline(always)] #[must_use] - pub fn selplus(&mut self) -> SELPLUS_W<4> { + pub fn selplus(&mut self) -> SELPLUS_W { SELPLUS_W::new(self) } #[doc = "Bit 8 - Analog Comparator Enable"] #[inline(always)] #[must_use] - pub fn acen(&mut self) -> ACEN_W<8> { + pub fn acen(&mut self) -> ACEN_W { ACEN_W::new(self) } #[doc = "Bits 9:10 - Edge Type"] #[inline(always)] #[must_use] - pub fn edgetyp(&mut self) -> EDGETYP_W<9> { + pub fn edgetyp(&mut self) -> EDGETYP_W { EDGETYP_W::new(self) } #[doc = "Bit 12 - Invert Comparator Output"] #[inline(always)] #[must_use] - pub fn inv(&mut self) -> INV_W<12> { + pub fn inv(&mut self) -> INV_W { INV_W::new(self) } #[doc = "Bit 13 - Selection Of Fault Source"] #[inline(always)] #[must_use] - pub fn selfs(&mut self) -> SELFS_W<13> { + pub fn selfs(&mut self) -> SELFS_W { SELFS_W::new(self) } #[doc = "Bit 14 - Fault Enable"] #[inline(always)] #[must_use] - pub fn fe(&mut self) -> FE_W<14> { + pub fn fe(&mut self) -> FE_W { FE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/acc/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/acc/wpmr.rs index 4efb38b0..fe7c4d66 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/acc/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/acc/wpsr.rs index c1214e9c..c581f09d 100644 --- a/arch/cortex-m/samv71q21-pac/src/acc/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/acc/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; impl R { @@ -22,15 +9,13 @@ impl R { WPVS_R::new((self.bits & 1) != 0) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/aes.rs b/arch/cortex-m/samv71q21-pac/src/aes.rs index f8f141ca..2050db65 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes.rs @@ -35,67 +35,83 @@ pub struct RegisterBlock { #[doc = "0x9c..0xac - GCM H Word Register"] pub gcmhr: [GCMHR; 4], } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "KEYWR (w) register accessor: an alias for `Reg`"] +#[doc = "KEYWR (w) register accessor: Key Word Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keywr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`keywr`] +module"] pub type KEYWR = crate::Reg; #[doc = "Key Word Register"] pub mod keywr; -#[doc = "IDATAR (w) register accessor: an alias for `Reg`"] +#[doc = "IDATAR (w) register accessor: Input Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idatar::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idatar`] +module"] pub type IDATAR = crate::Reg; #[doc = "Input Data Register"] pub mod idatar; -#[doc = "ODATAR (r) register accessor: an alias for `Reg`"] +#[doc = "ODATAR (r) register accessor: Output Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odatar::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`odatar`] +module"] pub type ODATAR = crate::Reg; #[doc = "Output Data Register"] pub mod odatar; -#[doc = "IVR (w) register accessor: an alias for `Reg`"] +#[doc = "IVR (w) register accessor: Initialization Vector Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ivr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ivr`] +module"] pub type IVR = crate::Reg; #[doc = "Initialization Vector Register"] pub mod ivr; -#[doc = "AADLENR (rw) register accessor: an alias for `Reg`"] +#[doc = "AADLENR (rw) register accessor: Additional Authenticated Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aadlenr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aadlenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aadlenr`] +module"] pub type AADLENR = crate::Reg; #[doc = "Additional Authenticated Data Length Register"] pub mod aadlenr; -#[doc = "CLENR (rw) register accessor: an alias for `Reg`"] +#[doc = "CLENR (rw) register accessor: Plaintext/Ciphertext Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clenr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clenr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clenr`] +module"] pub type CLENR = crate::Reg; #[doc = "Plaintext/Ciphertext Length Register"] pub mod clenr; -#[doc = "GHASHR (rw) register accessor: an alias for `Reg`"] +#[doc = "GHASHR (rw) register accessor: GCM Intermediate Hash Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghashr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ghashr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ghashr`] +module"] pub type GHASHR = crate::Reg; #[doc = "GCM Intermediate Hash Word Register"] pub mod ghashr; -#[doc = "TAGR (r) register accessor: an alias for `Reg`"] +#[doc = "TAGR (r) register accessor: GCM Authentication Tag Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tagr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tagr`] +module"] pub type TAGR = crate::Reg; #[doc = "GCM Authentication Tag Word Register"] pub mod tagr; -#[doc = "CTRR (r) register accessor: an alias for `Reg`"] +#[doc = "CTRR (r) register accessor: GCM Encryption Counter Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrr`] +module"] pub type CTRR = crate::Reg; #[doc = "GCM Encryption Counter Value Register"] pub mod ctrr; -#[doc = "GCMHR (rw) register accessor: an alias for `Reg`"] +#[doc = "GCMHR (rw) register accessor: GCM H Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcmhr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcmhr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gcmhr`] +module"] pub type GCMHR = crate::Reg; #[doc = "GCM H Word Register"] pub mod gcmhr; diff --git a/arch/cortex-m/samv71q21-pac/src/aes/aadlenr.rs b/arch/cortex-m/samv71q21-pac/src/aes/aadlenr.rs index 13def876..219f2772 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/aadlenr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/aadlenr.rs @@ -1,43 +1,11 @@ #[doc = "Register `AADLENR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `AADLENR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AADLEN` reader - Additional Authenticated Data Length"] pub type AADLEN_R = crate::FieldReader; #[doc = "Field `AADLEN` writer - Additional Authenticated Data Length"] -pub type AADLEN_W<'a, const O: u8> = crate::FieldWriter<'a, AADLENR_SPEC, 32, O, u32>; +pub type AADLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Additional Authenticated Data Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Additional Authenticated Data Length"] #[inline(always)] #[must_use] - pub fn aadlen(&mut self) -> AADLEN_W<0> { + pub fn aadlen(&mut self) -> AADLEN_W { AADLEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Additional Authenticated Data Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aadlenr](index.html) module"] +#[doc = "Additional Authenticated Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aadlenr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aadlenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AADLENR_SPEC; impl crate::RegisterSpec for AADLENR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [aadlenr::R](R) reader structure"] -impl crate::Readable for AADLENR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [aadlenr::W](W) writer structure"] +#[doc = "`read()` method returns [`aadlenr::R`](R) reader structure"] +impl crate::Readable for AADLENR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aadlenr::W`](W) writer structure"] impl crate::Writable for AADLENR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/clenr.rs b/arch/cortex-m/samv71q21-pac/src/aes/clenr.rs index 88f668d3..82415592 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/clenr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/clenr.rs @@ -1,43 +1,11 @@ #[doc = "Register `CLENR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLENR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLEN` reader - Plaintext/Ciphertext Length"] pub type CLEN_R = crate::FieldReader; #[doc = "Field `CLEN` writer - Plaintext/Ciphertext Length"] -pub type CLEN_W<'a, const O: u8> = crate::FieldWriter<'a, CLENR_SPEC, 32, O, u32>; +pub type CLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Plaintext/Ciphertext Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Plaintext/Ciphertext Length"] #[inline(always)] #[must_use] - pub fn clen(&mut self) -> CLEN_W<0> { + pub fn clen(&mut self) -> CLEN_W { CLEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Plaintext/Ciphertext Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clenr](index.html) module"] +#[doc = "Plaintext/Ciphertext Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clenr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clenr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLENR_SPEC; impl crate::RegisterSpec for CLENR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clenr::R](R) reader structure"] -impl crate::Readable for CLENR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clenr::W](W) writer structure"] +#[doc = "`read()` method returns [`clenr::R`](R) reader structure"] +impl crate::Readable for CLENR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clenr::W`](W) writer structure"] impl crate::Writable for CLENR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/cr.rs b/arch/cortex-m/samv71q21-pac/src/aes/cr.rs index ca80e089..fb86eba7 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/cr.rs @@ -1,64 +1,44 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `START` writer - Start Processing"] -pub type START_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOADSEED` writer - Random Number Generator Seed Loading"] -pub type LOADSEED_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type LOADSEED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Start Processing"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W<0> { + pub fn start(&mut self) -> START_W { START_W::new(self) } #[doc = "Bit 8 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<8> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Bit 16 - Random Number Generator Seed Loading"] #[inline(always)] #[must_use] - pub fn loadseed(&mut self) -> LOADSEED_W<16> { + pub fn loadseed(&mut self) -> LOADSEED_W { LOADSEED_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/ctrr.rs b/arch/cortex-m/samv71q21-pac/src/aes/ctrr.rs index 215ef95d..81b98e6d 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/ctrr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/ctrr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CTRR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CTR` reader - GCM Encryption Counter"] pub type CTR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CTR_R::new(self.bits) } } -#[doc = "GCM Encryption Counter Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrr](index.html) module"] +#[doc = "GCM Encryption Counter Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRR_SPEC; impl crate::RegisterSpec for CTRR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrr::R](R) reader structure"] -impl crate::Readable for CTRR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ctrr::R`](R) reader structure"] +impl crate::Readable for CTRR_SPEC {} #[doc = "`reset()` method sets CTRR to value 0"] impl crate::Resettable for CTRR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/aes/gcmhr.rs b/arch/cortex-m/samv71q21-pac/src/aes/gcmhr.rs index a7966845..40bb98f0 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/gcmhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/gcmhr.rs @@ -1,43 +1,11 @@ #[doc = "Register `GCMHR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GCMHR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `H` reader - GCM H Word x"] pub type H_R = crate::FieldReader; #[doc = "Field `H` writer - GCM H Word x"] -pub type H_W<'a, const O: u8> = crate::FieldWriter<'a, GCMHR_SPEC, 32, O, u32>; +pub type H_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - GCM H Word x"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - GCM H Word x"] #[inline(always)] #[must_use] - pub fn h(&mut self) -> H_W<0> { + pub fn h(&mut self) -> H_W { H_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GCM H Word Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcmhr](index.html) module"] +#[doc = "GCM H Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcmhr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcmhr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GCMHR_SPEC; impl crate::RegisterSpec for GCMHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gcmhr::R](R) reader structure"] -impl crate::Readable for GCMHR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gcmhr::W](W) writer structure"] +#[doc = "`read()` method returns [`gcmhr::R`](R) reader structure"] +impl crate::Readable for GCMHR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gcmhr::W`](W) writer structure"] impl crate::Writable for GCMHR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/ghashr.rs b/arch/cortex-m/samv71q21-pac/src/aes/ghashr.rs index de50b18a..7343a2d1 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/ghashr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/ghashr.rs @@ -1,43 +1,11 @@ #[doc = "Register `GHASHR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GHASHR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GHASH` reader - Intermediate GCM Hash Word x"] pub type GHASH_R = crate::FieldReader; #[doc = "Field `GHASH` writer - Intermediate GCM Hash Word x"] -pub type GHASH_W<'a, const O: u8> = crate::FieldWriter<'a, GHASHR_SPEC, 32, O, u32>; +pub type GHASH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Intermediate GCM Hash Word x"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Intermediate GCM Hash Word x"] #[inline(always)] #[must_use] - pub fn ghash(&mut self) -> GHASH_W<0> { + pub fn ghash(&mut self) -> GHASH_W { GHASH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "GCM Intermediate Hash Word Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ghashr](index.html) module"] +#[doc = "GCM Intermediate Hash Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ghashr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ghashr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GHASHR_SPEC; impl crate::RegisterSpec for GHASHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ghashr::R](R) reader structure"] -impl crate::Readable for GHASHR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ghashr::W](W) writer structure"] +#[doc = "`read()` method returns [`ghashr::R`](R) reader structure"] +impl crate::Readable for GHASHR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ghashr::W`](W) writer structure"] impl crate::Writable for GHASHR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/idatar.rs b/arch/cortex-m/samv71q21-pac/src/aes/idatar.rs index 1a33e7bd..a18f6d5e 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/idatar.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/idatar.rs @@ -1,48 +1,28 @@ #[doc = "Register `IDATAR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IDATA` writer - Input Data Word"] -pub type IDATA_W<'a, const O: u8> = crate::FieldWriter<'a, IDATAR_SPEC, 32, O, u32>; +pub type IDATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Input Data Word"] #[inline(always)] #[must_use] - pub fn idata(&mut self) -> IDATA_W<0> { + pub fn idata(&mut self) -> IDATA_W { IDATA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Input Data Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idatar](index.html) module"] +#[doc = "Input Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idatar::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDATAR_SPEC; impl crate::RegisterSpec for IDATAR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idatar::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idatar::W`](W) writer structure"] impl crate::Writable for IDATAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/idr.rs b/arch/cortex-m/samv71q21-pac/src/aes/idr.rs index daf185db..69446bf6 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/idr.rs @@ -1,64 +1,44 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATRDY` writer - Data Ready Interrupt Disable"] -pub type DATRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DATRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `URAD` writer - Unspecified Register Access Detection Interrupt Disable"] -pub type URAD_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type URAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TAGRDY` writer - GCM Tag Ready Interrupt Disable"] -pub type TAGRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TAGRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Data Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn datrdy(&mut self) -> DATRDY_W<0> { + pub fn datrdy(&mut self) -> DATRDY_W { DATRDY_W::new(self) } #[doc = "Bit 8 - Unspecified Register Access Detection Interrupt Disable"] #[inline(always)] #[must_use] - pub fn urad(&mut self) -> URAD_W<8> { + pub fn urad(&mut self) -> URAD_W { URAD_W::new(self) } #[doc = "Bit 16 - GCM Tag Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn tagrdy(&mut self) -> TAGRDY_W<16> { + pub fn tagrdy(&mut self) -> TAGRDY_W { TAGRDY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/ier.rs b/arch/cortex-m/samv71q21-pac/src/aes/ier.rs index d427566f..24843c56 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/ier.rs @@ -1,64 +1,44 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATRDY` writer - Data Ready Interrupt Enable"] -pub type DATRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DATRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `URAD` writer - Unspecified Register Access Detection Interrupt Enable"] -pub type URAD_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type URAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TAGRDY` writer - GCM Tag Ready Interrupt Enable"] -pub type TAGRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TAGRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Data Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn datrdy(&mut self) -> DATRDY_W<0> { + pub fn datrdy(&mut self) -> DATRDY_W { DATRDY_W::new(self) } #[doc = "Bit 8 - Unspecified Register Access Detection Interrupt Enable"] #[inline(always)] #[must_use] - pub fn urad(&mut self) -> URAD_W<8> { + pub fn urad(&mut self) -> URAD_W { URAD_W::new(self) } #[doc = "Bit 16 - GCM Tag Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tagrdy(&mut self) -> TAGRDY_W<16> { + pub fn tagrdy(&mut self) -> TAGRDY_W { TAGRDY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/imr.rs b/arch/cortex-m/samv71q21-pac/src/aes/imr.rs index 9d28424f..9f2da71b 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATRDY` reader - Data Ready Interrupt Mask"] pub type DATRDY_R = crate::BitReader; #[doc = "Field `URAD` reader - Unspecified Register Access Detection Interrupt Mask"] @@ -36,15 +23,13 @@ impl R { TAGRDY_R::new(((self.bits >> 16) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/aes/isr.rs b/arch/cortex-m/samv71q21-pac/src/aes/isr.rs index 21ab12b4..f1cabc04 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATRDY` reader - Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)"] pub type DATRDY_R = crate::BitReader; #[doc = "Field `URAD` reader - Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)"] @@ -59,32 +46,32 @@ impl URAT_R { _ => None, } } - #[doc = "Checks if the value of the field is `IDR_WR_PROCESSING`"] + #[doc = "Input Data Register written during the data processing when SMOD = 0x2 mode."] #[inline(always)] pub fn is_idr_wr_processing(&self) -> bool { *self == URATSELECT_A::IDR_WR_PROCESSING } - #[doc = "Checks if the value of the field is `ODR_RD_PROCESSING`"] + #[doc = "Output Data Register read during the data processing."] #[inline(always)] pub fn is_odr_rd_processing(&self) -> bool { *self == URATSELECT_A::ODR_RD_PROCESSING } - #[doc = "Checks if the value of the field is `MR_WR_PROCESSING`"] + #[doc = "Mode Register written during the data processing."] #[inline(always)] pub fn is_mr_wr_processing(&self) -> bool { *self == URATSELECT_A::MR_WR_PROCESSING } - #[doc = "Checks if the value of the field is `ODR_RD_SUBKGEN`"] + #[doc = "Output Data Register read during the sub-keys generation."] #[inline(always)] pub fn is_odr_rd_subkgen(&self) -> bool { *self == URATSELECT_A::ODR_RD_SUBKGEN } - #[doc = "Checks if the value of the field is `MR_WR_SUBKGEN`"] + #[doc = "Mode Register written during the sub-keys generation."] #[inline(always)] pub fn is_mr_wr_subkgen(&self) -> bool { *self == URATSELECT_A::MR_WR_SUBKGEN } - #[doc = "Checks if the value of the field is `WOR_RD_ACCESS`"] + #[doc = "Write-only register read access."] #[inline(always)] pub fn is_wor_rd_access(&self) -> bool { *self == URATSELECT_A::WOR_RD_ACCESS @@ -114,15 +101,13 @@ impl R { TAGRDY_R::new(((self.bits >> 16) & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/aes/ivr.rs b/arch/cortex-m/samv71q21-pac/src/aes/ivr.rs index 6f885f39..3e7e8e93 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/ivr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/ivr.rs @@ -1,48 +1,28 @@ #[doc = "Register `IVR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IV` writer - Initialization Vector"] -pub type IV_W<'a, const O: u8> = crate::FieldWriter<'a, IVR_SPEC, 32, O, u32>; +pub type IV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Initialization Vector"] #[inline(always)] #[must_use] - pub fn iv(&mut self) -> IV_W<0> { + pub fn iv(&mut self) -> IV_W { IV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Initialization Vector Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ivr](index.html) module"] +#[doc = "Initialization Vector Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ivr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IVR_SPEC; impl crate::RegisterSpec for IVR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ivr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ivr::W`](W) writer structure"] impl crate::Writable for IVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/keywr.rs b/arch/cortex-m/samv71q21-pac/src/aes/keywr.rs index 62149d56..6b91182d 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/keywr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/keywr.rs @@ -1,48 +1,28 @@ #[doc = "Register `KEYWR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `KEYW` writer - Key Word"] -pub type KEYW_W<'a, const O: u8> = crate::FieldWriter<'a, KEYWR_SPEC, 32, O, u32>; +pub type KEYW_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Key Word"] #[inline(always)] #[must_use] - pub fn keyw(&mut self) -> KEYW_W<0> { + pub fn keyw(&mut self) -> KEYW_W { KEYW_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Key Word Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [keywr](index.html) module"] +#[doc = "Key Word Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keywr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KEYWR_SPEC; impl crate::RegisterSpec for KEYWR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [keywr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`keywr::W`](W) writer structure"] impl crate::Writable for KEYWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/mr.rs b/arch/cortex-m/samv71q21-pac/src/aes/mr.rs index 048a2ae5..2ce84492 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/mr.rs @@ -1,47 +1,15 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CIPHER` reader - Processing Mode"] pub type CIPHER_R = crate::BitReader; #[doc = "Field `CIPHER` writer - Processing Mode"] -pub type CIPHER_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type CIPHER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GTAGEN` reader - GCM Automatic Tag Generation Enable"] pub type GTAGEN_R = crate::BitReader; #[doc = "Field `GTAGEN` writer - GCM Automatic Tag Generation Enable"] -pub type GTAGEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type GTAGEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUALBUFF` reader - Dual Input Buffer"] pub type DUALBUFF_R = crate::BitReader; #[doc = "Dual Input Buffer\n\nValue on reset: 0"] @@ -67,35 +35,38 @@ impl DUALBUFF_R { true => DUALBUFFSELECT_A::ACTIVE, } } - #[doc = "Checks if the value of the field is `INACTIVE`"] + #[doc = "AES_IDATARx cannot be written during processing of previous block."] #[inline(always)] pub fn is_inactive(&self) -> bool { *self == DUALBUFFSELECT_A::INACTIVE } - #[doc = "Checks if the value of the field is `ACTIVE`"] + #[doc = "AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files."] #[inline(always)] pub fn is_active(&self) -> bool { *self == DUALBUFFSELECT_A::ACTIVE } } #[doc = "Field `DUALBUFF` writer - Dual Input Buffer"] -pub type DUALBUFF_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, DUALBUFFSELECT_A>; -impl<'a, const O: u8> DUALBUFF_W<'a, O> { +pub type DUALBUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DUALBUFFSELECT_A>; +impl<'a, REG, const O: u8> DUALBUFF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "AES_IDATARx cannot be written during processing of previous block."] #[inline(always)] - pub fn inactive(self) -> &'a mut W { + pub fn inactive(self) -> &'a mut crate::W { self.variant(DUALBUFFSELECT_A::INACTIVE) } #[doc = "AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files."] #[inline(always)] - pub fn active(self) -> &'a mut W { + pub fn active(self) -> &'a mut crate::W { self.variant(DUALBUFFSELECT_A::ACTIVE) } } #[doc = "Field `PROCDLY` reader - Processing Delay"] pub type PROCDLY_R = crate::FieldReader; #[doc = "Field `PROCDLY` writer - Processing Delay"] -pub type PROCDLY_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O>; +pub type PROCDLY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SMOD` reader - Start Mode"] pub type SMOD_R = crate::FieldReader; #[doc = "Start Mode\n\nValue on reset: 0"] @@ -129,38 +100,42 @@ impl SMOD_R { _ => None, } } - #[doc = "Checks if the value of the field is `MANUAL_START`"] + #[doc = "Manual Mode"] #[inline(always)] pub fn is_manual_start(&self) -> bool { *self == SMODSELECT_A::MANUAL_START } - #[doc = "Checks if the value of the field is `AUTO_START`"] + #[doc = "Auto Mode"] #[inline(always)] pub fn is_auto_start(&self) -> bool { *self == SMODSELECT_A::AUTO_START } - #[doc = "Checks if the value of the field is `IDATAR0_START`"] + #[doc = "AES_IDATAR0 access only Auto Mode (DMA)"] #[inline(always)] pub fn is_idatar0_start(&self) -> bool { *self == SMODSELECT_A::IDATAR0_START } } #[doc = "Field `SMOD` writer - Start Mode"] -pub type SMOD_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 2, O, SMODSELECT_A>; -impl<'a, const O: u8> SMOD_W<'a, O> { +pub type SMOD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, SMODSELECT_A>; +impl<'a, REG, const O: u8> SMOD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Manual Mode"] #[inline(always)] - pub fn manual_start(self) -> &'a mut W { + pub fn manual_start(self) -> &'a mut crate::W { self.variant(SMODSELECT_A::MANUAL_START) } #[doc = "Auto Mode"] #[inline(always)] - pub fn auto_start(self) -> &'a mut W { + pub fn auto_start(self) -> &'a mut crate::W { self.variant(SMODSELECT_A::AUTO_START) } #[doc = "AES_IDATAR0 access only Auto Mode (DMA)"] #[inline(always)] - pub fn idatar0_start(self) -> &'a mut W { + pub fn idatar0_start(self) -> &'a mut crate::W { self.variant(SMODSELECT_A::IDATAR0_START) } } @@ -197,38 +172,42 @@ impl KEYSIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `AES128`"] + #[doc = "AES Key Size is 128 bits"] #[inline(always)] pub fn is_aes128(&self) -> bool { *self == KEYSIZESELECT_A::AES128 } - #[doc = "Checks if the value of the field is `AES192`"] + #[doc = "AES Key Size is 192 bits"] #[inline(always)] pub fn is_aes192(&self) -> bool { *self == KEYSIZESELECT_A::AES192 } - #[doc = "Checks if the value of the field is `AES256`"] + #[doc = "AES Key Size is 256 bits"] #[inline(always)] pub fn is_aes256(&self) -> bool { *self == KEYSIZESELECT_A::AES256 } } #[doc = "Field `KEYSIZE` writer - Key Size"] -pub type KEYSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 2, O, KEYSIZESELECT_A>; -impl<'a, const O: u8> KEYSIZE_W<'a, O> { +pub type KEYSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, KEYSIZESELECT_A>; +impl<'a, REG, const O: u8> KEYSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "AES Key Size is 128 bits"] #[inline(always)] - pub fn aes128(self) -> &'a mut W { + pub fn aes128(self) -> &'a mut crate::W { self.variant(KEYSIZESELECT_A::AES128) } #[doc = "AES Key Size is 192 bits"] #[inline(always)] - pub fn aes192(self) -> &'a mut W { + pub fn aes192(self) -> &'a mut crate::W { self.variant(KEYSIZESELECT_A::AES192) } #[doc = "AES Key Size is 256 bits"] #[inline(always)] - pub fn aes256(self) -> &'a mut W { + pub fn aes256(self) -> &'a mut crate::W { self.variant(KEYSIZESELECT_A::AES256) } } @@ -274,75 +253,79 @@ impl OPMOD_R { _ => None, } } - #[doc = "Checks if the value of the field is `ECB`"] + #[doc = "ECB: Electronic Code Book mode"] #[inline(always)] pub fn is_ecb(&self) -> bool { *self == OPMODSELECT_A::ECB } - #[doc = "Checks if the value of the field is `CBC`"] + #[doc = "CBC: Cipher Block Chaining mode"] #[inline(always)] pub fn is_cbc(&self) -> bool { *self == OPMODSELECT_A::CBC } - #[doc = "Checks if the value of the field is `OFB`"] + #[doc = "OFB: Output Feedback mode"] #[inline(always)] pub fn is_ofb(&self) -> bool { *self == OPMODSELECT_A::OFB } - #[doc = "Checks if the value of the field is `CFB`"] + #[doc = "CFB: Cipher Feedback mode"] #[inline(always)] pub fn is_cfb(&self) -> bool { *self == OPMODSELECT_A::CFB } - #[doc = "Checks if the value of the field is `CTR`"] + #[doc = "CTR: Counter mode (16-bit internal counter)"] #[inline(always)] pub fn is_ctr(&self) -> bool { *self == OPMODSELECT_A::CTR } - #[doc = "Checks if the value of the field is `GCM`"] + #[doc = "GCM: Galois/Counter mode"] #[inline(always)] pub fn is_gcm(&self) -> bool { *self == OPMODSELECT_A::GCM } } #[doc = "Field `OPMOD` writer - Operating Mode"] -pub type OPMOD_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 3, O, OPMODSELECT_A>; -impl<'a, const O: u8> OPMOD_W<'a, O> { +pub type OPMOD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, OPMODSELECT_A>; +impl<'a, REG, const O: u8> OPMOD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "ECB: Electronic Code Book mode"] #[inline(always)] - pub fn ecb(self) -> &'a mut W { + pub fn ecb(self) -> &'a mut crate::W { self.variant(OPMODSELECT_A::ECB) } #[doc = "CBC: Cipher Block Chaining mode"] #[inline(always)] - pub fn cbc(self) -> &'a mut W { + pub fn cbc(self) -> &'a mut crate::W { self.variant(OPMODSELECT_A::CBC) } #[doc = "OFB: Output Feedback mode"] #[inline(always)] - pub fn ofb(self) -> &'a mut W { + pub fn ofb(self) -> &'a mut crate::W { self.variant(OPMODSELECT_A::OFB) } #[doc = "CFB: Cipher Feedback mode"] #[inline(always)] - pub fn cfb(self) -> &'a mut W { + pub fn cfb(self) -> &'a mut crate::W { self.variant(OPMODSELECT_A::CFB) } #[doc = "CTR: Counter mode (16-bit internal counter)"] #[inline(always)] - pub fn ctr(self) -> &'a mut W { + pub fn ctr(self) -> &'a mut crate::W { self.variant(OPMODSELECT_A::CTR) } #[doc = "GCM: Galois/Counter mode"] #[inline(always)] - pub fn gcm(self) -> &'a mut W { + pub fn gcm(self) -> &'a mut crate::W { self.variant(OPMODSELECT_A::GCM) } } #[doc = "Field `LOD` reader - Last Output Data Mode"] pub type LOD_R = crate::BitReader; #[doc = "Field `LOD` writer - Last Output Data Mode"] -pub type LOD_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type LOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFBS` reader - Cipher Feedback Data Size"] pub type CFBS_R = crate::FieldReader; #[doc = "Cipher Feedback Data Size\n\nValue on reset: 0"] @@ -382,58 +365,62 @@ impl CFBS_R { _ => None, } } - #[doc = "Checks if the value of the field is `SIZE_128BIT`"] + #[doc = "128-bit"] #[inline(always)] pub fn is_size_128bit(&self) -> bool { *self == CFBSSELECT_A::SIZE_128BIT } - #[doc = "Checks if the value of the field is `SIZE_64BIT`"] + #[doc = "64-bit"] #[inline(always)] pub fn is_size_64bit(&self) -> bool { *self == CFBSSELECT_A::SIZE_64BIT } - #[doc = "Checks if the value of the field is `SIZE_32BIT`"] + #[doc = "32-bit"] #[inline(always)] pub fn is_size_32bit(&self) -> bool { *self == CFBSSELECT_A::SIZE_32BIT } - #[doc = "Checks if the value of the field is `SIZE_16BIT`"] + #[doc = "16-bit"] #[inline(always)] pub fn is_size_16bit(&self) -> bool { *self == CFBSSELECT_A::SIZE_16BIT } - #[doc = "Checks if the value of the field is `SIZE_8BIT`"] + #[doc = "8-bit"] #[inline(always)] pub fn is_size_8bit(&self) -> bool { *self == CFBSSELECT_A::SIZE_8BIT } } #[doc = "Field `CFBS` writer - Cipher Feedback Data Size"] -pub type CFBS_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 3, O, CFBSSELECT_A>; -impl<'a, const O: u8> CFBS_W<'a, O> { +pub type CFBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CFBSSELECT_A>; +impl<'a, REG, const O: u8> CFBS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "128-bit"] #[inline(always)] - pub fn size_128bit(self) -> &'a mut W { + pub fn size_128bit(self) -> &'a mut crate::W { self.variant(CFBSSELECT_A::SIZE_128BIT) } #[doc = "64-bit"] #[inline(always)] - pub fn size_64bit(self) -> &'a mut W { + pub fn size_64bit(self) -> &'a mut crate::W { self.variant(CFBSSELECT_A::SIZE_64BIT) } #[doc = "32-bit"] #[inline(always)] - pub fn size_32bit(self) -> &'a mut W { + pub fn size_32bit(self) -> &'a mut crate::W { self.variant(CFBSSELECT_A::SIZE_32BIT) } #[doc = "16-bit"] #[inline(always)] - pub fn size_16bit(self) -> &'a mut W { + pub fn size_16bit(self) -> &'a mut crate::W { self.variant(CFBSSELECT_A::SIZE_16BIT) } #[doc = "8-bit"] #[inline(always)] - pub fn size_8bit(self) -> &'a mut W { + pub fn size_8bit(self) -> &'a mut crate::W { self.variant(CFBSSELECT_A::SIZE_8BIT) } } @@ -464,18 +451,22 @@ impl CKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == CKEYSELECT_A::PASSWD } } #[doc = "Field `CKEY` writer - Countermeasure Key"] -pub type CKEY_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O, CKEYSELECT_A>; -impl<'a, const O: u8> CKEY_W<'a, O> { +pub type CKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, CKEYSELECT_A>; +impl<'a, REG, const O: u8> CKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(CKEYSELECT_A::PASSWD) } } @@ -535,82 +526,79 @@ impl W { #[doc = "Bit 0 - Processing Mode"] #[inline(always)] #[must_use] - pub fn cipher(&mut self) -> CIPHER_W<0> { + pub fn cipher(&mut self) -> CIPHER_W { CIPHER_W::new(self) } #[doc = "Bit 1 - GCM Automatic Tag Generation Enable"] #[inline(always)] #[must_use] - pub fn gtagen(&mut self) -> GTAGEN_W<1> { + pub fn gtagen(&mut self) -> GTAGEN_W { GTAGEN_W::new(self) } #[doc = "Bit 3 - Dual Input Buffer"] #[inline(always)] #[must_use] - pub fn dualbuff(&mut self) -> DUALBUFF_W<3> { + pub fn dualbuff(&mut self) -> DUALBUFF_W { DUALBUFF_W::new(self) } #[doc = "Bits 4:7 - Processing Delay"] #[inline(always)] #[must_use] - pub fn procdly(&mut self) -> PROCDLY_W<4> { + pub fn procdly(&mut self) -> PROCDLY_W { PROCDLY_W::new(self) } #[doc = "Bits 8:9 - Start Mode"] #[inline(always)] #[must_use] - pub fn smod(&mut self) -> SMOD_W<8> { + pub fn smod(&mut self) -> SMOD_W { SMOD_W::new(self) } #[doc = "Bits 10:11 - Key Size"] #[inline(always)] #[must_use] - pub fn keysize(&mut self) -> KEYSIZE_W<10> { + pub fn keysize(&mut self) -> KEYSIZE_W { KEYSIZE_W::new(self) } #[doc = "Bits 12:14 - Operating Mode"] #[inline(always)] #[must_use] - pub fn opmod(&mut self) -> OPMOD_W<12> { + pub fn opmod(&mut self) -> OPMOD_W { OPMOD_W::new(self) } #[doc = "Bit 15 - Last Output Data Mode"] #[inline(always)] #[must_use] - pub fn lod(&mut self) -> LOD_W<15> { + pub fn lod(&mut self) -> LOD_W { LOD_W::new(self) } #[doc = "Bits 16:18 - Cipher Feedback Data Size"] #[inline(always)] #[must_use] - pub fn cfbs(&mut self) -> CFBS_W<16> { + pub fn cfbs(&mut self) -> CFBS_W { CFBS_W::new(self) } #[doc = "Bits 20:23 - Countermeasure Key"] #[inline(always)] #[must_use] - pub fn ckey(&mut self) -> CKEY_W<20> { + pub fn ckey(&mut self) -> CKEY_W { CKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/aes/odatar.rs b/arch/cortex-m/samv71q21-pac/src/aes/odatar.rs index 2a0821ed..f6bfd77e 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/odatar.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/odatar.rs @@ -1,18 +1,5 @@ #[doc = "Register `ODATAR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ODATA` reader - Output Data"] pub type ODATA_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { ODATA_R::new(self.bits) } } -#[doc = "Output Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odatar](index.html) module"] +#[doc = "Output Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odatar::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ODATAR_SPEC; impl crate::RegisterSpec for ODATAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [odatar::R](R) reader structure"] -impl crate::Readable for ODATAR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`odatar::R`](R) reader structure"] +impl crate::Readable for ODATAR_SPEC {} #[doc = "`reset()` method sets ODATAR[%s] to value 0"] impl crate::Resettable for ODATAR_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/aes/tagr.rs b/arch/cortex-m/samv71q21-pac/src/aes/tagr.rs index aa45af22..630e5992 100644 --- a/arch/cortex-m/samv71q21-pac/src/aes/tagr.rs +++ b/arch/cortex-m/samv71q21-pac/src/aes/tagr.rs @@ -1,18 +1,5 @@ #[doc = "Register `TAGR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TAG` reader - GCM Authentication Tag x"] pub type TAG_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { TAG_R::new(self.bits) } } -#[doc = "GCM Authentication Tag Word Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tagr](index.html) module"] +#[doc = "GCM Authentication Tag Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tagr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TAGR_SPEC; impl crate::RegisterSpec for TAGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tagr::R](R) reader structure"] -impl crate::Readable for TAGR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tagr::R`](R) reader structure"] +impl crate::Readable for TAGR_SPEC {} #[doc = "`reset()` method sets TAGR[%s] to value 0"] impl crate::Resettable for TAGR_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/afec0.rs b/arch/cortex-m/samv71q21-pac/src/afec0.rs index ffb8f8dc..3ebb0785 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0.rs @@ -66,119 +66,148 @@ pub struct RegisterBlock { #[doc = "0xe8 - AFEC Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: AFEC Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "AFEC Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: AFEC Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "AFEC Mode Register"] pub mod mr; -#[doc = "EMR (rw) register accessor: an alias for `Reg`"] +#[doc = "EMR (rw) register accessor: AFEC Extended Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`emr`] +module"] pub type EMR = crate::Reg; #[doc = "AFEC Extended Mode Register"] pub mod emr; -#[doc = "SEQ1R (rw) register accessor: an alias for `Reg`"] +#[doc = "SEQ1R (rw) register accessor: AFEC Channel Sequence 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq1r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq1r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`seq1r`] +module"] pub type SEQ1R = crate::Reg; #[doc = "AFEC Channel Sequence 1 Register"] pub mod seq1r; -#[doc = "SEQ2R (rw) register accessor: an alias for `Reg`"] +#[doc = "SEQ2R (rw) register accessor: AFEC Channel Sequence 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq2r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq2r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`seq2r`] +module"] pub type SEQ2R = crate::Reg; #[doc = "AFEC Channel Sequence 2 Register"] pub mod seq2r; -#[doc = "CHER (w) register accessor: an alias for `Reg`"] +#[doc = "CHER (w) register accessor: AFEC Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cher::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cher`] +module"] pub type CHER = crate::Reg; #[doc = "AFEC Channel Enable Register"] pub mod cher; -#[doc = "CHDR (w) register accessor: an alias for `Reg`"] +#[doc = "CHDR (w) register accessor: AFEC Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`chdr`] +module"] pub type CHDR = crate::Reg; #[doc = "AFEC Channel Disable Register"] pub mod chdr; -#[doc = "CHSR (r) register accessor: an alias for `Reg`"] +#[doc = "CHSR (r) register accessor: AFEC Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`chsr`] +module"] pub type CHSR = crate::Reg; #[doc = "AFEC Channel Status Register"] pub mod chsr; -#[doc = "LCDR (r) register accessor: an alias for `Reg`"] +#[doc = "LCDR (r) register accessor: AFEC Last Converted Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lcdr`] +module"] pub type LCDR = crate::Reg; #[doc = "AFEC Last Converted Data Register"] pub mod lcdr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: AFEC Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "AFEC Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: AFEC Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "AFEC Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: AFEC Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "AFEC Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: AFEC Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "AFEC Interrupt Status Register"] pub mod isr; -#[doc = "OVER (r) register accessor: an alias for `Reg`"] +#[doc = "OVER (r) register accessor: AFEC Overrun Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`over::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`over`] +module"] pub type OVER = crate::Reg; #[doc = "AFEC Overrun Status Register"] pub mod over; -#[doc = "CWR (rw) register accessor: an alias for `Reg`"] +#[doc = "CWR (rw) register accessor: AFEC Compare Window Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cwr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cwr`] +module"] pub type CWR = crate::Reg; #[doc = "AFEC Compare Window Register"] pub mod cwr; -#[doc = "CGR (rw) register accessor: an alias for `Reg`"] +#[doc = "CGR (rw) register accessor: AFEC Channel Gain Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cgr`] +module"] pub type CGR = crate::Reg; #[doc = "AFEC Channel Gain Register"] pub mod cgr; -#[doc = "DIFFR (rw) register accessor: an alias for `Reg`"] +#[doc = "DIFFR (rw) register accessor: AFEC Channel Differential Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diffr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diffr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`diffr`] +module"] pub type DIFFR = crate::Reg; #[doc = "AFEC Channel Differential Register"] pub mod diffr; -#[doc = "CSELR (rw) register accessor: an alias for `Reg`"] +#[doc = "CSELR (rw) register accessor: AFEC Channel Selection Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cselr`] +module"] pub type CSELR = crate::Reg; #[doc = "AFEC Channel Selection Register"] pub mod cselr; -#[doc = "CDR (r) register accessor: an alias for `Reg`"] +#[doc = "CDR (r) register accessor: AFEC Channel Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cdr`] +module"] pub type CDR = crate::Reg; #[doc = "AFEC Channel Data Register"] pub mod cdr; -#[doc = "COCR (rw) register accessor: an alias for `Reg`"] +#[doc = "COCR (rw) register accessor: AFEC Channel Offset Compensation Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cocr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cocr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cocr`] +module"] pub type COCR = crate::Reg; #[doc = "AFEC Channel Offset Compensation Register"] pub mod cocr; -#[doc = "TEMPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "TEMPMR (rw) register accessor: AFEC Temperature Sensor Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tempmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tempmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tempmr`] +module"] pub type TEMPMR = crate::Reg; #[doc = "AFEC Temperature Sensor Mode Register"] pub mod tempmr; -#[doc = "TEMPCWR (rw) register accessor: an alias for `Reg`"] +#[doc = "TEMPCWR (rw) register accessor: AFEC Temperature Compare Window Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tempcwr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tempcwr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tempcwr`] +module"] pub type TEMPCWR = crate::Reg; #[doc = "AFEC Temperature Compare Window Register"] pub mod tempcwr; -#[doc = "ACR (rw) register accessor: an alias for `Reg`"] +#[doc = "ACR (rw) register accessor: AFEC Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`acr`] +module"] pub type ACR = crate::Reg; #[doc = "AFEC Analog Control Register"] pub mod acr; -#[doc = "SHMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SHMR (rw) register accessor: AFEC Sample & Hold Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`shmr`] +module"] pub type SHMR = crate::Reg; #[doc = "AFEC Sample & Hold Mode Register"] pub mod shmr; -#[doc = "COSR (rw) register accessor: an alias for `Reg`"] +#[doc = "COSR (rw) register accessor: AFEC Correction Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cosr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cosr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cosr`] +module"] pub type COSR = crate::Reg; #[doc = "AFEC Correction Select Register"] pub mod cosr; -#[doc = "CVR (rw) register accessor: an alias for `Reg`"] +#[doc = "CVR (rw) register accessor: AFEC Correction Values Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cvr`] +module"] pub type CVR = crate::Reg; #[doc = "AFEC Correction Values Register"] pub mod cvr; -#[doc = "CECR (rw) register accessor: an alias for `Reg`"] +#[doc = "CECR (rw) register accessor: AFEC Channel Error Correction Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cecr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cecr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cecr`] +module"] pub type CECR = crate::Reg; #[doc = "AFEC Channel Error Correction Register"] pub mod cecr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: AFEC Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "AFEC Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: AFEC Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "AFEC Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/acr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/acr.rs index 89e3f75f..465542d8 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/acr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/acr.rs @@ -1,51 +1,19 @@ #[doc = "Register `ACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PGA0EN` reader - PGA0 Enable"] pub type PGA0EN_R = crate::BitReader; #[doc = "Field `PGA0EN` writer - PGA0 Enable"] -pub type PGA0EN_W<'a, const O: u8> = crate::BitWriter<'a, ACR_SPEC, O>; +pub type PGA0EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PGA1EN` reader - PGA1 Enable"] pub type PGA1EN_R = crate::BitReader; #[doc = "Field `PGA1EN` writer - PGA1 Enable"] -pub type PGA1EN_W<'a, const O: u8> = crate::BitWriter<'a, ACR_SPEC, O>; +pub type PGA1EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IBCTL` reader - AFE Bias Current Control"] pub type IBCTL_R = crate::FieldReader; #[doc = "Field `IBCTL` writer - AFE Bias Current Control"] -pub type IBCTL_W<'a, const O: u8> = crate::FieldWriter<'a, ACR_SPEC, 2, O>; +pub type IBCTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bit 2 - PGA0 Enable"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bit 2 - PGA0 Enable"] #[inline(always)] #[must_use] - pub fn pga0en(&mut self) -> PGA0EN_W<2> { + pub fn pga0en(&mut self) -> PGA0EN_W { PGA0EN_W::new(self) } #[doc = "Bit 3 - PGA1 Enable"] #[inline(always)] #[must_use] - pub fn pga1en(&mut self) -> PGA1EN_W<3> { + pub fn pga1en(&mut self) -> PGA1EN_W { PGA1EN_W::new(self) } #[doc = "Bits 8:9 - AFE Bias Current Control"] #[inline(always)] #[must_use] - pub fn ibctl(&mut self) -> IBCTL_W<8> { + pub fn ibctl(&mut self) -> IBCTL_W { IBCTL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Analog Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acr](index.html) module"] +#[doc = "AFEC Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACR_SPEC; impl crate::RegisterSpec for ACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [acr::R](R) reader structure"] -impl crate::Readable for ACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [acr::W](W) writer structure"] +#[doc = "`read()` method returns [`acr::R`](R) reader structure"] +impl crate::Readable for ACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`acr::W`](W) writer structure"] impl crate::Writable for ACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cdr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cdr.rs index 3e694946..182c3134 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cdr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATA` reader - Converted Data"] pub type DATA_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { DATA_R::new((self.bits & 0xffff) as u16) } } -#[doc = "AFEC Channel Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cdr](index.html) module"] +#[doc = "AFEC Channel Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDR_SPEC; impl crate::RegisterSpec for CDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cdr::R](R) reader structure"] -impl crate::Readable for CDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cdr::R`](R) reader structure"] +impl crate::Readable for CDR_SPEC {} #[doc = "`reset()` method sets CDR to value 0"] impl crate::Resettable for CDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cecr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cecr.rs index 643bd394..2e3dd3c7 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cecr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cecr.rs @@ -1,87 +1,55 @@ #[doc = "Register `CECR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CECR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ECORR0` reader - Error Correction Enable for channel 0"] pub type ECORR0_R = crate::BitReader; #[doc = "Field `ECORR0` writer - Error Correction Enable for channel 0"] -pub type ECORR0_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR1` reader - Error Correction Enable for channel 1"] pub type ECORR1_R = crate::BitReader; #[doc = "Field `ECORR1` writer - Error Correction Enable for channel 1"] -pub type ECORR1_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR2` reader - Error Correction Enable for channel 2"] pub type ECORR2_R = crate::BitReader; #[doc = "Field `ECORR2` writer - Error Correction Enable for channel 2"] -pub type ECORR2_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR3` reader - Error Correction Enable for channel 3"] pub type ECORR3_R = crate::BitReader; #[doc = "Field `ECORR3` writer - Error Correction Enable for channel 3"] -pub type ECORR3_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR4` reader - Error Correction Enable for channel 4"] pub type ECORR4_R = crate::BitReader; #[doc = "Field `ECORR4` writer - Error Correction Enable for channel 4"] -pub type ECORR4_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR5` reader - Error Correction Enable for channel 5"] pub type ECORR5_R = crate::BitReader; #[doc = "Field `ECORR5` writer - Error Correction Enable for channel 5"] -pub type ECORR5_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR6` reader - Error Correction Enable for channel 6"] pub type ECORR6_R = crate::BitReader; #[doc = "Field `ECORR6` writer - Error Correction Enable for channel 6"] -pub type ECORR6_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR7` reader - Error Correction Enable for channel 7"] pub type ECORR7_R = crate::BitReader; #[doc = "Field `ECORR7` writer - Error Correction Enable for channel 7"] -pub type ECORR7_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR8` reader - Error Correction Enable for channel 8"] pub type ECORR8_R = crate::BitReader; #[doc = "Field `ECORR8` writer - Error Correction Enable for channel 8"] -pub type ECORR8_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR9` reader - Error Correction Enable for channel 9"] pub type ECORR9_R = crate::BitReader; #[doc = "Field `ECORR9` writer - Error Correction Enable for channel 9"] -pub type ECORR9_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR10` reader - Error Correction Enable for channel 10"] pub type ECORR10_R = crate::BitReader; #[doc = "Field `ECORR10` writer - Error Correction Enable for channel 10"] -pub type ECORR10_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ECORR11` reader - Error Correction Enable for channel 11"] pub type ECORR11_R = crate::BitReader; #[doc = "Field `ECORR11` writer - Error Correction Enable for channel 11"] -pub type ECORR11_W<'a, const O: u8> = crate::BitWriter<'a, CECR_SPEC, O>; +pub type ECORR11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Error Correction Enable for channel 0"] #[inline(always)] @@ -148,94 +116,91 @@ impl W { #[doc = "Bit 0 - Error Correction Enable for channel 0"] #[inline(always)] #[must_use] - pub fn ecorr0(&mut self) -> ECORR0_W<0> { + pub fn ecorr0(&mut self) -> ECORR0_W { ECORR0_W::new(self) } #[doc = "Bit 1 - Error Correction Enable for channel 1"] #[inline(always)] #[must_use] - pub fn ecorr1(&mut self) -> ECORR1_W<1> { + pub fn ecorr1(&mut self) -> ECORR1_W { ECORR1_W::new(self) } #[doc = "Bit 2 - Error Correction Enable for channel 2"] #[inline(always)] #[must_use] - pub fn ecorr2(&mut self) -> ECORR2_W<2> { + pub fn ecorr2(&mut self) -> ECORR2_W { ECORR2_W::new(self) } #[doc = "Bit 3 - Error Correction Enable for channel 3"] #[inline(always)] #[must_use] - pub fn ecorr3(&mut self) -> ECORR3_W<3> { + pub fn ecorr3(&mut self) -> ECORR3_W { ECORR3_W::new(self) } #[doc = "Bit 4 - Error Correction Enable for channel 4"] #[inline(always)] #[must_use] - pub fn ecorr4(&mut self) -> ECORR4_W<4> { + pub fn ecorr4(&mut self) -> ECORR4_W { ECORR4_W::new(self) } #[doc = "Bit 5 - Error Correction Enable for channel 5"] #[inline(always)] #[must_use] - pub fn ecorr5(&mut self) -> ECORR5_W<5> { + pub fn ecorr5(&mut self) -> ECORR5_W { ECORR5_W::new(self) } #[doc = "Bit 6 - Error Correction Enable for channel 6"] #[inline(always)] #[must_use] - pub fn ecorr6(&mut self) -> ECORR6_W<6> { + pub fn ecorr6(&mut self) -> ECORR6_W { ECORR6_W::new(self) } #[doc = "Bit 7 - Error Correction Enable for channel 7"] #[inline(always)] #[must_use] - pub fn ecorr7(&mut self) -> ECORR7_W<7> { + pub fn ecorr7(&mut self) -> ECORR7_W { ECORR7_W::new(self) } #[doc = "Bit 8 - Error Correction Enable for channel 8"] #[inline(always)] #[must_use] - pub fn ecorr8(&mut self) -> ECORR8_W<8> { + pub fn ecorr8(&mut self) -> ECORR8_W { ECORR8_W::new(self) } #[doc = "Bit 9 - Error Correction Enable for channel 9"] #[inline(always)] #[must_use] - pub fn ecorr9(&mut self) -> ECORR9_W<9> { + pub fn ecorr9(&mut self) -> ECORR9_W { ECORR9_W::new(self) } #[doc = "Bit 10 - Error Correction Enable for channel 10"] #[inline(always)] #[must_use] - pub fn ecorr10(&mut self) -> ECORR10_W<10> { + pub fn ecorr10(&mut self) -> ECORR10_W { ECORR10_W::new(self) } #[doc = "Bit 11 - Error Correction Enable for channel 11"] #[inline(always)] #[must_use] - pub fn ecorr11(&mut self) -> ECORR11_W<11> { + pub fn ecorr11(&mut self) -> ECORR11_W { ECORR11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Error Correction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cecr](index.html) module"] +#[doc = "AFEC Channel Error Correction Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cecr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cecr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CECR_SPEC; impl crate::RegisterSpec for CECR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cecr::R](R) reader structure"] -impl crate::Readable for CECR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cecr::W](W) writer structure"] +#[doc = "`read()` method returns [`cecr::R`](R) reader structure"] +impl crate::Readable for CECR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cecr::W`](W) writer structure"] impl crate::Writable for CECR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cgr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cgr.rs index 5621417c..e3509e84 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cgr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cgr.rs @@ -1,87 +1,55 @@ #[doc = "Register `CGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GAIN0` reader - Gain for Channel 0"] pub type GAIN0_R = crate::FieldReader; #[doc = "Field `GAIN0` writer - Gain for Channel 0"] -pub type GAIN0_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN1` reader - Gain for Channel 1"] pub type GAIN1_R = crate::FieldReader; #[doc = "Field `GAIN1` writer - Gain for Channel 1"] -pub type GAIN1_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN2` reader - Gain for Channel 2"] pub type GAIN2_R = crate::FieldReader; #[doc = "Field `GAIN2` writer - Gain for Channel 2"] -pub type GAIN2_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN3` reader - Gain for Channel 3"] pub type GAIN3_R = crate::FieldReader; #[doc = "Field `GAIN3` writer - Gain for Channel 3"] -pub type GAIN3_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN4` reader - Gain for Channel 4"] pub type GAIN4_R = crate::FieldReader; #[doc = "Field `GAIN4` writer - Gain for Channel 4"] -pub type GAIN4_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN5` reader - Gain for Channel 5"] pub type GAIN5_R = crate::FieldReader; #[doc = "Field `GAIN5` writer - Gain for Channel 5"] -pub type GAIN5_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN6` reader - Gain for Channel 6"] pub type GAIN6_R = crate::FieldReader; #[doc = "Field `GAIN6` writer - Gain for Channel 6"] -pub type GAIN6_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN7` reader - Gain for Channel 7"] pub type GAIN7_R = crate::FieldReader; #[doc = "Field `GAIN7` writer - Gain for Channel 7"] -pub type GAIN7_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN8` reader - Gain for Channel 8"] pub type GAIN8_R = crate::FieldReader; #[doc = "Field `GAIN8` writer - Gain for Channel 8"] -pub type GAIN8_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN9` reader - Gain for Channel 9"] pub type GAIN9_R = crate::FieldReader; #[doc = "Field `GAIN9` writer - Gain for Channel 9"] -pub type GAIN9_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN9_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN10` reader - Gain for Channel 10"] pub type GAIN10_R = crate::FieldReader; #[doc = "Field `GAIN10` writer - Gain for Channel 10"] -pub type GAIN10_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `GAIN11` reader - Gain for Channel 11"] pub type GAIN11_R = crate::FieldReader; #[doc = "Field `GAIN11` writer - Gain for Channel 11"] -pub type GAIN11_W<'a, const O: u8> = crate::FieldWriter<'a, CGR_SPEC, 2, O>; +pub type GAIN11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Gain for Channel 0"] #[inline(always)] @@ -148,94 +116,91 @@ impl W { #[doc = "Bits 0:1 - Gain for Channel 0"] #[inline(always)] #[must_use] - pub fn gain0(&mut self) -> GAIN0_W<0> { + pub fn gain0(&mut self) -> GAIN0_W { GAIN0_W::new(self) } #[doc = "Bits 2:3 - Gain for Channel 1"] #[inline(always)] #[must_use] - pub fn gain1(&mut self) -> GAIN1_W<2> { + pub fn gain1(&mut self) -> GAIN1_W { GAIN1_W::new(self) } #[doc = "Bits 4:5 - Gain for Channel 2"] #[inline(always)] #[must_use] - pub fn gain2(&mut self) -> GAIN2_W<4> { + pub fn gain2(&mut self) -> GAIN2_W { GAIN2_W::new(self) } #[doc = "Bits 6:7 - Gain for Channel 3"] #[inline(always)] #[must_use] - pub fn gain3(&mut self) -> GAIN3_W<6> { + pub fn gain3(&mut self) -> GAIN3_W { GAIN3_W::new(self) } #[doc = "Bits 8:9 - Gain for Channel 4"] #[inline(always)] #[must_use] - pub fn gain4(&mut self) -> GAIN4_W<8> { + pub fn gain4(&mut self) -> GAIN4_W { GAIN4_W::new(self) } #[doc = "Bits 10:11 - Gain for Channel 5"] #[inline(always)] #[must_use] - pub fn gain5(&mut self) -> GAIN5_W<10> { + pub fn gain5(&mut self) -> GAIN5_W { GAIN5_W::new(self) } #[doc = "Bits 12:13 - Gain for Channel 6"] #[inline(always)] #[must_use] - pub fn gain6(&mut self) -> GAIN6_W<12> { + pub fn gain6(&mut self) -> GAIN6_W { GAIN6_W::new(self) } #[doc = "Bits 14:15 - Gain for Channel 7"] #[inline(always)] #[must_use] - pub fn gain7(&mut self) -> GAIN7_W<14> { + pub fn gain7(&mut self) -> GAIN7_W { GAIN7_W::new(self) } #[doc = "Bits 16:17 - Gain for Channel 8"] #[inline(always)] #[must_use] - pub fn gain8(&mut self) -> GAIN8_W<16> { + pub fn gain8(&mut self) -> GAIN8_W { GAIN8_W::new(self) } #[doc = "Bits 18:19 - Gain for Channel 9"] #[inline(always)] #[must_use] - pub fn gain9(&mut self) -> GAIN9_W<18> { + pub fn gain9(&mut self) -> GAIN9_W { GAIN9_W::new(self) } #[doc = "Bits 20:21 - Gain for Channel 10"] #[inline(always)] #[must_use] - pub fn gain10(&mut self) -> GAIN10_W<20> { + pub fn gain10(&mut self) -> GAIN10_W { GAIN10_W::new(self) } #[doc = "Bits 22:23 - Gain for Channel 11"] #[inline(always)] #[must_use] - pub fn gain11(&mut self) -> GAIN11_W<22> { + pub fn gain11(&mut self) -> GAIN11_W { GAIN11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Gain Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cgr](index.html) module"] +#[doc = "AFEC Channel Gain Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CGR_SPEC; impl crate::RegisterSpec for CGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cgr::R](R) reader structure"] -impl crate::Readable for CGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cgr::W](W) writer structure"] +#[doc = "`read()` method returns [`cgr::R`](R) reader structure"] +impl crate::Readable for CGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cgr::W`](W) writer structure"] impl crate::Writable for CGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/chdr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/chdr.rs index 21a9f15d..1a67dcd6 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/chdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/chdr.rs @@ -1,136 +1,116 @@ #[doc = "Register `CHDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` writer - Channel 0 Disable"] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` writer - Channel 1 Disable"] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH2` writer - Channel 2 Disable"] -pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH3` writer - Channel 3 Disable"] -pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH4` writer - Channel 4 Disable"] -pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH5` writer - Channel 5 Disable"] -pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH6` writer - Channel 6 Disable"] -pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH7` writer - Channel 7 Disable"] -pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH8` writer - Channel 8 Disable"] -pub type CH8_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH9` writer - Channel 9 Disable"] -pub type CH9_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH10` writer - Channel 10 Disable"] -pub type CH10_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH11` writer - Channel 11 Disable"] -pub type CH11_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Channel 0 Disable"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1 - Channel 1 Disable"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Bit 2 - Channel 2 Disable"] #[inline(always)] #[must_use] - pub fn ch2(&mut self) -> CH2_W<2> { + pub fn ch2(&mut self) -> CH2_W { CH2_W::new(self) } #[doc = "Bit 3 - Channel 3 Disable"] #[inline(always)] #[must_use] - pub fn ch3(&mut self) -> CH3_W<3> { + pub fn ch3(&mut self) -> CH3_W { CH3_W::new(self) } #[doc = "Bit 4 - Channel 4 Disable"] #[inline(always)] #[must_use] - pub fn ch4(&mut self) -> CH4_W<4> { + pub fn ch4(&mut self) -> CH4_W { CH4_W::new(self) } #[doc = "Bit 5 - Channel 5 Disable"] #[inline(always)] #[must_use] - pub fn ch5(&mut self) -> CH5_W<5> { + pub fn ch5(&mut self) -> CH5_W { CH5_W::new(self) } #[doc = "Bit 6 - Channel 6 Disable"] #[inline(always)] #[must_use] - pub fn ch6(&mut self) -> CH6_W<6> { + pub fn ch6(&mut self) -> CH6_W { CH6_W::new(self) } #[doc = "Bit 7 - Channel 7 Disable"] #[inline(always)] #[must_use] - pub fn ch7(&mut self) -> CH7_W<7> { + pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self) } #[doc = "Bit 8 - Channel 8 Disable"] #[inline(always)] #[must_use] - pub fn ch8(&mut self) -> CH8_W<8> { + pub fn ch8(&mut self) -> CH8_W { CH8_W::new(self) } #[doc = "Bit 9 - Channel 9 Disable"] #[inline(always)] #[must_use] - pub fn ch9(&mut self) -> CH9_W<9> { + pub fn ch9(&mut self) -> CH9_W { CH9_W::new(self) } #[doc = "Bit 10 - Channel 10 Disable"] #[inline(always)] #[must_use] - pub fn ch10(&mut self) -> CH10_W<10> { + pub fn ch10(&mut self) -> CH10_W { CH10_W::new(self) } #[doc = "Bit 11 - Channel 11 Disable"] #[inline(always)] #[must_use] - pub fn ch11(&mut self) -> CH11_W<11> { + pub fn ch11(&mut self) -> CH11_W { CH11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chdr](index.html) module"] +#[doc = "AFEC Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHDR_SPEC; impl crate::RegisterSpec for CHDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [chdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`chdr::W`](W) writer structure"] impl crate::Writable for CHDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cher.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cher.rs index 4640d982..cf16edf2 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cher.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cher.rs @@ -1,136 +1,116 @@ #[doc = "Register `CHER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` writer - Channel 0 Enable"] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` writer - Channel 1 Enable"] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH2` writer - Channel 2 Enable"] -pub type CH2_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH3` writer - Channel 3 Enable"] -pub type CH3_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH4` writer - Channel 4 Enable"] -pub type CH4_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH5` writer - Channel 5 Enable"] -pub type CH5_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH6` writer - Channel 6 Enable"] -pub type CH6_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH7` writer - Channel 7 Enable"] -pub type CH7_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH8` writer - Channel 8 Enable"] -pub type CH8_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH9` writer - Channel 9 Enable"] -pub type CH9_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH10` writer - Channel 10 Enable"] -pub type CH10_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH11` writer - Channel 11 Enable"] -pub type CH11_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Channel 0 Enable"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1 - Channel 1 Enable"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Bit 2 - Channel 2 Enable"] #[inline(always)] #[must_use] - pub fn ch2(&mut self) -> CH2_W<2> { + pub fn ch2(&mut self) -> CH2_W { CH2_W::new(self) } #[doc = "Bit 3 - Channel 3 Enable"] #[inline(always)] #[must_use] - pub fn ch3(&mut self) -> CH3_W<3> { + pub fn ch3(&mut self) -> CH3_W { CH3_W::new(self) } #[doc = "Bit 4 - Channel 4 Enable"] #[inline(always)] #[must_use] - pub fn ch4(&mut self) -> CH4_W<4> { + pub fn ch4(&mut self) -> CH4_W { CH4_W::new(self) } #[doc = "Bit 5 - Channel 5 Enable"] #[inline(always)] #[must_use] - pub fn ch5(&mut self) -> CH5_W<5> { + pub fn ch5(&mut self) -> CH5_W { CH5_W::new(self) } #[doc = "Bit 6 - Channel 6 Enable"] #[inline(always)] #[must_use] - pub fn ch6(&mut self) -> CH6_W<6> { + pub fn ch6(&mut self) -> CH6_W { CH6_W::new(self) } #[doc = "Bit 7 - Channel 7 Enable"] #[inline(always)] #[must_use] - pub fn ch7(&mut self) -> CH7_W<7> { + pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self) } #[doc = "Bit 8 - Channel 8 Enable"] #[inline(always)] #[must_use] - pub fn ch8(&mut self) -> CH8_W<8> { + pub fn ch8(&mut self) -> CH8_W { CH8_W::new(self) } #[doc = "Bit 9 - Channel 9 Enable"] #[inline(always)] #[must_use] - pub fn ch9(&mut self) -> CH9_W<9> { + pub fn ch9(&mut self) -> CH9_W { CH9_W::new(self) } #[doc = "Bit 10 - Channel 10 Enable"] #[inline(always)] #[must_use] - pub fn ch10(&mut self) -> CH10_W<10> { + pub fn ch10(&mut self) -> CH10_W { CH10_W::new(self) } #[doc = "Bit 11 - Channel 11 Enable"] #[inline(always)] #[must_use] - pub fn ch11(&mut self) -> CH11_W<11> { + pub fn ch11(&mut self) -> CH11_W { CH11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cher](index.html) module"] +#[doc = "AFEC Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cher::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHER_SPEC; impl crate::RegisterSpec for CHER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cher::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cher::W`](W) writer structure"] impl crate::Writable for CHER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/chsr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/chsr.rs index 302c7427..5dbb7bd8 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/chsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/chsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CHSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CH0` reader - Channel 0 Status"] pub type CH0_R = crate::BitReader; #[doc = "Field `CH1` reader - Channel 1 Status"] @@ -99,15 +86,13 @@ impl R { CH11_R::new(((self.bits >> 11) & 1) != 0) } } -#[doc = "AFEC Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chsr](index.html) module"] +#[doc = "AFEC Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHSR_SPEC; impl crate::RegisterSpec for CHSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chsr::R](R) reader structure"] -impl crate::Readable for CHSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`chsr::R`](R) reader structure"] +impl crate::Readable for CHSR_SPEC {} #[doc = "`reset()` method sets CHSR to value 0"] impl crate::Resettable for CHSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cocr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cocr.rs index 3ac8632c..1e01291e 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cocr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cocr.rs @@ -1,43 +1,11 @@ #[doc = "Register `COCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `COCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AOFF` reader - Analog Offset"] pub type AOFF_R = crate::FieldReader; #[doc = "Field `AOFF` writer - Analog Offset"] -pub type AOFF_W<'a, const O: u8> = crate::FieldWriter<'a, COCR_SPEC, 10, O, u16>; +pub type AOFF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; impl R { #[doc = "Bits 0:9 - Analog Offset"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:9 - Analog Offset"] #[inline(always)] #[must_use] - pub fn aoff(&mut self) -> AOFF_W<0> { + pub fn aoff(&mut self) -> AOFF_W { AOFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Offset Compensation Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cocr](index.html) module"] +#[doc = "AFEC Channel Offset Compensation Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cocr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cocr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct COCR_SPEC; impl crate::RegisterSpec for COCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cocr::R](R) reader structure"] -impl crate::Readable for COCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cocr::W](W) writer structure"] +#[doc = "`read()` method returns [`cocr::R`](R) reader structure"] +impl crate::Readable for COCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cocr::W`](W) writer structure"] impl crate::Writable for COCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cosr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cosr.rs index 126a15c2..416fb8b9 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cosr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cosr.rs @@ -1,43 +1,11 @@ #[doc = "Register `COSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `COSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSEL` reader - Sample & Hold unit Correction Select"] pub type CSEL_R = crate::BitReader; #[doc = "Field `CSEL` writer - Sample & Hold unit Correction Select"] -pub type CSEL_W<'a, const O: u8> = crate::BitWriter<'a, COSR_SPEC, O>; +pub type CSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Sample & Hold unit Correction Select"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bit 0 - Sample & Hold unit Correction Select"] #[inline(always)] #[must_use] - pub fn csel(&mut self) -> CSEL_W<0> { + pub fn csel(&mut self) -> CSEL_W { CSEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Correction Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cosr](index.html) module"] +#[doc = "AFEC Correction Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cosr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cosr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct COSR_SPEC; impl crate::RegisterSpec for COSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cosr::R](R) reader structure"] -impl crate::Readable for COSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cosr::W](W) writer structure"] +#[doc = "`read()` method returns [`cosr::R`](R) reader structure"] +impl crate::Readable for COSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cosr::W`](W) writer structure"] impl crate::Writable for COSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cr.rs index 1436b9ee..5ccda09d 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cr.rs @@ -1,56 +1,36 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `START` writer - Start Conversion"] -pub type START_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<0> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Bit 1 - Start Conversion"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W<1> { + pub fn start(&mut self) -> START_W { START_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "AFEC Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cselr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cselr.rs index d34dea56..8aba8682 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cselr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cselr.rs @@ -1,43 +1,11 @@ #[doc = "Register `CSELR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSELR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSEL` reader - Channel Selection"] pub type CSEL_R = crate::FieldReader; #[doc = "Field `CSEL` writer - Channel Selection"] -pub type CSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CSELR_SPEC, 4, O>; +pub type CSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Channel Selection"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:3 - Channel Selection"] #[inline(always)] #[must_use] - pub fn csel(&mut self) -> CSEL_W<0> { + pub fn csel(&mut self) -> CSEL_W { CSEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Selection Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cselr](index.html) module"] +#[doc = "AFEC Channel Selection Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cselr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cselr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSELR_SPEC; impl crate::RegisterSpec for CSELR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cselr::R](R) reader structure"] -impl crate::Readable for CSELR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cselr::W](W) writer structure"] +#[doc = "`read()` method returns [`cselr::R`](R) reader structure"] +impl crate::Readable for CSELR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cselr::W`](W) writer structure"] impl crate::Writable for CSELR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cvr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cvr.rs index 3fb3b7e1..c08533e2 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cvr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cvr.rs @@ -1,47 +1,15 @@ #[doc = "Register `CVR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CVR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OFFSETCORR` reader - Offset Correction"] pub type OFFSETCORR_R = crate::FieldReader; #[doc = "Field `OFFSETCORR` writer - Offset Correction"] -pub type OFFSETCORR_W<'a, const O: u8> = crate::FieldWriter<'a, CVR_SPEC, 16, O, u16>; +pub type OFFSETCORR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `GAINCORR` reader - Gain Correction"] pub type GAINCORR_R = crate::FieldReader; #[doc = "Field `GAINCORR` writer - Gain Correction"] -pub type GAINCORR_W<'a, const O: u8> = crate::FieldWriter<'a, CVR_SPEC, 16, O, u16>; +pub type GAINCORR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Offset Correction"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Offset Correction"] #[inline(always)] #[must_use] - pub fn offsetcorr(&mut self) -> OFFSETCORR_W<0> { + pub fn offsetcorr(&mut self) -> OFFSETCORR_W { OFFSETCORR_W::new(self) } #[doc = "Bits 16:31 - Gain Correction"] #[inline(always)] #[must_use] - pub fn gaincorr(&mut self) -> GAINCORR_W<16> { + pub fn gaincorr(&mut self) -> GAINCORR_W { GAINCORR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Correction Values Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +#[doc = "AFEC Correction Values Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cvr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CVR_SPEC; impl crate::RegisterSpec for CVR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cvr::R](R) reader structure"] -impl crate::Readable for CVR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +#[doc = "`read()` method returns [`cvr::R`](R) reader structure"] +impl crate::Readable for CVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cvr::W`](W) writer structure"] impl crate::Writable for CVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/cwr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/cwr.rs index 642b57fd..e335852c 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/cwr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/cwr.rs @@ -1,47 +1,15 @@ #[doc = "Register `CWR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CWR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOWTHRES` reader - Low Threshold"] pub type LOWTHRES_R = crate::FieldReader; #[doc = "Field `LOWTHRES` writer - Low Threshold"] -pub type LOWTHRES_W<'a, const O: u8> = crate::FieldWriter<'a, CWR_SPEC, 16, O, u16>; +pub type LOWTHRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `HIGHTHRES` reader - High Threshold"] pub type HIGHTHRES_R = crate::FieldReader; #[doc = "Field `HIGHTHRES` writer - High Threshold"] -pub type HIGHTHRES_W<'a, const O: u8> = crate::FieldWriter<'a, CWR_SPEC, 16, O, u16>; +pub type HIGHTHRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Low Threshold"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Low Threshold"] #[inline(always)] #[must_use] - pub fn lowthres(&mut self) -> LOWTHRES_W<0> { + pub fn lowthres(&mut self) -> LOWTHRES_W { LOWTHRES_W::new(self) } #[doc = "Bits 16:31 - High Threshold"] #[inline(always)] #[must_use] - pub fn highthres(&mut self) -> HIGHTHRES_W<16> { + pub fn highthres(&mut self) -> HIGHTHRES_W { HIGHTHRES_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Compare Window Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cwr](index.html) module"] +#[doc = "AFEC Compare Window Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cwr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CWR_SPEC; impl crate::RegisterSpec for CWR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cwr::R](R) reader structure"] -impl crate::Readable for CWR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cwr::W](W) writer structure"] +#[doc = "`read()` method returns [`cwr::R`](R) reader structure"] +impl crate::Readable for CWR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cwr::W`](W) writer structure"] impl crate::Writable for CWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/diffr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/diffr.rs index f982e707..318c20bc 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/diffr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/diffr.rs @@ -1,87 +1,55 @@ #[doc = "Register `DIFFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DIFFR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIFF0` reader - Differential inputs for channel 0"] pub type DIFF0_R = crate::BitReader; #[doc = "Field `DIFF0` writer - Differential inputs for channel 0"] -pub type DIFF0_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF1` reader - Differential inputs for channel 1"] pub type DIFF1_R = crate::BitReader; #[doc = "Field `DIFF1` writer - Differential inputs for channel 1"] -pub type DIFF1_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF2` reader - Differential inputs for channel 2"] pub type DIFF2_R = crate::BitReader; #[doc = "Field `DIFF2` writer - Differential inputs for channel 2"] -pub type DIFF2_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF3` reader - Differential inputs for channel 3"] pub type DIFF3_R = crate::BitReader; #[doc = "Field `DIFF3` writer - Differential inputs for channel 3"] -pub type DIFF3_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF4` reader - Differential inputs for channel 4"] pub type DIFF4_R = crate::BitReader; #[doc = "Field `DIFF4` writer - Differential inputs for channel 4"] -pub type DIFF4_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF5` reader - Differential inputs for channel 5"] pub type DIFF5_R = crate::BitReader; #[doc = "Field `DIFF5` writer - Differential inputs for channel 5"] -pub type DIFF5_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF6` reader - Differential inputs for channel 6"] pub type DIFF6_R = crate::BitReader; #[doc = "Field `DIFF6` writer - Differential inputs for channel 6"] -pub type DIFF6_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF7` reader - Differential inputs for channel 7"] pub type DIFF7_R = crate::BitReader; #[doc = "Field `DIFF7` writer - Differential inputs for channel 7"] -pub type DIFF7_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF8` reader - Differential inputs for channel 8"] pub type DIFF8_R = crate::BitReader; #[doc = "Field `DIFF8` writer - Differential inputs for channel 8"] -pub type DIFF8_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF9` reader - Differential inputs for channel 9"] pub type DIFF9_R = crate::BitReader; #[doc = "Field `DIFF9` writer - Differential inputs for channel 9"] -pub type DIFF9_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF10` reader - Differential inputs for channel 10"] pub type DIFF10_R = crate::BitReader; #[doc = "Field `DIFF10` writer - Differential inputs for channel 10"] -pub type DIFF10_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF11` reader - Differential inputs for channel 11"] pub type DIFF11_R = crate::BitReader; #[doc = "Field `DIFF11` writer - Differential inputs for channel 11"] -pub type DIFF11_W<'a, const O: u8> = crate::BitWriter<'a, DIFFR_SPEC, O>; +pub type DIFF11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Differential inputs for channel 0"] #[inline(always)] @@ -148,94 +116,91 @@ impl W { #[doc = "Bit 0 - Differential inputs for channel 0"] #[inline(always)] #[must_use] - pub fn diff0(&mut self) -> DIFF0_W<0> { + pub fn diff0(&mut self) -> DIFF0_W { DIFF0_W::new(self) } #[doc = "Bit 1 - Differential inputs for channel 1"] #[inline(always)] #[must_use] - pub fn diff1(&mut self) -> DIFF1_W<1> { + pub fn diff1(&mut self) -> DIFF1_W { DIFF1_W::new(self) } #[doc = "Bit 2 - Differential inputs for channel 2"] #[inline(always)] #[must_use] - pub fn diff2(&mut self) -> DIFF2_W<2> { + pub fn diff2(&mut self) -> DIFF2_W { DIFF2_W::new(self) } #[doc = "Bit 3 - Differential inputs for channel 3"] #[inline(always)] #[must_use] - pub fn diff3(&mut self) -> DIFF3_W<3> { + pub fn diff3(&mut self) -> DIFF3_W { DIFF3_W::new(self) } #[doc = "Bit 4 - Differential inputs for channel 4"] #[inline(always)] #[must_use] - pub fn diff4(&mut self) -> DIFF4_W<4> { + pub fn diff4(&mut self) -> DIFF4_W { DIFF4_W::new(self) } #[doc = "Bit 5 - Differential inputs for channel 5"] #[inline(always)] #[must_use] - pub fn diff5(&mut self) -> DIFF5_W<5> { + pub fn diff5(&mut self) -> DIFF5_W { DIFF5_W::new(self) } #[doc = "Bit 6 - Differential inputs for channel 6"] #[inline(always)] #[must_use] - pub fn diff6(&mut self) -> DIFF6_W<6> { + pub fn diff6(&mut self) -> DIFF6_W { DIFF6_W::new(self) } #[doc = "Bit 7 - Differential inputs for channel 7"] #[inline(always)] #[must_use] - pub fn diff7(&mut self) -> DIFF7_W<7> { + pub fn diff7(&mut self) -> DIFF7_W { DIFF7_W::new(self) } #[doc = "Bit 8 - Differential inputs for channel 8"] #[inline(always)] #[must_use] - pub fn diff8(&mut self) -> DIFF8_W<8> { + pub fn diff8(&mut self) -> DIFF8_W { DIFF8_W::new(self) } #[doc = "Bit 9 - Differential inputs for channel 9"] #[inline(always)] #[must_use] - pub fn diff9(&mut self) -> DIFF9_W<9> { + pub fn diff9(&mut self) -> DIFF9_W { DIFF9_W::new(self) } #[doc = "Bit 10 - Differential inputs for channel 10"] #[inline(always)] #[must_use] - pub fn diff10(&mut self) -> DIFF10_W<10> { + pub fn diff10(&mut self) -> DIFF10_W { DIFF10_W::new(self) } #[doc = "Bit 11 - Differential inputs for channel 11"] #[inline(always)] #[must_use] - pub fn diff11(&mut self) -> DIFF11_W<11> { + pub fn diff11(&mut self) -> DIFF11_W { DIFF11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Differential Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diffr](index.html) module"] +#[doc = "AFEC Channel Differential Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`diffr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`diffr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIFFR_SPEC; impl crate::RegisterSpec for DIFFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [diffr::R](R) reader structure"] -impl crate::Readable for DIFFR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [diffr::W](W) writer structure"] +#[doc = "`read()` method returns [`diffr::R`](R) reader structure"] +impl crate::Readable for DIFFR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`diffr::W`](W) writer structure"] impl crate::Writable for DIFFR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/emr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/emr.rs index 5560d9ea..cb63f27d 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/emr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/emr.rs @@ -1,39 +1,7 @@ #[doc = "Register `EMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMPMODE` reader - Comparison Mode"] pub type CMPMODE_R = crate::FieldReader; #[doc = "Comparison Mode\n\nValue on reset: 0"] @@ -70,63 +38,67 @@ impl CMPMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Generates an event when the converted data is lower than the low threshold of the window."] #[inline(always)] pub fn is_low(&self) -> bool { *self == CMPMODESELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Generates an event when the converted data is higher than the high threshold of the window."] #[inline(always)] pub fn is_high(&self) -> bool { *self == CMPMODESELECT_A::HIGH } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "Generates an event when the converted data is in the comparison window."] #[inline(always)] pub fn is_in(&self) -> bool { *self == CMPMODESELECT_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "Generates an event when the converted data is out of the comparison window."] #[inline(always)] pub fn is_out(&self) -> bool { *self == CMPMODESELECT_A::OUT } } #[doc = "Field `CMPMODE` writer - Comparison Mode"] -pub type CMPMODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, EMR_SPEC, 2, O, CMPMODESELECT_A>; -impl<'a, const O: u8> CMPMODE_W<'a, O> { +pub type CMPMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CMPMODESELECT_A>; +impl<'a, REG, const O: u8> CMPMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Generates an event when the converted data is lower than the low threshold of the window."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(CMPMODESELECT_A::LOW) } #[doc = "Generates an event when the converted data is higher than the high threshold of the window."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(CMPMODESELECT_A::HIGH) } #[doc = "Generates an event when the converted data is in the comparison window."] #[inline(always)] - pub fn in_(self) -> &'a mut W { + pub fn in_(self) -> &'a mut crate::W { self.variant(CMPMODESELECT_A::IN) } #[doc = "Generates an event when the converted data is out of the comparison window."] #[inline(always)] - pub fn out(self) -> &'a mut W { + pub fn out(self) -> &'a mut crate::W { self.variant(CMPMODESELECT_A::OUT) } } #[doc = "Field `CMPSEL` reader - Comparison Selected Channel"] pub type CMPSEL_R = crate::FieldReader; #[doc = "Field `CMPSEL` writer - Comparison Selected Channel"] -pub type CMPSEL_W<'a, const O: u8> = crate::FieldWriter<'a, EMR_SPEC, 5, O>; +pub type CMPSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `CMPALL` reader - Compare All Channels"] pub type CMPALL_R = crate::BitReader; #[doc = "Field `CMPALL` writer - Compare All Channels"] -pub type CMPALL_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; +pub type CMPALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPFILTER` reader - Compare Event Filtering"] pub type CMPFILTER_R = crate::FieldReader; #[doc = "Field `CMPFILTER` writer - Compare Event Filtering"] -pub type CMPFILTER_W<'a, const O: u8> = crate::FieldWriter<'a, EMR_SPEC, 2, O>; +pub type CMPFILTER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `RES` reader - Resolution"] pub type RES_R = crate::FieldReader; #[doc = "Resolution\n\nValue on reset: 0"] @@ -166,69 +138,73 @@ impl RES_R { _ => None, } } - #[doc = "Checks if the value of the field is `NO_AVERAGE`"] + #[doc = "12-bit resolution, AFE sample rate is maximum (no averaging)."] #[inline(always)] pub fn is_no_average(&self) -> bool { *self == RESSELECT_A::NO_AVERAGE } - #[doc = "Checks if the value of the field is `OSR4`"] + #[doc = "13-bit resolution, AFE sample rate divided by 4 (averaging)."] #[inline(always)] pub fn is_osr4(&self) -> bool { *self == RESSELECT_A::OSR4 } - #[doc = "Checks if the value of the field is `OSR16`"] + #[doc = "14-bit resolution, AFE sample rate divided by 16 (averaging)."] #[inline(always)] pub fn is_osr16(&self) -> bool { *self == RESSELECT_A::OSR16 } - #[doc = "Checks if the value of the field is `OSR64`"] + #[doc = "15-bit resolution, AFE sample rate divided by 64 (averaging)."] #[inline(always)] pub fn is_osr64(&self) -> bool { *self == RESSELECT_A::OSR64 } - #[doc = "Checks if the value of the field is `OSR256`"] + #[doc = "16-bit resolution, AFE sample rate divided by 256 (averaging)."] #[inline(always)] pub fn is_osr256(&self) -> bool { *self == RESSELECT_A::OSR256 } } #[doc = "Field `RES` writer - Resolution"] -pub type RES_W<'a, const O: u8> = crate::FieldWriter<'a, EMR_SPEC, 3, O, RESSELECT_A>; -impl<'a, const O: u8> RES_W<'a, O> { +pub type RES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, RESSELECT_A>; +impl<'a, REG, const O: u8> RES_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "12-bit resolution, AFE sample rate is maximum (no averaging)."] #[inline(always)] - pub fn no_average(self) -> &'a mut W { + pub fn no_average(self) -> &'a mut crate::W { self.variant(RESSELECT_A::NO_AVERAGE) } #[doc = "13-bit resolution, AFE sample rate divided by 4 (averaging)."] #[inline(always)] - pub fn osr4(self) -> &'a mut W { + pub fn osr4(self) -> &'a mut crate::W { self.variant(RESSELECT_A::OSR4) } #[doc = "14-bit resolution, AFE sample rate divided by 16 (averaging)."] #[inline(always)] - pub fn osr16(self) -> &'a mut W { + pub fn osr16(self) -> &'a mut crate::W { self.variant(RESSELECT_A::OSR16) } #[doc = "15-bit resolution, AFE sample rate divided by 64 (averaging)."] #[inline(always)] - pub fn osr64(self) -> &'a mut W { + pub fn osr64(self) -> &'a mut crate::W { self.variant(RESSELECT_A::OSR64) } #[doc = "16-bit resolution, AFE sample rate divided by 256 (averaging)."] #[inline(always)] - pub fn osr256(self) -> &'a mut W { + pub fn osr256(self) -> &'a mut crate::W { self.variant(RESSELECT_A::OSR256) } } #[doc = "Field `TAG` reader - TAG of the AFEC_LDCR"] pub type TAG_R = crate::BitReader; #[doc = "Field `TAG` writer - TAG of the AFEC_LDCR"] -pub type TAG_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; +pub type TAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STM` reader - Single Trigger Mode"] pub type STM_R = crate::BitReader; #[doc = "Field `STM` writer - Single Trigger Mode"] -pub type STM_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; +pub type STM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SIGNMODE` reader - Sign Mode"] pub type SIGNMODE_R = crate::FieldReader; #[doc = "Sign Mode\n\nValue on reset: 0"] @@ -265,48 +241,52 @@ impl SIGNMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SE_UNSG_DF_SIGN`"] + #[doc = "Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions."] #[inline(always)] pub fn is_se_unsg_df_sign(&self) -> bool { *self == SIGNMODESELECT_A::SE_UNSG_DF_SIGN } - #[doc = "Checks if the value of the field is `SE_SIGN_DF_UNSG`"] + #[doc = "Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions."] #[inline(always)] pub fn is_se_sign_df_unsg(&self) -> bool { *self == SIGNMODESELECT_A::SE_SIGN_DF_UNSG } - #[doc = "Checks if the value of the field is `ALL_UNSIGNED`"] + #[doc = "All channels: Unsigned conversions."] #[inline(always)] pub fn is_all_unsigned(&self) -> bool { *self == SIGNMODESELECT_A::ALL_UNSIGNED } - #[doc = "Checks if the value of the field is `ALL_SIGNED`"] + #[doc = "All channels: Signed conversions."] #[inline(always)] pub fn is_all_signed(&self) -> bool { *self == SIGNMODESELECT_A::ALL_SIGNED } } #[doc = "Field `SIGNMODE` writer - Sign Mode"] -pub type SIGNMODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, EMR_SPEC, 2, O, SIGNMODESELECT_A>; -impl<'a, const O: u8> SIGNMODE_W<'a, O> { +pub type SIGNMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, SIGNMODESELECT_A>; +impl<'a, REG, const O: u8> SIGNMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions."] #[inline(always)] - pub fn se_unsg_df_sign(self) -> &'a mut W { + pub fn se_unsg_df_sign(self) -> &'a mut crate::W { self.variant(SIGNMODESELECT_A::SE_UNSG_DF_SIGN) } #[doc = "Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions."] #[inline(always)] - pub fn se_sign_df_unsg(self) -> &'a mut W { + pub fn se_sign_df_unsg(self) -> &'a mut crate::W { self.variant(SIGNMODESELECT_A::SE_SIGN_DF_UNSG) } #[doc = "All channels: Unsigned conversions."] #[inline(always)] - pub fn all_unsigned(self) -> &'a mut W { + pub fn all_unsigned(self) -> &'a mut crate::W { self.variant(SIGNMODESELECT_A::ALL_UNSIGNED) } #[doc = "All channels: Signed conversions."] #[inline(always)] - pub fn all_signed(self) -> &'a mut W { + pub fn all_signed(self) -> &'a mut crate::W { self.variant(SIGNMODESELECT_A::ALL_SIGNED) } } @@ -356,70 +336,67 @@ impl W { #[doc = "Bits 0:1 - Comparison Mode"] #[inline(always)] #[must_use] - pub fn cmpmode(&mut self) -> CMPMODE_W<0> { + pub fn cmpmode(&mut self) -> CMPMODE_W { CMPMODE_W::new(self) } #[doc = "Bits 3:7 - Comparison Selected Channel"] #[inline(always)] #[must_use] - pub fn cmpsel(&mut self) -> CMPSEL_W<3> { + pub fn cmpsel(&mut self) -> CMPSEL_W { CMPSEL_W::new(self) } #[doc = "Bit 9 - Compare All Channels"] #[inline(always)] #[must_use] - pub fn cmpall(&mut self) -> CMPALL_W<9> { + pub fn cmpall(&mut self) -> CMPALL_W { CMPALL_W::new(self) } #[doc = "Bits 12:13 - Compare Event Filtering"] #[inline(always)] #[must_use] - pub fn cmpfilter(&mut self) -> CMPFILTER_W<12> { + pub fn cmpfilter(&mut self) -> CMPFILTER_W { CMPFILTER_W::new(self) } #[doc = "Bits 16:18 - Resolution"] #[inline(always)] #[must_use] - pub fn res(&mut self) -> RES_W<16> { + pub fn res(&mut self) -> RES_W { RES_W::new(self) } #[doc = "Bit 24 - TAG of the AFEC_LDCR"] #[inline(always)] #[must_use] - pub fn tag(&mut self) -> TAG_W<24> { + pub fn tag(&mut self) -> TAG_W { TAG_W::new(self) } #[doc = "Bit 25 - Single Trigger Mode"] #[inline(always)] #[must_use] - pub fn stm(&mut self) -> STM_W<25> { + pub fn stm(&mut self) -> STM_W { STM_W::new(self) } #[doc = "Bits 28:29 - Sign Mode"] #[inline(always)] #[must_use] - pub fn signmode(&mut self) -> SIGNMODE_W<28> { + pub fn signmode(&mut self) -> SIGNMODE_W { SIGNMODE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Extended Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emr](index.html) module"] +#[doc = "AFEC Extended Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EMR_SPEC; impl crate::RegisterSpec for EMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [emr::R](R) reader structure"] -impl crate::Readable for EMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [emr::W](W) writer structure"] +#[doc = "`read()` method returns [`emr::R`](R) reader structure"] +impl crate::Readable for EMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"] impl crate::Writable for EMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/idr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/idr.rs index 150df726..2c3b9b14 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/idr.rs @@ -1,168 +1,148 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EOC0` writer - End of Conversion Interrupt Disable 0"] -pub type EOC0_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC1` writer - End of Conversion Interrupt Disable 1"] -pub type EOC1_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC2` writer - End of Conversion Interrupt Disable 2"] -pub type EOC2_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC3` writer - End of Conversion Interrupt Disable 3"] -pub type EOC3_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC4` writer - End of Conversion Interrupt Disable 4"] -pub type EOC4_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC5` writer - End of Conversion Interrupt Disable 5"] -pub type EOC5_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC6` writer - End of Conversion Interrupt Disable 6"] -pub type EOC6_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC7` writer - End of Conversion Interrupt Disable 7"] -pub type EOC7_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC8` writer - End of Conversion Interrupt Disable 8"] -pub type EOC8_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC9` writer - End of Conversion Interrupt Disable 9"] -pub type EOC9_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC10` writer - End of Conversion Interrupt Disable 10"] -pub type EOC10_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC11` writer - End of Conversion Interrupt Disable 11"] -pub type EOC11_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRDY` writer - Data Ready Interrupt Disable"] -pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GOVRE` writer - General Overrun Error Interrupt Disable"] -pub type GOVRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type GOVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COMPE` writer - Comparison Event Interrupt Disable"] -pub type COMPE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type COMPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEMPCHG` writer - Temperature Change Interrupt Disable"] -pub type TEMPCHG_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TEMPCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - End of Conversion Interrupt Disable 0"] #[inline(always)] #[must_use] - pub fn eoc0(&mut self) -> EOC0_W<0> { + pub fn eoc0(&mut self) -> EOC0_W { EOC0_W::new(self) } #[doc = "Bit 1 - End of Conversion Interrupt Disable 1"] #[inline(always)] #[must_use] - pub fn eoc1(&mut self) -> EOC1_W<1> { + pub fn eoc1(&mut self) -> EOC1_W { EOC1_W::new(self) } #[doc = "Bit 2 - End of Conversion Interrupt Disable 2"] #[inline(always)] #[must_use] - pub fn eoc2(&mut self) -> EOC2_W<2> { + pub fn eoc2(&mut self) -> EOC2_W { EOC2_W::new(self) } #[doc = "Bit 3 - End of Conversion Interrupt Disable 3"] #[inline(always)] #[must_use] - pub fn eoc3(&mut self) -> EOC3_W<3> { + pub fn eoc3(&mut self) -> EOC3_W { EOC3_W::new(self) } #[doc = "Bit 4 - End of Conversion Interrupt Disable 4"] #[inline(always)] #[must_use] - pub fn eoc4(&mut self) -> EOC4_W<4> { + pub fn eoc4(&mut self) -> EOC4_W { EOC4_W::new(self) } #[doc = "Bit 5 - End of Conversion Interrupt Disable 5"] #[inline(always)] #[must_use] - pub fn eoc5(&mut self) -> EOC5_W<5> { + pub fn eoc5(&mut self) -> EOC5_W { EOC5_W::new(self) } #[doc = "Bit 6 - End of Conversion Interrupt Disable 6"] #[inline(always)] #[must_use] - pub fn eoc6(&mut self) -> EOC6_W<6> { + pub fn eoc6(&mut self) -> EOC6_W { EOC6_W::new(self) } #[doc = "Bit 7 - End of Conversion Interrupt Disable 7"] #[inline(always)] #[must_use] - pub fn eoc7(&mut self) -> EOC7_W<7> { + pub fn eoc7(&mut self) -> EOC7_W { EOC7_W::new(self) } #[doc = "Bit 8 - End of Conversion Interrupt Disable 8"] #[inline(always)] #[must_use] - pub fn eoc8(&mut self) -> EOC8_W<8> { + pub fn eoc8(&mut self) -> EOC8_W { EOC8_W::new(self) } #[doc = "Bit 9 - End of Conversion Interrupt Disable 9"] #[inline(always)] #[must_use] - pub fn eoc9(&mut self) -> EOC9_W<9> { + pub fn eoc9(&mut self) -> EOC9_W { EOC9_W::new(self) } #[doc = "Bit 10 - End of Conversion Interrupt Disable 10"] #[inline(always)] #[must_use] - pub fn eoc10(&mut self) -> EOC10_W<10> { + pub fn eoc10(&mut self) -> EOC10_W { EOC10_W::new(self) } #[doc = "Bit 11 - End of Conversion Interrupt Disable 11"] #[inline(always)] #[must_use] - pub fn eoc11(&mut self) -> EOC11_W<11> { + pub fn eoc11(&mut self) -> EOC11_W { EOC11_W::new(self) } #[doc = "Bit 24 - Data Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn drdy(&mut self) -> DRDY_W<24> { + pub fn drdy(&mut self) -> DRDY_W { DRDY_W::new(self) } #[doc = "Bit 25 - General Overrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn govre(&mut self) -> GOVRE_W<25> { + pub fn govre(&mut self) -> GOVRE_W { GOVRE_W::new(self) } #[doc = "Bit 26 - Comparison Event Interrupt Disable"] #[inline(always)] #[must_use] - pub fn compe(&mut self) -> COMPE_W<26> { + pub fn compe(&mut self) -> COMPE_W { COMPE_W::new(self) } #[doc = "Bit 30 - Temperature Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn tempchg(&mut self) -> TEMPCHG_W<30> { + pub fn tempchg(&mut self) -> TEMPCHG_W { TEMPCHG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "AFEC Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/ier.rs b/arch/cortex-m/samv71q21-pac/src/afec0/ier.rs index aed74415..77f7c3c2 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/ier.rs @@ -1,168 +1,148 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EOC0` writer - End of Conversion Interrupt Enable 0"] -pub type EOC0_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC1` writer - End of Conversion Interrupt Enable 1"] -pub type EOC1_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC2` writer - End of Conversion Interrupt Enable 2"] -pub type EOC2_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC3` writer - End of Conversion Interrupt Enable 3"] -pub type EOC3_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC4` writer - End of Conversion Interrupt Enable 4"] -pub type EOC4_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC5` writer - End of Conversion Interrupt Enable 5"] -pub type EOC5_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC6` writer - End of Conversion Interrupt Enable 6"] -pub type EOC6_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC7` writer - End of Conversion Interrupt Enable 7"] -pub type EOC7_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC8` writer - End of Conversion Interrupt Enable 8"] -pub type EOC8_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC9` writer - End of Conversion Interrupt Enable 9"] -pub type EOC9_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC10` writer - End of Conversion Interrupt Enable 10"] -pub type EOC10_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC11` writer - End of Conversion Interrupt Enable 11"] -pub type EOC11_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRDY` writer - Data Ready Interrupt Enable"] -pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GOVRE` writer - General Overrun Error Interrupt Enable"] -pub type GOVRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type GOVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COMPE` writer - Comparison Event Interrupt Enable"] -pub type COMPE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type COMPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEMPCHG` writer - Temperature Change Interrupt Enable"] -pub type TEMPCHG_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TEMPCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - End of Conversion Interrupt Enable 0"] #[inline(always)] #[must_use] - pub fn eoc0(&mut self) -> EOC0_W<0> { + pub fn eoc0(&mut self) -> EOC0_W { EOC0_W::new(self) } #[doc = "Bit 1 - End of Conversion Interrupt Enable 1"] #[inline(always)] #[must_use] - pub fn eoc1(&mut self) -> EOC1_W<1> { + pub fn eoc1(&mut self) -> EOC1_W { EOC1_W::new(self) } #[doc = "Bit 2 - End of Conversion Interrupt Enable 2"] #[inline(always)] #[must_use] - pub fn eoc2(&mut self) -> EOC2_W<2> { + pub fn eoc2(&mut self) -> EOC2_W { EOC2_W::new(self) } #[doc = "Bit 3 - End of Conversion Interrupt Enable 3"] #[inline(always)] #[must_use] - pub fn eoc3(&mut self) -> EOC3_W<3> { + pub fn eoc3(&mut self) -> EOC3_W { EOC3_W::new(self) } #[doc = "Bit 4 - End of Conversion Interrupt Enable 4"] #[inline(always)] #[must_use] - pub fn eoc4(&mut self) -> EOC4_W<4> { + pub fn eoc4(&mut self) -> EOC4_W { EOC4_W::new(self) } #[doc = "Bit 5 - End of Conversion Interrupt Enable 5"] #[inline(always)] #[must_use] - pub fn eoc5(&mut self) -> EOC5_W<5> { + pub fn eoc5(&mut self) -> EOC5_W { EOC5_W::new(self) } #[doc = "Bit 6 - End of Conversion Interrupt Enable 6"] #[inline(always)] #[must_use] - pub fn eoc6(&mut self) -> EOC6_W<6> { + pub fn eoc6(&mut self) -> EOC6_W { EOC6_W::new(self) } #[doc = "Bit 7 - End of Conversion Interrupt Enable 7"] #[inline(always)] #[must_use] - pub fn eoc7(&mut self) -> EOC7_W<7> { + pub fn eoc7(&mut self) -> EOC7_W { EOC7_W::new(self) } #[doc = "Bit 8 - End of Conversion Interrupt Enable 8"] #[inline(always)] #[must_use] - pub fn eoc8(&mut self) -> EOC8_W<8> { + pub fn eoc8(&mut self) -> EOC8_W { EOC8_W::new(self) } #[doc = "Bit 9 - End of Conversion Interrupt Enable 9"] #[inline(always)] #[must_use] - pub fn eoc9(&mut self) -> EOC9_W<9> { + pub fn eoc9(&mut self) -> EOC9_W { EOC9_W::new(self) } #[doc = "Bit 10 - End of Conversion Interrupt Enable 10"] #[inline(always)] #[must_use] - pub fn eoc10(&mut self) -> EOC10_W<10> { + pub fn eoc10(&mut self) -> EOC10_W { EOC10_W::new(self) } #[doc = "Bit 11 - End of Conversion Interrupt Enable 11"] #[inline(always)] #[must_use] - pub fn eoc11(&mut self) -> EOC11_W<11> { + pub fn eoc11(&mut self) -> EOC11_W { EOC11_W::new(self) } #[doc = "Bit 24 - Data Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn drdy(&mut self) -> DRDY_W<24> { + pub fn drdy(&mut self) -> DRDY_W { DRDY_W::new(self) } #[doc = "Bit 25 - General Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn govre(&mut self) -> GOVRE_W<25> { + pub fn govre(&mut self) -> GOVRE_W { GOVRE_W::new(self) } #[doc = "Bit 26 - Comparison Event Interrupt Enable"] #[inline(always)] #[must_use] - pub fn compe(&mut self) -> COMPE_W<26> { + pub fn compe(&mut self) -> COMPE_W { COMPE_W::new(self) } #[doc = "Bit 30 - Temperature Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tempchg(&mut self) -> TEMPCHG_W<30> { + pub fn tempchg(&mut self) -> TEMPCHG_W { TEMPCHG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "AFEC Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/imr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/imr.rs index 56907ef3..727a619c 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EOC0` reader - End of Conversion Interrupt Mask 0"] pub type EOC0_R = crate::BitReader; #[doc = "Field `EOC1` reader - End of Conversion Interrupt Mask 1"] @@ -127,15 +114,13 @@ impl R { TEMPCHG_R::new(((self.bits >> 30) & 1) != 0) } } -#[doc = "AFEC Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "AFEC Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/isr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/isr.rs index 92baa71e..9d1f0494 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EOC0` reader - End of Conversion 0 (cleared by reading AFEC_CDRx)"] pub type EOC0_R = crate::BitReader; #[doc = "Field `EOC1` reader - End of Conversion 1 (cleared by reading AFEC_CDRx)"] @@ -127,15 +114,13 @@ impl R { TEMPCHG_R::new(((self.bits >> 30) & 1) != 0) } } -#[doc = "AFEC Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "AFEC Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/lcdr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/lcdr.rs index 4dfca43c..43c68e52 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/lcdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/lcdr.rs @@ -1,18 +1,5 @@ #[doc = "Register `LCDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LDATA` reader - Last Data Converted"] pub type LDATA_R = crate::FieldReader; #[doc = "Field `CHNB` reader - Channel Number"] @@ -29,15 +16,13 @@ impl R { CHNB_R::new(((self.bits >> 24) & 0x0f) as u8) } } -#[doc = "AFEC Last Converted Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lcdr](index.html) module"] +#[doc = "AFEC Last Converted Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LCDR_SPEC; impl crate::RegisterSpec for LCDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lcdr::R](R) reader structure"] -impl crate::Readable for LCDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`lcdr::R`](R) reader structure"] +impl crate::Readable for LCDR_SPEC {} #[doc = "`reset()` method sets LCDR to value 0"] impl crate::Resettable for LCDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/mr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/mr.rs index b641fde7..7d49597e 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TRGEN` reader - Trigger Enable"] pub type TRGEN_R = crate::BitReader; #[doc = "Trigger Enable\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl TRGEN_R { true => TRGENSELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "Hardware triggers are disabled. Starting a conversion is only possible by software."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == TRGENSELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "Hardware trigger selected by TRGSEL field is enabled."] #[inline(always)] pub fn is_en(&self) -> bool { *self == TRGENSELECT_A::EN } } #[doc = "Field `TRGEN` writer - Trigger Enable"] -pub type TRGEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, TRGENSELECT_A>; -impl<'a, const O: u8> TRGEN_W<'a, O> { +pub type TRGEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRGENSELECT_A>; +impl<'a, REG, const O: u8> TRGEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Hardware triggers are disabled. Starting a conversion is only possible by software."] #[inline(always)] - pub fn dis(self) -> &'a mut W { + pub fn dis(self) -> &'a mut crate::W { self.variant(TRGENSELECT_A::DIS) } #[doc = "Hardware trigger selected by TRGSEL field is enabled."] #[inline(always)] - pub fn en(self) -> &'a mut W { + pub fn en(self) -> &'a mut crate::W { self.variant(TRGENSELECT_A::EN) } } @@ -129,78 +100,82 @@ impl TRGSEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `AFEC_TRIG0`"] + #[doc = "AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1"] #[inline(always)] pub fn is_afec_trig0(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG0 } - #[doc = "Checks if the value of the field is `AFEC_TRIG1`"] + #[doc = "TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1"] #[inline(always)] pub fn is_afec_trig1(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG1 } - #[doc = "Checks if the value of the field is `AFEC_TRIG2`"] + #[doc = "TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1"] #[inline(always)] pub fn is_afec_trig2(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG2 } - #[doc = "Checks if the value of the field is `AFEC_TRIG3`"] + #[doc = "TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1"] #[inline(always)] pub fn is_afec_trig3(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG3 } - #[doc = "Checks if the value of the field is `AFEC_TRIG4`"] + #[doc = "PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1"] #[inline(always)] pub fn is_afec_trig4(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG4 } - #[doc = "Checks if the value of the field is `AFEC_TRIG5`"] + #[doc = "PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1"] #[inline(always)] pub fn is_afec_trig5(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG5 } - #[doc = "Checks if the value of the field is `AFEC_TRIG6`"] + #[doc = "Analog Comparator"] #[inline(always)] pub fn is_afec_trig6(&self) -> bool { *self == TRGSELSELECT_A::AFEC_TRIG6 } } #[doc = "Field `TRGSEL` writer - Trigger Selection"] -pub type TRGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 3, O, TRGSELSELECT_A>; -impl<'a, const O: u8> TRGSEL_W<'a, O> { +pub type TRGSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, TRGSELSELECT_A>; +impl<'a, REG, const O: u8> TRGSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1"] #[inline(always)] - pub fn afec_trig0(self) -> &'a mut W { + pub fn afec_trig0(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG0) } #[doc = "TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1"] #[inline(always)] - pub fn afec_trig1(self) -> &'a mut W { + pub fn afec_trig1(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG1) } #[doc = "TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1"] #[inline(always)] - pub fn afec_trig2(self) -> &'a mut W { + pub fn afec_trig2(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG2) } #[doc = "TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1"] #[inline(always)] - pub fn afec_trig3(self) -> &'a mut W { + pub fn afec_trig3(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG3) } #[doc = "PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1"] #[inline(always)] - pub fn afec_trig4(self) -> &'a mut W { + pub fn afec_trig4(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG4) } #[doc = "PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1"] #[inline(always)] - pub fn afec_trig5(self) -> &'a mut W { + pub fn afec_trig5(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG5) } #[doc = "Analog Comparator"] #[inline(always)] - pub fn afec_trig6(self) -> &'a mut W { + pub fn afec_trig6(self) -> &'a mut crate::W { self.variant(TRGSELSELECT_A::AFEC_TRIG6) } } @@ -229,28 +204,31 @@ impl SLEEP_R { true => SLEEPSELECT_A::SLEEP, } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "Normal mode: The AFE and reference voltage circuitry are kept ON between conversions."] #[inline(always)] pub fn is_normal(&self) -> bool { *self == SLEEPSELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `SLEEP`"] + #[doc = "Sleep mode: The AFE and reference voltage circuitry are OFF between conversions."] #[inline(always)] pub fn is_sleep(&self) -> bool { *self == SLEEPSELECT_A::SLEEP } } #[doc = "Field `SLEEP` writer - Sleep Mode"] -pub type SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, SLEEPSELECT_A>; -impl<'a, const O: u8> SLEEP_W<'a, O> { +pub type SLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SLEEPSELECT_A>; +impl<'a, REG, const O: u8> SLEEP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal mode: The AFE and reference voltage circuitry are kept ON between conversions."] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(SLEEPSELECT_A::NORMAL) } #[doc = "Sleep mode: The AFE and reference voltage circuitry are OFF between conversions."] #[inline(always)] - pub fn sleep(self) -> &'a mut W { + pub fn sleep(self) -> &'a mut crate::W { self.variant(SLEEPSELECT_A::SLEEP) } } @@ -279,28 +257,31 @@ impl FWUP_R { true => FWUPSELECT_A::ON, } } - #[doc = "Checks if the value of the field is `OFF`"] + #[doc = "Normal Sleep mode: The sleep mode is defined by the SLEEP bit."] #[inline(always)] pub fn is_off(&self) -> bool { *self == FWUPSELECT_A::OFF } - #[doc = "Checks if the value of the field is `ON`"] + #[doc = "Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF."] #[inline(always)] pub fn is_on(&self) -> bool { *self == FWUPSELECT_A::ON } } #[doc = "Field `FWUP` writer - Fast Wake-up"] -pub type FWUP_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, FWUPSELECT_A>; -impl<'a, const O: u8> FWUP_W<'a, O> { +pub type FWUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FWUPSELECT_A>; +impl<'a, REG, const O: u8> FWUP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal Sleep mode: The sleep mode is defined by the SLEEP bit."] #[inline(always)] - pub fn off(self) -> &'a mut W { + pub fn off(self) -> &'a mut crate::W { self.variant(FWUPSELECT_A::OFF) } #[doc = "Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF."] #[inline(always)] - pub fn on(self) -> &'a mut W { + pub fn on(self) -> &'a mut crate::W { self.variant(FWUPSELECT_A::ON) } } @@ -329,35 +310,38 @@ impl FREERUN_R { true => FREERUNSELECT_A::ON, } } - #[doc = "Checks if the value of the field is `OFF`"] + #[doc = "Normal mode"] #[inline(always)] pub fn is_off(&self) -> bool { *self == FREERUNSELECT_A::OFF } - #[doc = "Checks if the value of the field is `ON`"] + #[doc = "Free Run mode: Never wait for any trigger."] #[inline(always)] pub fn is_on(&self) -> bool { *self == FREERUNSELECT_A::ON } } #[doc = "Field `FREERUN` writer - Free Run Mode"] -pub type FREERUN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, FREERUNSELECT_A>; -impl<'a, const O: u8> FREERUN_W<'a, O> { +pub type FREERUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FREERUNSELECT_A>; +impl<'a, REG, const O: u8> FREERUN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal mode"] #[inline(always)] - pub fn off(self) -> &'a mut W { + pub fn off(self) -> &'a mut crate::W { self.variant(FREERUNSELECT_A::OFF) } #[doc = "Free Run mode: Never wait for any trigger."] #[inline(always)] - pub fn on(self) -> &'a mut W { + pub fn on(self) -> &'a mut crate::W { self.variant(FREERUNSELECT_A::ON) } } #[doc = "Field `PRESCAL` reader - Prescaler Rate Selection"] pub type PRESCAL_R = crate::FieldReader; #[doc = "Field `PRESCAL` writer - Prescaler Rate Selection"] -pub type PRESCAL_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O>; +pub type PRESCAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `STARTUP` reader - Start-up Time"] pub type STARTUP_R = crate::FieldReader; #[doc = "Start-up Time\n\nValue on reset: 0"] @@ -430,183 +414,187 @@ impl STARTUP_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SUT0`"] + #[doc = "0 periods of AFE clock"] #[inline(always)] pub fn is_sut0(&self) -> bool { *self == STARTUPSELECT_A::SUT0 } - #[doc = "Checks if the value of the field is `SUT8`"] + #[doc = "8 periods of AFE clock"] #[inline(always)] pub fn is_sut8(&self) -> bool { *self == STARTUPSELECT_A::SUT8 } - #[doc = "Checks if the value of the field is `SUT16`"] + #[doc = "16 periods of AFE clock"] #[inline(always)] pub fn is_sut16(&self) -> bool { *self == STARTUPSELECT_A::SUT16 } - #[doc = "Checks if the value of the field is `SUT24`"] + #[doc = "24 periods of AFE clock"] #[inline(always)] pub fn is_sut24(&self) -> bool { *self == STARTUPSELECT_A::SUT24 } - #[doc = "Checks if the value of the field is `SUT64`"] + #[doc = "64 periods of AFE clock"] #[inline(always)] pub fn is_sut64(&self) -> bool { *self == STARTUPSELECT_A::SUT64 } - #[doc = "Checks if the value of the field is `SUT80`"] + #[doc = "80 periods of AFE clock"] #[inline(always)] pub fn is_sut80(&self) -> bool { *self == STARTUPSELECT_A::SUT80 } - #[doc = "Checks if the value of the field is `SUT96`"] + #[doc = "96 periods of AFE clock"] #[inline(always)] pub fn is_sut96(&self) -> bool { *self == STARTUPSELECT_A::SUT96 } - #[doc = "Checks if the value of the field is `SUT112`"] + #[doc = "112 periods of AFE clock"] #[inline(always)] pub fn is_sut112(&self) -> bool { *self == STARTUPSELECT_A::SUT112 } - #[doc = "Checks if the value of the field is `SUT512`"] + #[doc = "512 periods of AFE clock"] #[inline(always)] pub fn is_sut512(&self) -> bool { *self == STARTUPSELECT_A::SUT512 } - #[doc = "Checks if the value of the field is `SUT576`"] + #[doc = "576 periods of AFE clock"] #[inline(always)] pub fn is_sut576(&self) -> bool { *self == STARTUPSELECT_A::SUT576 } - #[doc = "Checks if the value of the field is `SUT640`"] + #[doc = "640 periods of AFE clock"] #[inline(always)] pub fn is_sut640(&self) -> bool { *self == STARTUPSELECT_A::SUT640 } - #[doc = "Checks if the value of the field is `SUT704`"] + #[doc = "704 periods of AFE clock"] #[inline(always)] pub fn is_sut704(&self) -> bool { *self == STARTUPSELECT_A::SUT704 } - #[doc = "Checks if the value of the field is `SUT768`"] + #[doc = "768 periods of AFE clock"] #[inline(always)] pub fn is_sut768(&self) -> bool { *self == STARTUPSELECT_A::SUT768 } - #[doc = "Checks if the value of the field is `SUT832`"] + #[doc = "832 periods of AFE clock"] #[inline(always)] pub fn is_sut832(&self) -> bool { *self == STARTUPSELECT_A::SUT832 } - #[doc = "Checks if the value of the field is `SUT896`"] + #[doc = "896 periods of AFE clock"] #[inline(always)] pub fn is_sut896(&self) -> bool { *self == STARTUPSELECT_A::SUT896 } - #[doc = "Checks if the value of the field is `SUT960`"] + #[doc = "960 periods of AFE clock"] #[inline(always)] pub fn is_sut960(&self) -> bool { *self == STARTUPSELECT_A::SUT960 } } #[doc = "Field `STARTUP` writer - Start-up Time"] -pub type STARTUP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 4, O, STARTUPSELECT_A>; -impl<'a, const O: u8> STARTUP_W<'a, O> { +pub type STARTUP_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 4, O, STARTUPSELECT_A>; +impl<'a, REG, const O: u8> STARTUP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "0 periods of AFE clock"] #[inline(always)] - pub fn sut0(self) -> &'a mut W { + pub fn sut0(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT0) } #[doc = "8 periods of AFE clock"] #[inline(always)] - pub fn sut8(self) -> &'a mut W { + pub fn sut8(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT8) } #[doc = "16 periods of AFE clock"] #[inline(always)] - pub fn sut16(self) -> &'a mut W { + pub fn sut16(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT16) } #[doc = "24 periods of AFE clock"] #[inline(always)] - pub fn sut24(self) -> &'a mut W { + pub fn sut24(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT24) } #[doc = "64 periods of AFE clock"] #[inline(always)] - pub fn sut64(self) -> &'a mut W { + pub fn sut64(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT64) } #[doc = "80 periods of AFE clock"] #[inline(always)] - pub fn sut80(self) -> &'a mut W { + pub fn sut80(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT80) } #[doc = "96 periods of AFE clock"] #[inline(always)] - pub fn sut96(self) -> &'a mut W { + pub fn sut96(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT96) } #[doc = "112 periods of AFE clock"] #[inline(always)] - pub fn sut112(self) -> &'a mut W { + pub fn sut112(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT112) } #[doc = "512 periods of AFE clock"] #[inline(always)] - pub fn sut512(self) -> &'a mut W { + pub fn sut512(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT512) } #[doc = "576 periods of AFE clock"] #[inline(always)] - pub fn sut576(self) -> &'a mut W { + pub fn sut576(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT576) } #[doc = "640 periods of AFE clock"] #[inline(always)] - pub fn sut640(self) -> &'a mut W { + pub fn sut640(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT640) } #[doc = "704 periods of AFE clock"] #[inline(always)] - pub fn sut704(self) -> &'a mut W { + pub fn sut704(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT704) } #[doc = "768 periods of AFE clock"] #[inline(always)] - pub fn sut768(self) -> &'a mut W { + pub fn sut768(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT768) } #[doc = "832 periods of AFE clock"] #[inline(always)] - pub fn sut832(self) -> &'a mut W { + pub fn sut832(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT832) } #[doc = "896 periods of AFE clock"] #[inline(always)] - pub fn sut896(self) -> &'a mut W { + pub fn sut896(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT896) } #[doc = "960 periods of AFE clock"] #[inline(always)] - pub fn sut960(self) -> &'a mut W { + pub fn sut960(self) -> &'a mut crate::W { self.variant(STARTUPSELECT_A::SUT960) } } #[doc = "Field `ONE` reader - One"] pub type ONE_R = crate::BitReader; #[doc = "Field `ONE` writer - One"] -pub type ONE_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type ONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRACKTIM` reader - Tracking Time"] pub type TRACKTIM_R = crate::FieldReader; #[doc = "Field `TRACKTIM` writer - Tracking Time"] -pub type TRACKTIM_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O>; +pub type TRACKTIM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TRANSFER` reader - Transfer Period"] pub type TRANSFER_R = crate::FieldReader; #[doc = "Field `TRANSFER` writer - Transfer Period"] -pub type TRANSFER_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 2, O>; +pub type TRANSFER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `USEQ` reader - User Sequence Enable"] pub type USEQ_R = crate::BitReader; #[doc = "User Sequence Enable\n\nValue on reset: 0"] @@ -632,28 +620,31 @@ impl USEQ_R { true => USEQSELECT_A::REG_ORDER, } } - #[doc = "Checks if the value of the field is `NUM_ORDER`"] + #[doc = "Normal mode: The controller converts channels in a simple numeric order."] #[inline(always)] pub fn is_num_order(&self) -> bool { *self == USEQSELECT_A::NUM_ORDER } - #[doc = "Checks if the value of the field is `REG_ORDER`"] + #[doc = "User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R."] #[inline(always)] pub fn is_reg_order(&self) -> bool { *self == USEQSELECT_A::REG_ORDER } } #[doc = "Field `USEQ` writer - User Sequence Enable"] -pub type USEQ_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, USEQSELECT_A>; -impl<'a, const O: u8> USEQ_W<'a, O> { +pub type USEQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, USEQSELECT_A>; +impl<'a, REG, const O: u8> USEQ_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal mode: The controller converts channels in a simple numeric order."] #[inline(always)] - pub fn num_order(self) -> &'a mut W { + pub fn num_order(self) -> &'a mut crate::W { self.variant(USEQSELECT_A::NUM_ORDER) } #[doc = "User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R."] #[inline(always)] - pub fn reg_order(self) -> &'a mut W { + pub fn reg_order(self) -> &'a mut crate::W { self.variant(USEQSELECT_A::REG_ORDER) } } @@ -718,88 +709,85 @@ impl W { #[doc = "Bit 0 - Trigger Enable"] #[inline(always)] #[must_use] - pub fn trgen(&mut self) -> TRGEN_W<0> { + pub fn trgen(&mut self) -> TRGEN_W { TRGEN_W::new(self) } #[doc = "Bits 1:3 - Trigger Selection"] #[inline(always)] #[must_use] - pub fn trgsel(&mut self) -> TRGSEL_W<1> { + pub fn trgsel(&mut self) -> TRGSEL_W { TRGSEL_W::new(self) } #[doc = "Bit 5 - Sleep Mode"] #[inline(always)] #[must_use] - pub fn sleep(&mut self) -> SLEEP_W<5> { + pub fn sleep(&mut self) -> SLEEP_W { SLEEP_W::new(self) } #[doc = "Bit 6 - Fast Wake-up"] #[inline(always)] #[must_use] - pub fn fwup(&mut self) -> FWUP_W<6> { + pub fn fwup(&mut self) -> FWUP_W { FWUP_W::new(self) } #[doc = "Bit 7 - Free Run Mode"] #[inline(always)] #[must_use] - pub fn freerun(&mut self) -> FREERUN_W<7> { + pub fn freerun(&mut self) -> FREERUN_W { FREERUN_W::new(self) } #[doc = "Bits 8:15 - Prescaler Rate Selection"] #[inline(always)] #[must_use] - pub fn prescal(&mut self) -> PRESCAL_W<8> { + pub fn prescal(&mut self) -> PRESCAL_W { PRESCAL_W::new(self) } #[doc = "Bits 16:19 - Start-up Time"] #[inline(always)] #[must_use] - pub fn startup(&mut self) -> STARTUP_W<16> { + pub fn startup(&mut self) -> STARTUP_W { STARTUP_W::new(self) } #[doc = "Bit 23 - One"] #[inline(always)] #[must_use] - pub fn one(&mut self) -> ONE_W<23> { + pub fn one(&mut self) -> ONE_W { ONE_W::new(self) } #[doc = "Bits 24:27 - Tracking Time"] #[inline(always)] #[must_use] - pub fn tracktim(&mut self) -> TRACKTIM_W<24> { + pub fn tracktim(&mut self) -> TRACKTIM_W { TRACKTIM_W::new(self) } #[doc = "Bits 28:29 - Transfer Period"] #[inline(always)] #[must_use] - pub fn transfer(&mut self) -> TRANSFER_W<28> { + pub fn transfer(&mut self) -> TRANSFER_W { TRANSFER_W::new(self) } #[doc = "Bit 31 - User Sequence Enable"] #[inline(always)] #[must_use] - pub fn useq(&mut self) -> USEQ_W<31> { + pub fn useq(&mut self) -> USEQ_W { USEQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "AFEC Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/over.rs b/arch/cortex-m/samv71q21-pac/src/afec0/over.rs index 65f915ee..87b24437 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/over.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/over.rs @@ -1,18 +1,5 @@ #[doc = "Register `OVER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OVRE0` reader - Overrun Error 0"] pub type OVRE0_R = crate::BitReader; #[doc = "Field `OVRE1` reader - Overrun Error 1"] @@ -99,15 +86,13 @@ impl R { OVRE11_R::new(((self.bits >> 11) & 1) != 0) } } -#[doc = "AFEC Overrun Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [over](index.html) module"] +#[doc = "AFEC Overrun Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`over::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OVER_SPEC; impl crate::RegisterSpec for OVER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [over::R](R) reader structure"] -impl crate::Readable for OVER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`over::R`](R) reader structure"] +impl crate::Readable for OVER_SPEC {} #[doc = "`reset()` method sets OVER to value 0"] impl crate::Resettable for OVER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/seq1r.rs b/arch/cortex-m/samv71q21-pac/src/afec0/seq1r.rs index be2a45c0..b80ff8cf 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/seq1r.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/seq1r.rs @@ -1,71 +1,39 @@ #[doc = "Register `SEQ1R` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SEQ1R` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USCH0` reader - User Sequence Number 0"] pub type USCH0_R = crate::FieldReader; #[doc = "Field `USCH0` writer - User Sequence Number 0"] -pub type USCH0_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH1` reader - User Sequence Number 1"] pub type USCH1_R = crate::FieldReader; #[doc = "Field `USCH1` writer - User Sequence Number 1"] -pub type USCH1_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH2` reader - User Sequence Number 2"] pub type USCH2_R = crate::FieldReader; #[doc = "Field `USCH2` writer - User Sequence Number 2"] -pub type USCH2_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH3` reader - User Sequence Number 3"] pub type USCH3_R = crate::FieldReader; #[doc = "Field `USCH3` writer - User Sequence Number 3"] -pub type USCH3_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH4` reader - User Sequence Number 4"] pub type USCH4_R = crate::FieldReader; #[doc = "Field `USCH4` writer - User Sequence Number 4"] -pub type USCH4_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH5` reader - User Sequence Number 5"] pub type USCH5_R = crate::FieldReader; #[doc = "Field `USCH5` writer - User Sequence Number 5"] -pub type USCH5_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH6` reader - User Sequence Number 6"] pub type USCH6_R = crate::FieldReader; #[doc = "Field `USCH6` writer - User Sequence Number 6"] -pub type USCH6_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH7` reader - User Sequence Number 7"] pub type USCH7_R = crate::FieldReader; #[doc = "Field `USCH7` writer - User Sequence Number 7"] -pub type USCH7_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ1R_SPEC, 4, O>; +pub type USCH7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - User Sequence Number 0"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bits 0:3 - User Sequence Number 0"] #[inline(always)] #[must_use] - pub fn usch0(&mut self) -> USCH0_W<0> { + pub fn usch0(&mut self) -> USCH0_W { USCH0_W::new(self) } #[doc = "Bits 4:7 - User Sequence Number 1"] #[inline(always)] #[must_use] - pub fn usch1(&mut self) -> USCH1_W<4> { + pub fn usch1(&mut self) -> USCH1_W { USCH1_W::new(self) } #[doc = "Bits 8:11 - User Sequence Number 2"] #[inline(always)] #[must_use] - pub fn usch2(&mut self) -> USCH2_W<8> { + pub fn usch2(&mut self) -> USCH2_W { USCH2_W::new(self) } #[doc = "Bits 12:15 - User Sequence Number 3"] #[inline(always)] #[must_use] - pub fn usch3(&mut self) -> USCH3_W<12> { + pub fn usch3(&mut self) -> USCH3_W { USCH3_W::new(self) } #[doc = "Bits 16:19 - User Sequence Number 4"] #[inline(always)] #[must_use] - pub fn usch4(&mut self) -> USCH4_W<16> { + pub fn usch4(&mut self) -> USCH4_W { USCH4_W::new(self) } #[doc = "Bits 20:23 - User Sequence Number 5"] #[inline(always)] #[must_use] - pub fn usch5(&mut self) -> USCH5_W<20> { + pub fn usch5(&mut self) -> USCH5_W { USCH5_W::new(self) } #[doc = "Bits 24:27 - User Sequence Number 6"] #[inline(always)] #[must_use] - pub fn usch6(&mut self) -> USCH6_W<24> { + pub fn usch6(&mut self) -> USCH6_W { USCH6_W::new(self) } #[doc = "Bits 28:31 - User Sequence Number 7"] #[inline(always)] #[must_use] - pub fn usch7(&mut self) -> USCH7_W<28> { + pub fn usch7(&mut self) -> USCH7_W { USCH7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Sequence 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seq1r](index.html) module"] +#[doc = "AFEC Channel Sequence 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq1r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq1r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SEQ1R_SPEC; impl crate::RegisterSpec for SEQ1R_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [seq1r::R](R) reader structure"] -impl crate::Readable for SEQ1R_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [seq1r::W](W) writer structure"] +#[doc = "`read()` method returns [`seq1r::R`](R) reader structure"] +impl crate::Readable for SEQ1R_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seq1r::W`](W) writer structure"] impl crate::Writable for SEQ1R_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/seq2r.rs b/arch/cortex-m/samv71q21-pac/src/afec0/seq2r.rs index f1ac3ff7..8986b1b1 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/seq2r.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/seq2r.rs @@ -1,55 +1,23 @@ #[doc = "Register `SEQ2R` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SEQ2R` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USCH8` reader - User Sequence Number 8"] pub type USCH8_R = crate::FieldReader; #[doc = "Field `USCH8` writer - User Sequence Number 8"] -pub type USCH8_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ2R_SPEC, 4, O>; +pub type USCH8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH9` reader - User Sequence Number 9"] pub type USCH9_R = crate::FieldReader; #[doc = "Field `USCH9` writer - User Sequence Number 9"] -pub type USCH9_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ2R_SPEC, 4, O>; +pub type USCH9_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH10` reader - User Sequence Number 10"] pub type USCH10_R = crate::FieldReader; #[doc = "Field `USCH10` writer - User Sequence Number 10"] -pub type USCH10_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ2R_SPEC, 4, O>; +pub type USCH10_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `USCH11` reader - User Sequence Number 11"] pub type USCH11_R = crate::FieldReader; #[doc = "Field `USCH11` writer - User Sequence Number 11"] -pub type USCH11_W<'a, const O: u8> = crate::FieldWriter<'a, SEQ2R_SPEC, 4, O>; +pub type USCH11_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - User Sequence Number 8"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:3 - User Sequence Number 8"] #[inline(always)] #[must_use] - pub fn usch8(&mut self) -> USCH8_W<0> { + pub fn usch8(&mut self) -> USCH8_W { USCH8_W::new(self) } #[doc = "Bits 4:7 - User Sequence Number 9"] #[inline(always)] #[must_use] - pub fn usch9(&mut self) -> USCH9_W<4> { + pub fn usch9(&mut self) -> USCH9_W { USCH9_W::new(self) } #[doc = "Bits 8:11 - User Sequence Number 10"] #[inline(always)] #[must_use] - pub fn usch10(&mut self) -> USCH10_W<8> { + pub fn usch10(&mut self) -> USCH10_W { USCH10_W::new(self) } #[doc = "Bits 12:15 - User Sequence Number 11"] #[inline(always)] #[must_use] - pub fn usch11(&mut self) -> USCH11_W<12> { + pub fn usch11(&mut self) -> USCH11_W { USCH11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Channel Sequence 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seq2r](index.html) module"] +#[doc = "AFEC Channel Sequence 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq2r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq2r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SEQ2R_SPEC; impl crate::RegisterSpec for SEQ2R_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [seq2r::R](R) reader structure"] -impl crate::Readable for SEQ2R_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [seq2r::W](W) writer structure"] +#[doc = "`read()` method returns [`seq2r::R`](R) reader structure"] +impl crate::Readable for SEQ2R_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seq2r::W`](W) writer structure"] impl crate::Writable for SEQ2R_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/shmr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/shmr.rs index a04708dd..cf8b6727 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/shmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/shmr.rs @@ -1,87 +1,55 @@ #[doc = "Register `SHMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SHMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DUAL0` reader - Dual Sample & Hold for channel 0"] pub type DUAL0_R = crate::BitReader; #[doc = "Field `DUAL0` writer - Dual Sample & Hold for channel 0"] -pub type DUAL0_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL1` reader - Dual Sample & Hold for channel 1"] pub type DUAL1_R = crate::BitReader; #[doc = "Field `DUAL1` writer - Dual Sample & Hold for channel 1"] -pub type DUAL1_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL2` reader - Dual Sample & Hold for channel 2"] pub type DUAL2_R = crate::BitReader; #[doc = "Field `DUAL2` writer - Dual Sample & Hold for channel 2"] -pub type DUAL2_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL3` reader - Dual Sample & Hold for channel 3"] pub type DUAL3_R = crate::BitReader; #[doc = "Field `DUAL3` writer - Dual Sample & Hold for channel 3"] -pub type DUAL3_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL4` reader - Dual Sample & Hold for channel 4"] pub type DUAL4_R = crate::BitReader; #[doc = "Field `DUAL4` writer - Dual Sample & Hold for channel 4"] -pub type DUAL4_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL5` reader - Dual Sample & Hold for channel 5"] pub type DUAL5_R = crate::BitReader; #[doc = "Field `DUAL5` writer - Dual Sample & Hold for channel 5"] -pub type DUAL5_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL6` reader - Dual Sample & Hold for channel 6"] pub type DUAL6_R = crate::BitReader; #[doc = "Field `DUAL6` writer - Dual Sample & Hold for channel 6"] -pub type DUAL6_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL7` reader - Dual Sample & Hold for channel 7"] pub type DUAL7_R = crate::BitReader; #[doc = "Field `DUAL7` writer - Dual Sample & Hold for channel 7"] -pub type DUAL7_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL8` reader - Dual Sample & Hold for channel 8"] pub type DUAL8_R = crate::BitReader; #[doc = "Field `DUAL8` writer - Dual Sample & Hold for channel 8"] -pub type DUAL8_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL9` reader - Dual Sample & Hold for channel 9"] pub type DUAL9_R = crate::BitReader; #[doc = "Field `DUAL9` writer - Dual Sample & Hold for channel 9"] -pub type DUAL9_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL10` reader - Dual Sample & Hold for channel 10"] pub type DUAL10_R = crate::BitReader; #[doc = "Field `DUAL10` writer - Dual Sample & Hold for channel 10"] -pub type DUAL10_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUAL11` reader - Dual Sample & Hold for channel 11"] pub type DUAL11_R = crate::BitReader; #[doc = "Field `DUAL11` writer - Dual Sample & Hold for channel 11"] -pub type DUAL11_W<'a, const O: u8> = crate::BitWriter<'a, SHMR_SPEC, O>; +pub type DUAL11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Dual Sample & Hold for channel 0"] #[inline(always)] @@ -148,94 +116,91 @@ impl W { #[doc = "Bit 0 - Dual Sample & Hold for channel 0"] #[inline(always)] #[must_use] - pub fn dual0(&mut self) -> DUAL0_W<0> { + pub fn dual0(&mut self) -> DUAL0_W { DUAL0_W::new(self) } #[doc = "Bit 1 - Dual Sample & Hold for channel 1"] #[inline(always)] #[must_use] - pub fn dual1(&mut self) -> DUAL1_W<1> { + pub fn dual1(&mut self) -> DUAL1_W { DUAL1_W::new(self) } #[doc = "Bit 2 - Dual Sample & Hold for channel 2"] #[inline(always)] #[must_use] - pub fn dual2(&mut self) -> DUAL2_W<2> { + pub fn dual2(&mut self) -> DUAL2_W { DUAL2_W::new(self) } #[doc = "Bit 3 - Dual Sample & Hold for channel 3"] #[inline(always)] #[must_use] - pub fn dual3(&mut self) -> DUAL3_W<3> { + pub fn dual3(&mut self) -> DUAL3_W { DUAL3_W::new(self) } #[doc = "Bit 4 - Dual Sample & Hold for channel 4"] #[inline(always)] #[must_use] - pub fn dual4(&mut self) -> DUAL4_W<4> { + pub fn dual4(&mut self) -> DUAL4_W { DUAL4_W::new(self) } #[doc = "Bit 5 - Dual Sample & Hold for channel 5"] #[inline(always)] #[must_use] - pub fn dual5(&mut self) -> DUAL5_W<5> { + pub fn dual5(&mut self) -> DUAL5_W { DUAL5_W::new(self) } #[doc = "Bit 6 - Dual Sample & Hold for channel 6"] #[inline(always)] #[must_use] - pub fn dual6(&mut self) -> DUAL6_W<6> { + pub fn dual6(&mut self) -> DUAL6_W { DUAL6_W::new(self) } #[doc = "Bit 7 - Dual Sample & Hold for channel 7"] #[inline(always)] #[must_use] - pub fn dual7(&mut self) -> DUAL7_W<7> { + pub fn dual7(&mut self) -> DUAL7_W { DUAL7_W::new(self) } #[doc = "Bit 8 - Dual Sample & Hold for channel 8"] #[inline(always)] #[must_use] - pub fn dual8(&mut self) -> DUAL8_W<8> { + pub fn dual8(&mut self) -> DUAL8_W { DUAL8_W::new(self) } #[doc = "Bit 9 - Dual Sample & Hold for channel 9"] #[inline(always)] #[must_use] - pub fn dual9(&mut self) -> DUAL9_W<9> { + pub fn dual9(&mut self) -> DUAL9_W { DUAL9_W::new(self) } #[doc = "Bit 10 - Dual Sample & Hold for channel 10"] #[inline(always)] #[must_use] - pub fn dual10(&mut self) -> DUAL10_W<10> { + pub fn dual10(&mut self) -> DUAL10_W { DUAL10_W::new(self) } #[doc = "Bit 11 - Dual Sample & Hold for channel 11"] #[inline(always)] #[must_use] - pub fn dual11(&mut self) -> DUAL11_W<11> { + pub fn dual11(&mut self) -> DUAL11_W { DUAL11_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Sample & Hold Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [shmr](index.html) module"] +#[doc = "AFEC Sample & Hold Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SHMR_SPEC; impl crate::RegisterSpec for SHMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [shmr::R](R) reader structure"] -impl crate::Readable for SHMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [shmr::W](W) writer structure"] +#[doc = "`read()` method returns [`shmr::R`](R) reader structure"] +impl crate::Readable for SHMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shmr::W`](W) writer structure"] impl crate::Writable for SHMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/tempcwr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/tempcwr.rs index 0d0719de..1c447d3f 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/tempcwr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/tempcwr.rs @@ -1,47 +1,15 @@ #[doc = "Register `TEMPCWR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TEMPCWR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TLOWTHRES` reader - Temperature Low Threshold"] pub type TLOWTHRES_R = crate::FieldReader; #[doc = "Field `TLOWTHRES` writer - Temperature Low Threshold"] -pub type TLOWTHRES_W<'a, const O: u8> = crate::FieldWriter<'a, TEMPCWR_SPEC, 16, O, u16>; +pub type TLOWTHRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `THIGHTHRES` reader - Temperature High Threshold"] pub type THIGHTHRES_R = crate::FieldReader; #[doc = "Field `THIGHTHRES` writer - Temperature High Threshold"] -pub type THIGHTHRES_W<'a, const O: u8> = crate::FieldWriter<'a, TEMPCWR_SPEC, 16, O, u16>; +pub type THIGHTHRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Temperature Low Threshold"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Temperature Low Threshold"] #[inline(always)] #[must_use] - pub fn tlowthres(&mut self) -> TLOWTHRES_W<0> { + pub fn tlowthres(&mut self) -> TLOWTHRES_W { TLOWTHRES_W::new(self) } #[doc = "Bits 16:31 - Temperature High Threshold"] #[inline(always)] #[must_use] - pub fn thighthres(&mut self) -> THIGHTHRES_W<16> { + pub fn thighthres(&mut self) -> THIGHTHRES_W { THIGHTHRES_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Temperature Compare Window Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tempcwr](index.html) module"] +#[doc = "AFEC Temperature Compare Window Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tempcwr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tempcwr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TEMPCWR_SPEC; impl crate::RegisterSpec for TEMPCWR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tempcwr::R](R) reader structure"] -impl crate::Readable for TEMPCWR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tempcwr::W](W) writer structure"] +#[doc = "`read()` method returns [`tempcwr::R`](R) reader structure"] +impl crate::Readable for TEMPCWR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tempcwr::W`](W) writer structure"] impl crate::Writable for TEMPCWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/tempmr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/tempmr.rs index 518857f6..d58934cd 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/tempmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/tempmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `TEMPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TEMPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTCT` reader - Temperature Sensor RTC Trigger Mode"] pub type RTCT_R = crate::BitReader; #[doc = "Field `RTCT` writer - Temperature Sensor RTC Trigger Mode"] -pub type RTCT_W<'a, const O: u8> = crate::BitWriter<'a, TEMPMR_SPEC, O>; +pub type RTCT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEMPCMPMOD` reader - Temperature Comparison Mode"] pub type TEMPCMPMOD_R = crate::FieldReader; #[doc = "Temperature Comparison Mode\n\nValue on reset: 0"] @@ -74,49 +42,53 @@ impl TEMPCMPMOD_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Generates an event when the converted data is lower than the low threshold of the window."] #[inline(always)] pub fn is_low(&self) -> bool { *self == TEMPCMPMODSELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Generates an event when the converted data is higher than the high threshold of the window."] #[inline(always)] pub fn is_high(&self) -> bool { *self == TEMPCMPMODSELECT_A::HIGH } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "Generates an event when the converted data is in the comparison window."] #[inline(always)] pub fn is_in(&self) -> bool { *self == TEMPCMPMODSELECT_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "Generates an event when the converted data is out of the comparison window."] #[inline(always)] pub fn is_out(&self) -> bool { *self == TEMPCMPMODSELECT_A::OUT } } #[doc = "Field `TEMPCMPMOD` writer - Temperature Comparison Mode"] -pub type TEMPCMPMOD_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, TEMPMR_SPEC, 2, O, TEMPCMPMODSELECT_A>; -impl<'a, const O: u8> TEMPCMPMOD_W<'a, O> { +pub type TEMPCMPMOD_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 2, O, TEMPCMPMODSELECT_A>; +impl<'a, REG, const O: u8> TEMPCMPMOD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Generates an event when the converted data is lower than the low threshold of the window."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(TEMPCMPMODSELECT_A::LOW) } #[doc = "Generates an event when the converted data is higher than the high threshold of the window."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(TEMPCMPMODSELECT_A::HIGH) } #[doc = "Generates an event when the converted data is in the comparison window."] #[inline(always)] - pub fn in_(self) -> &'a mut W { + pub fn in_(self) -> &'a mut crate::W { self.variant(TEMPCMPMODSELECT_A::IN) } #[doc = "Generates an event when the converted data is out of the comparison window."] #[inline(always)] - pub fn out(self) -> &'a mut W { + pub fn out(self) -> &'a mut crate::W { self.variant(TEMPCMPMODSELECT_A::OUT) } } @@ -136,34 +108,31 @@ impl W { #[doc = "Bit 0 - Temperature Sensor RTC Trigger Mode"] #[inline(always)] #[must_use] - pub fn rtct(&mut self) -> RTCT_W<0> { + pub fn rtct(&mut self) -> RTCT_W { RTCT_W::new(self) } #[doc = "Bits 4:5 - Temperature Comparison Mode"] #[inline(always)] #[must_use] - pub fn tempcmpmod(&mut self) -> TEMPCMPMOD_W<4> { + pub fn tempcmpmod(&mut self) -> TEMPCMPMOD_W { TEMPCMPMOD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Temperature Sensor Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tempmr](index.html) module"] +#[doc = "AFEC Temperature Sensor Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tempmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tempmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TEMPMR_SPEC; impl crate::RegisterSpec for TEMPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tempmr::R](R) reader structure"] -impl crate::Readable for TEMPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tempmr::W](W) writer structure"] +#[doc = "`read()` method returns [`tempmr::R`](R) reader structure"] +impl crate::Readable for TEMPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tempmr::W`](W) writer structure"] impl crate::Writable for TEMPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/wpmr.rs index 8ad22b9b..22b73159 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protect KEY"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protect KEY\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protect KEY"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protect KEY"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AFEC Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "AFEC Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/afec0/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/afec0/wpsr.rs index 73440fc2..1f6b6457 100644 --- a/arch/cortex-m/samv71q21-pac/src/afec0/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/afec0/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protect Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protect Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "AFEC Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "AFEC Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/chipid.rs b/arch/cortex-m/samv71q21-pac/src/chipid.rs index c731c971..6315f2bc 100644 --- a/arch/cortex-m/samv71q21-pac/src/chipid.rs +++ b/arch/cortex-m/samv71q21-pac/src/chipid.rs @@ -6,11 +6,13 @@ pub struct RegisterBlock { #[doc = "0x04 - Chip ID Extension Register"] pub exid: EXID, } -#[doc = "CIDR (r) register accessor: an alias for `Reg`"] +#[doc = "CIDR (r) register accessor: Chip ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cidr`] +module"] pub type CIDR = crate::Reg; #[doc = "Chip ID Register"] pub mod cidr; -#[doc = "EXID (r) register accessor: an alias for `Reg`"] +#[doc = "EXID (r) register accessor: Chip ID Extension Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`exid`] +module"] pub type EXID = crate::Reg; #[doc = "Chip ID Extension Register"] pub mod exid; diff --git a/arch/cortex-m/samv71q21-pac/src/chipid/cidr.rs b/arch/cortex-m/samv71q21-pac/src/chipid/cidr.rs index 3ac975b3..8510e491 100644 --- a/arch/cortex-m/samv71q21-pac/src/chipid/cidr.rs +++ b/arch/cortex-m/samv71q21-pac/src/chipid/cidr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `VERSION` reader - Version of the Device"] pub type VERSION_R = crate::FieldReader; #[doc = "Field `EPROC` reader - Embedded Processor"] @@ -63,42 +50,42 @@ impl EPROC_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SAMX7`"] + #[doc = "Cortex-M7"] #[inline(always)] pub fn is_samx7(&self) -> bool { *self == EPROCSELECT_A::SAMX7 } - #[doc = "Checks if the value of the field is `ARM946ES`"] + #[doc = "ARM946ES"] #[inline(always)] pub fn is_arm946es(&self) -> bool { *self == EPROCSELECT_A::ARM946ES } - #[doc = "Checks if the value of the field is `ARM7TDMI`"] + #[doc = "ARM7TDMI"] #[inline(always)] pub fn is_arm7tdmi(&self) -> bool { *self == EPROCSELECT_A::ARM7TDMI } - #[doc = "Checks if the value of the field is `CM3`"] + #[doc = "Cortex-M3"] #[inline(always)] pub fn is_cm3(&self) -> bool { *self == EPROCSELECT_A::CM3 } - #[doc = "Checks if the value of the field is `ARM920T`"] + #[doc = "ARM920T"] #[inline(always)] pub fn is_arm920t(&self) -> bool { *self == EPROCSELECT_A::ARM920T } - #[doc = "Checks if the value of the field is `ARM926EJS`"] + #[doc = "ARM926EJS"] #[inline(always)] pub fn is_arm926ejs(&self) -> bool { *self == EPROCSELECT_A::ARM926EJS } - #[doc = "Checks if the value of the field is `CA5`"] + #[doc = "Cortex-A5"] #[inline(always)] pub fn is_ca5(&self) -> bool { *self == EPROCSELECT_A::CA5 } - #[doc = "Checks if the value of the field is `CM4`"] + #[doc = "Cortex-M4"] #[inline(always)] pub fn is_cm4(&self) -> bool { *self == EPROCSELECT_A::CM4 @@ -161,57 +148,57 @@ impl NVPSIZ_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None"] #[inline(always)] pub fn is_none(&self) -> bool { *self == NVPSIZSELECT_A::NONE } - #[doc = "Checks if the value of the field is `_8K`"] + #[doc = "8 Kbytes"] #[inline(always)] pub fn is_8k(&self) -> bool { *self == NVPSIZSELECT_A::_8K } - #[doc = "Checks if the value of the field is `_16K`"] + #[doc = "16 Kbytes"] #[inline(always)] pub fn is_16k(&self) -> bool { *self == NVPSIZSELECT_A::_16K } - #[doc = "Checks if the value of the field is `_32K`"] + #[doc = "32 Kbytes"] #[inline(always)] pub fn is_32k(&self) -> bool { *self == NVPSIZSELECT_A::_32K } - #[doc = "Checks if the value of the field is `_64K`"] + #[doc = "64 Kbytes"] #[inline(always)] pub fn is_64k(&self) -> bool { *self == NVPSIZSELECT_A::_64K } - #[doc = "Checks if the value of the field is `_128K`"] + #[doc = "128 Kbytes"] #[inline(always)] pub fn is_128k(&self) -> bool { *self == NVPSIZSELECT_A::_128K } - #[doc = "Checks if the value of the field is `_160K`"] + #[doc = "160 Kbytes"] #[inline(always)] pub fn is_160k(&self) -> bool { *self == NVPSIZSELECT_A::_160K } - #[doc = "Checks if the value of the field is `_256K`"] + #[doc = "256 Kbytes"] #[inline(always)] pub fn is_256k(&self) -> bool { *self == NVPSIZSELECT_A::_256K } - #[doc = "Checks if the value of the field is `_512K`"] + #[doc = "512 Kbytes"] #[inline(always)] pub fn is_512k(&self) -> bool { *self == NVPSIZSELECT_A::_512K } - #[doc = "Checks if the value of the field is `_1024K`"] + #[doc = "1024 Kbytes"] #[inline(always)] pub fn is_1024k(&self) -> bool { *self == NVPSIZSELECT_A::_1024K } - #[doc = "Checks if the value of the field is `_2048K`"] + #[doc = "2048 Kbytes"] #[inline(always)] pub fn is_2048k(&self) -> bool { *self == NVPSIZSELECT_A::_2048K @@ -271,52 +258,52 @@ impl NVPSIZ2_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None"] #[inline(always)] pub fn is_none(&self) -> bool { *self == NVPSIZ2SELECT_A::NONE } - #[doc = "Checks if the value of the field is `_8K`"] + #[doc = "8 Kbytes"] #[inline(always)] pub fn is_8k(&self) -> bool { *self == NVPSIZ2SELECT_A::_8K } - #[doc = "Checks if the value of the field is `_16K`"] + #[doc = "16 Kbytes"] #[inline(always)] pub fn is_16k(&self) -> bool { *self == NVPSIZ2SELECT_A::_16K } - #[doc = "Checks if the value of the field is `_32K`"] + #[doc = "32 Kbytes"] #[inline(always)] pub fn is_32k(&self) -> bool { *self == NVPSIZ2SELECT_A::_32K } - #[doc = "Checks if the value of the field is `_64K`"] + #[doc = "64 Kbytes"] #[inline(always)] pub fn is_64k(&self) -> bool { *self == NVPSIZ2SELECT_A::_64K } - #[doc = "Checks if the value of the field is `_128K`"] + #[doc = "128 Kbytes"] #[inline(always)] pub fn is_128k(&self) -> bool { *self == NVPSIZ2SELECT_A::_128K } - #[doc = "Checks if the value of the field is `_256K`"] + #[doc = "256 Kbytes"] #[inline(always)] pub fn is_256k(&self) -> bool { *self == NVPSIZ2SELECT_A::_256K } - #[doc = "Checks if the value of the field is `_512K`"] + #[doc = "512 Kbytes"] #[inline(always)] pub fn is_512k(&self) -> bool { *self == NVPSIZ2SELECT_A::_512K } - #[doc = "Checks if the value of the field is `_1024K`"] + #[doc = "1024 Kbytes"] #[inline(always)] pub fn is_1024k(&self) -> bool { *self == NVPSIZ2SELECT_A::_1024K } - #[doc = "Checks if the value of the field is `_2048K`"] + #[doc = "2048 Kbytes"] #[inline(always)] pub fn is_2048k(&self) -> bool { *self == NVPSIZ2SELECT_A::_2048K @@ -394,82 +381,82 @@ impl SRAMSIZ_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_48K`"] + #[doc = "48 Kbytes"] #[inline(always)] pub fn is_48k(&self) -> bool { *self == SRAMSIZSELECT_A::_48K } - #[doc = "Checks if the value of the field is `_192K`"] + #[doc = "192 Kbytes"] #[inline(always)] pub fn is_192k(&self) -> bool { *self == SRAMSIZSELECT_A::_192K } - #[doc = "Checks if the value of the field is `_384K`"] + #[doc = "384 Kbytes"] #[inline(always)] pub fn is_384k(&self) -> bool { *self == SRAMSIZSELECT_A::_384K } - #[doc = "Checks if the value of the field is `_6K`"] + #[doc = "6 Kbytes"] #[inline(always)] pub fn is_6k(&self) -> bool { *self == SRAMSIZSELECT_A::_6K } - #[doc = "Checks if the value of the field is `_24K`"] + #[doc = "24 Kbytes"] #[inline(always)] pub fn is_24k(&self) -> bool { *self == SRAMSIZSELECT_A::_24K } - #[doc = "Checks if the value of the field is `_4K`"] + #[doc = "4 Kbytes"] #[inline(always)] pub fn is_4k(&self) -> bool { *self == SRAMSIZSELECT_A::_4K } - #[doc = "Checks if the value of the field is `_80K`"] + #[doc = "80 Kbytes"] #[inline(always)] pub fn is_80k(&self) -> bool { *self == SRAMSIZSELECT_A::_80K } - #[doc = "Checks if the value of the field is `_160K`"] + #[doc = "160 Kbytes"] #[inline(always)] pub fn is_160k(&self) -> bool { *self == SRAMSIZSELECT_A::_160K } - #[doc = "Checks if the value of the field is `_8K`"] + #[doc = "8 Kbytes"] #[inline(always)] pub fn is_8k(&self) -> bool { *self == SRAMSIZSELECT_A::_8K } - #[doc = "Checks if the value of the field is `_16K`"] + #[doc = "16 Kbytes"] #[inline(always)] pub fn is_16k(&self) -> bool { *self == SRAMSIZSELECT_A::_16K } - #[doc = "Checks if the value of the field is `_32K`"] + #[doc = "32 Kbytes"] #[inline(always)] pub fn is_32k(&self) -> bool { *self == SRAMSIZSELECT_A::_32K } - #[doc = "Checks if the value of the field is `_64K`"] + #[doc = "64 Kbytes"] #[inline(always)] pub fn is_64k(&self) -> bool { *self == SRAMSIZSELECT_A::_64K } - #[doc = "Checks if the value of the field is `_128K`"] + #[doc = "128 Kbytes"] #[inline(always)] pub fn is_128k(&self) -> bool { *self == SRAMSIZSELECT_A::_128K } - #[doc = "Checks if the value of the field is `_256K`"] + #[doc = "256 Kbytes"] #[inline(always)] pub fn is_256k(&self) -> bool { *self == SRAMSIZSELECT_A::_256K } - #[doc = "Checks if the value of the field is `_96K`"] + #[doc = "96 Kbytes"] #[inline(always)] pub fn is_96k(&self) -> bool { *self == SRAMSIZSELECT_A::_96K } - #[doc = "Checks if the value of the field is `_512K`"] + #[doc = "512 Kbytes"] #[inline(always)] pub fn is_512k(&self) -> bool { *self == SRAMSIZSELECT_A::_512K @@ -511,22 +498,22 @@ impl ARCH_R { _ => None, } } - #[doc = "Checks if the value of the field is `SAME70`"] + #[doc = "SAM E70"] #[inline(always)] pub fn is_same70(&self) -> bool { *self == ARCHSELECT_A::SAME70 } - #[doc = "Checks if the value of the field is `SAMS70`"] + #[doc = "SAM S70"] #[inline(always)] pub fn is_sams70(&self) -> bool { *self == ARCHSELECT_A::SAMS70 } - #[doc = "Checks if the value of the field is `SAMV71`"] + #[doc = "SAM V71"] #[inline(always)] pub fn is_samv71(&self) -> bool { *self == ARCHSELECT_A::SAMV71 } - #[doc = "Checks if the value of the field is `SAMV70`"] + #[doc = "SAM V70"] #[inline(always)] pub fn is_samv70(&self) -> bool { *self == ARCHSELECT_A::SAMV70 @@ -571,27 +558,27 @@ impl NVPTYP_R { _ => None, } } - #[doc = "Checks if the value of the field is `ROM`"] + #[doc = "ROM"] #[inline(always)] pub fn is_rom(&self) -> bool { *self == NVPTYPSELECT_A::ROM } - #[doc = "Checks if the value of the field is `ROMLESS`"] + #[doc = "ROMless or on-chip Flash"] #[inline(always)] pub fn is_romless(&self) -> bool { *self == NVPTYPSELECT_A::ROMLESS } - #[doc = "Checks if the value of the field is `FLASH`"] + #[doc = "Embedded Flash Memory"] #[inline(always)] pub fn is_flash(&self) -> bool { *self == NVPTYPSELECT_A::FLASH } - #[doc = "Checks if the value of the field is `ROM_FLASH`"] + #[doc = "ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size"] #[inline(always)] pub fn is_rom_flash(&self) -> bool { *self == NVPTYPSELECT_A::ROM_FLASH } - #[doc = "Checks if the value of the field is `SRAM`"] + #[doc = "SRAM emulating ROM"] #[inline(always)] pub fn is_sram(&self) -> bool { *self == NVPTYPSELECT_A::SRAM @@ -641,15 +628,13 @@ impl R { EXT_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Chip ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cidr](index.html) module"] +#[doc = "Chip ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIDR_SPEC; impl crate::RegisterSpec for CIDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cidr::R](R) reader structure"] -impl crate::Readable for CIDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cidr::R`](R) reader structure"] +impl crate::Readable for CIDR_SPEC {} #[doc = "`reset()` method sets CIDR to value 0"] impl crate::Resettable for CIDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/chipid/exid.rs b/arch/cortex-m/samv71q21-pac/src/chipid/exid.rs index 4f952a38..47171f8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/chipid/exid.rs +++ b/arch/cortex-m/samv71q21-pac/src/chipid/exid.rs @@ -1,18 +1,5 @@ #[doc = "Register `EXID` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EXID` reader - Chip ID Extension"] pub type EXID_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { EXID_R::new(self.bits) } } -#[doc = "Chip ID Extension Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [exid](index.html) module"] +#[doc = "Chip ID Extension Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EXID_SPEC; impl crate::RegisterSpec for EXID_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [exid::R](R) reader structure"] -impl crate::Readable for EXID_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`exid::R`](R) reader structure"] +impl crate::Readable for EXID_SPEC {} #[doc = "`reset()` method sets EXID to value 0"] impl crate::Resettable for EXID_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/core_debug.rs b/arch/cortex-m/samv71q21-pac/src/core_debug.rs index c6a6ef81..4ac0a29f 100644 --- a/arch/cortex-m/samv71q21-pac/src/core_debug.rs +++ b/arch/cortex-m/samv71q21-pac/src/core_debug.rs @@ -11,19 +11,23 @@ pub struct RegisterBlock { #[doc = "0xfc - Debug Exception and Monitor Control Register"] pub demcr: DEMCR, } -#[doc = "DHCSR (rw) register accessor: an alias for `Reg`"] +#[doc = "DHCSR (rw) register accessor: Debug Halting Control and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dhcsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dhcsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dhcsr`] +module"] pub type DHCSR = crate::Reg; #[doc = "Debug Halting Control and Status Register"] pub mod dhcsr; -#[doc = "DCRSR (w) register accessor: an alias for `Reg`"] +#[doc = "DCRSR (w) register accessor: Debug Core Register Selector Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcrsr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dcrsr`] +module"] pub type DCRSR = crate::Reg; #[doc = "Debug Core Register Selector Register"] pub mod dcrsr; -#[doc = "DCRDR (rw) register accessor: an alias for `Reg`"] +#[doc = "DCRDR (rw) register accessor: Debug Core Register Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcrdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcrdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dcrdr`] +module"] pub type DCRDR = crate::Reg; #[doc = "Debug Core Register Data Register"] pub mod dcrdr; -#[doc = "DEMCR (rw) register accessor: an alias for `Reg`"] +#[doc = "DEMCR (rw) register accessor: Debug Exception and Monitor Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`demcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`demcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`demcr`] +module"] pub type DEMCR = crate::Reg; #[doc = "Debug Exception and Monitor Control Register"] pub mod demcr; diff --git a/arch/cortex-m/samv71q21-pac/src/core_debug/dcrdr.rs b/arch/cortex-m/samv71q21-pac/src/core_debug/dcrdr.rs index 8c602d3b..3f8f0be4 100644 --- a/arch/cortex-m/samv71q21-pac/src/core_debug/dcrdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/core_debug/dcrdr.rs @@ -1,39 +1,7 @@ #[doc = "Register `DCRDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCRDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Debug Core Register Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcrdr](index.html) module"] +#[doc = "Debug Core Register Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcrdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcrdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCRDR_SPEC; impl crate::RegisterSpec for DCRDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dcrdr::R](R) reader structure"] -impl crate::Readable for DCRDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dcrdr::W](W) writer structure"] +#[doc = "`read()` method returns [`dcrdr::R`](R) reader structure"] +impl crate::Readable for DCRDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcrdr::W`](W) writer structure"] impl crate::Writable for DCRDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/core_debug/dcrsr.rs b/arch/cortex-m/samv71q21-pac/src/core_debug/dcrsr.rs index 4a2d428b..e29a1aaf 100644 --- a/arch/cortex-m/samv71q21-pac/src/core_debug/dcrsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/core_debug/dcrsr.rs @@ -1,56 +1,36 @@ #[doc = "Register `DCRSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `REGSEL` writer - "] -pub type REGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, DCRSR_SPEC, 5, O>; +pub type REGSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `REGWnR` writer - "] -pub type REGWN_R_W<'a, const O: u8> = crate::BitWriter<'a, DCRSR_SPEC, O>; +pub type REGWN_R_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:4"] #[inline(always)] #[must_use] - pub fn regsel(&mut self) -> REGSEL_W<0> { + pub fn regsel(&mut self) -> REGSEL_W { REGSEL_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn regwn_r(&mut self) -> REGWN_R_W<16> { + pub fn regwn_r(&mut self) -> REGWN_R_W { REGWN_R_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Debug Core Register Selector Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcrsr](index.html) module"] +#[doc = "Debug Core Register Selector Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcrsr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCRSR_SPEC; impl crate::RegisterSpec for DCRSR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [dcrsr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`dcrsr::W`](W) writer structure"] impl crate::Writable for DCRSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/core_debug/demcr.rs b/arch/cortex-m/samv71q21-pac/src/core_debug/demcr.rs index 819ec9e5..bf4ac559 100644 --- a/arch/cortex-m/samv71q21-pac/src/core_debug/demcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/core_debug/demcr.rs @@ -1,91 +1,59 @@ #[doc = "Register `DEMCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEMCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VC_CORERESET` reader - "] pub type VC_CORERESET_R = crate::BitReader; #[doc = "Field `VC_CORERESET` writer - "] -pub type VC_CORERESET_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_CORERESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_MMERR` reader - "] pub type VC_MMERR_R = crate::BitReader; #[doc = "Field `VC_MMERR` writer - "] -pub type VC_MMERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_MMERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_NOCPERR` reader - "] pub type VC_NOCPERR_R = crate::BitReader; #[doc = "Field `VC_NOCPERR` writer - "] -pub type VC_NOCPERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_NOCPERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_CHKERR` reader - "] pub type VC_CHKERR_R = crate::BitReader; #[doc = "Field `VC_CHKERR` writer - "] -pub type VC_CHKERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_CHKERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_STATERR` reader - "] pub type VC_STATERR_R = crate::BitReader; #[doc = "Field `VC_STATERR` writer - "] -pub type VC_STATERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_STATERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_BUSERR` reader - "] pub type VC_BUSERR_R = crate::BitReader; #[doc = "Field `VC_BUSERR` writer - "] -pub type VC_BUSERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_BUSERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_INTERR` reader - "] pub type VC_INTERR_R = crate::BitReader; #[doc = "Field `VC_INTERR` writer - "] -pub type VC_INTERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_INTERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VC_HARDERR` reader - "] pub type VC_HARDERR_R = crate::BitReader; #[doc = "Field `VC_HARDERR` writer - "] -pub type VC_HARDERR_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type VC_HARDERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MON_EN` reader - "] pub type MON_EN_R = crate::BitReader; #[doc = "Field `MON_EN` writer - "] -pub type MON_EN_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type MON_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MON_PEND` reader - "] pub type MON_PEND_R = crate::BitReader; #[doc = "Field `MON_PEND` writer - "] -pub type MON_PEND_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type MON_PEND_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MON_STEP` reader - "] pub type MON_STEP_R = crate::BitReader; #[doc = "Field `MON_STEP` writer - "] -pub type MON_STEP_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type MON_STEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MON_REQ` reader - "] pub type MON_REQ_R = crate::BitReader; #[doc = "Field `MON_REQ` writer - "] -pub type MON_REQ_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type MON_REQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRCENA` reader - "] pub type TRCENA_R = crate::BitReader; #[doc = "Field `TRCENA` writer - "] -pub type TRCENA_W<'a, const O: u8> = crate::BitWriter<'a, DEMCR_SPEC, O>; +pub type TRCENA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -157,100 +125,97 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn vc_corereset(&mut self) -> VC_CORERESET_W<0> { + pub fn vc_corereset(&mut self) -> VC_CORERESET_W { VC_CORERESET_W::new(self) } #[doc = "Bit 4"] #[inline(always)] #[must_use] - pub fn vc_mmerr(&mut self) -> VC_MMERR_W<4> { + pub fn vc_mmerr(&mut self) -> VC_MMERR_W { VC_MMERR_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn vc_nocperr(&mut self) -> VC_NOCPERR_W<5> { + pub fn vc_nocperr(&mut self) -> VC_NOCPERR_W { VC_NOCPERR_W::new(self) } #[doc = "Bit 6"] #[inline(always)] #[must_use] - pub fn vc_chkerr(&mut self) -> VC_CHKERR_W<6> { + pub fn vc_chkerr(&mut self) -> VC_CHKERR_W { VC_CHKERR_W::new(self) } #[doc = "Bit 7"] #[inline(always)] #[must_use] - pub fn vc_staterr(&mut self) -> VC_STATERR_W<7> { + pub fn vc_staterr(&mut self) -> VC_STATERR_W { VC_STATERR_W::new(self) } #[doc = "Bit 8"] #[inline(always)] #[must_use] - pub fn vc_buserr(&mut self) -> VC_BUSERR_W<8> { + pub fn vc_buserr(&mut self) -> VC_BUSERR_W { VC_BUSERR_W::new(self) } #[doc = "Bit 9"] #[inline(always)] #[must_use] - pub fn vc_interr(&mut self) -> VC_INTERR_W<9> { + pub fn vc_interr(&mut self) -> VC_INTERR_W { VC_INTERR_W::new(self) } #[doc = "Bit 10"] #[inline(always)] #[must_use] - pub fn vc_harderr(&mut self) -> VC_HARDERR_W<10> { + pub fn vc_harderr(&mut self) -> VC_HARDERR_W { VC_HARDERR_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn mon_en(&mut self) -> MON_EN_W<16> { + pub fn mon_en(&mut self) -> MON_EN_W { MON_EN_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn mon_pend(&mut self) -> MON_PEND_W<17> { + pub fn mon_pend(&mut self) -> MON_PEND_W { MON_PEND_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn mon_step(&mut self) -> MON_STEP_W<18> { + pub fn mon_step(&mut self) -> MON_STEP_W { MON_STEP_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn mon_req(&mut self) -> MON_REQ_W<19> { + pub fn mon_req(&mut self) -> MON_REQ_W { MON_REQ_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn trcena(&mut self) -> TRCENA_W<24> { + pub fn trcena(&mut self) -> TRCENA_W { TRCENA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Debug Exception and Monitor Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [demcr](index.html) module"] +#[doc = "Debug Exception and Monitor Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`demcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`demcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEMCR_SPEC; impl crate::RegisterSpec for DEMCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [demcr::R](R) reader structure"] -impl crate::Readable for DEMCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [demcr::W](W) writer structure"] +#[doc = "`read()` method returns [`demcr::R`](R) reader structure"] +impl crate::Readable for DEMCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`demcr::W`](W) writer structure"] impl crate::Writable for DEMCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/core_debug/dhcsr.rs b/arch/cortex-m/samv71q21-pac/src/core_debug/dhcsr.rs index 876304cc..0103d692 100644 --- a/arch/cortex-m/samv71q21-pac/src/core_debug/dhcsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/core_debug/dhcsr.rs @@ -1,83 +1,51 @@ #[doc = "Register `DHCSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DHCSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C_DEBUGEN` reader - "] pub type C_DEBUGEN_R = crate::BitReader; #[doc = "Field `C_DEBUGEN` writer - "] -pub type C_DEBUGEN_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type C_DEBUGEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_HALT` reader - "] pub type C_HALT_R = crate::BitReader; #[doc = "Field `C_HALT` writer - "] -pub type C_HALT_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type C_HALT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_STEP` reader - "] pub type C_STEP_R = crate::BitReader; #[doc = "Field `C_STEP` writer - "] -pub type C_STEP_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type C_STEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_MASKINTS` reader - "] pub type C_MASKINTS_R = crate::BitReader; #[doc = "Field `C_MASKINTS` writer - "] -pub type C_MASKINTS_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type C_MASKINTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_SNAPSTALL` reader - "] pub type C_SNAPSTALL_R = crate::BitReader; #[doc = "Field `C_SNAPSTALL` writer - "] -pub type C_SNAPSTALL_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type C_SNAPSTALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `S_REGRDY` reader - "] pub type S_REGRDY_R = crate::BitReader; #[doc = "Field `S_REGRDY` writer - "] -pub type S_REGRDY_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type S_REGRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `S_HALT` reader - "] pub type S_HALT_R = crate::BitReader; #[doc = "Field `S_HALT` writer - "] -pub type S_HALT_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type S_HALT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `S_SLEEP` reader - "] pub type S_SLEEP_R = crate::BitReader; #[doc = "Field `S_SLEEP` writer - "] -pub type S_SLEEP_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type S_SLEEP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `S_LOCKUP` reader - "] pub type S_LOCKUP_R = crate::BitReader; #[doc = "Field `S_LOCKUP` writer - "] -pub type S_LOCKUP_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type S_LOCKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `S_RETIRE_ST` reader - "] pub type S_RETIRE_ST_R = crate::BitReader; #[doc = "Field `S_RETIRE_ST` writer - "] -pub type S_RETIRE_ST_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type S_RETIRE_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `S_RESET_ST` reader - "] pub type S_RESET_ST_R = crate::BitReader; #[doc = "Field `S_RESET_ST` writer - "] -pub type S_RESET_ST_W<'a, const O: u8> = crate::BitWriter<'a, DHCSR_SPEC, O>; +pub type S_RESET_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -139,88 +107,85 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn c_debugen(&mut self) -> C_DEBUGEN_W<0> { + pub fn c_debugen(&mut self) -> C_DEBUGEN_W { C_DEBUGEN_W::new(self) } #[doc = "Bit 1"] #[inline(always)] #[must_use] - pub fn c_halt(&mut self) -> C_HALT_W<1> { + pub fn c_halt(&mut self) -> C_HALT_W { C_HALT_W::new(self) } #[doc = "Bit 2"] #[inline(always)] #[must_use] - pub fn c_step(&mut self) -> C_STEP_W<2> { + pub fn c_step(&mut self) -> C_STEP_W { C_STEP_W::new(self) } #[doc = "Bit 3"] #[inline(always)] #[must_use] - pub fn c_maskints(&mut self) -> C_MASKINTS_W<3> { + pub fn c_maskints(&mut self) -> C_MASKINTS_W { C_MASKINTS_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn c_snapstall(&mut self) -> C_SNAPSTALL_W<5> { + pub fn c_snapstall(&mut self) -> C_SNAPSTALL_W { C_SNAPSTALL_W::new(self) } #[doc = "Bit 16"] #[inline(always)] #[must_use] - pub fn s_regrdy(&mut self) -> S_REGRDY_W<16> { + pub fn s_regrdy(&mut self) -> S_REGRDY_W { S_REGRDY_W::new(self) } #[doc = "Bit 17"] #[inline(always)] #[must_use] - pub fn s_halt(&mut self) -> S_HALT_W<17> { + pub fn s_halt(&mut self) -> S_HALT_W { S_HALT_W::new(self) } #[doc = "Bit 18"] #[inline(always)] #[must_use] - pub fn s_sleep(&mut self) -> S_SLEEP_W<18> { + pub fn s_sleep(&mut self) -> S_SLEEP_W { S_SLEEP_W::new(self) } #[doc = "Bit 19"] #[inline(always)] #[must_use] - pub fn s_lockup(&mut self) -> S_LOCKUP_W<19> { + pub fn s_lockup(&mut self) -> S_LOCKUP_W { S_LOCKUP_W::new(self) } #[doc = "Bit 24"] #[inline(always)] #[must_use] - pub fn s_retire_st(&mut self) -> S_RETIRE_ST_W<24> { + pub fn s_retire_st(&mut self) -> S_RETIRE_ST_W { S_RETIRE_ST_W::new(self) } #[doc = "Bit 25"] #[inline(always)] #[must_use] - pub fn s_reset_st(&mut self) -> S_RESET_ST_W<25> { + pub fn s_reset_st(&mut self) -> S_RESET_ST_W { S_RESET_ST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Debug Halting Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dhcsr](index.html) module"] +#[doc = "Debug Halting Control and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dhcsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dhcsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DHCSR_SPEC; impl crate::RegisterSpec for DHCSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dhcsr::R](R) reader structure"] -impl crate::Readable for DHCSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dhcsr::W](W) writer structure"] +#[doc = "`read()` method returns [`dhcsr::R`](R) reader structure"] +impl crate::Readable for DHCSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dhcsr::W`](W) writer structure"] impl crate::Writable for DHCSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc.rs b/arch/cortex-m/samv71q21-pac/src/dacc.rs index f51d16e7..865cd178 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc.rs @@ -33,59 +33,73 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "TRIGR (rw) register accessor: an alias for `Reg`"] +#[doc = "TRIGR (rw) register accessor: Trigger Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`trigr`] +module"] pub type TRIGR = crate::Reg; #[doc = "Trigger Register"] pub mod trigr; -#[doc = "CHER (w) register accessor: an alias for `Reg`"] +#[doc = "CHER (w) register accessor: Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cher::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cher`] +module"] pub type CHER = crate::Reg; #[doc = "Channel Enable Register"] pub mod cher; -#[doc = "CHDR (w) register accessor: an alias for `Reg`"] +#[doc = "CHDR (w) register accessor: Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`chdr`] +module"] pub type CHDR = crate::Reg; #[doc = "Channel Disable Register"] pub mod chdr; -#[doc = "CHSR (r) register accessor: an alias for `Reg`"] +#[doc = "CHSR (r) register accessor: Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`chsr`] +module"] pub type CHSR = crate::Reg; #[doc = "Channel Status Register"] pub mod chsr; -#[doc = "CDR (w) register accessor: an alias for `Reg`"] +#[doc = "CDR (w) register accessor: Conversion Data Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cdr`] +module"] pub type CDR = crate::Reg; #[doc = "Conversion Data Register 0"] pub mod cdr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "ACR (rw) register accessor: an alias for `Reg`"] +#[doc = "ACR (rw) register accessor: Analog Current Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`acr`] +module"] pub type ACR = crate::Reg; #[doc = "Analog Current Register"] pub mod acr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/acr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/acr.rs index 0f3bc71c..d4cb6f4b 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/acr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/acr.rs @@ -1,47 +1,15 @@ #[doc = "Register `ACR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IBCTLCH0` reader - Analog Output Current Control"] pub type IBCTLCH0_R = crate::FieldReader; #[doc = "Field `IBCTLCH0` writer - Analog Output Current Control"] -pub type IBCTLCH0_W<'a, const O: u8> = crate::FieldWriter<'a, ACR_SPEC, 2, O>; +pub type IBCTLCH0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `IBCTLCH1` reader - Analog Output Current Control"] pub type IBCTLCH1_R = crate::FieldReader; #[doc = "Field `IBCTLCH1` writer - Analog Output Current Control"] -pub type IBCTLCH1_W<'a, const O: u8> = crate::FieldWriter<'a, ACR_SPEC, 2, O>; +pub type IBCTLCH1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Analog Output Current Control"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:1 - Analog Output Current Control"] #[inline(always)] #[must_use] - pub fn ibctlch0(&mut self) -> IBCTLCH0_W<0> { + pub fn ibctlch0(&mut self) -> IBCTLCH0_W { IBCTLCH0_W::new(self) } #[doc = "Bits 2:3 - Analog Output Current Control"] #[inline(always)] #[must_use] - pub fn ibctlch1(&mut self) -> IBCTLCH1_W<2> { + pub fn ibctlch1(&mut self) -> IBCTLCH1_W { IBCTLCH1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Analog Current Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acr](index.html) module"] +#[doc = "Analog Current Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACR_SPEC; impl crate::RegisterSpec for ACR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [acr::R](R) reader structure"] -impl crate::Readable for ACR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [acr::W](W) writer structure"] +#[doc = "`read()` method returns [`acr::R`](R) reader structure"] +impl crate::Readable for ACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`acr::W`](W) writer structure"] impl crate::Writable for ACR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/cdr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/cdr.rs index 0657df1c..2144813f 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/cdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/cdr.rs @@ -1,56 +1,36 @@ #[doc = "Register `CDR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA0` writer - Data to Convert for channel 0"] -pub type DATA0_W<'a, const O: u8> = crate::FieldWriter<'a, CDR_SPEC, 16, O, u16>; +pub type DATA0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `DATA1` writer - Data to Convert for channel 1"] -pub type DATA1_W<'a, const O: u8> = crate::FieldWriter<'a, CDR_SPEC, 16, O, u16>; +pub type DATA1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl W { #[doc = "Bits 0:15 - Data to Convert for channel 0"] #[inline(always)] #[must_use] - pub fn data0(&mut self) -> DATA0_W<0> { + pub fn data0(&mut self) -> DATA0_W { DATA0_W::new(self) } #[doc = "Bits 16:31 - Data to Convert for channel 1"] #[inline(always)] #[must_use] - pub fn data1(&mut self) -> DATA1_W<16> { + pub fn data1(&mut self) -> DATA1_W { DATA1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Conversion Data Register 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cdr](index.html) module"] +#[doc = "Conversion Data Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDR_SPEC; impl crate::RegisterSpec for CDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cdr::W`](W) writer structure"] impl crate::Writable for CDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/chdr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/chdr.rs index ea367287..a1f68f74 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/chdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/chdr.rs @@ -1,56 +1,36 @@ #[doc = "Register `CHDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` writer - Channel 0 Disable"] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` writer - Channel 1 Disable"] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, CHDR_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Channel 0 Disable"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1 - Channel 1 Disable"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chdr](index.html) module"] +#[doc = "Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHDR_SPEC; impl crate::RegisterSpec for CHDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [chdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`chdr::W`](W) writer structure"] impl crate::Writable for CHDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/cher.rs b/arch/cortex-m/samv71q21-pac/src/dacc/cher.rs index f4a77532..3a32336d 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/cher.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/cher.rs @@ -1,56 +1,36 @@ #[doc = "Register `CHER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CH0` writer - Channel 0 Enable"] -pub type CH0_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CH1` writer - Channel 1 Enable"] -pub type CH1_W<'a, const O: u8> = crate::BitWriter<'a, CHER_SPEC, O>; +pub type CH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Channel 0 Enable"] #[inline(always)] #[must_use] - pub fn ch0(&mut self) -> CH0_W<0> { + pub fn ch0(&mut self) -> CH0_W { CH0_W::new(self) } #[doc = "Bit 1 - Channel 1 Enable"] #[inline(always)] #[must_use] - pub fn ch1(&mut self) -> CH1_W<1> { + pub fn ch1(&mut self) -> CH1_W { CH1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cher](index.html) module"] +#[doc = "Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cher::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHER_SPEC; impl crate::RegisterSpec for CHER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cher::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cher::W`](W) writer structure"] impl crate::Writable for CHER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/chsr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/chsr.rs index a98d43ec..d7f81c0e 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/chsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/chsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CHSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CH0` reader - Channel 0 Status"] pub type CH0_R = crate::BitReader; #[doc = "Field `CH1` reader - Channel 1 Status"] @@ -43,15 +30,13 @@ impl R { DACRDY1_R::new(((self.bits >> 9) & 1) != 0) } } -#[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chsr](index.html) module"] +#[doc = "Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CHSR_SPEC; impl crate::RegisterSpec for CHSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [chsr::R](R) reader structure"] -impl crate::Readable for CHSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`chsr::R`](R) reader structure"] +impl crate::Readable for CHSR_SPEC {} #[doc = "`reset()` method sets CHSR to value 0"] impl crate::Resettable for CHSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/cr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/cr.rs index 7bbc2331..c8f327a0 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/cr.rs @@ -1,48 +1,28 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<0> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/idr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/idr.rs index fcdeb024..1e8f31c5 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/idr.rs @@ -1,72 +1,52 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXRDY0` writer - Transmit Ready Interrupt Disable of channel 0"] -pub type TXRDY0_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY1` writer - Transmit Ready Interrupt Disable of channel 1"] -pub type TXRDY1_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC0` writer - End of Conversion Interrupt Disable of channel 0"] -pub type EOC0_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC1` writer - End of Conversion Interrupt Disable of channel 1"] -pub type EOC1_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmit Ready Interrupt Disable of channel 0"] #[inline(always)] #[must_use] - pub fn txrdy0(&mut self) -> TXRDY0_W<0> { + pub fn txrdy0(&mut self) -> TXRDY0_W { TXRDY0_W::new(self) } #[doc = "Bit 1 - Transmit Ready Interrupt Disable of channel 1"] #[inline(always)] #[must_use] - pub fn txrdy1(&mut self) -> TXRDY1_W<1> { + pub fn txrdy1(&mut self) -> TXRDY1_W { TXRDY1_W::new(self) } #[doc = "Bit 4 - End of Conversion Interrupt Disable of channel 0"] #[inline(always)] #[must_use] - pub fn eoc0(&mut self) -> EOC0_W<4> { + pub fn eoc0(&mut self) -> EOC0_W { EOC0_W::new(self) } #[doc = "Bit 5 - End of Conversion Interrupt Disable of channel 1"] #[inline(always)] #[must_use] - pub fn eoc1(&mut self) -> EOC1_W<5> { + pub fn eoc1(&mut self) -> EOC1_W { EOC1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/ier.rs b/arch/cortex-m/samv71q21-pac/src/dacc/ier.rs index 2382b3a3..a1f41c63 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/ier.rs @@ -1,72 +1,52 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXRDY0` writer - Transmit Ready Interrupt Enable of channel 0"] -pub type TXRDY0_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY1` writer - Transmit Ready Interrupt Enable of channel 1"] -pub type TXRDY1_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC0` writer - End of Conversion Interrupt Enable of channel 0"] -pub type EOC0_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOC1` writer - End of Conversion Interrupt Enable of channel 1"] -pub type EOC1_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmit Ready Interrupt Enable of channel 0"] #[inline(always)] #[must_use] - pub fn txrdy0(&mut self) -> TXRDY0_W<0> { + pub fn txrdy0(&mut self) -> TXRDY0_W { TXRDY0_W::new(self) } #[doc = "Bit 1 - Transmit Ready Interrupt Enable of channel 1"] #[inline(always)] #[must_use] - pub fn txrdy1(&mut self) -> TXRDY1_W<1> { + pub fn txrdy1(&mut self) -> TXRDY1_W { TXRDY1_W::new(self) } #[doc = "Bit 4 - End of Conversion Interrupt Enable of channel 0"] #[inline(always)] #[must_use] - pub fn eoc0(&mut self) -> EOC0_W<4> { + pub fn eoc0(&mut self) -> EOC0_W { EOC0_W::new(self) } #[doc = "Bit 5 - End of Conversion Interrupt Enable of channel 1"] #[inline(always)] #[must_use] - pub fn eoc1(&mut self) -> EOC1_W<5> { + pub fn eoc1(&mut self) -> EOC1_W { EOC1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/imr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/imr.rs index 7a147a91..6d66b79a 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXRDY0` reader - Transmit Ready Interrupt Mask of channel 0"] pub type TXRDY0_R = crate::BitReader; #[doc = "Field `TXRDY1` reader - Transmit Ready Interrupt Mask of channel 1"] @@ -43,15 +30,13 @@ impl R { EOC1_R::new(((self.bits >> 5) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/isr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/isr.rs index 8edcece4..97d83d84 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXRDY0` reader - Transmit Ready Interrupt Flag of channel 0"] pub type TXRDY0_R = crate::BitReader; #[doc = "Field `TXRDY1` reader - Transmit Ready Interrupt Flag of channel 1"] @@ -43,15 +30,13 @@ impl R { EOC1_R::new(((self.bits >> 5) & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/mr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/mr.rs index 43b84846..761cf48f 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MAXS0` reader - Max Speed Mode for Channel 0"] pub type MAXS0_R = crate::BitReader; #[doc = "Max Speed Mode for Channel 0\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl MAXS0_R { true => MAXS0SELECT_A::MAXIMUM, } } - #[doc = "Checks if the value of the field is `TRIG_EVENT`"] + #[doc = "External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)"] #[inline(always)] pub fn is_trig_event(&self) -> bool { *self == MAXS0SELECT_A::TRIG_EVENT } - #[doc = "Checks if the value of the field is `MAXIMUM`"] + #[doc = "Max speed mode enabled."] #[inline(always)] pub fn is_maximum(&self) -> bool { *self == MAXS0SELECT_A::MAXIMUM } } #[doc = "Field `MAXS0` writer - Max Speed Mode for Channel 0"] -pub type MAXS0_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, MAXS0SELECT_A>; -impl<'a, const O: u8> MAXS0_W<'a, O> { +pub type MAXS0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MAXS0SELECT_A>; +impl<'a, REG, const O: u8> MAXS0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)"] #[inline(always)] - pub fn trig_event(self) -> &'a mut W { + pub fn trig_event(self) -> &'a mut crate::W { self.variant(MAXS0SELECT_A::TRIG_EVENT) } #[doc = "Max speed mode enabled."] #[inline(always)] - pub fn maximum(self) -> &'a mut W { + pub fn maximum(self) -> &'a mut crate::W { self.variant(MAXS0SELECT_A::MAXIMUM) } } @@ -109,28 +80,31 @@ impl MAXS1_R { true => MAXS1SELECT_A::MAXIMUM, } } - #[doc = "Checks if the value of the field is `TRIG_EVENT`"] + #[doc = "External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)"] #[inline(always)] pub fn is_trig_event(&self) -> bool { *self == MAXS1SELECT_A::TRIG_EVENT } - #[doc = "Checks if the value of the field is `MAXIMUM`"] + #[doc = "Max speed mode enabled."] #[inline(always)] pub fn is_maximum(&self) -> bool { *self == MAXS1SELECT_A::MAXIMUM } } #[doc = "Field `MAXS1` writer - Max Speed Mode for Channel 1"] -pub type MAXS1_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, MAXS1SELECT_A>; -impl<'a, const O: u8> MAXS1_W<'a, O> { +pub type MAXS1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MAXS1SELECT_A>; +impl<'a, REG, const O: u8> MAXS1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.)"] #[inline(always)] - pub fn trig_event(self) -> &'a mut W { + pub fn trig_event(self) -> &'a mut crate::W { self.variant(MAXS1SELECT_A::TRIG_EVENT) } #[doc = "Max speed mode enabled."] #[inline(always)] - pub fn maximum(self) -> &'a mut W { + pub fn maximum(self) -> &'a mut crate::W { self.variant(MAXS1SELECT_A::MAXIMUM) } } @@ -159,35 +133,38 @@ impl WORD_R { true => WORDSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "One data to convert is written to the FIFO per access to DACC."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == WORDSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses)."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == WORDSELECT_A::ENABLED } } #[doc = "Field `WORD` writer - Word Transfer Mode"] -pub type WORD_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, WORDSELECT_A>; -impl<'a, const O: u8> WORD_W<'a, O> { +pub type WORD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WORDSELECT_A>; +impl<'a, REG, const O: u8> WORD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "One data to convert is written to the FIFO per access to DACC."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(WORDSELECT_A::DISABLED) } #[doc = "Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses)."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(WORDSELECT_A::ENABLED) } } #[doc = "Field `ZERO` reader - Must always be written to 0."] pub type ZERO_R = crate::BitReader; #[doc = "Field `ZERO` writer - Must always be written to 0."] -pub type ZERO_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type ZERO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIFF` reader - Differential Mode"] pub type DIFF_R = crate::BitReader; #[doc = "Differential Mode\n\nValue on reset: 0"] @@ -213,35 +190,38 @@ impl DIFF_R { true => DIFFSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "DAC0 and DAC1 are single-ended outputs."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == DIFFSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "DACP and DACN are differential outputs. The differential level is configured by the channel 0 value."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == DIFFSELECT_A::ENABLED } } #[doc = "Field `DIFF` writer - Differential Mode"] -pub type DIFF_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, DIFFSELECT_A>; -impl<'a, const O: u8> DIFF_W<'a, O> { +pub type DIFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DIFFSELECT_A>; +impl<'a, REG, const O: u8> DIFF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "DAC0 and DAC1 are single-ended outputs."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(DIFFSELECT_A::DISABLED) } #[doc = "DACP and DACN are differential outputs. The differential level is configured by the channel 0 value."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(DIFFSELECT_A::ENABLED) } } #[doc = "Field `PRESCALER` reader - Peripheral Clock to DAC Clock Ratio"] pub type PRESCALER_R = crate::FieldReader; #[doc = "Field `PRESCALER` writer - Peripheral Clock to DAC Clock Ratio"] -pub type PRESCALER_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O>; +pub type PRESCALER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Max Speed Mode for Channel 0"] #[inline(always)] @@ -278,58 +258,55 @@ impl W { #[doc = "Bit 0 - Max Speed Mode for Channel 0"] #[inline(always)] #[must_use] - pub fn maxs0(&mut self) -> MAXS0_W<0> { + pub fn maxs0(&mut self) -> MAXS0_W { MAXS0_W::new(self) } #[doc = "Bit 1 - Max Speed Mode for Channel 1"] #[inline(always)] #[must_use] - pub fn maxs1(&mut self) -> MAXS1_W<1> { + pub fn maxs1(&mut self) -> MAXS1_W { MAXS1_W::new(self) } #[doc = "Bit 4 - Word Transfer Mode"] #[inline(always)] #[must_use] - pub fn word(&mut self) -> WORD_W<4> { + pub fn word(&mut self) -> WORD_W { WORD_W::new(self) } #[doc = "Bit 5 - Must always be written to 0."] #[inline(always)] #[must_use] - pub fn zero(&mut self) -> ZERO_W<5> { + pub fn zero(&mut self) -> ZERO_W { ZERO_W::new(self) } #[doc = "Bit 23 - Differential Mode"] #[inline(always)] #[must_use] - pub fn diff(&mut self) -> DIFF_W<23> { + pub fn diff(&mut self) -> DIFF_W { DIFF_W::new(self) } #[doc = "Bits 24:27 - Peripheral Clock to DAC Clock Ratio"] #[inline(always)] #[must_use] - pub fn prescaler(&mut self) -> PRESCALER_W<24> { + pub fn prescaler(&mut self) -> PRESCALER_W { PRESCALER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/trigr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/trigr.rs index df54dcbf..83cea5c8 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/trigr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/trigr.rs @@ -1,39 +1,7 @@ #[doc = "Register `TRIGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TRIGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TRGEN0` reader - Trigger Enable of Channel 0"] pub type TRGEN0_R = crate::BitReader; #[doc = "Trigger Enable of Channel 0\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl TRGEN0_R { true => TRGEN0SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "External trigger mode disabled. DACC is in Free-running mode or Max speed mode."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == TRGEN0SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "External trigger mode enabled."] #[inline(always)] pub fn is_en(&self) -> bool { *self == TRGEN0SELECT_A::EN } } #[doc = "Field `TRGEN0` writer - Trigger Enable of Channel 0"] -pub type TRGEN0_W<'a, const O: u8> = crate::BitWriter<'a, TRIGR_SPEC, O, TRGEN0SELECT_A>; -impl<'a, const O: u8> TRGEN0_W<'a, O> { +pub type TRGEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRGEN0SELECT_A>; +impl<'a, REG, const O: u8> TRGEN0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "External trigger mode disabled. DACC is in Free-running mode or Max speed mode."] #[inline(always)] - pub fn dis(self) -> &'a mut W { + pub fn dis(self) -> &'a mut crate::W { self.variant(TRGEN0SELECT_A::DIS) } #[doc = "External trigger mode enabled."] #[inline(always)] - pub fn en(self) -> &'a mut W { + pub fn en(self) -> &'a mut crate::W { self.variant(TRGEN0SELECT_A::EN) } } @@ -109,28 +80,31 @@ impl TRGEN1_R { true => TRGEN1SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "External trigger mode disabled. DACC is in Free-running mode or Max speed mode."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == TRGEN1SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "External trigger mode enabled."] #[inline(always)] pub fn is_en(&self) -> bool { *self == TRGEN1SELECT_A::EN } } #[doc = "Field `TRGEN1` writer - Trigger Enable of Channel 1"] -pub type TRGEN1_W<'a, const O: u8> = crate::BitWriter<'a, TRIGR_SPEC, O, TRGEN1SELECT_A>; -impl<'a, const O: u8> TRGEN1_W<'a, O> { +pub type TRGEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRGEN1SELECT_A>; +impl<'a, REG, const O: u8> TRGEN1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "External trigger mode disabled. DACC is in Free-running mode or Max speed mode."] #[inline(always)] - pub fn dis(self) -> &'a mut W { + pub fn dis(self) -> &'a mut crate::W { self.variant(TRGEN1SELECT_A::DIS) } #[doc = "External trigger mode enabled."] #[inline(always)] - pub fn en(self) -> &'a mut W { + pub fn en(self) -> &'a mut crate::W { self.variant(TRGEN1SELECT_A::EN) } } @@ -182,88 +156,92 @@ impl TRGSEL0_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TRGSEL0`"] + #[doc = "DAC External Trigger Input (DATRG)"] #[inline(always)] pub fn is_trgsel0(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL0 } - #[doc = "Checks if the value of the field is `TRGSEL1`"] + #[doc = "TC0 Channel 0 Output (TIOA0)"] #[inline(always)] pub fn is_trgsel1(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL1 } - #[doc = "Checks if the value of the field is `TRGSEL2`"] + #[doc = "TC0 Channel 1 Output (TIOA1)"] #[inline(always)] pub fn is_trgsel2(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL2 } - #[doc = "Checks if the value of the field is `TRGSEL3`"] + #[doc = "TC0 Channel 2 Output (TIOA2)"] #[inline(always)] pub fn is_trgsel3(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL3 } - #[doc = "Checks if the value of the field is `TRGSEL4`"] + #[doc = "PWM0 Event Line 0"] #[inline(always)] pub fn is_trgsel4(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL4 } - #[doc = "Checks if the value of the field is `TRGSEL5`"] + #[doc = "PWM0 Event Line 1"] #[inline(always)] pub fn is_trgsel5(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL5 } - #[doc = "Checks if the value of the field is `TRGSEL6`"] + #[doc = "PWM1 Event Line 0"] #[inline(always)] pub fn is_trgsel6(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL6 } - #[doc = "Checks if the value of the field is `TRGSEL7`"] + #[doc = "PWM1 Event Line 1"] #[inline(always)] pub fn is_trgsel7(&self) -> bool { *self == TRGSEL0SELECT_A::TRGSEL7 } } #[doc = "Field `TRGSEL0` writer - Trigger Selection of Channel 0"] -pub type TRGSEL0_W<'a, const O: u8> = crate::FieldWriterSafe<'a, TRIGR_SPEC, 3, O, TRGSEL0SELECT_A>; -impl<'a, const O: u8> TRGSEL0_W<'a, O> { +pub type TRGSEL0_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, TRGSEL0SELECT_A>; +impl<'a, REG, const O: u8> TRGSEL0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "DAC External Trigger Input (DATRG)"] #[inline(always)] - pub fn trgsel0(self) -> &'a mut W { + pub fn trgsel0(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL0) } #[doc = "TC0 Channel 0 Output (TIOA0)"] #[inline(always)] - pub fn trgsel1(self) -> &'a mut W { + pub fn trgsel1(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL1) } #[doc = "TC0 Channel 1 Output (TIOA1)"] #[inline(always)] - pub fn trgsel2(self) -> &'a mut W { + pub fn trgsel2(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL2) } #[doc = "TC0 Channel 2 Output (TIOA2)"] #[inline(always)] - pub fn trgsel3(self) -> &'a mut W { + pub fn trgsel3(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL3) } #[doc = "PWM0 Event Line 0"] #[inline(always)] - pub fn trgsel4(self) -> &'a mut W { + pub fn trgsel4(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL4) } #[doc = "PWM0 Event Line 1"] #[inline(always)] - pub fn trgsel5(self) -> &'a mut W { + pub fn trgsel5(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL5) } #[doc = "PWM1 Event Line 0"] #[inline(always)] - pub fn trgsel6(self) -> &'a mut W { + pub fn trgsel6(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL6) } #[doc = "PWM1 Event Line 1"] #[inline(always)] - pub fn trgsel7(self) -> &'a mut W { + pub fn trgsel7(self) -> &'a mut crate::W { self.variant(TRGSEL0SELECT_A::TRGSEL7) } } @@ -315,88 +293,92 @@ impl TRGSEL1_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TRGSEL0`"] + #[doc = "DAC External Trigger Input (DATRG)"] #[inline(always)] pub fn is_trgsel0(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL0 } - #[doc = "Checks if the value of the field is `TRGSEL1`"] + #[doc = "TC0 Channel 0 Output (TIOA0)"] #[inline(always)] pub fn is_trgsel1(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL1 } - #[doc = "Checks if the value of the field is `TRGSEL2`"] + #[doc = "TC0 Channel 1 Output (TIOA1)"] #[inline(always)] pub fn is_trgsel2(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL2 } - #[doc = "Checks if the value of the field is `TRGSEL3`"] + #[doc = "TC0 Channel 2 Output (TIOA2)"] #[inline(always)] pub fn is_trgsel3(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL3 } - #[doc = "Checks if the value of the field is `TRGSEL4`"] + #[doc = "PWM0 Event Line 0"] #[inline(always)] pub fn is_trgsel4(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL4 } - #[doc = "Checks if the value of the field is `TRGSEL5`"] + #[doc = "PWM0 Event Line 1"] #[inline(always)] pub fn is_trgsel5(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL5 } - #[doc = "Checks if the value of the field is `TRGSEL6`"] + #[doc = "PWM1 Event Line 0"] #[inline(always)] pub fn is_trgsel6(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL6 } - #[doc = "Checks if the value of the field is `TRGSEL7`"] + #[doc = "PWM1 Event Line 1"] #[inline(always)] pub fn is_trgsel7(&self) -> bool { *self == TRGSEL1SELECT_A::TRGSEL7 } } #[doc = "Field `TRGSEL1` writer - Trigger Selection of Channel 1"] -pub type TRGSEL1_W<'a, const O: u8> = crate::FieldWriterSafe<'a, TRIGR_SPEC, 3, O, TRGSEL1SELECT_A>; -impl<'a, const O: u8> TRGSEL1_W<'a, O> { +pub type TRGSEL1_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, TRGSEL1SELECT_A>; +impl<'a, REG, const O: u8> TRGSEL1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "DAC External Trigger Input (DATRG)"] #[inline(always)] - pub fn trgsel0(self) -> &'a mut W { + pub fn trgsel0(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL0) } #[doc = "TC0 Channel 0 Output (TIOA0)"] #[inline(always)] - pub fn trgsel1(self) -> &'a mut W { + pub fn trgsel1(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL1) } #[doc = "TC0 Channel 1 Output (TIOA1)"] #[inline(always)] - pub fn trgsel2(self) -> &'a mut W { + pub fn trgsel2(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL2) } #[doc = "TC0 Channel 2 Output (TIOA2)"] #[inline(always)] - pub fn trgsel3(self) -> &'a mut W { + pub fn trgsel3(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL3) } #[doc = "PWM0 Event Line 0"] #[inline(always)] - pub fn trgsel4(self) -> &'a mut W { + pub fn trgsel4(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL4) } #[doc = "PWM0 Event Line 1"] #[inline(always)] - pub fn trgsel5(self) -> &'a mut W { + pub fn trgsel5(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL5) } #[doc = "PWM1 Event Line 0"] #[inline(always)] - pub fn trgsel6(self) -> &'a mut W { + pub fn trgsel6(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL6) } #[doc = "PWM1 Event Line 1"] #[inline(always)] - pub fn trgsel7(self) -> &'a mut W { + pub fn trgsel7(self) -> &'a mut crate::W { self.variant(TRGSEL1SELECT_A::TRGSEL7) } } @@ -442,68 +424,72 @@ impl OSR0_R { _ => None, } } - #[doc = "Checks if the value of the field is `OSR_1`"] + #[doc = "OSR = 1"] #[inline(always)] pub fn is_osr_1(&self) -> bool { *self == OSR0SELECT_A::OSR_1 } - #[doc = "Checks if the value of the field is `OSR_2`"] + #[doc = "OSR = 2"] #[inline(always)] pub fn is_osr_2(&self) -> bool { *self == OSR0SELECT_A::OSR_2 } - #[doc = "Checks if the value of the field is `OSR_4`"] + #[doc = "OSR = 4"] #[inline(always)] pub fn is_osr_4(&self) -> bool { *self == OSR0SELECT_A::OSR_4 } - #[doc = "Checks if the value of the field is `OSR_8`"] + #[doc = "OSR = 8"] #[inline(always)] pub fn is_osr_8(&self) -> bool { *self == OSR0SELECT_A::OSR_8 } - #[doc = "Checks if the value of the field is `OSR_16`"] + #[doc = "OSR = 16"] #[inline(always)] pub fn is_osr_16(&self) -> bool { *self == OSR0SELECT_A::OSR_16 } - #[doc = "Checks if the value of the field is `OSR_32`"] + #[doc = "OSR = 32"] #[inline(always)] pub fn is_osr_32(&self) -> bool { *self == OSR0SELECT_A::OSR_32 } } #[doc = "Field `OSR0` writer - Over Sampling Ratio of Channel 0"] -pub type OSR0_W<'a, const O: u8> = crate::FieldWriter<'a, TRIGR_SPEC, 3, O, OSR0SELECT_A>; -impl<'a, const O: u8> OSR0_W<'a, O> { +pub type OSR0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, OSR0SELECT_A>; +impl<'a, REG, const O: u8> OSR0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "OSR = 1"] #[inline(always)] - pub fn osr_1(self) -> &'a mut W { + pub fn osr_1(self) -> &'a mut crate::W { self.variant(OSR0SELECT_A::OSR_1) } #[doc = "OSR = 2"] #[inline(always)] - pub fn osr_2(self) -> &'a mut W { + pub fn osr_2(self) -> &'a mut crate::W { self.variant(OSR0SELECT_A::OSR_2) } #[doc = "OSR = 4"] #[inline(always)] - pub fn osr_4(self) -> &'a mut W { + pub fn osr_4(self) -> &'a mut crate::W { self.variant(OSR0SELECT_A::OSR_4) } #[doc = "OSR = 8"] #[inline(always)] - pub fn osr_8(self) -> &'a mut W { + pub fn osr_8(self) -> &'a mut crate::W { self.variant(OSR0SELECT_A::OSR_8) } #[doc = "OSR = 16"] #[inline(always)] - pub fn osr_16(self) -> &'a mut W { + pub fn osr_16(self) -> &'a mut crate::W { self.variant(OSR0SELECT_A::OSR_16) } #[doc = "OSR = 32"] #[inline(always)] - pub fn osr_32(self) -> &'a mut W { + pub fn osr_32(self) -> &'a mut crate::W { self.variant(OSR0SELECT_A::OSR_32) } } @@ -549,68 +535,72 @@ impl OSR1_R { _ => None, } } - #[doc = "Checks if the value of the field is `OSR_1`"] + #[doc = "OSR = 1"] #[inline(always)] pub fn is_osr_1(&self) -> bool { *self == OSR1SELECT_A::OSR_1 } - #[doc = "Checks if the value of the field is `OSR_2`"] + #[doc = "OSR = 2"] #[inline(always)] pub fn is_osr_2(&self) -> bool { *self == OSR1SELECT_A::OSR_2 } - #[doc = "Checks if the value of the field is `OSR_4`"] + #[doc = "OSR = 4"] #[inline(always)] pub fn is_osr_4(&self) -> bool { *self == OSR1SELECT_A::OSR_4 } - #[doc = "Checks if the value of the field is `OSR_8`"] + #[doc = "OSR = 8"] #[inline(always)] pub fn is_osr_8(&self) -> bool { *self == OSR1SELECT_A::OSR_8 } - #[doc = "Checks if the value of the field is `OSR_16`"] + #[doc = "OSR = 16"] #[inline(always)] pub fn is_osr_16(&self) -> bool { *self == OSR1SELECT_A::OSR_16 } - #[doc = "Checks if the value of the field is `OSR_32`"] + #[doc = "OSR = 32"] #[inline(always)] pub fn is_osr_32(&self) -> bool { *self == OSR1SELECT_A::OSR_32 } } #[doc = "Field `OSR1` writer - Over Sampling Ratio of Channel 1"] -pub type OSR1_W<'a, const O: u8> = crate::FieldWriter<'a, TRIGR_SPEC, 3, O, OSR1SELECT_A>; -impl<'a, const O: u8> OSR1_W<'a, O> { +pub type OSR1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, OSR1SELECT_A>; +impl<'a, REG, const O: u8> OSR1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "OSR = 1"] #[inline(always)] - pub fn osr_1(self) -> &'a mut W { + pub fn osr_1(self) -> &'a mut crate::W { self.variant(OSR1SELECT_A::OSR_1) } #[doc = "OSR = 2"] #[inline(always)] - pub fn osr_2(self) -> &'a mut W { + pub fn osr_2(self) -> &'a mut crate::W { self.variant(OSR1SELECT_A::OSR_2) } #[doc = "OSR = 4"] #[inline(always)] - pub fn osr_4(self) -> &'a mut W { + pub fn osr_4(self) -> &'a mut crate::W { self.variant(OSR1SELECT_A::OSR_4) } #[doc = "OSR = 8"] #[inline(always)] - pub fn osr_8(self) -> &'a mut W { + pub fn osr_8(self) -> &'a mut crate::W { self.variant(OSR1SELECT_A::OSR_8) } #[doc = "OSR = 16"] #[inline(always)] - pub fn osr_16(self) -> &'a mut W { + pub fn osr_16(self) -> &'a mut crate::W { self.variant(OSR1SELECT_A::OSR_16) } #[doc = "OSR = 32"] #[inline(always)] - pub fn osr_32(self) -> &'a mut W { + pub fn osr_32(self) -> &'a mut crate::W { self.variant(OSR1SELECT_A::OSR_32) } } @@ -650,58 +640,55 @@ impl W { #[doc = "Bit 0 - Trigger Enable of Channel 0"] #[inline(always)] #[must_use] - pub fn trgen0(&mut self) -> TRGEN0_W<0> { + pub fn trgen0(&mut self) -> TRGEN0_W { TRGEN0_W::new(self) } #[doc = "Bit 1 - Trigger Enable of Channel 1"] #[inline(always)] #[must_use] - pub fn trgen1(&mut self) -> TRGEN1_W<1> { + pub fn trgen1(&mut self) -> TRGEN1_W { TRGEN1_W::new(self) } #[doc = "Bits 4:6 - Trigger Selection of Channel 0"] #[inline(always)] #[must_use] - pub fn trgsel0(&mut self) -> TRGSEL0_W<4> { + pub fn trgsel0(&mut self) -> TRGSEL0_W { TRGSEL0_W::new(self) } #[doc = "Bits 8:10 - Trigger Selection of Channel 1"] #[inline(always)] #[must_use] - pub fn trgsel1(&mut self) -> TRGSEL1_W<8> { + pub fn trgsel1(&mut self) -> TRGSEL1_W { TRGSEL1_W::new(self) } #[doc = "Bits 16:18 - Over Sampling Ratio of Channel 0"] #[inline(always)] #[must_use] - pub fn osr0(&mut self) -> OSR0_W<16> { + pub fn osr0(&mut self) -> OSR0_W { OSR0_W::new(self) } #[doc = "Bits 20:22 - Over Sampling Ratio of Channel 1"] #[inline(always)] #[must_use] - pub fn osr1(&mut self) -> OSR1_W<20> { + pub fn osr1(&mut self) -> OSR1_W { OSR1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Trigger Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trigr](index.html) module"] +#[doc = "Trigger Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TRIGR_SPEC; impl crate::RegisterSpec for TRIGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [trigr::R](R) reader structure"] -impl crate::Readable for TRIGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [trigr::W](W) writer structure"] +#[doc = "`read()` method returns [`trigr::R`](R) reader structure"] +impl crate::Readable for TRIGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trigr::W`](W) writer structure"] impl crate::Writable for TRIGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/wpmr.rs index 825d7614..82c5d89a 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protect Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protect Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protect Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protect Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/dacc/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/dacc/wpsr.rs index 07acbfac..23bbcfad 100644 --- a/arch/cortex-m/samv71q21-pac/src/dacc/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/dacc/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xff) as u8) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/efc.rs b/arch/cortex-m/samv71q21-pac/src/efc.rs index 998f1b5a..1d75b06d 100644 --- a/arch/cortex-m/samv71q21-pac/src/efc.rs +++ b/arch/cortex-m/samv71q21-pac/src/efc.rs @@ -13,23 +13,28 @@ pub struct RegisterBlock { #[doc = "0xe4 - Write Protection Mode Register"] pub eefc_wpmr: EEFC_WPMR, } -#[doc = "EEFC_FMR (rw) register accessor: an alias for `Reg`"] +#[doc = "EEFC_FMR (rw) register accessor: EEFC Flash Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_fmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eefc_fmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eefc_fmr`] +module"] pub type EEFC_FMR = crate::Reg; #[doc = "EEFC Flash Mode Register"] pub mod eefc_fmr; -#[doc = "EEFC_FCR (w) register accessor: an alias for `Reg`"] +#[doc = "EEFC_FCR (w) register accessor: EEFC Flash Command Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eefc_fcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eefc_fcr`] +module"] pub type EEFC_FCR = crate::Reg; #[doc = "EEFC Flash Command Register"] pub mod eefc_fcr; -#[doc = "EEFC_FSR (r) register accessor: an alias for `Reg`"] +#[doc = "EEFC_FSR (r) register accessor: EEFC Flash Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_fsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eefc_fsr`] +module"] pub type EEFC_FSR = crate::Reg; #[doc = "EEFC Flash Status Register"] pub mod eefc_fsr; -#[doc = "EEFC_FRR (r) register accessor: an alias for `Reg`"] +#[doc = "EEFC_FRR (r) register accessor: EEFC Flash Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_frr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eefc_frr`] +module"] pub type EEFC_FRR = crate::Reg; #[doc = "EEFC Flash Result Register"] pub mod eefc_frr; -#[doc = "EEFC_WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "EEFC_WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eefc_wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eefc_wpmr`] +module"] pub type EEFC_WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod eefc_wpmr; diff --git a/arch/cortex-m/samv71q21-pac/src/efc/eefc_fcr.rs b/arch/cortex-m/samv71q21-pac/src/efc/eefc_fcr.rs index c1174026..c5cad047 100644 --- a/arch/cortex-m/samv71q21-pac/src/efc/eefc_fcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/efc/eefc_fcr.rs @@ -1,24 +1,5 @@ #[doc = "Register `EEFC_FCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Flash Command\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -76,116 +57,120 @@ impl crate::FieldSpec for FCMDSELECT_AW { type Ux = u8; } #[doc = "Field `FCMD` writer - Flash Command"] -pub type FCMD_W<'a, const O: u8> = crate::FieldWriter<'a, EEFC_FCR_SPEC, 8, O, FCMDSELECT_AW>; -impl<'a, const O: u8> FCMD_W<'a, O> { +pub type FCMD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, FCMDSELECT_AW>; +impl<'a, REG, const O: u8> FCMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Get Flash descriptor"] #[inline(always)] - pub fn getd(self) -> &'a mut W { + pub fn getd(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::GETD) } #[doc = "Write page"] #[inline(always)] - pub fn wp(self) -> &'a mut W { + pub fn wp(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::WP) } #[doc = "Write page and lock"] #[inline(always)] - pub fn wpl(self) -> &'a mut W { + pub fn wpl(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::WPL) } #[doc = "Erase page and write page"] #[inline(always)] - pub fn ewp(self) -> &'a mut W { + pub fn ewp(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::EWP) } #[doc = "Erase page and write page then lock"] #[inline(always)] - pub fn ewpl(self) -> &'a mut W { + pub fn ewpl(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::EWPL) } #[doc = "Erase all"] #[inline(always)] - pub fn ea(self) -> &'a mut W { + pub fn ea(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::EA) } #[doc = "Erase pages"] #[inline(always)] - pub fn epa(self) -> &'a mut W { + pub fn epa(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::EPA) } #[doc = "Set lock bit"] #[inline(always)] - pub fn slb(self) -> &'a mut W { + pub fn slb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::SLB) } #[doc = "Clear lock bit"] #[inline(always)] - pub fn clb(self) -> &'a mut W { + pub fn clb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::CLB) } #[doc = "Get lock bit"] #[inline(always)] - pub fn glb(self) -> &'a mut W { + pub fn glb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::GLB) } #[doc = "Set GPNVM bit"] #[inline(always)] - pub fn sgpb(self) -> &'a mut W { + pub fn sgpb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::SGPB) } #[doc = "Clear GPNVM bit"] #[inline(always)] - pub fn cgpb(self) -> &'a mut W { + pub fn cgpb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::CGPB) } #[doc = "Get GPNVM bit"] #[inline(always)] - pub fn ggpb(self) -> &'a mut W { + pub fn ggpb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::GGPB) } #[doc = "Start read unique identifier"] #[inline(always)] - pub fn stui(self) -> &'a mut W { + pub fn stui(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::STUI) } #[doc = "Stop read unique identifier"] #[inline(always)] - pub fn spui(self) -> &'a mut W { + pub fn spui(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::SPUI) } #[doc = "Get CALIB bit"] #[inline(always)] - pub fn gcalb(self) -> &'a mut W { + pub fn gcalb(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::GCALB) } #[doc = "Erase sector"] #[inline(always)] - pub fn es(self) -> &'a mut W { + pub fn es(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::ES) } #[doc = "Write user signature"] #[inline(always)] - pub fn wus(self) -> &'a mut W { + pub fn wus(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::WUS) } #[doc = "Erase user signature"] #[inline(always)] - pub fn eus(self) -> &'a mut W { + pub fn eus(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::EUS) } #[doc = "Start read user signature"] #[inline(always)] - pub fn stus(self) -> &'a mut W { + pub fn stus(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::STUS) } #[doc = "Stop read user signature"] #[inline(always)] - pub fn spus(self) -> &'a mut W { + pub fn spus(self) -> &'a mut crate::W { self.variant(FCMDSELECT_AW::SPUS) } } #[doc = "Field `FARG` writer - Flash Command Argument"] -pub type FARG_W<'a, const O: u8> = crate::FieldWriter<'a, EEFC_FCR_SPEC, 16, O, u16>; +pub type FARG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Flash Writing Protection Key\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -203,11 +188,15 @@ impl crate::FieldSpec for FKEYSELECT_AW { type Ux = u8; } #[doc = "Field `FKEY` writer - Flash Writing Protection Key"] -pub type FKEY_W<'a, const O: u8> = crate::FieldWriter<'a, EEFC_FCR_SPEC, 8, O, FKEYSELECT_AW>; -impl<'a, const O: u8> FKEY_W<'a, O> { +pub type FKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, FKEYSELECT_AW>; +impl<'a, REG, const O: u8> FKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(FKEYSELECT_AW::PASSWD) } } @@ -215,36 +204,35 @@ impl W { #[doc = "Bits 0:7 - Flash Command"] #[inline(always)] #[must_use] - pub fn fcmd(&mut self) -> FCMD_W<0> { + pub fn fcmd(&mut self) -> FCMD_W { FCMD_W::new(self) } #[doc = "Bits 8:23 - Flash Command Argument"] #[inline(always)] #[must_use] - pub fn farg(&mut self) -> FARG_W<8> { + pub fn farg(&mut self) -> FARG_W { FARG_W::new(self) } #[doc = "Bits 24:31 - Flash Writing Protection Key"] #[inline(always)] #[must_use] - pub fn fkey(&mut self) -> FKEY_W<24> { + pub fn fkey(&mut self) -> FKEY_W { FKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "EEFC Flash Command Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eefc_fcr](index.html) module"] +#[doc = "EEFC Flash Command Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eefc_fcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EEFC_FCR_SPEC; impl crate::RegisterSpec for EEFC_FCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [eefc_fcr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`eefc_fcr::W`](W) writer structure"] impl crate::Writable for EEFC_FCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/efc/eefc_fmr.rs b/arch/cortex-m/samv71q21-pac/src/efc/eefc_fmr.rs index 17250697..0aaeaf4c 100644 --- a/arch/cortex-m/samv71q21-pac/src/efc/eefc_fmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/efc/eefc_fmr.rs @@ -1,55 +1,23 @@ #[doc = "Register `EEFC_FMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EEFC_FMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FRDY` reader - Flash Ready Interrupt Enable"] pub type FRDY_R = crate::BitReader; #[doc = "Field `FRDY` writer - Flash Ready Interrupt Enable"] -pub type FRDY_W<'a, const O: u8> = crate::BitWriter<'a, EEFC_FMR_SPEC, O>; +pub type FRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FWS` reader - Flash Wait State"] pub type FWS_R = crate::FieldReader; #[doc = "Field `FWS` writer - Flash Wait State"] -pub type FWS_W<'a, const O: u8> = crate::FieldWriter<'a, EEFC_FMR_SPEC, 4, O>; +pub type FWS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SCOD` reader - Sequential Code Optimization Disable"] pub type SCOD_R = crate::BitReader; #[doc = "Field `SCOD` writer - Sequential Code Optimization Disable"] -pub type SCOD_W<'a, const O: u8> = crate::BitWriter<'a, EEFC_FMR_SPEC, O>; +pub type SCOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLOE` reader - Code Loop Optimization Enable"] pub type CLOE_R = crate::BitReader; #[doc = "Field `CLOE` writer - Code Loop Optimization Enable"] -pub type CLOE_W<'a, const O: u8> = crate::BitWriter<'a, EEFC_FMR_SPEC, O>; +pub type CLOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Flash Ready Interrupt Enable"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - Flash Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn frdy(&mut self) -> FRDY_W<0> { + pub fn frdy(&mut self) -> FRDY_W { FRDY_W::new(self) } #[doc = "Bits 8:11 - Flash Wait State"] #[inline(always)] #[must_use] - pub fn fws(&mut self) -> FWS_W<8> { + pub fn fws(&mut self) -> FWS_W { FWS_W::new(self) } #[doc = "Bit 16 - Sequential Code Optimization Disable"] #[inline(always)] #[must_use] - pub fn scod(&mut self) -> SCOD_W<16> { + pub fn scod(&mut self) -> SCOD_W { SCOD_W::new(self) } #[doc = "Bit 26 - Code Loop Optimization Enable"] #[inline(always)] #[must_use] - pub fn cloe(&mut self) -> CLOE_W<26> { + pub fn cloe(&mut self) -> CLOE_W { CLOE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "EEFC Flash Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eefc_fmr](index.html) module"] +#[doc = "EEFC Flash Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_fmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eefc_fmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EEFC_FMR_SPEC; impl crate::RegisterSpec for EEFC_FMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eefc_fmr::R](R) reader structure"] -impl crate::Readable for EEFC_FMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [eefc_fmr::W](W) writer structure"] +#[doc = "`read()` method returns [`eefc_fmr::R`](R) reader structure"] +impl crate::Readable for EEFC_FMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eefc_fmr::W`](W) writer structure"] impl crate::Writable for EEFC_FMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/efc/eefc_frr.rs b/arch/cortex-m/samv71q21-pac/src/efc/eefc_frr.rs index ac37e562..4043002b 100644 --- a/arch/cortex-m/samv71q21-pac/src/efc/eefc_frr.rs +++ b/arch/cortex-m/samv71q21-pac/src/efc/eefc_frr.rs @@ -1,18 +1,5 @@ #[doc = "Register `EEFC_FRR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FVALUE` reader - Flash Result Value"] pub type FVALUE_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { FVALUE_R::new(self.bits) } } -#[doc = "EEFC Flash Result Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eefc_frr](index.html) module"] +#[doc = "EEFC Flash Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_frr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EEFC_FRR_SPEC; impl crate::RegisterSpec for EEFC_FRR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eefc_frr::R](R) reader structure"] -impl crate::Readable for EEFC_FRR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`eefc_frr::R`](R) reader structure"] +impl crate::Readable for EEFC_FRR_SPEC {} #[doc = "`reset()` method sets EEFC_FRR to value 0"] impl crate::Resettable for EEFC_FRR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/efc/eefc_fsr.rs b/arch/cortex-m/samv71q21-pac/src/efc/eefc_fsr.rs index b01bf755..8945a0c2 100644 --- a/arch/cortex-m/samv71q21-pac/src/efc/eefc_fsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/efc/eefc_fsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `EEFC_FSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FRDY` reader - Flash Ready Status (cleared when Flash is busy)"] pub type FRDY_R = crate::BitReader; #[doc = "Field `FCMDE` reader - Flash Command Error Status (cleared on read or by writing EEFC_FCR)"] @@ -71,15 +58,13 @@ impl R { MECCEMSB_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "EEFC Flash Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eefc_fsr](index.html) module"] +#[doc = "EEFC Flash Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_fsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EEFC_FSR_SPEC; impl crate::RegisterSpec for EEFC_FSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eefc_fsr::R](R) reader structure"] -impl crate::Readable for EEFC_FSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`eefc_fsr::R`](R) reader structure"] +impl crate::Readable for EEFC_FSR_SPEC {} #[doc = "`reset()` method sets EEFC_FSR to value 0"] impl crate::Resettable for EEFC_FSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/efc/eefc_wpmr.rs b/arch/cortex-m/samv71q21-pac/src/efc/eefc_wpmr.rs index 022ccde0..7d0cd306 100644 --- a/arch/cortex-m/samv71q21-pac/src/efc/eefc_wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/efc/eefc_wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `EEFC_WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EEFC_WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, EEFC_WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, EEFC_WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eefc_wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eefc_wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`eefc_wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EEFC_WPMR_SPEC; impl crate::RegisterSpec for EEFC_WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eefc_wpmr::R](R) reader structure"] -impl crate::Readable for EEFC_WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [eefc_wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`eefc_wpmr::R`](R) reader structure"] +impl crate::Readable for EEFC_WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`eefc_wpmr::W`](W) writer structure"] impl crate::Writable for EEFC_WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm.rs b/arch/cortex-m/samv71q21-pac/src/etm.rs index 67764dc9..f4120419 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm.rs @@ -99,163 +99,203 @@ pub struct RegisterBlock { #[doc = "0xffc - ETM Component Identification Register #3"] pub cidr3: CIDR3, } -#[doc = "CR (rw) register accessor: an alias for `Reg`"] +#[doc = "CR (rw) register accessor: ETM Main Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "ETM Main Control Register"] pub mod cr; -#[doc = "CCR (r) register accessor: an alias for `Reg`"] +#[doc = "CCR (r) register accessor: ETM Configuration Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccr`] +module"] pub type CCR = crate::Reg; #[doc = "ETM Configuration Code Register"] pub mod ccr; -#[doc = "TRIGGER (rw) register accessor: an alias for `Reg`"] +#[doc = "TRIGGER (rw) register accessor: ETM Trigger Event Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigger::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`trigger`] +module"] pub type TRIGGER = crate::Reg; #[doc = "ETM Trigger Event Register"] pub mod trigger; -#[doc = "SR (rw) register accessor: an alias for `Reg`"] +#[doc = "SR (rw) register accessor: ETM Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "ETM Status Register"] pub mod sr; -#[doc = "SCR (r) register accessor: an alias for `Reg`"] +#[doc = "SCR (r) register accessor: ETM System Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +module"] pub type SCR = crate::Reg; #[doc = "ETM System Configuration Register"] pub mod scr; -#[doc = "TEEVR (rw) register accessor: an alias for `Reg`"] +#[doc = "TEEVR (rw) register accessor: ETM TraceEnable Event Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`teevr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`teevr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`teevr`] +module"] pub type TEEVR = crate::Reg; #[doc = "ETM TraceEnable Event Register"] pub mod teevr; -#[doc = "TECR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "TECR1 (rw) register accessor: ETM TraceEnable Control 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tecr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tecr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tecr1`] +module"] pub type TECR1 = crate::Reg; #[doc = "ETM TraceEnable Control 1 Register"] pub mod tecr1; -#[doc = "FFLR (rw) register accessor: an alias for `Reg`"] +#[doc = "FFLR (rw) register accessor: ETM FIFO Full Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fflr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fflr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fflr`] +module"] pub type FFLR = crate::Reg; #[doc = "ETM FIFO Full Level Register"] pub mod fflr; -#[doc = "CNTRLDVR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CNTRLDVR1 (rw) register accessor: ETM Free-running Counter Reload Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntrldvr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntrldvr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cntrldvr1`] +module"] pub type CNTRLDVR1 = crate::Reg; #[doc = "ETM Free-running Counter Reload Value"] pub mod cntrldvr1; -#[doc = "SYNCFR (r) register accessor: an alias for `Reg`"] +#[doc = "SYNCFR (r) register accessor: ETM Synchronization Frequency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syncfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`syncfr`] +module"] pub type SYNCFR = crate::Reg; #[doc = "ETM Synchronization Frequency Register"] pub mod syncfr; -#[doc = "IDR (r) register accessor: an alias for `Reg`"] +#[doc = "IDR (r) register accessor: ETM ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "ETM ID Register"] pub mod idr; -#[doc = "CCER (r) register accessor: an alias for `Reg`"] +#[doc = "CCER (r) register accessor: ETM Configuration Code Extension Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccer`] +module"] pub type CCER = crate::Reg; #[doc = "ETM Configuration Code Extension Register"] pub mod ccer; -#[doc = "TESSEICR (rw) register accessor: an alias for `Reg`"] +#[doc = "TESSEICR (rw) register accessor: ETM TraceEnable Start/Stop EmbeddedICE Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tesseicr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tesseicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tesseicr`] +module"] pub type TESSEICR = crate::Reg; #[doc = "ETM TraceEnable Start/Stop EmbeddedICE Control Register"] pub mod tesseicr; -#[doc = "TSEVT (rw) register accessor: an alias for `Reg`"] +#[doc = "TSEVT (rw) register accessor: ETM TimeStamp Event Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsevt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsevt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tsevt`] +module"] pub type TSEVT = crate::Reg; #[doc = "ETM TimeStamp Event Register"] pub mod tsevt; -#[doc = "TRACEIDR (rw) register accessor: an alias for `Reg`"] +#[doc = "TRACEIDR (rw) register accessor: ETM CoreSight Trace ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`traceidr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`traceidr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`traceidr`] +module"] pub type TRACEIDR = crate::Reg; #[doc = "ETM CoreSight Trace ID Register"] pub mod traceidr; -#[doc = "IDR2 (r) register accessor: an alias for `Reg`"] +#[doc = "IDR2 (r) register accessor: ETM ID Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr2`] +module"] pub type IDR2 = crate::Reg; #[doc = "ETM ID Register 2"] pub mod idr2; -#[doc = "PDSR (r) register accessor: an alias for `Reg`"] +#[doc = "PDSR (r) register accessor: ETM Device Power-Down Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdsr`] +module"] pub type PDSR = crate::Reg; #[doc = "ETM Device Power-Down Status Register"] pub mod pdsr; -#[doc = "ITMISCIN (r) register accessor: an alias for `Reg`"] +#[doc = "ITMISCIN (r) register accessor: ETM Integration Test Miscellaneous Inputs\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itmiscin::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`itmiscin`] +module"] pub type ITMISCIN = crate::Reg; #[doc = "ETM Integration Test Miscellaneous Inputs"] pub mod itmiscin; -#[doc = "ITTRIGOUT (w) register accessor: an alias for `Reg`"] +#[doc = "ITTRIGOUT (w) register accessor: ETM Integration Test Trigger Out\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ittrigout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ittrigout`] +module"] pub type ITTRIGOUT = crate::Reg; #[doc = "ETM Integration Test Trigger Out"] pub mod ittrigout; -#[doc = "ITATBCTR2 (r) register accessor: an alias for `Reg`"] +#[doc = "ITATBCTR2 (r) register accessor: ETM Integration Test ATB Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itatbctr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`itatbctr2`] +module"] pub type ITATBCTR2 = crate::Reg; #[doc = "ETM Integration Test ATB Control 2"] pub mod itatbctr2; -#[doc = "ITATBCTR0 (w) register accessor: an alias for `Reg`"] +#[doc = "ITATBCTR0 (w) register accessor: ETM Integration Test ATB Control 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itatbctr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`itatbctr0`] +module"] pub type ITATBCTR0 = crate::Reg; #[doc = "ETM Integration Test ATB Control 0"] pub mod itatbctr0; -#[doc = "ITCTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "ITCTRL (rw) register accessor: ETM Integration Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`itctrl`] +module"] pub type ITCTRL = crate::Reg; #[doc = "ETM Integration Mode Control Register"] pub mod itctrl; -#[doc = "CLAIMSET (rw) register accessor: an alias for `Reg`"] +#[doc = "CLAIMSET (rw) register accessor: ETM Claim Tag Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimset`] +module"] pub type CLAIMSET = crate::Reg; #[doc = "ETM Claim Tag Set Register"] pub mod claimset; -#[doc = "CLAIMCLR (rw) register accessor: an alias for `Reg`"] +#[doc = "CLAIMCLR (rw) register accessor: ETM Claim Tag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimclr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimclr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`claimclr`] +module"] pub type CLAIMCLR = crate::Reg; #[doc = "ETM Claim Tag Clear Register"] pub mod claimclr; -#[doc = "LAR (w) register accessor: an alias for `Reg`"] +#[doc = "LAR (w) register accessor: ETM Lock Access Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lar::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lar`] +module"] pub type LAR = crate::Reg; #[doc = "ETM Lock Access Register"] pub mod lar; -#[doc = "LSR (r) register accessor: an alias for `Reg`"] +#[doc = "LSR (r) register accessor: ETM Lock Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +module"] pub type LSR = crate::Reg; #[doc = "ETM Lock Status Register"] pub mod lsr; -#[doc = "AUTHSTATUS (r) register accessor: an alias for `Reg`"] +#[doc = "AUTHSTATUS (r) register accessor: ETM Authentication Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`authstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`authstatus`] +module"] pub type AUTHSTATUS = crate::Reg; #[doc = "ETM Authentication Status Register"] pub mod authstatus; -#[doc = "DEVTYPE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVTYPE (r) register accessor: ETM CoreSight Device Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devtype::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devtype`] +module"] pub type DEVTYPE = crate::Reg; #[doc = "ETM CoreSight Device Type Register"] pub mod devtype; -#[doc = "PIDR4 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR4 (r) register accessor: ETM Peripheral Identification Register #4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr4`] +module"] pub type PIDR4 = crate::Reg; #[doc = "ETM Peripheral Identification Register #4"] pub mod pidr4; -#[doc = "PIDR5 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR5 (r) register accessor: ETM Peripheral Identification Register #5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr5`] +module"] pub type PIDR5 = crate::Reg; #[doc = "ETM Peripheral Identification Register #5"] pub mod pidr5; -#[doc = "PIDR6 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR6 (r) register accessor: ETM Peripheral Identification Register #6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr6::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr6`] +module"] pub type PIDR6 = crate::Reg; #[doc = "ETM Peripheral Identification Register #6"] pub mod pidr6; -#[doc = "PIDR7 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR7 (r) register accessor: ETM Peripheral Identification Register #7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr7::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr7`] +module"] pub type PIDR7 = crate::Reg; #[doc = "ETM Peripheral Identification Register #7"] pub mod pidr7; -#[doc = "PIDR0 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR0 (r) register accessor: ETM Peripheral Identification Register #0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr0`] +module"] pub type PIDR0 = crate::Reg; #[doc = "ETM Peripheral Identification Register #0"] pub mod pidr0; -#[doc = "PIDR1 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR1 (r) register accessor: ETM Peripheral Identification Register #1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr1`] +module"] pub type PIDR1 = crate::Reg; #[doc = "ETM Peripheral Identification Register #1"] pub mod pidr1; -#[doc = "PIDR2 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR2 (r) register accessor: ETM Peripheral Identification Register #2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr2`] +module"] pub type PIDR2 = crate::Reg; #[doc = "ETM Peripheral Identification Register #2"] pub mod pidr2; -#[doc = "PIDR3 (r) register accessor: an alias for `Reg`"] +#[doc = "PIDR3 (r) register accessor: ETM Peripheral Identification Register #3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pidr3`] +module"] pub type PIDR3 = crate::Reg; #[doc = "ETM Peripheral Identification Register #3"] pub mod pidr3; -#[doc = "CIDR0 (r) register accessor: an alias for `Reg`"] +#[doc = "CIDR0 (r) register accessor: ETM Component Identification Register #0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cidr0`] +module"] pub type CIDR0 = crate::Reg; #[doc = "ETM Component Identification Register #0"] pub mod cidr0; -#[doc = "CIDR1 (r) register accessor: an alias for `Reg`"] +#[doc = "CIDR1 (r) register accessor: ETM Component Identification Register #1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cidr1`] +module"] pub type CIDR1 = crate::Reg; #[doc = "ETM Component Identification Register #1"] pub mod cidr1; -#[doc = "CIDR2 (r) register accessor: an alias for `Reg`"] +#[doc = "CIDR2 (r) register accessor: ETM Component Identification Register #2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cidr2`] +module"] pub type CIDR2 = crate::Reg; #[doc = "ETM Component Identification Register #2"] pub mod cidr2; -#[doc = "CIDR3 (r) register accessor: an alias for `Reg`"] +#[doc = "CIDR3 (r) register accessor: ETM Component Identification Register #3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cidr3`] +module"] pub type CIDR3 = crate::Reg; #[doc = "ETM Component Identification Register #3"] pub mod cidr3; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/authstatus.rs b/arch/cortex-m/samv71q21-pac/src/etm/authstatus.rs index 8f350a27..fdf849a5 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/authstatus.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/authstatus.rs @@ -1,18 +1,5 @@ #[doc = "Register `AUTHSTATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Authentication Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +#[doc = "ETM Authentication Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`authstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AUTHSTATUS_SPEC; impl crate::RegisterSpec for AUTHSTATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [authstatus::R](R) reader structure"] -impl crate::Readable for AUTHSTATUS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`authstatus::R`](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC {} #[doc = "`reset()` method sets AUTHSTATUS to value 0"] impl crate::Resettable for AUTHSTATUS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/ccer.rs b/arch/cortex-m/samv71q21-pac/src/etm/ccer.rs index 5eb22061..9e639bad 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/ccer.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/ccer.rs @@ -1,18 +1,5 @@ #[doc = "Register `CCER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Configuration Code Extension Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccer](index.html) module"] +#[doc = "ETM Configuration Code Extension Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCER_SPEC; impl crate::RegisterSpec for CCER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccer::R](R) reader structure"] -impl crate::Readable for CCER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ccer::R`](R) reader structure"] +impl crate::Readable for CCER_SPEC {} #[doc = "`reset()` method sets CCER to value 0x1854_1800"] impl crate::Resettable for CCER_SPEC { const RESET_VALUE: Self::Ux = 0x1854_1800; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/ccr.rs b/arch/cortex-m/samv71q21-pac/src/etm/ccr.rs index 70d16a23..44f3ba50 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/ccr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/ccr.rs @@ -1,18 +1,5 @@ #[doc = "Register `CCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Configuration Code Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +#[doc = "ETM Configuration Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCR_SPEC; impl crate::RegisterSpec for CCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccr::R](R) reader structure"] -impl crate::Readable for CCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CCR_SPEC {} #[doc = "`reset()` method sets CCR to value 0x8c80_2000"] impl crate::Resettable for CCR_SPEC { const RESET_VALUE: Self::Ux = 0x8c80_2000; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/cidr0.rs b/arch/cortex-m/samv71q21-pac/src/etm/cidr0.rs index 38223f62..8401b9fb 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/cidr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/cidr0.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIDR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Component Identification Register #0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cidr0](index.html) module"] +#[doc = "ETM Component Identification Register #0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIDR0_SPEC; impl crate::RegisterSpec for CIDR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cidr0::R](R) reader structure"] -impl crate::Readable for CIDR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cidr0::R`](R) reader structure"] +impl crate::Readable for CIDR0_SPEC {} #[doc = "`reset()` method sets CIDR0 to value 0x0d"] impl crate::Resettable for CIDR0_SPEC { const RESET_VALUE: Self::Ux = 0x0d; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/cidr1.rs b/arch/cortex-m/samv71q21-pac/src/etm/cidr1.rs index 1a7b9c3f..193ae0ad 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/cidr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/cidr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Component Identification Register #1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cidr1](index.html) module"] +#[doc = "ETM Component Identification Register #1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIDR1_SPEC; impl crate::RegisterSpec for CIDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cidr1::R](R) reader structure"] -impl crate::Readable for CIDR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cidr1::R`](R) reader structure"] +impl crate::Readable for CIDR1_SPEC {} #[doc = "`reset()` method sets CIDR1 to value 0x90"] impl crate::Resettable for CIDR1_SPEC { const RESET_VALUE: Self::Ux = 0x90; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/cidr2.rs b/arch/cortex-m/samv71q21-pac/src/etm/cidr2.rs index 718ed23c..7a2e3569 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/cidr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/cidr2.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Component Identification Register #2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cidr2](index.html) module"] +#[doc = "ETM Component Identification Register #2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIDR2_SPEC; impl crate::RegisterSpec for CIDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cidr2::R](R) reader structure"] -impl crate::Readable for CIDR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cidr2::R`](R) reader structure"] +impl crate::Readable for CIDR2_SPEC {} #[doc = "`reset()` method sets CIDR2 to value 0x05"] impl crate::Resettable for CIDR2_SPEC { const RESET_VALUE: Self::Ux = 0x05; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/cidr3.rs b/arch/cortex-m/samv71q21-pac/src/etm/cidr3.rs index ad13dec2..ebf362e1 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/cidr3.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/cidr3.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Component Identification Register #3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cidr3](index.html) module"] +#[doc = "ETM Component Identification Register #3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cidr3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIDR3_SPEC; impl crate::RegisterSpec for CIDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cidr3::R](R) reader structure"] -impl crate::Readable for CIDR3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cidr3::R`](R) reader structure"] +impl crate::Readable for CIDR3_SPEC {} #[doc = "`reset()` method sets CIDR3 to value 0xb1"] impl crate::Resettable for CIDR3_SPEC { const RESET_VALUE: Self::Ux = 0xb1; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/claimclr.rs b/arch/cortex-m/samv71q21-pac/src/etm/claimclr.rs index 313078f2..30dc6caa 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/claimclr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/claimclr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLAIMCLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLAIMCLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Claim Tag Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +#[doc = "ETM Claim Tag Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimclr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLAIMCLR_SPEC; impl crate::RegisterSpec for CLAIMCLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [claimclr::R](R) reader structure"] -impl crate::Readable for CLAIMCLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +#[doc = "`read()` method returns [`claimclr::R`](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`claimclr::W`](W) writer structure"] impl crate::Writable for CLAIMCLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/claimset.rs b/arch/cortex-m/samv71q21-pac/src/etm/claimset.rs index fcfbba99..31c61d57 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/claimset.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/claimset.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLAIMSET` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLAIMSET` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Claim Tag Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +#[doc = "ETM Claim Tag Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claimset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claimset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLAIMSET_SPEC; impl crate::RegisterSpec for CLAIMSET_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [claimset::R](R) reader structure"] -impl crate::Readable for CLAIMSET_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +#[doc = "`read()` method returns [`claimset::R`](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`claimset::W`](W) writer structure"] impl crate::Writable for CLAIMSET_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/cntrldvr1.rs b/arch/cortex-m/samv71q21-pac/src/etm/cntrldvr1.rs index fdba1674..c416ad75 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/cntrldvr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/cntrldvr1.rs @@ -1,39 +1,7 @@ #[doc = "Register `CNTRLDVR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNTRLDVR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Free-running Counter Reload Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cntrldvr1](index.html) module"] +#[doc = "ETM Free-running Counter Reload Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntrldvr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntrldvr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNTRLDVR1_SPEC; impl crate::RegisterSpec for CNTRLDVR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cntrldvr1::R](R) reader structure"] -impl crate::Readable for CNTRLDVR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cntrldvr1::W](W) writer structure"] +#[doc = "`read()` method returns [`cntrldvr1::R`](R) reader structure"] +impl crate::Readable for CNTRLDVR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cntrldvr1::W`](W) writer structure"] impl crate::Writable for CNTRLDVR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/cr.rs b/arch/cortex-m/samv71q21-pac/src/etm/cr.rs index d939f8c3..b26a4699 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/cr.rs @@ -1,83 +1,51 @@ #[doc = "Register `CR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ETMPD` reader - ETM Power Down"] pub type ETMPD_R = crate::BitReader; #[doc = "Field `ETMPD` writer - ETM Power Down"] -pub type ETMPD_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ETMPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PORTSIZE` reader - Port Size bits 2:0"] pub type PORTSIZE_R = crate::FieldReader; #[doc = "Field `PORTSIZE` writer - Port Size bits 2:0"] -pub type PORTSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 3, O>; +pub type PORTSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `STALL` reader - Stall Processor"] pub type STALL_R = crate::BitReader; #[doc = "Field `STALL` writer - Stall Processor"] -pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type STALL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BROUT` reader - Branch Output"] pub type BROUT_R = crate::BitReader; #[doc = "Field `BROUT` writer - Branch Output"] -pub type BROUT_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type BROUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DBGRQ` reader - Debug Request Control"] pub type DBGRQ_R = crate::BitReader; #[doc = "Field `DBGRQ` writer - Debug Request Control"] -pub type DBGRQ_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type DBGRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PROG` reader - ETM Programming"] pub type PROG_R = crate::BitReader; #[doc = "Field `PROG` writer - ETM Programming"] -pub type PROG_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PROG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PORTSEL` reader - ETM Port Select"] pub type PORTSEL_R = crate::BitReader; #[doc = "Field `PORTSEL` writer - ETM Port Select"] -pub type PORTSEL_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PORTSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PORTMODE2` reader - Port Mode bit 2"] pub type PORTMODE2_R = crate::BitReader; #[doc = "Field `PORTMODE2` writer - Port Mode bit 2"] -pub type PORTMODE2_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PORTMODE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PORTMODE` reader - Port Mode bits 1:0"] pub type PORTMODE_R = crate::FieldReader; #[doc = "Field `PORTMODE` writer - Port Mode bits 1:0"] -pub type PORTMODE_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 2, O>; +pub type PORTMODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `PORTSIZE3` reader - Port Size bit 3"] pub type PORTSIZE3_R = crate::BitReader; #[doc = "Field `PORTSIZE3` writer - Port Size bit 3"] -pub type PORTSIZE3_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PORTSIZE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSEN` reader - TimeStamp Enable"] pub type TSEN_R = crate::BitReader; #[doc = "Field `TSEN` writer - TimeStamp Enable"] -pub type TSEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - ETM Power Down"] #[inline(always)] @@ -139,88 +107,85 @@ impl W { #[doc = "Bit 0 - ETM Power Down"] #[inline(always)] #[must_use] - pub fn etmpd(&mut self) -> ETMPD_W<0> { + pub fn etmpd(&mut self) -> ETMPD_W { ETMPD_W::new(self) } #[doc = "Bits 4:6 - Port Size bits 2:0"] #[inline(always)] #[must_use] - pub fn portsize(&mut self) -> PORTSIZE_W<4> { + pub fn portsize(&mut self) -> PORTSIZE_W { PORTSIZE_W::new(self) } #[doc = "Bit 7 - Stall Processor"] #[inline(always)] #[must_use] - pub fn stall(&mut self) -> STALL_W<7> { + pub fn stall(&mut self) -> STALL_W { STALL_W::new(self) } #[doc = "Bit 8 - Branch Output"] #[inline(always)] #[must_use] - pub fn brout(&mut self) -> BROUT_W<8> { + pub fn brout(&mut self) -> BROUT_W { BROUT_W::new(self) } #[doc = "Bit 9 - Debug Request Control"] #[inline(always)] #[must_use] - pub fn dbgrq(&mut self) -> DBGRQ_W<9> { + pub fn dbgrq(&mut self) -> DBGRQ_W { DBGRQ_W::new(self) } #[doc = "Bit 10 - ETM Programming"] #[inline(always)] #[must_use] - pub fn prog(&mut self) -> PROG_W<10> { + pub fn prog(&mut self) -> PROG_W { PROG_W::new(self) } #[doc = "Bit 11 - ETM Port Select"] #[inline(always)] #[must_use] - pub fn portsel(&mut self) -> PORTSEL_W<11> { + pub fn portsel(&mut self) -> PORTSEL_W { PORTSEL_W::new(self) } #[doc = "Bit 13 - Port Mode bit 2"] #[inline(always)] #[must_use] - pub fn portmode2(&mut self) -> PORTMODE2_W<13> { + pub fn portmode2(&mut self) -> PORTMODE2_W { PORTMODE2_W::new(self) } #[doc = "Bits 16:17 - Port Mode bits 1:0"] #[inline(always)] #[must_use] - pub fn portmode(&mut self) -> PORTMODE_W<16> { + pub fn portmode(&mut self) -> PORTMODE_W { PORTMODE_W::new(self) } #[doc = "Bit 21 - Port Size bit 3"] #[inline(always)] #[must_use] - pub fn portsize3(&mut self) -> PORTSIZE3_W<21> { + pub fn portsize3(&mut self) -> PORTSIZE3_W { PORTSIZE3_W::new(self) } #[doc = "Bit 28 - TimeStamp Enable"] #[inline(always)] #[must_use] - pub fn tsen(&mut self) -> TSEN_W<28> { + pub fn tsen(&mut self) -> TSEN_W { TSEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Main Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "ETM Main Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cr::R](R) reader structure"] -impl crate::Readable for CR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/devtype.rs b/arch/cortex-m/samv71q21-pac/src/etm/devtype.rs index 932a3a4b..b9d0dc31 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/devtype.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/devtype.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVTYPE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM CoreSight Device Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +#[doc = "ETM CoreSight Device Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devtype::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVTYPE_SPEC; impl crate::RegisterSpec for DEVTYPE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devtype::R](R) reader structure"] -impl crate::Readable for DEVTYPE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`devtype::R`](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC {} #[doc = "`reset()` method sets DEVTYPE to value 0x13"] impl crate::Resettable for DEVTYPE_SPEC { const RESET_VALUE: Self::Ux = 0x13; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/fflr.rs b/arch/cortex-m/samv71q21-pac/src/etm/fflr.rs index ee8fdf32..b4ff61aa 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/fflr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/fflr.rs @@ -1,39 +1,7 @@ #[doc = "Register `FFLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FFLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM FIFO Full Level Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fflr](index.html) module"] +#[doc = "ETM FIFO Full Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fflr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fflr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FFLR_SPEC; impl crate::RegisterSpec for FFLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fflr::R](R) reader structure"] -impl crate::Readable for FFLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fflr::W](W) writer structure"] +#[doc = "`read()` method returns [`fflr::R`](R) reader structure"] +impl crate::Readable for FFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fflr::W`](W) writer structure"] impl crate::Writable for FFLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/idr.rs b/arch/cortex-m/samv71q21-pac/src/etm/idr.rs index 9463818c..980a55e1 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/idr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "ETM ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [idr::R](R) reader structure"] -impl crate::Readable for IDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`idr::R`](R) reader structure"] +impl crate::Readable for IDR_SPEC {} #[doc = "`reset()` method sets IDR to value 0x4114_f250"] impl crate::Resettable for IDR_SPEC { const RESET_VALUE: Self::Ux = 0x4114_f250; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/idr2.rs b/arch/cortex-m/samv71q21-pac/src/etm/idr2.rs index 3bf5efb3..f7de1863 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/idr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/idr2.rs @@ -1,18 +1,5 @@ #[doc = "Register `IDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM ID Register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr2](index.html) module"] +#[doc = "ETM ID Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR2_SPEC; impl crate::RegisterSpec for IDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [idr2::R](R) reader structure"] -impl crate::Readable for IDR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`idr2::R`](R) reader structure"] +impl crate::Readable for IDR2_SPEC {} #[doc = "`reset()` method sets IDR2 to value 0"] impl crate::Resettable for IDR2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/itatbctr0.rs b/arch/cortex-m/samv71q21-pac/src/etm/itatbctr0.rs index 94905ee8..46f80b62 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/itatbctr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/itatbctr0.rs @@ -1,24 +1,5 @@ #[doc = "Register `ITATBCTR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") @@ -28,18 +9,17 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Integration Test ATB Control 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itatbctr0](index.html) module"] +#[doc = "ETM Integration Test ATB Control 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itatbctr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ITATBCTR0_SPEC; impl crate::RegisterSpec for ITATBCTR0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [itatbctr0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`itatbctr0::W`](W) writer structure"] impl crate::Writable for ITATBCTR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/itatbctr2.rs b/arch/cortex-m/samv71q21-pac/src/etm/itatbctr2.rs index 50d5b15a..8f2bdff0 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/itatbctr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/itatbctr2.rs @@ -1,18 +1,5 @@ #[doc = "Register `ITATBCTR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Integration Test ATB Control 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itatbctr2](index.html) module"] +#[doc = "ETM Integration Test ATB Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itatbctr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ITATBCTR2_SPEC; impl crate::RegisterSpec for ITATBCTR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [itatbctr2::R](R) reader structure"] -impl crate::Readable for ITATBCTR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`itatbctr2::R`](R) reader structure"] +impl crate::Readable for ITATBCTR2_SPEC {} #[doc = "`reset()` method sets ITATBCTR2 to value 0"] impl crate::Resettable for ITATBCTR2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/itctrl.rs b/arch/cortex-m/samv71q21-pac/src/etm/itctrl.rs index a2c6040d..78e602f3 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/itctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/itctrl.rs @@ -1,43 +1,11 @@ #[doc = "Register `ITCTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ITCTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INTEGRATION` reader - "] pub type INTEGRATION_R = crate::BitReader; #[doc = "Field `INTEGRATION` writer - "] -pub type INTEGRATION_W<'a, const O: u8> = crate::BitWriter<'a, ITCTRL_SPEC, O>; +pub type INTEGRATION_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bit 0"] #[inline(always)] #[must_use] - pub fn integration(&mut self) -> INTEGRATION_W<0> { + pub fn integration(&mut self) -> INTEGRATION_W { INTEGRATION_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Integration Mode Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +#[doc = "ETM Integration Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`itctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ITCTRL_SPEC; impl crate::RegisterSpec for ITCTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [itctrl::R](R) reader structure"] -impl crate::Readable for ITCTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`itctrl::R`](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itctrl::W`](W) writer structure"] impl crate::Writable for ITCTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/itmiscin.rs b/arch/cortex-m/samv71q21-pac/src/etm/itmiscin.rs index cec037c0..6789bc35 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/itmiscin.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/itmiscin.rs @@ -1,18 +1,5 @@ #[doc = "Register `ITMISCIN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Integration Test Miscellaneous Inputs\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itmiscin](index.html) module"] +#[doc = "ETM Integration Test Miscellaneous Inputs\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`itmiscin::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ITMISCIN_SPEC; impl crate::RegisterSpec for ITMISCIN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [itmiscin::R](R) reader structure"] -impl crate::Readable for ITMISCIN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`itmiscin::R`](R) reader structure"] +impl crate::Readable for ITMISCIN_SPEC {} #[doc = "`reset()` method sets ITMISCIN to value 0"] impl crate::Resettable for ITMISCIN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/ittrigout.rs b/arch/cortex-m/samv71q21-pac/src/etm/ittrigout.rs index 4d5a0945..98cf6ae4 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/ittrigout.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/ittrigout.rs @@ -1,24 +1,5 @@ #[doc = "Register `ITTRIGOUT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") @@ -28,18 +9,17 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Integration Test Trigger Out\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ittrigout](index.html) module"] +#[doc = "ETM Integration Test Trigger Out\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ittrigout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ITTRIGOUT_SPEC; impl crate::RegisterSpec for ITTRIGOUT_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ittrigout::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ittrigout::W`](W) writer structure"] impl crate::Writable for ITTRIGOUT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/lar.rs b/arch/cortex-m/samv71q21-pac/src/etm/lar.rs index c8189347..7034f0a3 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/lar.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/lar.rs @@ -1,24 +1,5 @@ #[doc = "Register `LAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for crate::generic::Reg { fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { write!(f, "(not readable)") @@ -28,18 +9,17 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Lock Access Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lar](index.html) module"] +#[doc = "ETM Lock Access Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lar::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LAR_SPEC; impl crate::RegisterSpec for LAR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [lar::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`lar::W`](W) writer structure"] impl crate::Writable for LAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/lsr.rs b/arch/cortex-m/samv71q21-pac/src/etm/lsr.rs index e7d7a86a..8444c56c 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/lsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/lsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `LSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `Present` reader - "] pub type PRESENT_R = crate::BitReader; #[doc = "Field `Access` reader - "] @@ -36,15 +23,13 @@ impl R { BYTE_ACC_R::new(((self.bits >> 2) & 1) != 0) } } -#[doc = "ETM Lock Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +#[doc = "ETM Lock Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LSR_SPEC; impl crate::RegisterSpec for LSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lsr::R](R) reader structure"] -impl crate::Readable for LSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`lsr::R`](R) reader structure"] +impl crate::Readable for LSR_SPEC {} #[doc = "`reset()` method sets LSR to value 0"] impl crate::Resettable for LSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pdsr.rs b/arch/cortex-m/samv71q21-pac/src/etm/pdsr.rs index c2ac0c22..921623cc 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pdsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pdsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PDSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Device Power-Down Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdsr](index.html) module"] +#[doc = "ETM Device Power-Down Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDSR_SPEC; impl crate::RegisterSpec for PDSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pdsr::R](R) reader structure"] -impl crate::Readable for PDSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pdsr::R`](R) reader structure"] +impl crate::Readable for PDSR_SPEC {} #[doc = "`reset()` method sets PDSR to value 0x01"] impl crate::Resettable for PDSR_SPEC { const RESET_VALUE: Self::Ux = 0x01; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr0.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr0.rs index 65bcee79..084c8c07 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr0.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr0](index.html) module"] +#[doc = "ETM Peripheral Identification Register #0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR0_SPEC; impl crate::RegisterSpec for PIDR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr0::R](R) reader structure"] -impl crate::Readable for PIDR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr0::R`](R) reader structure"] +impl crate::Readable for PIDR0_SPEC {} #[doc = "`reset()` method sets PIDR0 to value 0x25"] impl crate::Resettable for PIDR0_SPEC { const RESET_VALUE: Self::Ux = 0x25; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr1.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr1.rs index 0d549aa3..4f755638 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr1](index.html) module"] +#[doc = "ETM Peripheral Identification Register #1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR1_SPEC; impl crate::RegisterSpec for PIDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr1::R](R) reader structure"] -impl crate::Readable for PIDR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr1::R`](R) reader structure"] +impl crate::Readable for PIDR1_SPEC {} #[doc = "`reset()` method sets PIDR1 to value 0xb9"] impl crate::Resettable for PIDR1_SPEC { const RESET_VALUE: Self::Ux = 0xb9; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr2.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr2.rs index 8f85e63b..724e3d23 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr2.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr2](index.html) module"] +#[doc = "ETM Peripheral Identification Register #2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR2_SPEC; impl crate::RegisterSpec for PIDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr2::R](R) reader structure"] -impl crate::Readable for PIDR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr2::R`](R) reader structure"] +impl crate::Readable for PIDR2_SPEC {} #[doc = "`reset()` method sets PIDR2 to value 0x0b"] impl crate::Resettable for PIDR2_SPEC { const RESET_VALUE: Self::Ux = 0x0b; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr3.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr3.rs index d60be78c..2e1d0c47 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr3.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr3.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr3](index.html) module"] +#[doc = "ETM Peripheral Identification Register #3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR3_SPEC; impl crate::RegisterSpec for PIDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr3::R](R) reader structure"] -impl crate::Readable for PIDR3_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr3::R`](R) reader structure"] +impl crate::Readable for PIDR3_SPEC {} #[doc = "`reset()` method sets PIDR3 to value 0"] impl crate::Resettable for PIDR3_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr4.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr4.rs index 9092cf21..2ed95bcf 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr4.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr4.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr4](index.html) module"] +#[doc = "ETM Peripheral Identification Register #4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR4_SPEC; impl crate::RegisterSpec for PIDR4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr4::R](R) reader structure"] -impl crate::Readable for PIDR4_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr4::R`](R) reader structure"] +impl crate::Readable for PIDR4_SPEC {} #[doc = "`reset()` method sets PIDR4 to value 0x04"] impl crate::Resettable for PIDR4_SPEC { const RESET_VALUE: Self::Ux = 0x04; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr5.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr5.rs index 72a478d3..9933c149 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr5.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr5.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR5` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr5](index.html) module"] +#[doc = "ETM Peripheral Identification Register #5\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR5_SPEC; impl crate::RegisterSpec for PIDR5_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr5::R](R) reader structure"] -impl crate::Readable for PIDR5_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr5::R`](R) reader structure"] +impl crate::Readable for PIDR5_SPEC {} #[doc = "`reset()` method sets PIDR5 to value 0"] impl crate::Resettable for PIDR5_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr6.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr6.rs index 4f19ba39..3d072346 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr6.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr6.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR6` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr6](index.html) module"] +#[doc = "ETM Peripheral Identification Register #6\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr6::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR6_SPEC; impl crate::RegisterSpec for PIDR6_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr6::R](R) reader structure"] -impl crate::Readable for PIDR6_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr6::R`](R) reader structure"] +impl crate::Readable for PIDR6_SPEC {} #[doc = "`reset()` method sets PIDR6 to value 0"] impl crate::Resettable for PIDR6_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/pidr7.rs b/arch/cortex-m/samv71q21-pac/src/etm/pidr7.rs index 24603184..a91bad7a 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/pidr7.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/pidr7.rs @@ -1,18 +1,5 @@ #[doc = "Register `PIDR7` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Peripheral Identification Register #7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pidr7](index.html) module"] +#[doc = "ETM Peripheral Identification Register #7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pidr7::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PIDR7_SPEC; impl crate::RegisterSpec for PIDR7_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pidr7::R](R) reader structure"] -impl crate::Readable for PIDR7_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pidr7::R`](R) reader structure"] +impl crate::Readable for PIDR7_SPEC {} #[doc = "`reset()` method sets PIDR7 to value 0"] impl crate::Resettable for PIDR7_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/scr.rs b/arch/cortex-m/samv71q21-pac/src/etm/scr.rs index ba78b37b..2aa1d021 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/scr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/scr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM System Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +#[doc = "ETM System Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCR_SPEC; impl crate::RegisterSpec for SCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scr::R](R) reader structure"] -impl crate::Readable for SCR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`scr::R`](R) reader structure"] +impl crate::Readable for SCR_SPEC {} #[doc = "`reset()` method sets SCR to value 0x0002_0d09"] impl crate::Resettable for SCR_SPEC { const RESET_VALUE: Self::Ux = 0x0002_0d09; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/sr.rs b/arch/cortex-m/samv71q21-pac/src/etm/sr.rs index 618ea128..bc47cda3 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/sr.rs @@ -1,39 +1,7 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "ETM Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sr::W](W) writer structure"] +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"] impl crate::Writable for SR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/syncfr.rs b/arch/cortex-m/samv71q21-pac/src/etm/syncfr.rs index ed99302d..20783c98 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/syncfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/syncfr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SYNCFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -23,15 +10,13 @@ impl core::fmt::Debug for crate::generic::Reg { self.read().fmt(f) } } -#[doc = "ETM Synchronization Frequency Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncfr](index.html) module"] +#[doc = "ETM Synchronization Frequency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`syncfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYNCFR_SPEC; impl crate::RegisterSpec for SYNCFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [syncfr::R](R) reader structure"] -impl crate::Readable for SYNCFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`syncfr::R`](R) reader structure"] +impl crate::Readable for SYNCFR_SPEC {} #[doc = "`reset()` method sets SYNCFR to value 0x0400"] impl crate::Resettable for SYNCFR_SPEC { const RESET_VALUE: Self::Ux = 0x0400; diff --git a/arch/cortex-m/samv71q21-pac/src/etm/tecr1.rs b/arch/cortex-m/samv71q21-pac/src/etm/tecr1.rs index 44b26a0d..10f0ed13 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/tecr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/tecr1.rs @@ -1,39 +1,7 @@ #[doc = "Register `TECR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TECR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM TraceEnable Control 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tecr1](index.html) module"] +#[doc = "ETM TraceEnable Control 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tecr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tecr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TECR1_SPEC; impl crate::RegisterSpec for TECR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tecr1::R](R) reader structure"] -impl crate::Readable for TECR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tecr1::W](W) writer structure"] +#[doc = "`read()` method returns [`tecr1::R`](R) reader structure"] +impl crate::Readable for TECR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tecr1::W`](W) writer structure"] impl crate::Writable for TECR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/teevr.rs b/arch/cortex-m/samv71q21-pac/src/etm/teevr.rs index e740ca84..ea35a1b3 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/teevr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/teevr.rs @@ -1,39 +1,7 @@ #[doc = "Register `TEEVR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TEEVR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM TraceEnable Event Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [teevr](index.html) module"] +#[doc = "ETM TraceEnable Event Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`teevr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`teevr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TEEVR_SPEC; impl crate::RegisterSpec for TEEVR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [teevr::R](R) reader structure"] -impl crate::Readable for TEEVR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [teevr::W](W) writer structure"] +#[doc = "`read()` method returns [`teevr::R`](R) reader structure"] +impl crate::Readable for TEEVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`teevr::W`](W) writer structure"] impl crate::Writable for TEEVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/tesseicr.rs b/arch/cortex-m/samv71q21-pac/src/etm/tesseicr.rs index 6ca30c83..c5cf029c 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/tesseicr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/tesseicr.rs @@ -1,39 +1,7 @@ #[doc = "Register `TESSEICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TESSEICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM TraceEnable Start/Stop EmbeddedICE Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tesseicr](index.html) module"] +#[doc = "ETM TraceEnable Start/Stop EmbeddedICE Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tesseicr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tesseicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TESSEICR_SPEC; impl crate::RegisterSpec for TESSEICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tesseicr::R](R) reader structure"] -impl crate::Readable for TESSEICR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tesseicr::W](W) writer structure"] +#[doc = "`read()` method returns [`tesseicr::R`](R) reader structure"] +impl crate::Readable for TESSEICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tesseicr::W`](W) writer structure"] impl crate::Writable for TESSEICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/traceidr.rs b/arch/cortex-m/samv71q21-pac/src/etm/traceidr.rs index e91b4277..0fe19157 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/traceidr.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/traceidr.rs @@ -1,39 +1,7 @@ #[doc = "Register `TRACEIDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TRACEIDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM CoreSight Trace ID Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [traceidr](index.html) module"] +#[doc = "ETM CoreSight Trace ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`traceidr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`traceidr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TRACEIDR_SPEC; impl crate::RegisterSpec for TRACEIDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [traceidr::R](R) reader structure"] -impl crate::Readable for TRACEIDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [traceidr::W](W) writer structure"] +#[doc = "`read()` method returns [`traceidr::R`](R) reader structure"] +impl crate::Readable for TRACEIDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`traceidr::W`](W) writer structure"] impl crate::Writable for TRACEIDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/trigger.rs b/arch/cortex-m/samv71q21-pac/src/etm/trigger.rs index 81feabc5..54882dc2 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/trigger.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/trigger.rs @@ -1,39 +1,7 @@ #[doc = "Register `TRIGGER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TRIGGER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM Trigger Event Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [trigger](index.html) module"] +#[doc = "ETM Trigger Event Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigger::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TRIGGER_SPEC; impl crate::RegisterSpec for TRIGGER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [trigger::R](R) reader structure"] -impl crate::Readable for TRIGGER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [trigger::W](W) writer structure"] +#[doc = "`read()` method returns [`trigger::R`](R) reader structure"] +impl crate::Readable for TRIGGER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"] impl crate::Writable for TRIGGER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/etm/tsevt.rs b/arch/cortex-m/samv71q21-pac/src/etm/tsevt.rs index bac99652..52a3ad09 100644 --- a/arch/cortex-m/samv71q21-pac/src/etm/tsevt.rs +++ b/arch/cortex-m/samv71q21-pac/src/etm/tsevt.rs @@ -1,39 +1,7 @@ #[doc = "Register `TSEVT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSEVT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { write!(f, "{}", self.bits()) @@ -48,22 +16,19 @@ impl W { #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ETM TimeStamp Event Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsevt](index.html) module"] +#[doc = "ETM TimeStamp Event Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsevt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsevt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSEVT_SPEC; impl crate::RegisterSpec for TSEVT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tsevt::R](R) reader structure"] -impl crate::Readable for TSEVT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tsevt::W](W) writer structure"] +#[doc = "`read()` method returns [`tsevt::R`](R) reader structure"] +impl crate::Readable for TSEVT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tsevt::W`](W) writer structure"] impl crate::Writable for TSEVT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/generic.rs b/arch/cortex-m/samv71q21-pac/src/generic.rs index a592894e..551a0aef 100644 --- a/arch/cortex-m/samv71q21-pac/src/generic.rs +++ b/arch/cortex-m/samv71q21-pac/src/generic.rs @@ -53,18 +53,13 @@ pub trait FieldSpec: Sized { #[doc = " Trait implemented by readable registers to enable the `read` method."] #[doc = ""] #[doc = " Registers marked with `Writable` can be also be `modify`'ed."] -pub trait Readable: RegisterSpec { - #[doc = " Result from a call to `read` and argument to `modify`."] - type Reader: From> + core::ops::Deref>; -} +pub trait Readable: RegisterSpec {} #[doc = " Trait implemented by writeable registers."] #[doc = ""] #[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] #[doc = ""] #[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable: RegisterSpec { - #[doc = " Writer type argument to `write`, et al."] - type Writer: From> + core::ops::DerefMut>; #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] @@ -115,11 +110,11 @@ impl Reg { #[doc = " let flag = reader.field2().bit_is_set();"] #[doc = " ```"] #[inline(always)] - pub fn read(&self) -> REG::Reader { - REG::Reader::from(R { + pub fn read(&self) -> R { + R { bits: self.register.get(), _reg: marker::PhantomData, - }) + } } } impl Reg { @@ -156,14 +151,14 @@ impl Reg { #[inline(always)] pub fn write(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -179,13 +174,13 @@ impl Reg { #[inline(always)] pub unsafe fn write_with_zero(&self, f: F) where - F: FnOnce(&mut REG::Writer) -> &mut W, + F: FnOnce(&mut W) -> &mut W, { self.register.set( - f(&mut REG::Writer::from(W { + f(&mut W { bits: REG::Ux::default(), _reg: marker::PhantomData, - })) + }) .bits, ); } @@ -219,33 +214,32 @@ impl Reg { #[inline(always)] pub fn modify(&self, f: F) where - for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set( f( - ®::Reader::from(R { + &R { bits, _reg: marker::PhantomData, - }), - &mut REG::Writer::from(W { + }, + &mut W { bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, _reg: marker::PhantomData, - }), + }, ) .bits, ); } } +#[doc(hidden)] +pub mod raw; #[doc = " Register reader."] #[doc = ""] #[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] #[doc = " method."] -pub struct R { - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} +pub type R = raw::R; impl R { #[doc = " Reads raw bits from register."] #[inline(always)] @@ -267,64 +261,13 @@ where #[doc = " Register writer."] #[doc = ""] #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] -pub struct W { - #[doc = "Writable bits"] - pub(crate) bits: REG::Ux, - _reg: marker::PhantomData, -} -impl W { - #[doc = " Writes raw bits to the register."] - #[doc = ""] - #[doc = " # Safety"] - #[doc = ""] - #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { - self.bits = bits; - self - } -} -#[doc(hidden)] -pub struct FieldReaderRaw -where - FI: FieldSpec, -{ - pub(crate) bits: FI::Ux, - _reg: marker::PhantomData, -} -impl FieldReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: FI::Ux) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitReaderRaw { - pub(crate) bits: bool, - _reg: marker::PhantomData, -} -impl BitReaderRaw { - #[doc = " Creates a new instance of the reader."] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(bits: bool) -> Self { - Self { - bits, - _reg: marker::PhantomData, - } - } -} +pub type W = raw::W; #[doc = " Field reader."] #[doc = ""] #[doc = " Result of the `read` methods of fields."] -pub type FieldReader = FieldReaderRaw; +pub type FieldReader = raw::FieldReader; #[doc = " Bit-wise field reader"] -pub type BitReader = BitReaderRaw; +pub type BitReader = raw::BitReader; impl FieldReader { #[doc = " Reads raw bits from field."] #[inline(always)] @@ -372,60 +315,12 @@ impl BitReader { pub struct Safe; #[doc(hidden)] pub struct Unsafe; -#[doc(hidden)] -pub struct FieldWriterRaw<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, Safety)>, -} -impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriterRaw<'a, REG, WI, O, FI, Safety> -where - REG: Writable + RegisterSpec, - FI: FieldSpec, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} -#[doc(hidden)] -pub struct BitWriterRaw<'a, REG, const O: u8, FI = bool, M = BitM> -where - REG: Writable + RegisterSpec, - bool: From, -{ - pub(crate) w: &'a mut REG::Writer, - _field: marker::PhantomData<(FI, M)>, -} -impl<'a, REG, const O: u8, FI, M> BitWriterRaw<'a, REG, O, FI, M> -where - REG: Writable + RegisterSpec, - bool: From, -{ - #[doc = " Creates a new instance of the writer"] - #[allow(unused)] - #[inline(always)] - pub(crate) fn new(w: &'a mut REG::Writer) -> Self { - Self { - w, - _field: marker::PhantomData, - } - } -} #[doc = " Write field Proxy with unsafe `bits`"] pub type FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8> = - FieldWriterRaw<'a, REG, WI, O, FI, Unsafe>; + raw::FieldWriter<'a, REG, WI, O, FI, Unsafe>; #[doc = " Write field Proxy with safe `bits`"] pub type FieldWriterSafe<'a, REG, const WI: u8, const O: u8, FI = u8> = - FieldWriterRaw<'a, REG, WI, O, FI, Safe>; + raw::FieldWriter<'a, REG, WI, O, FI, Safe>; impl<'a, REG, const WI: u8, const OF: u8, FI> FieldWriter<'a, REG, WI, OF, FI> where REG: Writable + RegisterSpec, @@ -447,7 +342,7 @@ macro_rules! bit_proxy { #[doc(hidden)] pub struct $mwv; #[doc = " Bit-wise write field proxy"] - pub type $writer<'a, REG, const O: u8, FI = bool> = BitWriterRaw<'a, REG, O, FI, $mwv>; + pub type $writer<'a, REG, const O: u8, FI = bool> = raw::BitWriter<'a, REG, O, FI, $mwv>; impl<'a, REG, const OF: u8, FI> $writer<'a, REG, OF, FI> where REG: Writable + RegisterSpec, @@ -467,14 +362,14 @@ macro_rules! impl_bit_proxy { { #[doc = " Writes bit to the field"] #[inline(always)] - pub fn bit(self, value: bool) -> &'a mut REG::Writer { + pub fn bit(self, value: bool) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { self.bit(bool::from(variant)) } } @@ -499,14 +394,14 @@ where #[doc = ""] #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] #[inline(always)] - pub unsafe fn bits(self, value: FI::Ux) -> &'a mut REG::Writer { + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { self.w.bits &= !(REG::Ux::mask::() << OF); self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { unsafe { self.bits(FI::Ux::from(variant)) } } } @@ -518,14 +413,14 @@ where { #[doc = " Writes raw bits to the field"] #[inline(always)] - pub fn bits(self, value: FI::Ux) -> &'a mut REG::Writer { + pub fn bits(self, value: FI::Ux) -> &'a mut W { self.w.bits &= !(REG::Ux::mask::() << OF); self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << OF; self.w } #[doc = " Writes `variant` to the field"] #[inline(always)] - pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + pub fn variant(self, variant: FI) -> &'a mut W { self.bits(FI::Ux::from(variant)) } } @@ -543,13 +438,13 @@ where { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { + pub fn set_bit(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { + pub fn clear_bit(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } @@ -561,7 +456,7 @@ where { #[doc = " Sets the field bit"] #[inline(always)] - pub fn set_bit(self) -> &'a mut REG::Writer { + pub fn set_bit(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } @@ -573,7 +468,7 @@ where { #[doc = " Clears the field bit"] #[inline(always)] - pub fn clear_bit(self) -> &'a mut REG::Writer { + pub fn clear_bit(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } @@ -585,7 +480,7 @@ where { #[doc = "Clears the field bit by passing one"] #[inline(always)] - pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + pub fn clear_bit_by_one(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } @@ -597,7 +492,7 @@ where { #[doc = "Sets the field bit by passing zero"] #[inline(always)] - pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + pub fn set_bit_by_zero(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } @@ -609,7 +504,7 @@ where { #[doc = "Toggle the field bit by passing one"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { + pub fn toggle_bit(self) -> &'a mut W { self.w.bits |= REG::Ux::one() << OF; self.w } @@ -621,7 +516,7 @@ where { #[doc = "Toggle the field bit by passing zero"] #[inline(always)] - pub fn toggle_bit(self) -> &'a mut REG::Writer { + pub fn toggle_bit(self) -> &'a mut W { self.w.bits &= !(REG::Ux::one() << OF); self.w } diff --git a/arch/cortex-m/samv71q21-pac/src/generic/raw.rs b/arch/cortex-m/samv71q21-pac/src/generic/raw.rs new file mode 100644 index 00000000..74e77524 --- /dev/null +++ b/arch/cortex-m/samv71q21-pac/src/generic/raw.rs @@ -0,0 +1,89 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, const O: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, const O: u8, FI, Safety> FieldWriter<'a, REG, WI, O, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, const O: u8, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, const O: u8, FI, M> BitWriter<'a, REG, O, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} diff --git a/arch/cortex-m/samv71q21-pac/src/gmac.rs b/arch/cortex-m/samv71q21-pac/src/gmac.rs index bad69349..29ff1653 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac.rs @@ -274,87 +274,108 @@ impl RegisterBlock { &self.gmac_sa[3] } } -#[doc = "NCR (rw) register accessor: an alias for `Reg`"] +#[doc = "NCR (rw) register accessor: Network Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ncr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ncr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ncr`] +module"] pub type NCR = crate::Reg; #[doc = "Network Control Register"] pub mod ncr; -#[doc = "NCFGR (rw) register accessor: an alias for `Reg`"] +#[doc = "NCFGR (rw) register accessor: Network Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ncfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ncfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ncfgr`] +module"] pub type NCFGR = crate::Reg; #[doc = "Network Configuration Register"] pub mod ncfgr; -#[doc = "NSR (r) register accessor: an alias for `Reg`"] +#[doc = "NSR (r) register accessor: Network Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`nsr`] +module"] pub type NSR = crate::Reg; #[doc = "Network Status Register"] pub mod nsr; -#[doc = "UR (rw) register accessor: an alias for `Reg`"] +#[doc = "UR (rw) register accessor: User Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ur::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ur::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ur`] +module"] pub type UR = crate::Reg; #[doc = "User Register"] pub mod ur; -#[doc = "DCFGR (rw) register accessor: an alias for `Reg`"] +#[doc = "DCFGR (rw) register accessor: DMA Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dcfgr`] +module"] pub type DCFGR = crate::Reg; #[doc = "DMA Configuration Register"] pub mod dcfgr; -#[doc = "TSR (rw) register accessor: an alias for `Reg`"] +#[doc = "TSR (rw) register accessor: Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tsr`] +module"] pub type TSR = crate::Reg; #[doc = "Transmit Status Register"] pub mod tsr; -#[doc = "RBQB (rw) register accessor: an alias for `Reg`"] +#[doc = "RBQB (rw) register accessor: Receive Buffer Queue Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbqb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbqb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbqb`] +module"] pub type RBQB = crate::Reg; #[doc = "Receive Buffer Queue Base Address Register"] pub mod rbqb; -#[doc = "TBQB (rw) register accessor: an alias for `Reg`"] +#[doc = "TBQB (rw) register accessor: Transmit Buffer Queue Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbqb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tbqb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbqb`] +module"] pub type TBQB = crate::Reg; #[doc = "Transmit Buffer Queue Base Address Register"] pub mod tbqb; -#[doc = "RSR (rw) register accessor: an alias for `Reg`"] +#[doc = "RSR (rw) register accessor: Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rsr`] +module"] pub type RSR = crate::Reg; #[doc = "Receive Status Register"] pub mod rsr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (rw) register accessor: an alias for `Reg`"] +#[doc = "IMR (rw) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "MAN (rw) register accessor: an alias for `Reg`"] +#[doc = "MAN (rw) register accessor: PHY Maintenance Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`man::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`man::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`man`] +module"] pub type MAN = crate::Reg; #[doc = "PHY Maintenance Register"] pub mod man; -#[doc = "RPQ (r) register accessor: an alias for `Reg`"] +#[doc = "RPQ (r) register accessor: Received Pause Quantum Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rpq::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rpq`] +module"] pub type RPQ = crate::Reg; #[doc = "Received Pause Quantum Register"] pub mod rpq; -#[doc = "TPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "TPQ (rw) register accessor: Transmit Pause Quantum Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tpq`] +module"] pub type TPQ = crate::Reg; #[doc = "Transmit Pause Quantum Register"] pub mod tpq; -#[doc = "TPSF (rw) register accessor: an alias for `Reg`"] +#[doc = "TPSF (rw) register accessor: TX Partial Store and Forward Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpsf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpsf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tpsf`] +module"] pub type TPSF = crate::Reg; #[doc = "TX Partial Store and Forward Register"] pub mod tpsf; -#[doc = "RPSF (rw) register accessor: an alias for `Reg`"] +#[doc = "RPSF (rw) register accessor: RX Partial Store and Forward Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rpsf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rpsf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rpsf`] +module"] pub type RPSF = crate::Reg; #[doc = "RX Partial Store and Forward Register"] pub mod rpsf; -#[doc = "RJFML (rw) register accessor: an alias for `Reg`"] +#[doc = "RJFML (rw) register accessor: RX Jumbo Frame Max Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rjfml::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rjfml::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rjfml`] +module"] pub type RJFML = crate::Reg; #[doc = "RX Jumbo Frame Max Length Register"] pub mod rjfml; -#[doc = "HRB (rw) register accessor: an alias for `Reg`"] +#[doc = "HRB (rw) register accessor: Hash Register Bottom\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hrb`] +module"] pub type HRB = crate::Reg; #[doc = "Hash Register Bottom"] pub mod hrb; -#[doc = "HRT (rw) register accessor: an alias for `Reg`"] +#[doc = "HRT (rw) register accessor: Hash Register Top\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hrt`] +module"] pub type HRT = crate::Reg; #[doc = "Hash Register Top"] pub mod hrt; @@ -363,375 +384,468 @@ pub use self::gmac_sa::GMAC_SA; #[doc = r"Cluster"] #[doc = "Specific Address 1 Bottom Register"] pub mod gmac_sa; -#[doc = "TIDM1 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIDM1 (rw) register accessor: Type ID Match 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tidm1`] +module"] pub type TIDM1 = crate::Reg; #[doc = "Type ID Match 1 Register"] pub mod tidm1; -#[doc = "TIDM2 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIDM2 (rw) register accessor: Type ID Match 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tidm2`] +module"] pub type TIDM2 = crate::Reg; #[doc = "Type ID Match 2 Register"] pub mod tidm2; -#[doc = "TIDM3 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIDM3 (rw) register accessor: Type ID Match 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tidm3`] +module"] pub type TIDM3 = crate::Reg; #[doc = "Type ID Match 3 Register"] pub mod tidm3; -#[doc = "TIDM4 (rw) register accessor: an alias for `Reg`"] +#[doc = "TIDM4 (rw) register accessor: Type ID Match 4 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tidm4`] +module"] pub type TIDM4 = crate::Reg; #[doc = "Type ID Match 4 Register"] pub mod tidm4; -#[doc = "WOL (rw) register accessor: an alias for `Reg`"] +#[doc = "WOL (rw) register accessor: Wake on LAN Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wol`] +module"] pub type WOL = crate::Reg; #[doc = "Wake on LAN Register"] pub mod wol; -#[doc = "IPGS (rw) register accessor: an alias for `Reg`"] +#[doc = "IPGS (rw) register accessor: IPG Stretch Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipgs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ipgs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ipgs`] +module"] pub type IPGS = crate::Reg; #[doc = "IPG Stretch Register"] pub mod ipgs; -#[doc = "SVLAN (rw) register accessor: an alias for `Reg`"] +#[doc = "SVLAN (rw) register accessor: Stacked VLAN Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`svlan::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`svlan::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`svlan`] +module"] pub type SVLAN = crate::Reg; #[doc = "Stacked VLAN Register"] pub mod svlan; -#[doc = "TPFCP (rw) register accessor: an alias for `Reg`"] +#[doc = "TPFCP (rw) register accessor: Transmit PFC Pause Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpfcp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpfcp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tpfcp`] +module"] pub type TPFCP = crate::Reg; #[doc = "Transmit PFC Pause Register"] pub mod tpfcp; -#[doc = "SAMB1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SAMB1 (rw) register accessor: Specific Address 1 Mask Bottom Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`samb1`] +module"] pub type SAMB1 = crate::Reg; #[doc = "Specific Address 1 Mask Bottom Register"] pub mod samb1; -#[doc = "SAMT1 (rw) register accessor: an alias for `Reg`"] +#[doc = "SAMT1 (rw) register accessor: Specific Address 1 Mask Top Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samt1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samt1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`samt1`] +module"] pub type SAMT1 = crate::Reg; #[doc = "Specific Address 1 Mask Top Register"] pub mod samt1; -#[doc = "NSC (rw) register accessor: an alias for `Reg`"] +#[doc = "NSC (rw) register accessor: 1588 Timer Nanosecond Comparison Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`nsc`] +module"] pub type NSC = crate::Reg; #[doc = "1588 Timer Nanosecond Comparison Register"] pub mod nsc; -#[doc = "SCL (rw) register accessor: an alias for `Reg`"] +#[doc = "SCL (rw) register accessor: 1588 Timer Second Comparison Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scl`] +module"] pub type SCL = crate::Reg; #[doc = "1588 Timer Second Comparison Low Register"] pub mod scl; -#[doc = "SCH (rw) register accessor: an alias for `Reg`"] +#[doc = "SCH (rw) register accessor: 1588 Timer Second Comparison High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sch::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sch::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sch`] +module"] pub type SCH = crate::Reg; #[doc = "1588 Timer Second Comparison High Register"] pub mod sch; -#[doc = "EFTSH (r) register accessor: an alias for `Reg`"] +#[doc = "EFTSH (r) register accessor: PTP Event Frame Transmitted Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eftsh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eftsh`] +module"] pub type EFTSH = crate::Reg; #[doc = "PTP Event Frame Transmitted Seconds High Register"] pub mod eftsh; -#[doc = "EFRSH (r) register accessor: an alias for `Reg`"] +#[doc = "EFRSH (r) register accessor: PTP Event Frame Received Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efrsh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`efrsh`] +module"] pub type EFRSH = crate::Reg; #[doc = "PTP Event Frame Received Seconds High Register"] pub mod efrsh; -#[doc = "PEFTSH (r) register accessor: an alias for `Reg`"] +#[doc = "PEFTSH (r) register accessor: PTP Peer Event Frame Transmitted Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peftsh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`peftsh`] +module"] pub type PEFTSH = crate::Reg; #[doc = "PTP Peer Event Frame Transmitted Seconds High Register"] pub mod peftsh; -#[doc = "PEFRSH (r) register accessor: an alias for `Reg`"] +#[doc = "PEFRSH (r) register accessor: PTP Peer Event Frame Received Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pefrsh::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pefrsh`] +module"] pub type PEFRSH = crate::Reg; #[doc = "PTP Peer Event Frame Received Seconds High Register"] pub mod pefrsh; -#[doc = "OTLO (r) register accessor: an alias for `Reg`"] +#[doc = "OTLO (r) register accessor: Octets Transmitted Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otlo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`otlo`] +module"] pub type OTLO = crate::Reg; #[doc = "Octets Transmitted Low Register"] pub mod otlo; -#[doc = "OTHI (r) register accessor: an alias for `Reg`"] +#[doc = "OTHI (r) register accessor: Octets Transmitted High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`othi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`othi`] +module"] pub type OTHI = crate::Reg; #[doc = "Octets Transmitted High Register"] pub mod othi; -#[doc = "FT (r) register accessor: an alias for `Reg`"] +#[doc = "FT (r) register accessor: Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ft::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ft`] +module"] pub type FT = crate::Reg; #[doc = "Frames Transmitted Register"] pub mod ft; -#[doc = "BCFT (r) register accessor: an alias for `Reg`"] +#[doc = "BCFT (r) register accessor: Broadcast Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bcft::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`bcft`] +module"] pub type BCFT = crate::Reg; #[doc = "Broadcast Frames Transmitted Register"] pub mod bcft; -#[doc = "MFT (r) register accessor: an alias for `Reg`"] +#[doc = "MFT (r) register accessor: Multicast Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mft::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mft`] +module"] pub type MFT = crate::Reg; #[doc = "Multicast Frames Transmitted Register"] pub mod mft; -#[doc = "PFT (r) register accessor: an alias for `Reg`"] +#[doc = "PFT (r) register accessor: Pause Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pft::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pft`] +module"] pub type PFT = crate::Reg; #[doc = "Pause Frames Transmitted Register"] pub mod pft; -#[doc = "BFT64 (r) register accessor: an alias for `Reg`"] +#[doc = "BFT64 (r) register accessor: 64 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bft64::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`bft64`] +module"] pub type BFT64 = crate::Reg; #[doc = "64 Byte Frames Transmitted Register"] pub mod bft64; -#[doc = "TBFT127 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFT127 (r) register accessor: 65 to 127 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft127::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbft127`] +module"] pub type TBFT127 = crate::Reg; #[doc = "65 to 127 Byte Frames Transmitted Register"] pub mod tbft127; -#[doc = "TBFT255 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFT255 (r) register accessor: 128 to 255 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft255::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbft255`] +module"] pub type TBFT255 = crate::Reg; #[doc = "128 to 255 Byte Frames Transmitted Register"] pub mod tbft255; -#[doc = "TBFT511 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFT511 (r) register accessor: 256 to 511 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft511::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbft511`] +module"] pub type TBFT511 = crate::Reg; #[doc = "256 to 511 Byte Frames Transmitted Register"] pub mod tbft511; -#[doc = "TBFT1023 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFT1023 (r) register accessor: 512 to 1023 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft1023::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbft1023`] +module"] pub type TBFT1023 = crate::Reg; #[doc = "512 to 1023 Byte Frames Transmitted Register"] pub mod tbft1023; -#[doc = "TBFT1518 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFT1518 (r) register accessor: 1024 to 1518 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft1518::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbft1518`] +module"] pub type TBFT1518 = crate::Reg; #[doc = "1024 to 1518 Byte Frames Transmitted Register"] pub mod tbft1518; -#[doc = "GTBFT1518 (r) register accessor: an alias for `Reg`"] +#[doc = "GTBFT1518 (r) register accessor: Greater Than 1518 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtbft1518::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gtbft1518`] +module"] pub type GTBFT1518 = crate::Reg; #[doc = "Greater Than 1518 Byte Frames Transmitted Register"] pub mod gtbft1518; -#[doc = "TUR (r) register accessor: an alias for `Reg`"] +#[doc = "TUR (r) register accessor: Transmit Underruns Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tur::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tur`] +module"] pub type TUR = crate::Reg; #[doc = "Transmit Underruns Register"] pub mod tur; -#[doc = "SCF (r) register accessor: an alias for `Reg`"] +#[doc = "SCF (r) register accessor: Single Collision Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scf`] +module"] pub type SCF = crate::Reg; #[doc = "Single Collision Frames Register"] pub mod scf; -#[doc = "MCF (r) register accessor: an alias for `Reg`"] +#[doc = "MCF (r) register accessor: Multiple Collision Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcf`] +module"] pub type MCF = crate::Reg; #[doc = "Multiple Collision Frames Register"] pub mod mcf; -#[doc = "EC (r) register accessor: an alias for `Reg`"] +#[doc = "EC (r) register accessor: Excessive Collisions Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ec::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ec`] +module"] pub type EC = crate::Reg; #[doc = "Excessive Collisions Register"] pub mod ec; -#[doc = "LC (r) register accessor: an alias for `Reg`"] +#[doc = "LC (r) register accessor: Late Collisions Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lc`] +module"] pub type LC = crate::Reg; #[doc = "Late Collisions Register"] pub mod lc; -#[doc = "DTF (r) register accessor: an alias for `Reg`"] +#[doc = "DTF (r) register accessor: Deferred Transmission Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dtf`] +module"] pub type DTF = crate::Reg; #[doc = "Deferred Transmission Frames Register"] pub mod dtf; -#[doc = "CSE (r) register accessor: an alias for `Reg`"] +#[doc = "CSE (r) register accessor: Carrier Sense Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cse`] +module"] pub type CSE = crate::Reg; #[doc = "Carrier Sense Errors Register"] pub mod cse; -#[doc = "ORLO (r) register accessor: an alias for `Reg`"] +#[doc = "ORLO (r) register accessor: Octets Received Low Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`orlo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`orlo`] +module"] pub type ORLO = crate::Reg; #[doc = "Octets Received Low Received Register"] pub mod orlo; -#[doc = "ORHI (r) register accessor: an alias for `Reg`"] +#[doc = "ORHI (r) register accessor: Octets Received High Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`orhi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`orhi`] +module"] pub type ORHI = crate::Reg; #[doc = "Octets Received High Received Register"] pub mod orhi; -#[doc = "FR (r) register accessor: an alias for `Reg`"] +#[doc = "FR (r) register accessor: Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fr`] +module"] pub type FR = crate::Reg; #[doc = "Frames Received Register"] pub mod fr; -#[doc = "BCFR (r) register accessor: an alias for `Reg`"] +#[doc = "BCFR (r) register accessor: Broadcast Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bcfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`bcfr`] +module"] pub type BCFR = crate::Reg; #[doc = "Broadcast Frames Received Register"] pub mod bcfr; -#[doc = "MFR (r) register accessor: an alias for `Reg`"] +#[doc = "MFR (r) register accessor: Multicast Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mfr`] +module"] pub type MFR = crate::Reg; #[doc = "Multicast Frames Received Register"] pub mod mfr; -#[doc = "PFR (r) register accessor: an alias for `Reg`"] +#[doc = "PFR (r) register accessor: Pause Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pfr`] +module"] pub type PFR = crate::Reg; #[doc = "Pause Frames Received Register"] pub mod pfr; -#[doc = "BFR64 (r) register accessor: an alias for `Reg`"] +#[doc = "BFR64 (r) register accessor: 64 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bfr64::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`bfr64`] +module"] pub type BFR64 = crate::Reg; #[doc = "64 Byte Frames Received Register"] pub mod bfr64; -#[doc = "TBFR127 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFR127 (r) register accessor: 65 to 127 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr127::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbfr127`] +module"] pub type TBFR127 = crate::Reg; #[doc = "65 to 127 Byte Frames Received Register"] pub mod tbfr127; -#[doc = "TBFR255 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFR255 (r) register accessor: 128 to 255 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr255::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbfr255`] +module"] pub type TBFR255 = crate::Reg; #[doc = "128 to 255 Byte Frames Received Register"] pub mod tbfr255; -#[doc = "TBFR511 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFR511 (r) register accessor: 256 to 511 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr511::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbfr511`] +module"] pub type TBFR511 = crate::Reg; #[doc = "256 to 511 Byte Frames Received Register"] pub mod tbfr511; -#[doc = "TBFR1023 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFR1023 (r) register accessor: 512 to 1023 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr1023::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbfr1023`] +module"] pub type TBFR1023 = crate::Reg; #[doc = "512 to 1023 Byte Frames Received Register"] pub mod tbfr1023; -#[doc = "TBFR1518 (r) register accessor: an alias for `Reg`"] +#[doc = "TBFR1518 (r) register accessor: 1024 to 1518 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr1518::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbfr1518`] +module"] pub type TBFR1518 = crate::Reg; #[doc = "1024 to 1518 Byte Frames Received Register"] pub mod tbfr1518; -#[doc = "TMXBFR (r) register accessor: an alias for `Reg`"] +#[doc = "TMXBFR (r) register accessor: 1519 to Maximum Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmxbfr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tmxbfr`] +module"] pub type TMXBFR = crate::Reg; #[doc = "1519 to Maximum Byte Frames Received Register"] pub mod tmxbfr; -#[doc = "UFR (r) register accessor: an alias for `Reg`"] +#[doc = "UFR (r) register accessor: Undersize Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ufr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ufr`] +module"] pub type UFR = crate::Reg; #[doc = "Undersize Frames Received Register"] pub mod ufr; -#[doc = "OFR (r) register accessor: an alias for `Reg`"] +#[doc = "OFR (r) register accessor: Oversize Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ofr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ofr`] +module"] pub type OFR = crate::Reg; #[doc = "Oversize Frames Received Register"] pub mod ofr; -#[doc = "JR (r) register accessor: an alias for `Reg`"] +#[doc = "JR (r) register accessor: Jabbers Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`jr`] +module"] pub type JR = crate::Reg; #[doc = "Jabbers Received Register"] pub mod jr; -#[doc = "FCSE (r) register accessor: an alias for `Reg`"] +#[doc = "FCSE (r) register accessor: Frame Check Sequence Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcse`] +module"] pub type FCSE = crate::Reg; #[doc = "Frame Check Sequence Errors Register"] pub mod fcse; -#[doc = "LFFE (r) register accessor: an alias for `Reg`"] +#[doc = "LFFE (r) register accessor: Length Field Frame Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lffe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lffe`] +module"] pub type LFFE = crate::Reg; #[doc = "Length Field Frame Errors Register"] pub mod lffe; -#[doc = "RSE (r) register accessor: an alias for `Reg`"] +#[doc = "RSE (r) register accessor: Receive Symbol Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rse`] +module"] pub type RSE = crate::Reg; #[doc = "Receive Symbol Errors Register"] pub mod rse; -#[doc = "AE (r) register accessor: an alias for `Reg`"] +#[doc = "AE (r) register accessor: Alignment Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ae`] +module"] pub type AE = crate::Reg; #[doc = "Alignment Errors Register"] pub mod ae; -#[doc = "RRE (r) register accessor: an alias for `Reg`"] +#[doc = "RRE (r) register accessor: Receive Resource Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rre::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rre`] +module"] pub type RRE = crate::Reg; #[doc = "Receive Resource Errors Register"] pub mod rre; -#[doc = "ROE (r) register accessor: an alias for `Reg`"] +#[doc = "ROE (r) register accessor: Receive Overrun Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`roe::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`roe`] +module"] pub type ROE = crate::Reg; #[doc = "Receive Overrun Register"] pub mod roe; -#[doc = "IHCE (r) register accessor: an alias for `Reg`"] +#[doc = "IHCE (r) register accessor: IP Header Checksum Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ihce::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ihce`] +module"] pub type IHCE = crate::Reg; #[doc = "IP Header Checksum Errors Register"] pub mod ihce; -#[doc = "TCE (r) register accessor: an alias for `Reg`"] +#[doc = "TCE (r) register accessor: TCP Checksum Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tce::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tce`] +module"] pub type TCE = crate::Reg; #[doc = "TCP Checksum Errors Register"] pub mod tce; -#[doc = "UCE (r) register accessor: an alias for `Reg`"] +#[doc = "UCE (r) register accessor: UDP Checksum Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uce::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`uce`] +module"] pub type UCE = crate::Reg; #[doc = "UDP Checksum Errors Register"] pub mod uce; -#[doc = "TISUBN (rw) register accessor: an alias for `Reg`"] +#[doc = "TISUBN (rw) register accessor: 1588 Timer Increment Sub-nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tisubn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tisubn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tisubn`] +module"] pub type TISUBN = crate::Reg; #[doc = "1588 Timer Increment Sub-nanoseconds Register"] pub mod tisubn; -#[doc = "TSH (rw) register accessor: an alias for `Reg`"] +#[doc = "TSH (rw) register accessor: 1588 Timer Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsh::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tsh`] +module"] pub type TSH = crate::Reg; #[doc = "1588 Timer Seconds High Register"] pub mod tsh; -#[doc = "TSL (rw) register accessor: an alias for `Reg`"] +#[doc = "TSL (rw) register accessor: 1588 Timer Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tsl`] +module"] pub type TSL = crate::Reg; #[doc = "1588 Timer Seconds Low Register"] pub mod tsl; -#[doc = "TN (rw) register accessor: an alias for `Reg`"] +#[doc = "TN (rw) register accessor: 1588 Timer Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tn::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tn`] +module"] pub type TN = crate::Reg; #[doc = "1588 Timer Nanoseconds Register"] pub mod tn; -#[doc = "TA (w) register accessor: an alias for `Reg`"] +#[doc = "TA (w) register accessor: 1588 Timer Adjust Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ta::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ta`] +module"] pub type TA = crate::Reg; #[doc = "1588 Timer Adjust Register"] pub mod ta; -#[doc = "TI (rw) register accessor: an alias for `Reg`"] +#[doc = "TI (rw) register accessor: 1588 Timer Increment Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ti::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ti::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ti`] +module"] pub type TI = crate::Reg; #[doc = "1588 Timer Increment Register"] pub mod ti; -#[doc = "EFTSL (r) register accessor: an alias for `Reg`"] +#[doc = "EFTSL (r) register accessor: PTP Event Frame Transmitted Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eftsl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eftsl`] +module"] pub type EFTSL = crate::Reg; #[doc = "PTP Event Frame Transmitted Seconds Low Register"] pub mod eftsl; -#[doc = "EFTN (r) register accessor: an alias for `Reg`"] +#[doc = "EFTN (r) register accessor: PTP Event Frame Transmitted Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eftn::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`eftn`] +module"] pub type EFTN = crate::Reg; #[doc = "PTP Event Frame Transmitted Nanoseconds Register"] pub mod eftn; -#[doc = "EFRSL (r) register accessor: an alias for `Reg`"] +#[doc = "EFRSL (r) register accessor: PTP Event Frame Received Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efrsl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`efrsl`] +module"] pub type EFRSL = crate::Reg; #[doc = "PTP Event Frame Received Seconds Low Register"] pub mod efrsl; -#[doc = "EFRN (r) register accessor: an alias for `Reg`"] +#[doc = "EFRN (r) register accessor: PTP Event Frame Received Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efrn::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`efrn`] +module"] pub type EFRN = crate::Reg; #[doc = "PTP Event Frame Received Nanoseconds Register"] pub mod efrn; -#[doc = "PEFTSL (r) register accessor: an alias for `Reg`"] +#[doc = "PEFTSL (r) register accessor: PTP Peer Event Frame Transmitted Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peftsl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`peftsl`] +module"] pub type PEFTSL = crate::Reg; #[doc = "PTP Peer Event Frame Transmitted Seconds Low Register"] pub mod peftsl; -#[doc = "PEFTN (r) register accessor: an alias for `Reg`"] +#[doc = "PEFTN (r) register accessor: PTP Peer Event Frame Transmitted Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peftn::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`peftn`] +module"] pub type PEFTN = crate::Reg; #[doc = "PTP Peer Event Frame Transmitted Nanoseconds Register"] pub mod peftn; -#[doc = "PEFRSL (r) register accessor: an alias for `Reg`"] +#[doc = "PEFRSL (r) register accessor: PTP Peer Event Frame Received Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pefrsl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pefrsl`] +module"] pub type PEFRSL = crate::Reg; #[doc = "PTP Peer Event Frame Received Seconds Low Register"] pub mod pefrsl; -#[doc = "PEFRN (r) register accessor: an alias for `Reg`"] +#[doc = "PEFRN (r) register accessor: PTP Peer Event Frame Received Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pefrn::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pefrn`] +module"] pub type PEFRN = crate::Reg; #[doc = "PTP Peer Event Frame Received Nanoseconds Register"] pub mod pefrn; -#[doc = "RXLPI (r) register accessor: an alias for `Reg`"] +#[doc = "RXLPI (r) register accessor: Received LPI Transitions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxlpi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxlpi`] +module"] pub type RXLPI = crate::Reg; #[doc = "Received LPI Transitions"] pub mod rxlpi; -#[doc = "RXLPITIME (r) register accessor: an alias for `Reg`"] +#[doc = "RXLPITIME (r) register accessor: Received LPI Time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxlpitime::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxlpitime`] +module"] pub type RXLPITIME = crate::Reg; #[doc = "Received LPI Time"] pub mod rxlpitime; -#[doc = "TXLPI (r) register accessor: an alias for `Reg`"] +#[doc = "TXLPI (r) register accessor: Transmit LPI Transitions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlpi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txlpi`] +module"] pub type TXLPI = crate::Reg; #[doc = "Transmit LPI Transitions"] pub mod txlpi; -#[doc = "TXLPITIME (r) register accessor: an alias for `Reg`"] +#[doc = "TXLPITIME (r) register accessor: Transmit LPI Time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlpitime::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txlpitime`] +module"] pub type TXLPITIME = crate::Reg; #[doc = "Transmit LPI Time"] pub mod txlpitime; -#[doc = "ISRPQ (r) register accessor: an alias for `Reg`"] +#[doc = "ISRPQ (r) register accessor: Interrupt Status Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isrpq::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isrpq`] +module"] pub type ISRPQ = crate::Reg; #[doc = "Interrupt Status Register Priority Queue (1..5)"] pub mod isrpq; -#[doc = "TBQBAPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "TBQBAPQ (rw) register accessor: Transmit Buffer Queue Base Address Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbqbapq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tbqbapq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tbqbapq`] +module"] pub type TBQBAPQ = crate::Reg; #[doc = "Transmit Buffer Queue Base Address Register Priority Queue (1..5)"] pub mod tbqbapq; -#[doc = "RBQBAPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "RBQBAPQ (rw) register accessor: Receive Buffer Queue Base Address Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbqbapq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbqbapq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbqbapq`] +module"] pub type RBQBAPQ = crate::Reg; #[doc = "Receive Buffer Queue Base Address Register Priority Queue (1..5)"] pub mod rbqbapq; -#[doc = "RBSRPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "RBSRPQ (rw) register accessor: Receive Buffer Size Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbsrpq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbsrpq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rbsrpq`] +module"] pub type RBSRPQ = crate::Reg; #[doc = "Receive Buffer Size Register Priority Queue (1..5)"] pub mod rbsrpq; -#[doc = "CBSCR (rw) register accessor: an alias for `Reg`"] +#[doc = "CBSCR (rw) register accessor: Credit-Based Shaping Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cbscr`] +module"] pub type CBSCR = crate::Reg; #[doc = "Credit-Based Shaping Control Register"] pub mod cbscr; -#[doc = "CBSISQA (rw) register accessor: an alias for `Reg`"] +#[doc = "CBSISQA (rw) register accessor: Credit-Based Shaping IdleSlope Register for Queue A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsisqa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsisqa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cbsisqa`] +module"] pub type CBSISQA = crate::Reg; #[doc = "Credit-Based Shaping IdleSlope Register for Queue A"] pub mod cbsisqa; -#[doc = "CBSISQB (rw) register accessor: an alias for `Reg`"] +#[doc = "CBSISQB (rw) register accessor: Credit-Based Shaping IdleSlope Register for Queue B\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsisqb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsisqb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cbsisqb`] +module"] pub type CBSISQB = crate::Reg; #[doc = "Credit-Based Shaping IdleSlope Register for Queue B"] pub mod cbsisqb; -#[doc = "ST1RPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "ST1RPQ (rw) register accessor: Screening Type 1 Register Priority Queue\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st1rpq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st1rpq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`st1rpq`] +module"] pub type ST1RPQ = crate::Reg; #[doc = "Screening Type 1 Register Priority Queue"] pub mod st1rpq; -#[doc = "ST2RPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "ST2RPQ (rw) register accessor: Screening Type 2 Register Priority Queue\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2rpq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2rpq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`st2rpq`] +module"] pub type ST2RPQ = crate::Reg; #[doc = "Screening Type 2 Register Priority Queue"] pub mod st2rpq; -#[doc = "IERPQ (w) register accessor: an alias for `Reg`"] +#[doc = "IERPQ (w) register accessor: Interrupt Enable Register Priority Queue (1..5)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ierpq::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ierpq`] +module"] pub type IERPQ = crate::Reg; #[doc = "Interrupt Enable Register Priority Queue (1..5)"] pub mod ierpq; -#[doc = "IDRPQ (w) register accessor: an alias for `Reg`"] +#[doc = "IDRPQ (w) register accessor: Interrupt Disable Register Priority Queue (1..5)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idrpq::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idrpq`] +module"] pub type IDRPQ = crate::Reg; #[doc = "Interrupt Disable Register Priority Queue (1..5)"] pub mod idrpq; -#[doc = "IMRPQ (rw) register accessor: an alias for `Reg`"] +#[doc = "IMRPQ (rw) register accessor: Interrupt Mask Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imrpq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imrpq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imrpq`] +module"] pub type IMRPQ = crate::Reg; #[doc = "Interrupt Mask Register Priority Queue (1..5)"] pub mod imrpq; -#[doc = "ST2ER (rw) register accessor: an alias for `Reg`"] +#[doc = "ST2ER (rw) register accessor: Screening Type 2 Ethertype Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2er::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2er::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`st2er`] +module"] pub type ST2ER = crate::Reg; #[doc = "Screening Type 2 Ethertype Register"] pub mod st2er; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ae.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ae.rs index 0bec840f..e8f9363d 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ae.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ae.rs @@ -1,18 +1,5 @@ #[doc = "Register `AE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `AER` reader - Alignment Errors"] pub type AER_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { AER_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Alignment Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ae](index.html) module"] +#[doc = "Alignment Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ae::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AE_SPEC; impl crate::RegisterSpec for AE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ae::R](R) reader structure"] -impl crate::Readable for AE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ae::R`](R) reader structure"] +impl crate::Readable for AE_SPEC {} #[doc = "`reset()` method sets AE to value 0"] impl crate::Resettable for AE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/bcfr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/bcfr.rs index 7550a123..a27abaad 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/bcfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/bcfr.rs @@ -1,18 +1,5 @@ #[doc = "Register `BCFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BFRX` reader - Broadcast Frames Received without Error"] pub type BFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { BFRX_R::new(self.bits) } } -#[doc = "Broadcast Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bcfr](index.html) module"] +#[doc = "Broadcast Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bcfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BCFR_SPEC; impl crate::RegisterSpec for BCFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bcfr::R](R) reader structure"] -impl crate::Readable for BCFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`bcfr::R`](R) reader structure"] +impl crate::Readable for BCFR_SPEC {} #[doc = "`reset()` method sets BCFR to value 0"] impl crate::Resettable for BCFR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/bcft.rs b/arch/cortex-m/samv71q21-pac/src/gmac/bcft.rs index 97ed61e8..4aa51e4c 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/bcft.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/bcft.rs @@ -1,18 +1,5 @@ #[doc = "Register `BCFT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BFTX` reader - Broadcast Frames Transmitted without Error"] pub type BFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { BFTX_R::new(self.bits) } } -#[doc = "Broadcast Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bcft](index.html) module"] +#[doc = "Broadcast Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bcft::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BCFT_SPEC; impl crate::RegisterSpec for BCFT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bcft::R](R) reader structure"] -impl crate::Readable for BCFT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`bcft::R`](R) reader structure"] +impl crate::Readable for BCFT_SPEC {} #[doc = "`reset()` method sets BCFT to value 0"] impl crate::Resettable for BCFT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/bfr64.rs b/arch/cortex-m/samv71q21-pac/src/gmac/bfr64.rs index 96cbb442..96aacca3 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/bfr64.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/bfr64.rs @@ -1,18 +1,5 @@ #[doc = "Register `BFR64` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 64 Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "64 Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bfr64](index.html) module"] +#[doc = "64 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bfr64::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BFR64_SPEC; impl crate::RegisterSpec for BFR64_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bfr64::R](R) reader structure"] -impl crate::Readable for BFR64_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`bfr64::R`](R) reader structure"] +impl crate::Readable for BFR64_SPEC {} #[doc = "`reset()` method sets BFR64 to value 0"] impl crate::Resettable for BFR64_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/bft64.rs b/arch/cortex-m/samv71q21-pac/src/gmac/bft64.rs index 4b13b97b..fb444e48 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/bft64.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/bft64.rs @@ -1,18 +1,5 @@ #[doc = "Register `BFT64` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - 64 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "64 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bft64](index.html) module"] +#[doc = "64 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bft64::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BFT64_SPEC; impl crate::RegisterSpec for BFT64_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bft64::R](R) reader structure"] -impl crate::Readable for BFT64_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`bft64::R`](R) reader structure"] +impl crate::Readable for BFT64_SPEC {} #[doc = "`reset()` method sets BFT64 to value 0"] impl crate::Resettable for BFT64_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/cbscr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/cbscr.rs index b25fd132..c1da8eb5 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/cbscr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/cbscr.rs @@ -1,47 +1,15 @@ #[doc = "Register `CBSCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CBSCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `QBE` reader - Queue B CBS Enable"] pub type QBE_R = crate::BitReader; #[doc = "Field `QBE` writer - Queue B CBS Enable"] -pub type QBE_W<'a, const O: u8> = crate::BitWriter<'a, CBSCR_SPEC, O>; +pub type QBE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `QAE` reader - Queue A CBS Enable"] pub type QAE_R = crate::BitReader; #[doc = "Field `QAE` writer - Queue A CBS Enable"] -pub type QAE_W<'a, const O: u8> = crate::BitWriter<'a, CBSCR_SPEC, O>; +pub type QAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Queue B CBS Enable"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 0 - Queue B CBS Enable"] #[inline(always)] #[must_use] - pub fn qbe(&mut self) -> QBE_W<0> { + pub fn qbe(&mut self) -> QBE_W { QBE_W::new(self) } #[doc = "Bit 1 - Queue A CBS Enable"] #[inline(always)] #[must_use] - pub fn qae(&mut self) -> QAE_W<1> { + pub fn qae(&mut self) -> QAE_W { QAE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Credit-Based Shaping Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cbscr](index.html) module"] +#[doc = "Credit-Based Shaping Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CBSCR_SPEC; impl crate::RegisterSpec for CBSCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cbscr::R](R) reader structure"] -impl crate::Readable for CBSCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cbscr::W](W) writer structure"] +#[doc = "`read()` method returns [`cbscr::R`](R) reader structure"] +impl crate::Readable for CBSCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cbscr::W`](W) writer structure"] impl crate::Writable for CBSCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqa.rs b/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqa.rs index de91fb8e..b137fadd 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqa.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqa.rs @@ -1,43 +1,11 @@ #[doc = "Register `CBSISQA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CBSISQA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IS` reader - IdleSlope"] pub type IS_R = crate::FieldReader; #[doc = "Field `IS` writer - IdleSlope"] -pub type IS_W<'a, const O: u8> = crate::FieldWriter<'a, CBSISQA_SPEC, 32, O, u32>; +pub type IS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - IdleSlope"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - IdleSlope"] #[inline(always)] #[must_use] - pub fn is(&mut self) -> IS_W<0> { + pub fn is(&mut self) -> IS_W { IS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Credit-Based Shaping IdleSlope Register for Queue A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cbsisqa](index.html) module"] +#[doc = "Credit-Based Shaping IdleSlope Register for Queue A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsisqa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsisqa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CBSISQA_SPEC; impl crate::RegisterSpec for CBSISQA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cbsisqa::R](R) reader structure"] -impl crate::Readable for CBSISQA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cbsisqa::W](W) writer structure"] +#[doc = "`read()` method returns [`cbsisqa::R`](R) reader structure"] +impl crate::Readable for CBSISQA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cbsisqa::W`](W) writer structure"] impl crate::Writable for CBSISQA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqb.rs b/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqb.rs index 6177e95c..3092b165 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqb.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/cbsisqb.rs @@ -1,43 +1,11 @@ #[doc = "Register `CBSISQB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CBSISQB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IS` reader - IdleSlope"] pub type IS_R = crate::FieldReader; #[doc = "Field `IS` writer - IdleSlope"] -pub type IS_W<'a, const O: u8> = crate::FieldWriter<'a, CBSISQB_SPEC, 32, O, u32>; +pub type IS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - IdleSlope"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - IdleSlope"] #[inline(always)] #[must_use] - pub fn is(&mut self) -> IS_W<0> { + pub fn is(&mut self) -> IS_W { IS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Credit-Based Shaping IdleSlope Register for Queue B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cbsisqb](index.html) module"] +#[doc = "Credit-Based Shaping IdleSlope Register for Queue B\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbsisqb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbsisqb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CBSISQB_SPEC; impl crate::RegisterSpec for CBSISQB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cbsisqb::R](R) reader structure"] -impl crate::Readable for CBSISQB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cbsisqb::W](W) writer structure"] +#[doc = "`read()` method returns [`cbsisqb::R`](R) reader structure"] +impl crate::Readable for CBSISQB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cbsisqb::W`](W) writer structure"] impl crate::Writable for CBSISQB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/cse.rs b/arch/cortex-m/samv71q21-pac/src/gmac/cse.rs index 0c1ed176..83ca9b10 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/cse.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/cse.rs @@ -1,18 +1,5 @@ #[doc = "Register `CSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CSR` reader - Carrier Sense Error"] pub type CSR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CSR_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Carrier Sense Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cse](index.html) module"] +#[doc = "Carrier Sense Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSE_SPEC; impl crate::RegisterSpec for CSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cse::R](R) reader structure"] -impl crate::Readable for CSE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cse::R`](R) reader structure"] +impl crate::Readable for CSE_SPEC {} #[doc = "`reset()` method sets CSE to value 0"] impl crate::Resettable for CSE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/dcfgr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/dcfgr.rs index 203dfb77..5cf0bc9a 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/dcfgr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/dcfgr.rs @@ -1,39 +1,7 @@ #[doc = "Register `DCFGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DCFGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FBLDO` reader - Fixed Burst Length for DMA Data Operations:"] pub type FBLDO_R = crate::FieldReader; #[doc = "Fixed Burst Length for DMA Data Operations:\n\nValue on reset: 0"] @@ -70,59 +38,63 @@ impl FBLDO_R { _ => None, } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "00001: Always use SINGLE AHB bursts"] #[inline(always)] pub fn is_single(&self) -> bool { *self == FBLDOSELECT_A::SINGLE } - #[doc = "Checks if the value of the field is `INCR4`"] + #[doc = "001xx: Attempt to use INCR4 AHB bursts (Default)"] #[inline(always)] pub fn is_incr4(&self) -> bool { *self == FBLDOSELECT_A::INCR4 } - #[doc = "Checks if the value of the field is `INCR8`"] + #[doc = "01xxx: Attempt to use INCR8 AHB bursts"] #[inline(always)] pub fn is_incr8(&self) -> bool { *self == FBLDOSELECT_A::INCR8 } - #[doc = "Checks if the value of the field is `INCR16`"] + #[doc = "1xxxx: Attempt to use INCR16 AHB bursts"] #[inline(always)] pub fn is_incr16(&self) -> bool { *self == FBLDOSELECT_A::INCR16 } } #[doc = "Field `FBLDO` writer - Fixed Burst Length for DMA Data Operations:"] -pub type FBLDO_W<'a, const O: u8> = crate::FieldWriter<'a, DCFGR_SPEC, 5, O, FBLDOSELECT_A>; -impl<'a, const O: u8> FBLDO_W<'a, O> { +pub type FBLDO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O, FBLDOSELECT_A>; +impl<'a, REG, const O: u8> FBLDO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "00001: Always use SINGLE AHB bursts"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(FBLDOSELECT_A::SINGLE) } #[doc = "001xx: Attempt to use INCR4 AHB bursts (Default)"] #[inline(always)] - pub fn incr4(self) -> &'a mut W { + pub fn incr4(self) -> &'a mut crate::W { self.variant(FBLDOSELECT_A::INCR4) } #[doc = "01xxx: Attempt to use INCR8 AHB bursts"] #[inline(always)] - pub fn incr8(self) -> &'a mut W { + pub fn incr8(self) -> &'a mut crate::W { self.variant(FBLDOSELECT_A::INCR8) } #[doc = "1xxxx: Attempt to use INCR16 AHB bursts"] #[inline(always)] - pub fn incr16(self) -> &'a mut W { + pub fn incr16(self) -> &'a mut crate::W { self.variant(FBLDOSELECT_A::INCR16) } } #[doc = "Field `ESMA` reader - Endian Swap Mode Enable for Management Descriptor Accesses"] pub type ESMA_R = crate::BitReader; #[doc = "Field `ESMA` writer - Endian Swap Mode Enable for Management Descriptor Accesses"] -pub type ESMA_W<'a, const O: u8> = crate::BitWriter<'a, DCFGR_SPEC, O>; +pub type ESMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ESPA` reader - Endian Swap Mode Enable for Packet Data Accesses"] pub type ESPA_R = crate::BitReader; #[doc = "Field `ESPA` writer - Endian Swap Mode Enable for Packet Data Accesses"] -pub type ESPA_W<'a, const O: u8> = crate::BitWriter<'a, DCFGR_SPEC, O>; +pub type ESPA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBMS` reader - Receiver Packet Buffer Memory Size Select"] pub type RXBMS_R = crate::FieldReader; #[doc = "Receiver Packet Buffer Memory Size Select\n\nValue on reset: 0"] @@ -159,67 +131,71 @@ impl RXBMS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `EIGHTH`"] + #[doc = "4/8 Kbyte Memory Size"] #[inline(always)] pub fn is_eighth(&self) -> bool { *self == RXBMSSELECT_A::EIGHTH } - #[doc = "Checks if the value of the field is `QUARTER`"] + #[doc = "4/4 Kbytes Memory Size"] #[inline(always)] pub fn is_quarter(&self) -> bool { *self == RXBMSSELECT_A::QUARTER } - #[doc = "Checks if the value of the field is `HALF`"] + #[doc = "4/2 Kbytes Memory Size"] #[inline(always)] pub fn is_half(&self) -> bool { *self == RXBMSSELECT_A::HALF } - #[doc = "Checks if the value of the field is `FULL`"] + #[doc = "4 Kbytes Memory Size"] #[inline(always)] pub fn is_full(&self) -> bool { *self == RXBMSSELECT_A::FULL } } #[doc = "Field `RXBMS` writer - Receiver Packet Buffer Memory Size Select"] -pub type RXBMS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, DCFGR_SPEC, 2, O, RXBMSSELECT_A>; -impl<'a, const O: u8> RXBMS_W<'a, O> { +pub type RXBMS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RXBMSSELECT_A>; +impl<'a, REG, const O: u8> RXBMS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "4/8 Kbyte Memory Size"] #[inline(always)] - pub fn eighth(self) -> &'a mut W { + pub fn eighth(self) -> &'a mut crate::W { self.variant(RXBMSSELECT_A::EIGHTH) } #[doc = "4/4 Kbytes Memory Size"] #[inline(always)] - pub fn quarter(self) -> &'a mut W { + pub fn quarter(self) -> &'a mut crate::W { self.variant(RXBMSSELECT_A::QUARTER) } #[doc = "4/2 Kbytes Memory Size"] #[inline(always)] - pub fn half(self) -> &'a mut W { + pub fn half(self) -> &'a mut crate::W { self.variant(RXBMSSELECT_A::HALF) } #[doc = "4 Kbytes Memory Size"] #[inline(always)] - pub fn full(self) -> &'a mut W { + pub fn full(self) -> &'a mut crate::W { self.variant(RXBMSSELECT_A::FULL) } } #[doc = "Field `TXPBMS` reader - Transmitter Packet Buffer Memory Size Select"] pub type TXPBMS_R = crate::BitReader; #[doc = "Field `TXPBMS` writer - Transmitter Packet Buffer Memory Size Select"] -pub type TXPBMS_W<'a, const O: u8> = crate::BitWriter<'a, DCFGR_SPEC, O>; +pub type TXPBMS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXCOEN` reader - Transmitter Checksum Generation Offload Enable"] pub type TXCOEN_R = crate::BitReader; #[doc = "Field `TXCOEN` writer - Transmitter Checksum Generation Offload Enable"] -pub type TXCOEN_W<'a, const O: u8> = crate::BitWriter<'a, DCFGR_SPEC, O>; +pub type TXCOEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRBS` reader - DMA Receive Buffer Size"] pub type DRBS_R = crate::FieldReader; #[doc = "Field `DRBS` writer - DMA Receive Buffer Size"] -pub type DRBS_W<'a, const O: u8> = crate::FieldWriter<'a, DCFGR_SPEC, 8, O>; +pub type DRBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DDRP` reader - DMA Discard Receive Packets"] pub type DDRP_R = crate::BitReader; #[doc = "Field `DDRP` writer - DMA Discard Receive Packets"] -pub type DDRP_W<'a, const O: u8> = crate::BitWriter<'a, DCFGR_SPEC, O>; +pub type DDRP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:4 - Fixed Burst Length for DMA Data Operations:"] #[inline(always)] @@ -266,70 +242,67 @@ impl W { #[doc = "Bits 0:4 - Fixed Burst Length for DMA Data Operations:"] #[inline(always)] #[must_use] - pub fn fbldo(&mut self) -> FBLDO_W<0> { + pub fn fbldo(&mut self) -> FBLDO_W { FBLDO_W::new(self) } #[doc = "Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses"] #[inline(always)] #[must_use] - pub fn esma(&mut self) -> ESMA_W<6> { + pub fn esma(&mut self) -> ESMA_W { ESMA_W::new(self) } #[doc = "Bit 7 - Endian Swap Mode Enable for Packet Data Accesses"] #[inline(always)] #[must_use] - pub fn espa(&mut self) -> ESPA_W<7> { + pub fn espa(&mut self) -> ESPA_W { ESPA_W::new(self) } #[doc = "Bits 8:9 - Receiver Packet Buffer Memory Size Select"] #[inline(always)] #[must_use] - pub fn rxbms(&mut self) -> RXBMS_W<8> { + pub fn rxbms(&mut self) -> RXBMS_W { RXBMS_W::new(self) } #[doc = "Bit 10 - Transmitter Packet Buffer Memory Size Select"] #[inline(always)] #[must_use] - pub fn txpbms(&mut self) -> TXPBMS_W<10> { + pub fn txpbms(&mut self) -> TXPBMS_W { TXPBMS_W::new(self) } #[doc = "Bit 11 - Transmitter Checksum Generation Offload Enable"] #[inline(always)] #[must_use] - pub fn txcoen(&mut self) -> TXCOEN_W<11> { + pub fn txcoen(&mut self) -> TXCOEN_W { TXCOEN_W::new(self) } #[doc = "Bits 16:23 - DMA Receive Buffer Size"] #[inline(always)] #[must_use] - pub fn drbs(&mut self) -> DRBS_W<16> { + pub fn drbs(&mut self) -> DRBS_W { DRBS_W::new(self) } #[doc = "Bit 24 - DMA Discard Receive Packets"] #[inline(always)] #[must_use] - pub fn ddrp(&mut self) -> DDRP_W<24> { + pub fn ddrp(&mut self) -> DDRP_W { DDRP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfgr](index.html) module"] +#[doc = "DMA Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DCFGR_SPEC; impl crate::RegisterSpec for DCFGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dcfgr::R](R) reader structure"] -impl crate::Readable for DCFGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dcfgr::W](W) writer structure"] +#[doc = "`read()` method returns [`dcfgr::R`](R) reader structure"] +impl crate::Readable for DCFGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcfgr::W`](W) writer structure"] impl crate::Writable for DCFGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/dtf.rs b/arch/cortex-m/samv71q21-pac/src/gmac/dtf.rs index 89cfb35e..dc707460 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/dtf.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/dtf.rs @@ -1,18 +1,5 @@ #[doc = "Register `DTF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DEFT` reader - Deferred Transmission"] pub type DEFT_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { DEFT_R::new(self.bits & 0x0003_ffff) } } -#[doc = "Deferred Transmission Frames Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtf](index.html) module"] +#[doc = "Deferred Transmission Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTF_SPEC; impl crate::RegisterSpec for DTF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dtf::R](R) reader structure"] -impl crate::Readable for DTF_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dtf::R`](R) reader structure"] +impl crate::Readable for DTF_SPEC {} #[doc = "`reset()` method sets DTF to value 0"] impl crate::Resettable for DTF_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ec.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ec.rs index a09bc759..f928d8ba 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ec.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ec.rs @@ -1,18 +1,5 @@ #[doc = "Register `EC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `XCOL` reader - Excessive Collisions"] pub type XCOL_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { XCOL_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Excessive Collisions Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ec](index.html) module"] +#[doc = "Excessive Collisions Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ec::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EC_SPEC; impl crate::RegisterSpec for EC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ec::R](R) reader structure"] -impl crate::Readable for EC_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ec::R`](R) reader structure"] +impl crate::Readable for EC_SPEC {} #[doc = "`reset()` method sets EC to value 0"] impl crate::Resettable for EC_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/efrn.rs b/arch/cortex-m/samv71q21-pac/src/gmac/efrn.rs index d218431b..9e59c8a1 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/efrn.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/efrn.rs @@ -1,18 +1,5 @@ #[doc = "Register `EFRN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits & 0x3fff_ffff) } } -#[doc = "PTP Event Frame Received Nanoseconds Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [efrn](index.html) module"] +#[doc = "PTP Event Frame Received Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efrn::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EFRN_SPEC; impl crate::RegisterSpec for EFRN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [efrn::R](R) reader structure"] -impl crate::Readable for EFRN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`efrn::R`](R) reader structure"] +impl crate::Readable for EFRN_SPEC {} #[doc = "`reset()` method sets EFRN to value 0"] impl crate::Resettable for EFRN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/efrsh.rs b/arch/cortex-m/samv71q21-pac/src/gmac/efrsh.rs index 5e284792..769d3504 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/efrsh.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/efrsh.rs @@ -1,18 +1,5 @@ #[doc = "Register `EFRSH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new((self.bits & 0xffff) as u16) } } -#[doc = "PTP Event Frame Received Seconds High Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [efrsh](index.html) module"] +#[doc = "PTP Event Frame Received Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efrsh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EFRSH_SPEC; impl crate::RegisterSpec for EFRSH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [efrsh::R](R) reader structure"] -impl crate::Readable for EFRSH_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`efrsh::R`](R) reader structure"] +impl crate::Readable for EFRSH_SPEC {} #[doc = "`reset()` method sets EFRSH to value 0"] impl crate::Resettable for EFRSH_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/efrsl.rs b/arch/cortex-m/samv71q21-pac/src/gmac/efrsl.rs index c675d023..934aacdc 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/efrsl.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/efrsl.rs @@ -1,18 +1,5 @@ #[doc = "Register `EFRSL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits) } } -#[doc = "PTP Event Frame Received Seconds Low Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [efrsl](index.html) module"] +#[doc = "PTP Event Frame Received Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`efrsl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EFRSL_SPEC; impl crate::RegisterSpec for EFRSL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [efrsl::R](R) reader structure"] -impl crate::Readable for EFRSL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`efrsl::R`](R) reader structure"] +impl crate::Readable for EFRSL_SPEC {} #[doc = "`reset()` method sets EFRSL to value 0"] impl crate::Resettable for EFRSL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/eftn.rs b/arch/cortex-m/samv71q21-pac/src/gmac/eftn.rs index 738ed223..08dfb1a9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/eftn.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/eftn.rs @@ -1,18 +1,5 @@ #[doc = "Register `EFTN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits & 0x3fff_ffff) } } -#[doc = "PTP Event Frame Transmitted Nanoseconds Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eftn](index.html) module"] +#[doc = "PTP Event Frame Transmitted Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eftn::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EFTN_SPEC; impl crate::RegisterSpec for EFTN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eftn::R](R) reader structure"] -impl crate::Readable for EFTN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`eftn::R`](R) reader structure"] +impl crate::Readable for EFTN_SPEC {} #[doc = "`reset()` method sets EFTN to value 0"] impl crate::Resettable for EFTN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/eftsh.rs b/arch/cortex-m/samv71q21-pac/src/gmac/eftsh.rs index 4ee7f3b6..079b1f0c 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/eftsh.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/eftsh.rs @@ -1,18 +1,5 @@ #[doc = "Register `EFTSH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new((self.bits & 0xffff) as u16) } } -#[doc = "PTP Event Frame Transmitted Seconds High Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eftsh](index.html) module"] +#[doc = "PTP Event Frame Transmitted Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eftsh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EFTSH_SPEC; impl crate::RegisterSpec for EFTSH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eftsh::R](R) reader structure"] -impl crate::Readable for EFTSH_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`eftsh::R`](R) reader structure"] +impl crate::Readable for EFTSH_SPEC {} #[doc = "`reset()` method sets EFTSH to value 0"] impl crate::Resettable for EFTSH_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/eftsl.rs b/arch/cortex-m/samv71q21-pac/src/gmac/eftsl.rs index 374afe02..991608e9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/eftsl.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/eftsl.rs @@ -1,18 +1,5 @@ #[doc = "Register `EFTSL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits) } } -#[doc = "PTP Event Frame Transmitted Seconds Low Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [eftsl](index.html) module"] +#[doc = "PTP Event Frame Transmitted Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`eftsl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EFTSL_SPEC; impl crate::RegisterSpec for EFTSL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [eftsl::R](R) reader structure"] -impl crate::Readable for EFTSL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`eftsl::R`](R) reader structure"] +impl crate::Readable for EFTSL_SPEC {} #[doc = "`reset()` method sets EFTSL to value 0"] impl crate::Resettable for EFTSL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/fcse.rs b/arch/cortex-m/samv71q21-pac/src/gmac/fcse.rs index 448ee12a..76c527f1 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/fcse.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/fcse.rs @@ -1,18 +1,5 @@ #[doc = "Register `FCSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FCKR` reader - Frame Check Sequence Errors"] pub type FCKR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { FCKR_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Frame Check Sequence Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcse](index.html) module"] +#[doc = "Frame Check Sequence Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FCSE_SPEC; impl crate::RegisterSpec for FCSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fcse::R](R) reader structure"] -impl crate::Readable for FCSE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fcse::R`](R) reader structure"] +impl crate::Readable for FCSE_SPEC {} #[doc = "`reset()` method sets FCSE to value 0"] impl crate::Resettable for FCSE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/fr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/fr.rs index a06f6101..daa25ec6 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/fr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/fr.rs @@ -1,18 +1,5 @@ #[doc = "Register `FR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FRX` reader - Frames Received without Error"] pub type FRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { FRX_R::new(self.bits) } } -#[doc = "Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fr](index.html) module"] +#[doc = "Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FR_SPEC; impl crate::RegisterSpec for FR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fr::R](R) reader structure"] -impl crate::Readable for FR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fr::R`](R) reader structure"] +impl crate::Readable for FR_SPEC {} #[doc = "`reset()` method sets FR to value 0"] impl crate::Resettable for FR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ft.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ft.rs index e6da8c32..434d8d81 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ft.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ft.rs @@ -1,18 +1,5 @@ #[doc = "Register `FT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FTX` reader - Frames Transmitted without Error"] pub type FTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { FTX_R::new(self.bits) } } -#[doc = "Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ft](index.html) module"] +#[doc = "Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ft::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FT_SPEC; impl crate::RegisterSpec for FT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ft::R](R) reader structure"] -impl crate::Readable for FT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ft::R`](R) reader structure"] +impl crate::Readable for FT_SPEC {} #[doc = "`reset()` method sets FT to value 0"] impl crate::Resettable for FT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa.rs index eebb165a..99a4cbc6 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa.rs @@ -6,11 +6,13 @@ pub struct GMAC_SA { #[doc = "0x04 - Specific Address 1 Top Register"] pub sat: SAT, } -#[doc = "SAB (rw) register accessor: an alias for `Reg`"] +#[doc = "SAB (rw) register accessor: Specific Address 1 Bottom Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sab::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sab::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sab`] +module"] pub type SAB = crate::Reg; #[doc = "Specific Address 1 Bottom Register"] pub mod sab; -#[doc = "SAT (rw) register accessor: an alias for `Reg`"] +#[doc = "SAT (rw) register accessor: Specific Address 1 Top Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sat`] +module"] pub type SAT = crate::Reg; #[doc = "Specific Address 1 Top Register"] pub mod sat; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sab.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sab.rs index 0b84587e..ae67a059 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sab.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sab.rs @@ -1,43 +1,11 @@ #[doc = "Register `SAB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SAB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Specific Address 1"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Specific Address 1"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, SAB_SPEC, 32, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Specific Address 1"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Specific Address 1"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Specific Address 1 Bottom Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sab](index.html) module"] +#[doc = "Specific Address 1 Bottom Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sab::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sab::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SAB_SPEC; impl crate::RegisterSpec for SAB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sab::R](R) reader structure"] -impl crate::Readable for SAB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sab::W](W) writer structure"] +#[doc = "`read()` method returns [`sab::R`](R) reader structure"] +impl crate::Readable for SAB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sab::W`](W) writer structure"] impl crate::Writable for SAB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sat.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sat.rs index ff39e6a4..3392ab58 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sat.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_sa/sat.rs @@ -1,43 +1,11 @@ #[doc = "Register `SAT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SAT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Specific Address 1"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Specific Address 1"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, SAT_SPEC, 16, O, u16>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Specific Address 1"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Specific Address 1"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Specific Address 1 Top Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sat](index.html) module"] +#[doc = "Specific Address 1 Top Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SAT_SPEC; impl crate::RegisterSpec for SAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sat::R](R) reader structure"] -impl crate::Readable for SAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sat::W](W) writer structure"] +#[doc = "`read()` method returns [`sat::R`](R) reader structure"] +impl crate::Readable for SAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sat::W`](W) writer structure"] impl crate::Writable for SAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw.rs index 20bb943e..0f2f3af5 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw.rs @@ -6,11 +6,13 @@ pub struct GMAC_ST2CW { #[doc = "0x04 - Screening Type 2 Compare Word 1 Register"] pub st2cw1: ST2CW1, } -#[doc = "ST2CW0 (rw) register accessor: an alias for `Reg`"] +#[doc = "ST2CW0 (rw) register accessor: Screening Type 2 Compare Word 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2cw0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2cw0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`st2cw0`] +module"] pub type ST2CW0 = crate::Reg; #[doc = "Screening Type 2 Compare Word 0 Register"] pub mod st2cw0; -#[doc = "ST2CW1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ST2CW1 (rw) register accessor: Screening Type 2 Compare Word 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2cw1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2cw1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`st2cw1`] +module"] pub type ST2CW1 = crate::Reg; #[doc = "Screening Type 2 Compare Word 1 Register"] pub mod st2cw1; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw0.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw0.rs index c37f803d..ed89b39d 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw0.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw0.rs @@ -1,47 +1,15 @@ #[doc = "Register `ST2CW0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ST2CW0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MASKVAL` reader - Mask Value"] pub type MASKVAL_R = crate::FieldReader; #[doc = "Field `MASKVAL` writer - Mask Value"] -pub type MASKVAL_W<'a, const O: u8> = crate::FieldWriter<'a, ST2CW0_SPEC, 16, O, u16>; +pub type MASKVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `COMPVAL` reader - Compare Value"] pub type COMPVAL_R = crate::FieldReader; #[doc = "Field `COMPVAL` writer - Compare Value"] -pub type COMPVAL_W<'a, const O: u8> = crate::FieldWriter<'a, ST2CW0_SPEC, 16, O, u16>; +pub type COMPVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Mask Value"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Mask Value"] #[inline(always)] #[must_use] - pub fn maskval(&mut self) -> MASKVAL_W<0> { + pub fn maskval(&mut self) -> MASKVAL_W { MASKVAL_W::new(self) } #[doc = "Bits 16:31 - Compare Value"] #[inline(always)] #[must_use] - pub fn compval(&mut self) -> COMPVAL_W<16> { + pub fn compval(&mut self) -> COMPVAL_W { COMPVAL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Screening Type 2 Compare Word 0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [st2cw0](index.html) module"] +#[doc = "Screening Type 2 Compare Word 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2cw0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2cw0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ST2CW0_SPEC; impl crate::RegisterSpec for ST2CW0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [st2cw0::R](R) reader structure"] -impl crate::Readable for ST2CW0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [st2cw0::W](W) writer structure"] +#[doc = "`read()` method returns [`st2cw0::R`](R) reader structure"] +impl crate::Readable for ST2CW0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`st2cw0::W`](W) writer structure"] impl crate::Writable for ST2CW0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw1.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw1.rs index 351a992a..27c59d99 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw1.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gmac_st2cw/st2cw1.rs @@ -1,43 +1,11 @@ #[doc = "Register `ST2CW1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ST2CW1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OFFSVAL` reader - Offset Value in Bytes"] pub type OFFSVAL_R = crate::FieldReader; #[doc = "Field `OFFSVAL` writer - Offset Value in Bytes"] -pub type OFFSVAL_W<'a, const O: u8> = crate::FieldWriter<'a, ST2CW1_SPEC, 7, O>; +pub type OFFSVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `OFFSSTRT` reader - Ethernet Frame Offset Start"] pub type OFFSSTRT_R = crate::FieldReader; #[doc = "Ethernet Frame Offset Start\n\nValue on reset: 0"] @@ -74,49 +42,52 @@ impl OFFSSTRT_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `FRAMESTART`"] + #[doc = "Offset from the start of the frame"] #[inline(always)] pub fn is_framestart(&self) -> bool { *self == OFFSSTRTSELECT_A::FRAMESTART } - #[doc = "Checks if the value of the field is `ETHERTYPE`"] + #[doc = "Offset from the byte after the EtherType field"] #[inline(always)] pub fn is_ethertype(&self) -> bool { *self == OFFSSTRTSELECT_A::ETHERTYPE } - #[doc = "Checks if the value of the field is `IP`"] + #[doc = "Offset from the byte after the IP header field"] #[inline(always)] pub fn is_ip(&self) -> bool { *self == OFFSSTRTSELECT_A::IP } - #[doc = "Checks if the value of the field is `TCP_UDP`"] + #[doc = "Offset from the byte after the TCP/UDP header field"] #[inline(always)] pub fn is_tcp_udp(&self) -> bool { *self == OFFSSTRTSELECT_A::TCP_UDP } } #[doc = "Field `OFFSSTRT` writer - Ethernet Frame Offset Start"] -pub type OFFSSTRT_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, ST2CW1_SPEC, 2, O, OFFSSTRTSELECT_A>; -impl<'a, const O: u8> OFFSSTRT_W<'a, O> { +pub type OFFSSTRT_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, OFFSSTRTSELECT_A>; +impl<'a, REG, const O: u8> OFFSSTRT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Offset from the start of the frame"] #[inline(always)] - pub fn framestart(self) -> &'a mut W { + pub fn framestart(self) -> &'a mut crate::W { self.variant(OFFSSTRTSELECT_A::FRAMESTART) } #[doc = "Offset from the byte after the EtherType field"] #[inline(always)] - pub fn ethertype(self) -> &'a mut W { + pub fn ethertype(self) -> &'a mut crate::W { self.variant(OFFSSTRTSELECT_A::ETHERTYPE) } #[doc = "Offset from the byte after the IP header field"] #[inline(always)] - pub fn ip(self) -> &'a mut W { + pub fn ip(self) -> &'a mut crate::W { self.variant(OFFSSTRTSELECT_A::IP) } #[doc = "Offset from the byte after the TCP/UDP header field"] #[inline(always)] - pub fn tcp_udp(self) -> &'a mut W { + pub fn tcp_udp(self) -> &'a mut crate::W { self.variant(OFFSSTRTSELECT_A::TCP_UDP) } } @@ -136,34 +107,31 @@ impl W { #[doc = "Bits 0:6 - Offset Value in Bytes"] #[inline(always)] #[must_use] - pub fn offsval(&mut self) -> OFFSVAL_W<0> { + pub fn offsval(&mut self) -> OFFSVAL_W { OFFSVAL_W::new(self) } #[doc = "Bits 7:8 - Ethernet Frame Offset Start"] #[inline(always)] #[must_use] - pub fn offsstrt(&mut self) -> OFFSSTRT_W<7> { + pub fn offsstrt(&mut self) -> OFFSSTRT_W { OFFSSTRT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Screening Type 2 Compare Word 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [st2cw1](index.html) module"] +#[doc = "Screening Type 2 Compare Word 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2cw1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2cw1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ST2CW1_SPEC; impl crate::RegisterSpec for ST2CW1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [st2cw1::R](R) reader structure"] -impl crate::Readable for ST2CW1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [st2cw1::W](W) writer structure"] +#[doc = "`read()` method returns [`st2cw1::R`](R) reader structure"] +impl crate::Readable for ST2CW1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`st2cw1::W`](W) writer structure"] impl crate::Writable for ST2CW1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/gtbft1518.rs b/arch/cortex-m/samv71q21-pac/src/gmac/gtbft1518.rs index dbd029a4..679fa60c 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/gtbft1518.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/gtbft1518.rs @@ -1,18 +1,5 @@ #[doc = "Register `GTBFT1518` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - Greater than 1518 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "Greater Than 1518 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gtbft1518](index.html) module"] +#[doc = "Greater Than 1518 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtbft1518::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GTBFT1518_SPEC; impl crate::RegisterSpec for GTBFT1518_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gtbft1518::R](R) reader structure"] -impl crate::Readable for GTBFT1518_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gtbft1518::R`](R) reader structure"] +impl crate::Readable for GTBFT1518_SPEC {} #[doc = "`reset()` method sets GTBFT1518 to value 0"] impl crate::Resettable for GTBFT1518_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/hrb.rs b/arch/cortex-m/samv71q21-pac/src/gmac/hrb.rs index 00540fc2..946f8288 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/hrb.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/hrb.rs @@ -1,43 +1,11 @@ #[doc = "Register `HRB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HRB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Hash Address"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Hash Address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, HRB_SPEC, 32, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Hash Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Hash Address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Hash Register Bottom\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hrb](index.html) module"] +#[doc = "Hash Register Bottom\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HRB_SPEC; impl crate::RegisterSpec for HRB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hrb::R](R) reader structure"] -impl crate::Readable for HRB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hrb::W](W) writer structure"] +#[doc = "`read()` method returns [`hrb::R`](R) reader structure"] +impl crate::Readable for HRB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hrb::W`](W) writer structure"] impl crate::Writable for HRB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/hrt.rs b/arch/cortex-m/samv71q21-pac/src/gmac/hrt.rs index 440b72a1..813d1f56 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/hrt.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/hrt.rs @@ -1,43 +1,11 @@ #[doc = "Register `HRT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HRT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Hash Address"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Hash Address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, HRT_SPEC, 32, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Hash Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Hash Address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Hash Register Top\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hrt](index.html) module"] +#[doc = "Hash Register Top\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hrt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hrt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HRT_SPEC; impl crate::RegisterSpec for HRT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hrt::R](R) reader structure"] -impl crate::Readable for HRT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hrt::W](W) writer structure"] +#[doc = "`read()` method returns [`hrt::R`](R) reader structure"] +impl crate::Readable for HRT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hrt::W`](W) writer structure"] impl crate::Writable for HRT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/idr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/idr.rs index 14f7c18f..aacab375 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/idr.rs @@ -1,248 +1,228 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MFS` writer - Management Frame Sent"] -pub type MFS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCOMP` writer - Receive Complete"] -pub type RCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUBR` writer - RX Used Bit Read"] -pub type RXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUBR` writer - TX Used Bit Read"] -pub type TXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TUR` writer - Transmit Underrun"] -pub type TUR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLEX` writer - Retry Limit Exceeded or Late Collision"] -pub type RLEX_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RLEX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"] -pub type TFC_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOMP` writer - Transmit Complete"] -pub type TCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROVR` writer - Receive Overrun"] -pub type ROVR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ROVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFNZ` writer - Pause Frame with Non-zero Pause Quantum Received"] -pub type PFNZ_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PFNZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTZ` writer - Pause Time Zero"] -pub type PTZ_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PTZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFTR` writer - Pause Frame Transmitted"] -pub type PFTR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PFTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXINT` writer - External Interrupt"] -pub type EXINT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EXINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRQFR` writer - PTP Delay Request Frame Received"] -pub type DRQFR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DRQFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SFR` writer - PTP Sync Frame Received"] -pub type SFR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRQFT` writer - PTP Delay Request Frame Transmitted"] -pub type DRQFT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DRQFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SFT` writer - PTP Sync Frame Transmitted"] -pub type SFT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRQFR` writer - PDelay Request Frame Received"] -pub type PDRQFR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PDRQFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRSFR` writer - PDelay Response Frame Received"] -pub type PDRSFR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PDRSFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRQFT` writer - PDelay Request Frame Transmitted"] -pub type PDRQFT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PDRQFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRSFT` writer - PDelay Response Frame Transmitted"] -pub type PDRSFT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PDRSFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRI` writer - TSU Seconds Register Increment"] -pub type SRI_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SRI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXLPISBC` writer - Enable RX LPI Indication"] -pub type RXLPISBC_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXLPISBC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WOL` writer - Wake On LAN"] -pub type WOL_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type WOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSUTIMCOMP` writer - TSU Timer Comparison"] -pub type TSUTIMCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TSUTIMCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Management Frame Sent"] #[inline(always)] #[must_use] - pub fn mfs(&mut self) -> MFS_W<0> { + pub fn mfs(&mut self) -> MFS_W { MFS_W::new(self) } #[doc = "Bit 1 - Receive Complete"] #[inline(always)] #[must_use] - pub fn rcomp(&mut self) -> RCOMP_W<1> { + pub fn rcomp(&mut self) -> RCOMP_W { RCOMP_W::new(self) } #[doc = "Bit 2 - RX Used Bit Read"] #[inline(always)] #[must_use] - pub fn rxubr(&mut self) -> RXUBR_W<2> { + pub fn rxubr(&mut self) -> RXUBR_W { RXUBR_W::new(self) } #[doc = "Bit 3 - TX Used Bit Read"] #[inline(always)] #[must_use] - pub fn txubr(&mut self) -> TXUBR_W<3> { + pub fn txubr(&mut self) -> TXUBR_W { TXUBR_W::new(self) } #[doc = "Bit 4 - Transmit Underrun"] #[inline(always)] #[must_use] - pub fn tur(&mut self) -> TUR_W<4> { + pub fn tur(&mut self) -> TUR_W { TUR_W::new(self) } #[doc = "Bit 5 - Retry Limit Exceeded or Late Collision"] #[inline(always)] #[must_use] - pub fn rlex(&mut self) -> RLEX_W<5> { + pub fn rlex(&mut self) -> RLEX_W { RLEX_W::new(self) } #[doc = "Bit 6 - Transmit Frame Corruption Due to AHB Error"] #[inline(always)] #[must_use] - pub fn tfc(&mut self) -> TFC_W<6> { + pub fn tfc(&mut self) -> TFC_W { TFC_W::new(self) } #[doc = "Bit 7 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn tcomp(&mut self) -> TCOMP_W<7> { + pub fn tcomp(&mut self) -> TCOMP_W { TCOMP_W::new(self) } #[doc = "Bit 10 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rovr(&mut self) -> ROVR_W<10> { + pub fn rovr(&mut self) -> ROVR_W { ROVR_W::new(self) } #[doc = "Bit 11 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<11> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Bit 12 - Pause Frame with Non-zero Pause Quantum Received"] #[inline(always)] #[must_use] - pub fn pfnz(&mut self) -> PFNZ_W<12> { + pub fn pfnz(&mut self) -> PFNZ_W { PFNZ_W::new(self) } #[doc = "Bit 13 - Pause Time Zero"] #[inline(always)] #[must_use] - pub fn ptz(&mut self) -> PTZ_W<13> { + pub fn ptz(&mut self) -> PTZ_W { PTZ_W::new(self) } #[doc = "Bit 14 - Pause Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pftr(&mut self) -> PFTR_W<14> { + pub fn pftr(&mut self) -> PFTR_W { PFTR_W::new(self) } #[doc = "Bit 15 - External Interrupt"] #[inline(always)] #[must_use] - pub fn exint(&mut self) -> EXINT_W<15> { + pub fn exint(&mut self) -> EXINT_W { EXINT_W::new(self) } #[doc = "Bit 18 - PTP Delay Request Frame Received"] #[inline(always)] #[must_use] - pub fn drqfr(&mut self) -> DRQFR_W<18> { + pub fn drqfr(&mut self) -> DRQFR_W { DRQFR_W::new(self) } #[doc = "Bit 19 - PTP Sync Frame Received"] #[inline(always)] #[must_use] - pub fn sfr(&mut self) -> SFR_W<19> { + pub fn sfr(&mut self) -> SFR_W { SFR_W::new(self) } #[doc = "Bit 20 - PTP Delay Request Frame Transmitted"] #[inline(always)] #[must_use] - pub fn drqft(&mut self) -> DRQFT_W<20> { + pub fn drqft(&mut self) -> DRQFT_W { DRQFT_W::new(self) } #[doc = "Bit 21 - PTP Sync Frame Transmitted"] #[inline(always)] #[must_use] - pub fn sft(&mut self) -> SFT_W<21> { + pub fn sft(&mut self) -> SFT_W { SFT_W::new(self) } #[doc = "Bit 22 - PDelay Request Frame Received"] #[inline(always)] #[must_use] - pub fn pdrqfr(&mut self) -> PDRQFR_W<22> { + pub fn pdrqfr(&mut self) -> PDRQFR_W { PDRQFR_W::new(self) } #[doc = "Bit 23 - PDelay Response Frame Received"] #[inline(always)] #[must_use] - pub fn pdrsfr(&mut self) -> PDRSFR_W<23> { + pub fn pdrsfr(&mut self) -> PDRSFR_W { PDRSFR_W::new(self) } #[doc = "Bit 24 - PDelay Request Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pdrqft(&mut self) -> PDRQFT_W<24> { + pub fn pdrqft(&mut self) -> PDRQFT_W { PDRQFT_W::new(self) } #[doc = "Bit 25 - PDelay Response Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pdrsft(&mut self) -> PDRSFT_W<25> { + pub fn pdrsft(&mut self) -> PDRSFT_W { PDRSFT_W::new(self) } #[doc = "Bit 26 - TSU Seconds Register Increment"] #[inline(always)] #[must_use] - pub fn sri(&mut self) -> SRI_W<26> { + pub fn sri(&mut self) -> SRI_W { SRI_W::new(self) } #[doc = "Bit 27 - Enable RX LPI Indication"] #[inline(always)] #[must_use] - pub fn rxlpisbc(&mut self) -> RXLPISBC_W<27> { + pub fn rxlpisbc(&mut self) -> RXLPISBC_W { RXLPISBC_W::new(self) } #[doc = "Bit 28 - Wake On LAN"] #[inline(always)] #[must_use] - pub fn wol(&mut self) -> WOL_W<28> { + pub fn wol(&mut self) -> WOL_W { WOL_W::new(self) } #[doc = "Bit 29 - TSU Timer Comparison"] #[inline(always)] #[must_use] - pub fn tsutimcomp(&mut self) -> TSUTIMCOMP_W<29> { + pub fn tsutimcomp(&mut self) -> TSUTIMCOMP_W { TSUTIMCOMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/idrpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/idrpq.rs index fcb6311f..ebd7fba0 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/idrpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/idrpq.rs @@ -1,96 +1,76 @@ #[doc = "Register `IDRPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RCOMP` writer - Receive Complete"] -pub type RCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type RCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUBR` writer - RX Used Bit Read"] -pub type RXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type RXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLEX` writer - Retry Limit Exceeded or Late Collision"] -pub type RLEX_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type RLEX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"] -pub type TFC_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type TFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOMP` writer - Transmit Complete"] -pub type TCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type TCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROVR` writer - Receive Overrun"] -pub type ROVR_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type ROVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, IDRPQ_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 1 - Receive Complete"] #[inline(always)] #[must_use] - pub fn rcomp(&mut self) -> RCOMP_W<1> { + pub fn rcomp(&mut self) -> RCOMP_W { RCOMP_W::new(self) } #[doc = "Bit 2 - RX Used Bit Read"] #[inline(always)] #[must_use] - pub fn rxubr(&mut self) -> RXUBR_W<2> { + pub fn rxubr(&mut self) -> RXUBR_W { RXUBR_W::new(self) } #[doc = "Bit 5 - Retry Limit Exceeded or Late Collision"] #[inline(always)] #[must_use] - pub fn rlex(&mut self) -> RLEX_W<5> { + pub fn rlex(&mut self) -> RLEX_W { RLEX_W::new(self) } #[doc = "Bit 6 - Transmit Frame Corruption Due to AHB Error"] #[inline(always)] #[must_use] - pub fn tfc(&mut self) -> TFC_W<6> { + pub fn tfc(&mut self) -> TFC_W { TFC_W::new(self) } #[doc = "Bit 7 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn tcomp(&mut self) -> TCOMP_W<7> { + pub fn tcomp(&mut self) -> TCOMP_W { TCOMP_W::new(self) } #[doc = "Bit 10 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rovr(&mut self) -> ROVR_W<10> { + pub fn rovr(&mut self) -> ROVR_W { ROVR_W::new(self) } #[doc = "Bit 11 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<11> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register Priority Queue (1..5)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idrpq](index.html) module"] +#[doc = "Interrupt Disable Register Priority Queue (1..5)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idrpq::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDRPQ_SPEC; impl crate::RegisterSpec for IDRPQ_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idrpq::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idrpq::W`](W) writer structure"] impl crate::Writable for IDRPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ier.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ier.rs index b777bbe9..afd33ef7 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ier.rs @@ -1,248 +1,228 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MFS` writer - Management Frame Sent"] -pub type MFS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCOMP` writer - Receive Complete"] -pub type RCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUBR` writer - RX Used Bit Read"] -pub type RXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUBR` writer - TX Used Bit Read"] -pub type TXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TUR` writer - Transmit Underrun"] -pub type TUR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLEX` writer - Retry Limit Exceeded or Late Collision"] -pub type RLEX_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RLEX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"] -pub type TFC_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOMP` writer - Transmit Complete"] -pub type TCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROVR` writer - Receive Overrun"] -pub type ROVR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ROVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFNZ` writer - Pause Frame with Non-zero Pause Quantum Received"] -pub type PFNZ_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PFNZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTZ` writer - Pause Time Zero"] -pub type PTZ_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PTZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFTR` writer - Pause Frame Transmitted"] -pub type PFTR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PFTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXINT` writer - External Interrupt"] -pub type EXINT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EXINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRQFR` writer - PTP Delay Request Frame Received"] -pub type DRQFR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DRQFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SFR` writer - PTP Sync Frame Received"] -pub type SFR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRQFT` writer - PTP Delay Request Frame Transmitted"] -pub type DRQFT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DRQFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SFT` writer - PTP Sync Frame Transmitted"] -pub type SFT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRQFR` writer - PDelay Request Frame Received"] -pub type PDRQFR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PDRQFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRSFR` writer - PDelay Response Frame Received"] -pub type PDRSFR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PDRSFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRQFT` writer - PDelay Request Frame Transmitted"] -pub type PDRQFT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PDRQFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRSFT` writer - PDelay Response Frame Transmitted"] -pub type PDRSFT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PDRSFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRI` writer - TSU Seconds Register Increment"] -pub type SRI_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SRI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXLPISBC` writer - Enable RX LPI Indication"] -pub type RXLPISBC_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXLPISBC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WOL` writer - Wake On LAN"] -pub type WOL_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type WOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSUTIMCOMP` writer - TSU Timer Comparison"] -pub type TSUTIMCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TSUTIMCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Management Frame Sent"] #[inline(always)] #[must_use] - pub fn mfs(&mut self) -> MFS_W<0> { + pub fn mfs(&mut self) -> MFS_W { MFS_W::new(self) } #[doc = "Bit 1 - Receive Complete"] #[inline(always)] #[must_use] - pub fn rcomp(&mut self) -> RCOMP_W<1> { + pub fn rcomp(&mut self) -> RCOMP_W { RCOMP_W::new(self) } #[doc = "Bit 2 - RX Used Bit Read"] #[inline(always)] #[must_use] - pub fn rxubr(&mut self) -> RXUBR_W<2> { + pub fn rxubr(&mut self) -> RXUBR_W { RXUBR_W::new(self) } #[doc = "Bit 3 - TX Used Bit Read"] #[inline(always)] #[must_use] - pub fn txubr(&mut self) -> TXUBR_W<3> { + pub fn txubr(&mut self) -> TXUBR_W { TXUBR_W::new(self) } #[doc = "Bit 4 - Transmit Underrun"] #[inline(always)] #[must_use] - pub fn tur(&mut self) -> TUR_W<4> { + pub fn tur(&mut self) -> TUR_W { TUR_W::new(self) } #[doc = "Bit 5 - Retry Limit Exceeded or Late Collision"] #[inline(always)] #[must_use] - pub fn rlex(&mut self) -> RLEX_W<5> { + pub fn rlex(&mut self) -> RLEX_W { RLEX_W::new(self) } #[doc = "Bit 6 - Transmit Frame Corruption Due to AHB Error"] #[inline(always)] #[must_use] - pub fn tfc(&mut self) -> TFC_W<6> { + pub fn tfc(&mut self) -> TFC_W { TFC_W::new(self) } #[doc = "Bit 7 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn tcomp(&mut self) -> TCOMP_W<7> { + pub fn tcomp(&mut self) -> TCOMP_W { TCOMP_W::new(self) } #[doc = "Bit 10 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rovr(&mut self) -> ROVR_W<10> { + pub fn rovr(&mut self) -> ROVR_W { ROVR_W::new(self) } #[doc = "Bit 11 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<11> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Bit 12 - Pause Frame with Non-zero Pause Quantum Received"] #[inline(always)] #[must_use] - pub fn pfnz(&mut self) -> PFNZ_W<12> { + pub fn pfnz(&mut self) -> PFNZ_W { PFNZ_W::new(self) } #[doc = "Bit 13 - Pause Time Zero"] #[inline(always)] #[must_use] - pub fn ptz(&mut self) -> PTZ_W<13> { + pub fn ptz(&mut self) -> PTZ_W { PTZ_W::new(self) } #[doc = "Bit 14 - Pause Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pftr(&mut self) -> PFTR_W<14> { + pub fn pftr(&mut self) -> PFTR_W { PFTR_W::new(self) } #[doc = "Bit 15 - External Interrupt"] #[inline(always)] #[must_use] - pub fn exint(&mut self) -> EXINT_W<15> { + pub fn exint(&mut self) -> EXINT_W { EXINT_W::new(self) } #[doc = "Bit 18 - PTP Delay Request Frame Received"] #[inline(always)] #[must_use] - pub fn drqfr(&mut self) -> DRQFR_W<18> { + pub fn drqfr(&mut self) -> DRQFR_W { DRQFR_W::new(self) } #[doc = "Bit 19 - PTP Sync Frame Received"] #[inline(always)] #[must_use] - pub fn sfr(&mut self) -> SFR_W<19> { + pub fn sfr(&mut self) -> SFR_W { SFR_W::new(self) } #[doc = "Bit 20 - PTP Delay Request Frame Transmitted"] #[inline(always)] #[must_use] - pub fn drqft(&mut self) -> DRQFT_W<20> { + pub fn drqft(&mut self) -> DRQFT_W { DRQFT_W::new(self) } #[doc = "Bit 21 - PTP Sync Frame Transmitted"] #[inline(always)] #[must_use] - pub fn sft(&mut self) -> SFT_W<21> { + pub fn sft(&mut self) -> SFT_W { SFT_W::new(self) } #[doc = "Bit 22 - PDelay Request Frame Received"] #[inline(always)] #[must_use] - pub fn pdrqfr(&mut self) -> PDRQFR_W<22> { + pub fn pdrqfr(&mut self) -> PDRQFR_W { PDRQFR_W::new(self) } #[doc = "Bit 23 - PDelay Response Frame Received"] #[inline(always)] #[must_use] - pub fn pdrsfr(&mut self) -> PDRSFR_W<23> { + pub fn pdrsfr(&mut self) -> PDRSFR_W { PDRSFR_W::new(self) } #[doc = "Bit 24 - PDelay Request Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pdrqft(&mut self) -> PDRQFT_W<24> { + pub fn pdrqft(&mut self) -> PDRQFT_W { PDRQFT_W::new(self) } #[doc = "Bit 25 - PDelay Response Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pdrsft(&mut self) -> PDRSFT_W<25> { + pub fn pdrsft(&mut self) -> PDRSFT_W { PDRSFT_W::new(self) } #[doc = "Bit 26 - TSU Seconds Register Increment"] #[inline(always)] #[must_use] - pub fn sri(&mut self) -> SRI_W<26> { + pub fn sri(&mut self) -> SRI_W { SRI_W::new(self) } #[doc = "Bit 27 - Enable RX LPI Indication"] #[inline(always)] #[must_use] - pub fn rxlpisbc(&mut self) -> RXLPISBC_W<27> { + pub fn rxlpisbc(&mut self) -> RXLPISBC_W { RXLPISBC_W::new(self) } #[doc = "Bit 28 - Wake On LAN"] #[inline(always)] #[must_use] - pub fn wol(&mut self) -> WOL_W<28> { + pub fn wol(&mut self) -> WOL_W { WOL_W::new(self) } #[doc = "Bit 29 - TSU Timer Comparison"] #[inline(always)] #[must_use] - pub fn tsutimcomp(&mut self) -> TSUTIMCOMP_W<29> { + pub fn tsutimcomp(&mut self) -> TSUTIMCOMP_W { TSUTIMCOMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ierpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ierpq.rs index 8ca61234..88cf35bf 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ierpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ierpq.rs @@ -1,96 +1,76 @@ #[doc = "Register `IERPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RCOMP` writer - Receive Complete"] -pub type RCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type RCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUBR` writer - RX Used Bit Read"] -pub type RXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type RXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLEX` writer - Retry Limit Exceeded or Late Collision"] -pub type RLEX_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type RLEX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"] -pub type TFC_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type TFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOMP` writer - Transmit Complete"] -pub type TCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type TCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROVR` writer - Receive Overrun"] -pub type ROVR_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type ROVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, IERPQ_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 1 - Receive Complete"] #[inline(always)] #[must_use] - pub fn rcomp(&mut self) -> RCOMP_W<1> { + pub fn rcomp(&mut self) -> RCOMP_W { RCOMP_W::new(self) } #[doc = "Bit 2 - RX Used Bit Read"] #[inline(always)] #[must_use] - pub fn rxubr(&mut self) -> RXUBR_W<2> { + pub fn rxubr(&mut self) -> RXUBR_W { RXUBR_W::new(self) } #[doc = "Bit 5 - Retry Limit Exceeded or Late Collision"] #[inline(always)] #[must_use] - pub fn rlex(&mut self) -> RLEX_W<5> { + pub fn rlex(&mut self) -> RLEX_W { RLEX_W::new(self) } #[doc = "Bit 6 - Transmit Frame Corruption Due to AHB Error"] #[inline(always)] #[must_use] - pub fn tfc(&mut self) -> TFC_W<6> { + pub fn tfc(&mut self) -> TFC_W { TFC_W::new(self) } #[doc = "Bit 7 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn tcomp(&mut self) -> TCOMP_W<7> { + pub fn tcomp(&mut self) -> TCOMP_W { TCOMP_W::new(self) } #[doc = "Bit 10 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rovr(&mut self) -> ROVR_W<10> { + pub fn rovr(&mut self) -> ROVR_W { ROVR_W::new(self) } #[doc = "Bit 11 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<11> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register Priority Queue (1..5)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ierpq](index.html) module"] +#[doc = "Interrupt Enable Register Priority Queue (1..5)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ierpq::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IERPQ_SPEC; impl crate::RegisterSpec for IERPQ_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ierpq::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ierpq::W`](W) writer structure"] impl crate::Writable for IERPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ihce.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ihce.rs index f3ffb386..c9f4f8b7 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ihce.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ihce.rs @@ -1,18 +1,5 @@ #[doc = "Register `IHCE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HCKER` reader - IP Header Checksum Errors"] pub type HCKER_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { HCKER_R::new((self.bits & 0xff) as u8) } } -#[doc = "IP Header Checksum Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ihce](index.html) module"] +#[doc = "IP Header Checksum Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ihce::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IHCE_SPEC; impl crate::RegisterSpec for IHCE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ihce::R](R) reader structure"] -impl crate::Readable for IHCE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ihce::R`](R) reader structure"] +impl crate::Readable for IHCE_SPEC {} #[doc = "`reset()` method sets IHCE to value 0"] impl crate::Resettable for IHCE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/imr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/imr.rs index 876bc7c9..046b9250 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/imr.rs @@ -1,143 +1,111 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MFS` reader - Management Frame Sent"] pub type MFS_R = crate::BitReader; #[doc = "Field `MFS` writer - Management Frame Sent"] -pub type MFS_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type MFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCOMP` reader - Receive Complete"] pub type RCOMP_R = crate::BitReader; #[doc = "Field `RCOMP` writer - Receive Complete"] -pub type RCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUBR` reader - RX Used Bit Read"] pub type RXUBR_R = crate::BitReader; #[doc = "Field `RXUBR` writer - RX Used Bit Read"] -pub type RXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUBR` reader - TX Used Bit Read"] pub type TXUBR_R = crate::BitReader; #[doc = "Field `TXUBR` writer - TX Used Bit Read"] -pub type TXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TUR` reader - Transmit Underrun"] pub type TUR_R = crate::BitReader; #[doc = "Field `TUR` writer - Transmit Underrun"] -pub type TUR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLEX` reader - Retry Limit Exceeded"] pub type RLEX_R = crate::BitReader; #[doc = "Field `RLEX` writer - Retry Limit Exceeded"] -pub type RLEX_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RLEX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFC` reader - Transmit Frame Corruption Due to AHB Error"] pub type TFC_R = crate::BitReader; #[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"] -pub type TFC_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOMP` reader - Transmit Complete"] pub type TCOMP_R = crate::BitReader; #[doc = "Field `TCOMP` writer - Transmit Complete"] -pub type TCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROVR` reader - Receive Overrun"] pub type ROVR_R = crate::BitReader; #[doc = "Field `ROVR` writer - Receive Overrun"] -pub type ROVR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type ROVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` reader - HRESP Not OK"] pub type HRESP_R = crate::BitReader; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFNZ` reader - Pause Frame with Non-zero Pause Quantum Received"] pub type PFNZ_R = crate::BitReader; #[doc = "Field `PFNZ` writer - Pause Frame with Non-zero Pause Quantum Received"] -pub type PFNZ_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PFNZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTZ` reader - Pause Time Zero"] pub type PTZ_R = crate::BitReader; #[doc = "Field `PTZ` writer - Pause Time Zero"] -pub type PTZ_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PTZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFTR` reader - Pause Frame Transmitted"] pub type PFTR_R = crate::BitReader; #[doc = "Field `PFTR` writer - Pause Frame Transmitted"] -pub type PFTR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PFTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXINT` reader - External Interrupt"] pub type EXINT_R = crate::BitReader; #[doc = "Field `EXINT` writer - External Interrupt"] -pub type EXINT_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type EXINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRQFR` reader - PTP Delay Request Frame Received"] pub type DRQFR_R = crate::BitReader; #[doc = "Field `DRQFR` writer - PTP Delay Request Frame Received"] -pub type DRQFR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type DRQFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SFR` reader - PTP Sync Frame Received"] pub type SFR_R = crate::BitReader; #[doc = "Field `SFR` writer - PTP Sync Frame Received"] -pub type SFR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type SFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRQFT` reader - PTP Delay Request Frame Transmitted"] pub type DRQFT_R = crate::BitReader; #[doc = "Field `DRQFT` writer - PTP Delay Request Frame Transmitted"] -pub type DRQFT_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type DRQFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SFT` reader - PTP Sync Frame Transmitted"] pub type SFT_R = crate::BitReader; #[doc = "Field `SFT` writer - PTP Sync Frame Transmitted"] -pub type SFT_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type SFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRQFR` reader - PDelay Request Frame Received"] pub type PDRQFR_R = crate::BitReader; #[doc = "Field `PDRQFR` writer - PDelay Request Frame Received"] -pub type PDRQFR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PDRQFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRSFR` reader - PDelay Response Frame Received"] pub type PDRSFR_R = crate::BitReader; #[doc = "Field `PDRSFR` writer - PDelay Response Frame Received"] -pub type PDRSFR_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PDRSFR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRQFT` reader - PDelay Request Frame Transmitted"] pub type PDRQFT_R = crate::BitReader; #[doc = "Field `PDRQFT` writer - PDelay Request Frame Transmitted"] -pub type PDRQFT_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PDRQFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDRSFT` reader - PDelay Response Frame Transmitted"] pub type PDRSFT_R = crate::BitReader; #[doc = "Field `PDRSFT` writer - PDelay Response Frame Transmitted"] -pub type PDRSFT_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type PDRSFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRI` reader - TSU Seconds Register Increment"] pub type SRI_R = crate::BitReader; #[doc = "Field `SRI` writer - TSU Seconds Register Increment"] -pub type SRI_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type SRI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXLPISBC` reader - Enable RX LPI Indication"] pub type RXLPISBC_R = crate::BitReader; #[doc = "Field `RXLPISBC` writer - Enable RX LPI Indication"] -pub type RXLPISBC_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type RXLPISBC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WOL` reader - Wake On LAN"] pub type WOL_R = crate::BitReader; #[doc = "Field `WOL` writer - Wake On LAN"] -pub type WOL_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type WOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSUTIMCOMP` reader - TSU Timer Comparison"] pub type TSUTIMCOMP_R = crate::BitReader; #[doc = "Field `TSUTIMCOMP` writer - TSU Timer Comparison"] -pub type TSUTIMCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IMR_SPEC, O>; +pub type TSUTIMCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Management Frame Sent"] #[inline(always)] @@ -274,178 +242,175 @@ impl W { #[doc = "Bit 0 - Management Frame Sent"] #[inline(always)] #[must_use] - pub fn mfs(&mut self) -> MFS_W<0> { + pub fn mfs(&mut self) -> MFS_W { MFS_W::new(self) } #[doc = "Bit 1 - Receive Complete"] #[inline(always)] #[must_use] - pub fn rcomp(&mut self) -> RCOMP_W<1> { + pub fn rcomp(&mut self) -> RCOMP_W { RCOMP_W::new(self) } #[doc = "Bit 2 - RX Used Bit Read"] #[inline(always)] #[must_use] - pub fn rxubr(&mut self) -> RXUBR_W<2> { + pub fn rxubr(&mut self) -> RXUBR_W { RXUBR_W::new(self) } #[doc = "Bit 3 - TX Used Bit Read"] #[inline(always)] #[must_use] - pub fn txubr(&mut self) -> TXUBR_W<3> { + pub fn txubr(&mut self) -> TXUBR_W { TXUBR_W::new(self) } #[doc = "Bit 4 - Transmit Underrun"] #[inline(always)] #[must_use] - pub fn tur(&mut self) -> TUR_W<4> { + pub fn tur(&mut self) -> TUR_W { TUR_W::new(self) } #[doc = "Bit 5 - Retry Limit Exceeded"] #[inline(always)] #[must_use] - pub fn rlex(&mut self) -> RLEX_W<5> { + pub fn rlex(&mut self) -> RLEX_W { RLEX_W::new(self) } #[doc = "Bit 6 - Transmit Frame Corruption Due to AHB Error"] #[inline(always)] #[must_use] - pub fn tfc(&mut self) -> TFC_W<6> { + pub fn tfc(&mut self) -> TFC_W { TFC_W::new(self) } #[doc = "Bit 7 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn tcomp(&mut self) -> TCOMP_W<7> { + pub fn tcomp(&mut self) -> TCOMP_W { TCOMP_W::new(self) } #[doc = "Bit 10 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rovr(&mut self) -> ROVR_W<10> { + pub fn rovr(&mut self) -> ROVR_W { ROVR_W::new(self) } #[doc = "Bit 11 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<11> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Bit 12 - Pause Frame with Non-zero Pause Quantum Received"] #[inline(always)] #[must_use] - pub fn pfnz(&mut self) -> PFNZ_W<12> { + pub fn pfnz(&mut self) -> PFNZ_W { PFNZ_W::new(self) } #[doc = "Bit 13 - Pause Time Zero"] #[inline(always)] #[must_use] - pub fn ptz(&mut self) -> PTZ_W<13> { + pub fn ptz(&mut self) -> PTZ_W { PTZ_W::new(self) } #[doc = "Bit 14 - Pause Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pftr(&mut self) -> PFTR_W<14> { + pub fn pftr(&mut self) -> PFTR_W { PFTR_W::new(self) } #[doc = "Bit 15 - External Interrupt"] #[inline(always)] #[must_use] - pub fn exint(&mut self) -> EXINT_W<15> { + pub fn exint(&mut self) -> EXINT_W { EXINT_W::new(self) } #[doc = "Bit 18 - PTP Delay Request Frame Received"] #[inline(always)] #[must_use] - pub fn drqfr(&mut self) -> DRQFR_W<18> { + pub fn drqfr(&mut self) -> DRQFR_W { DRQFR_W::new(self) } #[doc = "Bit 19 - PTP Sync Frame Received"] #[inline(always)] #[must_use] - pub fn sfr(&mut self) -> SFR_W<19> { + pub fn sfr(&mut self) -> SFR_W { SFR_W::new(self) } #[doc = "Bit 20 - PTP Delay Request Frame Transmitted"] #[inline(always)] #[must_use] - pub fn drqft(&mut self) -> DRQFT_W<20> { + pub fn drqft(&mut self) -> DRQFT_W { DRQFT_W::new(self) } #[doc = "Bit 21 - PTP Sync Frame Transmitted"] #[inline(always)] #[must_use] - pub fn sft(&mut self) -> SFT_W<21> { + pub fn sft(&mut self) -> SFT_W { SFT_W::new(self) } #[doc = "Bit 22 - PDelay Request Frame Received"] #[inline(always)] #[must_use] - pub fn pdrqfr(&mut self) -> PDRQFR_W<22> { + pub fn pdrqfr(&mut self) -> PDRQFR_W { PDRQFR_W::new(self) } #[doc = "Bit 23 - PDelay Response Frame Received"] #[inline(always)] #[must_use] - pub fn pdrsfr(&mut self) -> PDRSFR_W<23> { + pub fn pdrsfr(&mut self) -> PDRSFR_W { PDRSFR_W::new(self) } #[doc = "Bit 24 - PDelay Request Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pdrqft(&mut self) -> PDRQFT_W<24> { + pub fn pdrqft(&mut self) -> PDRQFT_W { PDRQFT_W::new(self) } #[doc = "Bit 25 - PDelay Response Frame Transmitted"] #[inline(always)] #[must_use] - pub fn pdrsft(&mut self) -> PDRSFT_W<25> { + pub fn pdrsft(&mut self) -> PDRSFT_W { PDRSFT_W::new(self) } #[doc = "Bit 26 - TSU Seconds Register Increment"] #[inline(always)] #[must_use] - pub fn sri(&mut self) -> SRI_W<26> { + pub fn sri(&mut self) -> SRI_W { SRI_W::new(self) } #[doc = "Bit 27 - Enable RX LPI Indication"] #[inline(always)] #[must_use] - pub fn rxlpisbc(&mut self) -> RXLPISBC_W<27> { + pub fn rxlpisbc(&mut self) -> RXLPISBC_W { RXLPISBC_W::new(self) } #[doc = "Bit 28 - Wake On LAN"] #[inline(always)] #[must_use] - pub fn wol(&mut self) -> WOL_W<28> { + pub fn wol(&mut self) -> WOL_W { WOL_W::new(self) } #[doc = "Bit 29 - TSU Timer Comparison"] #[inline(always)] #[must_use] - pub fn tsutimcomp(&mut self) -> TSUTIMCOMP_W<29> { + pub fn tsutimcomp(&mut self) -> TSUTIMCOMP_W { TSUTIMCOMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [imr::W](W) writer structure"] +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] impl crate::Writable for IMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/imrpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/imrpq.rs index ab03a6fe..c5db1bae 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/imrpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/imrpq.rs @@ -1,67 +1,35 @@ #[doc = "Register `IMRPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IMRPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RCOMP` reader - Receive Complete"] pub type RCOMP_R = crate::BitReader; #[doc = "Field `RCOMP` writer - Receive Complete"] -pub type RCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type RCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXUBR` reader - RX Used Bit Read"] pub type RXUBR_R = crate::BitReader; #[doc = "Field `RXUBR` writer - RX Used Bit Read"] -pub type RXUBR_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type RXUBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLEX` reader - Retry Limit Exceeded or Late Collision"] pub type RLEX_R = crate::BitReader; #[doc = "Field `RLEX` writer - Retry Limit Exceeded or Late Collision"] -pub type RLEX_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type RLEX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AHB` reader - AHB Error"] pub type AHB_R = crate::BitReader; #[doc = "Field `AHB` writer - AHB Error"] -pub type AHB_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type AHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOMP` reader - Transmit Complete"] pub type TCOMP_R = crate::BitReader; #[doc = "Field `TCOMP` writer - Transmit Complete"] -pub type TCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type TCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROVR` reader - Receive Overrun"] pub type ROVR_R = crate::BitReader; #[doc = "Field `ROVR` writer - Receive Overrun"] -pub type ROVR_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type ROVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` reader - HRESP Not OK"] pub type HRESP_R = crate::BitReader; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, IMRPQ_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Receive Complete"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bit 1 - Receive Complete"] #[inline(always)] #[must_use] - pub fn rcomp(&mut self) -> RCOMP_W<1> { + pub fn rcomp(&mut self) -> RCOMP_W { RCOMP_W::new(self) } #[doc = "Bit 2 - RX Used Bit Read"] #[inline(always)] #[must_use] - pub fn rxubr(&mut self) -> RXUBR_W<2> { + pub fn rxubr(&mut self) -> RXUBR_W { RXUBR_W::new(self) } #[doc = "Bit 5 - Retry Limit Exceeded or Late Collision"] #[inline(always)] #[must_use] - pub fn rlex(&mut self) -> RLEX_W<5> { + pub fn rlex(&mut self) -> RLEX_W { RLEX_W::new(self) } #[doc = "Bit 6 - AHB Error"] #[inline(always)] #[must_use] - pub fn ahb(&mut self) -> AHB_W<6> { + pub fn ahb(&mut self) -> AHB_W { AHB_W::new(self) } #[doc = "Bit 7 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn tcomp(&mut self) -> TCOMP_W<7> { + pub fn tcomp(&mut self) -> TCOMP_W { TCOMP_W::new(self) } #[doc = "Bit 10 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rovr(&mut self) -> ROVR_W<10> { + pub fn rovr(&mut self) -> ROVR_W { ROVR_W::new(self) } #[doc = "Bit 11 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<11> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Mask Register Priority Queue (1..5)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imrpq](index.html) module"] +#[doc = "Interrupt Mask Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imrpq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imrpq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMRPQ_SPEC; impl crate::RegisterSpec for IMRPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imrpq::R](R) reader structure"] -impl crate::Readable for IMRPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [imrpq::W](W) writer structure"] +#[doc = "`read()` method returns [`imrpq::R`](R) reader structure"] +impl crate::Readable for IMRPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`imrpq::W`](W) writer structure"] impl crate::Writable for IMRPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ipgs.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ipgs.rs index 62fa33e8..cfe2d025 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ipgs.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ipgs.rs @@ -1,43 +1,11 @@ #[doc = "Register `IPGS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IPGS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FL` reader - Frame Length"] pub type FL_R = crate::FieldReader; #[doc = "Field `FL` writer - Frame Length"] -pub type FL_W<'a, const O: u8> = crate::FieldWriter<'a, IPGS_SPEC, 16, O, u16>; +pub type FL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Frame Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Frame Length"] #[inline(always)] #[must_use] - pub fn fl(&mut self) -> FL_W<0> { + pub fn fl(&mut self) -> FL_W { FL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "IPG Stretch Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ipgs](index.html) module"] +#[doc = "IPG Stretch Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ipgs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ipgs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IPGS_SPEC; impl crate::RegisterSpec for IPGS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ipgs::R](R) reader structure"] -impl crate::Readable for IPGS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ipgs::W](W) writer structure"] +#[doc = "`read()` method returns [`ipgs::R`](R) reader structure"] +impl crate::Readable for IPGS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ipgs::W`](W) writer structure"] impl crate::Writable for IPGS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/isr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/isr.rs index 4cbeafc4..5519bae3 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MFS` reader - Management Frame Sent"] pub type MFS_R = crate::BitReader; #[doc = "Field `RCOMP` reader - Receive Complete"] @@ -190,15 +177,13 @@ impl R { TSUTIMCOMP_R::new(((self.bits >> 29) & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/isrpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/isrpq.rs index 341b6a79..4cc0b246 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/isrpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/isrpq.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISRPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RCOMP` reader - Receive Complete"] pub type RCOMP_R = crate::BitReader; #[doc = "Field `RXUBR` reader - RX Used Bit Read"] @@ -64,15 +51,13 @@ impl R { HRESP_R::new(((self.bits >> 11) & 1) != 0) } } -#[doc = "Interrupt Status Register Priority Queue (1..5)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isrpq](index.html) module"] +#[doc = "Interrupt Status Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isrpq::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISRPQ_SPEC; impl crate::RegisterSpec for ISRPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isrpq::R](R) reader structure"] -impl crate::Readable for ISRPQ_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isrpq::R`](R) reader structure"] +impl crate::Readable for ISRPQ_SPEC {} #[doc = "`reset()` method sets ISRPQ[%s] to value 0"] impl crate::Resettable for ISRPQ_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/jr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/jr.rs index bec04fbe..54500963 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/jr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/jr.rs @@ -1,18 +1,5 @@ #[doc = "Register `JR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `JRX` reader - Jabbers Received"] pub type JRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { JRX_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Jabbers Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [jr](index.html) module"] +#[doc = "Jabbers Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`jr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct JR_SPEC; impl crate::RegisterSpec for JR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [jr::R](R) reader structure"] -impl crate::Readable for JR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`jr::R`](R) reader structure"] +impl crate::Readable for JR_SPEC {} #[doc = "`reset()` method sets JR to value 0"] impl crate::Resettable for JR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/lc.rs b/arch/cortex-m/samv71q21-pac/src/gmac/lc.rs index 784e8776..544ba210 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/lc.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/lc.rs @@ -1,18 +1,5 @@ #[doc = "Register `LC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LCOL` reader - Late Collisions"] pub type LCOL_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { LCOL_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Late Collisions Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lc](index.html) module"] +#[doc = "Late Collisions Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LC_SPEC; impl crate::RegisterSpec for LC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lc::R](R) reader structure"] -impl crate::Readable for LC_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`lc::R`](R) reader structure"] +impl crate::Readable for LC_SPEC {} #[doc = "`reset()` method sets LC to value 0"] impl crate::Resettable for LC_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/lffe.rs b/arch/cortex-m/samv71q21-pac/src/gmac/lffe.rs index 266c5e9e..c17c9e7e 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/lffe.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/lffe.rs @@ -1,18 +1,5 @@ #[doc = "Register `LFFE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LFER` reader - Length Field Frame Errors"] pub type LFER_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { LFER_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Length Field Frame Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lffe](index.html) module"] +#[doc = "Length Field Frame Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lffe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LFFE_SPEC; impl crate::RegisterSpec for LFFE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lffe::R](R) reader structure"] -impl crate::Readable for LFFE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`lffe::R`](R) reader structure"] +impl crate::Readable for LFFE_SPEC {} #[doc = "`reset()` method sets LFFE to value 0"] impl crate::Resettable for LFFE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/man.rs b/arch/cortex-m/samv71q21-pac/src/gmac/man.rs index ebd1f1f6..3529e0f9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/man.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/man.rs @@ -1,67 +1,35 @@ #[doc = "Register `MAN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MAN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - PHY Data"] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - PHY Data"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, MAN_SPEC, 16, O, u16>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `WTN` reader - Write Ten"] pub type WTN_R = crate::FieldReader; #[doc = "Field `WTN` writer - Write Ten"] -pub type WTN_W<'a, const O: u8> = crate::FieldWriter<'a, MAN_SPEC, 2, O>; +pub type WTN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `REGA` reader - Register Address"] pub type REGA_R = crate::FieldReader; #[doc = "Field `REGA` writer - Register Address"] -pub type REGA_W<'a, const O: u8> = crate::FieldWriter<'a, MAN_SPEC, 5, O>; +pub type REGA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `PHYA` reader - PHY Address"] pub type PHYA_R = crate::FieldReader; #[doc = "Field `PHYA` writer - PHY Address"] -pub type PHYA_W<'a, const O: u8> = crate::FieldWriter<'a, MAN_SPEC, 5, O>; +pub type PHYA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `OP` reader - Operation"] pub type OP_R = crate::FieldReader; #[doc = "Field `OP` writer - Operation"] -pub type OP_W<'a, const O: u8> = crate::FieldWriter<'a, MAN_SPEC, 2, O>; +pub type OP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `CLTTO` reader - Clause 22 Operation"] pub type CLTTO_R = crate::BitReader; #[doc = "Field `CLTTO` writer - Clause 22 Operation"] -pub type CLTTO_W<'a, const O: u8> = crate::BitWriter<'a, MAN_SPEC, O>; +pub type CLTTO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WZO` reader - Write ZERO"] pub type WZO_R = crate::BitReader; #[doc = "Field `WZO` writer - Write ZERO"] -pub type WZO_W<'a, const O: u8> = crate::BitWriter<'a, MAN_SPEC, O>; +pub type WZO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - PHY Data"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bits 0:15 - PHY Data"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Bits 16:17 - Write Ten"] #[inline(always)] #[must_use] - pub fn wtn(&mut self) -> WTN_W<16> { + pub fn wtn(&mut self) -> WTN_W { WTN_W::new(self) } #[doc = "Bits 18:22 - Register Address"] #[inline(always)] #[must_use] - pub fn rega(&mut self) -> REGA_W<18> { + pub fn rega(&mut self) -> REGA_W { REGA_W::new(self) } #[doc = "Bits 23:27 - PHY Address"] #[inline(always)] #[must_use] - pub fn phya(&mut self) -> PHYA_W<23> { + pub fn phya(&mut self) -> PHYA_W { PHYA_W::new(self) } #[doc = "Bits 28:29 - Operation"] #[inline(always)] #[must_use] - pub fn op(&mut self) -> OP_W<28> { + pub fn op(&mut self) -> OP_W { OP_W::new(self) } #[doc = "Bit 30 - Clause 22 Operation"] #[inline(always)] #[must_use] - pub fn cltto(&mut self) -> CLTTO_W<30> { + pub fn cltto(&mut self) -> CLTTO_W { CLTTO_W::new(self) } #[doc = "Bit 31 - Write ZERO"] #[inline(always)] #[must_use] - pub fn wzo(&mut self) -> WZO_W<31> { + pub fn wzo(&mut self) -> WZO_W { WZO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PHY Maintenance Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [man](index.html) module"] +#[doc = "PHY Maintenance Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`man::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`man::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MAN_SPEC; impl crate::RegisterSpec for MAN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [man::R](R) reader structure"] -impl crate::Readable for MAN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [man::W](W) writer structure"] +#[doc = "`read()` method returns [`man::R`](R) reader structure"] +impl crate::Readable for MAN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`man::W`](W) writer structure"] impl crate::Writable for MAN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/mcf.rs b/arch/cortex-m/samv71q21-pac/src/gmac/mcf.rs index 84f53c2f..e72f7b08 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/mcf.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/mcf.rs @@ -1,18 +1,5 @@ #[doc = "Register `MCF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MCOL` reader - Multiple Collision"] pub type MCOL_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { MCOL_R::new(self.bits & 0x0003_ffff) } } -#[doc = "Multiple Collision Frames Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcf](index.html) module"] +#[doc = "Multiple Collision Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCF_SPEC; impl crate::RegisterSpec for MCF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mcf::R](R) reader structure"] -impl crate::Readable for MCF_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mcf::R`](R) reader structure"] +impl crate::Readable for MCF_SPEC {} #[doc = "`reset()` method sets MCF to value 0"] impl crate::Resettable for MCF_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/mfr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/mfr.rs index 7effde8a..207f3393 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/mfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/mfr.rs @@ -1,18 +1,5 @@ #[doc = "Register `MFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MFRX` reader - Multicast Frames Received without Error"] pub type MFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { MFRX_R::new(self.bits) } } -#[doc = "Multicast Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mfr](index.html) module"] +#[doc = "Multicast Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFR_SPEC; impl crate::RegisterSpec for MFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mfr::R](R) reader structure"] -impl crate::Readable for MFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mfr::R`](R) reader structure"] +impl crate::Readable for MFR_SPEC {} #[doc = "`reset()` method sets MFR to value 0"] impl crate::Resettable for MFR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/mft.rs b/arch/cortex-m/samv71q21-pac/src/gmac/mft.rs index f9afb4db..606a3345 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/mft.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/mft.rs @@ -1,18 +1,5 @@ #[doc = "Register `MFT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MFTX` reader - Multicast Frames Transmitted without Error"] pub type MFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { MFTX_R::new(self.bits) } } -#[doc = "Multicast Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mft](index.html) module"] +#[doc = "Multicast Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mft::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MFT_SPEC; impl crate::RegisterSpec for MFT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mft::R](R) reader structure"] -impl crate::Readable for MFT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mft::R`](R) reader structure"] +impl crate::Readable for MFT_SPEC {} #[doc = "`reset()` method sets MFT to value 0"] impl crate::Resettable for MFT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ncfgr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ncfgr.rs index 3b87c63d..8d70dcae 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ncfgr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ncfgr.rs @@ -1,95 +1,63 @@ #[doc = "Register `NCFGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NCFGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPD` reader - Speed"] pub type SPD_R = crate::BitReader; #[doc = "Field `SPD` writer - Speed"] -pub type SPD_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type SPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FD` reader - Full Duplex"] pub type FD_R = crate::BitReader; #[doc = "Field `FD` writer - Full Duplex"] -pub type FD_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type FD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DNVLAN` reader - Discard Non-VLAN FRAMES"] pub type DNVLAN_R = crate::BitReader; #[doc = "Field `DNVLAN` writer - Discard Non-VLAN FRAMES"] -pub type DNVLAN_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type DNVLAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `JFRAME` reader - Jumbo Frame Size"] pub type JFRAME_R = crate::BitReader; #[doc = "Field `JFRAME` writer - Jumbo Frame Size"] -pub type JFRAME_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type JFRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAF` reader - Copy All Frames"] pub type CAF_R = crate::BitReader; #[doc = "Field `CAF` writer - Copy All Frames"] -pub type CAF_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type CAF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBC` reader - No Broadcast"] pub type NBC_R = crate::BitReader; #[doc = "Field `NBC` writer - No Broadcast"] -pub type NBC_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type NBC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MTIHEN` reader - Multicast Hash Enable"] pub type MTIHEN_R = crate::BitReader; #[doc = "Field `MTIHEN` writer - Multicast Hash Enable"] -pub type MTIHEN_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type MTIHEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNIHEN` reader - Unicast Hash Enable"] pub type UNIHEN_R = crate::BitReader; #[doc = "Field `UNIHEN` writer - Unicast Hash Enable"] -pub type UNIHEN_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type UNIHEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MAXFS` reader - 1536 Maximum Frame Size"] pub type MAXFS_R = crate::BitReader; #[doc = "Field `MAXFS` writer - 1536 Maximum Frame Size"] -pub type MAXFS_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type MAXFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTY` reader - Retry Test"] pub type RTY_R = crate::BitReader; #[doc = "Field `RTY` writer - Retry Test"] -pub type RTY_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type RTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN` reader - Pause Enable"] pub type PEN_R = crate::BitReader; #[doc = "Field `PEN` writer - Pause Enable"] -pub type PEN_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type PEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBUFO` reader - Receive Buffer Offset"] pub type RXBUFO_R = crate::FieldReader; #[doc = "Field `RXBUFO` writer - Receive Buffer Offset"] -pub type RXBUFO_W<'a, const O: u8> = crate::FieldWriter<'a, NCFGR_SPEC, 2, O>; +pub type RXBUFO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `LFERD` reader - Length Field Error Frame Discard"] pub type LFERD_R = crate::BitReader; #[doc = "Field `LFERD` writer - Length Field Error Frame Discard"] -pub type LFERD_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type LFERD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RFCS` reader - Remove FCS"] pub type RFCS_R = crate::BitReader; #[doc = "Field `RFCS` writer - Remove FCS"] -pub type RFCS_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type RFCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLK` reader - MDC CLock Division"] pub type CLK_R = crate::FieldReader; #[doc = "MDC CLock Division\n\nValue on reset: 0"] @@ -132,103 +100,107 @@ impl CLK_R { _ => None, } } - #[doc = "Checks if the value of the field is `MCK_8`"] + #[doc = "MCK divided by 8 (MCK up to 20 MHz)"] #[inline(always)] pub fn is_mck_8(&self) -> bool { *self == CLKSELECT_A::MCK_8 } - #[doc = "Checks if the value of the field is `MCK_16`"] + #[doc = "MCK divided by 16 (MCK up to 40 MHz)"] #[inline(always)] pub fn is_mck_16(&self) -> bool { *self == CLKSELECT_A::MCK_16 } - #[doc = "Checks if the value of the field is `MCK_32`"] + #[doc = "MCK divided by 32 (MCK up to 80 MHz)"] #[inline(always)] pub fn is_mck_32(&self) -> bool { *self == CLKSELECT_A::MCK_32 } - #[doc = "Checks if the value of the field is `MCK_48`"] + #[doc = "MCK divided by 48 (MCK up to 120 MHz)"] #[inline(always)] pub fn is_mck_48(&self) -> bool { *self == CLKSELECT_A::MCK_48 } - #[doc = "Checks if the value of the field is `MCK_64`"] + #[doc = "MCK divided by 64 (MCK up to 160 MHz)"] #[inline(always)] pub fn is_mck_64(&self) -> bool { *self == CLKSELECT_A::MCK_64 } - #[doc = "Checks if the value of the field is `MCK_96`"] + #[doc = "MCK divided by 96 (MCK up to 240 MHz)"] #[inline(always)] pub fn is_mck_96(&self) -> bool { *self == CLKSELECT_A::MCK_96 } } #[doc = "Field `CLK` writer - MDC CLock Division"] -pub type CLK_W<'a, const O: u8> = crate::FieldWriter<'a, NCFGR_SPEC, 3, O, CLKSELECT_A>; -impl<'a, const O: u8> CLK_W<'a, O> { +pub type CLK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CLKSELECT_A>; +impl<'a, REG, const O: u8> CLK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "MCK divided by 8 (MCK up to 20 MHz)"] #[inline(always)] - pub fn mck_8(self) -> &'a mut W { + pub fn mck_8(self) -> &'a mut crate::W { self.variant(CLKSELECT_A::MCK_8) } #[doc = "MCK divided by 16 (MCK up to 40 MHz)"] #[inline(always)] - pub fn mck_16(self) -> &'a mut W { + pub fn mck_16(self) -> &'a mut crate::W { self.variant(CLKSELECT_A::MCK_16) } #[doc = "MCK divided by 32 (MCK up to 80 MHz)"] #[inline(always)] - pub fn mck_32(self) -> &'a mut W { + pub fn mck_32(self) -> &'a mut crate::W { self.variant(CLKSELECT_A::MCK_32) } #[doc = "MCK divided by 48 (MCK up to 120 MHz)"] #[inline(always)] - pub fn mck_48(self) -> &'a mut W { + pub fn mck_48(self) -> &'a mut crate::W { self.variant(CLKSELECT_A::MCK_48) } #[doc = "MCK divided by 64 (MCK up to 160 MHz)"] #[inline(always)] - pub fn mck_64(self) -> &'a mut W { + pub fn mck_64(self) -> &'a mut crate::W { self.variant(CLKSELECT_A::MCK_64) } #[doc = "MCK divided by 96 (MCK up to 240 MHz)"] #[inline(always)] - pub fn mck_96(self) -> &'a mut W { + pub fn mck_96(self) -> &'a mut crate::W { self.variant(CLKSELECT_A::MCK_96) } } #[doc = "Field `DBW` reader - Data Bus Width"] pub type DBW_R = crate::FieldReader; #[doc = "Field `DBW` writer - Data Bus Width"] -pub type DBW_W<'a, const O: u8> = crate::FieldWriter<'a, NCFGR_SPEC, 2, O>; +pub type DBW_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `DCPF` reader - Disable Copy of Pause Frames"] pub type DCPF_R = crate::BitReader; #[doc = "Field `DCPF` writer - Disable Copy of Pause Frames"] -pub type DCPF_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type DCPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXCOEN` reader - Receive Checksum Offload Enable"] pub type RXCOEN_R = crate::BitReader; #[doc = "Field `RXCOEN` writer - Receive Checksum Offload Enable"] -pub type RXCOEN_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type RXCOEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EFRHD` reader - Enable Frames Received in Half Duplex"] pub type EFRHD_R = crate::BitReader; #[doc = "Field `EFRHD` writer - Enable Frames Received in Half Duplex"] -pub type EFRHD_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type EFRHD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IRXFCS` reader - Ignore RX FCS"] pub type IRXFCS_R = crate::BitReader; #[doc = "Field `IRXFCS` writer - Ignore RX FCS"] -pub type IRXFCS_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type IRXFCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IPGSEN` reader - IP Stretch Enable"] pub type IPGSEN_R = crate::BitReader; #[doc = "Field `IPGSEN` writer - IP Stretch Enable"] -pub type IPGSEN_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type IPGSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBP` reader - Receive Bad Preamble"] pub type RXBP_R = crate::BitReader; #[doc = "Field `RXBP` writer - Receive Bad Preamble"] -pub type RXBP_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type RXBP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IRXER` reader - Ignore IPG GRXER"] pub type IRXER_R = crate::BitReader; #[doc = "Field `IRXER` writer - Ignore IPG GRXER"] -pub type IRXER_W<'a, const O: u8> = crate::BitWriter<'a, NCFGR_SPEC, O>; +pub type IRXER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Speed"] #[inline(always)] @@ -350,160 +322,157 @@ impl W { #[doc = "Bit 0 - Speed"] #[inline(always)] #[must_use] - pub fn spd(&mut self) -> SPD_W<0> { + pub fn spd(&mut self) -> SPD_W { SPD_W::new(self) } #[doc = "Bit 1 - Full Duplex"] #[inline(always)] #[must_use] - pub fn fd(&mut self) -> FD_W<1> { + pub fn fd(&mut self) -> FD_W { FD_W::new(self) } #[doc = "Bit 2 - Discard Non-VLAN FRAMES"] #[inline(always)] #[must_use] - pub fn dnvlan(&mut self) -> DNVLAN_W<2> { + pub fn dnvlan(&mut self) -> DNVLAN_W { DNVLAN_W::new(self) } #[doc = "Bit 3 - Jumbo Frame Size"] #[inline(always)] #[must_use] - pub fn jframe(&mut self) -> JFRAME_W<3> { + pub fn jframe(&mut self) -> JFRAME_W { JFRAME_W::new(self) } #[doc = "Bit 4 - Copy All Frames"] #[inline(always)] #[must_use] - pub fn caf(&mut self) -> CAF_W<4> { + pub fn caf(&mut self) -> CAF_W { CAF_W::new(self) } #[doc = "Bit 5 - No Broadcast"] #[inline(always)] #[must_use] - pub fn nbc(&mut self) -> NBC_W<5> { + pub fn nbc(&mut self) -> NBC_W { NBC_W::new(self) } #[doc = "Bit 6 - Multicast Hash Enable"] #[inline(always)] #[must_use] - pub fn mtihen(&mut self) -> MTIHEN_W<6> { + pub fn mtihen(&mut self) -> MTIHEN_W { MTIHEN_W::new(self) } #[doc = "Bit 7 - Unicast Hash Enable"] #[inline(always)] #[must_use] - pub fn unihen(&mut self) -> UNIHEN_W<7> { + pub fn unihen(&mut self) -> UNIHEN_W { UNIHEN_W::new(self) } #[doc = "Bit 8 - 1536 Maximum Frame Size"] #[inline(always)] #[must_use] - pub fn maxfs(&mut self) -> MAXFS_W<8> { + pub fn maxfs(&mut self) -> MAXFS_W { MAXFS_W::new(self) } #[doc = "Bit 12 - Retry Test"] #[inline(always)] #[must_use] - pub fn rty(&mut self) -> RTY_W<12> { + pub fn rty(&mut self) -> RTY_W { RTY_W::new(self) } #[doc = "Bit 13 - Pause Enable"] #[inline(always)] #[must_use] - pub fn pen(&mut self) -> PEN_W<13> { + pub fn pen(&mut self) -> PEN_W { PEN_W::new(self) } #[doc = "Bits 14:15 - Receive Buffer Offset"] #[inline(always)] #[must_use] - pub fn rxbufo(&mut self) -> RXBUFO_W<14> { + pub fn rxbufo(&mut self) -> RXBUFO_W { RXBUFO_W::new(self) } #[doc = "Bit 16 - Length Field Error Frame Discard"] #[inline(always)] #[must_use] - pub fn lferd(&mut self) -> LFERD_W<16> { + pub fn lferd(&mut self) -> LFERD_W { LFERD_W::new(self) } #[doc = "Bit 17 - Remove FCS"] #[inline(always)] #[must_use] - pub fn rfcs(&mut self) -> RFCS_W<17> { + pub fn rfcs(&mut self) -> RFCS_W { RFCS_W::new(self) } #[doc = "Bits 18:20 - MDC CLock Division"] #[inline(always)] #[must_use] - pub fn clk(&mut self) -> CLK_W<18> { + pub fn clk(&mut self) -> CLK_W { CLK_W::new(self) } #[doc = "Bits 21:22 - Data Bus Width"] #[inline(always)] #[must_use] - pub fn dbw(&mut self) -> DBW_W<21> { + pub fn dbw(&mut self) -> DBW_W { DBW_W::new(self) } #[doc = "Bit 23 - Disable Copy of Pause Frames"] #[inline(always)] #[must_use] - pub fn dcpf(&mut self) -> DCPF_W<23> { + pub fn dcpf(&mut self) -> DCPF_W { DCPF_W::new(self) } #[doc = "Bit 24 - Receive Checksum Offload Enable"] #[inline(always)] #[must_use] - pub fn rxcoen(&mut self) -> RXCOEN_W<24> { + pub fn rxcoen(&mut self) -> RXCOEN_W { RXCOEN_W::new(self) } #[doc = "Bit 25 - Enable Frames Received in Half Duplex"] #[inline(always)] #[must_use] - pub fn efrhd(&mut self) -> EFRHD_W<25> { + pub fn efrhd(&mut self) -> EFRHD_W { EFRHD_W::new(self) } #[doc = "Bit 26 - Ignore RX FCS"] #[inline(always)] #[must_use] - pub fn irxfcs(&mut self) -> IRXFCS_W<26> { + pub fn irxfcs(&mut self) -> IRXFCS_W { IRXFCS_W::new(self) } #[doc = "Bit 28 - IP Stretch Enable"] #[inline(always)] #[must_use] - pub fn ipgsen(&mut self) -> IPGSEN_W<28> { + pub fn ipgsen(&mut self) -> IPGSEN_W { IPGSEN_W::new(self) } #[doc = "Bit 29 - Receive Bad Preamble"] #[inline(always)] #[must_use] - pub fn rxbp(&mut self) -> RXBP_W<29> { + pub fn rxbp(&mut self) -> RXBP_W { RXBP_W::new(self) } #[doc = "Bit 30 - Ignore IPG GRXER"] #[inline(always)] #[must_use] - pub fn irxer(&mut self) -> IRXER_W<30> { + pub fn irxer(&mut self) -> IRXER_W { IRXER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Network Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ncfgr](index.html) module"] +#[doc = "Network Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ncfgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ncfgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NCFGR_SPEC; impl crate::RegisterSpec for NCFGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ncfgr::R](R) reader structure"] -impl crate::Readable for NCFGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ncfgr::W](W) writer structure"] +#[doc = "`read()` method returns [`ncfgr::R`](R) reader structure"] +impl crate::Readable for NCFGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ncfgr::W`](W) writer structure"] impl crate::Writable for NCFGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ncr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ncr.rs index e20b0fd6..3dd82688 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ncr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ncr.rs @@ -1,107 +1,75 @@ #[doc = "Register `NCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LBL` reader - Loop Back Local"] pub type LBL_R = crate::BitReader; #[doc = "Field `LBL` writer - Loop Back Local"] -pub type LBL_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type LBL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXEN` reader - Receive Enable"] pub type RXEN_R = crate::BitReader; #[doc = "Field `RXEN` writer - Receive Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` reader - Transmit Enable"] pub type TXEN_R = crate::BitReader; #[doc = "Field `TXEN` writer - Transmit Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MPE` reader - Management Port Enable"] pub type MPE_R = crate::BitReader; #[doc = "Field `MPE` writer - Management Port Enable"] -pub type MPE_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type MPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLRSTAT` reader - Clear Statistics Registers"] pub type CLRSTAT_R = crate::BitReader; #[doc = "Field `CLRSTAT` writer - Clear Statistics Registers"] -pub type CLRSTAT_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type CLRSTAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INCSTAT` reader - Increment Statistics Registers"] pub type INCSTAT_R = crate::BitReader; #[doc = "Field `INCSTAT` writer - Increment Statistics Registers"] -pub type INCSTAT_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type INCSTAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WESTAT` reader - Write Enable for Statistics Registers"] pub type WESTAT_R = crate::BitReader; #[doc = "Field `WESTAT` writer - Write Enable for Statistics Registers"] -pub type WESTAT_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type WESTAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BP` reader - Back pressure"] pub type BP_R = crate::BitReader; #[doc = "Field `BP` writer - Back pressure"] -pub type BP_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type BP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSTART` reader - Start Transmission"] pub type TSTART_R = crate::BitReader; #[doc = "Field `TSTART` writer - Start Transmission"] -pub type TSTART_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type TSTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `THALT` reader - Transmit Halt"] pub type THALT_R = crate::BitReader; #[doc = "Field `THALT` writer - Transmit Halt"] -pub type THALT_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type THALT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXPF` reader - Transmit Pause Frame"] pub type TXPF_R = crate::BitReader; #[doc = "Field `TXPF` writer - Transmit Pause Frame"] -pub type TXPF_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type TXPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXZQPF` reader - Transmit Zero Quantum Pause Frame"] pub type TXZQPF_R = crate::BitReader; #[doc = "Field `TXZQPF` writer - Transmit Zero Quantum Pause Frame"] -pub type TXZQPF_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type TXZQPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRTSM` reader - Store Receive Time Stamp to Memory"] pub type SRTSM_R = crate::BitReader; #[doc = "Field `SRTSM` writer - Store Receive Time Stamp to Memory"] -pub type SRTSM_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type SRTSM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENPBPR` reader - Enable PFC Priority-based Pause Reception"] pub type ENPBPR_R = crate::BitReader; #[doc = "Field `ENPBPR` writer - Enable PFC Priority-based Pause Reception"] -pub type ENPBPR_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type ENPBPR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXPBPF` reader - Transmit PFC Priority-based Pause Frame"] pub type TXPBPF_R = crate::BitReader; #[doc = "Field `TXPBPF` writer - Transmit PFC Priority-based Pause Frame"] -pub type TXPBPF_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type TXPBPF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FNP` reader - Flush Next Packet"] pub type FNP_R = crate::BitReader; #[doc = "Field `FNP` writer - Flush Next Packet"] -pub type FNP_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type FNP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXLPIEN` reader - Enable LPI Transmission"] pub type TXLPIEN_R = crate::BitReader; #[doc = "Field `TXLPIEN` writer - Enable LPI Transmission"] -pub type TXLPIEN_W<'a, const O: u8> = crate::BitWriter<'a, NCR_SPEC, O>; +pub type TXLPIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 1 - Loop Back Local"] #[inline(always)] @@ -193,124 +161,121 @@ impl W { #[doc = "Bit 1 - Loop Back Local"] #[inline(always)] #[must_use] - pub fn lbl(&mut self) -> LBL_W<1> { + pub fn lbl(&mut self) -> LBL_W { LBL_W::new(self) } #[doc = "Bit 2 - Receive Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<2> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 3 - Transmit Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<3> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 4 - Management Port Enable"] #[inline(always)] #[must_use] - pub fn mpe(&mut self) -> MPE_W<4> { + pub fn mpe(&mut self) -> MPE_W { MPE_W::new(self) } #[doc = "Bit 5 - Clear Statistics Registers"] #[inline(always)] #[must_use] - pub fn clrstat(&mut self) -> CLRSTAT_W<5> { + pub fn clrstat(&mut self) -> CLRSTAT_W { CLRSTAT_W::new(self) } #[doc = "Bit 6 - Increment Statistics Registers"] #[inline(always)] #[must_use] - pub fn incstat(&mut self) -> INCSTAT_W<6> { + pub fn incstat(&mut self) -> INCSTAT_W { INCSTAT_W::new(self) } #[doc = "Bit 7 - Write Enable for Statistics Registers"] #[inline(always)] #[must_use] - pub fn westat(&mut self) -> WESTAT_W<7> { + pub fn westat(&mut self) -> WESTAT_W { WESTAT_W::new(self) } #[doc = "Bit 8 - Back pressure"] #[inline(always)] #[must_use] - pub fn bp(&mut self) -> BP_W<8> { + pub fn bp(&mut self) -> BP_W { BP_W::new(self) } #[doc = "Bit 9 - Start Transmission"] #[inline(always)] #[must_use] - pub fn tstart(&mut self) -> TSTART_W<9> { + pub fn tstart(&mut self) -> TSTART_W { TSTART_W::new(self) } #[doc = "Bit 10 - Transmit Halt"] #[inline(always)] #[must_use] - pub fn thalt(&mut self) -> THALT_W<10> { + pub fn thalt(&mut self) -> THALT_W { THALT_W::new(self) } #[doc = "Bit 11 - Transmit Pause Frame"] #[inline(always)] #[must_use] - pub fn txpf(&mut self) -> TXPF_W<11> { + pub fn txpf(&mut self) -> TXPF_W { TXPF_W::new(self) } #[doc = "Bit 12 - Transmit Zero Quantum Pause Frame"] #[inline(always)] #[must_use] - pub fn txzqpf(&mut self) -> TXZQPF_W<12> { + pub fn txzqpf(&mut self) -> TXZQPF_W { TXZQPF_W::new(self) } #[doc = "Bit 15 - Store Receive Time Stamp to Memory"] #[inline(always)] #[must_use] - pub fn srtsm(&mut self) -> SRTSM_W<15> { + pub fn srtsm(&mut self) -> SRTSM_W { SRTSM_W::new(self) } #[doc = "Bit 16 - Enable PFC Priority-based Pause Reception"] #[inline(always)] #[must_use] - pub fn enpbpr(&mut self) -> ENPBPR_W<16> { + pub fn enpbpr(&mut self) -> ENPBPR_W { ENPBPR_W::new(self) } #[doc = "Bit 17 - Transmit PFC Priority-based Pause Frame"] #[inline(always)] #[must_use] - pub fn txpbpf(&mut self) -> TXPBPF_W<17> { + pub fn txpbpf(&mut self) -> TXPBPF_W { TXPBPF_W::new(self) } #[doc = "Bit 18 - Flush Next Packet"] #[inline(always)] #[must_use] - pub fn fnp(&mut self) -> FNP_W<18> { + pub fn fnp(&mut self) -> FNP_W { FNP_W::new(self) } #[doc = "Bit 19 - Enable LPI Transmission"] #[inline(always)] #[must_use] - pub fn txlpien(&mut self) -> TXLPIEN_W<19> { + pub fn txlpien(&mut self) -> TXLPIEN_W { TXLPIEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Network Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ncr](index.html) module"] +#[doc = "Network Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ncr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ncr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NCR_SPEC; impl crate::RegisterSpec for NCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ncr::R](R) reader structure"] -impl crate::Readable for NCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ncr::W](W) writer structure"] +#[doc = "`read()` method returns [`ncr::R`](R) reader structure"] +impl crate::Readable for NCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ncr::W`](W) writer structure"] impl crate::Writable for NCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/nsc.rs b/arch/cortex-m/samv71q21-pac/src/gmac/nsc.rs index 0bc69d8c..703549c9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/nsc.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/nsc.rs @@ -1,43 +1,11 @@ #[doc = "Register `NSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NANOSEC` reader - 1588 Timer Nanosecond Comparison Value"] pub type NANOSEC_R = crate::FieldReader; #[doc = "Field `NANOSEC` writer - 1588 Timer Nanosecond Comparison Value"] -pub type NANOSEC_W<'a, const O: u8> = crate::FieldWriter<'a, NSC_SPEC, 22, O, u32>; +pub type NANOSEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 22, O, u32>; impl R { #[doc = "Bits 0:21 - 1588 Timer Nanosecond Comparison Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:21 - 1588 Timer Nanosecond Comparison Value"] #[inline(always)] #[must_use] - pub fn nanosec(&mut self) -> NANOSEC_W<0> { + pub fn nanosec(&mut self) -> NANOSEC_W { NANOSEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Nanosecond Comparison Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nsc](index.html) module"] +#[doc = "1588 Timer Nanosecond Comparison Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NSC_SPEC; impl crate::RegisterSpec for NSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nsc::R](R) reader structure"] -impl crate::Readable for NSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nsc::W](W) writer structure"] +#[doc = "`read()` method returns [`nsc::R`](R) reader structure"] +impl crate::Readable for NSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nsc::W`](W) writer structure"] impl crate::Writable for NSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/nsr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/nsr.rs index 11be60a3..894c8377 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/nsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/nsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `NSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MDIO` reader - MDIO Input Status"] pub type MDIO_R = crate::BitReader; #[doc = "Field `IDLE` reader - PHY Management Logic Idle"] @@ -36,15 +23,13 @@ impl R { RXLPIS_R::new(((self.bits >> 7) & 1) != 0) } } -#[doc = "Network Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nsr](index.html) module"] +#[doc = "Network Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NSR_SPEC; impl crate::RegisterSpec for NSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nsr::R](R) reader structure"] -impl crate::Readable for NSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`nsr::R`](R) reader structure"] +impl crate::Readable for NSR_SPEC {} #[doc = "`reset()` method sets NSR to value 0"] impl crate::Resettable for NSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ofr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ofr.rs index 49d306fa..c335463b 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ofr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ofr.rs @@ -1,18 +1,5 @@ #[doc = "Register `OFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `OFRX` reader - Oversized Frames Received"] pub type OFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { OFRX_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Oversize Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ofr](index.html) module"] +#[doc = "Oversize Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ofr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OFR_SPEC; impl crate::RegisterSpec for OFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ofr::R](R) reader structure"] -impl crate::Readable for OFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ofr::R`](R) reader structure"] +impl crate::Readable for OFR_SPEC {} #[doc = "`reset()` method sets OFR to value 0"] impl crate::Resettable for OFR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/orhi.rs b/arch/cortex-m/samv71q21-pac/src/gmac/orhi.rs index c08a1eab..b6a9abf8 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/orhi.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/orhi.rs @@ -1,18 +1,5 @@ #[doc = "Register `ORHI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXO` reader - Received Octets"] pub type RXO_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXO_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Octets Received High Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [orhi](index.html) module"] +#[doc = "Octets Received High Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`orhi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ORHI_SPEC; impl crate::RegisterSpec for ORHI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [orhi::R](R) reader structure"] -impl crate::Readable for ORHI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`orhi::R`](R) reader structure"] +impl crate::Readable for ORHI_SPEC {} #[doc = "`reset()` method sets ORHI to value 0"] impl crate::Resettable for ORHI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/orlo.rs b/arch/cortex-m/samv71q21-pac/src/gmac/orlo.rs index e5f0a3d7..51c67322 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/orlo.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/orlo.rs @@ -1,18 +1,5 @@ #[doc = "Register `ORLO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXO` reader - Received Octets"] pub type RXO_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXO_R::new(self.bits) } } -#[doc = "Octets Received Low Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [orlo](index.html) module"] +#[doc = "Octets Received Low Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`orlo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ORLO_SPEC; impl crate::RegisterSpec for ORLO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [orlo::R](R) reader structure"] -impl crate::Readable for ORLO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`orlo::R`](R) reader structure"] +impl crate::Readable for ORLO_SPEC {} #[doc = "`reset()` method sets ORLO to value 0"] impl crate::Resettable for ORLO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/othi.rs b/arch/cortex-m/samv71q21-pac/src/gmac/othi.rs index fcd96218..35cf4b6c 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/othi.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/othi.rs @@ -1,18 +1,5 @@ #[doc = "Register `OTHI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXO` reader - Transmitted Octets"] pub type TXO_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { TXO_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Octets Transmitted High Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [othi](index.html) module"] +#[doc = "Octets Transmitted High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`othi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OTHI_SPEC; impl crate::RegisterSpec for OTHI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [othi::R](R) reader structure"] -impl crate::Readable for OTHI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`othi::R`](R) reader structure"] +impl crate::Readable for OTHI_SPEC {} #[doc = "`reset()` method sets OTHI to value 0"] impl crate::Resettable for OTHI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/otlo.rs b/arch/cortex-m/samv71q21-pac/src/gmac/otlo.rs index 32dee20b..26267c90 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/otlo.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/otlo.rs @@ -1,18 +1,5 @@ #[doc = "Register `OTLO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXO` reader - Transmitted Octets"] pub type TXO_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { TXO_R::new(self.bits) } } -#[doc = "Octets Transmitted Low Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [otlo](index.html) module"] +#[doc = "Octets Transmitted Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otlo::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OTLO_SPEC; impl crate::RegisterSpec for OTLO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [otlo::R](R) reader structure"] -impl crate::Readable for OTLO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`otlo::R`](R) reader structure"] +impl crate::Readable for OTLO_SPEC {} #[doc = "`reset()` method sets OTLO to value 0"] impl crate::Resettable for OTLO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/pefrn.rs b/arch/cortex-m/samv71q21-pac/src/gmac/pefrn.rs index ae35dbdc..b0bbb445 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/pefrn.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/pefrn.rs @@ -1,18 +1,5 @@ #[doc = "Register `PEFRN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits & 0x3fff_ffff) } } -#[doc = "PTP Peer Event Frame Received Nanoseconds Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pefrn](index.html) module"] +#[doc = "PTP Peer Event Frame Received Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pefrn::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEFRN_SPEC; impl crate::RegisterSpec for PEFRN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pefrn::R](R) reader structure"] -impl crate::Readable for PEFRN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pefrn::R`](R) reader structure"] +impl crate::Readable for PEFRN_SPEC {} #[doc = "`reset()` method sets PEFRN to value 0"] impl crate::Resettable for PEFRN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/pefrsh.rs b/arch/cortex-m/samv71q21-pac/src/gmac/pefrsh.rs index f4b80637..d1efb44f 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/pefrsh.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/pefrsh.rs @@ -1,18 +1,5 @@ #[doc = "Register `PEFRSH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new((self.bits & 0xffff) as u16) } } -#[doc = "PTP Peer Event Frame Received Seconds High Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pefrsh](index.html) module"] +#[doc = "PTP Peer Event Frame Received Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pefrsh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEFRSH_SPEC; impl crate::RegisterSpec for PEFRSH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pefrsh::R](R) reader structure"] -impl crate::Readable for PEFRSH_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pefrsh::R`](R) reader structure"] +impl crate::Readable for PEFRSH_SPEC {} #[doc = "`reset()` method sets PEFRSH to value 0"] impl crate::Resettable for PEFRSH_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/pefrsl.rs b/arch/cortex-m/samv71q21-pac/src/gmac/pefrsl.rs index 57becb56..cd47bbbe 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/pefrsl.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/pefrsl.rs @@ -1,18 +1,5 @@ #[doc = "Register `PEFRSL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits) } } -#[doc = "PTP Peer Event Frame Received Seconds Low Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pefrsl](index.html) module"] +#[doc = "PTP Peer Event Frame Received Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pefrsl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEFRSL_SPEC; impl crate::RegisterSpec for PEFRSL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pefrsl::R](R) reader structure"] -impl crate::Readable for PEFRSL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pefrsl::R`](R) reader structure"] +impl crate::Readable for PEFRSL_SPEC {} #[doc = "`reset()` method sets PEFRSL to value 0"] impl crate::Resettable for PEFRSL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/peftn.rs b/arch/cortex-m/samv71q21-pac/src/gmac/peftn.rs index a1b49738..d2e84223 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/peftn.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/peftn.rs @@ -1,18 +1,5 @@ #[doc = "Register `PEFTN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits & 0x3fff_ffff) } } -#[doc = "PTP Peer Event Frame Transmitted Nanoseconds Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peftn](index.html) module"] +#[doc = "PTP Peer Event Frame Transmitted Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peftn::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEFTN_SPEC; impl crate::RegisterSpec for PEFTN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peftn::R](R) reader structure"] -impl crate::Readable for PEFTN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`peftn::R`](R) reader structure"] +impl crate::Readable for PEFTN_SPEC {} #[doc = "`reset()` method sets PEFTN to value 0"] impl crate::Resettable for PEFTN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/peftsh.rs b/arch/cortex-m/samv71q21-pac/src/gmac/peftsh.rs index 1d88d0b4..0473033f 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/peftsh.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/peftsh.rs @@ -1,18 +1,5 @@ #[doc = "Register `PEFTSH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new((self.bits & 0xffff) as u16) } } -#[doc = "PTP Peer Event Frame Transmitted Seconds High Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peftsh](index.html) module"] +#[doc = "PTP Peer Event Frame Transmitted Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peftsh::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEFTSH_SPEC; impl crate::RegisterSpec for PEFTSH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peftsh::R](R) reader structure"] -impl crate::Readable for PEFTSH_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`peftsh::R`](R) reader structure"] +impl crate::Readable for PEFTSH_SPEC {} #[doc = "`reset()` method sets PEFTSH to value 0"] impl crate::Resettable for PEFTSH_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/peftsl.rs b/arch/cortex-m/samv71q21-pac/src/gmac/peftsl.rs index 34583cf8..067e3433 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/peftsl.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/peftsl.rs @@ -1,18 +1,5 @@ #[doc = "Register `PEFTSL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RUD` reader - Register Update"] pub type RUD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RUD_R::new(self.bits) } } -#[doc = "PTP Peer Event Frame Transmitted Seconds Low Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peftsl](index.html) module"] +#[doc = "PTP Peer Event Frame Transmitted Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peftsl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PEFTSL_SPEC; impl crate::RegisterSpec for PEFTSL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [peftsl::R](R) reader structure"] -impl crate::Readable for PEFTSL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`peftsl::R`](R) reader structure"] +impl crate::Readable for PEFTSL_SPEC {} #[doc = "`reset()` method sets PEFTSL to value 0"] impl crate::Resettable for PEFTSL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/pfr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/pfr.rs index f88ceafe..9d39d2fd 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/pfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/pfr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PFRX` reader - Pause Frames Received Register"] pub type PFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { PFRX_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Pause Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pfr](index.html) module"] +#[doc = "Pause Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PFR_SPEC; impl crate::RegisterSpec for PFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pfr::R](R) reader structure"] -impl crate::Readable for PFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pfr::R`](R) reader structure"] +impl crate::Readable for PFR_SPEC {} #[doc = "`reset()` method sets PFR to value 0"] impl crate::Resettable for PFR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/pft.rs b/arch/cortex-m/samv71q21-pac/src/gmac/pft.rs index 537db956..dc91a0c9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/pft.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/pft.rs @@ -1,18 +1,5 @@ #[doc = "Register `PFT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PFTX` reader - Pause Frames Transmitted Register"] pub type PFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { PFTX_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Pause Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pft](index.html) module"] +#[doc = "Pause Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pft::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PFT_SPEC; impl crate::RegisterSpec for PFT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pft::R](R) reader structure"] -impl crate::Readable for PFT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pft::R`](R) reader structure"] +impl crate::Readable for PFT_SPEC {} #[doc = "`reset()` method sets PFT to value 0"] impl crate::Resettable for PFT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rbqb.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rbqb.rs index a6c18587..37a3ae6d 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rbqb.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rbqb.rs @@ -1,43 +1,11 @@ #[doc = "Register `RBQB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RBQB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Receive Buffer Queue Base Address"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Receive Buffer Queue Base Address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, RBQB_SPEC, 30, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Receive Buffer Queue Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Receive Buffer Queue Base Address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<2> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Buffer Queue Base Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rbqb](index.html) module"] +#[doc = "Receive Buffer Queue Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbqb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbqb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RBQB_SPEC; impl crate::RegisterSpec for RBQB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rbqb::R](R) reader structure"] -impl crate::Readable for RBQB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rbqb::W](W) writer structure"] +#[doc = "`read()` method returns [`rbqb::R`](R) reader structure"] +impl crate::Readable for RBQB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rbqb::W`](W) writer structure"] impl crate::Writable for RBQB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rbqbapq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rbqbapq.rs index 0131b4a8..23ff7fc8 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rbqbapq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rbqbapq.rs @@ -1,43 +1,11 @@ #[doc = "Register `RBQBAPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RBQBAPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXBQBA` reader - Receive Buffer Queue Base Address"] pub type RXBQBA_R = crate::FieldReader; #[doc = "Field `RXBQBA` writer - Receive Buffer Queue Base Address"] -pub type RXBQBA_W<'a, const O: u8> = crate::FieldWriter<'a, RBQBAPQ_SPEC, 30, O, u32>; +pub type RXBQBA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Receive Buffer Queue Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Receive Buffer Queue Base Address"] #[inline(always)] #[must_use] - pub fn rxbqba(&mut self) -> RXBQBA_W<2> { + pub fn rxbqba(&mut self) -> RXBQBA_W { RXBQBA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Buffer Queue Base Address Register Priority Queue (1..5)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rbqbapq](index.html) module"] +#[doc = "Receive Buffer Queue Base Address Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbqbapq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbqbapq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RBQBAPQ_SPEC; impl crate::RegisterSpec for RBQBAPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rbqbapq::R](R) reader structure"] -impl crate::Readable for RBQBAPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rbqbapq::W](W) writer structure"] +#[doc = "`read()` method returns [`rbqbapq::R`](R) reader structure"] +impl crate::Readable for RBQBAPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rbqbapq::W`](W) writer structure"] impl crate::Writable for RBQBAPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rbsrpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rbsrpq.rs index 900c988f..574499ce 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rbsrpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rbsrpq.rs @@ -1,43 +1,11 @@ #[doc = "Register `RBSRPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RBSRPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RBS` reader - Receive Buffer Size"] pub type RBS_R = crate::FieldReader; #[doc = "Field `RBS` writer - Receive Buffer Size"] -pub type RBS_W<'a, const O: u8> = crate::FieldWriter<'a, RBSRPQ_SPEC, 16, O, u16>; +pub type RBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Receive Buffer Size"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Receive Buffer Size"] #[inline(always)] #[must_use] - pub fn rbs(&mut self) -> RBS_W<0> { + pub fn rbs(&mut self) -> RBS_W { RBS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Buffer Size Register Priority Queue (1..5)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rbsrpq](index.html) module"] +#[doc = "Receive Buffer Size Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbsrpq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbsrpq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RBSRPQ_SPEC; impl crate::RegisterSpec for RBSRPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rbsrpq::R](R) reader structure"] -impl crate::Readable for RBSRPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rbsrpq::W](W) writer structure"] +#[doc = "`read()` method returns [`rbsrpq::R`](R) reader structure"] +impl crate::Readable for RBSRPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rbsrpq::W`](W) writer structure"] impl crate::Writable for RBSRPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rjfml.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rjfml.rs index 9ea8d4f6..f51787ad 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rjfml.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rjfml.rs @@ -1,43 +1,11 @@ #[doc = "Register `RJFML` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RJFML` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FML` reader - Frame Max Length"] pub type FML_R = crate::FieldReader; #[doc = "Field `FML` writer - Frame Max Length"] -pub type FML_W<'a, const O: u8> = crate::FieldWriter<'a, RJFML_SPEC, 14, O, u16>; +pub type FML_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; impl R { #[doc = "Bits 0:13 - Frame Max Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:13 - Frame Max Length"] #[inline(always)] #[must_use] - pub fn fml(&mut self) -> FML_W<0> { + pub fn fml(&mut self) -> FML_W { FML_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "RX Jumbo Frame Max Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rjfml](index.html) module"] +#[doc = "RX Jumbo Frame Max Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rjfml::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rjfml::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RJFML_SPEC; impl crate::RegisterSpec for RJFML_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rjfml::R](R) reader structure"] -impl crate::Readable for RJFML_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rjfml::W](W) writer structure"] +#[doc = "`read()` method returns [`rjfml::R`](R) reader structure"] +impl crate::Readable for RJFML_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rjfml::W`](W) writer structure"] impl crate::Writable for RJFML_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/roe.rs b/arch/cortex-m/samv71q21-pac/src/gmac/roe.rs index f0bb15ea..ed92a304 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/roe.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/roe.rs @@ -1,18 +1,5 @@ #[doc = "Register `ROE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXOVR` reader - Receive Overruns"] pub type RXOVR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXOVR_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Receive Overrun Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [roe](index.html) module"] +#[doc = "Receive Overrun Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`roe::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ROE_SPEC; impl crate::RegisterSpec for ROE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [roe::R](R) reader structure"] -impl crate::Readable for ROE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`roe::R`](R) reader structure"] +impl crate::Readable for ROE_SPEC {} #[doc = "`reset()` method sets ROE to value 0"] impl crate::Resettable for ROE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rpq.rs index 059c2f28..f1806349 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rpq.rs @@ -1,18 +1,5 @@ #[doc = "Register `RPQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RPQ` reader - Received Pause Quantum"] pub type RPQ_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RPQ_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Received Pause Quantum Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rpq](index.html) module"] +#[doc = "Received Pause Quantum Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rpq::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RPQ_SPEC; impl crate::RegisterSpec for RPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rpq::R](R) reader structure"] -impl crate::Readable for RPQ_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rpq::R`](R) reader structure"] +impl crate::Readable for RPQ_SPEC {} #[doc = "`reset()` method sets RPQ to value 0"] impl crate::Resettable for RPQ_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rpsf.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rpsf.rs index ce7b5baa..6146310b 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rpsf.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rpsf.rs @@ -1,47 +1,15 @@ #[doc = "Register `RPSF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RPSF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RPB1ADR` reader - Receive Partial Store and Forward Address"] pub type RPB1ADR_R = crate::FieldReader; #[doc = "Field `RPB1ADR` writer - Receive Partial Store and Forward Address"] -pub type RPB1ADR_W<'a, const O: u8> = crate::FieldWriter<'a, RPSF_SPEC, 12, O, u16>; +pub type RPB1ADR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `ENRXP` reader - Enable RX Partial Store and Forward Operation"] pub type ENRXP_R = crate::BitReader; #[doc = "Field `ENRXP` writer - Enable RX Partial Store and Forward Operation"] -pub type ENRXP_W<'a, const O: u8> = crate::BitWriter<'a, RPSF_SPEC, O>; +pub type ENRXP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:11 - Receive Partial Store and Forward Address"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:11 - Receive Partial Store and Forward Address"] #[inline(always)] #[must_use] - pub fn rpb1adr(&mut self) -> RPB1ADR_W<0> { + pub fn rpb1adr(&mut self) -> RPB1ADR_W { RPB1ADR_W::new(self) } #[doc = "Bit 31 - Enable RX Partial Store and Forward Operation"] #[inline(always)] #[must_use] - pub fn enrxp(&mut self) -> ENRXP_W<31> { + pub fn enrxp(&mut self) -> ENRXP_W { ENRXP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "RX Partial Store and Forward Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rpsf](index.html) module"] +#[doc = "RX Partial Store and Forward Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rpsf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rpsf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RPSF_SPEC; impl crate::RegisterSpec for RPSF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rpsf::R](R) reader structure"] -impl crate::Readable for RPSF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rpsf::W](W) writer structure"] +#[doc = "`read()` method returns [`rpsf::R`](R) reader structure"] +impl crate::Readable for RPSF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rpsf::W`](W) writer structure"] impl crate::Writable for RPSF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rre.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rre.rs index 28baf55c..4814ce30 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rre.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rre.rs @@ -1,18 +1,5 @@ #[doc = "Register `RRE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRER` reader - Receive Resource Errors"] pub type RXRER_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXRER_R::new(self.bits & 0x0003_ffff) } } -#[doc = "Receive Resource Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rre](index.html) module"] +#[doc = "Receive Resource Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rre::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RRE_SPEC; impl crate::RegisterSpec for RRE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rre::R](R) reader structure"] -impl crate::Readable for RRE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rre::R`](R) reader structure"] +impl crate::Readable for RRE_SPEC {} #[doc = "`reset()` method sets RRE to value 0"] impl crate::Resettable for RRE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rse.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rse.rs index bc37ea73..9c650276 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rse.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rse.rs @@ -1,18 +1,5 @@ #[doc = "Register `RSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXSE` reader - Receive Symbol Errors"] pub type RXSE_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXSE_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Receive Symbol Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rse](index.html) module"] +#[doc = "Receive Symbol Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rse::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSE_SPEC; impl crate::RegisterSpec for RSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rse::R](R) reader structure"] -impl crate::Readable for RSE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rse::R`](R) reader structure"] +impl crate::Readable for RSE_SPEC {} #[doc = "`reset()` method sets RSE to value 0"] impl crate::Resettable for RSE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rsr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rsr.rs index d29f9f88..d94c923c 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rsr.rs @@ -1,55 +1,23 @@ #[doc = "Register `RSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BNA` reader - Buffer Not Available"] pub type BNA_R = crate::BitReader; #[doc = "Field `BNA` writer - Buffer Not Available"] -pub type BNA_W<'a, const O: u8> = crate::BitWriter<'a, RSR_SPEC, O>; +pub type BNA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REC` reader - Frame Received"] pub type REC_R = crate::BitReader; #[doc = "Field `REC` writer - Frame Received"] -pub type REC_W<'a, const O: u8> = crate::BitWriter<'a, RSR_SPEC, O>; +pub type REC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOVR` reader - Receive Overrun"] pub type RXOVR_R = crate::BitReader; #[doc = "Field `RXOVR` writer - Receive Overrun"] -pub type RXOVR_W<'a, const O: u8> = crate::BitWriter<'a, RSR_SPEC, O>; +pub type RXOVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HNO` reader - HRESP Not OK"] pub type HNO_R = crate::BitReader; #[doc = "Field `HNO` writer - HRESP Not OK"] -pub type HNO_W<'a, const O: u8> = crate::BitWriter<'a, RSR_SPEC, O>; +pub type HNO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Buffer Not Available"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - Buffer Not Available"] #[inline(always)] #[must_use] - pub fn bna(&mut self) -> BNA_W<0> { + pub fn bna(&mut self) -> BNA_W { BNA_W::new(self) } #[doc = "Bit 1 - Frame Received"] #[inline(always)] #[must_use] - pub fn rec(&mut self) -> REC_W<1> { + pub fn rec(&mut self) -> REC_W { REC_W::new(self) } #[doc = "Bit 2 - Receive Overrun"] #[inline(always)] #[must_use] - pub fn rxovr(&mut self) -> RXOVR_W<2> { + pub fn rxovr(&mut self) -> RXOVR_W { RXOVR_W::new(self) } #[doc = "Bit 3 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hno(&mut self) -> HNO_W<3> { + pub fn hno(&mut self) -> HNO_W { HNO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rsr](index.html) module"] +#[doc = "Receive Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSR_SPEC; impl crate::RegisterSpec for RSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rsr::R](R) reader structure"] -impl crate::Readable for RSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rsr::W](W) writer structure"] +#[doc = "`read()` method returns [`rsr::R`](R) reader structure"] +impl crate::Readable for RSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rsr::W`](W) writer structure"] impl crate::Writable for RSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rxlpi.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rxlpi.rs index 1c8b3558..037c229c 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rxlpi.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rxlpi.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXLPI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `COUNT` reader - Count of RX LPI transitions (cleared on read)"] pub type COUNT_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { COUNT_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Received LPI Transitions\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxlpi](index.html) module"] +#[doc = "Received LPI Transitions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxlpi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXLPI_SPEC; impl crate::RegisterSpec for RXLPI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxlpi::R](R) reader structure"] -impl crate::Readable for RXLPI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxlpi::R`](R) reader structure"] +impl crate::Readable for RXLPI_SPEC {} #[doc = "`reset()` method sets RXLPI to value 0"] impl crate::Resettable for RXLPI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/rxlpitime.rs b/arch/cortex-m/samv71q21-pac/src/gmac/rxlpitime.rs index 57a3ce23..199afe09 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/rxlpitime.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/rxlpitime.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXLPITIME` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LPITIME` reader - Time in LPI (cleared on read)"] pub type LPITIME_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { LPITIME_R::new(self.bits & 0x00ff_ffff) } } -#[doc = "Received LPI Time\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxlpitime](index.html) module"] +#[doc = "Received LPI Time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxlpitime::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXLPITIME_SPEC; impl crate::RegisterSpec for RXLPITIME_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxlpitime::R](R) reader structure"] -impl crate::Readable for RXLPITIME_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxlpitime::R`](R) reader structure"] +impl crate::Readable for RXLPITIME_SPEC {} #[doc = "`reset()` method sets RXLPITIME to value 0"] impl crate::Resettable for RXLPITIME_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/samb1.rs b/arch/cortex-m/samv71q21-pac/src/gmac/samb1.rs index c0792f41..a132fdb6 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/samb1.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/samb1.rs @@ -1,43 +1,11 @@ #[doc = "Register `SAMB1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SAMB1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Specific Address 1 Mask"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Specific Address 1 Mask"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, SAMB1_SPEC, 32, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Specific Address 1 Mask"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Specific Address 1 Mask"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Specific Address 1 Mask Bottom Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [samb1](index.html) module"] +#[doc = "Specific Address 1 Mask Bottom Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SAMB1_SPEC; impl crate::RegisterSpec for SAMB1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [samb1::R](R) reader structure"] -impl crate::Readable for SAMB1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [samb1::W](W) writer structure"] +#[doc = "`read()` method returns [`samb1::R`](R) reader structure"] +impl crate::Readable for SAMB1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`samb1::W`](W) writer structure"] impl crate::Writable for SAMB1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/samt1.rs b/arch/cortex-m/samv71q21-pac/src/gmac/samt1.rs index e120fcf3..558dbe06 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/samt1.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/samt1.rs @@ -1,43 +1,11 @@ #[doc = "Register `SAMT1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SAMT1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Specific Address 1 Mask"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Specific Address 1 Mask"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, SAMT1_SPEC, 16, O, u16>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Specific Address 1 Mask"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Specific Address 1 Mask"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Specific Address 1 Mask Top Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [samt1](index.html) module"] +#[doc = "Specific Address 1 Mask Top Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`samt1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`samt1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SAMT1_SPEC; impl crate::RegisterSpec for SAMT1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [samt1::R](R) reader structure"] -impl crate::Readable for SAMT1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [samt1::W](W) writer structure"] +#[doc = "`read()` method returns [`samt1::R`](R) reader structure"] +impl crate::Readable for SAMT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`samt1::W`](W) writer structure"] impl crate::Writable for SAMT1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/scf.rs b/arch/cortex-m/samv71q21-pac/src/gmac/scf.rs index 1abef3f2..249e4cfa 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/scf.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/scf.rs @@ -1,18 +1,5 @@ #[doc = "Register `SCF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SCOL` reader - Single Collision"] pub type SCOL_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { SCOL_R::new(self.bits & 0x0003_ffff) } } -#[doc = "Single Collision Frames Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scf](index.html) module"] +#[doc = "Single Collision Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCF_SPEC; impl crate::RegisterSpec for SCF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scf::R](R) reader structure"] -impl crate::Readable for SCF_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`scf::R`](R) reader structure"] +impl crate::Readable for SCF_SPEC {} #[doc = "`reset()` method sets SCF to value 0"] impl crate::Resettable for SCF_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/sch.rs b/arch/cortex-m/samv71q21-pac/src/gmac/sch.rs index 8e1c64dd..df8884a9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/sch.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/sch.rs @@ -1,43 +1,11 @@ #[doc = "Register `SCH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEC` reader - 1588 Timer Second Comparison Value"] pub type SEC_R = crate::FieldReader; #[doc = "Field `SEC` writer - 1588 Timer Second Comparison Value"] -pub type SEC_W<'a, const O: u8> = crate::FieldWriter<'a, SCH_SPEC, 16, O, u16>; +pub type SEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - 1588 Timer Second Comparison Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - 1588 Timer Second Comparison Value"] #[inline(always)] #[must_use] - pub fn sec(&mut self) -> SEC_W<0> { + pub fn sec(&mut self) -> SEC_W { SEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Second Comparison High Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sch](index.html) module"] +#[doc = "1588 Timer Second Comparison High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sch::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sch::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCH_SPEC; impl crate::RegisterSpec for SCH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sch::R](R) reader structure"] -impl crate::Readable for SCH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sch::W](W) writer structure"] +#[doc = "`read()` method returns [`sch::R`](R) reader structure"] +impl crate::Readable for SCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sch::W`](W) writer structure"] impl crate::Writable for SCH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/scl.rs b/arch/cortex-m/samv71q21-pac/src/gmac/scl.rs index 4ca36a5c..b2cb948b 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/scl.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/scl.rs @@ -1,43 +1,11 @@ #[doc = "Register `SCL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEC` reader - 1588 Timer Second Comparison Value"] pub type SEC_R = crate::FieldReader; #[doc = "Field `SEC` writer - 1588 Timer Second Comparison Value"] -pub type SEC_W<'a, const O: u8> = crate::FieldWriter<'a, SCL_SPEC, 32, O, u32>; +pub type SEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - 1588 Timer Second Comparison Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - 1588 Timer Second Comparison Value"] #[inline(always)] #[must_use] - pub fn sec(&mut self) -> SEC_W<0> { + pub fn sec(&mut self) -> SEC_W { SEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Second Comparison Low Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scl](index.html) module"] +#[doc = "1588 Timer Second Comparison Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCL_SPEC; impl crate::RegisterSpec for SCL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scl::R](R) reader structure"] -impl crate::Readable for SCL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scl::W](W) writer structure"] +#[doc = "`read()` method returns [`scl::R`](R) reader structure"] +impl crate::Readable for SCL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scl::W`](W) writer structure"] impl crate::Writable for SCL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/st1rpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/st1rpq.rs index 0d5e65e0..414a20c7 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/st1rpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/st1rpq.rs @@ -1,59 +1,27 @@ #[doc = "Register `ST1RPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ST1RPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `QNB` reader - Queue Number (0-5)"] pub type QNB_R = crate::FieldReader; #[doc = "Field `QNB` writer - Queue Number (0-5)"] -pub type QNB_W<'a, const O: u8> = crate::FieldWriter<'a, ST1RPQ_SPEC, 3, O>; +pub type QNB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DSTCM` reader - Differentiated Services or Traffic Class Match"] pub type DSTCM_R = crate::FieldReader; #[doc = "Field `DSTCM` writer - Differentiated Services or Traffic Class Match"] -pub type DSTCM_W<'a, const O: u8> = crate::FieldWriter<'a, ST1RPQ_SPEC, 8, O>; +pub type DSTCM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `UDPM` reader - UDP Port Match"] pub type UDPM_R = crate::FieldReader; #[doc = "Field `UDPM` writer - UDP Port Match"] -pub type UDPM_W<'a, const O: u8> = crate::FieldWriter<'a, ST1RPQ_SPEC, 16, O, u16>; +pub type UDPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `DSTCE` reader - Differentiated Services or Traffic Class Match Enable"] pub type DSTCE_R = crate::BitReader; #[doc = "Field `DSTCE` writer - Differentiated Services or Traffic Class Match Enable"] -pub type DSTCE_W<'a, const O: u8> = crate::BitWriter<'a, ST1RPQ_SPEC, O>; +pub type DSTCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UDPE` reader - UDP Port Match Enable"] pub type UDPE_R = crate::BitReader; #[doc = "Field `UDPE` writer - UDP Port Match Enable"] -pub type UDPE_W<'a, const O: u8> = crate::BitWriter<'a, ST1RPQ_SPEC, O>; +pub type UDPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:2 - Queue Number (0-5)"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bits 0:2 - Queue Number (0-5)"] #[inline(always)] #[must_use] - pub fn qnb(&mut self) -> QNB_W<0> { + pub fn qnb(&mut self) -> QNB_W { QNB_W::new(self) } #[doc = "Bits 4:11 - Differentiated Services or Traffic Class Match"] #[inline(always)] #[must_use] - pub fn dstcm(&mut self) -> DSTCM_W<4> { + pub fn dstcm(&mut self) -> DSTCM_W { DSTCM_W::new(self) } #[doc = "Bits 12:27 - UDP Port Match"] #[inline(always)] #[must_use] - pub fn udpm(&mut self) -> UDPM_W<12> { + pub fn udpm(&mut self) -> UDPM_W { UDPM_W::new(self) } #[doc = "Bit 28 - Differentiated Services or Traffic Class Match Enable"] #[inline(always)] #[must_use] - pub fn dstce(&mut self) -> DSTCE_W<28> { + pub fn dstce(&mut self) -> DSTCE_W { DSTCE_W::new(self) } #[doc = "Bit 29 - UDP Port Match Enable"] #[inline(always)] #[must_use] - pub fn udpe(&mut self) -> UDPE_W<29> { + pub fn udpe(&mut self) -> UDPE_W { UDPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Screening Type 1 Register Priority Queue\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [st1rpq](index.html) module"] +#[doc = "Screening Type 1 Register Priority Queue\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st1rpq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st1rpq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ST1RPQ_SPEC; impl crate::RegisterSpec for ST1RPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [st1rpq::R](R) reader structure"] -impl crate::Readable for ST1RPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [st1rpq::W](W) writer structure"] +#[doc = "`read()` method returns [`st1rpq::R`](R) reader structure"] +impl crate::Readable for ST1RPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`st1rpq::W`](W) writer structure"] impl crate::Writable for ST1RPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/st2er.rs b/arch/cortex-m/samv71q21-pac/src/gmac/st2er.rs index 08087446..046c5383 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/st2er.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/st2er.rs @@ -1,43 +1,11 @@ #[doc = "Register `ST2ER[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ST2ER[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `COMPVAL` reader - Ethertype Compare Value"] pub type COMPVAL_R = crate::FieldReader; #[doc = "Field `COMPVAL` writer - Ethertype Compare Value"] -pub type COMPVAL_W<'a, const O: u8> = crate::FieldWriter<'a, ST2ER_SPEC, 16, O, u16>; +pub type COMPVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Ethertype Compare Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Ethertype Compare Value"] #[inline(always)] #[must_use] - pub fn compval(&mut self) -> COMPVAL_W<0> { + pub fn compval(&mut self) -> COMPVAL_W { COMPVAL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Screening Type 2 Ethertype Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [st2er](index.html) module"] +#[doc = "Screening Type 2 Ethertype Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2er::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2er::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ST2ER_SPEC; impl crate::RegisterSpec for ST2ER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [st2er::R](R) reader structure"] -impl crate::Readable for ST2ER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [st2er::W](W) writer structure"] +#[doc = "`read()` method returns [`st2er::R`](R) reader structure"] +impl crate::Readable for ST2ER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`st2er::W`](W) writer structure"] impl crate::Writable for ST2ER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/st2rpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/st2rpq.rs index 7a5829bc..4708e538 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/st2rpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/st2rpq.rs @@ -1,83 +1,51 @@ #[doc = "Register `ST2RPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ST2RPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `QNB` reader - Queue Number (0-5)"] pub type QNB_R = crate::FieldReader; #[doc = "Field `QNB` writer - Queue Number (0-5)"] -pub type QNB_W<'a, const O: u8> = crate::FieldWriter<'a, ST2RPQ_SPEC, 3, O>; +pub type QNB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `VLANP` reader - VLAN Priority"] pub type VLANP_R = crate::FieldReader; #[doc = "Field `VLANP` writer - VLAN Priority"] -pub type VLANP_W<'a, const O: u8> = crate::FieldWriter<'a, ST2RPQ_SPEC, 3, O>; +pub type VLANP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `VLANE` reader - VLAN Enable"] pub type VLANE_R = crate::BitReader; #[doc = "Field `VLANE` writer - VLAN Enable"] -pub type VLANE_W<'a, const O: u8> = crate::BitWriter<'a, ST2RPQ_SPEC, O>; +pub type VLANE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2ETH` reader - Index of Screening Type 2 EtherType register x"] pub type I2ETH_R = crate::FieldReader; #[doc = "Field `I2ETH` writer - Index of Screening Type 2 EtherType register x"] -pub type I2ETH_W<'a, const O: u8> = crate::FieldWriter<'a, ST2RPQ_SPEC, 3, O>; +pub type I2ETH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `ETHE` reader - EtherType Enable"] pub type ETHE_R = crate::BitReader; #[doc = "Field `ETHE` writer - EtherType Enable"] -pub type ETHE_W<'a, const O: u8> = crate::BitWriter<'a, ST2RPQ_SPEC, O>; +pub type ETHE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COMPA` reader - Index of Screening Type 2 Compare Word 0/Word 1 register x"] pub type COMPA_R = crate::FieldReader; #[doc = "Field `COMPA` writer - Index of Screening Type 2 Compare Word 0/Word 1 register x"] -pub type COMPA_W<'a, const O: u8> = crate::FieldWriter<'a, ST2RPQ_SPEC, 5, O>; +pub type COMPA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `COMPAE` reader - Compare A Enable"] pub type COMPAE_R = crate::BitReader; #[doc = "Field `COMPAE` writer - Compare A Enable"] -pub type COMPAE_W<'a, const O: u8> = crate::BitWriter<'a, ST2RPQ_SPEC, O>; +pub type COMPAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COMPB` reader - Index of Screening Type 2 Compare Word 0/Word 1 register x"] pub type COMPB_R = crate::FieldReader; #[doc = "Field `COMPB` writer - Index of Screening Type 2 Compare Word 0/Word 1 register x"] -pub type COMPB_W<'a, const O: u8> = crate::FieldWriter<'a, ST2RPQ_SPEC, 5, O>; +pub type COMPB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `COMPBE` reader - Compare B Enable"] pub type COMPBE_R = crate::BitReader; #[doc = "Field `COMPBE` writer - Compare B Enable"] -pub type COMPBE_W<'a, const O: u8> = crate::BitWriter<'a, ST2RPQ_SPEC, O>; +pub type COMPBE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COMPC` reader - Index of Screening Type 2 Compare Word 0/Word 1 register x"] pub type COMPC_R = crate::FieldReader; #[doc = "Field `COMPC` writer - Index of Screening Type 2 Compare Word 0/Word 1 register x"] -pub type COMPC_W<'a, const O: u8> = crate::FieldWriter<'a, ST2RPQ_SPEC, 5, O>; +pub type COMPC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `COMPCE` reader - Compare C Enable"] pub type COMPCE_R = crate::BitReader; #[doc = "Field `COMPCE` writer - Compare C Enable"] -pub type COMPCE_W<'a, const O: u8> = crate::BitWriter<'a, ST2RPQ_SPEC, O>; +pub type COMPCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:2 - Queue Number (0-5)"] #[inline(always)] @@ -139,88 +107,85 @@ impl W { #[doc = "Bits 0:2 - Queue Number (0-5)"] #[inline(always)] #[must_use] - pub fn qnb(&mut self) -> QNB_W<0> { + pub fn qnb(&mut self) -> QNB_W { QNB_W::new(self) } #[doc = "Bits 4:6 - VLAN Priority"] #[inline(always)] #[must_use] - pub fn vlanp(&mut self) -> VLANP_W<4> { + pub fn vlanp(&mut self) -> VLANP_W { VLANP_W::new(self) } #[doc = "Bit 8 - VLAN Enable"] #[inline(always)] #[must_use] - pub fn vlane(&mut self) -> VLANE_W<8> { + pub fn vlane(&mut self) -> VLANE_W { VLANE_W::new(self) } #[doc = "Bits 9:11 - Index of Screening Type 2 EtherType register x"] #[inline(always)] #[must_use] - pub fn i2eth(&mut self) -> I2ETH_W<9> { + pub fn i2eth(&mut self) -> I2ETH_W { I2ETH_W::new(self) } #[doc = "Bit 12 - EtherType Enable"] #[inline(always)] #[must_use] - pub fn ethe(&mut self) -> ETHE_W<12> { + pub fn ethe(&mut self) -> ETHE_W { ETHE_W::new(self) } #[doc = "Bits 13:17 - Index of Screening Type 2 Compare Word 0/Word 1 register x"] #[inline(always)] #[must_use] - pub fn compa(&mut self) -> COMPA_W<13> { + pub fn compa(&mut self) -> COMPA_W { COMPA_W::new(self) } #[doc = "Bit 18 - Compare A Enable"] #[inline(always)] #[must_use] - pub fn compae(&mut self) -> COMPAE_W<18> { + pub fn compae(&mut self) -> COMPAE_W { COMPAE_W::new(self) } #[doc = "Bits 19:23 - Index of Screening Type 2 Compare Word 0/Word 1 register x"] #[inline(always)] #[must_use] - pub fn compb(&mut self) -> COMPB_W<19> { + pub fn compb(&mut self) -> COMPB_W { COMPB_W::new(self) } #[doc = "Bit 24 - Compare B Enable"] #[inline(always)] #[must_use] - pub fn compbe(&mut self) -> COMPBE_W<24> { + pub fn compbe(&mut self) -> COMPBE_W { COMPBE_W::new(self) } #[doc = "Bits 25:29 - Index of Screening Type 2 Compare Word 0/Word 1 register x"] #[inline(always)] #[must_use] - pub fn compc(&mut self) -> COMPC_W<25> { + pub fn compc(&mut self) -> COMPC_W { COMPC_W::new(self) } #[doc = "Bit 30 - Compare C Enable"] #[inline(always)] #[must_use] - pub fn compce(&mut self) -> COMPCE_W<30> { + pub fn compce(&mut self) -> COMPCE_W { COMPCE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Screening Type 2 Register Priority Queue\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [st2rpq](index.html) module"] +#[doc = "Screening Type 2 Register Priority Queue\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`st2rpq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`st2rpq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ST2RPQ_SPEC; impl crate::RegisterSpec for ST2RPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [st2rpq::R](R) reader structure"] -impl crate::Readable for ST2RPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [st2rpq::W](W) writer structure"] +#[doc = "`read()` method returns [`st2rpq::R`](R) reader structure"] +impl crate::Readable for ST2RPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`st2rpq::W`](W) writer structure"] impl crate::Writable for ST2RPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/svlan.rs b/arch/cortex-m/samv71q21-pac/src/gmac/svlan.rs index a3dd4824..c9383cf8 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/svlan.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/svlan.rs @@ -1,47 +1,15 @@ #[doc = "Register `SVLAN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SVLAN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VLAN_TYPE` reader - User Defined VLAN_TYPE Field"] pub type VLAN_TYPE_R = crate::FieldReader; #[doc = "Field `VLAN_TYPE` writer - User Defined VLAN_TYPE Field"] -pub type VLAN_TYPE_W<'a, const O: u8> = crate::FieldWriter<'a, SVLAN_SPEC, 16, O, u16>; +pub type VLAN_TYPE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `ESVLAN` reader - Enable Stacked VLAN Processing Mode"] pub type ESVLAN_R = crate::BitReader; #[doc = "Field `ESVLAN` writer - Enable Stacked VLAN Processing Mode"] -pub type ESVLAN_W<'a, const O: u8> = crate::BitWriter<'a, SVLAN_SPEC, O>; +pub type ESVLAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - User Defined VLAN_TYPE Field"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - User Defined VLAN_TYPE Field"] #[inline(always)] #[must_use] - pub fn vlan_type(&mut self) -> VLAN_TYPE_W<0> { + pub fn vlan_type(&mut self) -> VLAN_TYPE_W { VLAN_TYPE_W::new(self) } #[doc = "Bit 31 - Enable Stacked VLAN Processing Mode"] #[inline(always)] #[must_use] - pub fn esvlan(&mut self) -> ESVLAN_W<31> { + pub fn esvlan(&mut self) -> ESVLAN_W { ESVLAN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Stacked VLAN Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [svlan](index.html) module"] +#[doc = "Stacked VLAN Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`svlan::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`svlan::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SVLAN_SPEC; impl crate::RegisterSpec for SVLAN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [svlan::R](R) reader structure"] -impl crate::Readable for SVLAN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [svlan::W](W) writer structure"] +#[doc = "`read()` method returns [`svlan::R`](R) reader structure"] +impl crate::Readable for SVLAN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`svlan::W`](W) writer structure"] impl crate::Writable for SVLAN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ta.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ta.rs index f52afb58..5ebdd9a9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ta.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ta.rs @@ -1,56 +1,36 @@ #[doc = "Register `TA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ITDT` writer - Increment/Decrement"] -pub type ITDT_W<'a, const O: u8> = crate::FieldWriter<'a, TA_SPEC, 30, O, u32>; +pub type ITDT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; #[doc = "Field `ADJ` writer - Adjust 1588 Timer"] -pub type ADJ_W<'a, const O: u8> = crate::BitWriter<'a, TA_SPEC, O>; +pub type ADJ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:29 - Increment/Decrement"] #[inline(always)] #[must_use] - pub fn itdt(&mut self) -> ITDT_W<0> { + pub fn itdt(&mut self) -> ITDT_W { ITDT_W::new(self) } #[doc = "Bit 31 - Adjust 1588 Timer"] #[inline(always)] #[must_use] - pub fn adj(&mut self) -> ADJ_W<31> { + pub fn adj(&mut self) -> ADJ_W { ADJ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Adjust Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ta](index.html) module"] +#[doc = "1588 Timer Adjust Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ta::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TA_SPEC; impl crate::RegisterSpec for TA_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ta::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ta::W`](W) writer structure"] impl crate::Writable for TA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1023.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1023.rs index d806049e..a919fd21 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1023.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1023.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFR1023` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 512 to 1023 Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "512 to 1023 Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbfr1023](index.html) module"] +#[doc = "512 to 1023 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr1023::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFR1023_SPEC; impl crate::RegisterSpec for TBFR1023_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbfr1023::R](R) reader structure"] -impl crate::Readable for TBFR1023_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbfr1023::R`](R) reader structure"] +impl crate::Readable for TBFR1023_SPEC {} #[doc = "`reset()` method sets TBFR1023 to value 0"] impl crate::Resettable for TBFR1023_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr127.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr127.rs index f9c9490f..08b0bf61 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr127.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr127.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFR127` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 65 to 127 Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "65 to 127 Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbfr127](index.html) module"] +#[doc = "65 to 127 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr127::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFR127_SPEC; impl crate::RegisterSpec for TBFR127_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbfr127::R](R) reader structure"] -impl crate::Readable for TBFR127_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbfr127::R`](R) reader structure"] +impl crate::Readable for TBFR127_SPEC {} #[doc = "`reset()` method sets TBFR127 to value 0"] impl crate::Resettable for TBFR127_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1518.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1518.rs index ec223fc0..d40fe0aa 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1518.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr1518.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFR1518` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 1024 to 1518 Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "1024 to 1518 Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbfr1518](index.html) module"] +#[doc = "1024 to 1518 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr1518::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFR1518_SPEC; impl crate::RegisterSpec for TBFR1518_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbfr1518::R](R) reader structure"] -impl crate::Readable for TBFR1518_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbfr1518::R`](R) reader structure"] +impl crate::Readable for TBFR1518_SPEC {} #[doc = "`reset()` method sets TBFR1518 to value 0"] impl crate::Resettable for TBFR1518_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr255.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr255.rs index c9b22547..a087ae55 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr255.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr255.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFR255` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 128 to 255 Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "128 to 255 Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbfr255](index.html) module"] +#[doc = "128 to 255 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr255::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFR255_SPEC; impl crate::RegisterSpec for TBFR255_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbfr255::R](R) reader structure"] -impl crate::Readable for TBFR255_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbfr255::R`](R) reader structure"] +impl crate::Readable for TBFR255_SPEC {} #[doc = "`reset()` method sets TBFR255 to value 0"] impl crate::Resettable for TBFR255_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr511.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr511.rs index 25a1deeb..b7196f6d 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbfr511.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbfr511.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFR511` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 256 to 511 Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "256 to 511 Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbfr511](index.html) module"] +#[doc = "256 to 511 Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbfr511::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFR511_SPEC; impl crate::RegisterSpec for TBFR511_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbfr511::R](R) reader structure"] -impl crate::Readable for TBFR511_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbfr511::R`](R) reader structure"] +impl crate::Readable for TBFR511_SPEC {} #[doc = "`reset()` method sets TBFR511 to value 0"] impl crate::Resettable for TBFR511_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbft1023.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbft1023.rs index a9890774..3031c547 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbft1023.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbft1023.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFT1023` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - 512 to 1023 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "512 to 1023 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbft1023](index.html) module"] +#[doc = "512 to 1023 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft1023::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFT1023_SPEC; impl crate::RegisterSpec for TBFT1023_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbft1023::R](R) reader structure"] -impl crate::Readable for TBFT1023_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbft1023::R`](R) reader structure"] +impl crate::Readable for TBFT1023_SPEC {} #[doc = "`reset()` method sets TBFT1023 to value 0"] impl crate::Resettable for TBFT1023_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbft127.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbft127.rs index 90256c3a..cb74e214 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbft127.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbft127.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFT127` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - 65 to 127 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "65 to 127 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbft127](index.html) module"] +#[doc = "65 to 127 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft127::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFT127_SPEC; impl crate::RegisterSpec for TBFT127_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbft127::R](R) reader structure"] -impl crate::Readable for TBFT127_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbft127::R`](R) reader structure"] +impl crate::Readable for TBFT127_SPEC {} #[doc = "`reset()` method sets TBFT127 to value 0"] impl crate::Resettable for TBFT127_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbft1518.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbft1518.rs index 3a0661e8..d5fb4c25 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbft1518.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbft1518.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFT1518` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - 1024 to 1518 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "1024 to 1518 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbft1518](index.html) module"] +#[doc = "1024 to 1518 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft1518::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFT1518_SPEC; impl crate::RegisterSpec for TBFT1518_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbft1518::R](R) reader structure"] -impl crate::Readable for TBFT1518_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbft1518::R`](R) reader structure"] +impl crate::Readable for TBFT1518_SPEC {} #[doc = "`reset()` method sets TBFT1518 to value 0"] impl crate::Resettable for TBFT1518_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbft255.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbft255.rs index 8c2905be..c433c153 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbft255.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbft255.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFT255` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - 128 to 255 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "128 to 255 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbft255](index.html) module"] +#[doc = "128 to 255 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft255::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFT255_SPEC; impl crate::RegisterSpec for TBFT255_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbft255::R](R) reader structure"] -impl crate::Readable for TBFT255_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbft255::R`](R) reader structure"] +impl crate::Readable for TBFT255_SPEC {} #[doc = "`reset()` method sets TBFT255 to value 0"] impl crate::Resettable for TBFT255_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbft511.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbft511.rs index 1c2f89c8..6dc8d65a 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbft511.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbft511.rs @@ -1,18 +1,5 @@ #[doc = "Register `TBFT511` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFTX` reader - 256 to 511 Byte Frames Transmitted without Error"] pub type NFTX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFTX_R::new(self.bits) } } -#[doc = "256 to 511 Byte Frames Transmitted Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbft511](index.html) module"] +#[doc = "256 to 511 Byte Frames Transmitted Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbft511::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBFT511_SPEC; impl crate::RegisterSpec for TBFT511_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbft511::R](R) reader structure"] -impl crate::Readable for TBFT511_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tbft511::R`](R) reader structure"] +impl crate::Readable for TBFT511_SPEC {} #[doc = "`reset()` method sets TBFT511 to value 0"] impl crate::Resettable for TBFT511_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbqb.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbqb.rs index 19cd206a..32fd979f 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbqb.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbqb.rs @@ -1,43 +1,11 @@ #[doc = "Register `TBQB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TBQB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Transmit Buffer Queue Base Address"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Transmit Buffer Queue Base Address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, TBQB_SPEC, 30, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Transmit Buffer Queue Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Transmit Buffer Queue Base Address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<2> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Queue Base Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbqb](index.html) module"] +#[doc = "Transmit Buffer Queue Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbqb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tbqb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBQB_SPEC; impl crate::RegisterSpec for TBQB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbqb::R](R) reader structure"] -impl crate::Readable for TBQB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tbqb::W](W) writer structure"] +#[doc = "`read()` method returns [`tbqb::R`](R) reader structure"] +impl crate::Readable for TBQB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tbqb::W`](W) writer structure"] impl crate::Writable for TBQB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tbqbapq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tbqbapq.rs index 33e4b0e5..792d7adb 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tbqbapq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tbqbapq.rs @@ -1,43 +1,11 @@ #[doc = "Register `TBQBAPQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TBQBAPQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXBQBA` reader - Transmit Buffer Queue Base Address"] pub type TXBQBA_R = crate::FieldReader; #[doc = "Field `TXBQBA` writer - Transmit Buffer Queue Base Address"] -pub type TXBQBA_W<'a, const O: u8> = crate::FieldWriter<'a, TBQBAPQ_SPEC, 30, O, u32>; +pub type TXBQBA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Transmit Buffer Queue Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Transmit Buffer Queue Base Address"] #[inline(always)] #[must_use] - pub fn txbqba(&mut self) -> TXBQBA_W<2> { + pub fn txbqba(&mut self) -> TXBQBA_W { TXBQBA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Queue Base Address Register Priority Queue (1..5)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tbqbapq](index.html) module"] +#[doc = "Transmit Buffer Queue Base Address Register Priority Queue (1..5)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tbqbapq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tbqbapq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TBQBAPQ_SPEC; impl crate::RegisterSpec for TBQBAPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tbqbapq::R](R) reader structure"] -impl crate::Readable for TBQBAPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tbqbapq::W](W) writer structure"] +#[doc = "`read()` method returns [`tbqbapq::R`](R) reader structure"] +impl crate::Readable for TBQBAPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tbqbapq::W`](W) writer structure"] impl crate::Writable for TBQBAPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tce.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tce.rs index bcaf52ec..bf2ad94a 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tce.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tce.rs @@ -1,18 +1,5 @@ #[doc = "Register `TCE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TCKER` reader - TCP Checksum Errors"] pub type TCKER_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { TCKER_R::new((self.bits & 0xff) as u8) } } -#[doc = "TCP Checksum Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tce](index.html) module"] +#[doc = "TCP Checksum Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tce::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TCE_SPEC; impl crate::RegisterSpec for TCE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tce::R](R) reader structure"] -impl crate::Readable for TCE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tce::R`](R) reader structure"] +impl crate::Readable for TCE_SPEC {} #[doc = "`reset()` method sets TCE to value 0"] impl crate::Resettable for TCE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ti.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ti.rs index 8ac278bc..50d02738 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ti.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ti.rs @@ -1,51 +1,19 @@ #[doc = "Register `TI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TI` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CNS` reader - Count Nanoseconds"] pub type CNS_R = crate::FieldReader; #[doc = "Field `CNS` writer - Count Nanoseconds"] -pub type CNS_W<'a, const O: u8> = crate::FieldWriter<'a, TI_SPEC, 8, O>; +pub type CNS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `ACNS` reader - Alternative Count Nanoseconds"] pub type ACNS_R = crate::FieldReader; #[doc = "Field `ACNS` writer - Alternative Count Nanoseconds"] -pub type ACNS_W<'a, const O: u8> = crate::FieldWriter<'a, TI_SPEC, 8, O>; +pub type ACNS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `NIT` reader - Number of Increments"] pub type NIT_R = crate::FieldReader; #[doc = "Field `NIT` writer - Number of Increments"] -pub type NIT_W<'a, const O: u8> = crate::FieldWriter<'a, TI_SPEC, 8, O>; +pub type NIT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Count Nanoseconds"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bits 0:7 - Count Nanoseconds"] #[inline(always)] #[must_use] - pub fn cns(&mut self) -> CNS_W<0> { + pub fn cns(&mut self) -> CNS_W { CNS_W::new(self) } #[doc = "Bits 8:15 - Alternative Count Nanoseconds"] #[inline(always)] #[must_use] - pub fn acns(&mut self) -> ACNS_W<8> { + pub fn acns(&mut self) -> ACNS_W { ACNS_W::new(self) } #[doc = "Bits 16:23 - Number of Increments"] #[inline(always)] #[must_use] - pub fn nit(&mut self) -> NIT_W<16> { + pub fn nit(&mut self) -> NIT_W { NIT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Increment Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ti](index.html) module"] +#[doc = "1588 Timer Increment Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ti::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ti::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TI_SPEC; impl crate::RegisterSpec for TI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ti::R](R) reader structure"] -impl crate::Readable for TI_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ti::W](W) writer structure"] +#[doc = "`read()` method returns [`ti::R`](R) reader structure"] +impl crate::Readable for TI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ti::W`](W) writer structure"] impl crate::Writable for TI_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tidm1.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tidm1.rs index 9844b507..8ab149f7 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tidm1.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tidm1.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIDM1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIDM1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TID` reader - Type ID Match 1"] pub type TID_R = crate::FieldReader; #[doc = "Field `TID` writer - Type ID Match 1"] -pub type TID_W<'a, const O: u8> = crate::FieldWriter<'a, TIDM1_SPEC, 16, O, u16>; +pub type TID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `ENID1` reader - Enable Copying of TID Matched Frames"] pub type ENID1_R = crate::BitReader; #[doc = "Field `ENID1` writer - Enable Copying of TID Matched Frames"] -pub type ENID1_W<'a, const O: u8> = crate::BitWriter<'a, TIDM1_SPEC, O>; +pub type ENID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - Type ID Match 1"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Type ID Match 1"] #[inline(always)] #[must_use] - pub fn tid(&mut self) -> TID_W<0> { + pub fn tid(&mut self) -> TID_W { TID_W::new(self) } #[doc = "Bit 31 - Enable Copying of TID Matched Frames"] #[inline(always)] #[must_use] - pub fn enid1(&mut self) -> ENID1_W<31> { + pub fn enid1(&mut self) -> ENID1_W { ENID1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Type ID Match 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tidm1](index.html) module"] +#[doc = "Type ID Match 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIDM1_SPEC; impl crate::RegisterSpec for TIDM1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tidm1::R](R) reader structure"] -impl crate::Readable for TIDM1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tidm1::W](W) writer structure"] +#[doc = "`read()` method returns [`tidm1::R`](R) reader structure"] +impl crate::Readable for TIDM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tidm1::W`](W) writer structure"] impl crate::Writable for TIDM1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tidm2.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tidm2.rs index 4335e7d4..c73e9a38 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tidm2.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tidm2.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIDM2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIDM2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TID` reader - Type ID Match 2"] pub type TID_R = crate::FieldReader; #[doc = "Field `TID` writer - Type ID Match 2"] -pub type TID_W<'a, const O: u8> = crate::FieldWriter<'a, TIDM2_SPEC, 16, O, u16>; +pub type TID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `ENID2` reader - Enable Copying of TID Matched Frames"] pub type ENID2_R = crate::BitReader; #[doc = "Field `ENID2` writer - Enable Copying of TID Matched Frames"] -pub type ENID2_W<'a, const O: u8> = crate::BitWriter<'a, TIDM2_SPEC, O>; +pub type ENID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - Type ID Match 2"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Type ID Match 2"] #[inline(always)] #[must_use] - pub fn tid(&mut self) -> TID_W<0> { + pub fn tid(&mut self) -> TID_W { TID_W::new(self) } #[doc = "Bit 31 - Enable Copying of TID Matched Frames"] #[inline(always)] #[must_use] - pub fn enid2(&mut self) -> ENID2_W<31> { + pub fn enid2(&mut self) -> ENID2_W { ENID2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Type ID Match 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tidm2](index.html) module"] +#[doc = "Type ID Match 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIDM2_SPEC; impl crate::RegisterSpec for TIDM2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tidm2::R](R) reader structure"] -impl crate::Readable for TIDM2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tidm2::W](W) writer structure"] +#[doc = "`read()` method returns [`tidm2::R`](R) reader structure"] +impl crate::Readable for TIDM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tidm2::W`](W) writer structure"] impl crate::Writable for TIDM2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tidm3.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tidm3.rs index aeb6dd1c..d88d28ff 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tidm3.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tidm3.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIDM3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIDM3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TID` reader - Type ID Match 3"] pub type TID_R = crate::FieldReader; #[doc = "Field `TID` writer - Type ID Match 3"] -pub type TID_W<'a, const O: u8> = crate::FieldWriter<'a, TIDM3_SPEC, 16, O, u16>; +pub type TID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `ENID3` reader - Enable Copying of TID Matched Frames"] pub type ENID3_R = crate::BitReader; #[doc = "Field `ENID3` writer - Enable Copying of TID Matched Frames"] -pub type ENID3_W<'a, const O: u8> = crate::BitWriter<'a, TIDM3_SPEC, O>; +pub type ENID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - Type ID Match 3"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Type ID Match 3"] #[inline(always)] #[must_use] - pub fn tid(&mut self) -> TID_W<0> { + pub fn tid(&mut self) -> TID_W { TID_W::new(self) } #[doc = "Bit 31 - Enable Copying of TID Matched Frames"] #[inline(always)] #[must_use] - pub fn enid3(&mut self) -> ENID3_W<31> { + pub fn enid3(&mut self) -> ENID3_W { ENID3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Type ID Match 3 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tidm3](index.html) module"] +#[doc = "Type ID Match 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIDM3_SPEC; impl crate::RegisterSpec for TIDM3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tidm3::R](R) reader structure"] -impl crate::Readable for TIDM3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tidm3::W](W) writer structure"] +#[doc = "`read()` method returns [`tidm3::R`](R) reader structure"] +impl crate::Readable for TIDM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tidm3::W`](W) writer structure"] impl crate::Writable for TIDM3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tidm4.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tidm4.rs index 9f8b60a6..c3664408 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tidm4.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tidm4.rs @@ -1,47 +1,15 @@ #[doc = "Register `TIDM4` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIDM4` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TID` reader - Type ID Match 4"] pub type TID_R = crate::FieldReader; #[doc = "Field `TID` writer - Type ID Match 4"] -pub type TID_W<'a, const O: u8> = crate::FieldWriter<'a, TIDM4_SPEC, 16, O, u16>; +pub type TID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `ENID4` reader - Enable Copying of TID Matched Frames"] pub type ENID4_R = crate::BitReader; #[doc = "Field `ENID4` writer - Enable Copying of TID Matched Frames"] -pub type ENID4_W<'a, const O: u8> = crate::BitWriter<'a, TIDM4_SPEC, O>; +pub type ENID4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - Type ID Match 4"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Type ID Match 4"] #[inline(always)] #[must_use] - pub fn tid(&mut self) -> TID_W<0> { + pub fn tid(&mut self) -> TID_W { TID_W::new(self) } #[doc = "Bit 31 - Enable Copying of TID Matched Frames"] #[inline(always)] #[must_use] - pub fn enid4(&mut self) -> ENID4_W<31> { + pub fn enid4(&mut self) -> ENID4_W { ENID4_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Type ID Match 4 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tidm4](index.html) module"] +#[doc = "Type ID Match 4 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tidm4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tidm4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIDM4_SPEC; impl crate::RegisterSpec for TIDM4_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tidm4::R](R) reader structure"] -impl crate::Readable for TIDM4_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tidm4::W](W) writer structure"] +#[doc = "`read()` method returns [`tidm4::R`](R) reader structure"] +impl crate::Readable for TIDM4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tidm4::W`](W) writer structure"] impl crate::Writable for TIDM4_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tisubn.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tisubn.rs index f318dec9..c4672a0b 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tisubn.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tisubn.rs @@ -1,43 +1,11 @@ #[doc = "Register `TISUBN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TISUBN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LSBTIR` reader - Lower Significant Bits of Timer Increment Register"] pub type LSBTIR_R = crate::FieldReader; #[doc = "Field `LSBTIR` writer - Lower Significant Bits of Timer Increment Register"] -pub type LSBTIR_W<'a, const O: u8> = crate::FieldWriter<'a, TISUBN_SPEC, 16, O, u16>; +pub type LSBTIR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Lower Significant Bits of Timer Increment Register"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Lower Significant Bits of Timer Increment Register"] #[inline(always)] #[must_use] - pub fn lsbtir(&mut self) -> LSBTIR_W<0> { + pub fn lsbtir(&mut self) -> LSBTIR_W { LSBTIR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Increment Sub-nanoseconds Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tisubn](index.html) module"] +#[doc = "1588 Timer Increment Sub-nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tisubn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tisubn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TISUBN_SPEC; impl crate::RegisterSpec for TISUBN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tisubn::R](R) reader structure"] -impl crate::Readable for TISUBN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tisubn::W](W) writer structure"] +#[doc = "`read()` method returns [`tisubn::R`](R) reader structure"] +impl crate::Readable for TISUBN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tisubn::W`](W) writer structure"] impl crate::Writable for TISUBN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tmxbfr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tmxbfr.rs index 2f4bced2..3beb46cd 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tmxbfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tmxbfr.rs @@ -1,18 +1,5 @@ #[doc = "Register `TMXBFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NFRX` reader - 1519 to Maximum Byte Frames Received without Error"] pub type NFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NFRX_R::new(self.bits) } } -#[doc = "1519 to Maximum Byte Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tmxbfr](index.html) module"] +#[doc = "1519 to Maximum Byte Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmxbfr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TMXBFR_SPEC; impl crate::RegisterSpec for TMXBFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tmxbfr::R](R) reader structure"] -impl crate::Readable for TMXBFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tmxbfr::R`](R) reader structure"] +impl crate::Readable for TMXBFR_SPEC {} #[doc = "`reset()` method sets TMXBFR to value 0"] impl crate::Resettable for TMXBFR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tn.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tn.rs index 94aaee31..40b5aeec 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tn.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tn.rs @@ -1,43 +1,11 @@ #[doc = "Register `TN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TNS` reader - Timer Count in Nanoseconds"] pub type TNS_R = crate::FieldReader; #[doc = "Field `TNS` writer - Timer Count in Nanoseconds"] -pub type TNS_W<'a, const O: u8> = crate::FieldWriter<'a, TN_SPEC, 30, O, u32>; +pub type TNS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 0:29 - Timer Count in Nanoseconds"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:29 - Timer Count in Nanoseconds"] #[inline(always)] #[must_use] - pub fn tns(&mut self) -> TNS_W<0> { + pub fn tns(&mut self) -> TNS_W { TNS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Nanoseconds Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tn](index.html) module"] +#[doc = "1588 Timer Nanoseconds Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tn::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TN_SPEC; impl crate::RegisterSpec for TN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tn::R](R) reader structure"] -impl crate::Readable for TN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tn::W](W) writer structure"] +#[doc = "`read()` method returns [`tn::R`](R) reader structure"] +impl crate::Readable for TN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tn::W`](W) writer structure"] impl crate::Writable for TN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tpfcp.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tpfcp.rs index bfd88f03..f8fd5fc5 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tpfcp.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tpfcp.rs @@ -1,47 +1,15 @@ #[doc = "Register `TPFCP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TPFCP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PEV` reader - Priority Enable Vector"] pub type PEV_R = crate::FieldReader; #[doc = "Field `PEV` writer - Priority Enable Vector"] -pub type PEV_W<'a, const O: u8> = crate::FieldWriter<'a, TPFCP_SPEC, 8, O>; +pub type PEV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PQ` reader - Pause Quantum"] pub type PQ_R = crate::FieldReader; #[doc = "Field `PQ` writer - Pause Quantum"] -pub type PQ_W<'a, const O: u8> = crate::FieldWriter<'a, TPFCP_SPEC, 8, O>; +pub type PQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Priority Enable Vector"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:7 - Priority Enable Vector"] #[inline(always)] #[must_use] - pub fn pev(&mut self) -> PEV_W<0> { + pub fn pev(&mut self) -> PEV_W { PEV_W::new(self) } #[doc = "Bits 8:15 - Pause Quantum"] #[inline(always)] #[must_use] - pub fn pq(&mut self) -> PQ_W<8> { + pub fn pq(&mut self) -> PQ_W { PQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit PFC Pause Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tpfcp](index.html) module"] +#[doc = "Transmit PFC Pause Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpfcp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpfcp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TPFCP_SPEC; impl crate::RegisterSpec for TPFCP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tpfcp::R](R) reader structure"] -impl crate::Readable for TPFCP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tpfcp::W](W) writer structure"] +#[doc = "`read()` method returns [`tpfcp::R`](R) reader structure"] +impl crate::Readable for TPFCP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tpfcp::W`](W) writer structure"] impl crate::Writable for TPFCP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tpq.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tpq.rs index 2ee835a6..da0864f9 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tpq.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tpq.rs @@ -1,43 +1,11 @@ #[doc = "Register `TPQ` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TPQ` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TPQ` reader - Transmit Pause Quantum"] pub type TPQ_R = crate::FieldReader; #[doc = "Field `TPQ` writer - Transmit Pause Quantum"] -pub type TPQ_W<'a, const O: u8> = crate::FieldWriter<'a, TPQ_SPEC, 16, O, u16>; +pub type TPQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Transmit Pause Quantum"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Transmit Pause Quantum"] #[inline(always)] #[must_use] - pub fn tpq(&mut self) -> TPQ_W<0> { + pub fn tpq(&mut self) -> TPQ_W { TPQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Pause Quantum Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tpq](index.html) module"] +#[doc = "Transmit Pause Quantum Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TPQ_SPEC; impl crate::RegisterSpec for TPQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tpq::R](R) reader structure"] -impl crate::Readable for TPQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tpq::W](W) writer structure"] +#[doc = "`read()` method returns [`tpq::R`](R) reader structure"] +impl crate::Readable for TPQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tpq::W`](W) writer structure"] impl crate::Writable for TPQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tpsf.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tpsf.rs index c8a8499a..a9aaaa3a 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tpsf.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tpsf.rs @@ -1,47 +1,15 @@ #[doc = "Register `TPSF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TPSF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TPB1ADR` reader - Transmit Partial Store and Forward Address"] pub type TPB1ADR_R = crate::FieldReader; #[doc = "Field `TPB1ADR` writer - Transmit Partial Store and Forward Address"] -pub type TPB1ADR_W<'a, const O: u8> = crate::FieldWriter<'a, TPSF_SPEC, 12, O, u16>; +pub type TPB1ADR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `ENTXP` reader - Enable TX Partial Store and Forward Operation"] pub type ENTXP_R = crate::BitReader; #[doc = "Field `ENTXP` writer - Enable TX Partial Store and Forward Operation"] -pub type ENTXP_W<'a, const O: u8> = crate::BitWriter<'a, TPSF_SPEC, O>; +pub type ENTXP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:11 - Transmit Partial Store and Forward Address"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:11 - Transmit Partial Store and Forward Address"] #[inline(always)] #[must_use] - pub fn tpb1adr(&mut self) -> TPB1ADR_W<0> { + pub fn tpb1adr(&mut self) -> TPB1ADR_W { TPB1ADR_W::new(self) } #[doc = "Bit 31 - Enable TX Partial Store and Forward Operation"] #[inline(always)] #[must_use] - pub fn entxp(&mut self) -> ENTXP_W<31> { + pub fn entxp(&mut self) -> ENTXP_W { ENTXP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "TX Partial Store and Forward Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tpsf](index.html) module"] +#[doc = "TX Partial Store and Forward Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpsf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpsf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TPSF_SPEC; impl crate::RegisterSpec for TPSF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tpsf::R](R) reader structure"] -impl crate::Readable for TPSF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tpsf::W](W) writer structure"] +#[doc = "`read()` method returns [`tpsf::R`](R) reader structure"] +impl crate::Readable for TPSF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tpsf::W`](W) writer structure"] impl crate::Writable for TPSF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tsh.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tsh.rs index bdf20b29..0953c48a 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tsh.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tsh.rs @@ -1,43 +1,11 @@ #[doc = "Register `TSH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TCS` reader - Timer Count in Seconds"] pub type TCS_R = crate::FieldReader; #[doc = "Field `TCS` writer - Timer Count in Seconds"] -pub type TCS_W<'a, const O: u8> = crate::FieldWriter<'a, TSH_SPEC, 16, O, u16>; +pub type TCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Timer Count in Seconds"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Timer Count in Seconds"] #[inline(always)] #[must_use] - pub fn tcs(&mut self) -> TCS_W<0> { + pub fn tcs(&mut self) -> TCS_W { TCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Seconds High Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsh](index.html) module"] +#[doc = "1588 Timer Seconds High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsh::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSH_SPEC; impl crate::RegisterSpec for TSH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tsh::R](R) reader structure"] -impl crate::Readable for TSH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tsh::W](W) writer structure"] +#[doc = "`read()` method returns [`tsh::R`](R) reader structure"] +impl crate::Readable for TSH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tsh::W`](W) writer structure"] impl crate::Writable for TSH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tsl.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tsl.rs index 19834ac6..431f7e03 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tsl.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tsl.rs @@ -1,43 +1,11 @@ #[doc = "Register `TSL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TCS` reader - Timer Count in Seconds"] pub type TCS_R = crate::FieldReader; #[doc = "Field `TCS` writer - Timer Count in Seconds"] -pub type TCS_W<'a, const O: u8> = crate::FieldWriter<'a, TSL_SPEC, 32, O, u32>; +pub type TCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Timer Count in Seconds"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Timer Count in Seconds"] #[inline(always)] #[must_use] - pub fn tcs(&mut self) -> TCS_W<0> { + pub fn tcs(&mut self) -> TCS_W { TCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "1588 Timer Seconds Low Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsl](index.html) module"] +#[doc = "1588 Timer Seconds Low Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSL_SPEC; impl crate::RegisterSpec for TSL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tsl::R](R) reader structure"] -impl crate::Readable for TSL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tsl::W](W) writer structure"] +#[doc = "`read()` method returns [`tsl::R`](R) reader structure"] +impl crate::Readable for TSL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tsl::W`](W) writer structure"] impl crate::Writable for TSL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tsr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tsr.rs index 08e587d9..867d8306 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tsr.rs @@ -1,67 +1,35 @@ #[doc = "Register `TSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UBR` reader - Used Bit Read"] pub type UBR_R = crate::BitReader; #[doc = "Field `UBR` writer - Used Bit Read"] -pub type UBR_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type UBR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COL` reader - Collision Occurred"] pub type COL_R = crate::BitReader; #[doc = "Field `COL` writer - Collision Occurred"] -pub type COL_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type COL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RLE` reader - Retry Limit Exceeded"] pub type RLE_R = crate::BitReader; #[doc = "Field `RLE` writer - Retry Limit Exceeded"] -pub type RLE_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type RLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXGO` reader - Transmit Go"] pub type TXGO_R = crate::BitReader; #[doc = "Field `TXGO` writer - Transmit Go"] -pub type TXGO_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type TXGO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFC` reader - Transmit Frame Corruption Due to AHB Error"] pub type TFC_R = crate::BitReader; #[doc = "Field `TFC` writer - Transmit Frame Corruption Due to AHB Error"] -pub type TFC_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type TFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXCOMP` reader - Transmit Complete"] pub type TXCOMP_R = crate::BitReader; #[doc = "Field `TXCOMP` writer - Transmit Complete"] -pub type TXCOMP_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type TXCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HRESP` reader - HRESP Not OK"] pub type HRESP_R = crate::BitReader; #[doc = "Field `HRESP` writer - HRESP Not OK"] -pub type HRESP_W<'a, const O: u8> = crate::BitWriter<'a, TSR_SPEC, O>; +pub type HRESP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Used Bit Read"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bit 0 - Used Bit Read"] #[inline(always)] #[must_use] - pub fn ubr(&mut self) -> UBR_W<0> { + pub fn ubr(&mut self) -> UBR_W { UBR_W::new(self) } #[doc = "Bit 1 - Collision Occurred"] #[inline(always)] #[must_use] - pub fn col(&mut self) -> COL_W<1> { + pub fn col(&mut self) -> COL_W { COL_W::new(self) } #[doc = "Bit 2 - Retry Limit Exceeded"] #[inline(always)] #[must_use] - pub fn rle(&mut self) -> RLE_W<2> { + pub fn rle(&mut self) -> RLE_W { RLE_W::new(self) } #[doc = "Bit 3 - Transmit Go"] #[inline(always)] #[must_use] - pub fn txgo(&mut self) -> TXGO_W<3> { + pub fn txgo(&mut self) -> TXGO_W { TXGO_W::new(self) } #[doc = "Bit 4 - Transmit Frame Corruption Due to AHB Error"] #[inline(always)] #[must_use] - pub fn tfc(&mut self) -> TFC_W<4> { + pub fn tfc(&mut self) -> TFC_W { TFC_W::new(self) } #[doc = "Bit 5 - Transmit Complete"] #[inline(always)] #[must_use] - pub fn txcomp(&mut self) -> TXCOMP_W<5> { + pub fn txcomp(&mut self) -> TXCOMP_W { TXCOMP_W::new(self) } #[doc = "Bit 8 - HRESP Not OK"] #[inline(always)] #[must_use] - pub fn hresp(&mut self) -> HRESP_W<8> { + pub fn hresp(&mut self) -> HRESP_W { HRESP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tsr](index.html) module"] +#[doc = "Transmit Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSR_SPEC; impl crate::RegisterSpec for TSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tsr::R](R) reader structure"] -impl crate::Readable for TSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tsr::W](W) writer structure"] +#[doc = "`read()` method returns [`tsr::R`](R) reader structure"] +impl crate::Readable for TSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tsr::W`](W) writer structure"] impl crate::Writable for TSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/tur.rs b/arch/cortex-m/samv71q21-pac/src/gmac/tur.rs index b1d7544e..688f504f 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/tur.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/tur.rs @@ -1,18 +1,5 @@ #[doc = "Register `TUR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXUNR` reader - Transmit Underruns"] pub type TXUNR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { TXUNR_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Transmit Underruns Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tur](index.html) module"] +#[doc = "Transmit Underruns Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tur::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TUR_SPEC; impl crate::RegisterSpec for TUR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tur::R](R) reader structure"] -impl crate::Readable for TUR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`tur::R`](R) reader structure"] +impl crate::Readable for TUR_SPEC {} #[doc = "`reset()` method sets TUR to value 0"] impl crate::Resettable for TUR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/txlpi.rs b/arch/cortex-m/samv71q21-pac/src/gmac/txlpi.rs index 34e99b9d..34500548 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/txlpi.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/txlpi.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXLPI` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `COUNT` reader - Count of LPI transitions (cleared on read)"] pub type COUNT_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { COUNT_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Transmit LPI Transitions\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txlpi](index.html) module"] +#[doc = "Transmit LPI Transitions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlpi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXLPI_SPEC; impl crate::RegisterSpec for TXLPI_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txlpi::R](R) reader structure"] -impl crate::Readable for TXLPI_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txlpi::R`](R) reader structure"] +impl crate::Readable for TXLPI_SPEC {} #[doc = "`reset()` method sets TXLPI to value 0"] impl crate::Resettable for TXLPI_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/txlpitime.rs b/arch/cortex-m/samv71q21-pac/src/gmac/txlpitime.rs index 555c1800..f0bd47ff 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/txlpitime.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/txlpitime.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXLPITIME` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LPITIME` reader - Time in LPI (cleared on read)"] pub type LPITIME_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { LPITIME_R::new(self.bits & 0x00ff_ffff) } } -#[doc = "Transmit LPI Time\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txlpitime](index.html) module"] +#[doc = "Transmit LPI Time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlpitime::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXLPITIME_SPEC; impl crate::RegisterSpec for TXLPITIME_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txlpitime::R](R) reader structure"] -impl crate::Readable for TXLPITIME_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txlpitime::R`](R) reader structure"] +impl crate::Readable for TXLPITIME_SPEC {} #[doc = "`reset()` method sets TXLPITIME to value 0"] impl crate::Resettable for TXLPITIME_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/uce.rs b/arch/cortex-m/samv71q21-pac/src/gmac/uce.rs index 87c1d5fc..ba017831 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/uce.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/uce.rs @@ -1,18 +1,5 @@ #[doc = "Register `UCE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UCKER` reader - UDP Checksum Errors"] pub type UCKER_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { UCKER_R::new((self.bits & 0xff) as u8) } } -#[doc = "UDP Checksum Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uce](index.html) module"] +#[doc = "UDP Checksum Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uce::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UCE_SPEC; impl crate::RegisterSpec for UCE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uce::R](R) reader structure"] -impl crate::Readable for UCE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uce::R`](R) reader structure"] +impl crate::Readable for UCE_SPEC {} #[doc = "`reset()` method sets UCE to value 0"] impl crate::Resettable for UCE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ufr.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ufr.rs index 4d2f5069..a2e4df79 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ufr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ufr.rs @@ -1,18 +1,5 @@ #[doc = "Register `UFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `UFRX` reader - Undersize Frames Received"] pub type UFRX_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { UFRX_R::new((self.bits & 0x03ff) as u16) } } -#[doc = "Undersize Frames Received Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ufr](index.html) module"] +#[doc = "Undersize Frames Received Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ufr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UFR_SPEC; impl crate::RegisterSpec for UFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ufr::R](R) reader structure"] -impl crate::Readable for UFR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ufr::R`](R) reader structure"] +impl crate::Readable for UFR_SPEC {} #[doc = "`reset()` method sets UFR to value 0"] impl crate::Resettable for UFR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/ur.rs b/arch/cortex-m/samv71q21-pac/src/gmac/ur.rs index e0740f6b..b6b7d167 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/ur.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/ur.rs @@ -1,43 +1,11 @@ #[doc = "Register `UR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `UR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RMII` reader - Reduced MII Mode"] pub type RMII_R = crate::BitReader; #[doc = "Field `RMII` writer - Reduced MII Mode"] -pub type RMII_W<'a, const O: u8> = crate::BitWriter<'a, UR_SPEC, O>; +pub type RMII_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Reduced MII Mode"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bit 0 - Reduced MII Mode"] #[inline(always)] #[must_use] - pub fn rmii(&mut self) -> RMII_W<0> { + pub fn rmii(&mut self) -> RMII_W { RMII_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "User Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ur](index.html) module"] +#[doc = "User Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ur::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ur::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UR_SPEC; impl crate::RegisterSpec for UR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ur::R](R) reader structure"] -impl crate::Readable for UR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ur::W](W) writer structure"] +#[doc = "`read()` method returns [`ur::R`](R) reader structure"] +impl crate::Readable for UR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ur::W`](W) writer structure"] impl crate::Writable for UR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gmac/wol.rs b/arch/cortex-m/samv71q21-pac/src/gmac/wol.rs index 5bf4a367..68614065 100644 --- a/arch/cortex-m/samv71q21-pac/src/gmac/wol.rs +++ b/arch/cortex-m/samv71q21-pac/src/gmac/wol.rs @@ -1,59 +1,27 @@ #[doc = "Register `WOL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WOL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IP` reader - ARP Request IP Address"] pub type IP_R = crate::FieldReader; #[doc = "Field `IP` writer - ARP Request IP Address"] -pub type IP_W<'a, const O: u8> = crate::FieldWriter<'a, WOL_SPEC, 16, O, u16>; +pub type IP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `MAG` reader - Magic Packet Event Enable"] pub type MAG_R = crate::BitReader; #[doc = "Field `MAG` writer - Magic Packet Event Enable"] -pub type MAG_W<'a, const O: u8> = crate::BitWriter<'a, WOL_SPEC, O>; +pub type MAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARP` reader - ARP Request IP Address"] pub type ARP_R = crate::BitReader; #[doc = "Field `ARP` writer - ARP Request IP Address"] -pub type ARP_W<'a, const O: u8> = crate::BitWriter<'a, WOL_SPEC, O>; +pub type ARP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SA1` reader - Specific Address Register 1 Event Enable"] pub type SA1_R = crate::BitReader; #[doc = "Field `SA1` writer - Specific Address Register 1 Event Enable"] -pub type SA1_W<'a, const O: u8> = crate::BitWriter<'a, WOL_SPEC, O>; +pub type SA1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MTI` reader - Multicast Hash Event Enable"] pub type MTI_R = crate::BitReader; #[doc = "Field `MTI` writer - Multicast Hash Event Enable"] -pub type MTI_W<'a, const O: u8> = crate::BitWriter<'a, WOL_SPEC, O>; +pub type MTI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - ARP Request IP Address"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bits 0:15 - ARP Request IP Address"] #[inline(always)] #[must_use] - pub fn ip(&mut self) -> IP_W<0> { + pub fn ip(&mut self) -> IP_W { IP_W::new(self) } #[doc = "Bit 16 - Magic Packet Event Enable"] #[inline(always)] #[must_use] - pub fn mag(&mut self) -> MAG_W<16> { + pub fn mag(&mut self) -> MAG_W { MAG_W::new(self) } #[doc = "Bit 17 - ARP Request IP Address"] #[inline(always)] #[must_use] - pub fn arp(&mut self) -> ARP_W<17> { + pub fn arp(&mut self) -> ARP_W { ARP_W::new(self) } #[doc = "Bit 18 - Specific Address Register 1 Event Enable"] #[inline(always)] #[must_use] - pub fn sa1(&mut self) -> SA1_W<18> { + pub fn sa1(&mut self) -> SA1_W { SA1_W::new(self) } #[doc = "Bit 19 - Multicast Hash Event Enable"] #[inline(always)] #[must_use] - pub fn mti(&mut self) -> MTI_W<19> { + pub fn mti(&mut self) -> MTI_W { MTI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Wake on LAN Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wol](index.html) module"] +#[doc = "Wake on LAN Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WOL_SPEC; impl crate::RegisterSpec for WOL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wol::R](R) reader structure"] -impl crate::Readable for WOL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wol::W](W) writer structure"] +#[doc = "`read()` method returns [`wol::R`](R) reader structure"] +impl crate::Readable for WOL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wol::W`](W) writer structure"] impl crate::Writable for WOL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/gpbr.rs b/arch/cortex-m/samv71q21-pac/src/gpbr.rs index 903b91d4..6d019f22 100644 --- a/arch/cortex-m/samv71q21-pac/src/gpbr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gpbr.rs @@ -4,7 +4,8 @@ pub struct RegisterBlock { #[doc = "0x00..0x20 - General Purpose Backup Register 0"] pub sys_gpbr: [SYS_GPBR; 8], } -#[doc = "SYS_GPBR (rw) register accessor: an alias for `Reg`"] +#[doc = "SYS_GPBR (rw) register accessor: General Purpose Backup Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_gpbr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_gpbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sys_gpbr`] +module"] pub type SYS_GPBR = crate::Reg; #[doc = "General Purpose Backup Register 0"] pub mod sys_gpbr; diff --git a/arch/cortex-m/samv71q21-pac/src/gpbr/sys_gpbr.rs b/arch/cortex-m/samv71q21-pac/src/gpbr/sys_gpbr.rs index e080e786..fe4050f8 100644 --- a/arch/cortex-m/samv71q21-pac/src/gpbr/sys_gpbr.rs +++ b/arch/cortex-m/samv71q21-pac/src/gpbr/sys_gpbr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SYS_GPBR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SYS_GPBR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GPBR_VALUE` reader - Value of GPBR x"] pub type GPBR_VALUE_R = crate::FieldReader; #[doc = "Field `GPBR_VALUE` writer - Value of GPBR x"] -pub type GPBR_VALUE_W<'a, const O: u8> = crate::FieldWriter<'a, SYS_GPBR_SPEC, 32, O, u32>; +pub type GPBR_VALUE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Value of GPBR x"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Value of GPBR x"] #[inline(always)] #[must_use] - pub fn gpbr_value(&mut self) -> GPBR_VALUE_W<0> { + pub fn gpbr_value(&mut self) -> GPBR_VALUE_W { GPBR_VALUE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "General Purpose Backup Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sys_gpbr](index.html) module"] +#[doc = "General Purpose Backup Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sys_gpbr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sys_gpbr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYS_GPBR_SPEC; impl crate::RegisterSpec for SYS_GPBR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sys_gpbr::R](R) reader structure"] -impl crate::Readable for SYS_GPBR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sys_gpbr::W](W) writer structure"] +#[doc = "`read()` method returns [`sys_gpbr::R`](R) reader structure"] +impl crate::Readable for SYS_GPBR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sys_gpbr::W`](W) writer structure"] impl crate::Writable for SYS_GPBR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci.rs b/arch/cortex-m/samv71q21-pac/src/hsmci.rs index 03b1f18a..d2e7deef 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci.rs @@ -45,83 +45,102 @@ pub struct RegisterBlock { #[doc = "0x200..0x600 - FIFO Memory Aperture0 0"] pub fifo: [FIFO; 256], } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "DTOR (rw) register accessor: an alias for `Reg`"] +#[doc = "DTOR (rw) register accessor: Data Timeout Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dtor`] +module"] pub type DTOR = crate::Reg; #[doc = "Data Timeout Register"] pub mod dtor; -#[doc = "SDCR (rw) register accessor: an alias for `Reg`"] +#[doc = "SDCR (rw) register accessor: SD/SDIO Card Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sdcr`] +module"] pub type SDCR = crate::Reg; #[doc = "SD/SDIO Card Register"] pub mod sdcr; -#[doc = "ARGR (rw) register accessor: an alias for `Reg`"] +#[doc = "ARGR (rw) register accessor: Argument Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`argr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`argr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`argr`] +module"] pub type ARGR = crate::Reg; #[doc = "Argument Register"] pub mod argr; -#[doc = "CMDR (w) register accessor: an alias for `Reg`"] +#[doc = "CMDR (w) register accessor: Command Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmdr`] +module"] pub type CMDR = crate::Reg; #[doc = "Command Register"] pub mod cmdr; -#[doc = "BLKR (rw) register accessor: an alias for `Reg`"] +#[doc = "BLKR (rw) register accessor: Block Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blkr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blkr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`blkr`] +module"] pub type BLKR = crate::Reg; #[doc = "Block Register"] pub mod blkr; -#[doc = "CSTOR (rw) register accessor: an alias for `Reg`"] +#[doc = "CSTOR (rw) register accessor: Completion Signal Timeout Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cstor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cstor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cstor`] +module"] pub type CSTOR = crate::Reg; #[doc = "Completion Signal Timeout Register"] pub mod cstor; -#[doc = "RSPR (r) register accessor: an alias for `Reg`"] +#[doc = "RSPR (r) register accessor: Response Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rspr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rspr`] +module"] pub type RSPR = crate::Reg; #[doc = "Response Register 0"] pub mod rspr; -#[doc = "RDR (r) register accessor: an alias for `Reg`"] +#[doc = "RDR (r) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rdr`] +module"] pub type RDR = crate::Reg; #[doc = "Receive Data Register"] pub mod rdr; -#[doc = "TDR (w) register accessor: an alias for `Reg`"] +#[doc = "TDR (w) register accessor: Transmit Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tdr`] +module"] pub type TDR = crate::Reg; #[doc = "Transmit Data Register"] pub mod tdr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "DMA (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA (rw) register accessor: DMA Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma`] +module"] pub type DMA = crate::Reg; #[doc = "DMA Configuration Register"] pub mod dma; -#[doc = "CFG (rw) register accessor: an alias for `Reg`"] +#[doc = "CFG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub type CFG = crate::Reg; #[doc = "Configuration Register"] pub mod cfg; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; -#[doc = "FIFO (rw) register accessor: an alias for `Reg`"] +#[doc = "FIFO (rw) register accessor: FIFO Memory Aperture0 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fifo`] +module"] pub type FIFO = crate::Reg; #[doc = "FIFO Memory Aperture0 0"] pub mod fifo; diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/argr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/argr.rs index 86714baf..464a33cb 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/argr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/argr.rs @@ -1,43 +1,11 @@ #[doc = "Register `ARGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ARGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ARG` reader - Command Argument"] pub type ARG_R = crate::FieldReader; #[doc = "Field `ARG` writer - Command Argument"] -pub type ARG_W<'a, const O: u8> = crate::FieldWriter<'a, ARGR_SPEC, 32, O, u32>; +pub type ARG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Command Argument"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Command Argument"] #[inline(always)] #[must_use] - pub fn arg(&mut self) -> ARG_W<0> { + pub fn arg(&mut self) -> ARG_W { ARG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Argument Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [argr](index.html) module"] +#[doc = "Argument Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`argr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`argr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ARGR_SPEC; impl crate::RegisterSpec for ARGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [argr::R](R) reader structure"] -impl crate::Readable for ARGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [argr::W](W) writer structure"] +#[doc = "`read()` method returns [`argr::R`](R) reader structure"] +impl crate::Readable for ARGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`argr::W`](W) writer structure"] impl crate::Writable for ARGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/blkr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/blkr.rs index d60a376c..376ea2f2 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/blkr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/blkr.rs @@ -1,47 +1,15 @@ #[doc = "Register `BLKR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BLKR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BCNT` reader - MMC/SDIO Block Count - SDIO Byte Count"] pub type BCNT_R = crate::FieldReader; #[doc = "Field `BCNT` writer - MMC/SDIO Block Count - SDIO Byte Count"] -pub type BCNT_W<'a, const O: u8> = crate::FieldWriter<'a, BLKR_SPEC, 16, O, u16>; +pub type BCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `BLKLEN` reader - Data Block Length"] pub type BLKLEN_R = crate::FieldReader; #[doc = "Field `BLKLEN` writer - Data Block Length"] -pub type BLKLEN_W<'a, const O: u8> = crate::FieldWriter<'a, BLKR_SPEC, 16, O, u16>; +pub type BLKLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - MMC/SDIO Block Count - SDIO Byte Count"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - MMC/SDIO Block Count - SDIO Byte Count"] #[inline(always)] #[must_use] - pub fn bcnt(&mut self) -> BCNT_W<0> { + pub fn bcnt(&mut self) -> BCNT_W { BCNT_W::new(self) } #[doc = "Bits 16:31 - Data Block Length"] #[inline(always)] #[must_use] - pub fn blklen(&mut self) -> BLKLEN_W<16> { + pub fn blklen(&mut self) -> BLKLEN_W { BLKLEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Block Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [blkr](index.html) module"] +#[doc = "Block Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`blkr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`blkr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BLKR_SPEC; impl crate::RegisterSpec for BLKR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [blkr::R](R) reader structure"] -impl crate::Readable for BLKR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [blkr::W](W) writer structure"] +#[doc = "`read()` method returns [`blkr::R`](R) reader structure"] +impl crate::Readable for BLKR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`blkr::W`](W) writer structure"] impl crate::Writable for BLKR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/cfg.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/cfg.rs index fc178fba..46b44761 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/cfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/cfg.rs @@ -1,55 +1,23 @@ #[doc = "Register `CFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FIFOMODE` reader - HSMCI Internal FIFO control mode"] pub type FIFOMODE_R = crate::BitReader; #[doc = "Field `FIFOMODE` writer - HSMCI Internal FIFO control mode"] -pub type FIFOMODE_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type FIFOMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FERRCTRL` reader - Flow Error flag reset control mode"] pub type FERRCTRL_R = crate::BitReader; #[doc = "Field `FERRCTRL` writer - Flow Error flag reset control mode"] -pub type FERRCTRL_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type FERRCTRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSMODE` reader - High Speed Mode"] pub type HSMODE_R = crate::BitReader; #[doc = "Field `HSMODE` writer - High Speed Mode"] -pub type HSMODE_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type HSMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LSYNC` reader - Synchronize on the last block"] pub type LSYNC_R = crate::BitReader; #[doc = "Field `LSYNC` writer - Synchronize on the last block"] -pub type LSYNC_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type LSYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - HSMCI Internal FIFO control mode"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - HSMCI Internal FIFO control mode"] #[inline(always)] #[must_use] - pub fn fifomode(&mut self) -> FIFOMODE_W<0> { + pub fn fifomode(&mut self) -> FIFOMODE_W { FIFOMODE_W::new(self) } #[doc = "Bit 4 - Flow Error flag reset control mode"] #[inline(always)] #[must_use] - pub fn ferrctrl(&mut self) -> FERRCTRL_W<4> { + pub fn ferrctrl(&mut self) -> FERRCTRL_W { FERRCTRL_W::new(self) } #[doc = "Bit 8 - High Speed Mode"] #[inline(always)] #[must_use] - pub fn hsmode(&mut self) -> HSMODE_W<8> { + pub fn hsmode(&mut self) -> HSMODE_W { HSMODE_W::new(self) } #[doc = "Bit 12 - Synchronize on the last block"] #[inline(always)] #[must_use] - pub fn lsync(&mut self) -> LSYNC_W<12> { + pub fn lsync(&mut self) -> LSYNC_W { LSYNC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +#[doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC; impl crate::RegisterSpec for CFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cfg::R](R) reader structure"] -impl crate::Readable for CFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"] +#[doc = "`read()` method returns [`cfg::R`](R) reader structure"] +impl crate::Readable for CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate::Writable for CFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/cmdr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/cmdr.rs index 9224fd29..464458e5 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/cmdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/cmdr.rs @@ -1,26 +1,7 @@ #[doc = "Register `CMDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMDNB` writer - Command Number"] -pub type CMDNB_W<'a, const O: u8> = crate::FieldWriter<'a, CMDR_SPEC, 6, O>; +pub type CMDNB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Response Type\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -44,26 +25,30 @@ impl crate::FieldSpec for RSPTYPSELECT_AW { type Ux = u8; } #[doc = "Field `RSPTYP` writer - Response Type"] -pub type RSPTYP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CMDR_SPEC, 2, O, RSPTYPSELECT_AW>; -impl<'a, const O: u8> RSPTYP_W<'a, O> { +pub type RSPTYP_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RSPTYPSELECT_AW>; +impl<'a, REG, const O: u8> RSPTYP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No response"] #[inline(always)] - pub fn noresp(self) -> &'a mut W { + pub fn noresp(self) -> &'a mut crate::W { self.variant(RSPTYPSELECT_AW::NORESP) } #[doc = "48-bit response"] #[inline(always)] - pub fn _48_bit(self) -> &'a mut W { + pub fn _48_bit(self) -> &'a mut crate::W { self.variant(RSPTYPSELECT_AW::_48_BIT) } #[doc = "136-bit response"] #[inline(always)] - pub fn _136_bit(self) -> &'a mut W { + pub fn _136_bit(self) -> &'a mut crate::W { self.variant(RSPTYPSELECT_AW::_136_BIT) } #[doc = "R1b response type"] #[inline(always)] - pub fn r1b(self) -> &'a mut W { + pub fn r1b(self) -> &'a mut crate::W { self.variant(RSPTYPSELECT_AW::R1B) } } @@ -98,46 +83,50 @@ impl crate::FieldSpec for SPCMDSELECT_AW { type Ux = u8; } #[doc = "Field `SPCMD` writer - Special Command"] -pub type SPCMD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CMDR_SPEC, 3, O, SPCMDSELECT_AW>; -impl<'a, const O: u8> SPCMD_W<'a, O> { +pub type SPCMD_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, SPCMDSELECT_AW>; +impl<'a, REG, const O: u8> SPCMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Not a special CMD."] #[inline(always)] - pub fn std(self) -> &'a mut W { + pub fn std(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::STD) } #[doc = "Initialization CMD: 74 clock cycles for initialization sequence."] #[inline(always)] - pub fn init(self) -> &'a mut W { + pub fn init(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::INIT) } #[doc = "Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command."] #[inline(always)] - pub fn sync(self) -> &'a mut W { + pub fn sync(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::SYNC) } #[doc = "CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line."] #[inline(always)] - pub fn ce_ata(self) -> &'a mut W { + pub fn ce_ata(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::CE_ATA) } #[doc = "Interrupt command: Corresponds to the Interrupt Mode (CMD40)."] #[inline(always)] - pub fn it_cmd(self) -> &'a mut W { + pub fn it_cmd(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::IT_CMD) } #[doc = "Interrupt response: Corresponds to the Interrupt Mode (CMD40)."] #[inline(always)] - pub fn it_resp(self) -> &'a mut W { + pub fn it_resp(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::IT_RESP) } #[doc = "Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly."] #[inline(always)] - pub fn bor(self) -> &'a mut W { + pub fn bor(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::BOR) } #[doc = "End Boot Operation. This command allows the host processor to terminate the boot operation mode."] #[inline(always)] - pub fn ebo(self) -> &'a mut W { + pub fn ebo(self) -> &'a mut crate::W { self.variant(SPCMDSELECT_AW::EBO) } } @@ -156,16 +145,19 @@ impl From for bool { } } #[doc = "Field `OPDCMD` writer - Open Drain Command"] -pub type OPDCMD_W<'a, const O: u8> = crate::BitWriter<'a, CMDR_SPEC, O, OPDCMDSELECT_AW>; -impl<'a, const O: u8> OPDCMD_W<'a, O> { +pub type OPDCMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, OPDCMDSELECT_AW>; +impl<'a, REG, const O: u8> OPDCMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Push pull command."] #[inline(always)] - pub fn pushpull(self) -> &'a mut W { + pub fn pushpull(self) -> &'a mut crate::W { self.variant(OPDCMDSELECT_AW::PUSHPULL) } #[doc = "Open drain command."] #[inline(always)] - pub fn opendrain(self) -> &'a mut W { + pub fn opendrain(self) -> &'a mut crate::W { self.variant(OPDCMDSELECT_AW::OPENDRAIN) } } @@ -184,16 +176,19 @@ impl From for bool { } } #[doc = "Field `MAXLAT` writer - Max Latency for Command to Response"] -pub type MAXLAT_W<'a, const O: u8> = crate::BitWriter<'a, CMDR_SPEC, O, MAXLATSELECT_AW>; -impl<'a, const O: u8> MAXLAT_W<'a, O> { +pub type MAXLAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MAXLATSELECT_AW>; +impl<'a, REG, const O: u8> MAXLAT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "5-cycle max latency."] #[inline(always)] - pub fn _5(self) -> &'a mut W { + pub fn _5(self) -> &'a mut crate::W { self.variant(MAXLATSELECT_AW::_5) } #[doc = "64-cycle max latency."] #[inline(always)] - pub fn _64(self) -> &'a mut W { + pub fn _64(self) -> &'a mut crate::W { self.variant(MAXLATSELECT_AW::_64) } } @@ -218,21 +213,25 @@ impl crate::FieldSpec for TRCMDSELECT_AW { type Ux = u8; } #[doc = "Field `TRCMD` writer - Transfer Command"] -pub type TRCMD_W<'a, const O: u8> = crate::FieldWriter<'a, CMDR_SPEC, 2, O, TRCMDSELECT_AW>; -impl<'a, const O: u8> TRCMD_W<'a, O> { +pub type TRCMD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TRCMDSELECT_AW>; +impl<'a, REG, const O: u8> TRCMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No data transfer"] #[inline(always)] - pub fn no_data(self) -> &'a mut W { + pub fn no_data(self) -> &'a mut crate::W { self.variant(TRCMDSELECT_AW::NO_DATA) } #[doc = "Start data transfer"] #[inline(always)] - pub fn start_data(self) -> &'a mut W { + pub fn start_data(self) -> &'a mut crate::W { self.variant(TRCMDSELECT_AW::START_DATA) } #[doc = "Stop data transfer"] #[inline(always)] - pub fn stop_data(self) -> &'a mut W { + pub fn stop_data(self) -> &'a mut crate::W { self.variant(TRCMDSELECT_AW::STOP_DATA) } } @@ -251,16 +250,19 @@ impl From for bool { } } #[doc = "Field `TRDIR` writer - Transfer Direction"] -pub type TRDIR_W<'a, const O: u8> = crate::BitWriter<'a, CMDR_SPEC, O, TRDIRSELECT_AW>; -impl<'a, const O: u8> TRDIR_W<'a, O> { +pub type TRDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRDIRSELECT_AW>; +impl<'a, REG, const O: u8> TRDIR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Write."] #[inline(always)] - pub fn write(self) -> &'a mut W { + pub fn write(self) -> &'a mut crate::W { self.variant(TRDIRSELECT_AW::WRITE) } #[doc = "Read."] #[inline(always)] - pub fn read(self) -> &'a mut W { + pub fn read(self) -> &'a mut crate::W { self.variant(TRDIRSELECT_AW::READ) } } @@ -289,31 +291,35 @@ impl crate::FieldSpec for TRTYPSELECT_AW { type Ux = u8; } #[doc = "Field `TRTYP` writer - Transfer Type"] -pub type TRTYP_W<'a, const O: u8> = crate::FieldWriter<'a, CMDR_SPEC, 3, O, TRTYPSELECT_AW>; -impl<'a, const O: u8> TRTYP_W<'a, O> { +pub type TRTYP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, TRTYPSELECT_AW>; +impl<'a, REG, const O: u8> TRTYP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "MMC/SD Card Single Block"] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(TRTYPSELECT_AW::SINGLE) } #[doc = "MMC/SD Card Multiple Block"] #[inline(always)] - pub fn multiple(self) -> &'a mut W { + pub fn multiple(self) -> &'a mut crate::W { self.variant(TRTYPSELECT_AW::MULTIPLE) } #[doc = "MMC Stream"] #[inline(always)] - pub fn stream(self) -> &'a mut W { + pub fn stream(self) -> &'a mut crate::W { self.variant(TRTYPSELECT_AW::STREAM) } #[doc = "SDIO Byte"] #[inline(always)] - pub fn byte(self) -> &'a mut W { + pub fn byte(self) -> &'a mut crate::W { self.variant(TRTYPSELECT_AW::BYTE) } #[doc = "SDIO Block"] #[inline(always)] - pub fn block(self) -> &'a mut W { + pub fn block(self) -> &'a mut crate::W { self.variant(TRTYPSELECT_AW::BLOCK) } } @@ -338,21 +344,25 @@ impl crate::FieldSpec for IOSPCMDSELECT_AW { type Ux = u8; } #[doc = "Field `IOSPCMD` writer - SDIO Special Command"] -pub type IOSPCMD_W<'a, const O: u8> = crate::FieldWriter<'a, CMDR_SPEC, 2, O, IOSPCMDSELECT_AW>; -impl<'a, const O: u8> IOSPCMD_W<'a, O> { +pub type IOSPCMD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, IOSPCMDSELECT_AW>; +impl<'a, REG, const O: u8> IOSPCMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Not an SDIO Special Command"] #[inline(always)] - pub fn std(self) -> &'a mut W { + pub fn std(self) -> &'a mut crate::W { self.variant(IOSPCMDSELECT_AW::STD) } #[doc = "SDIO Suspend Command"] #[inline(always)] - pub fn suspend(self) -> &'a mut W { + pub fn suspend(self) -> &'a mut crate::W { self.variant(IOSPCMDSELECT_AW::SUSPEND) } #[doc = "SDIO Resume Command"] #[inline(always)] - pub fn resume(self) -> &'a mut W { + pub fn resume(self) -> &'a mut crate::W { self.variant(IOSPCMDSELECT_AW::RESUME) } } @@ -371,103 +381,105 @@ impl From for bool { } } #[doc = "Field `ATACS` writer - ATA with Command Completion Signal"] -pub type ATACS_W<'a, const O: u8> = crate::BitWriter<'a, CMDR_SPEC, O, ATACSSELECT_AW>; -impl<'a, const O: u8> ATACS_W<'a, O> { +pub type ATACS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ATACSSELECT_AW>; +impl<'a, REG, const O: u8> ATACS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal operation mode."] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(ATACSSELECT_AW::NORMAL) } #[doc = "This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR)."] #[inline(always)] - pub fn completion(self) -> &'a mut W { + pub fn completion(self) -> &'a mut crate::W { self.variant(ATACSSELECT_AW::COMPLETION) } } #[doc = "Field `BOOT_ACK` writer - Boot Operation Acknowledge"] -pub type BOOT_ACK_W<'a, const O: u8> = crate::BitWriter<'a, CMDR_SPEC, O>; +pub type BOOT_ACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:5 - Command Number"] #[inline(always)] #[must_use] - pub fn cmdnb(&mut self) -> CMDNB_W<0> { + pub fn cmdnb(&mut self) -> CMDNB_W { CMDNB_W::new(self) } #[doc = "Bits 6:7 - Response Type"] #[inline(always)] #[must_use] - pub fn rsptyp(&mut self) -> RSPTYP_W<6> { + pub fn rsptyp(&mut self) -> RSPTYP_W { RSPTYP_W::new(self) } #[doc = "Bits 8:10 - Special Command"] #[inline(always)] #[must_use] - pub fn spcmd(&mut self) -> SPCMD_W<8> { + pub fn spcmd(&mut self) -> SPCMD_W { SPCMD_W::new(self) } #[doc = "Bit 11 - Open Drain Command"] #[inline(always)] #[must_use] - pub fn opdcmd(&mut self) -> OPDCMD_W<11> { + pub fn opdcmd(&mut self) -> OPDCMD_W { OPDCMD_W::new(self) } #[doc = "Bit 12 - Max Latency for Command to Response"] #[inline(always)] #[must_use] - pub fn maxlat(&mut self) -> MAXLAT_W<12> { + pub fn maxlat(&mut self) -> MAXLAT_W { MAXLAT_W::new(self) } #[doc = "Bits 16:17 - Transfer Command"] #[inline(always)] #[must_use] - pub fn trcmd(&mut self) -> TRCMD_W<16> { + pub fn trcmd(&mut self) -> TRCMD_W { TRCMD_W::new(self) } #[doc = "Bit 18 - Transfer Direction"] #[inline(always)] #[must_use] - pub fn trdir(&mut self) -> TRDIR_W<18> { + pub fn trdir(&mut self) -> TRDIR_W { TRDIR_W::new(self) } #[doc = "Bits 19:21 - Transfer Type"] #[inline(always)] #[must_use] - pub fn trtyp(&mut self) -> TRTYP_W<19> { + pub fn trtyp(&mut self) -> TRTYP_W { TRTYP_W::new(self) } #[doc = "Bits 24:25 - SDIO Special Command"] #[inline(always)] #[must_use] - pub fn iospcmd(&mut self) -> IOSPCMD_W<24> { + pub fn iospcmd(&mut self) -> IOSPCMD_W { IOSPCMD_W::new(self) } #[doc = "Bit 26 - ATA with Command Completion Signal"] #[inline(always)] #[must_use] - pub fn atacs(&mut self) -> ATACS_W<26> { + pub fn atacs(&mut self) -> ATACS_W { ATACS_W::new(self) } #[doc = "Bit 27 - Boot Operation Acknowledge"] #[inline(always)] #[must_use] - pub fn boot_ack(&mut self) -> BOOT_ACK_W<27> { + pub fn boot_ack(&mut self) -> BOOT_ACK_W { BOOT_ACK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Command Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdr](index.html) module"] +#[doc = "Command Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMDR_SPEC; impl crate::RegisterSpec for CMDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmdr::W`](W) writer structure"] impl crate::Writable for CMDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/cr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/cr.rs index b93842a6..1937eb6d 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/cr.rs @@ -1,80 +1,60 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MCIEN` writer - Multi-Media Interface Enable"] -pub type MCIEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type MCIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MCIDIS` writer - Multi-Media Interface Disable"] -pub type MCIDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type MCIDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWSEN` writer - Power Save Mode Enable"] -pub type PWSEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PWSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWSDIS` writer - Power Save Mode Disable"] -pub type PWSDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PWSDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Multi-Media Interface Enable"] #[inline(always)] #[must_use] - pub fn mcien(&mut self) -> MCIEN_W<0> { + pub fn mcien(&mut self) -> MCIEN_W { MCIEN_W::new(self) } #[doc = "Bit 1 - Multi-Media Interface Disable"] #[inline(always)] #[must_use] - pub fn mcidis(&mut self) -> MCIDIS_W<1> { + pub fn mcidis(&mut self) -> MCIDIS_W { MCIDIS_W::new(self) } #[doc = "Bit 2 - Power Save Mode Enable"] #[inline(always)] #[must_use] - pub fn pwsen(&mut self) -> PWSEN_W<2> { + pub fn pwsen(&mut self) -> PWSEN_W { PWSEN_W::new(self) } #[doc = "Bit 3 - Power Save Mode Disable"] #[inline(always)] #[must_use] - pub fn pwsdis(&mut self) -> PWSDIS_W<3> { + pub fn pwsdis(&mut self) -> PWSDIS_W { PWSDIS_W::new(self) } #[doc = "Bit 7 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<7> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/cstor.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/cstor.rs index b4eab35e..3dd33859 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/cstor.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/cstor.rs @@ -1,43 +1,11 @@ #[doc = "Register `CSTOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSTOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSTOCYC` reader - Completion Signal Timeout Cycle Number"] pub type CSTOCYC_R = crate::FieldReader; #[doc = "Field `CSTOCYC` writer - Completion Signal Timeout Cycle Number"] -pub type CSTOCYC_W<'a, const O: u8> = crate::FieldWriter<'a, CSTOR_SPEC, 4, O>; +pub type CSTOCYC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CSTOMUL` reader - Completion Signal Timeout Multiplier"] pub type CSTOMUL_R = crate::FieldReader; #[doc = "Completion Signal Timeout Multiplier\n\nValue on reset: 0"] @@ -86,88 +54,92 @@ impl CSTOMUL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "CSTOCYC x 1"] #[inline(always)] pub fn is_1(&self) -> bool { *self == CSTOMULSELECT_A::_1 } - #[doc = "Checks if the value of the field is `_16`"] + #[doc = "CSTOCYC x 16"] #[inline(always)] pub fn is_16(&self) -> bool { *self == CSTOMULSELECT_A::_16 } - #[doc = "Checks if the value of the field is `_128`"] + #[doc = "CSTOCYC x 128"] #[inline(always)] pub fn is_128(&self) -> bool { *self == CSTOMULSELECT_A::_128 } - #[doc = "Checks if the value of the field is `_256`"] + #[doc = "CSTOCYC x 256"] #[inline(always)] pub fn is_256(&self) -> bool { *self == CSTOMULSELECT_A::_256 } - #[doc = "Checks if the value of the field is `_1024`"] + #[doc = "CSTOCYC x 1024"] #[inline(always)] pub fn is_1024(&self) -> bool { *self == CSTOMULSELECT_A::_1024 } - #[doc = "Checks if the value of the field is `_4096`"] + #[doc = "CSTOCYC x 4096"] #[inline(always)] pub fn is_4096(&self) -> bool { *self == CSTOMULSELECT_A::_4096 } - #[doc = "Checks if the value of the field is `_65536`"] + #[doc = "CSTOCYC x 65536"] #[inline(always)] pub fn is_65536(&self) -> bool { *self == CSTOMULSELECT_A::_65536 } - #[doc = "Checks if the value of the field is `_1048576`"] + #[doc = "CSTOCYC x 1048576"] #[inline(always)] pub fn is_1048576(&self) -> bool { *self == CSTOMULSELECT_A::_1048576 } } #[doc = "Field `CSTOMUL` writer - Completion Signal Timeout Multiplier"] -pub type CSTOMUL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CSTOR_SPEC, 3, O, CSTOMULSELECT_A>; -impl<'a, const O: u8> CSTOMUL_W<'a, O> { +pub type CSTOMUL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, CSTOMULSELECT_A>; +impl<'a, REG, const O: u8> CSTOMUL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "CSTOCYC x 1"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_1) } #[doc = "CSTOCYC x 16"] #[inline(always)] - pub fn _16(self) -> &'a mut W { + pub fn _16(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_16) } #[doc = "CSTOCYC x 128"] #[inline(always)] - pub fn _128(self) -> &'a mut W { + pub fn _128(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_128) } #[doc = "CSTOCYC x 256"] #[inline(always)] - pub fn _256(self) -> &'a mut W { + pub fn _256(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_256) } #[doc = "CSTOCYC x 1024"] #[inline(always)] - pub fn _1024(self) -> &'a mut W { + pub fn _1024(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_1024) } #[doc = "CSTOCYC x 4096"] #[inline(always)] - pub fn _4096(self) -> &'a mut W { + pub fn _4096(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_4096) } #[doc = "CSTOCYC x 65536"] #[inline(always)] - pub fn _65536(self) -> &'a mut W { + pub fn _65536(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_65536) } #[doc = "CSTOCYC x 1048576"] #[inline(always)] - pub fn _1048576(self) -> &'a mut W { + pub fn _1048576(self) -> &'a mut crate::W { self.variant(CSTOMULSELECT_A::_1048576) } } @@ -187,34 +159,31 @@ impl W { #[doc = "Bits 0:3 - Completion Signal Timeout Cycle Number"] #[inline(always)] #[must_use] - pub fn cstocyc(&mut self) -> CSTOCYC_W<0> { + pub fn cstocyc(&mut self) -> CSTOCYC_W { CSTOCYC_W::new(self) } #[doc = "Bits 4:6 - Completion Signal Timeout Multiplier"] #[inline(always)] #[must_use] - pub fn cstomul(&mut self) -> CSTOMUL_W<4> { + pub fn cstomul(&mut self) -> CSTOMUL_W { CSTOMUL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Completion Signal Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cstor](index.html) module"] +#[doc = "Completion Signal Timeout Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cstor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cstor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSTOR_SPEC; impl crate::RegisterSpec for CSTOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cstor::R](R) reader structure"] -impl crate::Readable for CSTOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cstor::W](W) writer structure"] +#[doc = "`read()` method returns [`cstor::R`](R) reader structure"] +impl crate::Readable for CSTOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cstor::W`](W) writer structure"] impl crate::Writable for CSTOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/dma.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/dma.rs index 50b142d3..97025227 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/dma.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/dma.rs @@ -1,39 +1,7 @@ #[doc = "Register `DMA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHKSIZE` reader - DMA Channel Read and Write Chunk Size"] pub type CHKSIZE_R = crate::FieldReader; #[doc = "DMA Channel Read and Write Chunk Size\n\nValue on reset: 0"] @@ -73,65 +41,69 @@ impl CHKSIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "1 data available"] #[inline(always)] pub fn is_1(&self) -> bool { *self == CHKSIZESELECT_A::_1 } - #[doc = "Checks if the value of the field is `_2`"] + #[doc = "2 data available"] #[inline(always)] pub fn is_2(&self) -> bool { *self == CHKSIZESELECT_A::_2 } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "4 data available"] #[inline(always)] pub fn is_4(&self) -> bool { *self == CHKSIZESELECT_A::_4 } - #[doc = "Checks if the value of the field is `_8`"] + #[doc = "8 data available"] #[inline(always)] pub fn is_8(&self) -> bool { *self == CHKSIZESELECT_A::_8 } - #[doc = "Checks if the value of the field is `_16`"] + #[doc = "16 data available"] #[inline(always)] pub fn is_16(&self) -> bool { *self == CHKSIZESELECT_A::_16 } } #[doc = "Field `CHKSIZE` writer - DMA Channel Read and Write Chunk Size"] -pub type CHKSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, DMA_SPEC, 3, O, CHKSIZESELECT_A>; -impl<'a, const O: u8> CHKSIZE_W<'a, O> { +pub type CHKSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CHKSIZESELECT_A>; +impl<'a, REG, const O: u8> CHKSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "1 data available"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(CHKSIZESELECT_A::_1) } #[doc = "2 data available"] #[inline(always)] - pub fn _2(self) -> &'a mut W { + pub fn _2(self) -> &'a mut crate::W { self.variant(CHKSIZESELECT_A::_2) } #[doc = "4 data available"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(CHKSIZESELECT_A::_4) } #[doc = "8 data available"] #[inline(always)] - pub fn _8(self) -> &'a mut W { + pub fn _8(self) -> &'a mut crate::W { self.variant(CHKSIZESELECT_A::_8) } #[doc = "16 data available"] #[inline(always)] - pub fn _16(self) -> &'a mut W { + pub fn _16(self) -> &'a mut crate::W { self.variant(CHKSIZESELECT_A::_16) } } #[doc = "Field `DMAEN` reader - DMA Hardware Handshaking Enable"] pub type DMAEN_R = crate::BitReader; #[doc = "Field `DMAEN` writer - DMA Hardware Handshaking Enable"] -pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, DMA_SPEC, O>; +pub type DMAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 4:6 - DMA Channel Read and Write Chunk Size"] #[inline(always)] @@ -148,34 +120,31 @@ impl W { #[doc = "Bits 4:6 - DMA Channel Read and Write Chunk Size"] #[inline(always)] #[must_use] - pub fn chksize(&mut self) -> CHKSIZE_W<4> { + pub fn chksize(&mut self) -> CHKSIZE_W { CHKSIZE_W::new(self) } #[doc = "Bit 8 - DMA Hardware Handshaking Enable"] #[inline(always)] #[must_use] - pub fn dmaen(&mut self) -> DMAEN_W<8> { + pub fn dmaen(&mut self) -> DMAEN_W { DMAEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma](index.html) module"] +#[doc = "DMA Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_SPEC; impl crate::RegisterSpec for DMA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma::R](R) reader structure"] -impl crate::Readable for DMA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma::W](W) writer structure"] +#[doc = "`read()` method returns [`dma::R`](R) reader structure"] +impl crate::Readable for DMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma::W`](W) writer structure"] impl crate::Writable for DMA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/dtor.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/dtor.rs index c3fc9ce8..24621755 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/dtor.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/dtor.rs @@ -1,43 +1,11 @@ #[doc = "Register `DTOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DTOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DTOCYC` reader - Data Timeout Cycle Number"] pub type DTOCYC_R = crate::FieldReader; #[doc = "Field `DTOCYC` writer - Data Timeout Cycle Number"] -pub type DTOCYC_W<'a, const O: u8> = crate::FieldWriter<'a, DTOR_SPEC, 4, O>; +pub type DTOCYC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `DTOMUL` reader - Data Timeout Multiplier"] pub type DTOMUL_R = crate::FieldReader; #[doc = "Data Timeout Multiplier\n\nValue on reset: 0"] @@ -86,88 +54,92 @@ impl DTOMUL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "DTOCYC"] #[inline(always)] pub fn is_1(&self) -> bool { *self == DTOMULSELECT_A::_1 } - #[doc = "Checks if the value of the field is `_16`"] + #[doc = "DTOCYC x 16"] #[inline(always)] pub fn is_16(&self) -> bool { *self == DTOMULSELECT_A::_16 } - #[doc = "Checks if the value of the field is `_128`"] + #[doc = "DTOCYC x 128"] #[inline(always)] pub fn is_128(&self) -> bool { *self == DTOMULSELECT_A::_128 } - #[doc = "Checks if the value of the field is `_256`"] + #[doc = "DTOCYC x 256"] #[inline(always)] pub fn is_256(&self) -> bool { *self == DTOMULSELECT_A::_256 } - #[doc = "Checks if the value of the field is `_1024`"] + #[doc = "DTOCYC x 1024"] #[inline(always)] pub fn is_1024(&self) -> bool { *self == DTOMULSELECT_A::_1024 } - #[doc = "Checks if the value of the field is `_4096`"] + #[doc = "DTOCYC x 4096"] #[inline(always)] pub fn is_4096(&self) -> bool { *self == DTOMULSELECT_A::_4096 } - #[doc = "Checks if the value of the field is `_65536`"] + #[doc = "DTOCYC x 65536"] #[inline(always)] pub fn is_65536(&self) -> bool { *self == DTOMULSELECT_A::_65536 } - #[doc = "Checks if the value of the field is `_1048576`"] + #[doc = "DTOCYC x 1048576"] #[inline(always)] pub fn is_1048576(&self) -> bool { *self == DTOMULSELECT_A::_1048576 } } #[doc = "Field `DTOMUL` writer - Data Timeout Multiplier"] -pub type DTOMUL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, DTOR_SPEC, 3, O, DTOMULSELECT_A>; -impl<'a, const O: u8> DTOMUL_W<'a, O> { +pub type DTOMUL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, DTOMULSELECT_A>; +impl<'a, REG, const O: u8> DTOMUL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "DTOCYC"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_1) } #[doc = "DTOCYC x 16"] #[inline(always)] - pub fn _16(self) -> &'a mut W { + pub fn _16(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_16) } #[doc = "DTOCYC x 128"] #[inline(always)] - pub fn _128(self) -> &'a mut W { + pub fn _128(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_128) } #[doc = "DTOCYC x 256"] #[inline(always)] - pub fn _256(self) -> &'a mut W { + pub fn _256(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_256) } #[doc = "DTOCYC x 1024"] #[inline(always)] - pub fn _1024(self) -> &'a mut W { + pub fn _1024(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_1024) } #[doc = "DTOCYC x 4096"] #[inline(always)] - pub fn _4096(self) -> &'a mut W { + pub fn _4096(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_4096) } #[doc = "DTOCYC x 65536"] #[inline(always)] - pub fn _65536(self) -> &'a mut W { + pub fn _65536(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_65536) } #[doc = "DTOCYC x 1048576"] #[inline(always)] - pub fn _1048576(self) -> &'a mut W { + pub fn _1048576(self) -> &'a mut crate::W { self.variant(DTOMULSELECT_A::_1048576) } } @@ -187,34 +159,31 @@ impl W { #[doc = "Bits 0:3 - Data Timeout Cycle Number"] #[inline(always)] #[must_use] - pub fn dtocyc(&mut self) -> DTOCYC_W<0> { + pub fn dtocyc(&mut self) -> DTOCYC_W { DTOCYC_W::new(self) } #[doc = "Bits 4:6 - Data Timeout Multiplier"] #[inline(always)] #[must_use] - pub fn dtomul(&mut self) -> DTOMUL_W<4> { + pub fn dtomul(&mut self) -> DTOMUL_W { DTOMUL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtor](index.html) module"] +#[doc = "Data Timeout Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTOR_SPEC; impl crate::RegisterSpec for DTOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dtor::R](R) reader structure"] -impl crate::Readable for DTOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dtor::W](W) writer structure"] +#[doc = "`read()` method returns [`dtor::R`](R) reader structure"] +impl crate::Readable for DTOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dtor::W`](W) writer structure"] impl crate::Writable for DTOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/fifo.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/fifo.rs index 747cbcd7..5876965d 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/fifo.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/fifo.rs @@ -1,43 +1,11 @@ #[doc = "Register `FIFO[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FIFO[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - Data to Read or Data to Write"] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - Data to Read or Data to Write"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, FIFO_SPEC, 32, O, u32>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Data to Read or Data to Write"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Data to Read or Data to Write"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FIFO Memory Aperture0 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo](index.html) module"] +#[doc = "FIFO Memory Aperture0 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FIFO_SPEC; impl crate::RegisterSpec for FIFO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fifo::R](R) reader structure"] -impl crate::Readable for FIFO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fifo::W](W) writer structure"] +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] impl crate::Writable for FIFO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/idr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/idr.rs index 7f6b2b91..578459d2 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/idr.rs @@ -1,232 +1,212 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMDRDY` writer - Command Ready Interrupt Disable"] -pub type CMDRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CMDRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRDY` writer - Receiver Ready Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLKE` writer - Data Block Ended Interrupt Disable"] -pub type BLKE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type BLKE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTIP` writer - Data Transfer in Progress Interrupt Disable"] -pub type DTIP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DTIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NOTBUSY` writer - Data Not Busy Interrupt Disable"] -pub type NOTBUSY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type NOTBUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIOIRQA` writer - SDIO Interrupt for Slot A Interrupt Disable"] -pub type SDIOIRQA_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SDIOIRQA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIOWAIT` writer - SDIO Read Wait Operation Status Interrupt Disable"] -pub type SDIOWAIT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SDIOWAIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSRCV` writer - Completion Signal received interrupt Disable"] -pub type CSRCV_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CSRCV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RINDE` writer - Response Index Error Interrupt Disable"] -pub type RINDE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RINDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RDIRE` writer - Response Direction Error Interrupt Disable"] -pub type RDIRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RDIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCRCE` writer - Response CRC Error Interrupt Disable"] -pub type RCRCE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RCRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RENDE` writer - Response End Bit Error Interrupt Disable"] -pub type RENDE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RENDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTOE` writer - Response Time-out Error Interrupt Disable"] -pub type RTOE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RTOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRCE` writer - Data CRC Error Interrupt Disable"] -pub type DCRCE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DCRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTOE` writer - Data Time-out Error Interrupt Disable"] -pub type DTOE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DTOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSTOE` writer - Completion Signal Time out Error Interrupt Disable"] -pub type CSTOE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CSTOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLKOVRE` writer - DMA Block Overrun Error Interrupt Disable"] -pub type BLKOVRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type BLKOVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOEMPTY` writer - FIFO empty Interrupt Disable"] -pub type FIFOEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type FIFOEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `XFRDONE` writer - Transfer Done Interrupt Disable"] -pub type XFRDONE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type XFRDONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKRCV` writer - Boot Acknowledge Interrupt Disable"] -pub type ACKRCV_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ACKRCV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKRCVE` writer - Boot Acknowledge Error Interrupt Disable"] -pub type ACKRCVE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ACKRCVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Interrupt Disable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Underrun Interrupt Disable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Command Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmdrdy(&mut self) -> CMDRDY_W<0> { + pub fn cmdrdy(&mut self) -> CMDRDY_W { CMDRDY_W::new(self) } #[doc = "Bit 1 - Receiver Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<1> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 2 - Transmit Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<2> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 3 - Data Block Ended Interrupt Disable"] #[inline(always)] #[must_use] - pub fn blke(&mut self) -> BLKE_W<3> { + pub fn blke(&mut self) -> BLKE_W { BLKE_W::new(self) } #[doc = "Bit 4 - Data Transfer in Progress Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dtip(&mut self) -> DTIP_W<4> { + pub fn dtip(&mut self) -> DTIP_W { DTIP_W::new(self) } #[doc = "Bit 5 - Data Not Busy Interrupt Disable"] #[inline(always)] #[must_use] - pub fn notbusy(&mut self) -> NOTBUSY_W<5> { + pub fn notbusy(&mut self) -> NOTBUSY_W { NOTBUSY_W::new(self) } #[doc = "Bit 8 - SDIO Interrupt for Slot A Interrupt Disable"] #[inline(always)] #[must_use] - pub fn sdioirqa(&mut self) -> SDIOIRQA_W<8> { + pub fn sdioirqa(&mut self) -> SDIOIRQA_W { SDIOIRQA_W::new(self) } #[doc = "Bit 12 - SDIO Read Wait Operation Status Interrupt Disable"] #[inline(always)] #[must_use] - pub fn sdiowait(&mut self) -> SDIOWAIT_W<12> { + pub fn sdiowait(&mut self) -> SDIOWAIT_W { SDIOWAIT_W::new(self) } #[doc = "Bit 13 - Completion Signal received interrupt Disable"] #[inline(always)] #[must_use] - pub fn csrcv(&mut self) -> CSRCV_W<13> { + pub fn csrcv(&mut self) -> CSRCV_W { CSRCV_W::new(self) } #[doc = "Bit 16 - Response Index Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rinde(&mut self) -> RINDE_W<16> { + pub fn rinde(&mut self) -> RINDE_W { RINDE_W::new(self) } #[doc = "Bit 17 - Response Direction Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rdire(&mut self) -> RDIRE_W<17> { + pub fn rdire(&mut self) -> RDIRE_W { RDIRE_W::new(self) } #[doc = "Bit 18 - Response CRC Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rcrce(&mut self) -> RCRCE_W<18> { + pub fn rcrce(&mut self) -> RCRCE_W { RCRCE_W::new(self) } #[doc = "Bit 19 - Response End Bit Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rende(&mut self) -> RENDE_W<19> { + pub fn rende(&mut self) -> RENDE_W { RENDE_W::new(self) } #[doc = "Bit 20 - Response Time-out Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rtoe(&mut self) -> RTOE_W<20> { + pub fn rtoe(&mut self) -> RTOE_W { RTOE_W::new(self) } #[doc = "Bit 21 - Data CRC Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dcrce(&mut self) -> DCRCE_W<21> { + pub fn dcrce(&mut self) -> DCRCE_W { DCRCE_W::new(self) } #[doc = "Bit 22 - Data Time-out Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dtoe(&mut self) -> DTOE_W<22> { + pub fn dtoe(&mut self) -> DTOE_W { DTOE_W::new(self) } #[doc = "Bit 23 - Completion Signal Time out Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cstoe(&mut self) -> CSTOE_W<23> { + pub fn cstoe(&mut self) -> CSTOE_W { CSTOE_W::new(self) } #[doc = "Bit 24 - DMA Block Overrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn blkovre(&mut self) -> BLKOVRE_W<24> { + pub fn blkovre(&mut self) -> BLKOVRE_W { BLKOVRE_W::new(self) } #[doc = "Bit 26 - FIFO empty Interrupt Disable"] #[inline(always)] #[must_use] - pub fn fifoempty(&mut self) -> FIFOEMPTY_W<26> { + pub fn fifoempty(&mut self) -> FIFOEMPTY_W { FIFOEMPTY_W::new(self) } #[doc = "Bit 27 - Transfer Done Interrupt Disable"] #[inline(always)] #[must_use] - pub fn xfrdone(&mut self) -> XFRDONE_W<27> { + pub fn xfrdone(&mut self) -> XFRDONE_W { XFRDONE_W::new(self) } #[doc = "Bit 28 - Boot Acknowledge Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ackrcv(&mut self) -> ACKRCV_W<28> { + pub fn ackrcv(&mut self) -> ACKRCV_W { ACKRCV_W::new(self) } #[doc = "Bit 29 - Boot Acknowledge Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ackrcve(&mut self) -> ACKRCVE_W<29> { + pub fn ackrcve(&mut self) -> ACKRCVE_W { ACKRCVE_W::new(self) } #[doc = "Bit 30 - Overrun Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<30> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 31 - Underrun Interrupt Disable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<31> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/ier.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/ier.rs index 0aaee8bc..d5220c14 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/ier.rs @@ -1,232 +1,212 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CMDRDY` writer - Command Ready Interrupt Enable"] -pub type CMDRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CMDRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRDY` writer - Receiver Ready Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLKE` writer - Data Block Ended Interrupt Enable"] -pub type BLKE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type BLKE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTIP` writer - Data Transfer in Progress Interrupt Enable"] -pub type DTIP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DTIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NOTBUSY` writer - Data Not Busy Interrupt Enable"] -pub type NOTBUSY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type NOTBUSY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIOIRQA` writer - SDIO Interrupt for Slot A Interrupt Enable"] -pub type SDIOIRQA_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SDIOIRQA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SDIOWAIT` writer - SDIO Read Wait Operation Status Interrupt Enable"] -pub type SDIOWAIT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SDIOWAIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSRCV` writer - Completion Signal Received Interrupt Enable"] -pub type CSRCV_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CSRCV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RINDE` writer - Response Index Error Interrupt Enable"] -pub type RINDE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RINDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RDIRE` writer - Response Direction Error Interrupt Enable"] -pub type RDIRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RDIRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCRCE` writer - Response CRC Error Interrupt Enable"] -pub type RCRCE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RCRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RENDE` writer - Response End Bit Error Interrupt Enable"] -pub type RENDE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RENDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTOE` writer - Response Time-out Error Interrupt Enable"] -pub type RTOE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RTOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCRCE` writer - Data CRC Error Interrupt Enable"] -pub type DCRCE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DCRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTOE` writer - Data Time-out Error Interrupt Enable"] -pub type DTOE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DTOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSTOE` writer - Completion Signal Timeout Error Interrupt Enable"] -pub type CSTOE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CSTOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BLKOVRE` writer - DMA Block Overrun Error Interrupt Enable"] -pub type BLKOVRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type BLKOVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOEMPTY` writer - FIFO empty Interrupt enable"] -pub type FIFOEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type FIFOEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `XFRDONE` writer - Transfer Done Interrupt enable"] -pub type XFRDONE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type XFRDONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKRCV` writer - Boot Acknowledge Interrupt Enable"] -pub type ACKRCV_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ACKRCV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACKRCVE` writer - Boot Acknowledge Error Interrupt Enable"] -pub type ACKRCVE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ACKRCVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Underrun Interrupt Enable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Command Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmdrdy(&mut self) -> CMDRDY_W<0> { + pub fn cmdrdy(&mut self) -> CMDRDY_W { CMDRDY_W::new(self) } #[doc = "Bit 1 - Receiver Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<1> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 2 - Transmit Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<2> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 3 - Data Block Ended Interrupt Enable"] #[inline(always)] #[must_use] - pub fn blke(&mut self) -> BLKE_W<3> { + pub fn blke(&mut self) -> BLKE_W { BLKE_W::new(self) } #[doc = "Bit 4 - Data Transfer in Progress Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dtip(&mut self) -> DTIP_W<4> { + pub fn dtip(&mut self) -> DTIP_W { DTIP_W::new(self) } #[doc = "Bit 5 - Data Not Busy Interrupt Enable"] #[inline(always)] #[must_use] - pub fn notbusy(&mut self) -> NOTBUSY_W<5> { + pub fn notbusy(&mut self) -> NOTBUSY_W { NOTBUSY_W::new(self) } #[doc = "Bit 8 - SDIO Interrupt for Slot A Interrupt Enable"] #[inline(always)] #[must_use] - pub fn sdioirqa(&mut self) -> SDIOIRQA_W<8> { + pub fn sdioirqa(&mut self) -> SDIOIRQA_W { SDIOIRQA_W::new(self) } #[doc = "Bit 12 - SDIO Read Wait Operation Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn sdiowait(&mut self) -> SDIOWAIT_W<12> { + pub fn sdiowait(&mut self) -> SDIOWAIT_W { SDIOWAIT_W::new(self) } #[doc = "Bit 13 - Completion Signal Received Interrupt Enable"] #[inline(always)] #[must_use] - pub fn csrcv(&mut self) -> CSRCV_W<13> { + pub fn csrcv(&mut self) -> CSRCV_W { CSRCV_W::new(self) } #[doc = "Bit 16 - Response Index Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rinde(&mut self) -> RINDE_W<16> { + pub fn rinde(&mut self) -> RINDE_W { RINDE_W::new(self) } #[doc = "Bit 17 - Response Direction Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rdire(&mut self) -> RDIRE_W<17> { + pub fn rdire(&mut self) -> RDIRE_W { RDIRE_W::new(self) } #[doc = "Bit 18 - Response CRC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rcrce(&mut self) -> RCRCE_W<18> { + pub fn rcrce(&mut self) -> RCRCE_W { RCRCE_W::new(self) } #[doc = "Bit 19 - Response End Bit Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rende(&mut self) -> RENDE_W<19> { + pub fn rende(&mut self) -> RENDE_W { RENDE_W::new(self) } #[doc = "Bit 20 - Response Time-out Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rtoe(&mut self) -> RTOE_W<20> { + pub fn rtoe(&mut self) -> RTOE_W { RTOE_W::new(self) } #[doc = "Bit 21 - Data CRC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dcrce(&mut self) -> DCRCE_W<21> { + pub fn dcrce(&mut self) -> DCRCE_W { DCRCE_W::new(self) } #[doc = "Bit 22 - Data Time-out Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dtoe(&mut self) -> DTOE_W<22> { + pub fn dtoe(&mut self) -> DTOE_W { DTOE_W::new(self) } #[doc = "Bit 23 - Completion Signal Timeout Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cstoe(&mut self) -> CSTOE_W<23> { + pub fn cstoe(&mut self) -> CSTOE_W { CSTOE_W::new(self) } #[doc = "Bit 24 - DMA Block Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn blkovre(&mut self) -> BLKOVRE_W<24> { + pub fn blkovre(&mut self) -> BLKOVRE_W { BLKOVRE_W::new(self) } #[doc = "Bit 26 - FIFO empty Interrupt enable"] #[inline(always)] #[must_use] - pub fn fifoempty(&mut self) -> FIFOEMPTY_W<26> { + pub fn fifoempty(&mut self) -> FIFOEMPTY_W { FIFOEMPTY_W::new(self) } #[doc = "Bit 27 - Transfer Done Interrupt enable"] #[inline(always)] #[must_use] - pub fn xfrdone(&mut self) -> XFRDONE_W<27> { + pub fn xfrdone(&mut self) -> XFRDONE_W { XFRDONE_W::new(self) } #[doc = "Bit 28 - Boot Acknowledge Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ackrcv(&mut self) -> ACKRCV_W<28> { + pub fn ackrcv(&mut self) -> ACKRCV_W { ACKRCV_W::new(self) } #[doc = "Bit 29 - Boot Acknowledge Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ackrcve(&mut self) -> ACKRCVE_W<29> { + pub fn ackrcve(&mut self) -> ACKRCVE_W { ACKRCVE_W::new(self) } #[doc = "Bit 30 - Overrun Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<30> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 31 - Underrun Interrupt Enable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<31> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/imr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/imr.rs index 6f08a618..a5504c69 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CMDRDY` reader - Command Ready Interrupt Mask"] pub type CMDRDY_R = crate::BitReader; #[doc = "Field `RXRDY` reader - Receiver Ready Interrupt Mask"] @@ -183,15 +170,13 @@ impl R { UNRE_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/mr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/mr.rs index 6823e03f..02076664 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/mr.rs @@ -1,67 +1,35 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLKDIV` reader - Clock Divider"] pub type CLKDIV_R = crate::FieldReader; #[doc = "Field `CLKDIV` writer - Clock Divider"] -pub type CLKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O>; +pub type CLKDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PWSDIV` reader - Power Saving Divider"] pub type PWSDIV_R = crate::FieldReader; #[doc = "Field `PWSDIV` writer - Power Saving Divider"] -pub type PWSDIV_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 3, O>; +pub type PWSDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `RDPROOF` reader - Read Proof Enable"] pub type RDPROOF_R = crate::BitReader; #[doc = "Field `RDPROOF` writer - Read Proof Enable"] -pub type RDPROOF_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RDPROOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRPROOF` reader - Write Proof Enable"] pub type WRPROOF_R = crate::BitReader; #[doc = "Field `WRPROOF` writer - Write Proof Enable"] -pub type WRPROOF_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WRPROOF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FBYTE` reader - Force Byte Transfer"] pub type FBYTE_R = crate::BitReader; #[doc = "Field `FBYTE` writer - Force Byte Transfer"] -pub type FBYTE_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type FBYTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PADV` reader - Padding Value"] pub type PADV_R = crate::BitReader; #[doc = "Field `PADV` writer - Padding Value"] -pub type PADV_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type PADV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLKODD` reader - Clock divider is odd"] pub type CLKODD_R = crate::BitReader; #[doc = "Field `CLKODD` writer - Clock divider is odd"] -pub type CLKODD_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type CLKODD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - Clock Divider"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bits 0:7 - Clock Divider"] #[inline(always)] #[must_use] - pub fn clkdiv(&mut self) -> CLKDIV_W<0> { + pub fn clkdiv(&mut self) -> CLKDIV_W { CLKDIV_W::new(self) } #[doc = "Bits 8:10 - Power Saving Divider"] #[inline(always)] #[must_use] - pub fn pwsdiv(&mut self) -> PWSDIV_W<8> { + pub fn pwsdiv(&mut self) -> PWSDIV_W { PWSDIV_W::new(self) } #[doc = "Bit 11 - Read Proof Enable"] #[inline(always)] #[must_use] - pub fn rdproof(&mut self) -> RDPROOF_W<11> { + pub fn rdproof(&mut self) -> RDPROOF_W { RDPROOF_W::new(self) } #[doc = "Bit 12 - Write Proof Enable"] #[inline(always)] #[must_use] - pub fn wrproof(&mut self) -> WRPROOF_W<12> { + pub fn wrproof(&mut self) -> WRPROOF_W { WRPROOF_W::new(self) } #[doc = "Bit 13 - Force Byte Transfer"] #[inline(always)] #[must_use] - pub fn fbyte(&mut self) -> FBYTE_W<13> { + pub fn fbyte(&mut self) -> FBYTE_W { FBYTE_W::new(self) } #[doc = "Bit 14 - Padding Value"] #[inline(always)] #[must_use] - pub fn padv(&mut self) -> PADV_W<14> { + pub fn padv(&mut self) -> PADV_W { PADV_W::new(self) } #[doc = "Bit 16 - Clock divider is odd"] #[inline(always)] #[must_use] - pub fn clkodd(&mut self) -> CLKODD_W<16> { + pub fn clkodd(&mut self) -> CLKODD_W { CLKODD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/rdr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/rdr.rs index fd3be16d..82583511 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/rdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/rdr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATA` reader - Data to Read"] pub type DATA_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { DATA_R::new(self.bits) } } -#[doc = "Receive Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdr](index.html) module"] +#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RDR_SPEC; impl crate::RegisterSpec for RDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rdr::R](R) reader structure"] -impl crate::Readable for RDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rdr::R`](R) reader structure"] +impl crate::Readable for RDR_SPEC {} #[doc = "`reset()` method sets RDR to value 0"] impl crate::Resettable for RDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/rspr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/rspr.rs index b8d833fb..f20f99f1 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/rspr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/rspr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RSPR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RSP` reader - Response"] pub type RSP_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RSP_R::new(self.bits) } } -#[doc = "Response Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rspr](index.html) module"] +#[doc = "Response Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rspr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSPR_SPEC; impl crate::RegisterSpec for RSPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rspr::R](R) reader structure"] -impl crate::Readable for RSPR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rspr::R`](R) reader structure"] +impl crate::Readable for RSPR_SPEC {} #[doc = "`reset()` method sets RSPR[%s] to value 0"] impl crate::Resettable for RSPR_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/sdcr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/sdcr.rs index a2b9cadc..1955de1b 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/sdcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/sdcr.rs @@ -1,39 +1,7 @@ #[doc = "Register `SDCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SDCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDCSEL` reader - SDCard/SDIO Slot"] pub type SDCSEL_R = crate::FieldReader; #[doc = "SDCard/SDIO Slot\n\nValue on reset: 0"] @@ -61,18 +29,22 @@ impl SDCSEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `SLOTA`"] + #[doc = "Slot A is selected."] #[inline(always)] pub fn is_slota(&self) -> bool { *self == SDCSELSELECT_A::SLOTA } } #[doc = "Field `SDCSEL` writer - SDCard/SDIO Slot"] -pub type SDCSEL_W<'a, const O: u8> = crate::FieldWriter<'a, SDCR_SPEC, 2, O, SDCSELSELECT_A>; -impl<'a, const O: u8> SDCSEL_W<'a, O> { +pub type SDCSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, SDCSELSELECT_A>; +impl<'a, REG, const O: u8> SDCSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Slot A is selected."] #[inline(always)] - pub fn slota(self) -> &'a mut W { + pub fn slota(self) -> &'a mut crate::W { self.variant(SDCSELSELECT_A::SLOTA) } } @@ -109,38 +81,42 @@ impl SDCBUS_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1`"] + #[doc = "1 bit"] #[inline(always)] pub fn is_1(&self) -> bool { *self == SDCBUSSELECT_A::_1 } - #[doc = "Checks if the value of the field is `_4`"] + #[doc = "4 bits"] #[inline(always)] pub fn is_4(&self) -> bool { *self == SDCBUSSELECT_A::_4 } - #[doc = "Checks if the value of the field is `_8`"] + #[doc = "8 bits"] #[inline(always)] pub fn is_8(&self) -> bool { *self == SDCBUSSELECT_A::_8 } } #[doc = "Field `SDCBUS` writer - SDCard/SDIO Bus Width"] -pub type SDCBUS_W<'a, const O: u8> = crate::FieldWriter<'a, SDCR_SPEC, 2, O, SDCBUSSELECT_A>; -impl<'a, const O: u8> SDCBUS_W<'a, O> { +pub type SDCBUS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, SDCBUSSELECT_A>; +impl<'a, REG, const O: u8> SDCBUS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "1 bit"] #[inline(always)] - pub fn _1(self) -> &'a mut W { + pub fn _1(self) -> &'a mut crate::W { self.variant(SDCBUSSELECT_A::_1) } #[doc = "4 bits"] #[inline(always)] - pub fn _4(self) -> &'a mut W { + pub fn _4(self) -> &'a mut crate::W { self.variant(SDCBUSSELECT_A::_4) } #[doc = "8 bits"] #[inline(always)] - pub fn _8(self) -> &'a mut W { + pub fn _8(self) -> &'a mut crate::W { self.variant(SDCBUSSELECT_A::_8) } } @@ -160,34 +136,31 @@ impl W { #[doc = "Bits 0:1 - SDCard/SDIO Slot"] #[inline(always)] #[must_use] - pub fn sdcsel(&mut self) -> SDCSEL_W<0> { + pub fn sdcsel(&mut self) -> SDCSEL_W { SDCSEL_W::new(self) } #[doc = "Bits 6:7 - SDCard/SDIO Bus Width"] #[inline(always)] #[must_use] - pub fn sdcbus(&mut self) -> SDCBUS_W<6> { + pub fn sdcbus(&mut self) -> SDCBUS_W { SDCBUS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SD/SDIO Card Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdcr](index.html) module"] +#[doc = "SD/SDIO Card Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SDCR_SPEC; impl crate::RegisterSpec for SDCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sdcr::R](R) reader structure"] -impl crate::Readable for SDCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sdcr::W](W) writer structure"] +#[doc = "`read()` method returns [`sdcr::R`](R) reader structure"] +impl crate::Readable for SDCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sdcr::W`](W) writer structure"] impl crate::Writable for SDCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/sr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/sr.rs index c1adfda3..b6e87e59 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CMDRDY` reader - Command Ready (cleared by writing in HSMCI_CMDR)"] pub type CMDRDY_R = crate::BitReader; #[doc = "Field `RXRDY` reader - Receiver Ready (cleared by reading HSMCI_RDR)"] @@ -183,15 +170,13 @@ impl R { UNRE_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/tdr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/tdr.rs index 1372652c..52e36464 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/tdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/tdr.rs @@ -1,48 +1,28 @@ #[doc = "Register `TDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` writer - Data to Write"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, TDR_SPEC, 32, O, u32>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Data to Write"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Data Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdr](index.html) module"] +#[doc = "Transmit Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TDR_SPEC; impl crate::RegisterSpec for TDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [tdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"] impl crate::Writable for TDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/wpmr.rs index c9b6338d..ebe985fb 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protect Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protect Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protect Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protect Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protect Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protect Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protect Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/hsmci/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/hsmci/wpsr.rs index 69b9952f..216a7a8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/hsmci/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/hsmci/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0.rs index 2b71185c..7a633b8e 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0.rs @@ -22,43 +22,53 @@ pub struct RegisterBlock { #[doc = "0x24 - Transmitter Holding Register"] pub thr: THR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "SCR (w) register accessor: an alias for `Reg`"] +#[doc = "SCR (w) register accessor: Status Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +module"] pub type SCR = crate::Reg; #[doc = "Status Clear Register"] pub mod scr; -#[doc = "SSR (w) register accessor: an alias for `Reg`"] +#[doc = "SSR (w) register accessor: Status Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ssr`] +module"] pub type SSR = crate::Reg; #[doc = "Status Set Register"] pub mod ssr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "RHR (r) register accessor: an alias for `Reg`"] +#[doc = "RHR (r) register accessor: Receiver Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rhr`] +module"] pub type RHR = crate::Reg; #[doc = "Receiver Holding Register"] pub mod rhr; -#[doc = "THR (w) register accessor: an alias for `Reg`"] +#[doc = "THR (w) register accessor: Transmitter Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +module"] pub type THR = crate::Reg; #[doc = "Transmitter Holding Register"] pub mod thr; diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/cr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/cr.rs index 64b3c588..2b219288 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/cr.rs @@ -1,96 +1,76 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXEN` writer - Receiver Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDIS` writer - Receiver Disable"] -pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CKEN` writer - Clocks Enable"] -pub type CKEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type CKEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CKDIS` writer - Clocks Disable"] -pub type CKDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type CKDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` writer - Transmitter Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDIS` writer - Transmitter Disable"] -pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Receiver Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<0> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 1 - Receiver Disable"] #[inline(always)] #[must_use] - pub fn rxdis(&mut self) -> RXDIS_W<1> { + pub fn rxdis(&mut self) -> RXDIS_W { RXDIS_W::new(self) } #[doc = "Bit 2 - Clocks Enable"] #[inline(always)] #[must_use] - pub fn cken(&mut self) -> CKEN_W<2> { + pub fn cken(&mut self) -> CKEN_W { CKEN_W::new(self) } #[doc = "Bit 3 - Clocks Disable"] #[inline(always)] #[must_use] - pub fn ckdis(&mut self) -> CKDIS_W<3> { + pub fn ckdis(&mut self) -> CKDIS_W { CKDIS_W::new(self) } #[doc = "Bit 4 - Transmitter Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<4> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 5 - Transmitter Disable"] #[inline(always)] #[must_use] - pub fn txdis(&mut self) -> TXDIS_W<5> { + pub fn txdis(&mut self) -> TXDIS_W { TXDIS_W::new(self) } #[doc = "Bit 7 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<7> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/idr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/idr.rs index 202985e6..44ebe516 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/idr.rs @@ -1,72 +1,52 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - Receiver Ready Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOR` writer - Receiver Overrun Interrupt Disable"] -pub type RXOR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUR` writer - Transmit Underflow Interrupt Disable"] -pub type TXUR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 1 - Receiver Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<1> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 2 - Receiver Overrun Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxor(&mut self) -> RXOR_W<2> { + pub fn rxor(&mut self) -> RXOR_W { RXOR_W::new(self) } #[doc = "Bit 5 - Transmit Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<5> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 6 - Transmit Underflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txur(&mut self) -> TXUR_W<6> { + pub fn txur(&mut self) -> TXUR_W { TXUR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/ier.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/ier.rs index fe4ae5b6..d61be459 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/ier.rs @@ -1,72 +1,52 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - Receiver Ready Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOR` writer - Receiver Overrun Interrupt Enable"] -pub type RXOR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUR` writer - Transmit Underflow Interrupt Enable"] -pub type TXUR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 1 - Receiver Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<1> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 2 - Receiver Overrun Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxor(&mut self) -> RXOR_W<2> { + pub fn rxor(&mut self) -> RXOR_W { RXOR_W::new(self) } #[doc = "Bit 5 - Transmit Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<5> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 6 - Transmit Underflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txur(&mut self) -> TXUR_W<6> { + pub fn txur(&mut self) -> TXUR_W { TXUR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/imr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/imr.rs index 829c33d0..f6657216 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Receiver Ready Interrupt Disable"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `RXOR` reader - Receiver Overrun Interrupt Disable"] @@ -43,15 +30,13 @@ impl R { TXUR_R::new(((self.bits >> 6) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/mr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/mr.rs index f85076ba..84c6d814 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MODE` reader - Inter-IC Sound Controller Mode"] pub type MODE_R = crate::BitReader; #[doc = "Inter-IC Sound Controller Mode\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl MODE_R { true => MODESELECT_A::MASTER, } } - #[doc = "Checks if the value of the field is `SLAVE`"] + #[doc = "I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization."] #[inline(always)] pub fn is_slave(&self) -> bool { *self == MODESELECT_A::SLAVE } - #[doc = "Checks if the value of the field is `MASTER`"] + #[doc = "Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set."] #[inline(always)] pub fn is_master(&self) -> bool { *self == MODESELECT_A::MASTER } } #[doc = "Field `MODE` writer - Inter-IC Sound Controller Mode"] -pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, MODESELECT_A>; -impl<'a, const O: u8> MODE_W<'a, O> { +pub type MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MODESELECT_A>; +impl<'a, REG, const O: u8> MODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "I2SC_CK and I2SC_WS pin inputs used as bit clock and word select/frame synchronization."] #[inline(always)] - pub fn slave(self) -> &'a mut W { + pub fn slave(self) -> &'a mut crate::W { self.variant(MODESELECT_A::SLAVE) } #[doc = "Bit clock and word select/frame synchronization generated by I2SC from MCK and output to I2SC_CK and I2SC_WS pins. Peripheral clock or GCLK is output as master clock on I2SC_MCK if I2SC_MR.IMCKMODE is set."] #[inline(always)] - pub fn master(self) -> &'a mut W { + pub fn master(self) -> &'a mut crate::W { self.variant(MODESELECT_A::MASTER) } } @@ -132,120 +103,124 @@ impl DATALENGTH_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_32_BITS`"] + #[doc = "Data length is set to 32 bits"] #[inline(always)] pub fn is_32_bits(&self) -> bool { *self == DATALENGTHSELECT_A::_32_BITS } - #[doc = "Checks if the value of the field is `_24_BITS`"] + #[doc = "Data length is set to 24 bits"] #[inline(always)] pub fn is_24_bits(&self) -> bool { *self == DATALENGTHSELECT_A::_24_BITS } - #[doc = "Checks if the value of the field is `_20_BITS`"] + #[doc = "Data length is set to 20 bits"] #[inline(always)] pub fn is_20_bits(&self) -> bool { *self == DATALENGTHSELECT_A::_20_BITS } - #[doc = "Checks if the value of the field is `_18_BITS`"] + #[doc = "Data length is set to 18 bits"] #[inline(always)] pub fn is_18_bits(&self) -> bool { *self == DATALENGTHSELECT_A::_18_BITS } - #[doc = "Checks if the value of the field is `_16_BITS`"] + #[doc = "Data length is set to 16 bits"] #[inline(always)] pub fn is_16_bits(&self) -> bool { *self == DATALENGTHSELECT_A::_16_BITS } - #[doc = "Checks if the value of the field is `_16_BITS_COMPACT`"] + #[doc = "Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word."] #[inline(always)] pub fn is_16_bits_compact(&self) -> bool { *self == DATALENGTHSELECT_A::_16_BITS_COMPACT } - #[doc = "Checks if the value of the field is `_8_BITS`"] + #[doc = "Data length is set to 8 bits"] #[inline(always)] pub fn is_8_bits(&self) -> bool { *self == DATALENGTHSELECT_A::_8_BITS } - #[doc = "Checks if the value of the field is `_8_BITS_COMPACT`"] + #[doc = "Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word."] #[inline(always)] pub fn is_8_bits_compact(&self) -> bool { *self == DATALENGTHSELECT_A::_8_BITS_COMPACT } } #[doc = "Field `DATALENGTH` writer - Data Word Length"] -pub type DATALENGTH_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, MR_SPEC, 3, O, DATALENGTHSELECT_A>; -impl<'a, const O: u8> DATALENGTH_W<'a, O> { +pub type DATALENGTH_W<'a, REG, const O: u8> = + crate::FieldWriterSafe<'a, REG, 3, O, DATALENGTHSELECT_A>; +impl<'a, REG, const O: u8> DATALENGTH_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Data length is set to 32 bits"] #[inline(always)] - pub fn _32_bits(self) -> &'a mut W { + pub fn _32_bits(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_32_BITS) } #[doc = "Data length is set to 24 bits"] #[inline(always)] - pub fn _24_bits(self) -> &'a mut W { + pub fn _24_bits(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_24_BITS) } #[doc = "Data length is set to 20 bits"] #[inline(always)] - pub fn _20_bits(self) -> &'a mut W { + pub fn _20_bits(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_20_BITS) } #[doc = "Data length is set to 18 bits"] #[inline(always)] - pub fn _18_bits(self) -> &'a mut W { + pub fn _18_bits(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_18_BITS) } #[doc = "Data length is set to 16 bits"] #[inline(always)] - pub fn _16_bits(self) -> &'a mut W { + pub fn _16_bits(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_16_BITS) } #[doc = "Data length is set to 16-bit compact stereo. Left sample in bits 15:0 and right sample in bits 31:16 of same word."] #[inline(always)] - pub fn _16_bits_compact(self) -> &'a mut W { + pub fn _16_bits_compact(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_16_BITS_COMPACT) } #[doc = "Data length is set to 8 bits"] #[inline(always)] - pub fn _8_bits(self) -> &'a mut W { + pub fn _8_bits(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_8_BITS) } #[doc = "Data length is set to 8-bit compact stereo. Left sample in bits 7:0 and right sample in bits 15:8 of the same word."] #[inline(always)] - pub fn _8_bits_compact(self) -> &'a mut W { + pub fn _8_bits_compact(self) -> &'a mut crate::W { self.variant(DATALENGTHSELECT_A::_8_BITS_COMPACT) } } #[doc = "Field `RXMONO` reader - Receive Mono"] pub type RXMONO_R = crate::BitReader; #[doc = "Field `RXMONO` writer - Receive Mono"] -pub type RXMONO_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RXMONO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDMA` reader - Single or Multiple DMA Controller Channels for Receiver"] pub type RXDMA_R = crate::BitReader; #[doc = "Field `RXDMA` writer - Single or Multiple DMA Controller Channels for Receiver"] -pub type RXDMA_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RXDMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXLOOP` reader - Loopback Test Mode"] pub type RXLOOP_R = crate::BitReader; #[doc = "Field `RXLOOP` writer - Loopback Test Mode"] -pub type RXLOOP_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RXLOOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXMONO` reader - Transmit Mono"] pub type TXMONO_R = crate::BitReader; #[doc = "Field `TXMONO` writer - Transmit Mono"] -pub type TXMONO_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type TXMONO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDMA` reader - Single or Multiple DMA Controller Channels for Transmitter"] pub type TXDMA_R = crate::BitReader; #[doc = "Field `TXDMA` writer - Single or Multiple DMA Controller Channels for Transmitter"] -pub type TXDMA_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type TXDMA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSAME` reader - Transmit Data when Underrun"] pub type TXSAME_R = crate::BitReader; #[doc = "Field `TXSAME` writer - Transmit Data when Underrun"] -pub type TXSAME_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type TXSAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IMCKDIV` reader - Selected Clock to I2SC Master Clock Ratio"] pub type IMCKDIV_R = crate::FieldReader; #[doc = "Field `IMCKDIV` writer - Selected Clock to I2SC Master Clock Ratio"] -pub type IMCKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 6, O>; +pub type IMCKDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `IMCKFS` reader - Master Clock to fs Ratio"] pub type IMCKFS_R = crate::FieldReader; #[doc = "Master Clock to fs Ratio\n\nValue on reset: 0"] @@ -306,139 +281,143 @@ impl IMCKFS_R { _ => None, } } - #[doc = "Checks if the value of the field is `M2SF32`"] + #[doc = "Sample frequency ratio set to 32"] #[inline(always)] pub fn is_m2sf32(&self) -> bool { *self == IMCKFSSELECT_A::M2SF32 } - #[doc = "Checks if the value of the field is `M2SF64`"] + #[doc = "Sample frequency ratio set to 64"] #[inline(always)] pub fn is_m2sf64(&self) -> bool { *self == IMCKFSSELECT_A::M2SF64 } - #[doc = "Checks if the value of the field is `M2SF96`"] + #[doc = "Sample frequency ratio set to 96"] #[inline(always)] pub fn is_m2sf96(&self) -> bool { *self == IMCKFSSELECT_A::M2SF96 } - #[doc = "Checks if the value of the field is `M2SF128`"] + #[doc = "Sample frequency ratio set to 128"] #[inline(always)] pub fn is_m2sf128(&self) -> bool { *self == IMCKFSSELECT_A::M2SF128 } - #[doc = "Checks if the value of the field is `M2SF192`"] + #[doc = "Sample frequency ratio set to 192"] #[inline(always)] pub fn is_m2sf192(&self) -> bool { *self == IMCKFSSELECT_A::M2SF192 } - #[doc = "Checks if the value of the field is `M2SF256`"] + #[doc = "Sample frequency ratio set to 256"] #[inline(always)] pub fn is_m2sf256(&self) -> bool { *self == IMCKFSSELECT_A::M2SF256 } - #[doc = "Checks if the value of the field is `M2SF384`"] + #[doc = "Sample frequency ratio set to 384"] #[inline(always)] pub fn is_m2sf384(&self) -> bool { *self == IMCKFSSELECT_A::M2SF384 } - #[doc = "Checks if the value of the field is `M2SF512`"] + #[doc = "Sample frequency ratio set to 512"] #[inline(always)] pub fn is_m2sf512(&self) -> bool { *self == IMCKFSSELECT_A::M2SF512 } - #[doc = "Checks if the value of the field is `M2SF768`"] + #[doc = "Sample frequency ratio set to 768"] #[inline(always)] pub fn is_m2sf768(&self) -> bool { *self == IMCKFSSELECT_A::M2SF768 } - #[doc = "Checks if the value of the field is `M2SF1024`"] + #[doc = "Sample frequency ratio set to 1024"] #[inline(always)] pub fn is_m2sf1024(&self) -> bool { *self == IMCKFSSELECT_A::M2SF1024 } - #[doc = "Checks if the value of the field is `M2SF1536`"] + #[doc = "Sample frequency ratio set to 1536"] #[inline(always)] pub fn is_m2sf1536(&self) -> bool { *self == IMCKFSSELECT_A::M2SF1536 } - #[doc = "Checks if the value of the field is `M2SF2048`"] + #[doc = "Sample frequency ratio set to 2048"] #[inline(always)] pub fn is_m2sf2048(&self) -> bool { *self == IMCKFSSELECT_A::M2SF2048 } } #[doc = "Field `IMCKFS` writer - Master Clock to fs Ratio"] -pub type IMCKFS_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 6, O, IMCKFSSELECT_A>; -impl<'a, const O: u8> IMCKFS_W<'a, O> { +pub type IMCKFS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O, IMCKFSSELECT_A>; +impl<'a, REG, const O: u8> IMCKFS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Sample frequency ratio set to 32"] #[inline(always)] - pub fn m2sf32(self) -> &'a mut W { + pub fn m2sf32(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF32) } #[doc = "Sample frequency ratio set to 64"] #[inline(always)] - pub fn m2sf64(self) -> &'a mut W { + pub fn m2sf64(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF64) } #[doc = "Sample frequency ratio set to 96"] #[inline(always)] - pub fn m2sf96(self) -> &'a mut W { + pub fn m2sf96(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF96) } #[doc = "Sample frequency ratio set to 128"] #[inline(always)] - pub fn m2sf128(self) -> &'a mut W { + pub fn m2sf128(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF128) } #[doc = "Sample frequency ratio set to 192"] #[inline(always)] - pub fn m2sf192(self) -> &'a mut W { + pub fn m2sf192(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF192) } #[doc = "Sample frequency ratio set to 256"] #[inline(always)] - pub fn m2sf256(self) -> &'a mut W { + pub fn m2sf256(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF256) } #[doc = "Sample frequency ratio set to 384"] #[inline(always)] - pub fn m2sf384(self) -> &'a mut W { + pub fn m2sf384(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF384) } #[doc = "Sample frequency ratio set to 512"] #[inline(always)] - pub fn m2sf512(self) -> &'a mut W { + pub fn m2sf512(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF512) } #[doc = "Sample frequency ratio set to 768"] #[inline(always)] - pub fn m2sf768(self) -> &'a mut W { + pub fn m2sf768(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF768) } #[doc = "Sample frequency ratio set to 1024"] #[inline(always)] - pub fn m2sf1024(self) -> &'a mut W { + pub fn m2sf1024(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF1024) } #[doc = "Sample frequency ratio set to 1536"] #[inline(always)] - pub fn m2sf1536(self) -> &'a mut W { + pub fn m2sf1536(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF1536) } #[doc = "Sample frequency ratio set to 2048"] #[inline(always)] - pub fn m2sf2048(self) -> &'a mut W { + pub fn m2sf2048(self) -> &'a mut crate::W { self.variant(IMCKFSSELECT_A::M2SF2048) } } #[doc = "Field `IMCKMODE` reader - Master Clock Mode"] pub type IMCKMODE_R = crate::BitReader; #[doc = "Field `IMCKMODE` writer - Master Clock Mode"] -pub type IMCKMODE_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type IMCKMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IWS` reader - I2SC_WS Slot Width"] pub type IWS_R = crate::BitReader; #[doc = "Field `IWS` writer - I2SC_WS Slot Width"] -pub type IWS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type IWS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Inter-IC Sound Controller Mode"] #[inline(always)] @@ -505,94 +484,91 @@ impl W { #[doc = "Bit 0 - Inter-IC Sound Controller Mode"] #[inline(always)] #[must_use] - pub fn mode(&mut self) -> MODE_W<0> { + pub fn mode(&mut self) -> MODE_W { MODE_W::new(self) } #[doc = "Bits 2:4 - Data Word Length"] #[inline(always)] #[must_use] - pub fn datalength(&mut self) -> DATALENGTH_W<2> { + pub fn datalength(&mut self) -> DATALENGTH_W { DATALENGTH_W::new(self) } #[doc = "Bit 8 - Receive Mono"] #[inline(always)] #[must_use] - pub fn rxmono(&mut self) -> RXMONO_W<8> { + pub fn rxmono(&mut self) -> RXMONO_W { RXMONO_W::new(self) } #[doc = "Bit 9 - Single or Multiple DMA Controller Channels for Receiver"] #[inline(always)] #[must_use] - pub fn rxdma(&mut self) -> RXDMA_W<9> { + pub fn rxdma(&mut self) -> RXDMA_W { RXDMA_W::new(self) } #[doc = "Bit 10 - Loopback Test Mode"] #[inline(always)] #[must_use] - pub fn rxloop(&mut self) -> RXLOOP_W<10> { + pub fn rxloop(&mut self) -> RXLOOP_W { RXLOOP_W::new(self) } #[doc = "Bit 12 - Transmit Mono"] #[inline(always)] #[must_use] - pub fn txmono(&mut self) -> TXMONO_W<12> { + pub fn txmono(&mut self) -> TXMONO_W { TXMONO_W::new(self) } #[doc = "Bit 13 - Single or Multiple DMA Controller Channels for Transmitter"] #[inline(always)] #[must_use] - pub fn txdma(&mut self) -> TXDMA_W<13> { + pub fn txdma(&mut self) -> TXDMA_W { TXDMA_W::new(self) } #[doc = "Bit 14 - Transmit Data when Underrun"] #[inline(always)] #[must_use] - pub fn txsame(&mut self) -> TXSAME_W<14> { + pub fn txsame(&mut self) -> TXSAME_W { TXSAME_W::new(self) } #[doc = "Bits 16:21 - Selected Clock to I2SC Master Clock Ratio"] #[inline(always)] #[must_use] - pub fn imckdiv(&mut self) -> IMCKDIV_W<16> { + pub fn imckdiv(&mut self) -> IMCKDIV_W { IMCKDIV_W::new(self) } #[doc = "Bits 24:29 - Master Clock to fs Ratio"] #[inline(always)] #[must_use] - pub fn imckfs(&mut self) -> IMCKFS_W<24> { + pub fn imckfs(&mut self) -> IMCKFS_W { IMCKFS_W::new(self) } #[doc = "Bit 30 - Master Clock Mode"] #[inline(always)] #[must_use] - pub fn imckmode(&mut self) -> IMCKMODE_W<30> { + pub fn imckmode(&mut self) -> IMCKMODE_W { IMCKMODE_W::new(self) } #[doc = "Bit 31 - I2SC_WS Slot Width"] #[inline(always)] #[must_use] - pub fn iws(&mut self) -> IWS_W<31> { + pub fn iws(&mut self) -> IWS_W { IWS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/rhr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/rhr.rs index 30057cdc..194e537f 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/rhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/rhr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RHR` reader - Receiver Holding Register"] pub type RHR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RHR_R::new(self.bits) } } -#[doc = "Receiver Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rhr](index.html) module"] +#[doc = "Receiver Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RHR_SPEC; impl crate::RegisterSpec for RHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rhr::R](R) reader structure"] -impl crate::Readable for RHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rhr::R`](R) reader structure"] +impl crate::Readable for RHR_SPEC {} #[doc = "`reset()` method sets RHR to value 0"] impl crate::Resettable for RHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/scr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/scr.rs index bd927b70..5630157f 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/scr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/scr.rs @@ -1,72 +1,52 @@ #[doc = "Register `SCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXOR` writer - Receive Overrun Status Clear"] -pub type RXOR_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type RXOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUR` writer - Transmit Underrun Status Clear"] -pub type TXUR_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type TXUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXORCH` writer - Receive Overrun Per Channel Status Clear"] -pub type RXORCH_W<'a, const O: u8> = crate::FieldWriter<'a, SCR_SPEC, 2, O>; +pub type RXORCH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `TXURCH` writer - Transmit Underrun Per Channel Status Clear"] -pub type TXURCH_W<'a, const O: u8> = crate::FieldWriter<'a, SCR_SPEC, 2, O>; +pub type TXURCH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl W { #[doc = "Bit 2 - Receive Overrun Status Clear"] #[inline(always)] #[must_use] - pub fn rxor(&mut self) -> RXOR_W<2> { + pub fn rxor(&mut self) -> RXOR_W { RXOR_W::new(self) } #[doc = "Bit 6 - Transmit Underrun Status Clear"] #[inline(always)] #[must_use] - pub fn txur(&mut self) -> TXUR_W<6> { + pub fn txur(&mut self) -> TXUR_W { TXUR_W::new(self) } #[doc = "Bits 8:9 - Receive Overrun Per Channel Status Clear"] #[inline(always)] #[must_use] - pub fn rxorch(&mut self) -> RXORCH_W<8> { + pub fn rxorch(&mut self) -> RXORCH_W { RXORCH_W::new(self) } #[doc = "Bits 20:21 - Transmit Underrun Per Channel Status Clear"] #[inline(always)] #[must_use] - pub fn txurch(&mut self) -> TXURCH_W<20> { + pub fn txurch(&mut self) -> TXURCH_W { TXURCH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +#[doc = "Status Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCR_SPEC; impl crate::RegisterSpec for SCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] impl crate::Writable for SCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/sr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/sr.rs index 21783cc1..dfefb3a9 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXEN` reader - Receiver Enabled"] pub type RXEN_R = crate::BitReader; #[doc = "Field `RXRDY` reader - Receive Ready"] @@ -71,15 +58,13 @@ impl R { TXURCH_R::new(((self.bits >> 20) & 3) as u8) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/ssr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/ssr.rs index 23ab64df..bff19f8c 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/ssr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/ssr.rs @@ -1,72 +1,52 @@ #[doc = "Register `SSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXOR` writer - Receive Overrun Status Set"] -pub type RXOR_W<'a, const O: u8> = crate::BitWriter<'a, SSR_SPEC, O>; +pub type RXOR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXUR` writer - Transmit Underrun Status Set"] -pub type TXUR_W<'a, const O: u8> = crate::BitWriter<'a, SSR_SPEC, O>; +pub type TXUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXORCH` writer - Receive Overrun Per Channel Status Set"] -pub type RXORCH_W<'a, const O: u8> = crate::FieldWriter<'a, SSR_SPEC, 2, O>; +pub type RXORCH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `TXURCH` writer - Transmit Underrun Per Channel Status Set"] -pub type TXURCH_W<'a, const O: u8> = crate::FieldWriter<'a, SSR_SPEC, 2, O>; +pub type TXURCH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl W { #[doc = "Bit 2 - Receive Overrun Status Set"] #[inline(always)] #[must_use] - pub fn rxor(&mut self) -> RXOR_W<2> { + pub fn rxor(&mut self) -> RXOR_W { RXOR_W::new(self) } #[doc = "Bit 6 - Transmit Underrun Status Set"] #[inline(always)] #[must_use] - pub fn txur(&mut self) -> TXUR_W<6> { + pub fn txur(&mut self) -> TXUR_W { TXUR_W::new(self) } #[doc = "Bits 8:9 - Receive Overrun Per Channel Status Set"] #[inline(always)] #[must_use] - pub fn rxorch(&mut self) -> RXORCH_W<8> { + pub fn rxorch(&mut self) -> RXORCH_W { RXORCH_W::new(self) } #[doc = "Bits 20:21 - Transmit Underrun Per Channel Status Set"] #[inline(always)] #[must_use] - pub fn txurch(&mut self) -> TXURCH_W<20> { + pub fn txurch(&mut self) -> TXURCH_W { TXURCH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ssr](index.html) module"] +#[doc = "Status Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ssr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSR_SPEC; impl crate::RegisterSpec for SSR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ssr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ssr::W`](W) writer structure"] impl crate::Writable for SSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/i2sc0/thr.rs b/arch/cortex-m/samv71q21-pac/src/i2sc0/thr.rs index e0b5d155..eecd7e8a 100644 --- a/arch/cortex-m/samv71q21-pac/src/i2sc0/thr.rs +++ b/arch/cortex-m/samv71q21-pac/src/i2sc0/thr.rs @@ -1,48 +1,28 @@ #[doc = "Register `THR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `THR` writer - Transmitter Holding Register"] -pub type THR_W<'a, const O: u8> = crate::FieldWriter<'a, THR_SPEC, 32, O, u32>; +pub type THR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Transmitter Holding Register"] #[inline(always)] #[must_use] - pub fn thr(&mut self) -> THR_W<0> { + pub fn thr(&mut self) -> THR_W { THR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmitter Holding Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [thr](index.html) module"] +#[doc = "Transmitter Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct THR_SPEC; impl crate::RegisterSpec for THR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [thr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`thr::W`](W) writer structure"] impl crate::Writable for THR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm.rs b/arch/cortex-m/samv71q21-pac/src/icm.rs index 02776e11..58ad0e69 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm.rs @@ -26,47 +26,57 @@ pub struct RegisterBlock { #[doc = "0x38..0x58 - User Initial Hash Value 0 Register 0"] pub uihval: [UIHVAL; 8], } -#[doc = "CFG (rw) register accessor: an alias for `Reg`"] +#[doc = "CFG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub type CFG = crate::Reg; #[doc = "Configuration Register"] pub mod cfg; -#[doc = "CTRL (w) register accessor: an alias for `Reg`"] +#[doc = "CTRL (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "Control Register"] pub mod ctrl; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "UASR (r) register accessor: an alias for `Reg`"] +#[doc = "UASR (r) register accessor: Undefined Access Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uasr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`uasr`] +module"] pub type UASR = crate::Reg; #[doc = "Undefined Access Status Register"] pub mod uasr; -#[doc = "DSCR (rw) register accessor: an alias for `Reg`"] +#[doc = "DSCR (rw) register accessor: Region Descriptor Area Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dscr`] +module"] pub type DSCR = crate::Reg; #[doc = "Region Descriptor Area Start Address Register"] pub mod dscr; -#[doc = "HASH (rw) register accessor: an alias for `Reg`"] +#[doc = "HASH (rw) register accessor: Region Hash Area Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hash::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hash::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hash`] +module"] pub type HASH = crate::Reg; #[doc = "Region Hash Area Start Address Register"] pub mod hash; -#[doc = "UIHVAL (w) register accessor: an alias for `Reg`"] +#[doc = "UIHVAL (w) register accessor: User Initial Hash Value 0 Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uihval::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`uihval`] +module"] pub type UIHVAL = crate::Reg; #[doc = "User Initial Hash Value 0 Register 0"] pub mod uihval; diff --git a/arch/cortex-m/samv71q21-pac/src/icm/cfg.rs b/arch/cortex-m/samv71q21-pac/src/icm/cfg.rs index d95ed8d4..2982305e 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/cfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/cfg.rs @@ -1,67 +1,35 @@ #[doc = "Register `CFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WBDIS` reader - Write Back Disable"] pub type WBDIS_R = crate::BitReader; #[doc = "Field `WBDIS` writer - Write Back Disable"] -pub type WBDIS_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type WBDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOMDIS` reader - End of Monitoring Disable"] pub type EOMDIS_R = crate::BitReader; #[doc = "Field `EOMDIS` writer - End of Monitoring Disable"] -pub type EOMDIS_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type EOMDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SLBDIS` reader - Secondary List Branching Disable"] pub type SLBDIS_R = crate::BitReader; #[doc = "Field `SLBDIS` writer - Secondary List Branching Disable"] -pub type SLBDIS_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type SLBDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BBC` reader - Bus Burden Control"] pub type BBC_R = crate::FieldReader; #[doc = "Field `BBC` writer - Bus Burden Control"] -pub type BBC_W<'a, const O: u8> = crate::FieldWriter<'a, CFG_SPEC, 4, O>; +pub type BBC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `ASCD` reader - Automatic Switch To Compare Digest"] pub type ASCD_R = crate::BitReader; #[doc = "Field `ASCD` writer - Automatic Switch To Compare Digest"] -pub type ASCD_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type ASCD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DUALBUFF` reader - Dual Input Buffer"] pub type DUALBUFF_R = crate::BitReader; #[doc = "Field `DUALBUFF` writer - Dual Input Buffer"] -pub type DUALBUFF_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type DUALBUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UIHASH` reader - User Initial Hash Value"] pub type UIHASH_R = crate::BitReader; #[doc = "Field `UIHASH` writer - User Initial Hash Value"] -pub type UIHASH_W<'a, const O: u8> = crate::BitWriter<'a, CFG_SPEC, O>; +pub type UIHASH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UALGO` reader - User SHA Algorithm"] pub type UALGO_R = crate::FieldReader; #[doc = "User SHA Algorithm\n\nValue on reset: 0"] @@ -95,38 +63,42 @@ impl UALGO_R { _ => None, } } - #[doc = "Checks if the value of the field is `SHA1`"] + #[doc = "SHA1 algorithm processed"] #[inline(always)] pub fn is_sha1(&self) -> bool { *self == UALGOSELECT_A::SHA1 } - #[doc = "Checks if the value of the field is `SHA256`"] + #[doc = "SHA256 algorithm processed"] #[inline(always)] pub fn is_sha256(&self) -> bool { *self == UALGOSELECT_A::SHA256 } - #[doc = "Checks if the value of the field is `SHA224`"] + #[doc = "SHA224 algorithm processed"] #[inline(always)] pub fn is_sha224(&self) -> bool { *self == UALGOSELECT_A::SHA224 } } #[doc = "Field `UALGO` writer - User SHA Algorithm"] -pub type UALGO_W<'a, const O: u8> = crate::FieldWriter<'a, CFG_SPEC, 3, O, UALGOSELECT_A>; -impl<'a, const O: u8> UALGO_W<'a, O> { +pub type UALGO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, UALGOSELECT_A>; +impl<'a, REG, const O: u8> UALGO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "SHA1 algorithm processed"] #[inline(always)] - pub fn sha1(self) -> &'a mut W { + pub fn sha1(self) -> &'a mut crate::W { self.variant(UALGOSELECT_A::SHA1) } #[doc = "SHA256 algorithm processed"] #[inline(always)] - pub fn sha256(self) -> &'a mut W { + pub fn sha256(self) -> &'a mut crate::W { self.variant(UALGOSELECT_A::SHA256) } #[doc = "SHA224 algorithm processed"] #[inline(always)] - pub fn sha224(self) -> &'a mut W { + pub fn sha224(self) -> &'a mut crate::W { self.variant(UALGOSELECT_A::SHA224) } } @@ -176,70 +148,67 @@ impl W { #[doc = "Bit 0 - Write Back Disable"] #[inline(always)] #[must_use] - pub fn wbdis(&mut self) -> WBDIS_W<0> { + pub fn wbdis(&mut self) -> WBDIS_W { WBDIS_W::new(self) } #[doc = "Bit 1 - End of Monitoring Disable"] #[inline(always)] #[must_use] - pub fn eomdis(&mut self) -> EOMDIS_W<1> { + pub fn eomdis(&mut self) -> EOMDIS_W { EOMDIS_W::new(self) } #[doc = "Bit 2 - Secondary List Branching Disable"] #[inline(always)] #[must_use] - pub fn slbdis(&mut self) -> SLBDIS_W<2> { + pub fn slbdis(&mut self) -> SLBDIS_W { SLBDIS_W::new(self) } #[doc = "Bits 4:7 - Bus Burden Control"] #[inline(always)] #[must_use] - pub fn bbc(&mut self) -> BBC_W<4> { + pub fn bbc(&mut self) -> BBC_W { BBC_W::new(self) } #[doc = "Bit 8 - Automatic Switch To Compare Digest"] #[inline(always)] #[must_use] - pub fn ascd(&mut self) -> ASCD_W<8> { + pub fn ascd(&mut self) -> ASCD_W { ASCD_W::new(self) } #[doc = "Bit 9 - Dual Input Buffer"] #[inline(always)] #[must_use] - pub fn dualbuff(&mut self) -> DUALBUFF_W<9> { + pub fn dualbuff(&mut self) -> DUALBUFF_W { DUALBUFF_W::new(self) } #[doc = "Bit 12 - User Initial Hash Value"] #[inline(always)] #[must_use] - pub fn uihash(&mut self) -> UIHASH_W<12> { + pub fn uihash(&mut self) -> UIHASH_W { UIHASH_W::new(self) } #[doc = "Bits 13:15 - User SHA Algorithm"] #[inline(always)] #[must_use] - pub fn ualgo(&mut self) -> UALGO_W<13> { + pub fn ualgo(&mut self) -> UALGO_W { UALGO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +#[doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG_SPEC; impl crate::RegisterSpec for CFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cfg::R](R) reader structure"] -impl crate::Readable for CFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cfg::W](W) writer structure"] +#[doc = "`read()` method returns [`cfg::R`](R) reader structure"] +impl crate::Readable for CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] impl crate::Writable for CFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm/ctrl.rs b/arch/cortex-m/samv71q21-pac/src/icm/ctrl.rs index bd097664..79d99783 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/ctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/ctrl.rs @@ -1,88 +1,68 @@ #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` writer - ICM Enable"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISABLE` writer - ICM Disable Register"] -pub type DISABLE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type DISABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REHASH` writer - Recompute Internal Hash"] -pub type REHASH_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 4, O>; +pub type REHASH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RMDIS` writer - Region Monitoring Disable"] -pub type RMDIS_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 4, O>; +pub type RMDIS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RMEN` writer - Region Monitoring Enable"] -pub type RMEN_W<'a, const O: u8> = crate::FieldWriter<'a, CTRL_SPEC, 4, O>; +pub type RMEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl W { #[doc = "Bit 0 - ICM Enable"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 1 - ICM Disable Register"] #[inline(always)] #[must_use] - pub fn disable(&mut self) -> DISABLE_W<1> { + pub fn disable(&mut self) -> DISABLE_W { DISABLE_W::new(self) } #[doc = "Bit 2 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<2> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Bits 4:7 - Recompute Internal Hash"] #[inline(always)] #[must_use] - pub fn rehash(&mut self) -> REHASH_W<4> { + pub fn rehash(&mut self) -> REHASH_W { REHASH_W::new(self) } #[doc = "Bits 8:11 - Region Monitoring Disable"] #[inline(always)] #[must_use] - pub fn rmdis(&mut self) -> RMDIS_W<8> { + pub fn rmdis(&mut self) -> RMDIS_W { RMDIS_W::new(self) } #[doc = "Bits 12:15 - Region Monitoring Enable"] #[inline(always)] #[must_use] - pub fn rmen(&mut self) -> RMEN_W<12> { + pub fn rmen(&mut self) -> RMEN_W { RMEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm/dscr.rs b/arch/cortex-m/samv71q21-pac/src/icm/dscr.rs index b764897f..ad676f94 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/dscr.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/dscr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DSCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DSCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DASA` reader - Descriptor Area Start Address"] pub type DASA_R = crate::FieldReader; #[doc = "Field `DASA` writer - Descriptor Area Start Address"] -pub type DASA_W<'a, const O: u8> = crate::FieldWriter<'a, DSCR_SPEC, 26, O, u32>; +pub type DASA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 26, O, u32>; impl R { #[doc = "Bits 6:31 - Descriptor Area Start Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 6:31 - Descriptor Area Start Address"] #[inline(always)] #[must_use] - pub fn dasa(&mut self) -> DASA_W<6> { + pub fn dasa(&mut self) -> DASA_W { DASA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Region Descriptor Area Start Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dscr](index.html) module"] +#[doc = "Region Descriptor Area Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DSCR_SPEC; impl crate::RegisterSpec for DSCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dscr::R](R) reader structure"] -impl crate::Readable for DSCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dscr::W](W) writer structure"] +#[doc = "`read()` method returns [`dscr::R`](R) reader structure"] +impl crate::Readable for DSCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dscr::W`](W) writer structure"] impl crate::Writable for DSCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm/hash.rs b/arch/cortex-m/samv71q21-pac/src/icm/hash.rs index 00000e19..e9f6a132 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/hash.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/hash.rs @@ -1,43 +1,11 @@ #[doc = "Register `HASH` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HASH` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HASA` reader - Hash Area Start Address"] pub type HASA_R = crate::FieldReader; #[doc = "Field `HASA` writer - Hash Area Start Address"] -pub type HASA_W<'a, const O: u8> = crate::FieldWriter<'a, HASH_SPEC, 25, O, u32>; +pub type HASA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 25, O, u32>; impl R { #[doc = "Bits 7:31 - Hash Area Start Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 7:31 - Hash Area Start Address"] #[inline(always)] #[must_use] - pub fn hasa(&mut self) -> HASA_W<7> { + pub fn hasa(&mut self) -> HASA_W { HASA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Region Hash Area Start Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hash](index.html) module"] +#[doc = "Region Hash Area Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hash::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hash::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HASH_SPEC; impl crate::RegisterSpec for HASH_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hash::R](R) reader structure"] -impl crate::Readable for HASH_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hash::W](W) writer structure"] +#[doc = "`read()` method returns [`hash::R`](R) reader structure"] +impl crate::Readable for HASH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hash::W`](W) writer structure"] impl crate::Writable for HASH_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm/idr.rs b/arch/cortex-m/samv71q21-pac/src/icm/idr.rs index d03d2d0a..4de106cb 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/idr.rs @@ -1,96 +1,76 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RHC` writer - Region Hash Completed Interrupt Disable"] -pub type RHC_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 4, O>; +pub type RHC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RDM` writer - Region Digest Mismatch Interrupt Disable"] -pub type RDM_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 4, O>; +pub type RDM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RBE` writer - Region Bus Error Interrupt Disable"] -pub type RBE_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 4, O>; +pub type RBE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RWC` writer - Region Wrap Condition Detected Interrupt Disable"] -pub type RWC_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 4, O>; +pub type RWC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `REC` writer - Region End bit Condition detected Interrupt Disable"] -pub type REC_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 4, O>; +pub type REC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RSU` writer - Region Status Updated Interrupt Disable"] -pub type RSU_W<'a, const O: u8> = crate::FieldWriter<'a, IDR_SPEC, 4, O>; +pub type RSU_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `URAD` writer - Undefined Register Access Detection Interrupt Disable"] -pub type URAD_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type URAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:3 - Region Hash Completed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rhc(&mut self) -> RHC_W<0> { + pub fn rhc(&mut self) -> RHC_W { RHC_W::new(self) } #[doc = "Bits 4:7 - Region Digest Mismatch Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rdm(&mut self) -> RDM_W<4> { + pub fn rdm(&mut self) -> RDM_W { RDM_W::new(self) } #[doc = "Bits 8:11 - Region Bus Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rbe(&mut self) -> RBE_W<8> { + pub fn rbe(&mut self) -> RBE_W { RBE_W::new(self) } #[doc = "Bits 12:15 - Region Wrap Condition Detected Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rwc(&mut self) -> RWC_W<12> { + pub fn rwc(&mut self) -> RWC_W { RWC_W::new(self) } #[doc = "Bits 16:19 - Region End bit Condition detected Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rec(&mut self) -> REC_W<16> { + pub fn rec(&mut self) -> REC_W { REC_W::new(self) } #[doc = "Bits 20:23 - Region Status Updated Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rsu(&mut self) -> RSU_W<20> { + pub fn rsu(&mut self) -> RSU_W { RSU_W::new(self) } #[doc = "Bit 24 - Undefined Register Access Detection Interrupt Disable"] #[inline(always)] #[must_use] - pub fn urad(&mut self) -> URAD_W<24> { + pub fn urad(&mut self) -> URAD_W { URAD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm/ier.rs b/arch/cortex-m/samv71q21-pac/src/icm/ier.rs index 7bd665b8..eb86024a 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/ier.rs @@ -1,96 +1,76 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RHC` writer - Region Hash Completed Interrupt Enable"] -pub type RHC_W<'a, const O: u8> = crate::FieldWriter<'a, IER_SPEC, 4, O>; +pub type RHC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RDM` writer - Region Digest Mismatch Interrupt Enable"] -pub type RDM_W<'a, const O: u8> = crate::FieldWriter<'a, IER_SPEC, 4, O>; +pub type RDM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RBE` writer - Region Bus Error Interrupt Enable"] -pub type RBE_W<'a, const O: u8> = crate::FieldWriter<'a, IER_SPEC, 4, O>; +pub type RBE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RWC` writer - Region Wrap Condition detected Interrupt Enable"] -pub type RWC_W<'a, const O: u8> = crate::FieldWriter<'a, IER_SPEC, 4, O>; +pub type RWC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `REC` writer - Region End bit Condition Detected Interrupt Enable"] -pub type REC_W<'a, const O: u8> = crate::FieldWriter<'a, IER_SPEC, 4, O>; +pub type REC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RSU` writer - Region Status Updated Interrupt Disable"] -pub type RSU_W<'a, const O: u8> = crate::FieldWriter<'a, IER_SPEC, 4, O>; +pub type RSU_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `URAD` writer - Undefined Register Access Detection Interrupt Enable"] -pub type URAD_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type URAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:3 - Region Hash Completed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rhc(&mut self) -> RHC_W<0> { + pub fn rhc(&mut self) -> RHC_W { RHC_W::new(self) } #[doc = "Bits 4:7 - Region Digest Mismatch Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rdm(&mut self) -> RDM_W<4> { + pub fn rdm(&mut self) -> RDM_W { RDM_W::new(self) } #[doc = "Bits 8:11 - Region Bus Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rbe(&mut self) -> RBE_W<8> { + pub fn rbe(&mut self) -> RBE_W { RBE_W::new(self) } #[doc = "Bits 12:15 - Region Wrap Condition detected Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rwc(&mut self) -> RWC_W<12> { + pub fn rwc(&mut self) -> RWC_W { RWC_W::new(self) } #[doc = "Bits 16:19 - Region End bit Condition Detected Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rec(&mut self) -> REC_W<16> { + pub fn rec(&mut self) -> REC_W { REC_W::new(self) } #[doc = "Bits 20:23 - Region Status Updated Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rsu(&mut self) -> RSU_W<20> { + pub fn rsu(&mut self) -> RSU_W { RSU_W::new(self) } #[doc = "Bit 24 - Undefined Register Access Detection Interrupt Enable"] #[inline(always)] #[must_use] - pub fn urad(&mut self) -> URAD_W<24> { + pub fn urad(&mut self) -> URAD_W { URAD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/icm/imr.rs b/arch/cortex-m/samv71q21-pac/src/icm/imr.rs index a9f36a07..4a8cdaad 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RHC` reader - Region Hash Completed Interrupt Mask"] pub type RHC_R = crate::FieldReader; #[doc = "Field `RDM` reader - Region Digest Mismatch Interrupt Mask"] @@ -64,15 +51,13 @@ impl R { URAD_R::new(((self.bits >> 24) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/icm/isr.rs b/arch/cortex-m/samv71q21-pac/src/icm/isr.rs index 2916c571..df73d6c4 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RHC` reader - Region Hash Completed"] pub type RHC_R = crate::FieldReader; #[doc = "Field `RDM` reader - Region Digest Mismatch"] @@ -64,15 +51,13 @@ impl R { URAD_R::new(((self.bits >> 24) & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/icm/sr.rs b/arch/cortex-m/samv71q21-pac/src/icm/sr.rs index 695aac45..ce62e438 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ENABLE` reader - ICM Controller Enable Register"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `RAWRMDIS` reader - Region Monitoring Disabled Raw Status"] @@ -36,15 +23,13 @@ impl R { RMDIS_R::new(((self.bits >> 12) & 0x0f) as u8) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/icm/uasr.rs b/arch/cortex-m/samv71q21-pac/src/icm/uasr.rs index 81bebc6a..6b540d87 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/uasr.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/uasr.rs @@ -1,18 +1,5 @@ #[doc = "Register `UASR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `URAT` reader - Undefined Register Access Trace"] pub type URAT_R = crate::FieldReader; #[doc = "Undefined Register Access Trace\n\nValue on reset: 0"] @@ -52,27 +39,27 @@ impl URAT_R { _ => None, } } - #[doc = "Checks if the value of the field is `UNSPEC_STRUCT_MEMBER`"] + #[doc = "Unspecified structure member set to one detected when the descriptor is loaded."] #[inline(always)] pub fn is_unspec_struct_member(&self) -> bool { *self == URATSELECT_A::UNSPEC_STRUCT_MEMBER } - #[doc = "Checks if the value of the field is `ICM_CFG_MODIFIED`"] + #[doc = "ICM_CFG modified during active monitoring."] #[inline(always)] pub fn is_icm_cfg_modified(&self) -> bool { *self == URATSELECT_A::ICM_CFG_MODIFIED } - #[doc = "Checks if the value of the field is `ICM_DSCR_MODIFIED`"] + #[doc = "ICM_DSCR modified during active monitoring."] #[inline(always)] pub fn is_icm_dscr_modified(&self) -> bool { *self == URATSELECT_A::ICM_DSCR_MODIFIED } - #[doc = "Checks if the value of the field is `ICM_HASH_MODIFIED`"] + #[doc = "ICM_HASH modified during active monitoring"] #[inline(always)] pub fn is_icm_hash_modified(&self) -> bool { *self == URATSELECT_A::ICM_HASH_MODIFIED } - #[doc = "Checks if the value of the field is `READ_ACCESS`"] + #[doc = "Write-only register read access"] #[inline(always)] pub fn is_read_access(&self) -> bool { *self == URATSELECT_A::READ_ACCESS @@ -85,15 +72,13 @@ impl R { URAT_R::new((self.bits & 7) as u8) } } -#[doc = "Undefined Access Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uasr](index.html) module"] +#[doc = "Undefined Access Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uasr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UASR_SPEC; impl crate::RegisterSpec for UASR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [uasr::R](R) reader structure"] -impl crate::Readable for UASR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`uasr::R`](R) reader structure"] +impl crate::Readable for UASR_SPEC {} #[doc = "`reset()` method sets UASR to value 0"] impl crate::Resettable for UASR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/icm/uihval.rs b/arch/cortex-m/samv71q21-pac/src/icm/uihval.rs index 8a76fe44..eae7d93a 100644 --- a/arch/cortex-m/samv71q21-pac/src/icm/uihval.rs +++ b/arch/cortex-m/samv71q21-pac/src/icm/uihval.rs @@ -1,48 +1,28 @@ #[doc = "Register `UIHVAL[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VAL` writer - Initial Hash Value"] -pub type VAL_W<'a, const O: u8> = crate::FieldWriter<'a, UIHVAL_SPEC, 32, O, u32>; +pub type VAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Initial Hash Value"] #[inline(always)] #[must_use] - pub fn val(&mut self) -> VAL_W<0> { + pub fn val(&mut self) -> VAL_W { VAL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "User Initial Hash Value 0 Register 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uihval](index.html) module"] +#[doc = "User Initial Hash Value 0 Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uihval::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct UIHVAL_SPEC; impl crate::RegisterSpec for UIHVAL_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [uihval::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`uihval::W`](W) writer structure"] impl crate::Writable for UIHVAL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi.rs b/arch/cortex-m/samv71q21-pac/src/isi.rs index e8341c3a..bef233b9 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi.rs @@ -53,103 +53,128 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CFG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "CFG1 (rw) register accessor: ISI Configuration 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cfg1`] +module"] pub type CFG1 = crate::Reg; #[doc = "ISI Configuration 1 Register"] pub mod cfg1; -#[doc = "CFG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "CFG2 (rw) register accessor: ISI Configuration 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cfg2`] +module"] pub type CFG2 = crate::Reg; #[doc = "ISI Configuration 2 Register"] pub mod cfg2; -#[doc = "PSIZE (rw) register accessor: an alias for `Reg`"] +#[doc = "PSIZE (rw) register accessor: ISI Preview Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psize::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psize::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`psize`] +module"] pub type PSIZE = crate::Reg; #[doc = "ISI Preview Size Register"] pub mod psize; -#[doc = "PDECF (rw) register accessor: an alias for `Reg`"] +#[doc = "PDECF (rw) register accessor: ISI Preview Decimation Factor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdecf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdecf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdecf`] +module"] pub type PDECF = crate::Reg; #[doc = "ISI Preview Decimation Factor Register"] pub mod pdecf; -#[doc = "Y2R_SET0 (rw) register accessor: an alias for `Reg`"] +#[doc = "Y2R_SET0 (rw) register accessor: ISI Color Space Conversion YCrCb To RGB Set 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y2r_set0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y2r_set0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`y2r_set0`] +module"] pub type Y2R_SET0 = crate::Reg; #[doc = "ISI Color Space Conversion YCrCb To RGB Set 0 Register"] pub mod y2r_set0; -#[doc = "Y2R_SET1 (rw) register accessor: an alias for `Reg`"] +#[doc = "Y2R_SET1 (rw) register accessor: ISI Color Space Conversion YCrCb To RGB Set 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y2r_set1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y2r_set1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`y2r_set1`] +module"] pub type Y2R_SET1 = crate::Reg; #[doc = "ISI Color Space Conversion YCrCb To RGB Set 1 Register"] pub mod y2r_set1; -#[doc = "R2Y_SET0 (rw) register accessor: an alias for `Reg`"] +#[doc = "R2Y_SET0 (rw) register accessor: ISI Color Space Conversion RGB To YCrCb Set 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2y_set0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2y_set0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`r2y_set0`] +module"] pub type R2Y_SET0 = crate::Reg; #[doc = "ISI Color Space Conversion RGB To YCrCb Set 0 Register"] pub mod r2y_set0; -#[doc = "R2Y_SET1 (rw) register accessor: an alias for `Reg`"] +#[doc = "R2Y_SET1 (rw) register accessor: ISI Color Space Conversion RGB To YCrCb Set 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2y_set1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2y_set1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`r2y_set1`] +module"] pub type R2Y_SET1 = crate::Reg; #[doc = "ISI Color Space Conversion RGB To YCrCb Set 1 Register"] pub mod r2y_set1; -#[doc = "R2Y_SET2 (rw) register accessor: an alias for `Reg`"] +#[doc = "R2Y_SET2 (rw) register accessor: ISI Color Space Conversion RGB To YCrCb Set 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2y_set2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2y_set2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`r2y_set2`] +module"] pub type R2Y_SET2 = crate::Reg; #[doc = "ISI Color Space Conversion RGB To YCrCb Set 2 Register"] pub mod r2y_set2; -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: ISI Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "ISI Control Register"] pub mod cr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: ISI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "ISI Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: ISI Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "ISI Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: ISI Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "ISI Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: ISI Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "ISI Interrupt Mask Register"] pub mod imr; -#[doc = "DMA_CHER (w) register accessor: an alias for `Reg`"] +#[doc = "DMA_CHER (w) register accessor: DMA Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_cher::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_cher`] +module"] pub type DMA_CHER = crate::Reg; #[doc = "DMA Channel Enable Register"] pub mod dma_cher; -#[doc = "DMA_CHDR (w) register accessor: an alias for `Reg`"] +#[doc = "DMA_CHDR (w) register accessor: DMA Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_chdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_chdr`] +module"] pub type DMA_CHDR = crate::Reg; #[doc = "DMA Channel Disable Register"] pub mod dma_chdr; -#[doc = "DMA_CHSR (r) register accessor: an alias for `Reg`"] +#[doc = "DMA_CHSR (r) register accessor: DMA Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_chsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_chsr`] +module"] pub type DMA_CHSR = crate::Reg; #[doc = "DMA Channel Status Register"] pub mod dma_chsr; -#[doc = "DMA_P_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA_P_ADDR (rw) register accessor: DMA Preview Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_p_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_p_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_p_addr`] +module"] pub type DMA_P_ADDR = crate::Reg; #[doc = "DMA Preview Base Address Register"] pub mod dma_p_addr; -#[doc = "DMA_P_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA_P_CTRL (rw) register accessor: DMA Preview Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_p_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_p_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_p_ctrl`] +module"] pub type DMA_P_CTRL = crate::Reg; #[doc = "DMA Preview Control Register"] pub mod dma_p_ctrl; -#[doc = "DMA_P_DSCR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA_P_DSCR (rw) register accessor: DMA Preview Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_p_dscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_p_dscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_p_dscr`] +module"] pub type DMA_P_DSCR = crate::Reg; #[doc = "DMA Preview Descriptor Address Register"] pub mod dma_p_dscr; -#[doc = "DMA_C_ADDR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA_C_ADDR (rw) register accessor: DMA Codec Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_c_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_c_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_c_addr`] +module"] pub type DMA_C_ADDR = crate::Reg; #[doc = "DMA Codec Base Address Register"] pub mod dma_c_addr; -#[doc = "DMA_C_CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA_C_CTRL (rw) register accessor: DMA Codec Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_c_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_c_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_c_ctrl`] +module"] pub type DMA_C_CTRL = crate::Reg; #[doc = "DMA Codec Control Register"] pub mod dma_c_ctrl; -#[doc = "DMA_C_DSCR (rw) register accessor: an alias for `Reg`"] +#[doc = "DMA_C_DSCR (rw) register accessor: DMA Codec Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_c_dscr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_c_dscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dma_c_dscr`] +module"] pub type DMA_C_DSCR = crate::Reg; #[doc = "DMA Codec Descriptor Address Register"] pub mod dma_c_dscr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/isi/cfg1.rs b/arch/cortex-m/samv71q21-pac/src/isi/cfg1.rs index 3d5c9d0b..462f9c32 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/cfg1.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/cfg1.rs @@ -1,75 +1,43 @@ #[doc = "Register `CFG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CFG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HSYNC_POL` reader - Horizontal Synchronization Polarity"] pub type HSYNC_POL_R = crate::BitReader; #[doc = "Field `HSYNC_POL` writer - Horizontal Synchronization Polarity"] -pub type HSYNC_POL_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type HSYNC_POL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VSYNC_POL` reader - Vertical Synchronization Polarity"] pub type VSYNC_POL_R = crate::BitReader; #[doc = "Field `VSYNC_POL` writer - Vertical Synchronization Polarity"] -pub type VSYNC_POL_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type VSYNC_POL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PIXCLK_POL` reader - Pixel Clock Polarity"] pub type PIXCLK_POL_R = crate::BitReader; #[doc = "Field `PIXCLK_POL` writer - Pixel Clock Polarity"] -pub type PIXCLK_POL_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type PIXCLK_POL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GRAYLE` reader - Grayscale Little Endian"] pub type GRAYLE_R = crate::BitReader; #[doc = "Field `GRAYLE` writer - Grayscale Little Endian"] -pub type GRAYLE_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type GRAYLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EMB_SYNC` reader - Embedded Synchronization"] pub type EMB_SYNC_R = crate::BitReader; #[doc = "Field `EMB_SYNC` writer - Embedded Synchronization"] -pub type EMB_SYNC_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type EMB_SYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRC_SYNC` reader - Embedded Synchronization Correction"] pub type CRC_SYNC_R = crate::BitReader; #[doc = "Field `CRC_SYNC` writer - Embedded Synchronization Correction"] -pub type CRC_SYNC_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type CRC_SYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRATE` reader - Frame Rate \\[0..7\\]"] pub type FRATE_R = crate::FieldReader; #[doc = "Field `FRATE` writer - Frame Rate \\[0..7\\]"] -pub type FRATE_W<'a, const O: u8> = crate::FieldWriter<'a, CFG1_SPEC, 3, O>; +pub type FRATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DISCR` reader - Disable Codec Request"] pub type DISCR_R = crate::BitReader; #[doc = "Field `DISCR` writer - Disable Codec Request"] -pub type DISCR_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type DISCR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FULL` reader - Full Mode is Allowed"] pub type FULL_R = crate::BitReader; #[doc = "Field `FULL` writer - Full Mode is Allowed"] -pub type FULL_W<'a, const O: u8> = crate::BitWriter<'a, CFG1_SPEC, O>; +pub type FULL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `THMASK` reader - Threshold Mask"] pub type THMASK_R = crate::FieldReader; #[doc = "Threshold Mask\n\nValue on reset: 0"] @@ -103,49 +71,53 @@ impl THMASK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BEATS_4`"] + #[doc = "Only 4 beats AHB burst allowed"] #[inline(always)] pub fn is_beats_4(&self) -> bool { *self == THMASKSELECT_A::BEATS_4 } - #[doc = "Checks if the value of the field is `BEATS_8`"] + #[doc = "Only 4 and 8 beats AHB burst allowed"] #[inline(always)] pub fn is_beats_8(&self) -> bool { *self == THMASKSELECT_A::BEATS_8 } - #[doc = "Checks if the value of the field is `BEATS_16`"] + #[doc = "4, 8 and 16 beats AHB burst allowed"] #[inline(always)] pub fn is_beats_16(&self) -> bool { *self == THMASKSELECT_A::BEATS_16 } } #[doc = "Field `THMASK` writer - Threshold Mask"] -pub type THMASK_W<'a, const O: u8> = crate::FieldWriter<'a, CFG1_SPEC, 2, O, THMASKSELECT_A>; -impl<'a, const O: u8> THMASK_W<'a, O> { +pub type THMASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, THMASKSELECT_A>; +impl<'a, REG, const O: u8> THMASK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Only 4 beats AHB burst allowed"] #[inline(always)] - pub fn beats_4(self) -> &'a mut W { + pub fn beats_4(self) -> &'a mut crate::W { self.variant(THMASKSELECT_A::BEATS_4) } #[doc = "Only 4 and 8 beats AHB burst allowed"] #[inline(always)] - pub fn beats_8(self) -> &'a mut W { + pub fn beats_8(self) -> &'a mut crate::W { self.variant(THMASKSELECT_A::BEATS_8) } #[doc = "4, 8 and 16 beats AHB burst allowed"] #[inline(always)] - pub fn beats_16(self) -> &'a mut W { + pub fn beats_16(self) -> &'a mut crate::W { self.variant(THMASKSELECT_A::BEATS_16) } } #[doc = "Field `SLD` reader - Start of Line Delay"] pub type SLD_R = crate::FieldReader; #[doc = "Field `SLD` writer - Start of Line Delay"] -pub type SLD_W<'a, const O: u8> = crate::FieldWriter<'a, CFG1_SPEC, 8, O>; +pub type SLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `SFD` reader - Start of Frame Delay"] pub type SFD_R = crate::FieldReader; #[doc = "Field `SFD` writer - Start of Frame Delay"] -pub type SFD_W<'a, const O: u8> = crate::FieldWriter<'a, CFG1_SPEC, 8, O>; +pub type SFD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 2 - Horizontal Synchronization Polarity"] #[inline(always)] @@ -212,94 +184,91 @@ impl W { #[doc = "Bit 2 - Horizontal Synchronization Polarity"] #[inline(always)] #[must_use] - pub fn hsync_pol(&mut self) -> HSYNC_POL_W<2> { + pub fn hsync_pol(&mut self) -> HSYNC_POL_W { HSYNC_POL_W::new(self) } #[doc = "Bit 3 - Vertical Synchronization Polarity"] #[inline(always)] #[must_use] - pub fn vsync_pol(&mut self) -> VSYNC_POL_W<3> { + pub fn vsync_pol(&mut self) -> VSYNC_POL_W { VSYNC_POL_W::new(self) } #[doc = "Bit 4 - Pixel Clock Polarity"] #[inline(always)] #[must_use] - pub fn pixclk_pol(&mut self) -> PIXCLK_POL_W<4> { + pub fn pixclk_pol(&mut self) -> PIXCLK_POL_W { PIXCLK_POL_W::new(self) } #[doc = "Bit 5 - Grayscale Little Endian"] #[inline(always)] #[must_use] - pub fn grayle(&mut self) -> GRAYLE_W<5> { + pub fn grayle(&mut self) -> GRAYLE_W { GRAYLE_W::new(self) } #[doc = "Bit 6 - Embedded Synchronization"] #[inline(always)] #[must_use] - pub fn emb_sync(&mut self) -> EMB_SYNC_W<6> { + pub fn emb_sync(&mut self) -> EMB_SYNC_W { EMB_SYNC_W::new(self) } #[doc = "Bit 7 - Embedded Synchronization Correction"] #[inline(always)] #[must_use] - pub fn crc_sync(&mut self) -> CRC_SYNC_W<7> { + pub fn crc_sync(&mut self) -> CRC_SYNC_W { CRC_SYNC_W::new(self) } #[doc = "Bits 8:10 - Frame Rate \\[0..7\\]"] #[inline(always)] #[must_use] - pub fn frate(&mut self) -> FRATE_W<8> { + pub fn frate(&mut self) -> FRATE_W { FRATE_W::new(self) } #[doc = "Bit 11 - Disable Codec Request"] #[inline(always)] #[must_use] - pub fn discr(&mut self) -> DISCR_W<11> { + pub fn discr(&mut self) -> DISCR_W { DISCR_W::new(self) } #[doc = "Bit 12 - Full Mode is Allowed"] #[inline(always)] #[must_use] - pub fn full(&mut self) -> FULL_W<12> { + pub fn full(&mut self) -> FULL_W { FULL_W::new(self) } #[doc = "Bits 13:14 - Threshold Mask"] #[inline(always)] #[must_use] - pub fn thmask(&mut self) -> THMASK_W<13> { + pub fn thmask(&mut self) -> THMASK_W { THMASK_W::new(self) } #[doc = "Bits 16:23 - Start of Line Delay"] #[inline(always)] #[must_use] - pub fn sld(&mut self) -> SLD_W<16> { + pub fn sld(&mut self) -> SLD_W { SLD_W::new(self) } #[doc = "Bits 24:31 - Start of Frame Delay"] #[inline(always)] #[must_use] - pub fn sfd(&mut self) -> SFD_W<24> { + pub fn sfd(&mut self) -> SFD_W { SFD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Configuration 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg1](index.html) module"] +#[doc = "ISI Configuration 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG1_SPEC; impl crate::RegisterSpec for CFG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cfg1::R](R) reader structure"] -impl crate::Readable for CFG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cfg1::W](W) writer structure"] +#[doc = "`read()` method returns [`cfg1::R`](R) reader structure"] +impl crate::Readable for CFG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfg1::W`](W) writer structure"] impl crate::Writable for CFG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/cfg2.rs b/arch/cortex-m/samv71q21-pac/src/isi/cfg2.rs index 8189a0fb..e8053b29 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/cfg2.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/cfg2.rs @@ -1,67 +1,35 @@ #[doc = "Register `CFG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CFG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IM_VSIZE` reader - Vertical Size of the Image Sensor \\[0..2047\\]"] pub type IM_VSIZE_R = crate::FieldReader; #[doc = "Field `IM_VSIZE` writer - Vertical Size of the Image Sensor \\[0..2047\\]"] -pub type IM_VSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CFG2_SPEC, 11, O, u16>; +pub type IM_VSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `GS_MODE` reader - Grayscale Pixel Format Mode"] pub type GS_MODE_R = crate::BitReader; #[doc = "Field `GS_MODE` writer - Grayscale Pixel Format Mode"] -pub type GS_MODE_W<'a, const O: u8> = crate::BitWriter<'a, CFG2_SPEC, O>; +pub type GS_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RGB_MODE` reader - RGB Input Mode"] pub type RGB_MODE_R = crate::BitReader; #[doc = "Field `RGB_MODE` writer - RGB Input Mode"] -pub type RGB_MODE_W<'a, const O: u8> = crate::BitWriter<'a, CFG2_SPEC, O>; +pub type RGB_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GRAYSCALE` reader - Grayscale Mode Format Enable"] pub type GRAYSCALE_R = crate::BitReader; #[doc = "Field `GRAYSCALE` writer - Grayscale Mode Format Enable"] -pub type GRAYSCALE_W<'a, const O: u8> = crate::BitWriter<'a, CFG2_SPEC, O>; +pub type GRAYSCALE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RGB_SWAP` reader - RGB Format Swap Mode"] pub type RGB_SWAP_R = crate::BitReader; #[doc = "Field `RGB_SWAP` writer - RGB Format Swap Mode"] -pub type RGB_SWAP_W<'a, const O: u8> = crate::BitWriter<'a, CFG2_SPEC, O>; +pub type RGB_SWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COL_SPACE` reader - Color Space for the Image Data"] pub type COL_SPACE_R = crate::BitReader; #[doc = "Field `COL_SPACE` writer - Color Space for the Image Data"] -pub type COL_SPACE_W<'a, const O: u8> = crate::BitWriter<'a, CFG2_SPEC, O>; +pub type COL_SPACE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IM_HSIZE` reader - Horizontal Size of the Image Sensor \\[0..2047\\]"] pub type IM_HSIZE_R = crate::FieldReader; #[doc = "Field `IM_HSIZE` writer - Horizontal Size of the Image Sensor \\[0..2047\\]"] -pub type IM_HSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CFG2_SPEC, 11, O, u16>; +pub type IM_HSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `YCC_SWAP` reader - YCrCb Format Swap Mode"] pub type YCC_SWAP_R = crate::FieldReader; #[doc = "YCrCb Format Swap Mode\n\nValue on reset: 0"] @@ -98,49 +66,52 @@ impl YCC_SWAP_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DEFAULT`"] + #[doc = "Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1)"] #[inline(always)] pub fn is_default(&self) -> bool { *self == YCC_SWAPSELECT_A::DEFAULT } - #[doc = "Checks if the value of the field is `MODE1`"] + #[doc = "Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1)"] #[inline(always)] pub fn is_mode1(&self) -> bool { *self == YCC_SWAPSELECT_A::MODE1 } - #[doc = "Checks if the value of the field is `MODE2`"] + #[doc = "Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i)"] #[inline(always)] pub fn is_mode2(&self) -> bool { *self == YCC_SWAPSELECT_A::MODE2 } - #[doc = "Checks if the value of the field is `MODE3`"] + #[doc = "Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i)"] #[inline(always)] pub fn is_mode3(&self) -> bool { *self == YCC_SWAPSELECT_A::MODE3 } } #[doc = "Field `YCC_SWAP` writer - YCrCb Format Swap Mode"] -pub type YCC_SWAP_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CFG2_SPEC, 2, O, YCC_SWAPSELECT_A>; -impl<'a, const O: u8> YCC_SWAP_W<'a, O> { +pub type YCC_SWAP_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, YCC_SWAPSELECT_A>; +impl<'a, REG, const O: u8> YCC_SWAP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1)"] #[inline(always)] - pub fn default(self) -> &'a mut W { + pub fn default(self) -> &'a mut crate::W { self.variant(YCC_SWAPSELECT_A::DEFAULT) } #[doc = "Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1)"] #[inline(always)] - pub fn mode1(self) -> &'a mut W { + pub fn mode1(self) -> &'a mut crate::W { self.variant(YCC_SWAPSELECT_A::MODE1) } #[doc = "Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i)"] #[inline(always)] - pub fn mode2(self) -> &'a mut W { + pub fn mode2(self) -> &'a mut crate::W { self.variant(YCC_SWAPSELECT_A::MODE2) } #[doc = "Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i)"] #[inline(always)] - pub fn mode3(self) -> &'a mut W { + pub fn mode3(self) -> &'a mut crate::W { self.variant(YCC_SWAPSELECT_A::MODE3) } } @@ -180,48 +151,52 @@ impl RGB_CFG_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DEFAULT`"] + #[doc = "Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B"] #[inline(always)] pub fn is_default(&self) -> bool { *self == RGB_CFGSELECT_A::DEFAULT } - #[doc = "Checks if the value of the field is `MODE1`"] + #[doc = "Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R"] #[inline(always)] pub fn is_mode1(&self) -> bool { *self == RGB_CFGSELECT_A::MODE1 } - #[doc = "Checks if the value of the field is `MODE2`"] + #[doc = "Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB)"] #[inline(always)] pub fn is_mode2(&self) -> bool { *self == RGB_CFGSELECT_A::MODE2 } - #[doc = "Checks if the value of the field is `MODE3`"] + #[doc = "Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB)"] #[inline(always)] pub fn is_mode3(&self) -> bool { *self == RGB_CFGSELECT_A::MODE3 } } #[doc = "Field `RGB_CFG` writer - RGB Pixel Mapping Configuration"] -pub type RGB_CFG_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CFG2_SPEC, 2, O, RGB_CFGSELECT_A>; -impl<'a, const O: u8> RGB_CFG_W<'a, O> { +pub type RGB_CFG_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RGB_CFGSELECT_A>; +impl<'a, REG, const O: u8> RGB_CFG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B"] #[inline(always)] - pub fn default(self) -> &'a mut W { + pub fn default(self) -> &'a mut crate::W { self.variant(RGB_CFGSELECT_A::DEFAULT) } #[doc = "Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R"] #[inline(always)] - pub fn mode1(self) -> &'a mut W { + pub fn mode1(self) -> &'a mut crate::W { self.variant(RGB_CFGSELECT_A::MODE1) } #[doc = "Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB)"] #[inline(always)] - pub fn mode2(self) -> &'a mut W { + pub fn mode2(self) -> &'a mut crate::W { self.variant(RGB_CFGSELECT_A::MODE2) } #[doc = "Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB)"] #[inline(always)] - pub fn mode3(self) -> &'a mut W { + pub fn mode3(self) -> &'a mut crate::W { self.variant(RGB_CFGSELECT_A::MODE3) } } @@ -276,76 +251,73 @@ impl W { #[doc = "Bits 0:10 - Vertical Size of the Image Sensor \\[0..2047\\]"] #[inline(always)] #[must_use] - pub fn im_vsize(&mut self) -> IM_VSIZE_W<0> { + pub fn im_vsize(&mut self) -> IM_VSIZE_W { IM_VSIZE_W::new(self) } #[doc = "Bit 11 - Grayscale Pixel Format Mode"] #[inline(always)] #[must_use] - pub fn gs_mode(&mut self) -> GS_MODE_W<11> { + pub fn gs_mode(&mut self) -> GS_MODE_W { GS_MODE_W::new(self) } #[doc = "Bit 12 - RGB Input Mode"] #[inline(always)] #[must_use] - pub fn rgb_mode(&mut self) -> RGB_MODE_W<12> { + pub fn rgb_mode(&mut self) -> RGB_MODE_W { RGB_MODE_W::new(self) } #[doc = "Bit 13 - Grayscale Mode Format Enable"] #[inline(always)] #[must_use] - pub fn grayscale(&mut self) -> GRAYSCALE_W<13> { + pub fn grayscale(&mut self) -> GRAYSCALE_W { GRAYSCALE_W::new(self) } #[doc = "Bit 14 - RGB Format Swap Mode"] #[inline(always)] #[must_use] - pub fn rgb_swap(&mut self) -> RGB_SWAP_W<14> { + pub fn rgb_swap(&mut self) -> RGB_SWAP_W { RGB_SWAP_W::new(self) } #[doc = "Bit 15 - Color Space for the Image Data"] #[inline(always)] #[must_use] - pub fn col_space(&mut self) -> COL_SPACE_W<15> { + pub fn col_space(&mut self) -> COL_SPACE_W { COL_SPACE_W::new(self) } #[doc = "Bits 16:26 - Horizontal Size of the Image Sensor \\[0..2047\\]"] #[inline(always)] #[must_use] - pub fn im_hsize(&mut self) -> IM_HSIZE_W<16> { + pub fn im_hsize(&mut self) -> IM_HSIZE_W { IM_HSIZE_W::new(self) } #[doc = "Bits 28:29 - YCrCb Format Swap Mode"] #[inline(always)] #[must_use] - pub fn ycc_swap(&mut self) -> YCC_SWAP_W<28> { + pub fn ycc_swap(&mut self) -> YCC_SWAP_W { YCC_SWAP_W::new(self) } #[doc = "Bits 30:31 - RGB Pixel Mapping Configuration"] #[inline(always)] #[must_use] - pub fn rgb_cfg(&mut self) -> RGB_CFG_W<30> { + pub fn rgb_cfg(&mut self) -> RGB_CFG_W { RGB_CFG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Configuration 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfg2](index.html) module"] +#[doc = "ISI Configuration 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CFG2_SPEC; impl crate::RegisterSpec for CFG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cfg2::R](R) reader structure"] -impl crate::Readable for CFG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cfg2::W](W) writer structure"] +#[doc = "`read()` method returns [`cfg2::R`](R) reader structure"] +impl crate::Readable for CFG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"] impl crate::Writable for CFG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/cr.rs b/arch/cortex-m/samv71q21-pac/src/isi/cr.rs index 903bc22b..d2649abb 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/cr.rs @@ -1,72 +1,52 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ISI_EN` writer - ISI Module Enable Request"] -pub type ISI_EN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ISI_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISI_DIS` writer - ISI Module Disable Request"] -pub type ISI_DIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ISI_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISI_SRST` writer - ISI Software Reset Request"] -pub type ISI_SRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ISI_SRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISI_CDC` writer - ISI Codec Request"] -pub type ISI_CDC_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ISI_CDC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - ISI Module Enable Request"] #[inline(always)] #[must_use] - pub fn isi_en(&mut self) -> ISI_EN_W<0> { + pub fn isi_en(&mut self) -> ISI_EN_W { ISI_EN_W::new(self) } #[doc = "Bit 1 - ISI Module Disable Request"] #[inline(always)] #[must_use] - pub fn isi_dis(&mut self) -> ISI_DIS_W<1> { + pub fn isi_dis(&mut self) -> ISI_DIS_W { ISI_DIS_W::new(self) } #[doc = "Bit 2 - ISI Software Reset Request"] #[inline(always)] #[must_use] - pub fn isi_srst(&mut self) -> ISI_SRST_W<2> { + pub fn isi_srst(&mut self) -> ISI_SRST_W { ISI_SRST_W::new(self) } #[doc = "Bit 8 - ISI Codec Request"] #[inline(always)] #[must_use] - pub fn isi_cdc(&mut self) -> ISI_CDC_W<8> { + pub fn isi_cdc(&mut self) -> ISI_CDC_W { ISI_CDC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "ISI Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_c_addr.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_c_addr.rs index 037e4961..5c2e66dd 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_c_addr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_c_addr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DMA_C_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA_C_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C_ADDR` reader - Codec Image Base Address"] pub type C_ADDR_R = crate::FieldReader; #[doc = "Field `C_ADDR` writer - Codec Image Base Address"] -pub type C_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, DMA_C_ADDR_SPEC, 30, O, u32>; +pub type C_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Codec Image Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Codec Image Base Address"] #[inline(always)] #[must_use] - pub fn c_addr(&mut self) -> C_ADDR_W<2> { + pub fn c_addr(&mut self) -> C_ADDR_W { C_ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Codec Base Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_c_addr](index.html) module"] +#[doc = "DMA Codec Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_c_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_c_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_C_ADDR_SPEC; impl crate::RegisterSpec for DMA_C_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_c_addr::R](R) reader structure"] -impl crate::Readable for DMA_C_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma_c_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`dma_c_addr::R`](R) reader structure"] +impl crate::Readable for DMA_C_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_c_addr::W`](W) writer structure"] impl crate::Writable for DMA_C_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_c_ctrl.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_c_ctrl.rs index e6ee6625..9929bb1d 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_c_ctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_c_ctrl.rs @@ -1,55 +1,23 @@ #[doc = "Register `DMA_C_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA_C_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C_FETCH` reader - Descriptor Fetch Control Bit"] pub type C_FETCH_R = crate::BitReader; #[doc = "Field `C_FETCH` writer - Descriptor Fetch Control Bit"] -pub type C_FETCH_W<'a, const O: u8> = crate::BitWriter<'a, DMA_C_CTRL_SPEC, O>; +pub type C_FETCH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_WB` reader - Descriptor Writeback Control Bit"] pub type C_WB_R = crate::BitReader; #[doc = "Field `C_WB` writer - Descriptor Writeback Control Bit"] -pub type C_WB_W<'a, const O: u8> = crate::BitWriter<'a, DMA_C_CTRL_SPEC, O>; +pub type C_WB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_IEN` reader - Transfer Done Flag Control"] pub type C_IEN_R = crate::BitReader; #[doc = "Field `C_IEN` writer - Transfer Done Flag Control"] -pub type C_IEN_W<'a, const O: u8> = crate::BitWriter<'a, DMA_C_CTRL_SPEC, O>; +pub type C_IEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_DONE` reader - Codec Transfer Done"] pub type C_DONE_R = crate::BitReader; #[doc = "Field `C_DONE` writer - Codec Transfer Done"] -pub type C_DONE_W<'a, const O: u8> = crate::BitWriter<'a, DMA_C_CTRL_SPEC, O>; +pub type C_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Descriptor Fetch Control Bit"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - Descriptor Fetch Control Bit"] #[inline(always)] #[must_use] - pub fn c_fetch(&mut self) -> C_FETCH_W<0> { + pub fn c_fetch(&mut self) -> C_FETCH_W { C_FETCH_W::new(self) } #[doc = "Bit 1 - Descriptor Writeback Control Bit"] #[inline(always)] #[must_use] - pub fn c_wb(&mut self) -> C_WB_W<1> { + pub fn c_wb(&mut self) -> C_WB_W { C_WB_W::new(self) } #[doc = "Bit 2 - Transfer Done Flag Control"] #[inline(always)] #[must_use] - pub fn c_ien(&mut self) -> C_IEN_W<2> { + pub fn c_ien(&mut self) -> C_IEN_W { C_IEN_W::new(self) } #[doc = "Bit 3 - Codec Transfer Done"] #[inline(always)] #[must_use] - pub fn c_done(&mut self) -> C_DONE_W<3> { + pub fn c_done(&mut self) -> C_DONE_W { C_DONE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Codec Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_c_ctrl](index.html) module"] +#[doc = "DMA Codec Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_c_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_c_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_C_CTRL_SPEC; impl crate::RegisterSpec for DMA_C_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_c_ctrl::R](R) reader structure"] -impl crate::Readable for DMA_C_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma_c_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`dma_c_ctrl::R`](R) reader structure"] +impl crate::Readable for DMA_C_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_c_ctrl::W`](W) writer structure"] impl crate::Writable for DMA_C_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_c_dscr.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_c_dscr.rs index 5c5385db..3f219903 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_c_dscr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_c_dscr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DMA_C_DSCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA_C_DSCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C_DSCR` reader - Codec Descriptor Base Address"] pub type C_DSCR_R = crate::FieldReader; #[doc = "Field `C_DSCR` writer - Codec Descriptor Base Address"] -pub type C_DSCR_W<'a, const O: u8> = crate::FieldWriter<'a, DMA_C_DSCR_SPEC, 30, O, u32>; +pub type C_DSCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Codec Descriptor Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Codec Descriptor Base Address"] #[inline(always)] #[must_use] - pub fn c_dscr(&mut self) -> C_DSCR_W<2> { + pub fn c_dscr(&mut self) -> C_DSCR_W { C_DSCR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Codec Descriptor Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_c_dscr](index.html) module"] +#[doc = "DMA Codec Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_c_dscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_c_dscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_C_DSCR_SPEC; impl crate::RegisterSpec for DMA_C_DSCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_c_dscr::R](R) reader structure"] -impl crate::Readable for DMA_C_DSCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma_c_dscr::W](W) writer structure"] +#[doc = "`read()` method returns [`dma_c_dscr::R`](R) reader structure"] +impl crate::Readable for DMA_C_DSCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_c_dscr::W`](W) writer structure"] impl crate::Writable for DMA_C_DSCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_chdr.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_chdr.rs index e007bce5..94640fa4 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_chdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_chdr.rs @@ -1,56 +1,36 @@ #[doc = "Register `DMA_CHDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P_CH_DIS` writer - Preview Channel Disable Request"] -pub type P_CH_DIS_W<'a, const O: u8> = crate::BitWriter<'a, DMA_CHDR_SPEC, O>; +pub type P_CH_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_CH_DIS` writer - Codec Channel Disable Request"] -pub type C_CH_DIS_W<'a, const O: u8> = crate::BitWriter<'a, DMA_CHDR_SPEC, O>; +pub type C_CH_DIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Preview Channel Disable Request"] #[inline(always)] #[must_use] - pub fn p_ch_dis(&mut self) -> P_CH_DIS_W<0> { + pub fn p_ch_dis(&mut self) -> P_CH_DIS_W { P_CH_DIS_W::new(self) } #[doc = "Bit 1 - Codec Channel Disable Request"] #[inline(always)] #[must_use] - pub fn c_ch_dis(&mut self) -> C_CH_DIS_W<1> { + pub fn c_ch_dis(&mut self) -> C_CH_DIS_W { C_CH_DIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Channel Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_chdr](index.html) module"] +#[doc = "DMA Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_chdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_CHDR_SPEC; impl crate::RegisterSpec for DMA_CHDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [dma_chdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`dma_chdr::W`](W) writer structure"] impl crate::Writable for DMA_CHDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_cher.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_cher.rs index 7cb3b98a..bebf9e36 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_cher.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_cher.rs @@ -1,56 +1,36 @@ #[doc = "Register `DMA_CHER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P_CH_EN` writer - Preview Channel Enable"] -pub type P_CH_EN_W<'a, const O: u8> = crate::BitWriter<'a, DMA_CHER_SPEC, O>; +pub type P_CH_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_CH_EN` writer - Codec Channel Enable"] -pub type C_CH_EN_W<'a, const O: u8> = crate::BitWriter<'a, DMA_CHER_SPEC, O>; +pub type C_CH_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Preview Channel Enable"] #[inline(always)] #[must_use] - pub fn p_ch_en(&mut self) -> P_CH_EN_W<0> { + pub fn p_ch_en(&mut self) -> P_CH_EN_W { P_CH_EN_W::new(self) } #[doc = "Bit 1 - Codec Channel Enable"] #[inline(always)] #[must_use] - pub fn c_ch_en(&mut self) -> C_CH_EN_W<1> { + pub fn c_ch_en(&mut self) -> C_CH_EN_W { C_CH_EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Channel Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_cher](index.html) module"] +#[doc = "DMA Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_cher::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_CHER_SPEC; impl crate::RegisterSpec for DMA_CHER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [dma_cher::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`dma_cher::W`](W) writer structure"] impl crate::Writable for DMA_CHER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_chsr.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_chsr.rs index 203875c9..df2b14b4 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_chsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_chsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `DMA_CHSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P_CH_S` reader - Preview DMA Channel Status"] pub type P_CH_S_R = crate::BitReader; #[doc = "Field `C_CH_S` reader - Code DMA Channel Status"] @@ -29,15 +16,13 @@ impl R { C_CH_S_R::new(((self.bits >> 1) & 1) != 0) } } -#[doc = "DMA Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_chsr](index.html) module"] +#[doc = "DMA Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_chsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_CHSR_SPEC; impl crate::RegisterSpec for DMA_CHSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_chsr::R](R) reader structure"] -impl crate::Readable for DMA_CHSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`dma_chsr::R`](R) reader structure"] +impl crate::Readable for DMA_CHSR_SPEC {} #[doc = "`reset()` method sets DMA_CHSR to value 0"] impl crate::Resettable for DMA_CHSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_p_addr.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_p_addr.rs index fb4ecb37..f31c0140 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_p_addr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_p_addr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DMA_P_ADDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA_P_ADDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P_ADDR` reader - Preview Image Base Address"] pub type P_ADDR_R = crate::FieldReader; #[doc = "Field `P_ADDR` writer - Preview Image Base Address"] -pub type P_ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, DMA_P_ADDR_SPEC, 30, O, u32>; +pub type P_ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Preview Image Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Preview Image Base Address"] #[inline(always)] #[must_use] - pub fn p_addr(&mut self) -> P_ADDR_W<2> { + pub fn p_addr(&mut self) -> P_ADDR_W { P_ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Preview Base Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_p_addr](index.html) module"] +#[doc = "DMA Preview Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_p_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_p_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_P_ADDR_SPEC; impl crate::RegisterSpec for DMA_P_ADDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_p_addr::R](R) reader structure"] -impl crate::Readable for DMA_P_ADDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma_p_addr::W](W) writer structure"] +#[doc = "`read()` method returns [`dma_p_addr::R`](R) reader structure"] +impl crate::Readable for DMA_P_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_p_addr::W`](W) writer structure"] impl crate::Writable for DMA_P_ADDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_p_ctrl.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_p_ctrl.rs index 6031f3dc..09487cfc 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_p_ctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_p_ctrl.rs @@ -1,55 +1,23 @@ #[doc = "Register `DMA_P_CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA_P_CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P_FETCH` reader - Descriptor Fetch Control Bit"] pub type P_FETCH_R = crate::BitReader; #[doc = "Field `P_FETCH` writer - Descriptor Fetch Control Bit"] -pub type P_FETCH_W<'a, const O: u8> = crate::BitWriter<'a, DMA_P_CTRL_SPEC, O>; +pub type P_FETCH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P_WB` reader - Descriptor Writeback Control Bit"] pub type P_WB_R = crate::BitReader; #[doc = "Field `P_WB` writer - Descriptor Writeback Control Bit"] -pub type P_WB_W<'a, const O: u8> = crate::BitWriter<'a, DMA_P_CTRL_SPEC, O>; +pub type P_WB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P_IEN` reader - Transfer Done Flag Control"] pub type P_IEN_R = crate::BitReader; #[doc = "Field `P_IEN` writer - Transfer Done Flag Control"] -pub type P_IEN_W<'a, const O: u8> = crate::BitWriter<'a, DMA_P_CTRL_SPEC, O>; +pub type P_IEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P_DONE` reader - Preview Transfer Done"] pub type P_DONE_R = crate::BitReader; #[doc = "Field `P_DONE` writer - Preview Transfer Done"] -pub type P_DONE_W<'a, const O: u8> = crate::BitWriter<'a, DMA_P_CTRL_SPEC, O>; +pub type P_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Descriptor Fetch Control Bit"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - Descriptor Fetch Control Bit"] #[inline(always)] #[must_use] - pub fn p_fetch(&mut self) -> P_FETCH_W<0> { + pub fn p_fetch(&mut self) -> P_FETCH_W { P_FETCH_W::new(self) } #[doc = "Bit 1 - Descriptor Writeback Control Bit"] #[inline(always)] #[must_use] - pub fn p_wb(&mut self) -> P_WB_W<1> { + pub fn p_wb(&mut self) -> P_WB_W { P_WB_W::new(self) } #[doc = "Bit 2 - Transfer Done Flag Control"] #[inline(always)] #[must_use] - pub fn p_ien(&mut self) -> P_IEN_W<2> { + pub fn p_ien(&mut self) -> P_IEN_W { P_IEN_W::new(self) } #[doc = "Bit 3 - Preview Transfer Done"] #[inline(always)] #[must_use] - pub fn p_done(&mut self) -> P_DONE_W<3> { + pub fn p_done(&mut self) -> P_DONE_W { P_DONE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Preview Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_p_ctrl](index.html) module"] +#[doc = "DMA Preview Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_p_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_p_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_P_CTRL_SPEC; impl crate::RegisterSpec for DMA_P_CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_p_ctrl::R](R) reader structure"] -impl crate::Readable for DMA_P_CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma_p_ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`dma_p_ctrl::R`](R) reader structure"] +impl crate::Readable for DMA_P_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_p_ctrl::W`](W) writer structure"] impl crate::Writable for DMA_P_CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/dma_p_dscr.rs b/arch/cortex-m/samv71q21-pac/src/isi/dma_p_dscr.rs index e4534460..3db8a923 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/dma_p_dscr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/dma_p_dscr.rs @@ -1,43 +1,11 @@ #[doc = "Register `DMA_P_DSCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DMA_P_DSCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P_DSCR` reader - Preview Descriptor Base Address"] pub type P_DSCR_R = crate::FieldReader; #[doc = "Field `P_DSCR` writer - Preview Descriptor Base Address"] -pub type P_DSCR_W<'a, const O: u8> = crate::FieldWriter<'a, DMA_P_DSCR_SPEC, 30, O, u32>; +pub type P_DSCR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bits 2:31 - Preview Descriptor Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:31 - Preview Descriptor Base Address"] #[inline(always)] #[must_use] - pub fn p_dscr(&mut self) -> P_DSCR_W<2> { + pub fn p_dscr(&mut self) -> P_DSCR_W { P_DSCR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "DMA Preview Descriptor Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_p_dscr](index.html) module"] +#[doc = "DMA Preview Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_p_dscr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_p_dscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMA_P_DSCR_SPEC; impl crate::RegisterSpec for DMA_P_DSCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dma_p_dscr::R](R) reader structure"] -impl crate::Readable for DMA_P_DSCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dma_p_dscr::W](W) writer structure"] +#[doc = "`read()` method returns [`dma_p_dscr::R`](R) reader structure"] +impl crate::Readable for DMA_P_DSCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma_p_dscr::W`](W) writer structure"] impl crate::Writable for DMA_P_DSCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/idr.rs b/arch/cortex-m/samv71q21-pac/src/isi/idr.rs index 6ad5c1f9..7684f2b2 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/idr.rs @@ -1,112 +1,92 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIS_DONE` writer - Disable Done Interrupt Disable"] -pub type DIS_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DIS_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST` writer - Software Reset Interrupt Disable"] -pub type SRST_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VSYNC` writer - Vertical Synchronization Interrupt Disable"] -pub type VSYNC_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type VSYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFR_DONE` writer - Preview DMA Transfer Done Interrupt Disable"] -pub type PXFR_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PXFR_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CXFR_DONE` writer - Codec DMA Transfer Done Interrupt Disable"] -pub type CXFR_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CXFR_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P_OVR` writer - Preview Datapath Overflow Interrupt Disable"] -pub type P_OVR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P_OVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_OVR` writer - Codec Datapath Overflow Interrupt Disable"] -pub type C_OVR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type C_OVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRC_ERR` writer - Embedded Synchronization CRC Error Interrupt Disable"] -pub type CRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FR_OVR` writer - Frame Rate Overflow Interrupt Disable"] -pub type FR_OVR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type FR_OVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 1 - Disable Done Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dis_done(&mut self) -> DIS_DONE_W<1> { + pub fn dis_done(&mut self) -> DIS_DONE_W { DIS_DONE_W::new(self) } #[doc = "Bit 2 - Software Reset Interrupt Disable"] #[inline(always)] #[must_use] - pub fn srst(&mut self) -> SRST_W<2> { + pub fn srst(&mut self) -> SRST_W { SRST_W::new(self) } #[doc = "Bit 10 - Vertical Synchronization Interrupt Disable"] #[inline(always)] #[must_use] - pub fn vsync(&mut self) -> VSYNC_W<10> { + pub fn vsync(&mut self) -> VSYNC_W { VSYNC_W::new(self) } #[doc = "Bit 16 - Preview DMA Transfer Done Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pxfr_done(&mut self) -> PXFR_DONE_W<16> { + pub fn pxfr_done(&mut self) -> PXFR_DONE_W { PXFR_DONE_W::new(self) } #[doc = "Bit 17 - Codec DMA Transfer Done Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cxfr_done(&mut self) -> CXFR_DONE_W<17> { + pub fn cxfr_done(&mut self) -> CXFR_DONE_W { CXFR_DONE_W::new(self) } #[doc = "Bit 24 - Preview Datapath Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p_ovr(&mut self) -> P_OVR_W<24> { + pub fn p_ovr(&mut self) -> P_OVR_W { P_OVR_W::new(self) } #[doc = "Bit 25 - Codec Datapath Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn c_ovr(&mut self) -> C_OVR_W<25> { + pub fn c_ovr(&mut self) -> C_OVR_W { C_OVR_W::new(self) } #[doc = "Bit 26 - Embedded Synchronization CRC Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn crc_err(&mut self) -> CRC_ERR_W<26> { + pub fn crc_err(&mut self) -> CRC_ERR_W { CRC_ERR_W::new(self) } #[doc = "Bit 27 - Frame Rate Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn fr_ovr(&mut self) -> FR_OVR_W<27> { + pub fn fr_ovr(&mut self) -> FR_OVR_W { FR_OVR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "ISI Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/ier.rs b/arch/cortex-m/samv71q21-pac/src/isi/ier.rs index d8e0fe3d..a18f65d1 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/ier.rs @@ -1,112 +1,92 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIS_DONE` writer - Disable Done Interrupt Enable"] -pub type DIS_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DIS_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SRST` writer - Software Reset Interrupt Enable"] -pub type SRST_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VSYNC` writer - Vertical Synchronization Interrupt Enable"] -pub type VSYNC_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type VSYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PXFR_DONE` writer - Preview DMA Transfer Done Interrupt Enable"] -pub type PXFR_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PXFR_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CXFR_DONE` writer - Codec DMA Transfer Done Interrupt Enable"] -pub type CXFR_DONE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CXFR_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P_OVR` writer - Preview Datapath Overflow Interrupt Enable"] -pub type P_OVR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P_OVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `C_OVR` writer - Codec Datapath Overflow Interrupt Enable"] -pub type C_OVR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type C_OVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRC_ERR` writer - Embedded Synchronization CRC Error Interrupt Enable"] -pub type CRC_ERR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CRC_ERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FR_OVR` writer - Frame Rate Overflow Interrupt Enable"] -pub type FR_OVR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type FR_OVR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 1 - Disable Done Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dis_done(&mut self) -> DIS_DONE_W<1> { + pub fn dis_done(&mut self) -> DIS_DONE_W { DIS_DONE_W::new(self) } #[doc = "Bit 2 - Software Reset Interrupt Enable"] #[inline(always)] #[must_use] - pub fn srst(&mut self) -> SRST_W<2> { + pub fn srst(&mut self) -> SRST_W { SRST_W::new(self) } #[doc = "Bit 10 - Vertical Synchronization Interrupt Enable"] #[inline(always)] #[must_use] - pub fn vsync(&mut self) -> VSYNC_W<10> { + pub fn vsync(&mut self) -> VSYNC_W { VSYNC_W::new(self) } #[doc = "Bit 16 - Preview DMA Transfer Done Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pxfr_done(&mut self) -> PXFR_DONE_W<16> { + pub fn pxfr_done(&mut self) -> PXFR_DONE_W { PXFR_DONE_W::new(self) } #[doc = "Bit 17 - Codec DMA Transfer Done Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cxfr_done(&mut self) -> CXFR_DONE_W<17> { + pub fn cxfr_done(&mut self) -> CXFR_DONE_W { CXFR_DONE_W::new(self) } #[doc = "Bit 24 - Preview Datapath Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p_ovr(&mut self) -> P_OVR_W<24> { + pub fn p_ovr(&mut self) -> P_OVR_W { P_OVR_W::new(self) } #[doc = "Bit 25 - Codec Datapath Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn c_ovr(&mut self) -> C_OVR_W<25> { + pub fn c_ovr(&mut self) -> C_OVR_W { C_OVR_W::new(self) } #[doc = "Bit 26 - Embedded Synchronization CRC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn crc_err(&mut self) -> CRC_ERR_W<26> { + pub fn crc_err(&mut self) -> CRC_ERR_W { CRC_ERR_W::new(self) } #[doc = "Bit 27 - Frame Rate Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn fr_ovr(&mut self) -> FR_OVR_W<27> { + pub fn fr_ovr(&mut self) -> FR_OVR_W { FR_OVR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "ISI Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/imr.rs b/arch/cortex-m/samv71q21-pac/src/isi/imr.rs index a33bb4b5..c40069dc 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DIS_DONE` reader - Module Disable Operation Completed"] pub type DIS_DONE_R = crate::BitReader; #[doc = "Field `SRST` reader - Software Reset Completed"] @@ -78,15 +65,13 @@ impl R { FR_OVR_R::new(((self.bits >> 27) & 1) != 0) } } -#[doc = "ISI Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "ISI Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/isi/pdecf.rs b/arch/cortex-m/samv71q21-pac/src/isi/pdecf.rs index dcc9af65..0f252da6 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/pdecf.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/pdecf.rs @@ -1,43 +1,11 @@ #[doc = "Register `PDECF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PDECF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DEC_FACTOR` reader - Decimation Factor"] pub type DEC_FACTOR_R = crate::FieldReader; #[doc = "Field `DEC_FACTOR` writer - Decimation Factor"] -pub type DEC_FACTOR_W<'a, const O: u8> = crate::FieldWriter<'a, PDECF_SPEC, 8, O>; +pub type DEC_FACTOR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Decimation Factor"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:7 - Decimation Factor"] #[inline(always)] #[must_use] - pub fn dec_factor(&mut self) -> DEC_FACTOR_W<0> { + pub fn dec_factor(&mut self) -> DEC_FACTOR_W { DEC_FACTOR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Preview Decimation Factor Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdecf](index.html) module"] +#[doc = "ISI Preview Decimation Factor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdecf::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdecf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDECF_SPEC; impl crate::RegisterSpec for PDECF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pdecf::R](R) reader structure"] -impl crate::Readable for PDECF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pdecf::W](W) writer structure"] +#[doc = "`read()` method returns [`pdecf::R`](R) reader structure"] +impl crate::Readable for PDECF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pdecf::W`](W) writer structure"] impl crate::Writable for PDECF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/psize.rs b/arch/cortex-m/samv71q21-pac/src/isi/psize.rs index cb60427d..46f6153b 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/psize.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/psize.rs @@ -1,47 +1,15 @@ #[doc = "Register `PSIZE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PSIZE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PREV_VSIZE` reader - Vertical Size for the Preview Path"] pub type PREV_VSIZE_R = crate::FieldReader; #[doc = "Field `PREV_VSIZE` writer - Vertical Size for the Preview Path"] -pub type PREV_VSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, PSIZE_SPEC, 10, O, u16>; +pub type PREV_VSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; #[doc = "Field `PREV_HSIZE` reader - Horizontal Size for the Preview Path"] pub type PREV_HSIZE_R = crate::FieldReader; #[doc = "Field `PREV_HSIZE` writer - Horizontal Size for the Preview Path"] -pub type PREV_HSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, PSIZE_SPEC, 10, O, u16>; +pub type PREV_HSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 10, O, u16>; impl R { #[doc = "Bits 0:9 - Vertical Size for the Preview Path"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:9 - Vertical Size for the Preview Path"] #[inline(always)] #[must_use] - pub fn prev_vsize(&mut self) -> PREV_VSIZE_W<0> { + pub fn prev_vsize(&mut self) -> PREV_VSIZE_W { PREV_VSIZE_W::new(self) } #[doc = "Bits 16:25 - Horizontal Size for the Preview Path"] #[inline(always)] #[must_use] - pub fn prev_hsize(&mut self) -> PREV_HSIZE_W<16> { + pub fn prev_hsize(&mut self) -> PREV_HSIZE_W { PREV_HSIZE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Preview Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psize](index.html) module"] +#[doc = "ISI Preview Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psize::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psize::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PSIZE_SPEC; impl crate::RegisterSpec for PSIZE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [psize::R](R) reader structure"] -impl crate::Readable for PSIZE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [psize::W](W) writer structure"] +#[doc = "`read()` method returns [`psize::R`](R) reader structure"] +impl crate::Readable for PSIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`psize::W`](W) writer structure"] impl crate::Writable for PSIZE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/r2y_set0.rs b/arch/cortex-m/samv71q21-pac/src/isi/r2y_set0.rs index 8e92060a..20769988 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/r2y_set0.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/r2y_set0.rs @@ -1,55 +1,23 @@ #[doc = "Register `R2Y_SET0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `R2Y_SET0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C0` reader - Color Space Conversion Matrix Coefficient C0"] pub type C0_R = crate::FieldReader; #[doc = "Field `C0` writer - Color Space Conversion Matrix Coefficient C0"] -pub type C0_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET0_SPEC, 7, O>; +pub type C0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `C1` reader - Color Space Conversion Matrix Coefficient C1"] pub type C1_R = crate::FieldReader; #[doc = "Field `C1` writer - Color Space Conversion Matrix Coefficient C1"] -pub type C1_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET0_SPEC, 7, O>; +pub type C1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `C2` reader - Color Space Conversion Matrix Coefficient C2"] pub type C2_R = crate::FieldReader; #[doc = "Field `C2` writer - Color Space Conversion Matrix Coefficient C2"] -pub type C2_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET0_SPEC, 7, O>; +pub type C2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `Roff` reader - Color Space Conversion Red Component Offset"] pub type ROFF_R = crate::BitReader; #[doc = "Field `Roff` writer - Color Space Conversion Red Component Offset"] -pub type ROFF_W<'a, const O: u8> = crate::BitWriter<'a, R2Y_SET0_SPEC, O>; +pub type ROFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Color Space Conversion Matrix Coefficient C0"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - Color Space Conversion Matrix Coefficient C0"] #[inline(always)] #[must_use] - pub fn c0(&mut self) -> C0_W<0> { + pub fn c0(&mut self) -> C0_W { C0_W::new(self) } #[doc = "Bits 8:14 - Color Space Conversion Matrix Coefficient C1"] #[inline(always)] #[must_use] - pub fn c1(&mut self) -> C1_W<8> { + pub fn c1(&mut self) -> C1_W { C1_W::new(self) } #[doc = "Bits 16:22 - Color Space Conversion Matrix Coefficient C2"] #[inline(always)] #[must_use] - pub fn c2(&mut self) -> C2_W<16> { + pub fn c2(&mut self) -> C2_W { C2_W::new(self) } #[doc = "Bit 24 - Color Space Conversion Red Component Offset"] #[inline(always)] #[must_use] - pub fn roff(&mut self) -> ROFF_W<24> { + pub fn roff(&mut self) -> ROFF_W { ROFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Color Space Conversion RGB To YCrCb Set 0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r2y_set0](index.html) module"] +#[doc = "ISI Color Space Conversion RGB To YCrCb Set 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2y_set0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2y_set0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct R2Y_SET0_SPEC; impl crate::RegisterSpec for R2Y_SET0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [r2y_set0::R](R) reader structure"] -impl crate::Readable for R2Y_SET0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [r2y_set0::W](W) writer structure"] +#[doc = "`read()` method returns [`r2y_set0::R`](R) reader structure"] +impl crate::Readable for R2Y_SET0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`r2y_set0::W`](W) writer structure"] impl crate::Writable for R2Y_SET0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/r2y_set1.rs b/arch/cortex-m/samv71q21-pac/src/isi/r2y_set1.rs index d28e42f9..fe018d62 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/r2y_set1.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/r2y_set1.rs @@ -1,55 +1,23 @@ #[doc = "Register `R2Y_SET1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `R2Y_SET1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C3` reader - Color Space Conversion Matrix Coefficient C3"] pub type C3_R = crate::FieldReader; #[doc = "Field `C3` writer - Color Space Conversion Matrix Coefficient C3"] -pub type C3_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET1_SPEC, 7, O>; +pub type C3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `C4` reader - Color Space Conversion Matrix Coefficient C4"] pub type C4_R = crate::FieldReader; #[doc = "Field `C4` writer - Color Space Conversion Matrix Coefficient C4"] -pub type C4_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET1_SPEC, 7, O>; +pub type C4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `C5` reader - Color Space Conversion Matrix Coefficient C5"] pub type C5_R = crate::FieldReader; #[doc = "Field `C5` writer - Color Space Conversion Matrix Coefficient C5"] -pub type C5_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET1_SPEC, 7, O>; +pub type C5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `Goff` reader - Color Space Conversion Green Component Offset"] pub type GOFF_R = crate::BitReader; #[doc = "Field `Goff` writer - Color Space Conversion Green Component Offset"] -pub type GOFF_W<'a, const O: u8> = crate::BitWriter<'a, R2Y_SET1_SPEC, O>; +pub type GOFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Color Space Conversion Matrix Coefficient C3"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - Color Space Conversion Matrix Coefficient C3"] #[inline(always)] #[must_use] - pub fn c3(&mut self) -> C3_W<0> { + pub fn c3(&mut self) -> C3_W { C3_W::new(self) } #[doc = "Bits 8:14 - Color Space Conversion Matrix Coefficient C4"] #[inline(always)] #[must_use] - pub fn c4(&mut self) -> C4_W<8> { + pub fn c4(&mut self) -> C4_W { C4_W::new(self) } #[doc = "Bits 16:22 - Color Space Conversion Matrix Coefficient C5"] #[inline(always)] #[must_use] - pub fn c5(&mut self) -> C5_W<16> { + pub fn c5(&mut self) -> C5_W { C5_W::new(self) } #[doc = "Bit 24 - Color Space Conversion Green Component Offset"] #[inline(always)] #[must_use] - pub fn goff(&mut self) -> GOFF_W<24> { + pub fn goff(&mut self) -> GOFF_W { GOFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Color Space Conversion RGB To YCrCb Set 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r2y_set1](index.html) module"] +#[doc = "ISI Color Space Conversion RGB To YCrCb Set 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2y_set1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2y_set1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct R2Y_SET1_SPEC; impl crate::RegisterSpec for R2Y_SET1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [r2y_set1::R](R) reader structure"] -impl crate::Readable for R2Y_SET1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [r2y_set1::W](W) writer structure"] +#[doc = "`read()` method returns [`r2y_set1::R`](R) reader structure"] +impl crate::Readable for R2Y_SET1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`r2y_set1::W`](W) writer structure"] impl crate::Writable for R2Y_SET1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/r2y_set2.rs b/arch/cortex-m/samv71q21-pac/src/isi/r2y_set2.rs index 8a730ef3..cfebd874 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/r2y_set2.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/r2y_set2.rs @@ -1,55 +1,23 @@ #[doc = "Register `R2Y_SET2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `R2Y_SET2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C6` reader - Color Space Conversion Matrix Coefficient C6"] pub type C6_R = crate::FieldReader; #[doc = "Field `C6` writer - Color Space Conversion Matrix Coefficient C6"] -pub type C6_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET2_SPEC, 7, O>; +pub type C6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `C7` reader - Color Space Conversion Matrix Coefficient C7"] pub type C7_R = crate::FieldReader; #[doc = "Field `C7` writer - Color Space Conversion Matrix Coefficient C7"] -pub type C7_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET2_SPEC, 7, O>; +pub type C7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `C8` reader - Color Space Conversion Matrix Coefficient C8"] pub type C8_R = crate::FieldReader; #[doc = "Field `C8` writer - Color Space Conversion Matrix Coefficient C8"] -pub type C8_W<'a, const O: u8> = crate::FieldWriter<'a, R2Y_SET2_SPEC, 7, O>; +pub type C8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `Boff` reader - Color Space Conversion Blue Component Offset"] pub type BOFF_R = crate::BitReader; #[doc = "Field `Boff` writer - Color Space Conversion Blue Component Offset"] -pub type BOFF_W<'a, const O: u8> = crate::BitWriter<'a, R2Y_SET2_SPEC, O>; +pub type BOFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Color Space Conversion Matrix Coefficient C6"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - Color Space Conversion Matrix Coefficient C6"] #[inline(always)] #[must_use] - pub fn c6(&mut self) -> C6_W<0> { + pub fn c6(&mut self) -> C6_W { C6_W::new(self) } #[doc = "Bits 8:14 - Color Space Conversion Matrix Coefficient C7"] #[inline(always)] #[must_use] - pub fn c7(&mut self) -> C7_W<8> { + pub fn c7(&mut self) -> C7_W { C7_W::new(self) } #[doc = "Bits 16:22 - Color Space Conversion Matrix Coefficient C8"] #[inline(always)] #[must_use] - pub fn c8(&mut self) -> C8_W<16> { + pub fn c8(&mut self) -> C8_W { C8_W::new(self) } #[doc = "Bit 24 - Color Space Conversion Blue Component Offset"] #[inline(always)] #[must_use] - pub fn boff(&mut self) -> BOFF_W<24> { + pub fn boff(&mut self) -> BOFF_W { BOFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Color Space Conversion RGB To YCrCb Set 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r2y_set2](index.html) module"] +#[doc = "ISI Color Space Conversion RGB To YCrCb Set 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2y_set2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2y_set2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct R2Y_SET2_SPEC; impl crate::RegisterSpec for R2Y_SET2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [r2y_set2::R](R) reader structure"] -impl crate::Readable for R2Y_SET2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [r2y_set2::W](W) writer structure"] +#[doc = "`read()` method returns [`r2y_set2::R`](R) reader structure"] +impl crate::Readable for R2Y_SET2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`r2y_set2::W`](W) writer structure"] impl crate::Writable for R2Y_SET2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/sr.rs b/arch/cortex-m/samv71q21-pac/src/isi/sr.rs index 614d1b12..17a6a31f 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ENABLE` reader - Module Enable"] pub type ENABLE_R = crate::BitReader; #[doc = "Field `DIS_DONE` reader - Module Disable Request has Terminated (cleared on read)"] @@ -99,15 +86,13 @@ impl R { FR_OVR_R::new(((self.bits >> 27) & 1) != 0) } } -#[doc = "ISI Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "ISI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/isi/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/isi/wpmr.rs index 7c727315..88c78641 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key Password"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key Password\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key Password"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key Password"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/isi/wpsr.rs index 69b9952f..216a7a8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/isi/y2r_set0.rs b/arch/cortex-m/samv71q21-pac/src/isi/y2r_set0.rs index e3c4089f..f04ccd7e 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/y2r_set0.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/y2r_set0.rs @@ -1,55 +1,23 @@ #[doc = "Register `Y2R_SET0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `Y2R_SET0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C0` reader - Color Space Conversion Matrix Coefficient C0"] pub type C0_R = crate::FieldReader; #[doc = "Field `C0` writer - Color Space Conversion Matrix Coefficient C0"] -pub type C0_W<'a, const O: u8> = crate::FieldWriter<'a, Y2R_SET0_SPEC, 8, O>; +pub type C0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `C1` reader - Color Space Conversion Matrix Coefficient C1"] pub type C1_R = crate::FieldReader; #[doc = "Field `C1` writer - Color Space Conversion Matrix Coefficient C1"] -pub type C1_W<'a, const O: u8> = crate::FieldWriter<'a, Y2R_SET0_SPEC, 8, O>; +pub type C1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `C2` reader - Color Space Conversion Matrix Coefficient C2"] pub type C2_R = crate::FieldReader; #[doc = "Field `C2` writer - Color Space Conversion Matrix Coefficient C2"] -pub type C2_W<'a, const O: u8> = crate::FieldWriter<'a, Y2R_SET0_SPEC, 8, O>; +pub type C2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `C3` reader - Color Space Conversion Matrix Coefficient C3"] pub type C3_R = crate::FieldReader; #[doc = "Field `C3` writer - Color Space Conversion Matrix Coefficient C3"] -pub type C3_W<'a, const O: u8> = crate::FieldWriter<'a, Y2R_SET0_SPEC, 8, O>; +pub type C3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Color Space Conversion Matrix Coefficient C0"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:7 - Color Space Conversion Matrix Coefficient C0"] #[inline(always)] #[must_use] - pub fn c0(&mut self) -> C0_W<0> { + pub fn c0(&mut self) -> C0_W { C0_W::new(self) } #[doc = "Bits 8:15 - Color Space Conversion Matrix Coefficient C1"] #[inline(always)] #[must_use] - pub fn c1(&mut self) -> C1_W<8> { + pub fn c1(&mut self) -> C1_W { C1_W::new(self) } #[doc = "Bits 16:23 - Color Space Conversion Matrix Coefficient C2"] #[inline(always)] #[must_use] - pub fn c2(&mut self) -> C2_W<16> { + pub fn c2(&mut self) -> C2_W { C2_W::new(self) } #[doc = "Bits 24:31 - Color Space Conversion Matrix Coefficient C3"] #[inline(always)] #[must_use] - pub fn c3(&mut self) -> C3_W<24> { + pub fn c3(&mut self) -> C3_W { C3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Color Space Conversion YCrCb To RGB Set 0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [y2r_set0](index.html) module"] +#[doc = "ISI Color Space Conversion YCrCb To RGB Set 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y2r_set0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y2r_set0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Y2R_SET0_SPEC; impl crate::RegisterSpec for Y2R_SET0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [y2r_set0::R](R) reader structure"] -impl crate::Readable for Y2R_SET0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [y2r_set0::W](W) writer structure"] +#[doc = "`read()` method returns [`y2r_set0::R`](R) reader structure"] +impl crate::Readable for Y2R_SET0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`y2r_set0::W`](W) writer structure"] impl crate::Writable for Y2R_SET0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/isi/y2r_set1.rs b/arch/cortex-m/samv71q21-pac/src/isi/y2r_set1.rs index 3c5ee85a..21053599 100644 --- a/arch/cortex-m/samv71q21-pac/src/isi/y2r_set1.rs +++ b/arch/cortex-m/samv71q21-pac/src/isi/y2r_set1.rs @@ -1,55 +1,23 @@ #[doc = "Register `Y2R_SET1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `Y2R_SET1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `C4` reader - Color Space Conversion Matrix Coefficient C4"] pub type C4_R = crate::FieldReader; #[doc = "Field `C4` writer - Color Space Conversion Matrix Coefficient C4"] -pub type C4_W<'a, const O: u8> = crate::FieldWriter<'a, Y2R_SET1_SPEC, 9, O, u16>; +pub type C4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `Yoff` reader - Color Space Conversion Luminance Default Offset"] pub type YOFF_R = crate::BitReader; #[doc = "Field `Yoff` writer - Color Space Conversion Luminance Default Offset"] -pub type YOFF_W<'a, const O: u8> = crate::BitWriter<'a, Y2R_SET1_SPEC, O>; +pub type YOFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `Croff` reader - Color Space Conversion Red Chrominance Default Offset"] pub type CROFF_R = crate::BitReader; #[doc = "Field `Croff` writer - Color Space Conversion Red Chrominance Default Offset"] -pub type CROFF_W<'a, const O: u8> = crate::BitWriter<'a, Y2R_SET1_SPEC, O>; +pub type CROFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `Cboff` reader - Color Space Conversion Blue Chrominance Default Offset"] pub type CBOFF_R = crate::BitReader; #[doc = "Field `Cboff` writer - Color Space Conversion Blue Chrominance Default Offset"] -pub type CBOFF_W<'a, const O: u8> = crate::BitWriter<'a, Y2R_SET1_SPEC, O>; +pub type CBOFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:8 - Color Space Conversion Matrix Coefficient C4"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:8 - Color Space Conversion Matrix Coefficient C4"] #[inline(always)] #[must_use] - pub fn c4(&mut self) -> C4_W<0> { + pub fn c4(&mut self) -> C4_W { C4_W::new(self) } #[doc = "Bit 12 - Color Space Conversion Luminance Default Offset"] #[inline(always)] #[must_use] - pub fn yoff(&mut self) -> YOFF_W<12> { + pub fn yoff(&mut self) -> YOFF_W { YOFF_W::new(self) } #[doc = "Bit 13 - Color Space Conversion Red Chrominance Default Offset"] #[inline(always)] #[must_use] - pub fn croff(&mut self) -> CROFF_W<13> { + pub fn croff(&mut self) -> CROFF_W { CROFF_W::new(self) } #[doc = "Bit 14 - Color Space Conversion Blue Chrominance Default Offset"] #[inline(always)] #[must_use] - pub fn cboff(&mut self) -> CBOFF_W<14> { + pub fn cboff(&mut self) -> CBOFF_W { CBOFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "ISI Color Space Conversion YCrCb To RGB Set 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [y2r_set1](index.html) module"] +#[doc = "ISI Color Space Conversion YCrCb To RGB Set 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`y2r_set1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`y2r_set1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct Y2R_SET1_SPEC; impl crate::RegisterSpec for Y2R_SET1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [y2r_set1::R](R) reader structure"] -impl crate::Readable for Y2R_SET1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [y2r_set1::W](W) writer structure"] +#[doc = "`read()` method returns [`y2r_set1::R`](R) reader structure"] +impl crate::Readable for Y2R_SET1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`y2r_set1::W`](W) writer structure"] impl crate::Writable for Y2R_SET1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/lib.rs b/arch/cortex-m/samv71q21-pac/src/lib.rs index 2303a596..79ff81a7 100644 --- a/arch/cortex-m/samv71q21-pac/src/lib.rs +++ b/arch/cortex-m/samv71q21-pac/src/lib.rs @@ -1,5 +1,5 @@ -#![doc = "Peripheral access API for ATSAMV71Q21B microcontrollers (generated using svd2rust v0.29.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.29.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for ATSAMV71Q21B microcontrollers (generated using svd2rust v0.30.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![deny(dead_code)] #![deny(improper_ctypes)] #![deny(missing_docs)] @@ -361,6 +361,24 @@ impl ACC { pub const fn ptr() -> *const acc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for ACC { type Target = acc::RegisterBlock; @@ -389,6 +407,24 @@ impl AES { pub const fn ptr() -> *const aes::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for AES { type Target = aes::RegisterBlock; @@ -417,6 +453,24 @@ impl AFEC0 { pub const fn ptr() -> *const afec0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for AFEC0 { type Target = afec0::RegisterBlock; @@ -445,6 +499,24 @@ impl AFEC1 { pub const fn ptr() -> *const afec0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for AFEC1 { type Target = afec0::RegisterBlock; @@ -473,6 +545,24 @@ impl CHIPID { pub const fn ptr() -> *const chipid::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CHIPID { type Target = chipid::RegisterBlock; @@ -501,6 +591,24 @@ impl DACC { pub const fn ptr() -> *const dacc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for DACC { type Target = dacc::RegisterBlock; @@ -529,6 +637,24 @@ impl EFC { pub const fn ptr() -> *const efc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for EFC { type Target = efc::RegisterBlock; @@ -557,6 +683,24 @@ impl GMAC { pub const fn ptr() -> *const gmac::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GMAC { type Target = gmac::RegisterBlock; @@ -585,6 +729,24 @@ impl GPBR { pub const fn ptr() -> *const gpbr::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for GPBR { type Target = gpbr::RegisterBlock; @@ -613,6 +775,24 @@ impl HSMCI { pub const fn ptr() -> *const hsmci::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for HSMCI { type Target = hsmci::RegisterBlock; @@ -641,6 +821,24 @@ impl I2SC0 { pub const fn ptr() -> *const i2sc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for I2SC0 { type Target = i2sc0::RegisterBlock; @@ -669,6 +867,24 @@ impl I2SC1 { pub const fn ptr() -> *const i2sc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for I2SC1 { type Target = i2sc0::RegisterBlock; @@ -697,6 +913,24 @@ impl ICM { pub const fn ptr() -> *const icm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for ICM { type Target = icm::RegisterBlock; @@ -725,6 +959,24 @@ impl ISI { pub const fn ptr() -> *const isi::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for ISI { type Target = isi::RegisterBlock; @@ -753,6 +1005,24 @@ impl MATRIX { pub const fn ptr() -> *const matrix::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for MATRIX { type Target = matrix::RegisterBlock; @@ -781,6 +1051,24 @@ impl MCAN0 { pub const fn ptr() -> *const mcan0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for MCAN0 { type Target = mcan0::RegisterBlock; @@ -809,6 +1097,24 @@ impl MCAN1 { pub const fn ptr() -> *const mcan0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for MCAN1 { type Target = mcan0::RegisterBlock; @@ -837,6 +1143,24 @@ impl MLB { pub const fn ptr() -> *const mlb::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for MLB { type Target = mlb::RegisterBlock; @@ -865,6 +1189,24 @@ impl PIOA { pub const fn ptr() -> *const pioa::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIOA { type Target = pioa::RegisterBlock; @@ -893,6 +1235,24 @@ impl PIOB { pub const fn ptr() -> *const pioa::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIOB { type Target = pioa::RegisterBlock; @@ -921,6 +1281,24 @@ impl PIOC { pub const fn ptr() -> *const pioa::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIOC { type Target = pioa::RegisterBlock; @@ -949,6 +1327,24 @@ impl PIOD { pub const fn ptr() -> *const pioa::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIOD { type Target = pioa::RegisterBlock; @@ -977,6 +1373,24 @@ impl PIOE { pub const fn ptr() -> *const pioa::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PIOE { type Target = pioa::RegisterBlock; @@ -1005,6 +1419,24 @@ impl PMC { pub const fn ptr() -> *const pmc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PMC { type Target = pmc::RegisterBlock; @@ -1033,6 +1465,24 @@ impl PWM0 { pub const fn ptr() -> *const pwm0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM0 { type Target = pwm0::RegisterBlock; @@ -1061,6 +1511,24 @@ impl PWM1 { pub const fn ptr() -> *const pwm0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for PWM1 { type Target = pwm0::RegisterBlock; @@ -1089,6 +1557,24 @@ impl QSPI { pub const fn ptr() -> *const qspi::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for QSPI { type Target = qspi::RegisterBlock; @@ -1117,6 +1603,24 @@ impl RSTC { pub const fn ptr() -> *const rstc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for RSTC { type Target = rstc::RegisterBlock; @@ -1145,6 +1649,24 @@ impl RSWDT { pub const fn ptr() -> *const rswdt::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for RSWDT { type Target = rswdt::RegisterBlock; @@ -1173,6 +1695,24 @@ impl RTC { pub const fn ptr() -> *const rtc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for RTC { type Target = rtc::RegisterBlock; @@ -1201,6 +1741,24 @@ impl RTT { pub const fn ptr() -> *const rtt::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for RTT { type Target = rtt::RegisterBlock; @@ -1229,6 +1787,24 @@ impl SMC { pub const fn ptr() -> *const smc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SMC { type Target = smc::RegisterBlock; @@ -1257,6 +1833,24 @@ impl SPI0 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI0 { type Target = spi0::RegisterBlock; @@ -1285,6 +1879,24 @@ impl SPI1 { pub const fn ptr() -> *const spi0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SPI1 { type Target = spi0::RegisterBlock; @@ -1313,6 +1925,24 @@ impl SSC { pub const fn ptr() -> *const ssc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SSC { type Target = ssc::RegisterBlock; @@ -1341,6 +1971,24 @@ impl SUPC { pub const fn ptr() -> *const supc::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SUPC { type Target = supc::RegisterBlock; @@ -1369,6 +2017,24 @@ impl TC0 { pub const fn ptr() -> *const tc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TC0 { type Target = tc0::RegisterBlock; @@ -1397,6 +2063,24 @@ impl TC1 { pub const fn ptr() -> *const tc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TC1 { type Target = tc0::RegisterBlock; @@ -1425,6 +2109,24 @@ impl TC2 { pub const fn ptr() -> *const tc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TC2 { type Target = tc0::RegisterBlock; @@ -1453,6 +2155,24 @@ impl TC3 { pub const fn ptr() -> *const tc0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TC3 { type Target = tc0::RegisterBlock; @@ -1481,6 +2201,24 @@ impl TRNG { pub const fn ptr() -> *const trng::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TRNG { type Target = trng::RegisterBlock; @@ -1509,6 +2247,24 @@ impl TWIHS0 { pub const fn ptr() -> *const twihs0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TWIHS0 { type Target = twihs0::RegisterBlock; @@ -1537,6 +2293,24 @@ impl TWIHS1 { pub const fn ptr() -> *const twihs0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TWIHS1 { type Target = twihs0::RegisterBlock; @@ -1565,6 +2339,24 @@ impl TWIHS2 { pub const fn ptr() -> *const twihs0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for TWIHS2 { type Target = twihs0::RegisterBlock; @@ -1593,6 +2385,24 @@ impl UART0 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART0 { type Target = uart0::RegisterBlock; @@ -1621,6 +2431,24 @@ impl UART1 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART1 { type Target = uart0::RegisterBlock; @@ -1649,6 +2477,24 @@ impl UART2 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART2 { type Target = uart0::RegisterBlock; @@ -1677,6 +2523,24 @@ impl UART3 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART3 { type Target = uart0::RegisterBlock; @@ -1705,6 +2569,24 @@ impl UART4 { pub const fn ptr() -> *const uart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UART4 { type Target = uart0::RegisterBlock; @@ -1733,6 +2615,24 @@ impl USART0 { pub const fn ptr() -> *const usart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USART0 { type Target = usart0::RegisterBlock; @@ -1761,6 +2661,24 @@ impl USART1 { pub const fn ptr() -> *const usart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USART1 { type Target = usart0::RegisterBlock; @@ -1789,6 +2707,24 @@ impl USART2 { pub const fn ptr() -> *const usart0::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USART2 { type Target = usart0::RegisterBlock; @@ -1817,6 +2753,24 @@ impl USBHS { pub const fn ptr() -> *const usbhs::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for USBHS { type Target = usbhs::RegisterBlock; @@ -1845,6 +2799,24 @@ impl UTMI { pub const fn ptr() -> *const utmi::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for UTMI { type Target = utmi::RegisterBlock; @@ -1873,6 +2845,24 @@ impl WDT { pub const fn ptr() -> *const wdt::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for WDT { type Target = wdt::RegisterBlock; @@ -1901,6 +2891,24 @@ impl XDMAC { pub const fn ptr() -> *const xdmac::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for XDMAC { type Target = xdmac::RegisterBlock; @@ -1929,6 +2937,24 @@ impl LOCKBIT { pub const fn ptr() -> *const lockbit::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for LOCKBIT { type Target = lockbit::RegisterBlock; @@ -1957,6 +2983,24 @@ impl SCN_SCB { pub const fn ptr() -> *const scn_scb::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SCN_SCB { type Target = scn_scb::RegisterBlock; @@ -1985,6 +3029,24 @@ impl SYS_TICK { pub const fn ptr() -> *const sys_tick::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for SYS_TICK { type Target = sys_tick::RegisterBlock; @@ -2013,6 +3075,24 @@ impl CORE_DEBUG { pub const fn ptr() -> *const core_debug::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for CORE_DEBUG { type Target = core_debug::RegisterBlock; @@ -2041,6 +3121,24 @@ impl ETM { pub const fn ptr() -> *const etm::RegisterBlock { Self::PTR } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } } impl Deref for ETM { type Target = etm::RegisterBlock; diff --git a/arch/cortex-m/samv71q21-pac/src/lockbit.rs b/arch/cortex-m/samv71q21-pac/src/lockbit.rs index 679b0527..abe5e8a5 100644 --- a/arch/cortex-m/samv71q21-pac/src/lockbit.rs +++ b/arch/cortex-m/samv71q21-pac/src/lockbit.rs @@ -10,19 +10,23 @@ pub struct RegisterBlock { #[doc = "0x0c - Lock Bits Word 3"] pub word3: WORD3, } -#[doc = "WORD0 (rw) register accessor: an alias for `Reg`"] +#[doc = "WORD0 (rw) register accessor: Lock Bits Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`word0`] +module"] pub type WORD0 = crate::Reg; #[doc = "Lock Bits Word 0"] pub mod word0; -#[doc = "WORD1 (rw) register accessor: an alias for `Reg`"] +#[doc = "WORD1 (rw) register accessor: Lock Bits Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`word1`] +module"] pub type WORD1 = crate::Reg; #[doc = "Lock Bits Word 1"] pub mod word1; -#[doc = "WORD2 (rw) register accessor: an alias for `Reg`"] +#[doc = "WORD2 (rw) register accessor: Lock Bits Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`word2`] +module"] pub type WORD2 = crate::Reg; #[doc = "Lock Bits Word 2"] pub mod word2; -#[doc = "WORD3 (rw) register accessor: an alias for `Reg`"] +#[doc = "WORD3 (rw) register accessor: Lock Bits Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`word3`] +module"] pub type WORD3 = crate::Reg; #[doc = "Lock Bits Word 3"] pub mod word3; diff --git a/arch/cortex-m/samv71q21-pac/src/lockbit/word0.rs b/arch/cortex-m/samv71q21-pac/src/lockbit/word0.rs index df1dc3cb..be388eb2 100644 --- a/arch/cortex-m/samv71q21-pac/src/lockbit/word0.rs +++ b/arch/cortex-m/samv71q21-pac/src/lockbit/word0.rs @@ -1,167 +1,135 @@ #[doc = "Register `WORD0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WORD0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOCK_REGION_0` reader - Lock Region 0"] pub type LOCK_REGION_0_R = crate::BitReader; #[doc = "Field `LOCK_REGION_0` writer - Lock Region 0"] -pub type LOCK_REGION_0_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_1` reader - Lock Region 1"] pub type LOCK_REGION_1_R = crate::BitReader; #[doc = "Field `LOCK_REGION_1` writer - Lock Region 1"] -pub type LOCK_REGION_1_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_2` reader - Lock Region 2"] pub type LOCK_REGION_2_R = crate::BitReader; #[doc = "Field `LOCK_REGION_2` writer - Lock Region 2"] -pub type LOCK_REGION_2_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_3` reader - Lock Region 3"] pub type LOCK_REGION_3_R = crate::BitReader; #[doc = "Field `LOCK_REGION_3` writer - Lock Region 3"] -pub type LOCK_REGION_3_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_4` reader - Lock Region 4"] pub type LOCK_REGION_4_R = crate::BitReader; #[doc = "Field `LOCK_REGION_4` writer - Lock Region 4"] -pub type LOCK_REGION_4_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_5` reader - Lock Region 5"] pub type LOCK_REGION_5_R = crate::BitReader; #[doc = "Field `LOCK_REGION_5` writer - Lock Region 5"] -pub type LOCK_REGION_5_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_6` reader - Lock Region 6"] pub type LOCK_REGION_6_R = crate::BitReader; #[doc = "Field `LOCK_REGION_6` writer - Lock Region 6"] -pub type LOCK_REGION_6_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_7` reader - Lock Region 7"] pub type LOCK_REGION_7_R = crate::BitReader; #[doc = "Field `LOCK_REGION_7` writer - Lock Region 7"] -pub type LOCK_REGION_7_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_8` reader - Lock Region 8"] pub type LOCK_REGION_8_R = crate::BitReader; #[doc = "Field `LOCK_REGION_8` writer - Lock Region 8"] -pub type LOCK_REGION_8_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_9` reader - Lock Region 9"] pub type LOCK_REGION_9_R = crate::BitReader; #[doc = "Field `LOCK_REGION_9` writer - Lock Region 9"] -pub type LOCK_REGION_9_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_10` reader - Lock Region 10"] pub type LOCK_REGION_10_R = crate::BitReader; #[doc = "Field `LOCK_REGION_10` writer - Lock Region 10"] -pub type LOCK_REGION_10_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_11` reader - Lock Region 11"] pub type LOCK_REGION_11_R = crate::BitReader; #[doc = "Field `LOCK_REGION_11` writer - Lock Region 11"] -pub type LOCK_REGION_11_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_12` reader - Lock Region 12"] pub type LOCK_REGION_12_R = crate::BitReader; #[doc = "Field `LOCK_REGION_12` writer - Lock Region 12"] -pub type LOCK_REGION_12_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_13` reader - Lock Region 13"] pub type LOCK_REGION_13_R = crate::BitReader; #[doc = "Field `LOCK_REGION_13` writer - Lock Region 13"] -pub type LOCK_REGION_13_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_14` reader - Lock Region 14"] pub type LOCK_REGION_14_R = crate::BitReader; #[doc = "Field `LOCK_REGION_14` writer - Lock Region 14"] -pub type LOCK_REGION_14_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_15` reader - Lock Region 15"] pub type LOCK_REGION_15_R = crate::BitReader; #[doc = "Field `LOCK_REGION_15` writer - Lock Region 15"] -pub type LOCK_REGION_15_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_16` reader - Lock Region 16"] pub type LOCK_REGION_16_R = crate::BitReader; #[doc = "Field `LOCK_REGION_16` writer - Lock Region 16"] -pub type LOCK_REGION_16_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_17` reader - Lock Region 17"] pub type LOCK_REGION_17_R = crate::BitReader; #[doc = "Field `LOCK_REGION_17` writer - Lock Region 17"] -pub type LOCK_REGION_17_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_18` reader - Lock Region 18"] pub type LOCK_REGION_18_R = crate::BitReader; #[doc = "Field `LOCK_REGION_18` writer - Lock Region 18"] -pub type LOCK_REGION_18_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_19` reader - Lock Region 19"] pub type LOCK_REGION_19_R = crate::BitReader; #[doc = "Field `LOCK_REGION_19` writer - Lock Region 19"] -pub type LOCK_REGION_19_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_20` reader - Lock Region 20"] pub type LOCK_REGION_20_R = crate::BitReader; #[doc = "Field `LOCK_REGION_20` writer - Lock Region 20"] -pub type LOCK_REGION_20_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_21` reader - Lock Region 21"] pub type LOCK_REGION_21_R = crate::BitReader; #[doc = "Field `LOCK_REGION_21` writer - Lock Region 21"] -pub type LOCK_REGION_21_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_22` reader - Lock Region 22"] pub type LOCK_REGION_22_R = crate::BitReader; #[doc = "Field `LOCK_REGION_22` writer - Lock Region 22"] -pub type LOCK_REGION_22_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_23` reader - Lock Region 23"] pub type LOCK_REGION_23_R = crate::BitReader; #[doc = "Field `LOCK_REGION_23` writer - Lock Region 23"] -pub type LOCK_REGION_23_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_24` reader - Lock Region 24"] pub type LOCK_REGION_24_R = crate::BitReader; #[doc = "Field `LOCK_REGION_24` writer - Lock Region 24"] -pub type LOCK_REGION_24_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_25` reader - Lock Region 25"] pub type LOCK_REGION_25_R = crate::BitReader; #[doc = "Field `LOCK_REGION_25` writer - Lock Region 25"] -pub type LOCK_REGION_25_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_26` reader - Lock Region 26"] pub type LOCK_REGION_26_R = crate::BitReader; #[doc = "Field `LOCK_REGION_26` writer - Lock Region 26"] -pub type LOCK_REGION_26_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_27` reader - Lock Region 27"] pub type LOCK_REGION_27_R = crate::BitReader; #[doc = "Field `LOCK_REGION_27` writer - Lock Region 27"] -pub type LOCK_REGION_27_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_28` reader - Lock Region 28"] pub type LOCK_REGION_28_R = crate::BitReader; #[doc = "Field `LOCK_REGION_28` writer - Lock Region 28"] -pub type LOCK_REGION_28_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_29` reader - Lock Region 29"] pub type LOCK_REGION_29_R = crate::BitReader; #[doc = "Field `LOCK_REGION_29` writer - Lock Region 29"] -pub type LOCK_REGION_29_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_30` reader - Lock Region 30"] pub type LOCK_REGION_30_R = crate::BitReader; #[doc = "Field `LOCK_REGION_30` writer - Lock Region 30"] -pub type LOCK_REGION_30_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_31` reader - Lock Region 31"] pub type LOCK_REGION_31_R = crate::BitReader; #[doc = "Field `LOCK_REGION_31` writer - Lock Region 31"] -pub type LOCK_REGION_31_W<'a, const O: u8> = crate::BitWriter<'a, WORD0_SPEC, O>; +pub type LOCK_REGION_31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Lock Region 0"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Lock Region 0"] #[inline(always)] #[must_use] - pub fn lock_region_0(&mut self) -> LOCK_REGION_0_W<0> { + pub fn lock_region_0(&mut self) -> LOCK_REGION_0_W { LOCK_REGION_0_W::new(self) } #[doc = "Bit 1 - Lock Region 1"] #[inline(always)] #[must_use] - pub fn lock_region_1(&mut self) -> LOCK_REGION_1_W<1> { + pub fn lock_region_1(&mut self) -> LOCK_REGION_1_W { LOCK_REGION_1_W::new(self) } #[doc = "Bit 2 - Lock Region 2"] #[inline(always)] #[must_use] - pub fn lock_region_2(&mut self) -> LOCK_REGION_2_W<2> { + pub fn lock_region_2(&mut self) -> LOCK_REGION_2_W { LOCK_REGION_2_W::new(self) } #[doc = "Bit 3 - Lock Region 3"] #[inline(always)] #[must_use] - pub fn lock_region_3(&mut self) -> LOCK_REGION_3_W<3> { + pub fn lock_region_3(&mut self) -> LOCK_REGION_3_W { LOCK_REGION_3_W::new(self) } #[doc = "Bit 4 - Lock Region 4"] #[inline(always)] #[must_use] - pub fn lock_region_4(&mut self) -> LOCK_REGION_4_W<4> { + pub fn lock_region_4(&mut self) -> LOCK_REGION_4_W { LOCK_REGION_4_W::new(self) } #[doc = "Bit 5 - Lock Region 5"] #[inline(always)] #[must_use] - pub fn lock_region_5(&mut self) -> LOCK_REGION_5_W<5> { + pub fn lock_region_5(&mut self) -> LOCK_REGION_5_W { LOCK_REGION_5_W::new(self) } #[doc = "Bit 6 - Lock Region 6"] #[inline(always)] #[must_use] - pub fn lock_region_6(&mut self) -> LOCK_REGION_6_W<6> { + pub fn lock_region_6(&mut self) -> LOCK_REGION_6_W { LOCK_REGION_6_W::new(self) } #[doc = "Bit 7 - Lock Region 7"] #[inline(always)] #[must_use] - pub fn lock_region_7(&mut self) -> LOCK_REGION_7_W<7> { + pub fn lock_region_7(&mut self) -> LOCK_REGION_7_W { LOCK_REGION_7_W::new(self) } #[doc = "Bit 8 - Lock Region 8"] #[inline(always)] #[must_use] - pub fn lock_region_8(&mut self) -> LOCK_REGION_8_W<8> { + pub fn lock_region_8(&mut self) -> LOCK_REGION_8_W { LOCK_REGION_8_W::new(self) } #[doc = "Bit 9 - Lock Region 9"] #[inline(always)] #[must_use] - pub fn lock_region_9(&mut self) -> LOCK_REGION_9_W<9> { + pub fn lock_region_9(&mut self) -> LOCK_REGION_9_W { LOCK_REGION_9_W::new(self) } #[doc = "Bit 10 - Lock Region 10"] #[inline(always)] #[must_use] - pub fn lock_region_10(&mut self) -> LOCK_REGION_10_W<10> { + pub fn lock_region_10(&mut self) -> LOCK_REGION_10_W { LOCK_REGION_10_W::new(self) } #[doc = "Bit 11 - Lock Region 11"] #[inline(always)] #[must_use] - pub fn lock_region_11(&mut self) -> LOCK_REGION_11_W<11> { + pub fn lock_region_11(&mut self) -> LOCK_REGION_11_W { LOCK_REGION_11_W::new(self) } #[doc = "Bit 12 - Lock Region 12"] #[inline(always)] #[must_use] - pub fn lock_region_12(&mut self) -> LOCK_REGION_12_W<12> { + pub fn lock_region_12(&mut self) -> LOCK_REGION_12_W { LOCK_REGION_12_W::new(self) } #[doc = "Bit 13 - Lock Region 13"] #[inline(always)] #[must_use] - pub fn lock_region_13(&mut self) -> LOCK_REGION_13_W<13> { + pub fn lock_region_13(&mut self) -> LOCK_REGION_13_W { LOCK_REGION_13_W::new(self) } #[doc = "Bit 14 - Lock Region 14"] #[inline(always)] #[must_use] - pub fn lock_region_14(&mut self) -> LOCK_REGION_14_W<14> { + pub fn lock_region_14(&mut self) -> LOCK_REGION_14_W { LOCK_REGION_14_W::new(self) } #[doc = "Bit 15 - Lock Region 15"] #[inline(always)] #[must_use] - pub fn lock_region_15(&mut self) -> LOCK_REGION_15_W<15> { + pub fn lock_region_15(&mut self) -> LOCK_REGION_15_W { LOCK_REGION_15_W::new(self) } #[doc = "Bit 16 - Lock Region 16"] #[inline(always)] #[must_use] - pub fn lock_region_16(&mut self) -> LOCK_REGION_16_W<16> { + pub fn lock_region_16(&mut self) -> LOCK_REGION_16_W { LOCK_REGION_16_W::new(self) } #[doc = "Bit 17 - Lock Region 17"] #[inline(always)] #[must_use] - pub fn lock_region_17(&mut self) -> LOCK_REGION_17_W<17> { + pub fn lock_region_17(&mut self) -> LOCK_REGION_17_W { LOCK_REGION_17_W::new(self) } #[doc = "Bit 18 - Lock Region 18"] #[inline(always)] #[must_use] - pub fn lock_region_18(&mut self) -> LOCK_REGION_18_W<18> { + pub fn lock_region_18(&mut self) -> LOCK_REGION_18_W { LOCK_REGION_18_W::new(self) } #[doc = "Bit 19 - Lock Region 19"] #[inline(always)] #[must_use] - pub fn lock_region_19(&mut self) -> LOCK_REGION_19_W<19> { + pub fn lock_region_19(&mut self) -> LOCK_REGION_19_W { LOCK_REGION_19_W::new(self) } #[doc = "Bit 20 - Lock Region 20"] #[inline(always)] #[must_use] - pub fn lock_region_20(&mut self) -> LOCK_REGION_20_W<20> { + pub fn lock_region_20(&mut self) -> LOCK_REGION_20_W { LOCK_REGION_20_W::new(self) } #[doc = "Bit 21 - Lock Region 21"] #[inline(always)] #[must_use] - pub fn lock_region_21(&mut self) -> LOCK_REGION_21_W<21> { + pub fn lock_region_21(&mut self) -> LOCK_REGION_21_W { LOCK_REGION_21_W::new(self) } #[doc = "Bit 22 - Lock Region 22"] #[inline(always)] #[must_use] - pub fn lock_region_22(&mut self) -> LOCK_REGION_22_W<22> { + pub fn lock_region_22(&mut self) -> LOCK_REGION_22_W { LOCK_REGION_22_W::new(self) } #[doc = "Bit 23 - Lock Region 23"] #[inline(always)] #[must_use] - pub fn lock_region_23(&mut self) -> LOCK_REGION_23_W<23> { + pub fn lock_region_23(&mut self) -> LOCK_REGION_23_W { LOCK_REGION_23_W::new(self) } #[doc = "Bit 24 - Lock Region 24"] #[inline(always)] #[must_use] - pub fn lock_region_24(&mut self) -> LOCK_REGION_24_W<24> { + pub fn lock_region_24(&mut self) -> LOCK_REGION_24_W { LOCK_REGION_24_W::new(self) } #[doc = "Bit 25 - Lock Region 25"] #[inline(always)] #[must_use] - pub fn lock_region_25(&mut self) -> LOCK_REGION_25_W<25> { + pub fn lock_region_25(&mut self) -> LOCK_REGION_25_W { LOCK_REGION_25_W::new(self) } #[doc = "Bit 26 - Lock Region 26"] #[inline(always)] #[must_use] - pub fn lock_region_26(&mut self) -> LOCK_REGION_26_W<26> { + pub fn lock_region_26(&mut self) -> LOCK_REGION_26_W { LOCK_REGION_26_W::new(self) } #[doc = "Bit 27 - Lock Region 27"] #[inline(always)] #[must_use] - pub fn lock_region_27(&mut self) -> LOCK_REGION_27_W<27> { + pub fn lock_region_27(&mut self) -> LOCK_REGION_27_W { LOCK_REGION_27_W::new(self) } #[doc = "Bit 28 - Lock Region 28"] #[inline(always)] #[must_use] - pub fn lock_region_28(&mut self) -> LOCK_REGION_28_W<28> { + pub fn lock_region_28(&mut self) -> LOCK_REGION_28_W { LOCK_REGION_28_W::new(self) } #[doc = "Bit 29 - Lock Region 29"] #[inline(always)] #[must_use] - pub fn lock_region_29(&mut self) -> LOCK_REGION_29_W<29> { + pub fn lock_region_29(&mut self) -> LOCK_REGION_29_W { LOCK_REGION_29_W::new(self) } #[doc = "Bit 30 - Lock Region 30"] #[inline(always)] #[must_use] - pub fn lock_region_30(&mut self) -> LOCK_REGION_30_W<30> { + pub fn lock_region_30(&mut self) -> LOCK_REGION_30_W { LOCK_REGION_30_W::new(self) } #[doc = "Bit 31 - Lock Region 31"] #[inline(always)] #[must_use] - pub fn lock_region_31(&mut self) -> LOCK_REGION_31_W<31> { + pub fn lock_region_31(&mut self) -> LOCK_REGION_31_W { LOCK_REGION_31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lock Bits Word 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [word0](index.html) module"] +#[doc = "Lock Bits Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WORD0_SPEC; impl crate::RegisterSpec for WORD0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [word0::R](R) reader structure"] -impl crate::Readable for WORD0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [word0::W](W) writer structure"] +#[doc = "`read()` method returns [`word0::R`](R) reader structure"] +impl crate::Readable for WORD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`word0::W`](W) writer structure"] impl crate::Writable for WORD0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/lockbit/word1.rs b/arch/cortex-m/samv71q21-pac/src/lockbit/word1.rs index f4ac9ce8..93028d30 100644 --- a/arch/cortex-m/samv71q21-pac/src/lockbit/word1.rs +++ b/arch/cortex-m/samv71q21-pac/src/lockbit/word1.rs @@ -1,167 +1,135 @@ #[doc = "Register `WORD1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WORD1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOCK_REGION_32` reader - Lock Region 32"] pub type LOCK_REGION_32_R = crate::BitReader; #[doc = "Field `LOCK_REGION_32` writer - Lock Region 32"] -pub type LOCK_REGION_32_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_33` reader - Lock Region 33"] pub type LOCK_REGION_33_R = crate::BitReader; #[doc = "Field `LOCK_REGION_33` writer - Lock Region 33"] -pub type LOCK_REGION_33_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_34` reader - Lock Region 34"] pub type LOCK_REGION_34_R = crate::BitReader; #[doc = "Field `LOCK_REGION_34` writer - Lock Region 34"] -pub type LOCK_REGION_34_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_35` reader - Lock Region 35"] pub type LOCK_REGION_35_R = crate::BitReader; #[doc = "Field `LOCK_REGION_35` writer - Lock Region 35"] -pub type LOCK_REGION_35_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_36` reader - Lock Region 36"] pub type LOCK_REGION_36_R = crate::BitReader; #[doc = "Field `LOCK_REGION_36` writer - Lock Region 36"] -pub type LOCK_REGION_36_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_37` reader - Lock Region 37"] pub type LOCK_REGION_37_R = crate::BitReader; #[doc = "Field `LOCK_REGION_37` writer - Lock Region 37"] -pub type LOCK_REGION_37_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_38` reader - Lock Region 38"] pub type LOCK_REGION_38_R = crate::BitReader; #[doc = "Field `LOCK_REGION_38` writer - Lock Region 38"] -pub type LOCK_REGION_38_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_39` reader - Lock Region 39"] pub type LOCK_REGION_39_R = crate::BitReader; #[doc = "Field `LOCK_REGION_39` writer - Lock Region 39"] -pub type LOCK_REGION_39_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_40` reader - Lock Region 40"] pub type LOCK_REGION_40_R = crate::BitReader; #[doc = "Field `LOCK_REGION_40` writer - Lock Region 40"] -pub type LOCK_REGION_40_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_41` reader - Lock Region 41"] pub type LOCK_REGION_41_R = crate::BitReader; #[doc = "Field `LOCK_REGION_41` writer - Lock Region 41"] -pub type LOCK_REGION_41_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_42` reader - Lock Region 42"] pub type LOCK_REGION_42_R = crate::BitReader; #[doc = "Field `LOCK_REGION_42` writer - Lock Region 42"] -pub type LOCK_REGION_42_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_43` reader - Lock Region 43"] pub type LOCK_REGION_43_R = crate::BitReader; #[doc = "Field `LOCK_REGION_43` writer - Lock Region 43"] -pub type LOCK_REGION_43_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_44` reader - Lock Region 44"] pub type LOCK_REGION_44_R = crate::BitReader; #[doc = "Field `LOCK_REGION_44` writer - Lock Region 44"] -pub type LOCK_REGION_44_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_45` reader - Lock Region 45"] pub type LOCK_REGION_45_R = crate::BitReader; #[doc = "Field `LOCK_REGION_45` writer - Lock Region 45"] -pub type LOCK_REGION_45_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_46` reader - Lock Region 46"] pub type LOCK_REGION_46_R = crate::BitReader; #[doc = "Field `LOCK_REGION_46` writer - Lock Region 46"] -pub type LOCK_REGION_46_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_47` reader - Lock Region 47"] pub type LOCK_REGION_47_R = crate::BitReader; #[doc = "Field `LOCK_REGION_47` writer - Lock Region 47"] -pub type LOCK_REGION_47_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_48` reader - Lock Region 48"] pub type LOCK_REGION_48_R = crate::BitReader; #[doc = "Field `LOCK_REGION_48` writer - Lock Region 48"] -pub type LOCK_REGION_48_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_49` reader - Lock Region 49"] pub type LOCK_REGION_49_R = crate::BitReader; #[doc = "Field `LOCK_REGION_49` writer - Lock Region 49"] -pub type LOCK_REGION_49_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_50` reader - Lock Region 50"] pub type LOCK_REGION_50_R = crate::BitReader; #[doc = "Field `LOCK_REGION_50` writer - Lock Region 50"] -pub type LOCK_REGION_50_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_51` reader - Lock Region 51"] pub type LOCK_REGION_51_R = crate::BitReader; #[doc = "Field `LOCK_REGION_51` writer - Lock Region 51"] -pub type LOCK_REGION_51_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_52` reader - Lock Region 52"] pub type LOCK_REGION_52_R = crate::BitReader; #[doc = "Field `LOCK_REGION_52` writer - Lock Region 52"] -pub type LOCK_REGION_52_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_53` reader - Lock Region 53"] pub type LOCK_REGION_53_R = crate::BitReader; #[doc = "Field `LOCK_REGION_53` writer - Lock Region 53"] -pub type LOCK_REGION_53_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_54` reader - Lock Region 54"] pub type LOCK_REGION_54_R = crate::BitReader; #[doc = "Field `LOCK_REGION_54` writer - Lock Region 54"] -pub type LOCK_REGION_54_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_55` reader - Lock Region 55"] pub type LOCK_REGION_55_R = crate::BitReader; #[doc = "Field `LOCK_REGION_55` writer - Lock Region 55"] -pub type LOCK_REGION_55_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_56` reader - Lock Region 56"] pub type LOCK_REGION_56_R = crate::BitReader; #[doc = "Field `LOCK_REGION_56` writer - Lock Region 56"] -pub type LOCK_REGION_56_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_57` reader - Lock Region 57"] pub type LOCK_REGION_57_R = crate::BitReader; #[doc = "Field `LOCK_REGION_57` writer - Lock Region 57"] -pub type LOCK_REGION_57_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_58` reader - Lock Region 58"] pub type LOCK_REGION_58_R = crate::BitReader; #[doc = "Field `LOCK_REGION_58` writer - Lock Region 58"] -pub type LOCK_REGION_58_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_59` reader - Lock Region 59"] pub type LOCK_REGION_59_R = crate::BitReader; #[doc = "Field `LOCK_REGION_59` writer - Lock Region 59"] -pub type LOCK_REGION_59_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_60` reader - Lock Region 60"] pub type LOCK_REGION_60_R = crate::BitReader; #[doc = "Field `LOCK_REGION_60` writer - Lock Region 60"] -pub type LOCK_REGION_60_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_61` reader - Lock Region 61"] pub type LOCK_REGION_61_R = crate::BitReader; #[doc = "Field `LOCK_REGION_61` writer - Lock Region 61"] -pub type LOCK_REGION_61_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_61_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_62` reader - Lock Region 62"] pub type LOCK_REGION_62_R = crate::BitReader; #[doc = "Field `LOCK_REGION_62` writer - Lock Region 62"] -pub type LOCK_REGION_62_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_62_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_63` reader - Lock Region 63"] pub type LOCK_REGION_63_R = crate::BitReader; #[doc = "Field `LOCK_REGION_63` writer - Lock Region 63"] -pub type LOCK_REGION_63_W<'a, const O: u8> = crate::BitWriter<'a, WORD1_SPEC, O>; +pub type LOCK_REGION_63_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Lock Region 32"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Lock Region 32"] #[inline(always)] #[must_use] - pub fn lock_region_32(&mut self) -> LOCK_REGION_32_W<0> { + pub fn lock_region_32(&mut self) -> LOCK_REGION_32_W { LOCK_REGION_32_W::new(self) } #[doc = "Bit 1 - Lock Region 33"] #[inline(always)] #[must_use] - pub fn lock_region_33(&mut self) -> LOCK_REGION_33_W<1> { + pub fn lock_region_33(&mut self) -> LOCK_REGION_33_W { LOCK_REGION_33_W::new(self) } #[doc = "Bit 2 - Lock Region 34"] #[inline(always)] #[must_use] - pub fn lock_region_34(&mut self) -> LOCK_REGION_34_W<2> { + pub fn lock_region_34(&mut self) -> LOCK_REGION_34_W { LOCK_REGION_34_W::new(self) } #[doc = "Bit 3 - Lock Region 35"] #[inline(always)] #[must_use] - pub fn lock_region_35(&mut self) -> LOCK_REGION_35_W<3> { + pub fn lock_region_35(&mut self) -> LOCK_REGION_35_W { LOCK_REGION_35_W::new(self) } #[doc = "Bit 4 - Lock Region 36"] #[inline(always)] #[must_use] - pub fn lock_region_36(&mut self) -> LOCK_REGION_36_W<4> { + pub fn lock_region_36(&mut self) -> LOCK_REGION_36_W { LOCK_REGION_36_W::new(self) } #[doc = "Bit 5 - Lock Region 37"] #[inline(always)] #[must_use] - pub fn lock_region_37(&mut self) -> LOCK_REGION_37_W<5> { + pub fn lock_region_37(&mut self) -> LOCK_REGION_37_W { LOCK_REGION_37_W::new(self) } #[doc = "Bit 6 - Lock Region 38"] #[inline(always)] #[must_use] - pub fn lock_region_38(&mut self) -> LOCK_REGION_38_W<6> { + pub fn lock_region_38(&mut self) -> LOCK_REGION_38_W { LOCK_REGION_38_W::new(self) } #[doc = "Bit 7 - Lock Region 39"] #[inline(always)] #[must_use] - pub fn lock_region_39(&mut self) -> LOCK_REGION_39_W<7> { + pub fn lock_region_39(&mut self) -> LOCK_REGION_39_W { LOCK_REGION_39_W::new(self) } #[doc = "Bit 8 - Lock Region 40"] #[inline(always)] #[must_use] - pub fn lock_region_40(&mut self) -> LOCK_REGION_40_W<8> { + pub fn lock_region_40(&mut self) -> LOCK_REGION_40_W { LOCK_REGION_40_W::new(self) } #[doc = "Bit 9 - Lock Region 41"] #[inline(always)] #[must_use] - pub fn lock_region_41(&mut self) -> LOCK_REGION_41_W<9> { + pub fn lock_region_41(&mut self) -> LOCK_REGION_41_W { LOCK_REGION_41_W::new(self) } #[doc = "Bit 10 - Lock Region 42"] #[inline(always)] #[must_use] - pub fn lock_region_42(&mut self) -> LOCK_REGION_42_W<10> { + pub fn lock_region_42(&mut self) -> LOCK_REGION_42_W { LOCK_REGION_42_W::new(self) } #[doc = "Bit 11 - Lock Region 43"] #[inline(always)] #[must_use] - pub fn lock_region_43(&mut self) -> LOCK_REGION_43_W<11> { + pub fn lock_region_43(&mut self) -> LOCK_REGION_43_W { LOCK_REGION_43_W::new(self) } #[doc = "Bit 12 - Lock Region 44"] #[inline(always)] #[must_use] - pub fn lock_region_44(&mut self) -> LOCK_REGION_44_W<12> { + pub fn lock_region_44(&mut self) -> LOCK_REGION_44_W { LOCK_REGION_44_W::new(self) } #[doc = "Bit 13 - Lock Region 45"] #[inline(always)] #[must_use] - pub fn lock_region_45(&mut self) -> LOCK_REGION_45_W<13> { + pub fn lock_region_45(&mut self) -> LOCK_REGION_45_W { LOCK_REGION_45_W::new(self) } #[doc = "Bit 14 - Lock Region 46"] #[inline(always)] #[must_use] - pub fn lock_region_46(&mut self) -> LOCK_REGION_46_W<14> { + pub fn lock_region_46(&mut self) -> LOCK_REGION_46_W { LOCK_REGION_46_W::new(self) } #[doc = "Bit 15 - Lock Region 47"] #[inline(always)] #[must_use] - pub fn lock_region_47(&mut self) -> LOCK_REGION_47_W<15> { + pub fn lock_region_47(&mut self) -> LOCK_REGION_47_W { LOCK_REGION_47_W::new(self) } #[doc = "Bit 16 - Lock Region 48"] #[inline(always)] #[must_use] - pub fn lock_region_48(&mut self) -> LOCK_REGION_48_W<16> { + pub fn lock_region_48(&mut self) -> LOCK_REGION_48_W { LOCK_REGION_48_W::new(self) } #[doc = "Bit 17 - Lock Region 49"] #[inline(always)] #[must_use] - pub fn lock_region_49(&mut self) -> LOCK_REGION_49_W<17> { + pub fn lock_region_49(&mut self) -> LOCK_REGION_49_W { LOCK_REGION_49_W::new(self) } #[doc = "Bit 18 - Lock Region 50"] #[inline(always)] #[must_use] - pub fn lock_region_50(&mut self) -> LOCK_REGION_50_W<18> { + pub fn lock_region_50(&mut self) -> LOCK_REGION_50_W { LOCK_REGION_50_W::new(self) } #[doc = "Bit 19 - Lock Region 51"] #[inline(always)] #[must_use] - pub fn lock_region_51(&mut self) -> LOCK_REGION_51_W<19> { + pub fn lock_region_51(&mut self) -> LOCK_REGION_51_W { LOCK_REGION_51_W::new(self) } #[doc = "Bit 20 - Lock Region 52"] #[inline(always)] #[must_use] - pub fn lock_region_52(&mut self) -> LOCK_REGION_52_W<20> { + pub fn lock_region_52(&mut self) -> LOCK_REGION_52_W { LOCK_REGION_52_W::new(self) } #[doc = "Bit 21 - Lock Region 53"] #[inline(always)] #[must_use] - pub fn lock_region_53(&mut self) -> LOCK_REGION_53_W<21> { + pub fn lock_region_53(&mut self) -> LOCK_REGION_53_W { LOCK_REGION_53_W::new(self) } #[doc = "Bit 22 - Lock Region 54"] #[inline(always)] #[must_use] - pub fn lock_region_54(&mut self) -> LOCK_REGION_54_W<22> { + pub fn lock_region_54(&mut self) -> LOCK_REGION_54_W { LOCK_REGION_54_W::new(self) } #[doc = "Bit 23 - Lock Region 55"] #[inline(always)] #[must_use] - pub fn lock_region_55(&mut self) -> LOCK_REGION_55_W<23> { + pub fn lock_region_55(&mut self) -> LOCK_REGION_55_W { LOCK_REGION_55_W::new(self) } #[doc = "Bit 24 - Lock Region 56"] #[inline(always)] #[must_use] - pub fn lock_region_56(&mut self) -> LOCK_REGION_56_W<24> { + pub fn lock_region_56(&mut self) -> LOCK_REGION_56_W { LOCK_REGION_56_W::new(self) } #[doc = "Bit 25 - Lock Region 57"] #[inline(always)] #[must_use] - pub fn lock_region_57(&mut self) -> LOCK_REGION_57_W<25> { + pub fn lock_region_57(&mut self) -> LOCK_REGION_57_W { LOCK_REGION_57_W::new(self) } #[doc = "Bit 26 - Lock Region 58"] #[inline(always)] #[must_use] - pub fn lock_region_58(&mut self) -> LOCK_REGION_58_W<26> { + pub fn lock_region_58(&mut self) -> LOCK_REGION_58_W { LOCK_REGION_58_W::new(self) } #[doc = "Bit 27 - Lock Region 59"] #[inline(always)] #[must_use] - pub fn lock_region_59(&mut self) -> LOCK_REGION_59_W<27> { + pub fn lock_region_59(&mut self) -> LOCK_REGION_59_W { LOCK_REGION_59_W::new(self) } #[doc = "Bit 28 - Lock Region 60"] #[inline(always)] #[must_use] - pub fn lock_region_60(&mut self) -> LOCK_REGION_60_W<28> { + pub fn lock_region_60(&mut self) -> LOCK_REGION_60_W { LOCK_REGION_60_W::new(self) } #[doc = "Bit 29 - Lock Region 61"] #[inline(always)] #[must_use] - pub fn lock_region_61(&mut self) -> LOCK_REGION_61_W<29> { + pub fn lock_region_61(&mut self) -> LOCK_REGION_61_W { LOCK_REGION_61_W::new(self) } #[doc = "Bit 30 - Lock Region 62"] #[inline(always)] #[must_use] - pub fn lock_region_62(&mut self) -> LOCK_REGION_62_W<30> { + pub fn lock_region_62(&mut self) -> LOCK_REGION_62_W { LOCK_REGION_62_W::new(self) } #[doc = "Bit 31 - Lock Region 63"] #[inline(always)] #[must_use] - pub fn lock_region_63(&mut self) -> LOCK_REGION_63_W<31> { + pub fn lock_region_63(&mut self) -> LOCK_REGION_63_W { LOCK_REGION_63_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lock Bits Word 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [word1](index.html) module"] +#[doc = "Lock Bits Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WORD1_SPEC; impl crate::RegisterSpec for WORD1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [word1::R](R) reader structure"] -impl crate::Readable for WORD1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [word1::W](W) writer structure"] +#[doc = "`read()` method returns [`word1::R`](R) reader structure"] +impl crate::Readable for WORD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`word1::W`](W) writer structure"] impl crate::Writable for WORD1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/lockbit/word2.rs b/arch/cortex-m/samv71q21-pac/src/lockbit/word2.rs index abaf3412..84c30cd6 100644 --- a/arch/cortex-m/samv71q21-pac/src/lockbit/word2.rs +++ b/arch/cortex-m/samv71q21-pac/src/lockbit/word2.rs @@ -1,167 +1,135 @@ #[doc = "Register `WORD2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WORD2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOCK_REGION_64` reader - Lock Region 64"] pub type LOCK_REGION_64_R = crate::BitReader; #[doc = "Field `LOCK_REGION_64` writer - Lock Region 64"] -pub type LOCK_REGION_64_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_64_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_65` reader - Lock Region 65"] pub type LOCK_REGION_65_R = crate::BitReader; #[doc = "Field `LOCK_REGION_65` writer - Lock Region 65"] -pub type LOCK_REGION_65_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_65_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_66` reader - Lock Region 66"] pub type LOCK_REGION_66_R = crate::BitReader; #[doc = "Field `LOCK_REGION_66` writer - Lock Region 66"] -pub type LOCK_REGION_66_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_66_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_67` reader - Lock Region 67"] pub type LOCK_REGION_67_R = crate::BitReader; #[doc = "Field `LOCK_REGION_67` writer - Lock Region 67"] -pub type LOCK_REGION_67_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_67_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_68` reader - Lock Region 68"] pub type LOCK_REGION_68_R = crate::BitReader; #[doc = "Field `LOCK_REGION_68` writer - Lock Region 68"] -pub type LOCK_REGION_68_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_68_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_69` reader - Lock Region 69"] pub type LOCK_REGION_69_R = crate::BitReader; #[doc = "Field `LOCK_REGION_69` writer - Lock Region 69"] -pub type LOCK_REGION_69_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_69_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_70` reader - Lock Region 70"] pub type LOCK_REGION_70_R = crate::BitReader; #[doc = "Field `LOCK_REGION_70` writer - Lock Region 70"] -pub type LOCK_REGION_70_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_70_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_71` reader - Lock Region 71"] pub type LOCK_REGION_71_R = crate::BitReader; #[doc = "Field `LOCK_REGION_71` writer - Lock Region 71"] -pub type LOCK_REGION_71_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_71_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_72` reader - Lock Region 72"] pub type LOCK_REGION_72_R = crate::BitReader; #[doc = "Field `LOCK_REGION_72` writer - Lock Region 72"] -pub type LOCK_REGION_72_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_72_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_73` reader - Lock Region 73"] pub type LOCK_REGION_73_R = crate::BitReader; #[doc = "Field `LOCK_REGION_73` writer - Lock Region 73"] -pub type LOCK_REGION_73_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_73_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_74` reader - Lock Region 74"] pub type LOCK_REGION_74_R = crate::BitReader; #[doc = "Field `LOCK_REGION_74` writer - Lock Region 74"] -pub type LOCK_REGION_74_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_74_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_75` reader - Lock Region 75"] pub type LOCK_REGION_75_R = crate::BitReader; #[doc = "Field `LOCK_REGION_75` writer - Lock Region 75"] -pub type LOCK_REGION_75_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_75_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_76` reader - Lock Region 76"] pub type LOCK_REGION_76_R = crate::BitReader; #[doc = "Field `LOCK_REGION_76` writer - Lock Region 76"] -pub type LOCK_REGION_76_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_76_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_77` reader - Lock Region 77"] pub type LOCK_REGION_77_R = crate::BitReader; #[doc = "Field `LOCK_REGION_77` writer - Lock Region 77"] -pub type LOCK_REGION_77_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_77_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_78` reader - Lock Region 78"] pub type LOCK_REGION_78_R = crate::BitReader; #[doc = "Field `LOCK_REGION_78` writer - Lock Region 78"] -pub type LOCK_REGION_78_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_78_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_79` reader - Lock Region 79"] pub type LOCK_REGION_79_R = crate::BitReader; #[doc = "Field `LOCK_REGION_79` writer - Lock Region 79"] -pub type LOCK_REGION_79_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_79_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_80` reader - Lock Region 80"] pub type LOCK_REGION_80_R = crate::BitReader; #[doc = "Field `LOCK_REGION_80` writer - Lock Region 80"] -pub type LOCK_REGION_80_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_80_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_81` reader - Lock Region 81"] pub type LOCK_REGION_81_R = crate::BitReader; #[doc = "Field `LOCK_REGION_81` writer - Lock Region 81"] -pub type LOCK_REGION_81_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_81_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_82` reader - Lock Region 82"] pub type LOCK_REGION_82_R = crate::BitReader; #[doc = "Field `LOCK_REGION_82` writer - Lock Region 82"] -pub type LOCK_REGION_82_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_82_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_83` reader - Lock Region 83"] pub type LOCK_REGION_83_R = crate::BitReader; #[doc = "Field `LOCK_REGION_83` writer - Lock Region 83"] -pub type LOCK_REGION_83_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_83_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_84` reader - Lock Region 84"] pub type LOCK_REGION_84_R = crate::BitReader; #[doc = "Field `LOCK_REGION_84` writer - Lock Region 84"] -pub type LOCK_REGION_84_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_84_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_85` reader - Lock Region 85"] pub type LOCK_REGION_85_R = crate::BitReader; #[doc = "Field `LOCK_REGION_85` writer - Lock Region 85"] -pub type LOCK_REGION_85_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_85_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_86` reader - Lock Region 86"] pub type LOCK_REGION_86_R = crate::BitReader; #[doc = "Field `LOCK_REGION_86` writer - Lock Region 86"] -pub type LOCK_REGION_86_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_86_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_87` reader - Lock Region 87"] pub type LOCK_REGION_87_R = crate::BitReader; #[doc = "Field `LOCK_REGION_87` writer - Lock Region 87"] -pub type LOCK_REGION_87_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_87_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_88` reader - Lock Region 88"] pub type LOCK_REGION_88_R = crate::BitReader; #[doc = "Field `LOCK_REGION_88` writer - Lock Region 88"] -pub type LOCK_REGION_88_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_88_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_89` reader - Lock Region 89"] pub type LOCK_REGION_89_R = crate::BitReader; #[doc = "Field `LOCK_REGION_89` writer - Lock Region 89"] -pub type LOCK_REGION_89_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_89_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_90` reader - Lock Region 90"] pub type LOCK_REGION_90_R = crate::BitReader; #[doc = "Field `LOCK_REGION_90` writer - Lock Region 90"] -pub type LOCK_REGION_90_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_90_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_91` reader - Lock Region 91"] pub type LOCK_REGION_91_R = crate::BitReader; #[doc = "Field `LOCK_REGION_91` writer - Lock Region 91"] -pub type LOCK_REGION_91_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_91_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_92` reader - Lock Region 92"] pub type LOCK_REGION_92_R = crate::BitReader; #[doc = "Field `LOCK_REGION_92` writer - Lock Region 92"] -pub type LOCK_REGION_92_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_92_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_93` reader - Lock Region 93"] pub type LOCK_REGION_93_R = crate::BitReader; #[doc = "Field `LOCK_REGION_93` writer - Lock Region 93"] -pub type LOCK_REGION_93_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_93_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_94` reader - Lock Region 94"] pub type LOCK_REGION_94_R = crate::BitReader; #[doc = "Field `LOCK_REGION_94` writer - Lock Region 94"] -pub type LOCK_REGION_94_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_94_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_95` reader - Lock Region 95"] pub type LOCK_REGION_95_R = crate::BitReader; #[doc = "Field `LOCK_REGION_95` writer - Lock Region 95"] -pub type LOCK_REGION_95_W<'a, const O: u8> = crate::BitWriter<'a, WORD2_SPEC, O>; +pub type LOCK_REGION_95_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Lock Region 64"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Lock Region 64"] #[inline(always)] #[must_use] - pub fn lock_region_64(&mut self) -> LOCK_REGION_64_W<0> { + pub fn lock_region_64(&mut self) -> LOCK_REGION_64_W { LOCK_REGION_64_W::new(self) } #[doc = "Bit 1 - Lock Region 65"] #[inline(always)] #[must_use] - pub fn lock_region_65(&mut self) -> LOCK_REGION_65_W<1> { + pub fn lock_region_65(&mut self) -> LOCK_REGION_65_W { LOCK_REGION_65_W::new(self) } #[doc = "Bit 2 - Lock Region 66"] #[inline(always)] #[must_use] - pub fn lock_region_66(&mut self) -> LOCK_REGION_66_W<2> { + pub fn lock_region_66(&mut self) -> LOCK_REGION_66_W { LOCK_REGION_66_W::new(self) } #[doc = "Bit 3 - Lock Region 67"] #[inline(always)] #[must_use] - pub fn lock_region_67(&mut self) -> LOCK_REGION_67_W<3> { + pub fn lock_region_67(&mut self) -> LOCK_REGION_67_W { LOCK_REGION_67_W::new(self) } #[doc = "Bit 4 - Lock Region 68"] #[inline(always)] #[must_use] - pub fn lock_region_68(&mut self) -> LOCK_REGION_68_W<4> { + pub fn lock_region_68(&mut self) -> LOCK_REGION_68_W { LOCK_REGION_68_W::new(self) } #[doc = "Bit 5 - Lock Region 69"] #[inline(always)] #[must_use] - pub fn lock_region_69(&mut self) -> LOCK_REGION_69_W<5> { + pub fn lock_region_69(&mut self) -> LOCK_REGION_69_W { LOCK_REGION_69_W::new(self) } #[doc = "Bit 6 - Lock Region 70"] #[inline(always)] #[must_use] - pub fn lock_region_70(&mut self) -> LOCK_REGION_70_W<6> { + pub fn lock_region_70(&mut self) -> LOCK_REGION_70_W { LOCK_REGION_70_W::new(self) } #[doc = "Bit 7 - Lock Region 71"] #[inline(always)] #[must_use] - pub fn lock_region_71(&mut self) -> LOCK_REGION_71_W<7> { + pub fn lock_region_71(&mut self) -> LOCK_REGION_71_W { LOCK_REGION_71_W::new(self) } #[doc = "Bit 8 - Lock Region 72"] #[inline(always)] #[must_use] - pub fn lock_region_72(&mut self) -> LOCK_REGION_72_W<8> { + pub fn lock_region_72(&mut self) -> LOCK_REGION_72_W { LOCK_REGION_72_W::new(self) } #[doc = "Bit 9 - Lock Region 73"] #[inline(always)] #[must_use] - pub fn lock_region_73(&mut self) -> LOCK_REGION_73_W<9> { + pub fn lock_region_73(&mut self) -> LOCK_REGION_73_W { LOCK_REGION_73_W::new(self) } #[doc = "Bit 10 - Lock Region 74"] #[inline(always)] #[must_use] - pub fn lock_region_74(&mut self) -> LOCK_REGION_74_W<10> { + pub fn lock_region_74(&mut self) -> LOCK_REGION_74_W { LOCK_REGION_74_W::new(self) } #[doc = "Bit 11 - Lock Region 75"] #[inline(always)] #[must_use] - pub fn lock_region_75(&mut self) -> LOCK_REGION_75_W<11> { + pub fn lock_region_75(&mut self) -> LOCK_REGION_75_W { LOCK_REGION_75_W::new(self) } #[doc = "Bit 12 - Lock Region 76"] #[inline(always)] #[must_use] - pub fn lock_region_76(&mut self) -> LOCK_REGION_76_W<12> { + pub fn lock_region_76(&mut self) -> LOCK_REGION_76_W { LOCK_REGION_76_W::new(self) } #[doc = "Bit 13 - Lock Region 77"] #[inline(always)] #[must_use] - pub fn lock_region_77(&mut self) -> LOCK_REGION_77_W<13> { + pub fn lock_region_77(&mut self) -> LOCK_REGION_77_W { LOCK_REGION_77_W::new(self) } #[doc = "Bit 14 - Lock Region 78"] #[inline(always)] #[must_use] - pub fn lock_region_78(&mut self) -> LOCK_REGION_78_W<14> { + pub fn lock_region_78(&mut self) -> LOCK_REGION_78_W { LOCK_REGION_78_W::new(self) } #[doc = "Bit 15 - Lock Region 79"] #[inline(always)] #[must_use] - pub fn lock_region_79(&mut self) -> LOCK_REGION_79_W<15> { + pub fn lock_region_79(&mut self) -> LOCK_REGION_79_W { LOCK_REGION_79_W::new(self) } #[doc = "Bit 16 - Lock Region 80"] #[inline(always)] #[must_use] - pub fn lock_region_80(&mut self) -> LOCK_REGION_80_W<16> { + pub fn lock_region_80(&mut self) -> LOCK_REGION_80_W { LOCK_REGION_80_W::new(self) } #[doc = "Bit 17 - Lock Region 81"] #[inline(always)] #[must_use] - pub fn lock_region_81(&mut self) -> LOCK_REGION_81_W<17> { + pub fn lock_region_81(&mut self) -> LOCK_REGION_81_W { LOCK_REGION_81_W::new(self) } #[doc = "Bit 18 - Lock Region 82"] #[inline(always)] #[must_use] - pub fn lock_region_82(&mut self) -> LOCK_REGION_82_W<18> { + pub fn lock_region_82(&mut self) -> LOCK_REGION_82_W { LOCK_REGION_82_W::new(self) } #[doc = "Bit 19 - Lock Region 83"] #[inline(always)] #[must_use] - pub fn lock_region_83(&mut self) -> LOCK_REGION_83_W<19> { + pub fn lock_region_83(&mut self) -> LOCK_REGION_83_W { LOCK_REGION_83_W::new(self) } #[doc = "Bit 20 - Lock Region 84"] #[inline(always)] #[must_use] - pub fn lock_region_84(&mut self) -> LOCK_REGION_84_W<20> { + pub fn lock_region_84(&mut self) -> LOCK_REGION_84_W { LOCK_REGION_84_W::new(self) } #[doc = "Bit 21 - Lock Region 85"] #[inline(always)] #[must_use] - pub fn lock_region_85(&mut self) -> LOCK_REGION_85_W<21> { + pub fn lock_region_85(&mut self) -> LOCK_REGION_85_W { LOCK_REGION_85_W::new(self) } #[doc = "Bit 22 - Lock Region 86"] #[inline(always)] #[must_use] - pub fn lock_region_86(&mut self) -> LOCK_REGION_86_W<22> { + pub fn lock_region_86(&mut self) -> LOCK_REGION_86_W { LOCK_REGION_86_W::new(self) } #[doc = "Bit 23 - Lock Region 87"] #[inline(always)] #[must_use] - pub fn lock_region_87(&mut self) -> LOCK_REGION_87_W<23> { + pub fn lock_region_87(&mut self) -> LOCK_REGION_87_W { LOCK_REGION_87_W::new(self) } #[doc = "Bit 24 - Lock Region 88"] #[inline(always)] #[must_use] - pub fn lock_region_88(&mut self) -> LOCK_REGION_88_W<24> { + pub fn lock_region_88(&mut self) -> LOCK_REGION_88_W { LOCK_REGION_88_W::new(self) } #[doc = "Bit 25 - Lock Region 89"] #[inline(always)] #[must_use] - pub fn lock_region_89(&mut self) -> LOCK_REGION_89_W<25> { + pub fn lock_region_89(&mut self) -> LOCK_REGION_89_W { LOCK_REGION_89_W::new(self) } #[doc = "Bit 26 - Lock Region 90"] #[inline(always)] #[must_use] - pub fn lock_region_90(&mut self) -> LOCK_REGION_90_W<26> { + pub fn lock_region_90(&mut self) -> LOCK_REGION_90_W { LOCK_REGION_90_W::new(self) } #[doc = "Bit 27 - Lock Region 91"] #[inline(always)] #[must_use] - pub fn lock_region_91(&mut self) -> LOCK_REGION_91_W<27> { + pub fn lock_region_91(&mut self) -> LOCK_REGION_91_W { LOCK_REGION_91_W::new(self) } #[doc = "Bit 28 - Lock Region 92"] #[inline(always)] #[must_use] - pub fn lock_region_92(&mut self) -> LOCK_REGION_92_W<28> { + pub fn lock_region_92(&mut self) -> LOCK_REGION_92_W { LOCK_REGION_92_W::new(self) } #[doc = "Bit 29 - Lock Region 93"] #[inline(always)] #[must_use] - pub fn lock_region_93(&mut self) -> LOCK_REGION_93_W<29> { + pub fn lock_region_93(&mut self) -> LOCK_REGION_93_W { LOCK_REGION_93_W::new(self) } #[doc = "Bit 30 - Lock Region 94"] #[inline(always)] #[must_use] - pub fn lock_region_94(&mut self) -> LOCK_REGION_94_W<30> { + pub fn lock_region_94(&mut self) -> LOCK_REGION_94_W { LOCK_REGION_94_W::new(self) } #[doc = "Bit 31 - Lock Region 95"] #[inline(always)] #[must_use] - pub fn lock_region_95(&mut self) -> LOCK_REGION_95_W<31> { + pub fn lock_region_95(&mut self) -> LOCK_REGION_95_W { LOCK_REGION_95_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lock Bits Word 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [word2](index.html) module"] +#[doc = "Lock Bits Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WORD2_SPEC; impl crate::RegisterSpec for WORD2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [word2::R](R) reader structure"] -impl crate::Readable for WORD2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [word2::W](W) writer structure"] +#[doc = "`read()` method returns [`word2::R`](R) reader structure"] +impl crate::Readable for WORD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`word2::W`](W) writer structure"] impl crate::Writable for WORD2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/lockbit/word3.rs b/arch/cortex-m/samv71q21-pac/src/lockbit/word3.rs index 16ec4d25..a134fb61 100644 --- a/arch/cortex-m/samv71q21-pac/src/lockbit/word3.rs +++ b/arch/cortex-m/samv71q21-pac/src/lockbit/word3.rs @@ -1,167 +1,135 @@ #[doc = "Register `WORD3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WORD3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOCK_REGION_96` reader - Lock Region 96"] pub type LOCK_REGION_96_R = crate::BitReader; #[doc = "Field `LOCK_REGION_96` writer - Lock Region 96"] -pub type LOCK_REGION_96_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_96_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_97` reader - Lock Region 97"] pub type LOCK_REGION_97_R = crate::BitReader; #[doc = "Field `LOCK_REGION_97` writer - Lock Region 97"] -pub type LOCK_REGION_97_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_97_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_98` reader - Lock Region 98"] pub type LOCK_REGION_98_R = crate::BitReader; #[doc = "Field `LOCK_REGION_98` writer - Lock Region 98"] -pub type LOCK_REGION_98_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_98_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_99` reader - Lock Region 99"] pub type LOCK_REGION_99_R = crate::BitReader; #[doc = "Field `LOCK_REGION_99` writer - Lock Region 99"] -pub type LOCK_REGION_99_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_99_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_100` reader - Lock Region 100"] pub type LOCK_REGION_100_R = crate::BitReader; #[doc = "Field `LOCK_REGION_100` writer - Lock Region 100"] -pub type LOCK_REGION_100_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_100_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_101` reader - Lock Region 101"] pub type LOCK_REGION_101_R = crate::BitReader; #[doc = "Field `LOCK_REGION_101` writer - Lock Region 101"] -pub type LOCK_REGION_101_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_101_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_102` reader - Lock Region 102"] pub type LOCK_REGION_102_R = crate::BitReader; #[doc = "Field `LOCK_REGION_102` writer - Lock Region 102"] -pub type LOCK_REGION_102_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_102_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_103` reader - Lock Region 103"] pub type LOCK_REGION_103_R = crate::BitReader; #[doc = "Field `LOCK_REGION_103` writer - Lock Region 103"] -pub type LOCK_REGION_103_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_103_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_104` reader - Lock Region 104"] pub type LOCK_REGION_104_R = crate::BitReader; #[doc = "Field `LOCK_REGION_104` writer - Lock Region 104"] -pub type LOCK_REGION_104_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_104_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_105` reader - Lock Region 105"] pub type LOCK_REGION_105_R = crate::BitReader; #[doc = "Field `LOCK_REGION_105` writer - Lock Region 105"] -pub type LOCK_REGION_105_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_105_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_106` reader - Lock Region 106"] pub type LOCK_REGION_106_R = crate::BitReader; #[doc = "Field `LOCK_REGION_106` writer - Lock Region 106"] -pub type LOCK_REGION_106_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_106_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_107` reader - Lock Region 107"] pub type LOCK_REGION_107_R = crate::BitReader; #[doc = "Field `LOCK_REGION_107` writer - Lock Region 107"] -pub type LOCK_REGION_107_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_107_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_108` reader - Lock Region 108"] pub type LOCK_REGION_108_R = crate::BitReader; #[doc = "Field `LOCK_REGION_108` writer - Lock Region 108"] -pub type LOCK_REGION_108_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_108_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_109` reader - Lock Region 109"] pub type LOCK_REGION_109_R = crate::BitReader; #[doc = "Field `LOCK_REGION_109` writer - Lock Region 109"] -pub type LOCK_REGION_109_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_109_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_110` reader - Lock Region 110"] pub type LOCK_REGION_110_R = crate::BitReader; #[doc = "Field `LOCK_REGION_110` writer - Lock Region 110"] -pub type LOCK_REGION_110_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_110_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_111` reader - Lock Region 111"] pub type LOCK_REGION_111_R = crate::BitReader; #[doc = "Field `LOCK_REGION_111` writer - Lock Region 111"] -pub type LOCK_REGION_111_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_111_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_112` reader - Lock Region 112"] pub type LOCK_REGION_112_R = crate::BitReader; #[doc = "Field `LOCK_REGION_112` writer - Lock Region 112"] -pub type LOCK_REGION_112_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_112_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_113` reader - Lock Region 113"] pub type LOCK_REGION_113_R = crate::BitReader; #[doc = "Field `LOCK_REGION_113` writer - Lock Region 113"] -pub type LOCK_REGION_113_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_113_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_114` reader - Lock Region 114"] pub type LOCK_REGION_114_R = crate::BitReader; #[doc = "Field `LOCK_REGION_114` writer - Lock Region 114"] -pub type LOCK_REGION_114_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_114_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_115` reader - Lock Region 115"] pub type LOCK_REGION_115_R = crate::BitReader; #[doc = "Field `LOCK_REGION_115` writer - Lock Region 115"] -pub type LOCK_REGION_115_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_115_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_116` reader - Lock Region 116"] pub type LOCK_REGION_116_R = crate::BitReader; #[doc = "Field `LOCK_REGION_116` writer - Lock Region 116"] -pub type LOCK_REGION_116_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_116_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_117` reader - Lock Region 117"] pub type LOCK_REGION_117_R = crate::BitReader; #[doc = "Field `LOCK_REGION_117` writer - Lock Region 117"] -pub type LOCK_REGION_117_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_117_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_118` reader - Lock Region 118"] pub type LOCK_REGION_118_R = crate::BitReader; #[doc = "Field `LOCK_REGION_118` writer - Lock Region 118"] -pub type LOCK_REGION_118_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_118_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_119` reader - Lock Region 119"] pub type LOCK_REGION_119_R = crate::BitReader; #[doc = "Field `LOCK_REGION_119` writer - Lock Region 119"] -pub type LOCK_REGION_119_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_119_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_120` reader - Lock Region 120"] pub type LOCK_REGION_120_R = crate::BitReader; #[doc = "Field `LOCK_REGION_120` writer - Lock Region 120"] -pub type LOCK_REGION_120_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_120_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_121` reader - Lock Region 121"] pub type LOCK_REGION_121_R = crate::BitReader; #[doc = "Field `LOCK_REGION_121` writer - Lock Region 121"] -pub type LOCK_REGION_121_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_121_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_122` reader - Lock Region 122"] pub type LOCK_REGION_122_R = crate::BitReader; #[doc = "Field `LOCK_REGION_122` writer - Lock Region 122"] -pub type LOCK_REGION_122_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_122_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_123` reader - Lock Region 123"] pub type LOCK_REGION_123_R = crate::BitReader; #[doc = "Field `LOCK_REGION_123` writer - Lock Region 123"] -pub type LOCK_REGION_123_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_123_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_124` reader - Lock Region 124"] pub type LOCK_REGION_124_R = crate::BitReader; #[doc = "Field `LOCK_REGION_124` writer - Lock Region 124"] -pub type LOCK_REGION_124_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_124_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_125` reader - Lock Region 125"] pub type LOCK_REGION_125_R = crate::BitReader; #[doc = "Field `LOCK_REGION_125` writer - Lock Region 125"] -pub type LOCK_REGION_125_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_125_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_126` reader - Lock Region 126"] pub type LOCK_REGION_126_R = crate::BitReader; #[doc = "Field `LOCK_REGION_126` writer - Lock Region 126"] -pub type LOCK_REGION_126_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_126_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCK_REGION_127` reader - Lock Region 127"] pub type LOCK_REGION_127_R = crate::BitReader; #[doc = "Field `LOCK_REGION_127` writer - Lock Region 127"] -pub type LOCK_REGION_127_W<'a, const O: u8> = crate::BitWriter<'a, WORD3_SPEC, O>; +pub type LOCK_REGION_127_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Lock Region 96"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Lock Region 96"] #[inline(always)] #[must_use] - pub fn lock_region_96(&mut self) -> LOCK_REGION_96_W<0> { + pub fn lock_region_96(&mut self) -> LOCK_REGION_96_W { LOCK_REGION_96_W::new(self) } #[doc = "Bit 1 - Lock Region 97"] #[inline(always)] #[must_use] - pub fn lock_region_97(&mut self) -> LOCK_REGION_97_W<1> { + pub fn lock_region_97(&mut self) -> LOCK_REGION_97_W { LOCK_REGION_97_W::new(self) } #[doc = "Bit 2 - Lock Region 98"] #[inline(always)] #[must_use] - pub fn lock_region_98(&mut self) -> LOCK_REGION_98_W<2> { + pub fn lock_region_98(&mut self) -> LOCK_REGION_98_W { LOCK_REGION_98_W::new(self) } #[doc = "Bit 3 - Lock Region 99"] #[inline(always)] #[must_use] - pub fn lock_region_99(&mut self) -> LOCK_REGION_99_W<3> { + pub fn lock_region_99(&mut self) -> LOCK_REGION_99_W { LOCK_REGION_99_W::new(self) } #[doc = "Bit 4 - Lock Region 100"] #[inline(always)] #[must_use] - pub fn lock_region_100(&mut self) -> LOCK_REGION_100_W<4> { + pub fn lock_region_100(&mut self) -> LOCK_REGION_100_W { LOCK_REGION_100_W::new(self) } #[doc = "Bit 5 - Lock Region 101"] #[inline(always)] #[must_use] - pub fn lock_region_101(&mut self) -> LOCK_REGION_101_W<5> { + pub fn lock_region_101(&mut self) -> LOCK_REGION_101_W { LOCK_REGION_101_W::new(self) } #[doc = "Bit 6 - Lock Region 102"] #[inline(always)] #[must_use] - pub fn lock_region_102(&mut self) -> LOCK_REGION_102_W<6> { + pub fn lock_region_102(&mut self) -> LOCK_REGION_102_W { LOCK_REGION_102_W::new(self) } #[doc = "Bit 7 - Lock Region 103"] #[inline(always)] #[must_use] - pub fn lock_region_103(&mut self) -> LOCK_REGION_103_W<7> { + pub fn lock_region_103(&mut self) -> LOCK_REGION_103_W { LOCK_REGION_103_W::new(self) } #[doc = "Bit 8 - Lock Region 104"] #[inline(always)] #[must_use] - pub fn lock_region_104(&mut self) -> LOCK_REGION_104_W<8> { + pub fn lock_region_104(&mut self) -> LOCK_REGION_104_W { LOCK_REGION_104_W::new(self) } #[doc = "Bit 9 - Lock Region 105"] #[inline(always)] #[must_use] - pub fn lock_region_105(&mut self) -> LOCK_REGION_105_W<9> { + pub fn lock_region_105(&mut self) -> LOCK_REGION_105_W { LOCK_REGION_105_W::new(self) } #[doc = "Bit 10 - Lock Region 106"] #[inline(always)] #[must_use] - pub fn lock_region_106(&mut self) -> LOCK_REGION_106_W<10> { + pub fn lock_region_106(&mut self) -> LOCK_REGION_106_W { LOCK_REGION_106_W::new(self) } #[doc = "Bit 11 - Lock Region 107"] #[inline(always)] #[must_use] - pub fn lock_region_107(&mut self) -> LOCK_REGION_107_W<11> { + pub fn lock_region_107(&mut self) -> LOCK_REGION_107_W { LOCK_REGION_107_W::new(self) } #[doc = "Bit 12 - Lock Region 108"] #[inline(always)] #[must_use] - pub fn lock_region_108(&mut self) -> LOCK_REGION_108_W<12> { + pub fn lock_region_108(&mut self) -> LOCK_REGION_108_W { LOCK_REGION_108_W::new(self) } #[doc = "Bit 13 - Lock Region 109"] #[inline(always)] #[must_use] - pub fn lock_region_109(&mut self) -> LOCK_REGION_109_W<13> { + pub fn lock_region_109(&mut self) -> LOCK_REGION_109_W { LOCK_REGION_109_W::new(self) } #[doc = "Bit 14 - Lock Region 110"] #[inline(always)] #[must_use] - pub fn lock_region_110(&mut self) -> LOCK_REGION_110_W<14> { + pub fn lock_region_110(&mut self) -> LOCK_REGION_110_W { LOCK_REGION_110_W::new(self) } #[doc = "Bit 15 - Lock Region 111"] #[inline(always)] #[must_use] - pub fn lock_region_111(&mut self) -> LOCK_REGION_111_W<15> { + pub fn lock_region_111(&mut self) -> LOCK_REGION_111_W { LOCK_REGION_111_W::new(self) } #[doc = "Bit 16 - Lock Region 112"] #[inline(always)] #[must_use] - pub fn lock_region_112(&mut self) -> LOCK_REGION_112_W<16> { + pub fn lock_region_112(&mut self) -> LOCK_REGION_112_W { LOCK_REGION_112_W::new(self) } #[doc = "Bit 17 - Lock Region 113"] #[inline(always)] #[must_use] - pub fn lock_region_113(&mut self) -> LOCK_REGION_113_W<17> { + pub fn lock_region_113(&mut self) -> LOCK_REGION_113_W { LOCK_REGION_113_W::new(self) } #[doc = "Bit 18 - Lock Region 114"] #[inline(always)] #[must_use] - pub fn lock_region_114(&mut self) -> LOCK_REGION_114_W<18> { + pub fn lock_region_114(&mut self) -> LOCK_REGION_114_W { LOCK_REGION_114_W::new(self) } #[doc = "Bit 19 - Lock Region 115"] #[inline(always)] #[must_use] - pub fn lock_region_115(&mut self) -> LOCK_REGION_115_W<19> { + pub fn lock_region_115(&mut self) -> LOCK_REGION_115_W { LOCK_REGION_115_W::new(self) } #[doc = "Bit 20 - Lock Region 116"] #[inline(always)] #[must_use] - pub fn lock_region_116(&mut self) -> LOCK_REGION_116_W<20> { + pub fn lock_region_116(&mut self) -> LOCK_REGION_116_W { LOCK_REGION_116_W::new(self) } #[doc = "Bit 21 - Lock Region 117"] #[inline(always)] #[must_use] - pub fn lock_region_117(&mut self) -> LOCK_REGION_117_W<21> { + pub fn lock_region_117(&mut self) -> LOCK_REGION_117_W { LOCK_REGION_117_W::new(self) } #[doc = "Bit 22 - Lock Region 118"] #[inline(always)] #[must_use] - pub fn lock_region_118(&mut self) -> LOCK_REGION_118_W<22> { + pub fn lock_region_118(&mut self) -> LOCK_REGION_118_W { LOCK_REGION_118_W::new(self) } #[doc = "Bit 23 - Lock Region 119"] #[inline(always)] #[must_use] - pub fn lock_region_119(&mut self) -> LOCK_REGION_119_W<23> { + pub fn lock_region_119(&mut self) -> LOCK_REGION_119_W { LOCK_REGION_119_W::new(self) } #[doc = "Bit 24 - Lock Region 120"] #[inline(always)] #[must_use] - pub fn lock_region_120(&mut self) -> LOCK_REGION_120_W<24> { + pub fn lock_region_120(&mut self) -> LOCK_REGION_120_W { LOCK_REGION_120_W::new(self) } #[doc = "Bit 25 - Lock Region 121"] #[inline(always)] #[must_use] - pub fn lock_region_121(&mut self) -> LOCK_REGION_121_W<25> { + pub fn lock_region_121(&mut self) -> LOCK_REGION_121_W { LOCK_REGION_121_W::new(self) } #[doc = "Bit 26 - Lock Region 122"] #[inline(always)] #[must_use] - pub fn lock_region_122(&mut self) -> LOCK_REGION_122_W<26> { + pub fn lock_region_122(&mut self) -> LOCK_REGION_122_W { LOCK_REGION_122_W::new(self) } #[doc = "Bit 27 - Lock Region 123"] #[inline(always)] #[must_use] - pub fn lock_region_123(&mut self) -> LOCK_REGION_123_W<27> { + pub fn lock_region_123(&mut self) -> LOCK_REGION_123_W { LOCK_REGION_123_W::new(self) } #[doc = "Bit 28 - Lock Region 124"] #[inline(always)] #[must_use] - pub fn lock_region_124(&mut self) -> LOCK_REGION_124_W<28> { + pub fn lock_region_124(&mut self) -> LOCK_REGION_124_W { LOCK_REGION_124_W::new(self) } #[doc = "Bit 29 - Lock Region 125"] #[inline(always)] #[must_use] - pub fn lock_region_125(&mut self) -> LOCK_REGION_125_W<29> { + pub fn lock_region_125(&mut self) -> LOCK_REGION_125_W { LOCK_REGION_125_W::new(self) } #[doc = "Bit 30 - Lock Region 126"] #[inline(always)] #[must_use] - pub fn lock_region_126(&mut self) -> LOCK_REGION_126_W<30> { + pub fn lock_region_126(&mut self) -> LOCK_REGION_126_W { LOCK_REGION_126_W::new(self) } #[doc = "Bit 31 - Lock Region 127"] #[inline(always)] #[must_use] - pub fn lock_region_127(&mut self) -> LOCK_REGION_127_W<31> { + pub fn lock_region_127(&mut self) -> LOCK_REGION_127_W { LOCK_REGION_127_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Lock Bits Word 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [word3](index.html) module"] +#[doc = "Lock Bits Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`word3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`word3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WORD3_SPEC; impl crate::RegisterSpec for WORD3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [word3::R](R) reader structure"] -impl crate::Readable for WORD3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [word3::W](W) writer structure"] +#[doc = "`read()` method returns [`word3::R`](R) reader structure"] +impl crate::Readable for WORD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`word3::W`](W) writer structure"] impl crate::Writable for WORD3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix.rs b/arch/cortex-m/samv71q21-pac/src/matrix.rs index ac75a4a4..78623558 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix.rs @@ -30,11 +30,13 @@ pub struct RegisterBlock { #[doc = "0x1e8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "MCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "MCFG (rw) register accessor: Master Configuration Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mcfg`] +module"] pub type MCFG = crate::Reg; #[doc = "Master Configuration Register 0"] pub mod mcfg; -#[doc = "SCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "SCFG (rw) register accessor: Slave Configuration Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scfg`] +module"] pub type SCFG = crate::Reg; #[doc = "Slave Configuration Register 0"] pub mod scfg; @@ -43,35 +45,43 @@ pub use self::matrix_pr::MATRIX_PR; #[doc = r"Cluster"] #[doc = "Priority Register A for Slave 0"] pub mod matrix_pr; -#[doc = "MRCR (rw) register accessor: an alias for `Reg`"] +#[doc = "MRCR (rw) register accessor: Master Remap Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mrcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mrcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mrcr`] +module"] pub type MRCR = crate::Reg; #[doc = "Master Remap Control Register"] pub mod mrcr; -#[doc = "CCFG_CAN0 (rw) register accessor: an alias for `Reg`"] +#[doc = "CCFG_CAN0 (rw) register accessor: CAN0 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_can0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_can0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccfg_can0`] +module"] pub type CCFG_CAN0 = crate::Reg; #[doc = "CAN0 Configuration Register"] pub mod ccfg_can0; -#[doc = "CCFG_SYSIO (rw) register accessor: an alias for `Reg`"] +#[doc = "CCFG_SYSIO (rw) register accessor: System I/O and CAN1 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_sysio::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_sysio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccfg_sysio`] +module"] pub type CCFG_SYSIO = crate::Reg; #[doc = "System I/O and CAN1 Configuration Register"] pub mod ccfg_sysio; -#[doc = "CCFG_PCCR (rw) register accessor: an alias for `Reg`"] +#[doc = "CCFG_PCCR (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_pccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_pccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccfg_pccr`] +module"] pub type CCFG_PCCR = crate::Reg; #[doc = "Peripheral Clock Configuration Register"] pub mod ccfg_pccr; -#[doc = "CCFG_DYNCKG (rw) register accessor: an alias for `Reg`"] +#[doc = "CCFG_DYNCKG (rw) register accessor: Dynamic Clock Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_dynckg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_dynckg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccfg_dynckg`] +module"] pub type CCFG_DYNCKG = crate::Reg; #[doc = "Dynamic Clock Gating Register"] pub mod ccfg_dynckg; -#[doc = "CCFG_SMCNFCS (rw) register accessor: an alias for `Reg`"] +#[doc = "CCFG_SMCNFCS (rw) register accessor: SMC NAND Flash Chip Select Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_smcnfcs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_smcnfcs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccfg_smcnfcs`] +module"] pub type CCFG_SMCNFCS = crate::Reg; #[doc = "SMC NAND Flash Chip Select Configuration Register"] pub mod ccfg_smcnfcs; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_can0.rs b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_can0.rs index 66eebe90..fb504463 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_can0.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_can0.rs @@ -1,43 +1,11 @@ #[doc = "Register `CCFG_CAN0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CCFG_CAN0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CAN0DMABA` reader - CAN0 DMA Base Address"] pub type CAN0DMABA_R = crate::FieldReader; #[doc = "Field `CAN0DMABA` writer - CAN0 DMA Base Address"] -pub type CAN0DMABA_W<'a, const O: u8> = crate::FieldWriter<'a, CCFG_CAN0_SPEC, 16, O, u16>; +pub type CAN0DMABA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 16:31 - CAN0 DMA Base Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 16:31 - CAN0 DMA Base Address"] #[inline(always)] #[must_use] - pub fn can0dmaba(&mut self) -> CAN0DMABA_W<16> { + pub fn can0dmaba(&mut self) -> CAN0DMABA_W { CAN0DMABA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "CAN0 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccfg_can0](index.html) module"] +#[doc = "CAN0 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_can0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_can0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCFG_CAN0_SPEC; impl crate::RegisterSpec for CCFG_CAN0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccfg_can0::R](R) reader structure"] -impl crate::Readable for CCFG_CAN0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ccfg_can0::W](W) writer structure"] +#[doc = "`read()` method returns [`ccfg_can0::R`](R) reader structure"] +impl crate::Readable for CCFG_CAN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccfg_can0::W`](W) writer structure"] impl crate::Writable for CCFG_CAN0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_dynckg.rs b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_dynckg.rs index be751081..edb941b8 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_dynckg.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_dynckg.rs @@ -1,51 +1,19 @@ #[doc = "Register `CCFG_DYNCKG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CCFG_DYNCKG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MATCKG` reader - MATRIX Dynamic Clock Gating"] pub type MATCKG_R = crate::BitReader; #[doc = "Field `MATCKG` writer - MATRIX Dynamic Clock Gating"] -pub type MATCKG_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_DYNCKG_SPEC, O>; +pub type MATCKG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BRIDCKG` reader - Bridge Dynamic Clock Gating Enable"] pub type BRIDCKG_R = crate::BitReader; #[doc = "Field `BRIDCKG` writer - Bridge Dynamic Clock Gating Enable"] -pub type BRIDCKG_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_DYNCKG_SPEC, O>; +pub type BRIDCKG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EFCCKG` reader - EFC Dynamic Clock Gating Enable"] pub type EFCCKG_R = crate::BitReader; #[doc = "Field `EFCCKG` writer - EFC Dynamic Clock Gating Enable"] -pub type EFCCKG_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_DYNCKG_SPEC, O>; +pub type EFCCKG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - MATRIX Dynamic Clock Gating"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bit 0 - MATRIX Dynamic Clock Gating"] #[inline(always)] #[must_use] - pub fn matckg(&mut self) -> MATCKG_W<0> { + pub fn matckg(&mut self) -> MATCKG_W { MATCKG_W::new(self) } #[doc = "Bit 1 - Bridge Dynamic Clock Gating Enable"] #[inline(always)] #[must_use] - pub fn bridckg(&mut self) -> BRIDCKG_W<1> { + pub fn bridckg(&mut self) -> BRIDCKG_W { BRIDCKG_W::new(self) } #[doc = "Bit 2 - EFC Dynamic Clock Gating Enable"] #[inline(always)] #[must_use] - pub fn efcckg(&mut self) -> EFCCKG_W<2> { + pub fn efcckg(&mut self) -> EFCCKG_W { EFCCKG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Dynamic Clock Gating Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccfg_dynckg](index.html) module"] +#[doc = "Dynamic Clock Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_dynckg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_dynckg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCFG_DYNCKG_SPEC; impl crate::RegisterSpec for CCFG_DYNCKG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccfg_dynckg::R](R) reader structure"] -impl crate::Readable for CCFG_DYNCKG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ccfg_dynckg::W](W) writer structure"] +#[doc = "`read()` method returns [`ccfg_dynckg::R`](R) reader structure"] +impl crate::Readable for CCFG_DYNCKG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccfg_dynckg::W`](W) writer structure"] impl crate::Writable for CCFG_DYNCKG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_pccr.rs b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_pccr.rs index b12337fd..84a14aa3 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_pccr.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_pccr.rs @@ -1,51 +1,19 @@ #[doc = "Register `CCFG_PCCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CCFG_PCCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TC0CC` reader - TC0 Clock Configuration"] pub type TC0CC_R = crate::BitReader; #[doc = "Field `TC0CC` writer - TC0 Clock Configuration"] -pub type TC0CC_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_PCCR_SPEC, O>; +pub type TC0CC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2SC0CC` reader - I2SC0 Clock Configuration"] pub type I2SC0CC_R = crate::BitReader; #[doc = "Field `I2SC0CC` writer - I2SC0 Clock Configuration"] -pub type I2SC0CC_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_PCCR_SPEC, O>; +pub type I2SC0CC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `I2SC1CC` reader - I2SC1 Clock Configuration"] pub type I2SC1CC_R = crate::BitReader; #[doc = "Field `I2SC1CC` writer - I2SC1 Clock Configuration"] -pub type I2SC1CC_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_PCCR_SPEC, O>; +pub type I2SC1CC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 20 - TC0 Clock Configuration"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bit 20 - TC0 Clock Configuration"] #[inline(always)] #[must_use] - pub fn tc0cc(&mut self) -> TC0CC_W<20> { + pub fn tc0cc(&mut self) -> TC0CC_W { TC0CC_W::new(self) } #[doc = "Bit 21 - I2SC0 Clock Configuration"] #[inline(always)] #[must_use] - pub fn i2sc0cc(&mut self) -> I2SC0CC_W<21> { + pub fn i2sc0cc(&mut self) -> I2SC0CC_W { I2SC0CC_W::new(self) } #[doc = "Bit 22 - I2SC1 Clock Configuration"] #[inline(always)] #[must_use] - pub fn i2sc1cc(&mut self) -> I2SC1CC_W<22> { + pub fn i2sc1cc(&mut self) -> I2SC1CC_W { I2SC1CC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral Clock Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccfg_pccr](index.html) module"] +#[doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_pccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_pccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCFG_PCCR_SPEC; impl crate::RegisterSpec for CCFG_PCCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccfg_pccr::R](R) reader structure"] -impl crate::Readable for CCFG_PCCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ccfg_pccr::W](W) writer structure"] +#[doc = "`read()` method returns [`ccfg_pccr::R`](R) reader structure"] +impl crate::Readable for CCFG_PCCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccfg_pccr::W`](W) writer structure"] impl crate::Writable for CCFG_PCCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_smcnfcs.rs b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_smcnfcs.rs index e7756b73..14c1a9db 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_smcnfcs.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_smcnfcs.rs @@ -1,55 +1,23 @@ #[doc = "Register `CCFG_SMCNFCS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CCFG_SMCNFCS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMC_NFCS0` reader - SMC NAND Flash Chip Select 0 Assignment"] pub type SMC_NFCS0_R = crate::BitReader; #[doc = "Field `SMC_NFCS0` writer - SMC NAND Flash Chip Select 0 Assignment"] -pub type SMC_NFCS0_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SMCNFCS_SPEC, O>; +pub type SMC_NFCS0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMC_NFCS1` reader - SMC NAND Flash Chip Select 1 Assignment"] pub type SMC_NFCS1_R = crate::BitReader; #[doc = "Field `SMC_NFCS1` writer - SMC NAND Flash Chip Select 1 Assignment"] -pub type SMC_NFCS1_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SMCNFCS_SPEC, O>; +pub type SMC_NFCS1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMC_NFCS2` reader - SMC NAND Flash Chip Select 2 Assignment"] pub type SMC_NFCS2_R = crate::BitReader; #[doc = "Field `SMC_NFCS2` writer - SMC NAND Flash Chip Select 2 Assignment"] -pub type SMC_NFCS2_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SMCNFCS_SPEC, O>; +pub type SMC_NFCS2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMC_NFCS3` reader - SMC NAND Flash Chip Select 3 Assignment"] pub type SMC_NFCS3_R = crate::BitReader; #[doc = "Field `SMC_NFCS3` writer - SMC NAND Flash Chip Select 3 Assignment"] -pub type SMC_NFCS3_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SMCNFCS_SPEC, O>; +pub type SMC_NFCS3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - SMC NAND Flash Chip Select 0 Assignment"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - SMC NAND Flash Chip Select 0 Assignment"] #[inline(always)] #[must_use] - pub fn smc_nfcs0(&mut self) -> SMC_NFCS0_W<0> { + pub fn smc_nfcs0(&mut self) -> SMC_NFCS0_W { SMC_NFCS0_W::new(self) } #[doc = "Bit 1 - SMC NAND Flash Chip Select 1 Assignment"] #[inline(always)] #[must_use] - pub fn smc_nfcs1(&mut self) -> SMC_NFCS1_W<1> { + pub fn smc_nfcs1(&mut self) -> SMC_NFCS1_W { SMC_NFCS1_W::new(self) } #[doc = "Bit 2 - SMC NAND Flash Chip Select 2 Assignment"] #[inline(always)] #[must_use] - pub fn smc_nfcs2(&mut self) -> SMC_NFCS2_W<2> { + pub fn smc_nfcs2(&mut self) -> SMC_NFCS2_W { SMC_NFCS2_W::new(self) } #[doc = "Bit 3 - SMC NAND Flash Chip Select 3 Assignment"] #[inline(always)] #[must_use] - pub fn smc_nfcs3(&mut self) -> SMC_NFCS3_W<3> { + pub fn smc_nfcs3(&mut self) -> SMC_NFCS3_W { SMC_NFCS3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC NAND Flash Chip Select Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccfg_smcnfcs](index.html) module"] +#[doc = "SMC NAND Flash Chip Select Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_smcnfcs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_smcnfcs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCFG_SMCNFCS_SPEC; impl crate::RegisterSpec for CCFG_SMCNFCS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccfg_smcnfcs::R](R) reader structure"] -impl crate::Readable for CCFG_SMCNFCS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ccfg_smcnfcs::W](W) writer structure"] +#[doc = "`read()` method returns [`ccfg_smcnfcs::R`](R) reader structure"] +impl crate::Readable for CCFG_SMCNFCS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccfg_smcnfcs::W`](W) writer structure"] impl crate::Writable for CCFG_SMCNFCS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_sysio.rs b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_sysio.rs index 0046a6cf..8a99e470 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_sysio.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/ccfg_sysio.rs @@ -1,63 +1,31 @@ #[doc = "Register `CCFG_SYSIO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CCFG_SYSIO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SYSIO4` reader - PB4 or TDI Assignment"] pub type SYSIO4_R = crate::BitReader; #[doc = "Field `SYSIO4` writer - PB4 or TDI Assignment"] -pub type SYSIO4_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SYSIO_SPEC, O>; +pub type SYSIO4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYSIO5` reader - PB5 or TDO/TRACESWO Assignment"] pub type SYSIO5_R = crate::BitReader; #[doc = "Field `SYSIO5` writer - PB5 or TDO/TRACESWO Assignment"] -pub type SYSIO5_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SYSIO_SPEC, O>; +pub type SYSIO5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYSIO6` reader - PB6 or TMS/SWDIO Assignment"] pub type SYSIO6_R = crate::BitReader; #[doc = "Field `SYSIO6` writer - PB6 or TMS/SWDIO Assignment"] -pub type SYSIO6_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SYSIO_SPEC, O>; +pub type SYSIO6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYSIO7` reader - PB7 or TCK/SWCLK Assignment"] pub type SYSIO7_R = crate::BitReader; #[doc = "Field `SYSIO7` writer - PB7 or TCK/SWCLK Assignment"] -pub type SYSIO7_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SYSIO_SPEC, O>; +pub type SYSIO7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYSIO12` reader - PB12 or ERASE Assignment"] pub type SYSIO12_R = crate::BitReader; #[doc = "Field `SYSIO12` writer - PB12 or ERASE Assignment"] -pub type SYSIO12_W<'a, const O: u8> = crate::BitWriter<'a, CCFG_SYSIO_SPEC, O>; +pub type SYSIO12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAN1DMABA` reader - CAN1 DMA Base Address"] pub type CAN1DMABA_R = crate::FieldReader; #[doc = "Field `CAN1DMABA` writer - CAN1 DMA Base Address"] -pub type CAN1DMABA_W<'a, const O: u8> = crate::FieldWriter<'a, CCFG_SYSIO_SPEC, 16, O, u16>; +pub type CAN1DMABA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 4 - PB4 or TDI Assignment"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bit 4 - PB4 or TDI Assignment"] #[inline(always)] #[must_use] - pub fn sysio4(&mut self) -> SYSIO4_W<4> { + pub fn sysio4(&mut self) -> SYSIO4_W { SYSIO4_W::new(self) } #[doc = "Bit 5 - PB5 or TDO/TRACESWO Assignment"] #[inline(always)] #[must_use] - pub fn sysio5(&mut self) -> SYSIO5_W<5> { + pub fn sysio5(&mut self) -> SYSIO5_W { SYSIO5_W::new(self) } #[doc = "Bit 6 - PB6 or TMS/SWDIO Assignment"] #[inline(always)] #[must_use] - pub fn sysio6(&mut self) -> SYSIO6_W<6> { + pub fn sysio6(&mut self) -> SYSIO6_W { SYSIO6_W::new(self) } #[doc = "Bit 7 - PB7 or TCK/SWCLK Assignment"] #[inline(always)] #[must_use] - pub fn sysio7(&mut self) -> SYSIO7_W<7> { + pub fn sysio7(&mut self) -> SYSIO7_W { SYSIO7_W::new(self) } #[doc = "Bit 12 - PB12 or ERASE Assignment"] #[inline(always)] #[must_use] - pub fn sysio12(&mut self) -> SYSIO12_W<12> { + pub fn sysio12(&mut self) -> SYSIO12_W { SYSIO12_W::new(self) } #[doc = "Bits 16:31 - CAN1 DMA Base Address"] #[inline(always)] #[must_use] - pub fn can1dmaba(&mut self) -> CAN1DMABA_W<16> { + pub fn can1dmaba(&mut self) -> CAN1DMABA_W { CAN1DMABA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "System I/O and CAN1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccfg_sysio](index.html) module"] +#[doc = "System I/O and CAN1 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccfg_sysio::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccfg_sysio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCFG_SYSIO_SPEC; impl crate::RegisterSpec for CCFG_SYSIO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccfg_sysio::R](R) reader structure"] -impl crate::Readable for CCFG_SYSIO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ccfg_sysio::W](W) writer structure"] +#[doc = "`read()` method returns [`ccfg_sysio::R`](R) reader structure"] +impl crate::Readable for CCFG_SYSIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccfg_sysio::W`](W) writer structure"] impl crate::Writable for CCFG_SYSIO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr.rs b/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr.rs index 601c74e8..309a7d77 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr.rs @@ -6,11 +6,13 @@ pub struct MATRIX_PR { #[doc = "0x04 - Priority Register B for Slave 0"] pub prbs: PRBS, } -#[doc = "PRAS (rw) register accessor: an alias for `Reg`"] +#[doc = "PRAS (rw) register accessor: Priority Register A for Slave 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pras::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pras::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pras`] +module"] pub type PRAS = crate::Reg; #[doc = "Priority Register A for Slave 0"] pub mod pras; -#[doc = "PRBS (rw) register accessor: an alias for `Reg`"] +#[doc = "PRBS (rw) register accessor: Priority Register B for Slave 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prbs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prbs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`prbs`] +module"] pub type PRBS = crate::Reg; #[doc = "Priority Register B for Slave 0"] pub mod prbs; diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/pras.rs b/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/pras.rs index f1445b1e..b889bfdc 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/pras.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/pras.rs @@ -1,71 +1,39 @@ #[doc = "Register `PRAS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PRAS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `M0PR` reader - Master 0 Priority"] pub type M0PR_R = crate::FieldReader; #[doc = "Field `M0PR` writer - Master 0 Priority"] -pub type M0PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M0PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M1PR` reader - Master 1 Priority"] pub type M1PR_R = crate::FieldReader; #[doc = "Field `M1PR` writer - Master 1 Priority"] -pub type M1PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M1PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M2PR` reader - Master 2 Priority"] pub type M2PR_R = crate::FieldReader; #[doc = "Field `M2PR` writer - Master 2 Priority"] -pub type M2PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M2PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M3PR` reader - Master 3 Priority"] pub type M3PR_R = crate::FieldReader; #[doc = "Field `M3PR` writer - Master 3 Priority"] -pub type M3PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M3PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M4PR` reader - Master 4 Priority"] pub type M4PR_R = crate::FieldReader; #[doc = "Field `M4PR` writer - Master 4 Priority"] -pub type M4PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M4PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M5PR` reader - Master 5 Priority"] pub type M5PR_R = crate::FieldReader; #[doc = "Field `M5PR` writer - Master 5 Priority"] -pub type M5PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M5PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M6PR` reader - Master 6 Priority"] pub type M6PR_R = crate::FieldReader; #[doc = "Field `M6PR` writer - Master 6 Priority"] -pub type M6PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M6PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M7PR` reader - Master 7 Priority"] pub type M7PR_R = crate::FieldReader; #[doc = "Field `M7PR` writer - Master 7 Priority"] -pub type M7PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRAS_SPEC, 2, O>; +pub type M7PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Master 0 Priority"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bits 0:1 - Master 0 Priority"] #[inline(always)] #[must_use] - pub fn m0pr(&mut self) -> M0PR_W<0> { + pub fn m0pr(&mut self) -> M0PR_W { M0PR_W::new(self) } #[doc = "Bits 4:5 - Master 1 Priority"] #[inline(always)] #[must_use] - pub fn m1pr(&mut self) -> M1PR_W<4> { + pub fn m1pr(&mut self) -> M1PR_W { M1PR_W::new(self) } #[doc = "Bits 8:9 - Master 2 Priority"] #[inline(always)] #[must_use] - pub fn m2pr(&mut self) -> M2PR_W<8> { + pub fn m2pr(&mut self) -> M2PR_W { M2PR_W::new(self) } #[doc = "Bits 12:13 - Master 3 Priority"] #[inline(always)] #[must_use] - pub fn m3pr(&mut self) -> M3PR_W<12> { + pub fn m3pr(&mut self) -> M3PR_W { M3PR_W::new(self) } #[doc = "Bits 16:17 - Master 4 Priority"] #[inline(always)] #[must_use] - pub fn m4pr(&mut self) -> M4PR_W<16> { + pub fn m4pr(&mut self) -> M4PR_W { M4PR_W::new(self) } #[doc = "Bits 20:21 - Master 5 Priority"] #[inline(always)] #[must_use] - pub fn m5pr(&mut self) -> M5PR_W<20> { + pub fn m5pr(&mut self) -> M5PR_W { M5PR_W::new(self) } #[doc = "Bits 24:25 - Master 6 Priority"] #[inline(always)] #[must_use] - pub fn m6pr(&mut self) -> M6PR_W<24> { + pub fn m6pr(&mut self) -> M6PR_W { M6PR_W::new(self) } #[doc = "Bits 28:29 - Master 7 Priority"] #[inline(always)] #[must_use] - pub fn m7pr(&mut self) -> M7PR_W<28> { + pub fn m7pr(&mut self) -> M7PR_W { M7PR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Priority Register A for Slave 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pras](index.html) module"] +#[doc = "Priority Register A for Slave 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pras::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pras::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PRAS_SPEC; impl crate::RegisterSpec for PRAS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pras::R](R) reader structure"] -impl crate::Readable for PRAS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pras::W](W) writer structure"] +#[doc = "`read()` method returns [`pras::R`](R) reader structure"] +impl crate::Readable for PRAS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pras::W`](W) writer structure"] impl crate::Writable for PRAS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/prbs.rs b/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/prbs.rs index 72a26426..89a6225e 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/prbs.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/matrix_pr/prbs.rs @@ -1,59 +1,27 @@ #[doc = "Register `PRBS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PRBS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `M8PR` reader - Master 8 Priority"] pub type M8PR_R = crate::FieldReader; #[doc = "Field `M8PR` writer - Master 8 Priority"] -pub type M8PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRBS_SPEC, 2, O>; +pub type M8PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M9PR` reader - Master 9 Priority"] pub type M9PR_R = crate::FieldReader; #[doc = "Field `M9PR` writer - Master 9 Priority"] -pub type M9PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRBS_SPEC, 2, O>; +pub type M9PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M10PR` reader - Master 10 Priority"] pub type M10PR_R = crate::FieldReader; #[doc = "Field `M10PR` writer - Master 10 Priority"] -pub type M10PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRBS_SPEC, 2, O>; +pub type M10PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M11PR` reader - Master 11 Priority"] pub type M11PR_R = crate::FieldReader; #[doc = "Field `M11PR` writer - Master 11 Priority"] -pub type M11PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRBS_SPEC, 2, O>; +pub type M11PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; #[doc = "Field `M12PR` reader - Master 12 Priority"] pub type M12PR_R = crate::FieldReader; #[doc = "Field `M12PR` writer - Master 12 Priority"] -pub type M12PR_W<'a, const O: u8> = crate::FieldWriter<'a, PRBS_SPEC, 2, O>; +pub type M12PR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bits 0:1 - Master 8 Priority"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bits 0:1 - Master 8 Priority"] #[inline(always)] #[must_use] - pub fn m8pr(&mut self) -> M8PR_W<0> { + pub fn m8pr(&mut self) -> M8PR_W { M8PR_W::new(self) } #[doc = "Bits 4:5 - Master 9 Priority"] #[inline(always)] #[must_use] - pub fn m9pr(&mut self) -> M9PR_W<4> { + pub fn m9pr(&mut self) -> M9PR_W { M9PR_W::new(self) } #[doc = "Bits 8:9 - Master 10 Priority"] #[inline(always)] #[must_use] - pub fn m10pr(&mut self) -> M10PR_W<8> { + pub fn m10pr(&mut self) -> M10PR_W { M10PR_W::new(self) } #[doc = "Bits 12:13 - Master 11 Priority"] #[inline(always)] #[must_use] - pub fn m11pr(&mut self) -> M11PR_W<12> { + pub fn m11pr(&mut self) -> M11PR_W { M11PR_W::new(self) } #[doc = "Bits 16:17 - Master 12 Priority"] #[inline(always)] #[must_use] - pub fn m12pr(&mut self) -> M12PR_W<16> { + pub fn m12pr(&mut self) -> M12PR_W { M12PR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Priority Register B for Slave 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prbs](index.html) module"] +#[doc = "Priority Register B for Slave 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prbs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prbs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PRBS_SPEC; impl crate::RegisterSpec for PRBS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [prbs::R](R) reader structure"] -impl crate::Readable for PRBS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [prbs::W](W) writer structure"] +#[doc = "`read()` method returns [`prbs::R`](R) reader structure"] +impl crate::Readable for PRBS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`prbs::W`](W) writer structure"] impl crate::Writable for PRBS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/mcfg.rs b/arch/cortex-m/samv71q21-pac/src/matrix/mcfg.rs index c7bbc745..8f5e2657 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/mcfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/mcfg.rs @@ -1,39 +1,7 @@ #[doc = "Register `MCFG[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MCFG[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ULBT` reader - Undefined Length Burst Type"] pub type ULBT_R = crate::FieldReader; #[doc = "Undefined Length Burst Type\n\nValue on reset: 0"] @@ -82,88 +50,92 @@ impl ULBT_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `UNLTD_LENGTH`"] + #[doc = "Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave."] #[inline(always)] pub fn is_unltd_length(&self) -> bool { *self == ULBTSELECT_A::UNLTD_LENGTH } - #[doc = "Checks if the value of the field is `SINGLE_ACCESS`"] + #[doc = "Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence."] #[inline(always)] pub fn is_single_access(&self) -> bool { *self == ULBTSELECT_A::SINGLE_ACCESS } - #[doc = "Checks if the value of the field is `_4BEAT_BURST`"] + #[doc = "4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats."] #[inline(always)] pub fn is_4beat_burst(&self) -> bool { *self == ULBTSELECT_A::_4BEAT_BURST } - #[doc = "Checks if the value of the field is `_8BEAT_BURST`"] + #[doc = "8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats."] #[inline(always)] pub fn is_8beat_burst(&self) -> bool { *self == ULBTSELECT_A::_8BEAT_BURST } - #[doc = "Checks if the value of the field is `_16BEAT_BURST`"] + #[doc = "16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats."] #[inline(always)] pub fn is_16beat_burst(&self) -> bool { *self == ULBTSELECT_A::_16BEAT_BURST } - #[doc = "Checks if the value of the field is `_32BEAT_BURST`"] + #[doc = "32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats."] #[inline(always)] pub fn is_32beat_burst(&self) -> bool { *self == ULBTSELECT_A::_32BEAT_BURST } - #[doc = "Checks if the value of the field is `_64BEAT_BURST`"] + #[doc = "64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats."] #[inline(always)] pub fn is_64beat_burst(&self) -> bool { *self == ULBTSELECT_A::_64BEAT_BURST } - #[doc = "Checks if the value of the field is `_128BEAT_BURST`"] + #[doc = "128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats."] #[inline(always)] pub fn is_128beat_burst(&self) -> bool { *self == ULBTSELECT_A::_128BEAT_BURST } } #[doc = "Field `ULBT` writer - Undefined Length Burst Type"] -pub type ULBT_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MCFG_SPEC, 3, O, ULBTSELECT_A>; -impl<'a, const O: u8> ULBT_W<'a, O> { +pub type ULBT_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, ULBTSELECT_A>; +impl<'a, REG, const O: u8> ULBT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave."] #[inline(always)] - pub fn unltd_length(self) -> &'a mut W { + pub fn unltd_length(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::UNLTD_LENGTH) } #[doc = "Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence."] #[inline(always)] - pub fn single_access(self) -> &'a mut W { + pub fn single_access(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::SINGLE_ACCESS) } #[doc = "4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats."] #[inline(always)] - pub fn _4beat_burst(self) -> &'a mut W { + pub fn _4beat_burst(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::_4BEAT_BURST) } #[doc = "8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats."] #[inline(always)] - pub fn _8beat_burst(self) -> &'a mut W { + pub fn _8beat_burst(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::_8BEAT_BURST) } #[doc = "16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats."] #[inline(always)] - pub fn _16beat_burst(self) -> &'a mut W { + pub fn _16beat_burst(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::_16BEAT_BURST) } #[doc = "32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats."] #[inline(always)] - pub fn _32beat_burst(self) -> &'a mut W { + pub fn _32beat_burst(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::_32BEAT_BURST) } #[doc = "64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats."] #[inline(always)] - pub fn _64beat_burst(self) -> &'a mut W { + pub fn _64beat_burst(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::_64BEAT_BURST) } #[doc = "128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats."] #[inline(always)] - pub fn _128beat_burst(self) -> &'a mut W { + pub fn _128beat_burst(self) -> &'a mut crate::W { self.variant(ULBTSELECT_A::_128BEAT_BURST) } } @@ -178,28 +150,25 @@ impl W { #[doc = "Bits 0:2 - Undefined Length Burst Type"] #[inline(always)] #[must_use] - pub fn ulbt(&mut self) -> ULBT_W<0> { + pub fn ulbt(&mut self) -> ULBT_W { ULBT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Master Configuration Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mcfg](index.html) module"] +#[doc = "Master Configuration Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCFG_SPEC; impl crate::RegisterSpec for MCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mcfg::R](R) reader structure"] -impl crate::Readable for MCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`mcfg::R`](R) reader structure"] +impl crate::Readable for MCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mcfg::W`](W) writer structure"] impl crate::Writable for MCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/mrcr.rs b/arch/cortex-m/samv71q21-pac/src/matrix/mrcr.rs index 971e36e7..729f2303 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/mrcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/mrcr.rs @@ -1,91 +1,59 @@ #[doc = "Register `MRCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MRCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RCB0` reader - Remap Command Bit for Master 0"] pub type RCB0_R = crate::BitReader; #[doc = "Field `RCB0` writer - Remap Command Bit for Master 0"] -pub type RCB0_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB1` reader - Remap Command Bit for Master 1"] pub type RCB1_R = crate::BitReader; #[doc = "Field `RCB1` writer - Remap Command Bit for Master 1"] -pub type RCB1_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB2` reader - Remap Command Bit for Master 2"] pub type RCB2_R = crate::BitReader; #[doc = "Field `RCB2` writer - Remap Command Bit for Master 2"] -pub type RCB2_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB3` reader - Remap Command Bit for Master 3"] pub type RCB3_R = crate::BitReader; #[doc = "Field `RCB3` writer - Remap Command Bit for Master 3"] -pub type RCB3_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB4` reader - Remap Command Bit for Master 4"] pub type RCB4_R = crate::BitReader; #[doc = "Field `RCB4` writer - Remap Command Bit for Master 4"] -pub type RCB4_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB5` reader - Remap Command Bit for Master 5"] pub type RCB5_R = crate::BitReader; #[doc = "Field `RCB5` writer - Remap Command Bit for Master 5"] -pub type RCB5_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB6` reader - Remap Command Bit for Master 6"] pub type RCB6_R = crate::BitReader; #[doc = "Field `RCB6` writer - Remap Command Bit for Master 6"] -pub type RCB6_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB7` reader - Remap Command Bit for Master 7"] pub type RCB7_R = crate::BitReader; #[doc = "Field `RCB7` writer - Remap Command Bit for Master 7"] -pub type RCB7_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB8` reader - Remap Command Bit for Master 8"] pub type RCB8_R = crate::BitReader; #[doc = "Field `RCB8` writer - Remap Command Bit for Master 8"] -pub type RCB8_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB9` reader - Remap Command Bit for Master 9"] pub type RCB9_R = crate::BitReader; #[doc = "Field `RCB9` writer - Remap Command Bit for Master 9"] -pub type RCB9_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB10` reader - Remap Command Bit for Master 10"] pub type RCB10_R = crate::BitReader; #[doc = "Field `RCB10` writer - Remap Command Bit for Master 10"] -pub type RCB10_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB11` reader - Remap Command Bit for Master 11"] pub type RCB11_R = crate::BitReader; #[doc = "Field `RCB11` writer - Remap Command Bit for Master 11"] -pub type RCB11_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCB12` reader - Remap Command Bit for Master 12"] pub type RCB12_R = crate::BitReader; #[doc = "Field `RCB12` writer - Remap Command Bit for Master 12"] -pub type RCB12_W<'a, const O: u8> = crate::BitWriter<'a, MRCR_SPEC, O>; +pub type RCB12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Remap Command Bit for Master 0"] #[inline(always)] @@ -157,100 +125,97 @@ impl W { #[doc = "Bit 0 - Remap Command Bit for Master 0"] #[inline(always)] #[must_use] - pub fn rcb0(&mut self) -> RCB0_W<0> { + pub fn rcb0(&mut self) -> RCB0_W { RCB0_W::new(self) } #[doc = "Bit 1 - Remap Command Bit for Master 1"] #[inline(always)] #[must_use] - pub fn rcb1(&mut self) -> RCB1_W<1> { + pub fn rcb1(&mut self) -> RCB1_W { RCB1_W::new(self) } #[doc = "Bit 2 - Remap Command Bit for Master 2"] #[inline(always)] #[must_use] - pub fn rcb2(&mut self) -> RCB2_W<2> { + pub fn rcb2(&mut self) -> RCB2_W { RCB2_W::new(self) } #[doc = "Bit 3 - Remap Command Bit for Master 3"] #[inline(always)] #[must_use] - pub fn rcb3(&mut self) -> RCB3_W<3> { + pub fn rcb3(&mut self) -> RCB3_W { RCB3_W::new(self) } #[doc = "Bit 4 - Remap Command Bit for Master 4"] #[inline(always)] #[must_use] - pub fn rcb4(&mut self) -> RCB4_W<4> { + pub fn rcb4(&mut self) -> RCB4_W { RCB4_W::new(self) } #[doc = "Bit 5 - Remap Command Bit for Master 5"] #[inline(always)] #[must_use] - pub fn rcb5(&mut self) -> RCB5_W<5> { + pub fn rcb5(&mut self) -> RCB5_W { RCB5_W::new(self) } #[doc = "Bit 6 - Remap Command Bit for Master 6"] #[inline(always)] #[must_use] - pub fn rcb6(&mut self) -> RCB6_W<6> { + pub fn rcb6(&mut self) -> RCB6_W { RCB6_W::new(self) } #[doc = "Bit 7 - Remap Command Bit for Master 7"] #[inline(always)] #[must_use] - pub fn rcb7(&mut self) -> RCB7_W<7> { + pub fn rcb7(&mut self) -> RCB7_W { RCB7_W::new(self) } #[doc = "Bit 8 - Remap Command Bit for Master 8"] #[inline(always)] #[must_use] - pub fn rcb8(&mut self) -> RCB8_W<8> { + pub fn rcb8(&mut self) -> RCB8_W { RCB8_W::new(self) } #[doc = "Bit 9 - Remap Command Bit for Master 9"] #[inline(always)] #[must_use] - pub fn rcb9(&mut self) -> RCB9_W<9> { + pub fn rcb9(&mut self) -> RCB9_W { RCB9_W::new(self) } #[doc = "Bit 10 - Remap Command Bit for Master 10"] #[inline(always)] #[must_use] - pub fn rcb10(&mut self) -> RCB10_W<10> { + pub fn rcb10(&mut self) -> RCB10_W { RCB10_W::new(self) } #[doc = "Bit 11 - Remap Command Bit for Master 11"] #[inline(always)] #[must_use] - pub fn rcb11(&mut self) -> RCB11_W<11> { + pub fn rcb11(&mut self) -> RCB11_W { RCB11_W::new(self) } #[doc = "Bit 12 - Remap Command Bit for Master 12"] #[inline(always)] #[must_use] - pub fn rcb12(&mut self) -> RCB12_W<12> { + pub fn rcb12(&mut self) -> RCB12_W { RCB12_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Master Remap Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mrcr](index.html) module"] +#[doc = "Master Remap Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mrcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mrcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MRCR_SPEC; impl crate::RegisterSpec for MRCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mrcr::R](R) reader structure"] -impl crate::Readable for MRCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mrcr::W](W) writer structure"] +#[doc = "`read()` method returns [`mrcr::R`](R) reader structure"] +impl crate::Readable for MRCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mrcr::W`](W) writer structure"] impl crate::Writable for MRCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/scfg.rs b/arch/cortex-m/samv71q21-pac/src/matrix/scfg.rs index 2a25beb1..099916a7 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/scfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/scfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `SCFG[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCFG[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SLOT_CYCLE` reader - Maximum Bus Grant Duration for Masters"] pub type SLOT_CYCLE_R = crate::FieldReader; #[doc = "Field `SLOT_CYCLE` writer - Maximum Bus Grant Duration for Masters"] -pub type SLOT_CYCLE_W<'a, const O: u8> = crate::FieldWriter<'a, SCFG_SPEC, 9, O, u16>; +pub type SLOT_CYCLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `DEFMSTR_TYPE` reader - Default Master Type"] pub type DEFMSTR_TYPE_R = crate::FieldReader; #[doc = "Default Master Type\n\nValue on reset: 0"] @@ -71,46 +39,50 @@ impl DEFMSTR_TYPE_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access."] #[inline(always)] pub fn is_none(&self) -> bool { *self == DEFMSTR_TYPESELECT_A::NONE } - #[doc = "Checks if the value of the field is `LAST`"] + #[doc = "Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again."] #[inline(always)] pub fn is_last(&self) -> bool { *self == DEFMSTR_TYPESELECT_A::LAST } - #[doc = "Checks if the value of the field is `FIXED`"] + #[doc = "Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again."] #[inline(always)] pub fn is_fixed(&self) -> bool { *self == DEFMSTR_TYPESELECT_A::FIXED } } #[doc = "Field `DEFMSTR_TYPE` writer - Default Master Type"] -pub type DEFMSTR_TYPE_W<'a, const O: u8> = - crate::FieldWriter<'a, SCFG_SPEC, 2, O, DEFMSTR_TYPESELECT_A>; -impl<'a, const O: u8> DEFMSTR_TYPE_W<'a, O> { +pub type DEFMSTR_TYPE_W<'a, REG, const O: u8> = + crate::FieldWriter<'a, REG, 2, O, DEFMSTR_TYPESELECT_A>; +impl<'a, REG, const O: u8> DEFMSTR_TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access."] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(DEFMSTR_TYPESELECT_A::NONE) } #[doc = "Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again."] #[inline(always)] - pub fn last(self) -> &'a mut W { + pub fn last(self) -> &'a mut crate::W { self.variant(DEFMSTR_TYPESELECT_A::LAST) } #[doc = "Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again."] #[inline(always)] - pub fn fixed(self) -> &'a mut W { + pub fn fixed(self) -> &'a mut crate::W { self.variant(DEFMSTR_TYPESELECT_A::FIXED) } } #[doc = "Field `FIXED_DEFMSTR` reader - Fixed Default Master"] pub type FIXED_DEFMSTR_R = crate::FieldReader; #[doc = "Field `FIXED_DEFMSTR` writer - Fixed Default Master"] -pub type FIXED_DEFMSTR_W<'a, const O: u8> = crate::FieldWriter<'a, SCFG_SPEC, 4, O>; +pub type FIXED_DEFMSTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:8 - Maximum Bus Grant Duration for Masters"] #[inline(always)] @@ -132,40 +104,37 @@ impl W { #[doc = "Bits 0:8 - Maximum Bus Grant Duration for Masters"] #[inline(always)] #[must_use] - pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W<0> { + pub fn slot_cycle(&mut self) -> SLOT_CYCLE_W { SLOT_CYCLE_W::new(self) } #[doc = "Bits 16:17 - Default Master Type"] #[inline(always)] #[must_use] - pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W<16> { + pub fn defmstr_type(&mut self) -> DEFMSTR_TYPE_W { DEFMSTR_TYPE_W::new(self) } #[doc = "Bits 18:21 - Fixed Default Master"] #[inline(always)] #[must_use] - pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W<18> { + pub fn fixed_defmstr(&mut self) -> FIXED_DEFMSTR_W { FIXED_DEFMSTR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Slave Configuration Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scfg](index.html) module"] +#[doc = "Slave Configuration Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCFG_SPEC; impl crate::RegisterSpec for SCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scfg::R](R) reader structure"] -impl crate::Readable for SCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scfg::W](W) writer structure"] +#[doc = "`read()` method returns [`scfg::R`](R) reader structure"] +impl crate::Readable for SCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scfg::W`](W) writer structure"] impl crate::Writable for SCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/matrix/wpmr.rs index abcfcffa..7e1bb598 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/matrix/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/matrix/wpsr.rs index 69b9952f..216a7a8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/matrix/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/matrix/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0.rs b/arch/cortex-m/samv71q21-pac/src/mcan0.rs index 9a00f2dd..630bbf1e 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0.rs @@ -101,191 +101,238 @@ pub struct RegisterBlock { #[doc = "0xf8 - Transmit Event FIFO Acknowledge Register"] pub txefa: TXEFA, } -#[doc = "CREL (r) register accessor: an alias for `Reg`"] +#[doc = "CREL (r) register accessor: Core Release Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crel::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`crel`] +module"] pub type CREL = crate::Reg; #[doc = "Core Release Register"] pub mod crel; -#[doc = "ENDN (r) register accessor: an alias for `Reg`"] +#[doc = "ENDN (r) register accessor: Endian Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endn::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`endn`] +module"] pub type ENDN = crate::Reg; #[doc = "Endian Register"] pub mod endn; -#[doc = "CUST (rw) register accessor: an alias for `Reg`"] +#[doc = "CUST (rw) register accessor: Customer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cust::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cust::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cust`] +module"] pub type CUST = crate::Reg; #[doc = "Customer Register"] pub mod cust; -#[doc = "DBTP (rw) register accessor: an alias for `Reg`"] +#[doc = "DBTP (rw) register accessor: Data Bit Timing and Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbtp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbtp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dbtp`] +module"] pub type DBTP = crate::Reg; #[doc = "Data Bit Timing and Prescaler Register"] pub mod dbtp; -#[doc = "TEST (rw) register accessor: an alias for `Reg`"] +#[doc = "TEST (rw) register accessor: Test Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`test`] +module"] pub type TEST = crate::Reg; #[doc = "Test Register"] pub mod test; -#[doc = "RWD (rw) register accessor: an alias for `Reg`"] +#[doc = "RWD (rw) register accessor: RAM Watchdog Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rwd`] +module"] pub type RWD = crate::Reg; #[doc = "RAM Watchdog Register"] pub mod rwd; -#[doc = "CCCR (rw) register accessor: an alias for `Reg`"] +#[doc = "CCCR (rw) register accessor: CC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cccr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cccr`] +module"] pub type CCCR = crate::Reg; #[doc = "CC Control Register"] pub mod cccr; -#[doc = "NBTP (rw) register accessor: an alias for `Reg`"] +#[doc = "NBTP (rw) register accessor: Nominal Bit Timing and Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nbtp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nbtp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`nbtp`] +module"] pub type NBTP = crate::Reg; #[doc = "Nominal Bit Timing and Prescaler Register"] pub mod nbtp; -#[doc = "TSCC (rw) register accessor: an alias for `Reg`"] +#[doc = "TSCC (rw) register accessor: Timestamp Counter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tscc`] +module"] pub type TSCC = crate::Reg; #[doc = "Timestamp Counter Configuration Register"] pub mod tscc; -#[doc = "TSCV (rw) register accessor: an alias for `Reg`"] +#[doc = "TSCV (rw) register accessor: Timestamp Counter Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tscv`] +module"] pub type TSCV = crate::Reg; #[doc = "Timestamp Counter Value Register"] pub mod tscv; -#[doc = "TOCC (rw) register accessor: an alias for `Reg`"] +#[doc = "TOCC (rw) register accessor: Timeout Counter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tocc`] +module"] pub type TOCC = crate::Reg; #[doc = "Timeout Counter Configuration Register"] pub mod tocc; -#[doc = "TOCV (rw) register accessor: an alias for `Reg`"] +#[doc = "TOCV (rw) register accessor: Timeout Counter Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tocv`] +module"] pub type TOCV = crate::Reg; #[doc = "Timeout Counter Value Register"] pub mod tocv; -#[doc = "ECR (r) register accessor: an alias for `Reg`"] +#[doc = "ECR (r) register accessor: Error Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ecr`] +module"] pub type ECR = crate::Reg; #[doc = "Error Counter Register"] pub mod ecr; -#[doc = "PSR (r) register accessor: an alias for `Reg`"] +#[doc = "PSR (r) register accessor: Protocol Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`psr`] +module"] pub type PSR = crate::Reg; #[doc = "Protocol Status Register"] pub mod psr; -#[doc = "TDCR (rw) register accessor: an alias for `Reg`"] +#[doc = "TDCR (rw) register accessor: Transmit Delay Compensation Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tdcr`] +module"] pub type TDCR = crate::Reg; #[doc = "Transmit Delay Compensation Register"] pub mod tdcr; -#[doc = "IR (rw) register accessor: an alias for `Reg`"] +#[doc = "IR (rw) register accessor: Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ir`] +module"] pub type IR = crate::Reg; #[doc = "Interrupt Register"] pub mod ir; -#[doc = "IE (rw) register accessor: an alias for `Reg`"] +#[doc = "IE (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ie`] +module"] pub type IE = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ie; -#[doc = "ILS (rw) register accessor: an alias for `Reg`"] +#[doc = "ILS (rw) register accessor: Interrupt Line Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ils::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ils::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ils`] +module"] pub type ILS = crate::Reg; #[doc = "Interrupt Line Select Register"] pub mod ils; -#[doc = "ILE (rw) register accessor: an alias for `Reg`"] +#[doc = "ILE (rw) register accessor: Interrupt Line Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ile::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ile::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ile`] +module"] pub type ILE = crate::Reg; #[doc = "Interrupt Line Enable Register"] pub mod ile; -#[doc = "GFC (rw) register accessor: an alias for `Reg`"] +#[doc = "GFC (rw) register accessor: Global Filter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gfc`] +module"] pub type GFC = crate::Reg; #[doc = "Global Filter Configuration Register"] pub mod gfc; -#[doc = "SIDFC (rw) register accessor: an alias for `Reg`"] +#[doc = "SIDFC (rw) register accessor: Standard ID Filter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sidfc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sidfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sidfc`] +module"] pub type SIDFC = crate::Reg; #[doc = "Standard ID Filter Configuration Register"] pub mod sidfc; -#[doc = "XIDFC (rw) register accessor: an alias for `Reg`"] +#[doc = "XIDFC (rw) register accessor: Extended ID Filter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidfc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`xidfc`] +module"] pub type XIDFC = crate::Reg; #[doc = "Extended ID Filter Configuration Register"] pub mod xidfc; -#[doc = "XIDAM (rw) register accessor: an alias for `Reg`"] +#[doc = "XIDAM (rw) register accessor: Extended ID AND Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidam::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`xidam`] +module"] pub type XIDAM = crate::Reg; #[doc = "Extended ID AND Mask Register"] pub mod xidam; -#[doc = "HPMS (r) register accessor: an alias for `Reg`"] +#[doc = "HPMS (r) register accessor: High Priority Message Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpms::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hpms`] +module"] pub type HPMS = crate::Reg; #[doc = "High Priority Message Status Register"] pub mod hpms; -#[doc = "NDAT1 (rw) register accessor: an alias for `Reg`"] +#[doc = "NDAT1 (rw) register accessor: New Data 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ndat1`] +module"] pub type NDAT1 = crate::Reg; #[doc = "New Data 1 Register"] pub mod ndat1; -#[doc = "NDAT2 (rw) register accessor: an alias for `Reg`"] +#[doc = "NDAT2 (rw) register accessor: New Data 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ndat2`] +module"] pub type NDAT2 = crate::Reg; #[doc = "New Data 2 Register"] pub mod ndat2; -#[doc = "RXF0C (rw) register accessor: an alias for `Reg`"] +#[doc = "RXF0C (rw) register accessor: Receive FIFO 0 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxf0c`] +module"] pub type RXF0C = crate::Reg; #[doc = "Receive FIFO 0 Configuration Register"] pub mod rxf0c; -#[doc = "RXF0S (r) register accessor: an alias for `Reg`"] +#[doc = "RXF0S (r) register accessor: Receive FIFO 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0s::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxf0s`] +module"] pub type RXF0S = crate::Reg; #[doc = "Receive FIFO 0 Status Register"] pub mod rxf0s; -#[doc = "RXF0A (rw) register accessor: an alias for `Reg`"] +#[doc = "RXF0A (rw) register accessor: Receive FIFO 0 Acknowledge Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxf0a`] +module"] pub type RXF0A = crate::Reg; #[doc = "Receive FIFO 0 Acknowledge Register"] pub mod rxf0a; -#[doc = "RXBC (rw) register accessor: an alias for `Reg`"] +#[doc = "RXBC (rw) register accessor: Receive Rx Buffer Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxbc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxbc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxbc`] +module"] pub type RXBC = crate::Reg; #[doc = "Receive Rx Buffer Configuration Register"] pub mod rxbc; -#[doc = "RXF1C (rw) register accessor: an alias for `Reg`"] +#[doc = "RXF1C (rw) register accessor: Receive FIFO 1 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1c::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxf1c`] +module"] pub type RXF1C = crate::Reg; #[doc = "Receive FIFO 1 Configuration Register"] pub mod rxf1c; -#[doc = "RXF1S (r) register accessor: an alias for `Reg`"] +#[doc = "RXF1S (r) register accessor: Receive FIFO 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1s::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxf1s`] +module"] pub type RXF1S = crate::Reg; #[doc = "Receive FIFO 1 Status Register"] pub mod rxf1s; -#[doc = "RXF1A (rw) register accessor: an alias for `Reg`"] +#[doc = "RXF1A (rw) register accessor: Receive FIFO 1 Acknowledge Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1a::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxf1a`] +module"] pub type RXF1A = crate::Reg; #[doc = "Receive FIFO 1 Acknowledge Register"] pub mod rxf1a; -#[doc = "RXESC (rw) register accessor: an alias for `Reg`"] +#[doc = "RXESC (rw) register accessor: Receive Buffer / FIFO Element Size Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxesc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxesc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rxesc`] +module"] pub type RXESC = crate::Reg; #[doc = "Receive Buffer / FIFO Element Size Configuration Register"] pub mod rxesc; -#[doc = "TXBC (rw) register accessor: an alias for `Reg`"] +#[doc = "TXBC (rw) register accessor: Transmit Buffer Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbc`] +module"] pub type TXBC = crate::Reg; #[doc = "Transmit Buffer Configuration Register"] pub mod txbc; -#[doc = "TXFQS (r) register accessor: an alias for `Reg`"] +#[doc = "TXFQS (r) register accessor: Transmit FIFO/Queue Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfqs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txfqs`] +module"] pub type TXFQS = crate::Reg; #[doc = "Transmit FIFO/Queue Status Register"] pub mod txfqs; -#[doc = "TXESC (rw) register accessor: an alias for `Reg`"] +#[doc = "TXESC (rw) register accessor: Transmit Buffer Element Size Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txesc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txesc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txesc`] +module"] pub type TXESC = crate::Reg; #[doc = "Transmit Buffer Element Size Configuration Register"] pub mod txesc; -#[doc = "TXBRP (r) register accessor: an alias for `Reg`"] +#[doc = "TXBRP (r) register accessor: Transmit Buffer Request Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrp::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbrp`] +module"] pub type TXBRP = crate::Reg; #[doc = "Transmit Buffer Request Pending Register"] pub mod txbrp; -#[doc = "TXBAR (rw) register accessor: an alias for `Reg`"] +#[doc = "TXBAR (rw) register accessor: Transmit Buffer Add Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbar`] +module"] pub type TXBAR = crate::Reg; #[doc = "Transmit Buffer Add Request Register"] pub mod txbar; -#[doc = "TXBCR (rw) register accessor: an alias for `Reg`"] +#[doc = "TXBCR (rw) register accessor: Transmit Buffer Cancellation Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbcr`] +module"] pub type TXBCR = crate::Reg; #[doc = "Transmit Buffer Cancellation Request Register"] pub mod txbcr; -#[doc = "TXBTO (r) register accessor: an alias for `Reg`"] +#[doc = "TXBTO (r) register accessor: Transmit Buffer Transmission Occurred Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbto::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbto`] +module"] pub type TXBTO = crate::Reg; #[doc = "Transmit Buffer Transmission Occurred Register"] pub mod txbto; -#[doc = "TXBCF (r) register accessor: an alias for `Reg`"] +#[doc = "TXBCF (r) register accessor: Transmit Buffer Cancellation Finished Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcf::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbcf`] +module"] pub type TXBCF = crate::Reg; #[doc = "Transmit Buffer Cancellation Finished Register"] pub mod txbcf; -#[doc = "TXBTIE (rw) register accessor: an alias for `Reg`"] +#[doc = "TXBTIE (rw) register accessor: Transmit Buffer Transmission Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbtie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbtie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbtie`] +module"] pub type TXBTIE = crate::Reg; #[doc = "Transmit Buffer Transmission Interrupt Enable Register"] pub mod txbtie; -#[doc = "TXBCIE (rw) register accessor: an alias for `Reg`"] +#[doc = "TXBCIE (rw) register accessor: Transmit Buffer Cancellation Finished Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcie::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txbcie`] +module"] pub type TXBCIE = crate::Reg; #[doc = "Transmit Buffer Cancellation Finished Interrupt Enable Register"] pub mod txbcie; -#[doc = "TXEFC (rw) register accessor: an alias for `Reg`"] +#[doc = "TXEFC (rw) register accessor: Transmit Event FIFO Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txefc`] +module"] pub type TXEFC = crate::Reg; #[doc = "Transmit Event FIFO Configuration Register"] pub mod txefc; -#[doc = "TXEFS (r) register accessor: an alias for `Reg`"] +#[doc = "TXEFS (r) register accessor: Transmit Event FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txefs`] +module"] pub type TXEFS = crate::Reg; #[doc = "Transmit Event FIFO Status Register"] pub mod txefs; -#[doc = "TXEFA (rw) register accessor: an alias for `Reg`"] +#[doc = "TXEFA (rw) register accessor: Transmit Event FIFO Acknowledge Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`txefa`] +module"] pub type TXEFA = crate::Reg; #[doc = "Transmit Event FIFO Acknowledge Register"] pub mod txefa; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/cccr.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/cccr.rs index 39307b5a..433dc1b5 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/cccr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/cccr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CCCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CCCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INIT` reader - Initialization (read/write)"] pub type INIT_R = crate::BitReader; #[doc = "Initialization (read/write)\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl INIT_R { true => INITSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Normal operation."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == INITSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Initialization is started."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == INITSELECT_A::ENABLED } } #[doc = "Field `INIT` writer - Initialization (read/write)"] -pub type INIT_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, INITSELECT_A>; -impl<'a, const O: u8> INIT_W<'a, O> { +pub type INIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INITSELECT_A>; +impl<'a, REG, const O: u8> INIT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal operation."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(INITSELECT_A::DISABLED) } #[doc = "Initialization is started."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(INITSELECT_A::ENABLED) } } @@ -109,28 +80,31 @@ impl CCE_R { true => CCESELECT_A::CONFIGURABLE, } } - #[doc = "Checks if the value of the field is `PROTECTED`"] + #[doc = "The processor has no write access to the protected configuration registers."] #[inline(always)] pub fn is_protected(&self) -> bool { *self == CCESELECT_A::PROTECTED } - #[doc = "Checks if the value of the field is `CONFIGURABLE`"] + #[doc = "The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1')."] #[inline(always)] pub fn is_configurable(&self) -> bool { *self == CCESELECT_A::CONFIGURABLE } } #[doc = "Field `CCE` writer - Configuration Change Enable (read/write, write protection)"] -pub type CCE_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, CCESELECT_A>; -impl<'a, const O: u8> CCE_W<'a, O> { +pub type CCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CCESELECT_A>; +impl<'a, REG, const O: u8> CCE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The processor has no write access to the protected configuration registers."] #[inline(always)] - pub fn protected(self) -> &'a mut W { + pub fn protected(self) -> &'a mut crate::W { self.variant(CCESELECT_A::PROTECTED) } #[doc = "The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1')."] #[inline(always)] - pub fn configurable(self) -> &'a mut W { + pub fn configurable(self) -> &'a mut crate::W { self.variant(CCESELECT_A::CONFIGURABLE) } } @@ -159,35 +133,38 @@ impl ASM_R { true => ASMSELECT_A::RESTRICTED, } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "Normal CAN operation."] #[inline(always)] pub fn is_normal(&self) -> bool { *self == ASMSELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `RESTRICTED`"] + #[doc = "Restricted Operation mode active."] #[inline(always)] pub fn is_restricted(&self) -> bool { *self == ASMSELECT_A::RESTRICTED } } #[doc = "Field `ASM` writer - Restricted Operation Mode (read/write, write protection against '1')"] -pub type ASM_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, ASMSELECT_A>; -impl<'a, const O: u8> ASM_W<'a, O> { +pub type ASM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ASMSELECT_A>; +impl<'a, REG, const O: u8> ASM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal CAN operation."] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(ASMSELECT_A::NORMAL) } #[doc = "Restricted Operation mode active."] #[inline(always)] - pub fn restricted(self) -> &'a mut W { + pub fn restricted(self) -> &'a mut crate::W { self.variant(ASMSELECT_A::RESTRICTED) } } #[doc = "Field `CSA` reader - Clock Stop Acknowledge (read-only)"] pub type CSA_R = crate::BitReader; #[doc = "Field `CSA` writer - Clock Stop Acknowledge (read-only)"] -pub type CSA_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O>; +pub type CSA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSR` reader - Clock Stop Request (read/write)"] pub type CSR_R = crate::BitReader; #[doc = "Clock Stop Request (read/write)\n\nValue on reset: 0"] @@ -213,28 +190,31 @@ impl CSR_R { true => CSRSELECT_A::CLOCK_STOP, } } - #[doc = "Checks if the value of the field is `NO_CLOCK_STOP`"] + #[doc = "No clock stop is requested."] #[inline(always)] pub fn is_no_clock_stop(&self) -> bool { *self == CSRSELECT_A::NO_CLOCK_STOP } - #[doc = "Checks if the value of the field is `CLOCK_STOP`"] + #[doc = "Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle."] #[inline(always)] pub fn is_clock_stop(&self) -> bool { *self == CSRSELECT_A::CLOCK_STOP } } #[doc = "Field `CSR` writer - Clock Stop Request (read/write)"] -pub type CSR_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, CSRSELECT_A>; -impl<'a, const O: u8> CSR_W<'a, O> { +pub type CSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CSRSELECT_A>; +impl<'a, REG, const O: u8> CSR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No clock stop is requested."] #[inline(always)] - pub fn no_clock_stop(self) -> &'a mut W { + pub fn no_clock_stop(self) -> &'a mut crate::W { self.variant(CSRSELECT_A::NO_CLOCK_STOP) } #[doc = "Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle."] #[inline(always)] - pub fn clock_stop(self) -> &'a mut W { + pub fn clock_stop(self) -> &'a mut crate::W { self.variant(CSRSELECT_A::CLOCK_STOP) } } @@ -263,28 +243,31 @@ impl MON_R { true => MONSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Bus Monitoring mode is disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == MONSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Bus Monitoring mode is enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == MONSELECT_A::ENABLED } } #[doc = "Field `MON` writer - Bus Monitoring Mode (read/write, write protection against '1')"] -pub type MON_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, MONSELECT_A>; -impl<'a, const O: u8> MON_W<'a, O> { +pub type MON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MONSELECT_A>; +impl<'a, REG, const O: u8> MON_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Bus Monitoring mode is disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(MONSELECT_A::DISABLED) } #[doc = "Bus Monitoring mode is enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(MONSELECT_A::ENABLED) } } @@ -313,28 +296,31 @@ impl DAR_R { true => DARSELECT_A::NO_AUTO_RETX, } } - #[doc = "Checks if the value of the field is `AUTO_RETX`"] + #[doc = "Automatic retransmission of messages not transmitted successfully enabled."] #[inline(always)] pub fn is_auto_retx(&self) -> bool { *self == DARSELECT_A::AUTO_RETX } - #[doc = "Checks if the value of the field is `NO_AUTO_RETX`"] + #[doc = "Automatic retransmission disabled."] #[inline(always)] pub fn is_no_auto_retx(&self) -> bool { *self == DARSELECT_A::NO_AUTO_RETX } } #[doc = "Field `DAR` writer - Disable Automatic Retransmission (read/write, write protection)"] -pub type DAR_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, DARSELECT_A>; -impl<'a, const O: u8> DAR_W<'a, O> { +pub type DAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DARSELECT_A>; +impl<'a, REG, const O: u8> DAR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Automatic retransmission of messages not transmitted successfully enabled."] #[inline(always)] - pub fn auto_retx(self) -> &'a mut W { + pub fn auto_retx(self) -> &'a mut crate::W { self.variant(DARSELECT_A::AUTO_RETX) } #[doc = "Automatic retransmission disabled."] #[inline(always)] - pub fn no_auto_retx(self) -> &'a mut W { + pub fn no_auto_retx(self) -> &'a mut crate::W { self.variant(DARSELECT_A::NO_AUTO_RETX) } } @@ -363,28 +349,31 @@ impl TEST_R { true => TESTSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Normal operation, MCAN_TEST register holds reset values."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == TESTSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Test mode, write access to MCAN_TEST register enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == TESTSELECT_A::ENABLED } } #[doc = "Field `TEST` writer - Test Mode Enable (read/write, write protection against '1')"] -pub type TEST_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, TESTSELECT_A>; -impl<'a, const O: u8> TEST_W<'a, O> { +pub type TEST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TESTSELECT_A>; +impl<'a, REG, const O: u8> TEST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Normal operation, MCAN_TEST register holds reset values."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(TESTSELECT_A::DISABLED) } #[doc = "Test mode, write access to MCAN_TEST register enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(TESTSELECT_A::ENABLED) } } @@ -413,28 +402,31 @@ impl FDOE_R { true => FDOESELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "FD operation disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == FDOESELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "FD operation enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == FDOESELECT_A::ENABLED } } #[doc = "Field `FDOE` writer - CAN FD Operation Enable (read/write, write protection)"] -pub type FDOE_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, FDOESELECT_A>; -impl<'a, const O: u8> FDOE_W<'a, O> { +pub type FDOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FDOESELECT_A>; +impl<'a, REG, const O: u8> FDOE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "FD operation disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(FDOESELECT_A::DISABLED) } #[doc = "FD operation enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(FDOESELECT_A::ENABLED) } } @@ -463,47 +455,50 @@ impl BRSE_R { true => BRSESELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Bit rate switching for transmissions disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == BRSESELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Bit rate switching for transmissions enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == BRSESELECT_A::ENABLED } } #[doc = "Field `BRSE` writer - Bit Rate Switching Enable (read/write, write protection)"] -pub type BRSE_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O, BRSESELECT_A>; -impl<'a, const O: u8> BRSE_W<'a, O> { +pub type BRSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BRSESELECT_A>; +impl<'a, REG, const O: u8> BRSE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Bit rate switching for transmissions disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(BRSESELECT_A::DISABLED) } #[doc = "Bit rate switching for transmissions enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(BRSESELECT_A::ENABLED) } } #[doc = "Field `PXHD` reader - Protocol Exception Event Handling (read/write, write protection)"] pub type PXHD_R = crate::BitReader; #[doc = "Field `PXHD` writer - Protocol Exception Event Handling (read/write, write protection)"] -pub type PXHD_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O>; +pub type PXHD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EFBI` reader - Edge Filtering during Bus Integration (read/write, write protection)"] pub type EFBI_R = crate::BitReader; #[doc = "Field `EFBI` writer - Edge Filtering during Bus Integration (read/write, write protection)"] -pub type EFBI_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O>; +pub type EFBI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXP` reader - Transmit Pause (read/write, write protection)"] pub type TXP_R = crate::BitReader; #[doc = "Field `TXP` writer - Transmit Pause (read/write, write protection)"] -pub type TXP_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O>; +pub type TXP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NISO` reader - Non-ISO Operation"] pub type NISO_R = crate::BitReader; #[doc = "Field `NISO` writer - Non-ISO Operation"] -pub type NISO_W<'a, const O: u8> = crate::BitWriter<'a, CCCR_SPEC, O>; +pub type NISO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Initialization (read/write)"] #[inline(always)] @@ -580,106 +575,103 @@ impl W { #[doc = "Bit 0 - Initialization (read/write)"] #[inline(always)] #[must_use] - pub fn init(&mut self) -> INIT_W<0> { + pub fn init(&mut self) -> INIT_W { INIT_W::new(self) } #[doc = "Bit 1 - Configuration Change Enable (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn cce(&mut self) -> CCE_W<1> { + pub fn cce(&mut self) -> CCE_W { CCE_W::new(self) } #[doc = "Bit 2 - Restricted Operation Mode (read/write, write protection against '1')"] #[inline(always)] #[must_use] - pub fn asm(&mut self) -> ASM_W<2> { + pub fn asm(&mut self) -> ASM_W { ASM_W::new(self) } #[doc = "Bit 3 - Clock Stop Acknowledge (read-only)"] #[inline(always)] #[must_use] - pub fn csa(&mut self) -> CSA_W<3> { + pub fn csa(&mut self) -> CSA_W { CSA_W::new(self) } #[doc = "Bit 4 - Clock Stop Request (read/write)"] #[inline(always)] #[must_use] - pub fn csr(&mut self) -> CSR_W<4> { + pub fn csr(&mut self) -> CSR_W { CSR_W::new(self) } #[doc = "Bit 5 - Bus Monitoring Mode (read/write, write protection against '1')"] #[inline(always)] #[must_use] - pub fn mon(&mut self) -> MON_W<5> { + pub fn mon(&mut self) -> MON_W { MON_W::new(self) } #[doc = "Bit 6 - Disable Automatic Retransmission (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn dar(&mut self) -> DAR_W<6> { + pub fn dar(&mut self) -> DAR_W { DAR_W::new(self) } #[doc = "Bit 7 - Test Mode Enable (read/write, write protection against '1')"] #[inline(always)] #[must_use] - pub fn test(&mut self) -> TEST_W<7> { + pub fn test(&mut self) -> TEST_W { TEST_W::new(self) } #[doc = "Bit 8 - CAN FD Operation Enable (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn fdoe(&mut self) -> FDOE_W<8> { + pub fn fdoe(&mut self) -> FDOE_W { FDOE_W::new(self) } #[doc = "Bit 9 - Bit Rate Switching Enable (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn brse(&mut self) -> BRSE_W<9> { + pub fn brse(&mut self) -> BRSE_W { BRSE_W::new(self) } #[doc = "Bit 12 - Protocol Exception Event Handling (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn pxhd(&mut self) -> PXHD_W<12> { + pub fn pxhd(&mut self) -> PXHD_W { PXHD_W::new(self) } #[doc = "Bit 13 - Edge Filtering during Bus Integration (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn efbi(&mut self) -> EFBI_W<13> { + pub fn efbi(&mut self) -> EFBI_W { EFBI_W::new(self) } #[doc = "Bit 14 - Transmit Pause (read/write, write protection)"] #[inline(always)] #[must_use] - pub fn txp(&mut self) -> TXP_W<14> { + pub fn txp(&mut self) -> TXP_W { TXP_W::new(self) } #[doc = "Bit 15 - Non-ISO Operation"] #[inline(always)] #[must_use] - pub fn niso(&mut self) -> NISO_W<15> { + pub fn niso(&mut self) -> NISO_W { NISO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "CC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cccr](index.html) module"] +#[doc = "CC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cccr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCCR_SPEC; impl crate::RegisterSpec for CCCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cccr::R](R) reader structure"] -impl crate::Readable for CCCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cccr::W](W) writer structure"] +#[doc = "`read()` method returns [`cccr::R`](R) reader structure"] +impl crate::Readable for CCCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cccr::W`](W) writer structure"] impl crate::Writable for CCCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/crel.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/crel.rs index e4becfa9..8677a0da 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/crel.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/crel.rs @@ -1,18 +1,5 @@ #[doc = "Register `CREL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DAY` reader - Timestamp Day"] pub type DAY_R = crate::FieldReader; #[doc = "Field `MON` reader - Timestamp Month"] @@ -57,15 +44,13 @@ impl R { REL_R::new(((self.bits >> 28) & 0x0f) as u8) } } -#[doc = "Core Release Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crel](index.html) module"] +#[doc = "Core Release Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crel::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CREL_SPEC; impl crate::RegisterSpec for CREL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [crel::R](R) reader structure"] -impl crate::Readable for CREL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`crel::R`](R) reader structure"] +impl crate::Readable for CREL_SPEC {} #[doc = "`reset()` method sets CREL to value 0"] impl crate::Resettable for CREL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/cust.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/cust.rs index 52fa165b..0125e4e0 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/cust.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/cust.rs @@ -1,43 +1,11 @@ #[doc = "Register `CUST` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CUST` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSV` reader - Customer-specific Value"] pub type CSV_R = crate::FieldReader; #[doc = "Field `CSV` writer - Customer-specific Value"] -pub type CSV_W<'a, const O: u8> = crate::FieldWriter<'a, CUST_SPEC, 32, O, u32>; +pub type CSV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Customer-specific Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Customer-specific Value"] #[inline(always)] #[must_use] - pub fn csv(&mut self) -> CSV_W<0> { + pub fn csv(&mut self) -> CSV_W { CSV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Customer Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cust](index.html) module"] +#[doc = "Customer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cust::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cust::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CUST_SPEC; impl crate::RegisterSpec for CUST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cust::R](R) reader structure"] -impl crate::Readable for CUST_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cust::W](W) writer structure"] +#[doc = "`read()` method returns [`cust::R`](R) reader structure"] +impl crate::Readable for CUST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cust::W`](W) writer structure"] impl crate::Writable for CUST_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/dbtp.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/dbtp.rs index 0617ac41..cd31e01e 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/dbtp.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/dbtp.rs @@ -1,55 +1,23 @@ #[doc = "Register `DBTP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DBTP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DSJW` reader - Data (Re) Synchronization Jump Width"] pub type DSJW_R = crate::FieldReader; #[doc = "Field `DSJW` writer - Data (Re) Synchronization Jump Width"] -pub type DSJW_W<'a, const O: u8> = crate::FieldWriter<'a, DBTP_SPEC, 3, O>; +pub type DSJW_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DTSEG2` reader - Data Time Segment After Sample Point"] pub type DTSEG2_R = crate::FieldReader; #[doc = "Field `DTSEG2` writer - Data Time Segment After Sample Point"] -pub type DTSEG2_W<'a, const O: u8> = crate::FieldWriter<'a, DBTP_SPEC, 4, O>; +pub type DTSEG2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `DTSEG1` reader - Data Time Segment Before Sample Point"] pub type DTSEG1_R = crate::FieldReader; #[doc = "Field `DTSEG1` writer - Data Time Segment Before Sample Point"] -pub type DTSEG1_W<'a, const O: u8> = crate::FieldWriter<'a, DBTP_SPEC, 5, O>; +pub type DTSEG1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DBRP` reader - Data Bit Rate Prescaler"] pub type DBRP_R = crate::FieldReader; #[doc = "Field `DBRP` writer - Data Bit Rate Prescaler"] -pub type DBRP_W<'a, const O: u8> = crate::FieldWriter<'a, DBTP_SPEC, 5, O>; +pub type DBRP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `TDC` reader - Transmitter Delay Compensation"] pub type TDC_R = crate::BitReader; #[doc = "Transmitter Delay Compensation\n\nValue on reset: 0"] @@ -75,28 +43,31 @@ impl TDC_R { true => TDCSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Transmitter Delay Compensation disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == TDCSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Transmitter Delay Compensation enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == TDCSELECT_A::ENABLED } } #[doc = "Field `TDC` writer - Transmitter Delay Compensation"] -pub type TDC_W<'a, const O: u8> = crate::BitWriter<'a, DBTP_SPEC, O, TDCSELECT_A>; -impl<'a, const O: u8> TDC_W<'a, O> { +pub type TDC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TDCSELECT_A>; +impl<'a, REG, const O: u8> TDC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Transmitter Delay Compensation disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(TDCSELECT_A::DISABLED) } #[doc = "Transmitter Delay Compensation enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(TDCSELECT_A::ENABLED) } } @@ -131,52 +102,49 @@ impl W { #[doc = "Bits 0:2 - Data (Re) Synchronization Jump Width"] #[inline(always)] #[must_use] - pub fn dsjw(&mut self) -> DSJW_W<0> { + pub fn dsjw(&mut self) -> DSJW_W { DSJW_W::new(self) } #[doc = "Bits 4:7 - Data Time Segment After Sample Point"] #[inline(always)] #[must_use] - pub fn dtseg2(&mut self) -> DTSEG2_W<4> { + pub fn dtseg2(&mut self) -> DTSEG2_W { DTSEG2_W::new(self) } #[doc = "Bits 8:12 - Data Time Segment Before Sample Point"] #[inline(always)] #[must_use] - pub fn dtseg1(&mut self) -> DTSEG1_W<8> { + pub fn dtseg1(&mut self) -> DTSEG1_W { DTSEG1_W::new(self) } #[doc = "Bits 16:20 - Data Bit Rate Prescaler"] #[inline(always)] #[must_use] - pub fn dbrp(&mut self) -> DBRP_W<16> { + pub fn dbrp(&mut self) -> DBRP_W { DBRP_W::new(self) } #[doc = "Bit 23 - Transmitter Delay Compensation"] #[inline(always)] #[must_use] - pub fn tdc(&mut self) -> TDC_W<23> { + pub fn tdc(&mut self) -> TDC_W { TDC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Data Bit Timing and Prescaler Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbtp](index.html) module"] +#[doc = "Data Bit Timing and Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbtp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbtp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DBTP_SPEC; impl crate::RegisterSpec for DBTP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dbtp::R](R) reader structure"] -impl crate::Readable for DBTP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dbtp::W](W) writer structure"] +#[doc = "`read()` method returns [`dbtp::R`](R) reader structure"] +impl crate::Readable for DBTP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbtp::W`](W) writer structure"] impl crate::Writable for DBTP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ecr.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ecr.rs index dd5bae55..5d81781f 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ecr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ecr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ECR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TEC` reader - Transmit Error Counter"] pub type TEC_R = crate::FieldReader; #[doc = "Field `REC` reader - Receive Error Counter"] @@ -43,15 +30,13 @@ impl R { CEL_R::new(((self.bits >> 16) & 0xff) as u8) } } -#[doc = "Error Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ecr](index.html) module"] +#[doc = "Error Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ECR_SPEC; impl crate::RegisterSpec for ECR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ecr::R](R) reader structure"] -impl crate::Readable for ECR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ecr::R`](R) reader structure"] +impl crate::Readable for ECR_SPEC {} #[doc = "`reset()` method sets ECR to value 0"] impl crate::Resettable for ECR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/endn.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/endn.rs index 236820aa..062b6c6c 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/endn.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/endn.rs @@ -1,18 +1,5 @@ #[doc = "Register `ENDN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ETV` reader - Endianness Test Value"] pub type ETV_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { ETV_R::new(self.bits) } } -#[doc = "Endian Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [endn](index.html) module"] +#[doc = "Endian Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endn::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENDN_SPEC; impl crate::RegisterSpec for ENDN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [endn::R](R) reader structure"] -impl crate::Readable for ENDN_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`endn::R`](R) reader structure"] +impl crate::Readable for ENDN_SPEC {} #[doc = "`reset()` method sets ENDN to value 0"] impl crate::Resettable for ENDN_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/gfc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/gfc.rs index 196fb218..5fa6d2be 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/gfc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/gfc.rs @@ -1,39 +1,7 @@ #[doc = "Register `GFC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GFC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RRFE` reader - Reject Remote Frames Extended"] pub type RRFE_R = crate::BitReader; #[doc = "Reject Remote Frames Extended\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl RRFE_R { true => RRFESELECT_A::REJECT, } } - #[doc = "Checks if the value of the field is `FILTER`"] + #[doc = "Filter remote frames with 29-bit extended IDs."] #[inline(always)] pub fn is_filter(&self) -> bool { *self == RRFESELECT_A::FILTER } - #[doc = "Checks if the value of the field is `REJECT`"] + #[doc = "Reject all remote frames with 29-bit extended IDs."] #[inline(always)] pub fn is_reject(&self) -> bool { *self == RRFESELECT_A::REJECT } } #[doc = "Field `RRFE` writer - Reject Remote Frames Extended"] -pub type RRFE_W<'a, const O: u8> = crate::BitWriter<'a, GFC_SPEC, O, RRFESELECT_A>; -impl<'a, const O: u8> RRFE_W<'a, O> { +pub type RRFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RRFESELECT_A>; +impl<'a, REG, const O: u8> RRFE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Filter remote frames with 29-bit extended IDs."] #[inline(always)] - pub fn filter(self) -> &'a mut W { + pub fn filter(self) -> &'a mut crate::W { self.variant(RRFESELECT_A::FILTER) } #[doc = "Reject all remote frames with 29-bit extended IDs."] #[inline(always)] - pub fn reject(self) -> &'a mut W { + pub fn reject(self) -> &'a mut crate::W { self.variant(RRFESELECT_A::REJECT) } } @@ -109,28 +80,31 @@ impl RRFS_R { true => RRFSSELECT_A::REJECT, } } - #[doc = "Checks if the value of the field is `FILTER`"] + #[doc = "Filter remote frames with 11-bit standard IDs."] #[inline(always)] pub fn is_filter(&self) -> bool { *self == RRFSSELECT_A::FILTER } - #[doc = "Checks if the value of the field is `REJECT`"] + #[doc = "Reject all remote frames with 11-bit standard IDs."] #[inline(always)] pub fn is_reject(&self) -> bool { *self == RRFSSELECT_A::REJECT } } #[doc = "Field `RRFS` writer - Reject Remote Frames Standard"] -pub type RRFS_W<'a, const O: u8> = crate::BitWriter<'a, GFC_SPEC, O, RRFSSELECT_A>; -impl<'a, const O: u8> RRFS_W<'a, O> { +pub type RRFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RRFSSELECT_A>; +impl<'a, REG, const O: u8> RRFS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Filter remote frames with 11-bit standard IDs."] #[inline(always)] - pub fn filter(self) -> &'a mut W { + pub fn filter(self) -> &'a mut crate::W { self.variant(RRFSSELECT_A::FILTER) } #[doc = "Reject all remote frames with 11-bit standard IDs."] #[inline(always)] - pub fn reject(self) -> &'a mut W { + pub fn reject(self) -> &'a mut crate::W { self.variant(RRFSSELECT_A::REJECT) } } @@ -164,28 +138,32 @@ impl ANFE_R { _ => None, } } - #[doc = "Checks if the value of the field is `RX_FIFO_0`"] + #[doc = "Accept in Rx FIFO 0"] #[inline(always)] pub fn is_rx_fifo_0(&self) -> bool { *self == ANFESELECT_A::RX_FIFO_0 } - #[doc = "Checks if the value of the field is `RX_FIFO_1`"] + #[doc = "Accept in Rx FIFO 1"] #[inline(always)] pub fn is_rx_fifo_1(&self) -> bool { *self == ANFESELECT_A::RX_FIFO_1 } } #[doc = "Field `ANFE` writer - Accept Non-matching Frames Extended"] -pub type ANFE_W<'a, const O: u8> = crate::FieldWriter<'a, GFC_SPEC, 2, O, ANFESELECT_A>; -impl<'a, const O: u8> ANFE_W<'a, O> { +pub type ANFE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, ANFESELECT_A>; +impl<'a, REG, const O: u8> ANFE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Accept in Rx FIFO 0"] #[inline(always)] - pub fn rx_fifo_0(self) -> &'a mut W { + pub fn rx_fifo_0(self) -> &'a mut crate::W { self.variant(ANFESELECT_A::RX_FIFO_0) } #[doc = "Accept in Rx FIFO 1"] #[inline(always)] - pub fn rx_fifo_1(self) -> &'a mut W { + pub fn rx_fifo_1(self) -> &'a mut crate::W { self.variant(ANFESELECT_A::RX_FIFO_1) } } @@ -219,28 +197,32 @@ impl ANFS_R { _ => None, } } - #[doc = "Checks if the value of the field is `RX_FIFO_0`"] + #[doc = "Accept in Rx FIFO 0"] #[inline(always)] pub fn is_rx_fifo_0(&self) -> bool { *self == ANFSSELECT_A::RX_FIFO_0 } - #[doc = "Checks if the value of the field is `RX_FIFO_1`"] + #[doc = "Accept in Rx FIFO 1"] #[inline(always)] pub fn is_rx_fifo_1(&self) -> bool { *self == ANFSSELECT_A::RX_FIFO_1 } } #[doc = "Field `ANFS` writer - Accept Non-matching Frames Standard"] -pub type ANFS_W<'a, const O: u8> = crate::FieldWriter<'a, GFC_SPEC, 2, O, ANFSSELECT_A>; -impl<'a, const O: u8> ANFS_W<'a, O> { +pub type ANFS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, ANFSSELECT_A>; +impl<'a, REG, const O: u8> ANFS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Accept in Rx FIFO 0"] #[inline(always)] - pub fn rx_fifo_0(self) -> &'a mut W { + pub fn rx_fifo_0(self) -> &'a mut crate::W { self.variant(ANFSSELECT_A::RX_FIFO_0) } #[doc = "Accept in Rx FIFO 1"] #[inline(always)] - pub fn rx_fifo_1(self) -> &'a mut W { + pub fn rx_fifo_1(self) -> &'a mut crate::W { self.variant(ANFSSELECT_A::RX_FIFO_1) } } @@ -270,46 +252,43 @@ impl W { #[doc = "Bit 0 - Reject Remote Frames Extended"] #[inline(always)] #[must_use] - pub fn rrfe(&mut self) -> RRFE_W<0> { + pub fn rrfe(&mut self) -> RRFE_W { RRFE_W::new(self) } #[doc = "Bit 1 - Reject Remote Frames Standard"] #[inline(always)] #[must_use] - pub fn rrfs(&mut self) -> RRFS_W<1> { + pub fn rrfs(&mut self) -> RRFS_W { RRFS_W::new(self) } #[doc = "Bits 2:3 - Accept Non-matching Frames Extended"] #[inline(always)] #[must_use] - pub fn anfe(&mut self) -> ANFE_W<2> { + pub fn anfe(&mut self) -> ANFE_W { ANFE_W::new(self) } #[doc = "Bits 4:5 - Accept Non-matching Frames Standard"] #[inline(always)] #[must_use] - pub fn anfs(&mut self) -> ANFS_W<4> { + pub fn anfs(&mut self) -> ANFS_W { ANFS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Filter Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gfc](index.html) module"] +#[doc = "Global Filter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GFC_SPEC; impl crate::RegisterSpec for GFC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gfc::R](R) reader structure"] -impl crate::Readable for GFC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gfc::W](W) writer structure"] +#[doc = "`read()` method returns [`gfc::R`](R) reader structure"] +impl crate::Readable for GFC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gfc::W`](W) writer structure"] impl crate::Writable for GFC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/hpms.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/hpms.rs index 7d52ef54..6b7df303 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/hpms.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/hpms.rs @@ -1,18 +1,5 @@ #[doc = "Register `HPMS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BIDX` reader - Buffer Index"] pub type BIDX_R = crate::FieldReader; #[doc = "Field `MSI` reader - Message Storage Indicator"] @@ -51,22 +38,22 @@ impl MSI_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NO_FIFO_SEL`"] + #[doc = "No FIFO selected."] #[inline(always)] pub fn is_no_fifo_sel(&self) -> bool { *self == MSISELECT_A::NO_FIFO_SEL } - #[doc = "Checks if the value of the field is `LOST`"] + #[doc = "FIFO message lost."] #[inline(always)] pub fn is_lost(&self) -> bool { *self == MSISELECT_A::LOST } - #[doc = "Checks if the value of the field is `FIFO_0`"] + #[doc = "Message stored in FIFO 0."] #[inline(always)] pub fn is_fifo_0(&self) -> bool { *self == MSISELECT_A::FIFO_0 } - #[doc = "Checks if the value of the field is `FIFO_1`"] + #[doc = "Message stored in FIFO 1."] #[inline(always)] pub fn is_fifo_1(&self) -> bool { *self == MSISELECT_A::FIFO_1 @@ -98,15 +85,13 @@ impl R { FLST_R::new(((self.bits >> 15) & 1) != 0) } } -#[doc = "High Priority Message Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hpms](index.html) module"] +#[doc = "High Priority Message Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpms::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HPMS_SPEC; impl crate::RegisterSpec for HPMS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hpms::R](R) reader structure"] -impl crate::Readable for HPMS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hpms::R`](R) reader structure"] +impl crate::Readable for HPMS_SPEC {} #[doc = "`reset()` method sets HPMS to value 0"] impl crate::Resettable for HPMS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ie.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ie.rs index f901e3c5..27f2304d 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ie.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ie.rs @@ -1,151 +1,119 @@ #[doc = "Register `IE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RF0NE` reader - Receive FIFO 0 New Message Interrupt Enable"] pub type RF0NE_R = crate::BitReader; #[doc = "Field `RF0NE` writer - Receive FIFO 0 New Message Interrupt Enable"] -pub type RF0NE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF0NE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0WE` reader - Receive FIFO 0 Watermark Reached Interrupt Enable"] pub type RF0WE_R = crate::BitReader; #[doc = "Field `RF0WE` writer - Receive FIFO 0 Watermark Reached Interrupt Enable"] -pub type RF0WE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF0WE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0FE` reader - Receive FIFO 0 Full Interrupt Enable"] pub type RF0FE_R = crate::BitReader; #[doc = "Field `RF0FE` writer - Receive FIFO 0 Full Interrupt Enable"] -pub type RF0FE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF0FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0LE` reader - Receive FIFO 0 Message Lost Interrupt Enable"] pub type RF0LE_R = crate::BitReader; #[doc = "Field `RF0LE` writer - Receive FIFO 0 Message Lost Interrupt Enable"] -pub type RF0LE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF0LE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1NE` reader - Receive FIFO 1 New Message Interrupt Enable"] pub type RF1NE_R = crate::BitReader; #[doc = "Field `RF1NE` writer - Receive FIFO 1 New Message Interrupt Enable"] -pub type RF1NE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF1NE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1WE` reader - Receive FIFO 1 Watermark Reached Interrupt Enable"] pub type RF1WE_R = crate::BitReader; #[doc = "Field `RF1WE` writer - Receive FIFO 1 Watermark Reached Interrupt Enable"] -pub type RF1WE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF1WE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1FE` reader - Receive FIFO 1 Full Interrupt Enable"] pub type RF1FE_R = crate::BitReader; #[doc = "Field `RF1FE` writer - Receive FIFO 1 Full Interrupt Enable"] -pub type RF1FE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF1FE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1LE` reader - Receive FIFO 1 Message Lost Interrupt Enable"] pub type RF1LE_R = crate::BitReader; #[doc = "Field `RF1LE` writer - Receive FIFO 1 Message Lost Interrupt Enable"] -pub type RF1LE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type RF1LE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HPME` reader - High Priority Message Interrupt Enable"] pub type HPME_R = crate::BitReader; #[doc = "Field `HPME` writer - High Priority Message Interrupt Enable"] -pub type HPME_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type HPME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCE` reader - Transmission Completed Interrupt Enable"] pub type TCE_R = crate::BitReader; #[doc = "Field `TCE` writer - Transmission Completed Interrupt Enable"] -pub type TCE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCFE` reader - Transmission Cancellation Finished Interrupt Enable"] pub type TCFE_R = crate::BitReader; #[doc = "Field `TCFE` writer - Transmission Cancellation Finished Interrupt Enable"] -pub type TCFE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TCFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFEE` reader - Tx FIFO Empty Interrupt Enable"] pub type TFEE_R = crate::BitReader; #[doc = "Field `TFEE` writer - Tx FIFO Empty Interrupt Enable"] -pub type TFEE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TFEE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFNE` reader - Tx Event FIFO New Entry Interrupt Enable"] pub type TEFNE_R = crate::BitReader; #[doc = "Field `TEFNE` writer - Tx Event FIFO New Entry Interrupt Enable"] -pub type TEFNE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TEFNE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFWE` reader - Tx Event FIFO Watermark Reached Interrupt Enable"] pub type TEFWE_R = crate::BitReader; #[doc = "Field `TEFWE` writer - Tx Event FIFO Watermark Reached Interrupt Enable"] -pub type TEFWE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TEFWE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFFE` reader - Tx Event FIFO Full Interrupt Enable"] pub type TEFFE_R = crate::BitReader; #[doc = "Field `TEFFE` writer - Tx Event FIFO Full Interrupt Enable"] -pub type TEFFE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TEFFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFLE` reader - Tx Event FIFO Event Lost Interrupt Enable"] pub type TEFLE_R = crate::BitReader; #[doc = "Field `TEFLE` writer - Tx Event FIFO Event Lost Interrupt Enable"] -pub type TEFLE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TEFLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSWE` reader - Timestamp Wraparound Interrupt Enable"] pub type TSWE_R = crate::BitReader; #[doc = "Field `TSWE` writer - Timestamp Wraparound Interrupt Enable"] -pub type TSWE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TSWE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MRAFE` reader - Message RAM Access Failure Interrupt Enable"] pub type MRAFE_R = crate::BitReader; #[doc = "Field `MRAFE` writer - Message RAM Access Failure Interrupt Enable"] -pub type MRAFE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type MRAFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOOE` reader - Timeout Occurred Interrupt Enable"] pub type TOOE_R = crate::BitReader; #[doc = "Field `TOOE` writer - Timeout Occurred Interrupt Enable"] -pub type TOOE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type TOOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRXE` reader - Message stored to Dedicated Receive Buffer Interrupt Enable"] pub type DRXE_R = crate::BitReader; #[doc = "Field `DRXE` writer - Message stored to Dedicated Receive Buffer Interrupt Enable"] -pub type DRXE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type DRXE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ELOE` reader - Error Logging Overflow Interrupt Enable"] pub type ELOE_R = crate::BitReader; #[doc = "Field `ELOE` writer - Error Logging Overflow Interrupt Enable"] -pub type ELOE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type ELOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPE` reader - Error Passive Interrupt Enable"] pub type EPE_R = crate::BitReader; #[doc = "Field `EPE` writer - Error Passive Interrupt Enable"] -pub type EPE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type EPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EWE` reader - Warning Status Interrupt Enable"] pub type EWE_R = crate::BitReader; #[doc = "Field `EWE` writer - Warning Status Interrupt Enable"] -pub type EWE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type EWE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOE` reader - Bus_Off Status Interrupt Enable"] pub type BOE_R = crate::BitReader; #[doc = "Field `BOE` writer - Bus_Off Status Interrupt Enable"] -pub type BOE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type BOE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDIE` reader - Watchdog Interrupt Enable"] pub type WDIE_R = crate::BitReader; #[doc = "Field `WDIE` writer - Watchdog Interrupt Enable"] -pub type WDIE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type WDIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEAE` reader - Protocol Error in Arbitration Phase Enable"] pub type PEAE_R = crate::BitReader; #[doc = "Field `PEAE` writer - Protocol Error in Arbitration Phase Enable"] -pub type PEAE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type PEAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEDE` reader - Protocol Error in Data Phase Enable"] pub type PEDE_R = crate::BitReader; #[doc = "Field `PEDE` writer - Protocol Error in Data Phase Enable"] -pub type PEDE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type PEDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARAE` reader - Access to Reserved Address Enable"] pub type ARAE_R = crate::BitReader; #[doc = "Field `ARAE` writer - Access to Reserved Address Enable"] -pub type ARAE_W<'a, const O: u8> = crate::BitWriter<'a, IE_SPEC, O>; +pub type ARAE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO 0 New Message Interrupt Enable"] #[inline(always)] @@ -292,190 +260,187 @@ impl W { #[doc = "Bit 0 - Receive FIFO 0 New Message Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf0ne(&mut self) -> RF0NE_W<0> { + pub fn rf0ne(&mut self) -> RF0NE_W { RF0NE_W::new(self) } #[doc = "Bit 1 - Receive FIFO 0 Watermark Reached Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf0we(&mut self) -> RF0WE_W<1> { + pub fn rf0we(&mut self) -> RF0WE_W { RF0WE_W::new(self) } #[doc = "Bit 2 - Receive FIFO 0 Full Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf0fe(&mut self) -> RF0FE_W<2> { + pub fn rf0fe(&mut self) -> RF0FE_W { RF0FE_W::new(self) } #[doc = "Bit 3 - Receive FIFO 0 Message Lost Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf0le(&mut self) -> RF0LE_W<3> { + pub fn rf0le(&mut self) -> RF0LE_W { RF0LE_W::new(self) } #[doc = "Bit 4 - Receive FIFO 1 New Message Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf1ne(&mut self) -> RF1NE_W<4> { + pub fn rf1ne(&mut self) -> RF1NE_W { RF1NE_W::new(self) } #[doc = "Bit 5 - Receive FIFO 1 Watermark Reached Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf1we(&mut self) -> RF1WE_W<5> { + pub fn rf1we(&mut self) -> RF1WE_W { RF1WE_W::new(self) } #[doc = "Bit 6 - Receive FIFO 1 Full Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf1fe(&mut self) -> RF1FE_W<6> { + pub fn rf1fe(&mut self) -> RF1FE_W { RF1FE_W::new(self) } #[doc = "Bit 7 - Receive FIFO 1 Message Lost Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rf1le(&mut self) -> RF1LE_W<7> { + pub fn rf1le(&mut self) -> RF1LE_W { RF1LE_W::new(self) } #[doc = "Bit 8 - High Priority Message Interrupt Enable"] #[inline(always)] #[must_use] - pub fn hpme(&mut self) -> HPME_W<8> { + pub fn hpme(&mut self) -> HPME_W { HPME_W::new(self) } #[doc = "Bit 9 - Transmission Completed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tce(&mut self) -> TCE_W<9> { + pub fn tce(&mut self) -> TCE_W { TCE_W::new(self) } #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tcfe(&mut self) -> TCFE_W<10> { + pub fn tcfe(&mut self) -> TCFE_W { TCFE_W::new(self) } #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tfee(&mut self) -> TFEE_W<11> { + pub fn tfee(&mut self) -> TFEE_W { TFEE_W::new(self) } #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tefne(&mut self) -> TEFNE_W<12> { + pub fn tefne(&mut self) -> TEFNE_W { TEFNE_W::new(self) } #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tefwe(&mut self) -> TEFWE_W<13> { + pub fn tefwe(&mut self) -> TEFWE_W { TEFWE_W::new(self) } #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"] #[inline(always)] #[must_use] - pub fn teffe(&mut self) -> TEFFE_W<14> { + pub fn teffe(&mut self) -> TEFFE_W { TEFFE_W::new(self) } #[doc = "Bit 15 - Tx Event FIFO Event Lost Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tefle(&mut self) -> TEFLE_W<15> { + pub fn tefle(&mut self) -> TEFLE_W { TEFLE_W::new(self) } #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tswe(&mut self) -> TSWE_W<16> { + pub fn tswe(&mut self) -> TSWE_W { TSWE_W::new(self) } #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"] #[inline(always)] #[must_use] - pub fn mrafe(&mut self) -> MRAFE_W<17> { + pub fn mrafe(&mut self) -> MRAFE_W { MRAFE_W::new(self) } #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tooe(&mut self) -> TOOE_W<18> { + pub fn tooe(&mut self) -> TOOE_W { TOOE_W::new(self) } #[doc = "Bit 19 - Message stored to Dedicated Receive Buffer Interrupt Enable"] #[inline(always)] #[must_use] - pub fn drxe(&mut self) -> DRXE_W<19> { + pub fn drxe(&mut self) -> DRXE_W { DRXE_W::new(self) } #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn eloe(&mut self) -> ELOE_W<22> { + pub fn eloe(&mut self) -> ELOE_W { ELOE_W::new(self) } #[doc = "Bit 23 - Error Passive Interrupt Enable"] #[inline(always)] #[must_use] - pub fn epe(&mut self) -> EPE_W<23> { + pub fn epe(&mut self) -> EPE_W { EPE_W::new(self) } #[doc = "Bit 24 - Warning Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ewe(&mut self) -> EWE_W<24> { + pub fn ewe(&mut self) -> EWE_W { EWE_W::new(self) } #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn boe(&mut self) -> BOE_W<25> { + pub fn boe(&mut self) -> BOE_W { BOE_W::new(self) } #[doc = "Bit 26 - Watchdog Interrupt Enable"] #[inline(always)] #[must_use] - pub fn wdie(&mut self) -> WDIE_W<26> { + pub fn wdie(&mut self) -> WDIE_W { WDIE_W::new(self) } #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"] #[inline(always)] #[must_use] - pub fn peae(&mut self) -> PEAE_W<27> { + pub fn peae(&mut self) -> PEAE_W { PEAE_W::new(self) } #[doc = "Bit 28 - Protocol Error in Data Phase Enable"] #[inline(always)] #[must_use] - pub fn pede(&mut self) -> PEDE_W<28> { + pub fn pede(&mut self) -> PEDE_W { PEDE_W::new(self) } #[doc = "Bit 29 - Access to Reserved Address Enable"] #[inline(always)] #[must_use] - pub fn arae(&mut self) -> ARAE_W<29> { + pub fn arae(&mut self) -> ARAE_W { ARAE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ie](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IE_SPEC; impl crate::RegisterSpec for IE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ie::R](R) reader structure"] -impl crate::Readable for IE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ie::W](W) writer structure"] +#[doc = "`read()` method returns [`ie::R`](R) reader structure"] +impl crate::Readable for IE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"] impl crate::Writable for IE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ile.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ile.rs index 3d11faf0..01d2504d 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ile.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ile.rs @@ -1,47 +1,15 @@ #[doc = "Register `ILE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ILE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EINT0` reader - Enable Interrupt Line 0"] pub type EINT0_R = crate::BitReader; #[doc = "Field `EINT0` writer - Enable Interrupt Line 0"] -pub type EINT0_W<'a, const O: u8> = crate::BitWriter<'a, ILE_SPEC, O>; +pub type EINT0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EINT1` reader - Enable Interrupt Line 1"] pub type EINT1_R = crate::BitReader; #[doc = "Field `EINT1` writer - Enable Interrupt Line 1"] -pub type EINT1_W<'a, const O: u8> = crate::BitWriter<'a, ILE_SPEC, O>; +pub type EINT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable Interrupt Line 0"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 0 - Enable Interrupt Line 0"] #[inline(always)] #[must_use] - pub fn eint0(&mut self) -> EINT0_W<0> { + pub fn eint0(&mut self) -> EINT0_W { EINT0_W::new(self) } #[doc = "Bit 1 - Enable Interrupt Line 1"] #[inline(always)] #[must_use] - pub fn eint1(&mut self) -> EINT1_W<1> { + pub fn eint1(&mut self) -> EINT1_W { EINT1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Line Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ile](index.html) module"] +#[doc = "Interrupt Line Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ile::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ile::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ILE_SPEC; impl crate::RegisterSpec for ILE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ile::R](R) reader structure"] -impl crate::Readable for ILE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ile::W](W) writer structure"] +#[doc = "`read()` method returns [`ile::R`](R) reader structure"] +impl crate::Readable for ILE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ile::W`](W) writer structure"] impl crate::Writable for ILE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ils.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ils.rs index 89d8f499..4746768e 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ils.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ils.rs @@ -1,151 +1,119 @@ #[doc = "Register `ILS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ILS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RF0NL` reader - Receive FIFO 0 New Message Interrupt Line"] pub type RF0NL_R = crate::BitReader; #[doc = "Field `RF0NL` writer - Receive FIFO 0 New Message Interrupt Line"] -pub type RF0NL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF0NL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0WL` reader - Receive FIFO 0 Watermark Reached Interrupt Line"] pub type RF0WL_R = crate::BitReader; #[doc = "Field `RF0WL` writer - Receive FIFO 0 Watermark Reached Interrupt Line"] -pub type RF0WL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF0WL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0FL` reader - Receive FIFO 0 Full Interrupt Line"] pub type RF0FL_R = crate::BitReader; #[doc = "Field `RF0FL` writer - Receive FIFO 0 Full Interrupt Line"] -pub type RF0FL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF0FL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0LL` reader - Receive FIFO 0 Message Lost Interrupt Line"] pub type RF0LL_R = crate::BitReader; #[doc = "Field `RF0LL` writer - Receive FIFO 0 Message Lost Interrupt Line"] -pub type RF0LL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF0LL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1NL` reader - Receive FIFO 1 New Message Interrupt Line"] pub type RF1NL_R = crate::BitReader; #[doc = "Field `RF1NL` writer - Receive FIFO 1 New Message Interrupt Line"] -pub type RF1NL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF1NL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1WL` reader - Receive FIFO 1 Watermark Reached Interrupt Line"] pub type RF1WL_R = crate::BitReader; #[doc = "Field `RF1WL` writer - Receive FIFO 1 Watermark Reached Interrupt Line"] -pub type RF1WL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF1WL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1FL` reader - Receive FIFO 1 Full Interrupt Line"] pub type RF1FL_R = crate::BitReader; #[doc = "Field `RF1FL` writer - Receive FIFO 1 Full Interrupt Line"] -pub type RF1FL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF1FL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1LL` reader - Receive FIFO 1 Message Lost Interrupt Line"] pub type RF1LL_R = crate::BitReader; #[doc = "Field `RF1LL` writer - Receive FIFO 1 Message Lost Interrupt Line"] -pub type RF1LL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type RF1LL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HPML` reader - High Priority Message Interrupt Line"] pub type HPML_R = crate::BitReader; #[doc = "Field `HPML` writer - High Priority Message Interrupt Line"] -pub type HPML_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type HPML_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCL` reader - Transmission Completed Interrupt Line"] pub type TCL_R = crate::BitReader; #[doc = "Field `TCL` writer - Transmission Completed Interrupt Line"] -pub type TCL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TCL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCFL` reader - Transmission Cancellation Finished Interrupt Line"] pub type TCFL_R = crate::BitReader; #[doc = "Field `TCFL` writer - Transmission Cancellation Finished Interrupt Line"] -pub type TCFL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TCFL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFEL` reader - Tx FIFO Empty Interrupt Line"] pub type TFEL_R = crate::BitReader; #[doc = "Field `TFEL` writer - Tx FIFO Empty Interrupt Line"] -pub type TFEL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TFEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFNL` reader - Tx Event FIFO New Entry Interrupt Line"] pub type TEFNL_R = crate::BitReader; #[doc = "Field `TEFNL` writer - Tx Event FIFO New Entry Interrupt Line"] -pub type TEFNL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TEFNL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFWL` reader - Tx Event FIFO Watermark Reached Interrupt Line"] pub type TEFWL_R = crate::BitReader; #[doc = "Field `TEFWL` writer - Tx Event FIFO Watermark Reached Interrupt Line"] -pub type TEFWL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TEFWL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFFL` reader - Tx Event FIFO Full Interrupt Line"] pub type TEFFL_R = crate::BitReader; #[doc = "Field `TEFFL` writer - Tx Event FIFO Full Interrupt Line"] -pub type TEFFL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TEFFL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFLL` reader - Tx Event FIFO Event Lost Interrupt Line"] pub type TEFLL_R = crate::BitReader; #[doc = "Field `TEFLL` writer - Tx Event FIFO Event Lost Interrupt Line"] -pub type TEFLL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TEFLL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSWL` reader - Timestamp Wraparound Interrupt Line"] pub type TSWL_R = crate::BitReader; #[doc = "Field `TSWL` writer - Timestamp Wraparound Interrupt Line"] -pub type TSWL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TSWL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MRAFL` reader - Message RAM Access Failure Interrupt Line"] pub type MRAFL_R = crate::BitReader; #[doc = "Field `MRAFL` writer - Message RAM Access Failure Interrupt Line"] -pub type MRAFL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type MRAFL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOOL` reader - Timeout Occurred Interrupt Line"] pub type TOOL_R = crate::BitReader; #[doc = "Field `TOOL` writer - Timeout Occurred Interrupt Line"] -pub type TOOL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type TOOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRXL` reader - Message stored to Dedicated Receive Buffer Interrupt Line"] pub type DRXL_R = crate::BitReader; #[doc = "Field `DRXL` writer - Message stored to Dedicated Receive Buffer Interrupt Line"] -pub type DRXL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type DRXL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ELOL` reader - Error Logging Overflow Interrupt Line"] pub type ELOL_R = crate::BitReader; #[doc = "Field `ELOL` writer - Error Logging Overflow Interrupt Line"] -pub type ELOL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type ELOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPL` reader - Error Passive Interrupt Line"] pub type EPL_R = crate::BitReader; #[doc = "Field `EPL` writer - Error Passive Interrupt Line"] -pub type EPL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type EPL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EWL` reader - Warning Status Interrupt Line"] pub type EWL_R = crate::BitReader; #[doc = "Field `EWL` writer - Warning Status Interrupt Line"] -pub type EWL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type EWL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BOL` reader - Bus_Off Status Interrupt Line"] pub type BOL_R = crate::BitReader; #[doc = "Field `BOL` writer - Bus_Off Status Interrupt Line"] -pub type BOL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type BOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDIL` reader - Watchdog Interrupt Line"] pub type WDIL_R = crate::BitReader; #[doc = "Field `WDIL` writer - Watchdog Interrupt Line"] -pub type WDIL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type WDIL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEAL` reader - Protocol Error in Arbitration Phase Line"] pub type PEAL_R = crate::BitReader; #[doc = "Field `PEAL` writer - Protocol Error in Arbitration Phase Line"] -pub type PEAL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type PEAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEDL` reader - Protocol Error in Data Phase Line"] pub type PEDL_R = crate::BitReader; #[doc = "Field `PEDL` writer - Protocol Error in Data Phase Line"] -pub type PEDL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type PEDL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARAL` reader - Access to Reserved Address Line"] pub type ARAL_R = crate::BitReader; #[doc = "Field `ARAL` writer - Access to Reserved Address Line"] -pub type ARAL_W<'a, const O: u8> = crate::BitWriter<'a, ILS_SPEC, O>; +pub type ARAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO 0 New Message Interrupt Line"] #[inline(always)] @@ -292,190 +260,187 @@ impl W { #[doc = "Bit 0 - Receive FIFO 0 New Message Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf0nl(&mut self) -> RF0NL_W<0> { + pub fn rf0nl(&mut self) -> RF0NL_W { RF0NL_W::new(self) } #[doc = "Bit 1 - Receive FIFO 0 Watermark Reached Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf0wl(&mut self) -> RF0WL_W<1> { + pub fn rf0wl(&mut self) -> RF0WL_W { RF0WL_W::new(self) } #[doc = "Bit 2 - Receive FIFO 0 Full Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf0fl(&mut self) -> RF0FL_W<2> { + pub fn rf0fl(&mut self) -> RF0FL_W { RF0FL_W::new(self) } #[doc = "Bit 3 - Receive FIFO 0 Message Lost Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf0ll(&mut self) -> RF0LL_W<3> { + pub fn rf0ll(&mut self) -> RF0LL_W { RF0LL_W::new(self) } #[doc = "Bit 4 - Receive FIFO 1 New Message Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf1nl(&mut self) -> RF1NL_W<4> { + pub fn rf1nl(&mut self) -> RF1NL_W { RF1NL_W::new(self) } #[doc = "Bit 5 - Receive FIFO 1 Watermark Reached Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf1wl(&mut self) -> RF1WL_W<5> { + pub fn rf1wl(&mut self) -> RF1WL_W { RF1WL_W::new(self) } #[doc = "Bit 6 - Receive FIFO 1 Full Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf1fl(&mut self) -> RF1FL_W<6> { + pub fn rf1fl(&mut self) -> RF1FL_W { RF1FL_W::new(self) } #[doc = "Bit 7 - Receive FIFO 1 Message Lost Interrupt Line"] #[inline(always)] #[must_use] - pub fn rf1ll(&mut self) -> RF1LL_W<7> { + pub fn rf1ll(&mut self) -> RF1LL_W { RF1LL_W::new(self) } #[doc = "Bit 8 - High Priority Message Interrupt Line"] #[inline(always)] #[must_use] - pub fn hpml(&mut self) -> HPML_W<8> { + pub fn hpml(&mut self) -> HPML_W { HPML_W::new(self) } #[doc = "Bit 9 - Transmission Completed Interrupt Line"] #[inline(always)] #[must_use] - pub fn tcl(&mut self) -> TCL_W<9> { + pub fn tcl(&mut self) -> TCL_W { TCL_W::new(self) } #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"] #[inline(always)] #[must_use] - pub fn tcfl(&mut self) -> TCFL_W<10> { + pub fn tcfl(&mut self) -> TCFL_W { TCFL_W::new(self) } #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"] #[inline(always)] #[must_use] - pub fn tfel(&mut self) -> TFEL_W<11> { + pub fn tfel(&mut self) -> TFEL_W { TFEL_W::new(self) } #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"] #[inline(always)] #[must_use] - pub fn tefnl(&mut self) -> TEFNL_W<12> { + pub fn tefnl(&mut self) -> TEFNL_W { TEFNL_W::new(self) } #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"] #[inline(always)] #[must_use] - pub fn tefwl(&mut self) -> TEFWL_W<13> { + pub fn tefwl(&mut self) -> TEFWL_W { TEFWL_W::new(self) } #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"] #[inline(always)] #[must_use] - pub fn teffl(&mut self) -> TEFFL_W<14> { + pub fn teffl(&mut self) -> TEFFL_W { TEFFL_W::new(self) } #[doc = "Bit 15 - Tx Event FIFO Event Lost Interrupt Line"] #[inline(always)] #[must_use] - pub fn tefll(&mut self) -> TEFLL_W<15> { + pub fn tefll(&mut self) -> TEFLL_W { TEFLL_W::new(self) } #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"] #[inline(always)] #[must_use] - pub fn tswl(&mut self) -> TSWL_W<16> { + pub fn tswl(&mut self) -> TSWL_W { TSWL_W::new(self) } #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"] #[inline(always)] #[must_use] - pub fn mrafl(&mut self) -> MRAFL_W<17> { + pub fn mrafl(&mut self) -> MRAFL_W { MRAFL_W::new(self) } #[doc = "Bit 18 - Timeout Occurred Interrupt Line"] #[inline(always)] #[must_use] - pub fn tool(&mut self) -> TOOL_W<18> { + pub fn tool(&mut self) -> TOOL_W { TOOL_W::new(self) } #[doc = "Bit 19 - Message stored to Dedicated Receive Buffer Interrupt Line"] #[inline(always)] #[must_use] - pub fn drxl(&mut self) -> DRXL_W<19> { + pub fn drxl(&mut self) -> DRXL_W { DRXL_W::new(self) } #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"] #[inline(always)] #[must_use] - pub fn elol(&mut self) -> ELOL_W<22> { + pub fn elol(&mut self) -> ELOL_W { ELOL_W::new(self) } #[doc = "Bit 23 - Error Passive Interrupt Line"] #[inline(always)] #[must_use] - pub fn epl(&mut self) -> EPL_W<23> { + pub fn epl(&mut self) -> EPL_W { EPL_W::new(self) } #[doc = "Bit 24 - Warning Status Interrupt Line"] #[inline(always)] #[must_use] - pub fn ewl(&mut self) -> EWL_W<24> { + pub fn ewl(&mut self) -> EWL_W { EWL_W::new(self) } #[doc = "Bit 25 - Bus_Off Status Interrupt Line"] #[inline(always)] #[must_use] - pub fn bol(&mut self) -> BOL_W<25> { + pub fn bol(&mut self) -> BOL_W { BOL_W::new(self) } #[doc = "Bit 26 - Watchdog Interrupt Line"] #[inline(always)] #[must_use] - pub fn wdil(&mut self) -> WDIL_W<26> { + pub fn wdil(&mut self) -> WDIL_W { WDIL_W::new(self) } #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"] #[inline(always)] #[must_use] - pub fn peal(&mut self) -> PEAL_W<27> { + pub fn peal(&mut self) -> PEAL_W { PEAL_W::new(self) } #[doc = "Bit 28 - Protocol Error in Data Phase Line"] #[inline(always)] #[must_use] - pub fn pedl(&mut self) -> PEDL_W<28> { + pub fn pedl(&mut self) -> PEDL_W { PEDL_W::new(self) } #[doc = "Bit 29 - Access to Reserved Address Line"] #[inline(always)] #[must_use] - pub fn aral(&mut self) -> ARAL_W<29> { + pub fn aral(&mut self) -> ARAL_W { ARAL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Line Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ils](index.html) module"] +#[doc = "Interrupt Line Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ils::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ils::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ILS_SPEC; impl crate::RegisterSpec for ILS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ils::R](R) reader structure"] -impl crate::Readable for ILS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ils::W](W) writer structure"] +#[doc = "`read()` method returns [`ils::R`](R) reader structure"] +impl crate::Readable for ILS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ils::W`](W) writer structure"] impl crate::Writable for ILS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ir.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ir.rs index 3de2a360..12c84cc2 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ir.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ir.rs @@ -1,151 +1,119 @@ #[doc = "Register `IR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RF0N` reader - Receive FIFO 0 New Message"] pub type RF0N_R = crate::BitReader; #[doc = "Field `RF0N` writer - Receive FIFO 0 New Message"] -pub type RF0N_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF0N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0W` reader - Receive FIFO 0 Watermark Reached"] pub type RF0W_R = crate::BitReader; #[doc = "Field `RF0W` writer - Receive FIFO 0 Watermark Reached"] -pub type RF0W_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF0W_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0F` reader - Receive FIFO 0 Full"] pub type RF0F_R = crate::BitReader; #[doc = "Field `RF0F` writer - Receive FIFO 0 Full"] -pub type RF0F_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF0F_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF0L` reader - Receive FIFO 0 Message Lost"] pub type RF0L_R = crate::BitReader; #[doc = "Field `RF0L` writer - Receive FIFO 0 Message Lost"] -pub type RF0L_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF0L_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1N` reader - Receive FIFO 1 New Message"] pub type RF1N_R = crate::BitReader; #[doc = "Field `RF1N` writer - Receive FIFO 1 New Message"] -pub type RF1N_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF1N_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1W` reader - Receive FIFO 1 Watermark Reached"] pub type RF1W_R = crate::BitReader; #[doc = "Field `RF1W` writer - Receive FIFO 1 Watermark Reached"] -pub type RF1W_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF1W_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1F` reader - Receive FIFO 1 Full"] pub type RF1F_R = crate::BitReader; #[doc = "Field `RF1F` writer - Receive FIFO 1 Full"] -pub type RF1F_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF1F_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RF1L` reader - Receive FIFO 1 Message Lost"] pub type RF1L_R = crate::BitReader; #[doc = "Field `RF1L` writer - Receive FIFO 1 Message Lost"] -pub type RF1L_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type RF1L_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HPM` reader - High Priority Message"] pub type HPM_R = crate::BitReader; #[doc = "Field `HPM` writer - High Priority Message"] -pub type HPM_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type HPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TC` reader - Transmission Completed"] pub type TC_R = crate::BitReader; #[doc = "Field `TC` writer - Transmission Completed"] -pub type TC_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCF` reader - Transmission Cancellation Finished"] pub type TCF_R = crate::BitReader; #[doc = "Field `TCF` writer - Transmission Cancellation Finished"] -pub type TCF_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TCF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TFE` reader - Tx FIFO Empty"] pub type TFE_R = crate::BitReader; #[doc = "Field `TFE` writer - Tx FIFO Empty"] -pub type TFE_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFN` reader - Tx Event FIFO New Entry"] pub type TEFN_R = crate::BitReader; #[doc = "Field `TEFN` writer - Tx Event FIFO New Entry"] -pub type TEFN_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TEFN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached"] pub type TEFW_R = crate::BitReader; #[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached"] -pub type TEFW_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TEFW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFF` reader - Tx Event FIFO Full"] pub type TEFF_R = crate::BitReader; #[doc = "Field `TEFF` writer - Tx Event FIFO Full"] -pub type TEFF_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TEFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost"] pub type TEFL_R = crate::BitReader; #[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost"] -pub type TEFL_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TEFL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSW` reader - Timestamp Wraparound"] pub type TSW_R = crate::BitReader; #[doc = "Field `TSW` writer - Timestamp Wraparound"] -pub type TSW_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TSW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MRAF` reader - Message RAM Access Failure"] pub type MRAF_R = crate::BitReader; #[doc = "Field `MRAF` writer - Message RAM Access Failure"] -pub type MRAF_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type MRAF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOO` reader - Timeout Occurred"] pub type TOO_R = crate::BitReader; #[doc = "Field `TOO` writer - Timeout Occurred"] -pub type TOO_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type TOO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRX` reader - Message stored to Dedicated Receive Buffer"] pub type DRX_R = crate::BitReader; #[doc = "Field `DRX` writer - Message stored to Dedicated Receive Buffer"] -pub type DRX_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type DRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ELO` reader - Error Logging Overflow"] pub type ELO_R = crate::BitReader; #[doc = "Field `ELO` writer - Error Logging Overflow"] -pub type ELO_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type ELO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EP` reader - Error Passive"] pub type EP_R = crate::BitReader; #[doc = "Field `EP` writer - Error Passive"] -pub type EP_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type EP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EW` reader - Warning Status"] pub type EW_R = crate::BitReader; #[doc = "Field `EW` writer - Warning Status"] -pub type EW_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type EW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BO` reader - Bus_Off Status"] pub type BO_R = crate::BitReader; #[doc = "Field `BO` writer - Bus_Off Status"] -pub type BO_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type BO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDI` reader - Watchdog Interrupt"] pub type WDI_R = crate::BitReader; #[doc = "Field `WDI` writer - Watchdog Interrupt"] -pub type WDI_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type WDI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase"] pub type PEA_R = crate::BitReader; #[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase"] -pub type PEA_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type PEA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PED` reader - Protocol Error in Data Phase"] pub type PED_R = crate::BitReader; #[doc = "Field `PED` writer - Protocol Error in Data Phase"] -pub type PED_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type PED_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARA` reader - Access to Reserved Address"] pub type ARA_R = crate::BitReader; #[doc = "Field `ARA` writer - Access to Reserved Address"] -pub type ARA_W<'a, const O: u8> = crate::BitWriter<'a, IR_SPEC, O>; +pub type ARA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Receive FIFO 0 New Message"] #[inline(always)] @@ -292,190 +260,187 @@ impl W { #[doc = "Bit 0 - Receive FIFO 0 New Message"] #[inline(always)] #[must_use] - pub fn rf0n(&mut self) -> RF0N_W<0> { + pub fn rf0n(&mut self) -> RF0N_W { RF0N_W::new(self) } #[doc = "Bit 1 - Receive FIFO 0 Watermark Reached"] #[inline(always)] #[must_use] - pub fn rf0w(&mut self) -> RF0W_W<1> { + pub fn rf0w(&mut self) -> RF0W_W { RF0W_W::new(self) } #[doc = "Bit 2 - Receive FIFO 0 Full"] #[inline(always)] #[must_use] - pub fn rf0f(&mut self) -> RF0F_W<2> { + pub fn rf0f(&mut self) -> RF0F_W { RF0F_W::new(self) } #[doc = "Bit 3 - Receive FIFO 0 Message Lost"] #[inline(always)] #[must_use] - pub fn rf0l(&mut self) -> RF0L_W<3> { + pub fn rf0l(&mut self) -> RF0L_W { RF0L_W::new(self) } #[doc = "Bit 4 - Receive FIFO 1 New Message"] #[inline(always)] #[must_use] - pub fn rf1n(&mut self) -> RF1N_W<4> { + pub fn rf1n(&mut self) -> RF1N_W { RF1N_W::new(self) } #[doc = "Bit 5 - Receive FIFO 1 Watermark Reached"] #[inline(always)] #[must_use] - pub fn rf1w(&mut self) -> RF1W_W<5> { + pub fn rf1w(&mut self) -> RF1W_W { RF1W_W::new(self) } #[doc = "Bit 6 - Receive FIFO 1 Full"] #[inline(always)] #[must_use] - pub fn rf1f(&mut self) -> RF1F_W<6> { + pub fn rf1f(&mut self) -> RF1F_W { RF1F_W::new(self) } #[doc = "Bit 7 - Receive FIFO 1 Message Lost"] #[inline(always)] #[must_use] - pub fn rf1l(&mut self) -> RF1L_W<7> { + pub fn rf1l(&mut self) -> RF1L_W { RF1L_W::new(self) } #[doc = "Bit 8 - High Priority Message"] #[inline(always)] #[must_use] - pub fn hpm(&mut self) -> HPM_W<8> { + pub fn hpm(&mut self) -> HPM_W { HPM_W::new(self) } #[doc = "Bit 9 - Transmission Completed"] #[inline(always)] #[must_use] - pub fn tc(&mut self) -> TC_W<9> { + pub fn tc(&mut self) -> TC_W { TC_W::new(self) } #[doc = "Bit 10 - Transmission Cancellation Finished"] #[inline(always)] #[must_use] - pub fn tcf(&mut self) -> TCF_W<10> { + pub fn tcf(&mut self) -> TCF_W { TCF_W::new(self) } #[doc = "Bit 11 - Tx FIFO Empty"] #[inline(always)] #[must_use] - pub fn tfe(&mut self) -> TFE_W<11> { + pub fn tfe(&mut self) -> TFE_W { TFE_W::new(self) } #[doc = "Bit 12 - Tx Event FIFO New Entry"] #[inline(always)] #[must_use] - pub fn tefn(&mut self) -> TEFN_W<12> { + pub fn tefn(&mut self) -> TEFN_W { TEFN_W::new(self) } #[doc = "Bit 13 - Tx Event FIFO Watermark Reached"] #[inline(always)] #[must_use] - pub fn tefw(&mut self) -> TEFW_W<13> { + pub fn tefw(&mut self) -> TEFW_W { TEFW_W::new(self) } #[doc = "Bit 14 - Tx Event FIFO Full"] #[inline(always)] #[must_use] - pub fn teff(&mut self) -> TEFF_W<14> { + pub fn teff(&mut self) -> TEFF_W { TEFF_W::new(self) } #[doc = "Bit 15 - Tx Event FIFO Element Lost"] #[inline(always)] #[must_use] - pub fn tefl(&mut self) -> TEFL_W<15> { + pub fn tefl(&mut self) -> TEFL_W { TEFL_W::new(self) } #[doc = "Bit 16 - Timestamp Wraparound"] #[inline(always)] #[must_use] - pub fn tsw(&mut self) -> TSW_W<16> { + pub fn tsw(&mut self) -> TSW_W { TSW_W::new(self) } #[doc = "Bit 17 - Message RAM Access Failure"] #[inline(always)] #[must_use] - pub fn mraf(&mut self) -> MRAF_W<17> { + pub fn mraf(&mut self) -> MRAF_W { MRAF_W::new(self) } #[doc = "Bit 18 - Timeout Occurred"] #[inline(always)] #[must_use] - pub fn too(&mut self) -> TOO_W<18> { + pub fn too(&mut self) -> TOO_W { TOO_W::new(self) } #[doc = "Bit 19 - Message stored to Dedicated Receive Buffer"] #[inline(always)] #[must_use] - pub fn drx(&mut self) -> DRX_W<19> { + pub fn drx(&mut self) -> DRX_W { DRX_W::new(self) } #[doc = "Bit 22 - Error Logging Overflow"] #[inline(always)] #[must_use] - pub fn elo(&mut self) -> ELO_W<22> { + pub fn elo(&mut self) -> ELO_W { ELO_W::new(self) } #[doc = "Bit 23 - Error Passive"] #[inline(always)] #[must_use] - pub fn ep(&mut self) -> EP_W<23> { + pub fn ep(&mut self) -> EP_W { EP_W::new(self) } #[doc = "Bit 24 - Warning Status"] #[inline(always)] #[must_use] - pub fn ew(&mut self) -> EW_W<24> { + pub fn ew(&mut self) -> EW_W { EW_W::new(self) } #[doc = "Bit 25 - Bus_Off Status"] #[inline(always)] #[must_use] - pub fn bo(&mut self) -> BO_W<25> { + pub fn bo(&mut self) -> BO_W { BO_W::new(self) } #[doc = "Bit 26 - Watchdog Interrupt"] #[inline(always)] #[must_use] - pub fn wdi(&mut self) -> WDI_W<26> { + pub fn wdi(&mut self) -> WDI_W { WDI_W::new(self) } #[doc = "Bit 27 - Protocol Error in Arbitration Phase"] #[inline(always)] #[must_use] - pub fn pea(&mut self) -> PEA_W<27> { + pub fn pea(&mut self) -> PEA_W { PEA_W::new(self) } #[doc = "Bit 28 - Protocol Error in Data Phase"] #[inline(always)] #[must_use] - pub fn ped(&mut self) -> PED_W<28> { + pub fn ped(&mut self) -> PED_W { PED_W::new(self) } #[doc = "Bit 29 - Access to Reserved Address"] #[inline(always)] #[must_use] - pub fn ara(&mut self) -> ARA_W<29> { + pub fn ara(&mut self) -> ARA_W { ARA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ir](index.html) module"] +#[doc = "Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IR_SPEC; impl crate::RegisterSpec for IR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ir::R](R) reader structure"] -impl crate::Readable for IR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ir::W](W) writer structure"] +#[doc = "`read()` method returns [`ir::R`](R) reader structure"] +impl crate::Readable for IR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"] impl crate::Writable for IR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/nbtp.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/nbtp.rs index 8e78bf95..3e18afd3 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/nbtp.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/nbtp.rs @@ -1,55 +1,23 @@ #[doc = "Register `NBTP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NBTP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NTSEG2` reader - Nominal Time Segment After Sample Point"] pub type NTSEG2_R = crate::FieldReader; #[doc = "Field `NTSEG2` writer - Nominal Time Segment After Sample Point"] -pub type NTSEG2_W<'a, const O: u8> = crate::FieldWriter<'a, NBTP_SPEC, 7, O>; +pub type NTSEG2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `NTSEG1` reader - Nominal Time Segment Before Sample Point"] pub type NTSEG1_R = crate::FieldReader; #[doc = "Field `NTSEG1` writer - Nominal Time Segment Before Sample Point"] -pub type NTSEG1_W<'a, const O: u8> = crate::FieldWriter<'a, NBTP_SPEC, 8, O>; +pub type NTSEG1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `NBRP` reader - Nominal Bit Rate Prescaler"] pub type NBRP_R = crate::FieldReader; #[doc = "Field `NBRP` writer - Nominal Bit Rate Prescaler"] -pub type NBRP_W<'a, const O: u8> = crate::FieldWriter<'a, NBTP_SPEC, 9, O, u16>; +pub type NBRP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `NSJW` reader - Nominal (Re) Synchronization Jump Width"] pub type NSJW_R = crate::FieldReader; #[doc = "Field `NSJW` writer - Nominal (Re) Synchronization Jump Width"] -pub type NSJW_W<'a, const O: u8> = crate::FieldWriter<'a, NBTP_SPEC, 7, O>; +pub type NSJW_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - Nominal Time Segment After Sample Point"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - Nominal Time Segment After Sample Point"] #[inline(always)] #[must_use] - pub fn ntseg2(&mut self) -> NTSEG2_W<0> { + pub fn ntseg2(&mut self) -> NTSEG2_W { NTSEG2_W::new(self) } #[doc = "Bits 8:15 - Nominal Time Segment Before Sample Point"] #[inline(always)] #[must_use] - pub fn ntseg1(&mut self) -> NTSEG1_W<8> { + pub fn ntseg1(&mut self) -> NTSEG1_W { NTSEG1_W::new(self) } #[doc = "Bits 16:24 - Nominal Bit Rate Prescaler"] #[inline(always)] #[must_use] - pub fn nbrp(&mut self) -> NBRP_W<16> { + pub fn nbrp(&mut self) -> NBRP_W { NBRP_W::new(self) } #[doc = "Bits 25:31 - Nominal (Re) Synchronization Jump Width"] #[inline(always)] #[must_use] - pub fn nsjw(&mut self) -> NSJW_W<25> { + pub fn nsjw(&mut self) -> NSJW_W { NSJW_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Nominal Bit Timing and Prescaler Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nbtp](index.html) module"] +#[doc = "Nominal Bit Timing and Prescaler Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nbtp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nbtp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NBTP_SPEC; impl crate::RegisterSpec for NBTP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [nbtp::R](R) reader structure"] -impl crate::Readable for NBTP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [nbtp::W](W) writer structure"] +#[doc = "`read()` method returns [`nbtp::R`](R) reader structure"] +impl crate::Readable for NBTP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nbtp::W`](W) writer structure"] impl crate::Writable for NBTP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ndat1.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ndat1.rs index 28677e88..dac5652d 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ndat1.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ndat1.rs @@ -1,167 +1,135 @@ #[doc = "Register `NDAT1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NDAT1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ND0` reader - New Data"] pub type ND0_R = crate::BitReader; #[doc = "Field `ND0` writer - New Data"] -pub type ND0_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND1` reader - New Data"] pub type ND1_R = crate::BitReader; #[doc = "Field `ND1` writer - New Data"] -pub type ND1_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND2` reader - New Data"] pub type ND2_R = crate::BitReader; #[doc = "Field `ND2` writer - New Data"] -pub type ND2_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND3` reader - New Data"] pub type ND3_R = crate::BitReader; #[doc = "Field `ND3` writer - New Data"] -pub type ND3_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND4` reader - New Data"] pub type ND4_R = crate::BitReader; #[doc = "Field `ND4` writer - New Data"] -pub type ND4_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND5` reader - New Data"] pub type ND5_R = crate::BitReader; #[doc = "Field `ND5` writer - New Data"] -pub type ND5_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND6` reader - New Data"] pub type ND6_R = crate::BitReader; #[doc = "Field `ND6` writer - New Data"] -pub type ND6_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND7` reader - New Data"] pub type ND7_R = crate::BitReader; #[doc = "Field `ND7` writer - New Data"] -pub type ND7_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND8` reader - New Data"] pub type ND8_R = crate::BitReader; #[doc = "Field `ND8` writer - New Data"] -pub type ND8_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND9` reader - New Data"] pub type ND9_R = crate::BitReader; #[doc = "Field `ND9` writer - New Data"] -pub type ND9_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND10` reader - New Data"] pub type ND10_R = crate::BitReader; #[doc = "Field `ND10` writer - New Data"] -pub type ND10_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND11` reader - New Data"] pub type ND11_R = crate::BitReader; #[doc = "Field `ND11` writer - New Data"] -pub type ND11_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND12` reader - New Data"] pub type ND12_R = crate::BitReader; #[doc = "Field `ND12` writer - New Data"] -pub type ND12_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND13` reader - New Data"] pub type ND13_R = crate::BitReader; #[doc = "Field `ND13` writer - New Data"] -pub type ND13_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND14` reader - New Data"] pub type ND14_R = crate::BitReader; #[doc = "Field `ND14` writer - New Data"] -pub type ND14_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND15` reader - New Data"] pub type ND15_R = crate::BitReader; #[doc = "Field `ND15` writer - New Data"] -pub type ND15_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND16` reader - New Data"] pub type ND16_R = crate::BitReader; #[doc = "Field `ND16` writer - New Data"] -pub type ND16_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND17` reader - New Data"] pub type ND17_R = crate::BitReader; #[doc = "Field `ND17` writer - New Data"] -pub type ND17_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND18` reader - New Data"] pub type ND18_R = crate::BitReader; #[doc = "Field `ND18` writer - New Data"] -pub type ND18_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND19` reader - New Data"] pub type ND19_R = crate::BitReader; #[doc = "Field `ND19` writer - New Data"] -pub type ND19_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND20` reader - New Data"] pub type ND20_R = crate::BitReader; #[doc = "Field `ND20` writer - New Data"] -pub type ND20_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND21` reader - New Data"] pub type ND21_R = crate::BitReader; #[doc = "Field `ND21` writer - New Data"] -pub type ND21_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND22` reader - New Data"] pub type ND22_R = crate::BitReader; #[doc = "Field `ND22` writer - New Data"] -pub type ND22_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND23` reader - New Data"] pub type ND23_R = crate::BitReader; #[doc = "Field `ND23` writer - New Data"] -pub type ND23_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND24` reader - New Data"] pub type ND24_R = crate::BitReader; #[doc = "Field `ND24` writer - New Data"] -pub type ND24_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND25` reader - New Data"] pub type ND25_R = crate::BitReader; #[doc = "Field `ND25` writer - New Data"] -pub type ND25_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND26` reader - New Data"] pub type ND26_R = crate::BitReader; #[doc = "Field `ND26` writer - New Data"] -pub type ND26_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND27` reader - New Data"] pub type ND27_R = crate::BitReader; #[doc = "Field `ND27` writer - New Data"] -pub type ND27_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND28` reader - New Data"] pub type ND28_R = crate::BitReader; #[doc = "Field `ND28` writer - New Data"] -pub type ND28_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND29` reader - New Data"] pub type ND29_R = crate::BitReader; #[doc = "Field `ND29` writer - New Data"] -pub type ND29_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND30` reader - New Data"] pub type ND30_R = crate::BitReader; #[doc = "Field `ND30` writer - New Data"] -pub type ND30_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND31` reader - New Data"] pub type ND31_R = crate::BitReader; #[doc = "Field `ND31` writer - New Data"] -pub type ND31_W<'a, const O: u8> = crate::BitWriter<'a, NDAT1_SPEC, O>; +pub type ND31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - New Data"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - New Data"] #[inline(always)] #[must_use] - pub fn nd0(&mut self) -> ND0_W<0> { + pub fn nd0(&mut self) -> ND0_W { ND0_W::new(self) } #[doc = "Bit 1 - New Data"] #[inline(always)] #[must_use] - pub fn nd1(&mut self) -> ND1_W<1> { + pub fn nd1(&mut self) -> ND1_W { ND1_W::new(self) } #[doc = "Bit 2 - New Data"] #[inline(always)] #[must_use] - pub fn nd2(&mut self) -> ND2_W<2> { + pub fn nd2(&mut self) -> ND2_W { ND2_W::new(self) } #[doc = "Bit 3 - New Data"] #[inline(always)] #[must_use] - pub fn nd3(&mut self) -> ND3_W<3> { + pub fn nd3(&mut self) -> ND3_W { ND3_W::new(self) } #[doc = "Bit 4 - New Data"] #[inline(always)] #[must_use] - pub fn nd4(&mut self) -> ND4_W<4> { + pub fn nd4(&mut self) -> ND4_W { ND4_W::new(self) } #[doc = "Bit 5 - New Data"] #[inline(always)] #[must_use] - pub fn nd5(&mut self) -> ND5_W<5> { + pub fn nd5(&mut self) -> ND5_W { ND5_W::new(self) } #[doc = "Bit 6 - New Data"] #[inline(always)] #[must_use] - pub fn nd6(&mut self) -> ND6_W<6> { + pub fn nd6(&mut self) -> ND6_W { ND6_W::new(self) } #[doc = "Bit 7 - New Data"] #[inline(always)] #[must_use] - pub fn nd7(&mut self) -> ND7_W<7> { + pub fn nd7(&mut self) -> ND7_W { ND7_W::new(self) } #[doc = "Bit 8 - New Data"] #[inline(always)] #[must_use] - pub fn nd8(&mut self) -> ND8_W<8> { + pub fn nd8(&mut self) -> ND8_W { ND8_W::new(self) } #[doc = "Bit 9 - New Data"] #[inline(always)] #[must_use] - pub fn nd9(&mut self) -> ND9_W<9> { + pub fn nd9(&mut self) -> ND9_W { ND9_W::new(self) } #[doc = "Bit 10 - New Data"] #[inline(always)] #[must_use] - pub fn nd10(&mut self) -> ND10_W<10> { + pub fn nd10(&mut self) -> ND10_W { ND10_W::new(self) } #[doc = "Bit 11 - New Data"] #[inline(always)] #[must_use] - pub fn nd11(&mut self) -> ND11_W<11> { + pub fn nd11(&mut self) -> ND11_W { ND11_W::new(self) } #[doc = "Bit 12 - New Data"] #[inline(always)] #[must_use] - pub fn nd12(&mut self) -> ND12_W<12> { + pub fn nd12(&mut self) -> ND12_W { ND12_W::new(self) } #[doc = "Bit 13 - New Data"] #[inline(always)] #[must_use] - pub fn nd13(&mut self) -> ND13_W<13> { + pub fn nd13(&mut self) -> ND13_W { ND13_W::new(self) } #[doc = "Bit 14 - New Data"] #[inline(always)] #[must_use] - pub fn nd14(&mut self) -> ND14_W<14> { + pub fn nd14(&mut self) -> ND14_W { ND14_W::new(self) } #[doc = "Bit 15 - New Data"] #[inline(always)] #[must_use] - pub fn nd15(&mut self) -> ND15_W<15> { + pub fn nd15(&mut self) -> ND15_W { ND15_W::new(self) } #[doc = "Bit 16 - New Data"] #[inline(always)] #[must_use] - pub fn nd16(&mut self) -> ND16_W<16> { + pub fn nd16(&mut self) -> ND16_W { ND16_W::new(self) } #[doc = "Bit 17 - New Data"] #[inline(always)] #[must_use] - pub fn nd17(&mut self) -> ND17_W<17> { + pub fn nd17(&mut self) -> ND17_W { ND17_W::new(self) } #[doc = "Bit 18 - New Data"] #[inline(always)] #[must_use] - pub fn nd18(&mut self) -> ND18_W<18> { + pub fn nd18(&mut self) -> ND18_W { ND18_W::new(self) } #[doc = "Bit 19 - New Data"] #[inline(always)] #[must_use] - pub fn nd19(&mut self) -> ND19_W<19> { + pub fn nd19(&mut self) -> ND19_W { ND19_W::new(self) } #[doc = "Bit 20 - New Data"] #[inline(always)] #[must_use] - pub fn nd20(&mut self) -> ND20_W<20> { + pub fn nd20(&mut self) -> ND20_W { ND20_W::new(self) } #[doc = "Bit 21 - New Data"] #[inline(always)] #[must_use] - pub fn nd21(&mut self) -> ND21_W<21> { + pub fn nd21(&mut self) -> ND21_W { ND21_W::new(self) } #[doc = "Bit 22 - New Data"] #[inline(always)] #[must_use] - pub fn nd22(&mut self) -> ND22_W<22> { + pub fn nd22(&mut self) -> ND22_W { ND22_W::new(self) } #[doc = "Bit 23 - New Data"] #[inline(always)] #[must_use] - pub fn nd23(&mut self) -> ND23_W<23> { + pub fn nd23(&mut self) -> ND23_W { ND23_W::new(self) } #[doc = "Bit 24 - New Data"] #[inline(always)] #[must_use] - pub fn nd24(&mut self) -> ND24_W<24> { + pub fn nd24(&mut self) -> ND24_W { ND24_W::new(self) } #[doc = "Bit 25 - New Data"] #[inline(always)] #[must_use] - pub fn nd25(&mut self) -> ND25_W<25> { + pub fn nd25(&mut self) -> ND25_W { ND25_W::new(self) } #[doc = "Bit 26 - New Data"] #[inline(always)] #[must_use] - pub fn nd26(&mut self) -> ND26_W<26> { + pub fn nd26(&mut self) -> ND26_W { ND26_W::new(self) } #[doc = "Bit 27 - New Data"] #[inline(always)] #[must_use] - pub fn nd27(&mut self) -> ND27_W<27> { + pub fn nd27(&mut self) -> ND27_W { ND27_W::new(self) } #[doc = "Bit 28 - New Data"] #[inline(always)] #[must_use] - pub fn nd28(&mut self) -> ND28_W<28> { + pub fn nd28(&mut self) -> ND28_W { ND28_W::new(self) } #[doc = "Bit 29 - New Data"] #[inline(always)] #[must_use] - pub fn nd29(&mut self) -> ND29_W<29> { + pub fn nd29(&mut self) -> ND29_W { ND29_W::new(self) } #[doc = "Bit 30 - New Data"] #[inline(always)] #[must_use] - pub fn nd30(&mut self) -> ND30_W<30> { + pub fn nd30(&mut self) -> ND30_W { ND30_W::new(self) } #[doc = "Bit 31 - New Data"] #[inline(always)] #[must_use] - pub fn nd31(&mut self) -> ND31_W<31> { + pub fn nd31(&mut self) -> ND31_W { ND31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "New Data 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat1](index.html) module"] +#[doc = "New Data 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NDAT1_SPEC; impl crate::RegisterSpec for NDAT1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ndat1::R](R) reader structure"] -impl crate::Readable for NDAT1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ndat1::W](W) writer structure"] +#[doc = "`read()` method returns [`ndat1::R`](R) reader structure"] +impl crate::Readable for NDAT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ndat1::W`](W) writer structure"] impl crate::Writable for NDAT1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/ndat2.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/ndat2.rs index 0e29e26f..1bde7f15 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/ndat2.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/ndat2.rs @@ -1,167 +1,135 @@ #[doc = "Register `NDAT2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `NDAT2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ND32` reader - New Data"] pub type ND32_R = crate::BitReader; #[doc = "Field `ND32` writer - New Data"] -pub type ND32_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND33` reader - New Data"] pub type ND33_R = crate::BitReader; #[doc = "Field `ND33` writer - New Data"] -pub type ND33_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND34` reader - New Data"] pub type ND34_R = crate::BitReader; #[doc = "Field `ND34` writer - New Data"] -pub type ND34_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND35` reader - New Data"] pub type ND35_R = crate::BitReader; #[doc = "Field `ND35` writer - New Data"] -pub type ND35_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND36` reader - New Data"] pub type ND36_R = crate::BitReader; #[doc = "Field `ND36` writer - New Data"] -pub type ND36_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND36_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND37` reader - New Data"] pub type ND37_R = crate::BitReader; #[doc = "Field `ND37` writer - New Data"] -pub type ND37_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND38` reader - New Data"] pub type ND38_R = crate::BitReader; #[doc = "Field `ND38` writer - New Data"] -pub type ND38_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND38_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND39` reader - New Data"] pub type ND39_R = crate::BitReader; #[doc = "Field `ND39` writer - New Data"] -pub type ND39_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND40` reader - New Data"] pub type ND40_R = crate::BitReader; #[doc = "Field `ND40` writer - New Data"] -pub type ND40_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND41` reader - New Data"] pub type ND41_R = crate::BitReader; #[doc = "Field `ND41` writer - New Data"] -pub type ND41_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND42` reader - New Data"] pub type ND42_R = crate::BitReader; #[doc = "Field `ND42` writer - New Data"] -pub type ND42_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND43` reader - New Data"] pub type ND43_R = crate::BitReader; #[doc = "Field `ND43` writer - New Data"] -pub type ND43_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND44` reader - New Data"] pub type ND44_R = crate::BitReader; #[doc = "Field `ND44` writer - New Data"] -pub type ND44_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND45` reader - New Data"] pub type ND45_R = crate::BitReader; #[doc = "Field `ND45` writer - New Data"] -pub type ND45_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND46` reader - New Data"] pub type ND46_R = crate::BitReader; #[doc = "Field `ND46` writer - New Data"] -pub type ND46_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND47` reader - New Data"] pub type ND47_R = crate::BitReader; #[doc = "Field `ND47` writer - New Data"] -pub type ND47_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND48` reader - New Data"] pub type ND48_R = crate::BitReader; #[doc = "Field `ND48` writer - New Data"] -pub type ND48_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND49` reader - New Data"] pub type ND49_R = crate::BitReader; #[doc = "Field `ND49` writer - New Data"] -pub type ND49_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND50` reader - New Data"] pub type ND50_R = crate::BitReader; #[doc = "Field `ND50` writer - New Data"] -pub type ND50_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND51` reader - New Data"] pub type ND51_R = crate::BitReader; #[doc = "Field `ND51` writer - New Data"] -pub type ND51_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND52` reader - New Data"] pub type ND52_R = crate::BitReader; #[doc = "Field `ND52` writer - New Data"] -pub type ND52_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND53` reader - New Data"] pub type ND53_R = crate::BitReader; #[doc = "Field `ND53` writer - New Data"] -pub type ND53_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND54` reader - New Data"] pub type ND54_R = crate::BitReader; #[doc = "Field `ND54` writer - New Data"] -pub type ND54_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND54_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND55` reader - New Data"] pub type ND55_R = crate::BitReader; #[doc = "Field `ND55` writer - New Data"] -pub type ND55_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND55_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND56` reader - New Data"] pub type ND56_R = crate::BitReader; #[doc = "Field `ND56` writer - New Data"] -pub type ND56_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND57` reader - New Data"] pub type ND57_R = crate::BitReader; #[doc = "Field `ND57` writer - New Data"] -pub type ND57_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND58` reader - New Data"] pub type ND58_R = crate::BitReader; #[doc = "Field `ND58` writer - New Data"] -pub type ND58_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND59` reader - New Data"] pub type ND59_R = crate::BitReader; #[doc = "Field `ND59` writer - New Data"] -pub type ND59_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND60` reader - New Data"] pub type ND60_R = crate::BitReader; #[doc = "Field `ND60` writer - New Data"] -pub type ND60_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND61` reader - New Data"] pub type ND61_R = crate::BitReader; #[doc = "Field `ND61` writer - New Data"] -pub type ND61_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND61_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND62` reader - New Data"] pub type ND62_R = crate::BitReader; #[doc = "Field `ND62` writer - New Data"] -pub type ND62_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND62_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ND63` reader - New Data"] pub type ND63_R = crate::BitReader; #[doc = "Field `ND63` writer - New Data"] -pub type ND63_W<'a, const O: u8> = crate::BitWriter<'a, NDAT2_SPEC, O>; +pub type ND63_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - New Data"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - New Data"] #[inline(always)] #[must_use] - pub fn nd32(&mut self) -> ND32_W<0> { + pub fn nd32(&mut self) -> ND32_W { ND32_W::new(self) } #[doc = "Bit 1 - New Data"] #[inline(always)] #[must_use] - pub fn nd33(&mut self) -> ND33_W<1> { + pub fn nd33(&mut self) -> ND33_W { ND33_W::new(self) } #[doc = "Bit 2 - New Data"] #[inline(always)] #[must_use] - pub fn nd34(&mut self) -> ND34_W<2> { + pub fn nd34(&mut self) -> ND34_W { ND34_W::new(self) } #[doc = "Bit 3 - New Data"] #[inline(always)] #[must_use] - pub fn nd35(&mut self) -> ND35_W<3> { + pub fn nd35(&mut self) -> ND35_W { ND35_W::new(self) } #[doc = "Bit 4 - New Data"] #[inline(always)] #[must_use] - pub fn nd36(&mut self) -> ND36_W<4> { + pub fn nd36(&mut self) -> ND36_W { ND36_W::new(self) } #[doc = "Bit 5 - New Data"] #[inline(always)] #[must_use] - pub fn nd37(&mut self) -> ND37_W<5> { + pub fn nd37(&mut self) -> ND37_W { ND37_W::new(self) } #[doc = "Bit 6 - New Data"] #[inline(always)] #[must_use] - pub fn nd38(&mut self) -> ND38_W<6> { + pub fn nd38(&mut self) -> ND38_W { ND38_W::new(self) } #[doc = "Bit 7 - New Data"] #[inline(always)] #[must_use] - pub fn nd39(&mut self) -> ND39_W<7> { + pub fn nd39(&mut self) -> ND39_W { ND39_W::new(self) } #[doc = "Bit 8 - New Data"] #[inline(always)] #[must_use] - pub fn nd40(&mut self) -> ND40_W<8> { + pub fn nd40(&mut self) -> ND40_W { ND40_W::new(self) } #[doc = "Bit 9 - New Data"] #[inline(always)] #[must_use] - pub fn nd41(&mut self) -> ND41_W<9> { + pub fn nd41(&mut self) -> ND41_W { ND41_W::new(self) } #[doc = "Bit 10 - New Data"] #[inline(always)] #[must_use] - pub fn nd42(&mut self) -> ND42_W<10> { + pub fn nd42(&mut self) -> ND42_W { ND42_W::new(self) } #[doc = "Bit 11 - New Data"] #[inline(always)] #[must_use] - pub fn nd43(&mut self) -> ND43_W<11> { + pub fn nd43(&mut self) -> ND43_W { ND43_W::new(self) } #[doc = "Bit 12 - New Data"] #[inline(always)] #[must_use] - pub fn nd44(&mut self) -> ND44_W<12> { + pub fn nd44(&mut self) -> ND44_W { ND44_W::new(self) } #[doc = "Bit 13 - New Data"] #[inline(always)] #[must_use] - pub fn nd45(&mut self) -> ND45_W<13> { + pub fn nd45(&mut self) -> ND45_W { ND45_W::new(self) } #[doc = "Bit 14 - New Data"] #[inline(always)] #[must_use] - pub fn nd46(&mut self) -> ND46_W<14> { + pub fn nd46(&mut self) -> ND46_W { ND46_W::new(self) } #[doc = "Bit 15 - New Data"] #[inline(always)] #[must_use] - pub fn nd47(&mut self) -> ND47_W<15> { + pub fn nd47(&mut self) -> ND47_W { ND47_W::new(self) } #[doc = "Bit 16 - New Data"] #[inline(always)] #[must_use] - pub fn nd48(&mut self) -> ND48_W<16> { + pub fn nd48(&mut self) -> ND48_W { ND48_W::new(self) } #[doc = "Bit 17 - New Data"] #[inline(always)] #[must_use] - pub fn nd49(&mut self) -> ND49_W<17> { + pub fn nd49(&mut self) -> ND49_W { ND49_W::new(self) } #[doc = "Bit 18 - New Data"] #[inline(always)] #[must_use] - pub fn nd50(&mut self) -> ND50_W<18> { + pub fn nd50(&mut self) -> ND50_W { ND50_W::new(self) } #[doc = "Bit 19 - New Data"] #[inline(always)] #[must_use] - pub fn nd51(&mut self) -> ND51_W<19> { + pub fn nd51(&mut self) -> ND51_W { ND51_W::new(self) } #[doc = "Bit 20 - New Data"] #[inline(always)] #[must_use] - pub fn nd52(&mut self) -> ND52_W<20> { + pub fn nd52(&mut self) -> ND52_W { ND52_W::new(self) } #[doc = "Bit 21 - New Data"] #[inline(always)] #[must_use] - pub fn nd53(&mut self) -> ND53_W<21> { + pub fn nd53(&mut self) -> ND53_W { ND53_W::new(self) } #[doc = "Bit 22 - New Data"] #[inline(always)] #[must_use] - pub fn nd54(&mut self) -> ND54_W<22> { + pub fn nd54(&mut self) -> ND54_W { ND54_W::new(self) } #[doc = "Bit 23 - New Data"] #[inline(always)] #[must_use] - pub fn nd55(&mut self) -> ND55_W<23> { + pub fn nd55(&mut self) -> ND55_W { ND55_W::new(self) } #[doc = "Bit 24 - New Data"] #[inline(always)] #[must_use] - pub fn nd56(&mut self) -> ND56_W<24> { + pub fn nd56(&mut self) -> ND56_W { ND56_W::new(self) } #[doc = "Bit 25 - New Data"] #[inline(always)] #[must_use] - pub fn nd57(&mut self) -> ND57_W<25> { + pub fn nd57(&mut self) -> ND57_W { ND57_W::new(self) } #[doc = "Bit 26 - New Data"] #[inline(always)] #[must_use] - pub fn nd58(&mut self) -> ND58_W<26> { + pub fn nd58(&mut self) -> ND58_W { ND58_W::new(self) } #[doc = "Bit 27 - New Data"] #[inline(always)] #[must_use] - pub fn nd59(&mut self) -> ND59_W<27> { + pub fn nd59(&mut self) -> ND59_W { ND59_W::new(self) } #[doc = "Bit 28 - New Data"] #[inline(always)] #[must_use] - pub fn nd60(&mut self) -> ND60_W<28> { + pub fn nd60(&mut self) -> ND60_W { ND60_W::new(self) } #[doc = "Bit 29 - New Data"] #[inline(always)] #[must_use] - pub fn nd61(&mut self) -> ND61_W<29> { + pub fn nd61(&mut self) -> ND61_W { ND61_W::new(self) } #[doc = "Bit 30 - New Data"] #[inline(always)] #[must_use] - pub fn nd62(&mut self) -> ND62_W<30> { + pub fn nd62(&mut self) -> ND62_W { ND62_W::new(self) } #[doc = "Bit 31 - New Data"] #[inline(always)] #[must_use] - pub fn nd63(&mut self) -> ND63_W<31> { + pub fn nd63(&mut self) -> ND63_W { ND63_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "New Data 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ndat2](index.html) module"] +#[doc = "New Data 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct NDAT2_SPEC; impl crate::RegisterSpec for NDAT2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ndat2::R](R) reader structure"] -impl crate::Readable for NDAT2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ndat2::W](W) writer structure"] +#[doc = "`read()` method returns [`ndat2::R`](R) reader structure"] +impl crate::Readable for NDAT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ndat2::W`](W) writer structure"] impl crate::Writable for NDAT2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/psr.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/psr.rs index df150b6d..41200dec 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/psr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/psr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LEC` reader - Last Error Code (set to 111 on read)"] pub type LEC_R = crate::FieldReader; #[doc = "Last Error Code (set to 111 on read)\n\nValue on reset: 0"] @@ -61,42 +48,42 @@ impl LEC_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NO_ERROR`"] + #[doc = "No error occurred since LEC has been reset by successful reception or transmission."] #[inline(always)] pub fn is_no_error(&self) -> bool { *self == LECSELECT_A::NO_ERROR } - #[doc = "Checks if the value of the field is `STUFF_ERROR`"] + #[doc = "More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed."] #[inline(always)] pub fn is_stuff_error(&self) -> bool { *self == LECSELECT_A::STUFF_ERROR } - #[doc = "Checks if the value of the field is `FORM_ERROR`"] + #[doc = "A fixed format part of a received frame has the wrong format."] #[inline(always)] pub fn is_form_error(&self) -> bool { *self == LECSELECT_A::FORM_ERROR } - #[doc = "Checks if the value of the field is `ACK_ERROR`"] + #[doc = "The message transmitted by the MCAN was not acknowledged by another node."] #[inline(always)] pub fn is_ack_error(&self) -> bool { *self == LECSELECT_A::ACK_ERROR } - #[doc = "Checks if the value of the field is `BIT1_ERROR`"] + #[doc = "During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant."] #[inline(always)] pub fn is_bit1_error(&self) -> bool { *self == LECSELECT_A::BIT1_ERROR } - #[doc = "Checks if the value of the field is `BIT0_ERROR`"] + #[doc = "During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed)."] #[inline(always)] pub fn is_bit0_error(&self) -> bool { *self == LECSELECT_A::BIT0_ERROR } - #[doc = "Checks if the value of the field is `CRC_ERROR`"] + #[doc = "The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data."] #[inline(always)] pub fn is_crc_error(&self) -> bool { *self == LECSELECT_A::CRC_ERROR } - #[doc = "Checks if the value of the field is `NO_CHANGE`"] + #[doc = "Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register."] #[inline(always)] pub fn is_no_change(&self) -> bool { *self == LECSELECT_A::NO_CHANGE @@ -138,22 +125,22 @@ impl ACT_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SYNCHRONIZING`"] + #[doc = "Node is synchronizing on CAN communication"] #[inline(always)] pub fn is_synchronizing(&self) -> bool { *self == ACTSELECT_A::SYNCHRONIZING } - #[doc = "Checks if the value of the field is `IDLE`"] + #[doc = "Node is neither receiver nor transmitter"] #[inline(always)] pub fn is_idle(&self) -> bool { *self == ACTSELECT_A::IDLE } - #[doc = "Checks if the value of the field is `RECEIVER`"] + #[doc = "Node is operating as receiver"] #[inline(always)] pub fn is_receiver(&self) -> bool { *self == ACTSELECT_A::RECEIVER } - #[doc = "Checks if the value of the field is `TRANSMITTER`"] + #[doc = "Node is operating as transmitter"] #[inline(always)] pub fn is_transmitter(&self) -> bool { *self == ACTSELECT_A::TRANSMITTER @@ -234,15 +221,13 @@ impl R { TDCV_R::new(((self.bits >> 16) & 0x7f) as u8) } } -#[doc = "Protocol Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psr](index.html) module"] +#[doc = "Protocol Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PSR_SPEC; impl crate::RegisterSpec for PSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [psr::R](R) reader structure"] -impl crate::Readable for PSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`psr::R`](R) reader structure"] +impl crate::Readable for PSR_SPEC {} #[doc = "`reset()` method sets PSR to value 0"] impl crate::Resettable for PSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rwd.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rwd.rs index 559067ce..ed377302 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rwd.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rwd.rs @@ -1,47 +1,15 @@ #[doc = "Register `RWD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RWD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WDC` reader - Watchdog Configuration (read/write)"] pub type WDC_R = crate::FieldReader; #[doc = "Field `WDC` writer - Watchdog Configuration (read/write)"] -pub type WDC_W<'a, const O: u8> = crate::FieldWriter<'a, RWD_SPEC, 8, O>; +pub type WDC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `WDV` reader - Watchdog Value (read-only)"] pub type WDV_R = crate::FieldReader; #[doc = "Field `WDV` writer - Watchdog Value (read-only)"] -pub type WDV_W<'a, const O: u8> = crate::FieldWriter<'a, RWD_SPEC, 8, O>; +pub type WDV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Watchdog Configuration (read/write)"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:7 - Watchdog Configuration (read/write)"] #[inline(always)] #[must_use] - pub fn wdc(&mut self) -> WDC_W<0> { + pub fn wdc(&mut self) -> WDC_W { WDC_W::new(self) } #[doc = "Bits 8:15 - Watchdog Value (read-only)"] #[inline(always)] #[must_use] - pub fn wdv(&mut self) -> WDV_W<8> { + pub fn wdv(&mut self) -> WDV_W { WDV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "RAM Watchdog Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rwd](index.html) module"] +#[doc = "RAM Watchdog Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RWD_SPEC; impl crate::RegisterSpec for RWD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rwd::R](R) reader structure"] -impl crate::Readable for RWD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rwd::W](W) writer structure"] +#[doc = "`read()` method returns [`rwd::R`](R) reader structure"] +impl crate::Readable for RWD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rwd::W`](W) writer structure"] impl crate::Writable for RWD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxbc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxbc.rs index 23a04be2..1084cb65 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxbc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxbc.rs @@ -1,43 +1,11 @@ #[doc = "Register `RXBC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXBC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RBSA` reader - Receive Buffer Start Address"] pub type RBSA_R = crate::FieldReader; #[doc = "Field `RBSA` writer - Receive Buffer Start Address"] -pub type RBSA_W<'a, const O: u8> = crate::FieldWriter<'a, RXBC_SPEC, 14, O, u16>; +pub type RBSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; impl R { #[doc = "Bits 2:15 - Receive Buffer Start Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 2:15 - Receive Buffer Start Address"] #[inline(always)] #[must_use] - pub fn rbsa(&mut self) -> RBSA_W<2> { + pub fn rbsa(&mut self) -> RBSA_W { RBSA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Rx Buffer Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxbc](index.html) module"] +#[doc = "Receive Rx Buffer Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxbc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxbc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXBC_SPEC; impl crate::RegisterSpec for RXBC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxbc::R](R) reader structure"] -impl crate::Readable for RXBC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxbc::W](W) writer structure"] +#[doc = "`read()` method returns [`rxbc::R`](R) reader structure"] +impl crate::Readable for RXBC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxbc::W`](W) writer structure"] impl crate::Writable for RXBC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxesc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxesc.rs index 902b78f1..6b1bf84e 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxesc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxesc.rs @@ -1,39 +1,7 @@ #[doc = "Register `RXESC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXESC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `F0DS` reader - Receive FIFO 0 Data Field Size"] pub type F0DS_R = crate::FieldReader; #[doc = "Receive FIFO 0 Data Field Size\n\nValue on reset: 0"] @@ -82,88 +50,92 @@ impl F0DS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8-byte data field"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == F0DSSELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_12_BYTE`"] + #[doc = "12-byte data field"] #[inline(always)] pub fn is_12_byte(&self) -> bool { *self == F0DSSELECT_A::_12_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16-byte data field"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == F0DSSELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_20_BYTE`"] + #[doc = "20-byte data field"] #[inline(always)] pub fn is_20_byte(&self) -> bool { *self == F0DSSELECT_A::_20_BYTE } - #[doc = "Checks if the value of the field is `_24_BYTE`"] + #[doc = "24-byte data field"] #[inline(always)] pub fn is_24_byte(&self) -> bool { *self == F0DSSELECT_A::_24_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32-byte data field"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == F0DSSELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_48_BYTE`"] + #[doc = "48-byte data field"] #[inline(always)] pub fn is_48_byte(&self) -> bool { *self == F0DSSELECT_A::_48_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64-byte data field"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == F0DSSELECT_A::_64_BYTE } } #[doc = "Field `F0DS` writer - Receive FIFO 0 Data Field Size"] -pub type F0DS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, RXESC_SPEC, 3, O, F0DSSELECT_A>; -impl<'a, const O: u8> F0DS_W<'a, O> { +pub type F0DS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, F0DSSELECT_A>; +impl<'a, REG, const O: u8> F0DS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8-byte data field"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_8_BYTE) } #[doc = "12-byte data field"] #[inline(always)] - pub fn _12_byte(self) -> &'a mut W { + pub fn _12_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_12_BYTE) } #[doc = "16-byte data field"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_16_BYTE) } #[doc = "20-byte data field"] #[inline(always)] - pub fn _20_byte(self) -> &'a mut W { + pub fn _20_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_20_BYTE) } #[doc = "24-byte data field"] #[inline(always)] - pub fn _24_byte(self) -> &'a mut W { + pub fn _24_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_24_BYTE) } #[doc = "32-byte data field"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_32_BYTE) } #[doc = "48-byte data field"] #[inline(always)] - pub fn _48_byte(self) -> &'a mut W { + pub fn _48_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_48_BYTE) } #[doc = "64-byte data field"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(F0DSSELECT_A::_64_BYTE) } } @@ -215,88 +187,92 @@ impl F1DS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8-byte data field"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == F1DSSELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_12_BYTE`"] + #[doc = "12-byte data field"] #[inline(always)] pub fn is_12_byte(&self) -> bool { *self == F1DSSELECT_A::_12_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16-byte data field"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == F1DSSELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_20_BYTE`"] + #[doc = "20-byte data field"] #[inline(always)] pub fn is_20_byte(&self) -> bool { *self == F1DSSELECT_A::_20_BYTE } - #[doc = "Checks if the value of the field is `_24_BYTE`"] + #[doc = "24-byte data field"] #[inline(always)] pub fn is_24_byte(&self) -> bool { *self == F1DSSELECT_A::_24_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32-byte data field"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == F1DSSELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_48_BYTE`"] + #[doc = "48-byte data field"] #[inline(always)] pub fn is_48_byte(&self) -> bool { *self == F1DSSELECT_A::_48_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64-byte data field"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == F1DSSELECT_A::_64_BYTE } } #[doc = "Field `F1DS` writer - Receive FIFO 1 Data Field Size"] -pub type F1DS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, RXESC_SPEC, 3, O, F1DSSELECT_A>; -impl<'a, const O: u8> F1DS_W<'a, O> { +pub type F1DS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, F1DSSELECT_A>; +impl<'a, REG, const O: u8> F1DS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8-byte data field"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_8_BYTE) } #[doc = "12-byte data field"] #[inline(always)] - pub fn _12_byte(self) -> &'a mut W { + pub fn _12_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_12_BYTE) } #[doc = "16-byte data field"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_16_BYTE) } #[doc = "20-byte data field"] #[inline(always)] - pub fn _20_byte(self) -> &'a mut W { + pub fn _20_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_20_BYTE) } #[doc = "24-byte data field"] #[inline(always)] - pub fn _24_byte(self) -> &'a mut W { + pub fn _24_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_24_BYTE) } #[doc = "32-byte data field"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_32_BYTE) } #[doc = "48-byte data field"] #[inline(always)] - pub fn _48_byte(self) -> &'a mut W { + pub fn _48_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_48_BYTE) } #[doc = "64-byte data field"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(F1DSSELECT_A::_64_BYTE) } } @@ -348,88 +324,92 @@ impl RBDS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8-byte data field"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == RBDSSELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_12_BYTE`"] + #[doc = "12-byte data field"] #[inline(always)] pub fn is_12_byte(&self) -> bool { *self == RBDSSELECT_A::_12_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16-byte data field"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == RBDSSELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_20_BYTE`"] + #[doc = "20-byte data field"] #[inline(always)] pub fn is_20_byte(&self) -> bool { *self == RBDSSELECT_A::_20_BYTE } - #[doc = "Checks if the value of the field is `_24_BYTE`"] + #[doc = "24-byte data field"] #[inline(always)] pub fn is_24_byte(&self) -> bool { *self == RBDSSELECT_A::_24_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32-byte data field"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == RBDSSELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_48_BYTE`"] + #[doc = "48-byte data field"] #[inline(always)] pub fn is_48_byte(&self) -> bool { *self == RBDSSELECT_A::_48_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64-byte data field"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == RBDSSELECT_A::_64_BYTE } } #[doc = "Field `RBDS` writer - Receive Buffer Data Field Size"] -pub type RBDS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, RXESC_SPEC, 3, O, RBDSSELECT_A>; -impl<'a, const O: u8> RBDS_W<'a, O> { +pub type RBDS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, RBDSSELECT_A>; +impl<'a, REG, const O: u8> RBDS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8-byte data field"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_8_BYTE) } #[doc = "12-byte data field"] #[inline(always)] - pub fn _12_byte(self) -> &'a mut W { + pub fn _12_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_12_BYTE) } #[doc = "16-byte data field"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_16_BYTE) } #[doc = "20-byte data field"] #[inline(always)] - pub fn _20_byte(self) -> &'a mut W { + pub fn _20_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_20_BYTE) } #[doc = "24-byte data field"] #[inline(always)] - pub fn _24_byte(self) -> &'a mut W { + pub fn _24_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_24_BYTE) } #[doc = "32-byte data field"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_32_BYTE) } #[doc = "48-byte data field"] #[inline(always)] - pub fn _48_byte(self) -> &'a mut W { + pub fn _48_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_48_BYTE) } #[doc = "64-byte data field"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(RBDSSELECT_A::_64_BYTE) } } @@ -454,40 +434,37 @@ impl W { #[doc = "Bits 0:2 - Receive FIFO 0 Data Field Size"] #[inline(always)] #[must_use] - pub fn f0ds(&mut self) -> F0DS_W<0> { + pub fn f0ds(&mut self) -> F0DS_W { F0DS_W::new(self) } #[doc = "Bits 4:6 - Receive FIFO 1 Data Field Size"] #[inline(always)] #[must_use] - pub fn f1ds(&mut self) -> F1DS_W<4> { + pub fn f1ds(&mut self) -> F1DS_W { F1DS_W::new(self) } #[doc = "Bits 8:10 - Receive Buffer Data Field Size"] #[inline(always)] #[must_use] - pub fn rbds(&mut self) -> RBDS_W<8> { + pub fn rbds(&mut self) -> RBDS_W { RBDS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Buffer / FIFO Element Size Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxesc](index.html) module"] +#[doc = "Receive Buffer / FIFO Element Size Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxesc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxesc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXESC_SPEC; impl crate::RegisterSpec for RXESC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxesc::R](R) reader structure"] -impl crate::Readable for RXESC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxesc::W](W) writer structure"] +#[doc = "`read()` method returns [`rxesc::R`](R) reader structure"] +impl crate::Readable for RXESC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxesc::W`](W) writer structure"] impl crate::Writable for RXESC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0a.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0a.rs index 4a967bce..06a48c1d 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0a.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0a.rs @@ -1,43 +1,11 @@ #[doc = "Register `RXF0A` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXF0A` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `F0AI` reader - Receive FIFO 0 Acknowledge Index"] pub type F0AI_R = crate::FieldReader; #[doc = "Field `F0AI` writer - Receive FIFO 0 Acknowledge Index"] -pub type F0AI_W<'a, const O: u8> = crate::FieldWriter<'a, RXF0A_SPEC, 6, O>; +pub type F0AI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - Receive FIFO 0 Acknowledge Index"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:5 - Receive FIFO 0 Acknowledge Index"] #[inline(always)] #[must_use] - pub fn f0ai(&mut self) -> F0AI_W<0> { + pub fn f0ai(&mut self) -> F0AI_W { F0AI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive FIFO 0 Acknowledge Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0a](index.html) module"] +#[doc = "Receive FIFO 0 Acknowledge Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF0A_SPEC; impl crate::RegisterSpec for RXF0A_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf0a::R](R) reader structure"] -impl crate::Readable for RXF0A_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxf0a::W](W) writer structure"] +#[doc = "`read()` method returns [`rxf0a::R`](R) reader structure"] +impl crate::Readable for RXF0A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf0a::W`](W) writer structure"] impl crate::Writable for RXF0A_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0c.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0c.rs index d8d5ead9..33b67e9f 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0c.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0c.rs @@ -1,55 +1,23 @@ #[doc = "Register `RXF0C` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXF0C` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `F0SA` reader - Receive FIFO 0 Start Address"] pub type F0SA_R = crate::FieldReader; #[doc = "Field `F0SA` writer - Receive FIFO 0 Start Address"] -pub type F0SA_W<'a, const O: u8> = crate::FieldWriter<'a, RXF0C_SPEC, 14, O, u16>; +pub type F0SA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `F0S` reader - Receive FIFO 0 Start Address"] pub type F0S_R = crate::FieldReader; #[doc = "Field `F0S` writer - Receive FIFO 0 Start Address"] -pub type F0S_W<'a, const O: u8> = crate::FieldWriter<'a, RXF0C_SPEC, 7, O>; +pub type F0S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `F0WM` reader - Receive FIFO 0 Watermark"] pub type F0WM_R = crate::FieldReader; #[doc = "Field `F0WM` writer - Receive FIFO 0 Watermark"] -pub type F0WM_W<'a, const O: u8> = crate::FieldWriter<'a, RXF0C_SPEC, 7, O>; +pub type F0WM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `F0OM` reader - FIFO 0 Operation Mode"] pub type F0OM_R = crate::BitReader; #[doc = "Field `F0OM` writer - FIFO 0 Operation Mode"] -pub type F0OM_W<'a, const O: u8> = crate::BitWriter<'a, RXF0C_SPEC, O>; +pub type F0OM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 2:15 - Receive FIFO 0 Start Address"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 2:15 - Receive FIFO 0 Start Address"] #[inline(always)] #[must_use] - pub fn f0sa(&mut self) -> F0SA_W<2> { + pub fn f0sa(&mut self) -> F0SA_W { F0SA_W::new(self) } #[doc = "Bits 16:22 - Receive FIFO 0 Start Address"] #[inline(always)] #[must_use] - pub fn f0s(&mut self) -> F0S_W<16> { + pub fn f0s(&mut self) -> F0S_W { F0S_W::new(self) } #[doc = "Bits 24:30 - Receive FIFO 0 Watermark"] #[inline(always)] #[must_use] - pub fn f0wm(&mut self) -> F0WM_W<24> { + pub fn f0wm(&mut self) -> F0WM_W { F0WM_W::new(self) } #[doc = "Bit 31 - FIFO 0 Operation Mode"] #[inline(always)] #[must_use] - pub fn f0om(&mut self) -> F0OM_W<31> { + pub fn f0om(&mut self) -> F0OM_W { F0OM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive FIFO 0 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0c](index.html) module"] +#[doc = "Receive FIFO 0 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF0C_SPEC; impl crate::RegisterSpec for RXF0C_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf0c::R](R) reader structure"] -impl crate::Readable for RXF0C_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxf0c::W](W) writer structure"] +#[doc = "`read()` method returns [`rxf0c::R`](R) reader structure"] +impl crate::Readable for RXF0C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf0c::W`](W) writer structure"] impl crate::Writable for RXF0C_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0s.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0s.rs index fe99df3e..551b5810 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0s.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf0s.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXF0S` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `F0FL` reader - Receive FIFO 0 Fill Level"] pub type F0FL_R = crate::FieldReader; #[doc = "Field `F0GI` reader - Receive FIFO 0 Get Index"] @@ -50,15 +37,13 @@ impl R { RF0L_R::new(((self.bits >> 25) & 1) != 0) } } -#[doc = "Receive FIFO 0 Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf0s](index.html) module"] +#[doc = "Receive FIFO 0 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0s::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF0S_SPEC; impl crate::RegisterSpec for RXF0S_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf0s::R](R) reader structure"] -impl crate::Readable for RXF0S_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxf0s::R`](R) reader structure"] +impl crate::Readable for RXF0S_SPEC {} #[doc = "`reset()` method sets RXF0S to value 0"] impl crate::Resettable for RXF0S_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1a.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1a.rs index e70ec47e..3b35ac36 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1a.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1a.rs @@ -1,43 +1,11 @@ #[doc = "Register `RXF1A` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXF1A` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `F1AI` reader - Receive FIFO 1 Acknowledge Index"] pub type F1AI_R = crate::FieldReader; #[doc = "Field `F1AI` writer - Receive FIFO 1 Acknowledge Index"] -pub type F1AI_W<'a, const O: u8> = crate::FieldWriter<'a, RXF1A_SPEC, 6, O>; +pub type F1AI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - Receive FIFO 1 Acknowledge Index"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:5 - Receive FIFO 1 Acknowledge Index"] #[inline(always)] #[must_use] - pub fn f1ai(&mut self) -> F1AI_W<0> { + pub fn f1ai(&mut self) -> F1AI_W { F1AI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive FIFO 1 Acknowledge Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1a](index.html) module"] +#[doc = "Receive FIFO 1 Acknowledge Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1a::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF1A_SPEC; impl crate::RegisterSpec for RXF1A_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf1a::R](R) reader structure"] -impl crate::Readable for RXF1A_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxf1a::W](W) writer structure"] +#[doc = "`read()` method returns [`rxf1a::R`](R) reader structure"] +impl crate::Readable for RXF1A_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf1a::W`](W) writer structure"] impl crate::Writable for RXF1A_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1c.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1c.rs index 7b6716e0..cb4cb9bd 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1c.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1c.rs @@ -1,55 +1,23 @@ #[doc = "Register `RXF1C` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RXF1C` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `F1SA` reader - Receive FIFO 1 Start Address"] pub type F1SA_R = crate::FieldReader; #[doc = "Field `F1SA` writer - Receive FIFO 1 Start Address"] -pub type F1SA_W<'a, const O: u8> = crate::FieldWriter<'a, RXF1C_SPEC, 14, O, u16>; +pub type F1SA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `F1S` reader - Receive FIFO 1 Start Address"] pub type F1S_R = crate::FieldReader; #[doc = "Field `F1S` writer - Receive FIFO 1 Start Address"] -pub type F1S_W<'a, const O: u8> = crate::FieldWriter<'a, RXF1C_SPEC, 7, O>; +pub type F1S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `F1WM` reader - Receive FIFO 1 Watermark"] pub type F1WM_R = crate::FieldReader; #[doc = "Field `F1WM` writer - Receive FIFO 1 Watermark"] -pub type F1WM_W<'a, const O: u8> = crate::FieldWriter<'a, RXF1C_SPEC, 7, O>; +pub type F1WM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `F1OM` reader - FIFO 1 Operation Mode"] pub type F1OM_R = crate::BitReader; #[doc = "Field `F1OM` writer - FIFO 1 Operation Mode"] -pub type F1OM_W<'a, const O: u8> = crate::BitWriter<'a, RXF1C_SPEC, O>; +pub type F1OM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 2:15 - Receive FIFO 1 Start Address"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 2:15 - Receive FIFO 1 Start Address"] #[inline(always)] #[must_use] - pub fn f1sa(&mut self) -> F1SA_W<2> { + pub fn f1sa(&mut self) -> F1SA_W { F1SA_W::new(self) } #[doc = "Bits 16:22 - Receive FIFO 1 Start Address"] #[inline(always)] #[must_use] - pub fn f1s(&mut self) -> F1S_W<16> { + pub fn f1s(&mut self) -> F1S_W { F1S_W::new(self) } #[doc = "Bits 24:30 - Receive FIFO 1 Watermark"] #[inline(always)] #[must_use] - pub fn f1wm(&mut self) -> F1WM_W<24> { + pub fn f1wm(&mut self) -> F1WM_W { F1WM_W::new(self) } #[doc = "Bit 31 - FIFO 1 Operation Mode"] #[inline(always)] #[must_use] - pub fn f1om(&mut self) -> F1OM_W<31> { + pub fn f1om(&mut self) -> F1OM_W { F1OM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive FIFO 1 Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1c](index.html) module"] +#[doc = "Receive FIFO 1 Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1c::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF1C_SPEC; impl crate::RegisterSpec for RXF1C_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf1c::R](R) reader structure"] -impl crate::Readable for RXF1C_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rxf1c::W](W) writer structure"] +#[doc = "`read()` method returns [`rxf1c::R`](R) reader structure"] +impl crate::Readable for RXF1C_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf1c::W`](W) writer structure"] impl crate::Writable for RXF1C_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1s.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1s.rs index 6ee6ccce..00e5a0b2 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1s.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/rxf1s.rs @@ -1,18 +1,5 @@ #[doc = "Register `RXF1S` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `F1FL` reader - Receive FIFO 1 Fill Level"] pub type F1FL_R = crate::FieldReader; #[doc = "Field `F1GI` reader - Receive FIFO 1 Get Index"] @@ -59,22 +46,22 @@ impl DMS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `IDLE`"] + #[doc = "Idle state, wait for reception of debug messages, DMA request is cleared."] #[inline(always)] pub fn is_idle(&self) -> bool { *self == DMSSELECT_A::IDLE } - #[doc = "Checks if the value of the field is `MSG_A`"] + #[doc = "Debug message A received."] #[inline(always)] pub fn is_msg_a(&self) -> bool { *self == DMSSELECT_A::MSG_A } - #[doc = "Checks if the value of the field is `MSG_AB`"] + #[doc = "Debug messages A, B received."] #[inline(always)] pub fn is_msg_ab(&self) -> bool { *self == DMSSELECT_A::MSG_AB } - #[doc = "Checks if the value of the field is `MSG_ABC`"] + #[doc = "Debug messages A, B, C received, DMA request is set."] #[inline(always)] pub fn is_msg_abc(&self) -> bool { *self == DMSSELECT_A::MSG_ABC @@ -112,15 +99,13 @@ impl R { DMS_R::new(((self.bits >> 30) & 3) as u8) } } -#[doc = "Receive FIFO 1 Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxf1s](index.html) module"] +#[doc = "Receive FIFO 1 Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1s::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RXF1S_SPEC; impl crate::RegisterSpec for RXF1S_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rxf1s::R](R) reader structure"] -impl crate::Readable for RXF1S_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rxf1s::R`](R) reader structure"] +impl crate::Readable for RXF1S_SPEC {} #[doc = "`reset()` method sets RXF1S to value 0"] impl crate::Resettable for RXF1S_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/sidfc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/sidfc.rs index 0f4adba1..00e51502 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/sidfc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/sidfc.rs @@ -1,47 +1,15 @@ #[doc = "Register `SIDFC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SIDFC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FLSSA` reader - Filter List Standard Start Address"] pub type FLSSA_R = crate::FieldReader; #[doc = "Field `FLSSA` writer - Filter List Standard Start Address"] -pub type FLSSA_W<'a, const O: u8> = crate::FieldWriter<'a, SIDFC_SPEC, 14, O, u16>; +pub type FLSSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `LSS` reader - List Size Standard"] pub type LSS_R = crate::FieldReader; #[doc = "Field `LSS` writer - List Size Standard"] -pub type LSS_W<'a, const O: u8> = crate::FieldWriter<'a, SIDFC_SPEC, 8, O>; +pub type LSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 2:15 - Filter List Standard Start Address"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 2:15 - Filter List Standard Start Address"] #[inline(always)] #[must_use] - pub fn flssa(&mut self) -> FLSSA_W<2> { + pub fn flssa(&mut self) -> FLSSA_W { FLSSA_W::new(self) } #[doc = "Bits 16:23 - List Size Standard"] #[inline(always)] #[must_use] - pub fn lss(&mut self) -> LSS_W<16> { + pub fn lss(&mut self) -> LSS_W { LSS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Standard ID Filter Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sidfc](index.html) module"] +#[doc = "Standard ID Filter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sidfc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sidfc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SIDFC_SPEC; impl crate::RegisterSpec for SIDFC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sidfc::R](R) reader structure"] -impl crate::Readable for SIDFC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sidfc::W](W) writer structure"] +#[doc = "`read()` method returns [`sidfc::R`](R) reader structure"] +impl crate::Readable for SIDFC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sidfc::W`](W) writer structure"] impl crate::Writable for SIDFC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/tdcr.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/tdcr.rs index d5294469..acac5caa 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/tdcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/tdcr.rs @@ -1,47 +1,15 @@ #[doc = "Register `TDCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TDCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TDCF` reader - Transmitter Delay Compensation Filter"] pub type TDCF_R = crate::FieldReader; #[doc = "Field `TDCF` writer - Transmitter Delay Compensation Filter"] -pub type TDCF_W<'a, const O: u8> = crate::FieldWriter<'a, TDCR_SPEC, 7, O>; +pub type TDCF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `TDCO` reader - Transmitter Delay Compensation Offset"] pub type TDCO_R = crate::FieldReader; #[doc = "Field `TDCO` writer - Transmitter Delay Compensation Offset"] -pub type TDCO_W<'a, const O: u8> = crate::FieldWriter<'a, TDCR_SPEC, 7, O>; +pub type TDCO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter"] #[inline(always)] #[must_use] - pub fn tdcf(&mut self) -> TDCF_W<0> { + pub fn tdcf(&mut self) -> TDCF_W { TDCF_W::new(self) } #[doc = "Bits 8:14 - Transmitter Delay Compensation Offset"] #[inline(always)] #[must_use] - pub fn tdco(&mut self) -> TDCO_W<8> { + pub fn tdco(&mut self) -> TDCO_W { TDCO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Delay Compensation Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdcr](index.html) module"] +#[doc = "Transmit Delay Compensation Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TDCR_SPEC; impl crate::RegisterSpec for TDCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tdcr::R](R) reader structure"] -impl crate::Readable for TDCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tdcr::W](W) writer structure"] +#[doc = "`read()` method returns [`tdcr::R`](R) reader structure"] +impl crate::Readable for TDCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tdcr::W`](W) writer structure"] impl crate::Writable for TDCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/test.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/test.rs index 80d58337..adb82bc8 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/test.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/test.rs @@ -1,39 +1,7 @@ #[doc = "Register `TEST` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TEST` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LBCK` reader - Loop Back Mode (read/write)"] pub type LBCK_R = crate::BitReader; #[doc = "Loop Back Mode (read/write)\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl LBCK_R { true => LBCKSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Reset value. Loop Back mode is disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == LBCKSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Loop Back mode is enabled (see Section 6.1.9)."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == LBCKSELECT_A::ENABLED } } #[doc = "Field `LBCK` writer - Loop Back Mode (read/write)"] -pub type LBCK_W<'a, const O: u8> = crate::BitWriter<'a, TEST_SPEC, O, LBCKSELECT_A>; -impl<'a, const O: u8> LBCK_W<'a, O> { +pub type LBCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LBCKSELECT_A>; +impl<'a, REG, const O: u8> LBCK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Reset value. Loop Back mode is disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(LBCKSELECT_A::DISABLED) } #[doc = "Loop Back mode is enabled (see Section 6.1.9)."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(LBCKSELECT_A::ENABLED) } } @@ -120,55 +91,59 @@ impl TX_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `RESET`"] + #[doc = "Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time."] #[inline(always)] pub fn is_reset(&self) -> bool { *self == TXSELECT_A::RESET } - #[doc = "Checks if the value of the field is `SAMPLE_POINT_MONITORING`"] + #[doc = "Sample Point can be monitored at pin CANTX."] #[inline(always)] pub fn is_sample_point_monitoring(&self) -> bool { *self == TXSELECT_A::SAMPLE_POINT_MONITORING } - #[doc = "Checks if the value of the field is `DOMINANT`"] + #[doc = "Dominant ('0') level at pin CANTX."] #[inline(always)] pub fn is_dominant(&self) -> bool { *self == TXSELECT_A::DOMINANT } - #[doc = "Checks if the value of the field is `RECESSIVE`"] + #[doc = "Recessive ('1') at pin CANTX."] #[inline(always)] pub fn is_recessive(&self) -> bool { *self == TXSELECT_A::RECESSIVE } } #[doc = "Field `TX` writer - Control of Transmit Pin (read/write)"] -pub type TX_W<'a, const O: u8> = crate::FieldWriterSafe<'a, TEST_SPEC, 2, O, TXSELECT_A>; -impl<'a, const O: u8> TX_W<'a, O> { +pub type TX_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TXSELECT_A>; +impl<'a, REG, const O: u8> TX_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time."] #[inline(always)] - pub fn reset(self) -> &'a mut W { + pub fn reset(self) -> &'a mut crate::W { self.variant(TXSELECT_A::RESET) } #[doc = "Sample Point can be monitored at pin CANTX."] #[inline(always)] - pub fn sample_point_monitoring(self) -> &'a mut W { + pub fn sample_point_monitoring(self) -> &'a mut crate::W { self.variant(TXSELECT_A::SAMPLE_POINT_MONITORING) } #[doc = "Dominant ('0') level at pin CANTX."] #[inline(always)] - pub fn dominant(self) -> &'a mut W { + pub fn dominant(self) -> &'a mut crate::W { self.variant(TXSELECT_A::DOMINANT) } #[doc = "Recessive ('1') at pin CANTX."] #[inline(always)] - pub fn recessive(self) -> &'a mut W { + pub fn recessive(self) -> &'a mut crate::W { self.variant(TXSELECT_A::RECESSIVE) } } #[doc = "Field `RX` reader - Receive Pin (read-only)"] pub type RX_R = crate::BitReader; #[doc = "Field `RX` writer - Receive Pin (read-only)"] -pub type RX_W<'a, const O: u8> = crate::BitWriter<'a, TEST_SPEC, O>; +pub type RX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 4 - Loop Back Mode (read/write)"] #[inline(always)] @@ -190,40 +165,37 @@ impl W { #[doc = "Bit 4 - Loop Back Mode (read/write)"] #[inline(always)] #[must_use] - pub fn lbck(&mut self) -> LBCK_W<4> { + pub fn lbck(&mut self) -> LBCK_W { LBCK_W::new(self) } #[doc = "Bits 5:6 - Control of Transmit Pin (read/write)"] #[inline(always)] #[must_use] - pub fn tx(&mut self) -> TX_W<5> { + pub fn tx(&mut self) -> TX_W { TX_W::new(self) } #[doc = "Bit 7 - Receive Pin (read-only)"] #[inline(always)] #[must_use] - pub fn rx(&mut self) -> RX_W<7> { + pub fn rx(&mut self) -> RX_W { RX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Test Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [test](index.html) module"] +#[doc = "Test Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TEST_SPEC; impl crate::RegisterSpec for TEST_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [test::R](R) reader structure"] -impl crate::Readable for TEST_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [test::W](W) writer structure"] +#[doc = "`read()` method returns [`test::R`](R) reader structure"] +impl crate::Readable for TEST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`test::W`](W) writer structure"] impl crate::Writable for TEST_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/tocc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/tocc.rs index a92a470e..dac0589f 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/tocc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/tocc.rs @@ -1,39 +1,7 @@ #[doc = "Register `TOCC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TOCC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ETOC` reader - Enable Timeout Counter"] pub type ETOC_R = crate::BitReader; #[doc = "Enable Timeout Counter\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl ETOC_R { true => ETOCSELECT_A::TOS_CONTROLLED, } } - #[doc = "Checks if the value of the field is `NO_TIMEOUT`"] + #[doc = "Timeout Counter disabled."] #[inline(always)] pub fn is_no_timeout(&self) -> bool { *self == ETOCSELECT_A::NO_TIMEOUT } - #[doc = "Checks if the value of the field is `TOS_CONTROLLED`"] + #[doc = "Timeout Counter enabled."] #[inline(always)] pub fn is_tos_controlled(&self) -> bool { *self == ETOCSELECT_A::TOS_CONTROLLED } } #[doc = "Field `ETOC` writer - Enable Timeout Counter"] -pub type ETOC_W<'a, const O: u8> = crate::BitWriter<'a, TOCC_SPEC, O, ETOCSELECT_A>; -impl<'a, const O: u8> ETOC_W<'a, O> { +pub type ETOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ETOCSELECT_A>; +impl<'a, REG, const O: u8> ETOC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Timeout Counter disabled."] #[inline(always)] - pub fn no_timeout(self) -> &'a mut W { + pub fn no_timeout(self) -> &'a mut crate::W { self.variant(ETOCSELECT_A::NO_TIMEOUT) } #[doc = "Timeout Counter enabled."] #[inline(always)] - pub fn tos_controlled(self) -> &'a mut W { + pub fn tos_controlled(self) -> &'a mut crate::W { self.variant(ETOCSELECT_A::TOS_CONTROLLED) } } @@ -120,55 +91,59 @@ impl TOS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "Continuous operation"] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == TOSSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `TX_EV_TIMEOUT`"] + #[doc = "Timeout controlled by Tx Event FIFO"] #[inline(always)] pub fn is_tx_ev_timeout(&self) -> bool { *self == TOSSELECT_A::TX_EV_TIMEOUT } - #[doc = "Checks if the value of the field is `RX0_EV_TIMEOUT`"] + #[doc = "Timeout controlled by Receive FIFO 0"] #[inline(always)] pub fn is_rx0_ev_timeout(&self) -> bool { *self == TOSSELECT_A::RX0_EV_TIMEOUT } - #[doc = "Checks if the value of the field is `RX1_EV_TIMEOUT`"] + #[doc = "Timeout controlled by Receive FIFO 1"] #[inline(always)] pub fn is_rx1_ev_timeout(&self) -> bool { *self == TOSSELECT_A::RX1_EV_TIMEOUT } } #[doc = "Field `TOS` writer - Timeout Select"] -pub type TOS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, TOCC_SPEC, 2, O, TOSSELECT_A>; -impl<'a, const O: u8> TOS_W<'a, O> { +pub type TOS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TOSSELECT_A>; +impl<'a, REG, const O: u8> TOS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Continuous operation"] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(TOSSELECT_A::CONTINUOUS) } #[doc = "Timeout controlled by Tx Event FIFO"] #[inline(always)] - pub fn tx_ev_timeout(self) -> &'a mut W { + pub fn tx_ev_timeout(self) -> &'a mut crate::W { self.variant(TOSSELECT_A::TX_EV_TIMEOUT) } #[doc = "Timeout controlled by Receive FIFO 0"] #[inline(always)] - pub fn rx0_ev_timeout(self) -> &'a mut W { + pub fn rx0_ev_timeout(self) -> &'a mut crate::W { self.variant(TOSSELECT_A::RX0_EV_TIMEOUT) } #[doc = "Timeout controlled by Receive FIFO 1"] #[inline(always)] - pub fn rx1_ev_timeout(self) -> &'a mut W { + pub fn rx1_ev_timeout(self) -> &'a mut crate::W { self.variant(TOSSELECT_A::RX1_EV_TIMEOUT) } } #[doc = "Field `TOP` reader - Timeout Period"] pub type TOP_R = crate::FieldReader; #[doc = "Field `TOP` writer - Timeout Period"] -pub type TOP_W<'a, const O: u8> = crate::FieldWriter<'a, TOCC_SPEC, 16, O, u16>; +pub type TOP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 0 - Enable Timeout Counter"] #[inline(always)] @@ -190,40 +165,37 @@ impl W { #[doc = "Bit 0 - Enable Timeout Counter"] #[inline(always)] #[must_use] - pub fn etoc(&mut self) -> ETOC_W<0> { + pub fn etoc(&mut self) -> ETOC_W { ETOC_W::new(self) } #[doc = "Bits 1:2 - Timeout Select"] #[inline(always)] #[must_use] - pub fn tos(&mut self) -> TOS_W<1> { + pub fn tos(&mut self) -> TOS_W { TOS_W::new(self) } #[doc = "Bits 16:31 - Timeout Period"] #[inline(always)] #[must_use] - pub fn top(&mut self) -> TOP_W<16> { + pub fn top(&mut self) -> TOP_W { TOP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Timeout Counter Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocc](index.html) module"] +#[doc = "Timeout Counter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TOCC_SPEC; impl crate::RegisterSpec for TOCC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tocc::R](R) reader structure"] -impl crate::Readable for TOCC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tocc::W](W) writer structure"] +#[doc = "`read()` method returns [`tocc::R`](R) reader structure"] +impl crate::Readable for TOCC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tocc::W`](W) writer structure"] impl crate::Writable for TOCC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/tocv.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/tocv.rs index c206c491..d007cc98 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/tocv.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/tocv.rs @@ -1,43 +1,11 @@ #[doc = "Register `TOCV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TOCV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TOC` reader - Timeout Counter (cleared on write)"] pub type TOC_R = crate::FieldReader; #[doc = "Field `TOC` writer - Timeout Counter (cleared on write)"] -pub type TOC_W<'a, const O: u8> = crate::FieldWriter<'a, TOCV_SPEC, 16, O, u16>; +pub type TOC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Timeout Counter (cleared on write)"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Timeout Counter (cleared on write)"] #[inline(always)] #[must_use] - pub fn toc(&mut self) -> TOC_W<0> { + pub fn toc(&mut self) -> TOC_W { TOC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Timeout Counter Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tocv](index.html) module"] +#[doc = "Timeout Counter Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TOCV_SPEC; impl crate::RegisterSpec for TOCV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tocv::R](R) reader structure"] -impl crate::Readable for TOCV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tocv::W](W) writer structure"] +#[doc = "`read()` method returns [`tocv::R`](R) reader structure"] +impl crate::Readable for TOCV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tocv::W`](W) writer structure"] impl crate::Writable for TOCV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/tscc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/tscc.rs index ea15e4a7..f25c68a1 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/tscc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/tscc.rs @@ -1,39 +1,7 @@ #[doc = "Register `TSCC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSCC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TSS` reader - Timestamp Select"] pub type TSS_R = crate::FieldReader; #[doc = "Timestamp Select\n\nValue on reset: 0"] @@ -67,45 +35,49 @@ impl TSS_R { _ => None, } } - #[doc = "Checks if the value of the field is `ALWAYS_0`"] + #[doc = "Timestamp counter value always 0x0000"] #[inline(always)] pub fn is_always_0(&self) -> bool { *self == TSSSELECT_A::ALWAYS_0 } - #[doc = "Checks if the value of the field is `TCP_INC`"] + #[doc = "Timestamp counter value incremented according to TCP"] #[inline(always)] pub fn is_tcp_inc(&self) -> bool { *self == TSSSELECT_A::TCP_INC } - #[doc = "Checks if the value of the field is `EXT_TIMESTAMP`"] + #[doc = "External timestamp counter value used"] #[inline(always)] pub fn is_ext_timestamp(&self) -> bool { *self == TSSSELECT_A::EXT_TIMESTAMP } } #[doc = "Field `TSS` writer - Timestamp Select"] -pub type TSS_W<'a, const O: u8> = crate::FieldWriter<'a, TSCC_SPEC, 2, O, TSSSELECT_A>; -impl<'a, const O: u8> TSS_W<'a, O> { +pub type TSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TSSSELECT_A>; +impl<'a, REG, const O: u8> TSS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Timestamp counter value always 0x0000"] #[inline(always)] - pub fn always_0(self) -> &'a mut W { + pub fn always_0(self) -> &'a mut crate::W { self.variant(TSSSELECT_A::ALWAYS_0) } #[doc = "Timestamp counter value incremented according to TCP"] #[inline(always)] - pub fn tcp_inc(self) -> &'a mut W { + pub fn tcp_inc(self) -> &'a mut crate::W { self.variant(TSSSELECT_A::TCP_INC) } #[doc = "External timestamp counter value used"] #[inline(always)] - pub fn ext_timestamp(self) -> &'a mut W { + pub fn ext_timestamp(self) -> &'a mut crate::W { self.variant(TSSSELECT_A::EXT_TIMESTAMP) } } #[doc = "Field `TCP` reader - Timestamp Counter Prescaler"] pub type TCP_R = crate::FieldReader; #[doc = "Field `TCP` writer - Timestamp Counter Prescaler"] -pub type TCP_W<'a, const O: u8> = crate::FieldWriter<'a, TSCC_SPEC, 4, O>; +pub type TCP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:1 - Timestamp Select"] #[inline(always)] @@ -122,34 +94,31 @@ impl W { #[doc = "Bits 0:1 - Timestamp Select"] #[inline(always)] #[must_use] - pub fn tss(&mut self) -> TSS_W<0> { + pub fn tss(&mut self) -> TSS_W { TSS_W::new(self) } #[doc = "Bits 16:19 - Timestamp Counter Prescaler"] #[inline(always)] #[must_use] - pub fn tcp(&mut self) -> TCP_W<16> { + pub fn tcp(&mut self) -> TCP_W { TCP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Timestamp Counter Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscc](index.html) module"] +#[doc = "Timestamp Counter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSCC_SPEC; impl crate::RegisterSpec for TSCC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tscc::R](R) reader structure"] -impl crate::Readable for TSCC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tscc::W](W) writer structure"] +#[doc = "`read()` method returns [`tscc::R`](R) reader structure"] +impl crate::Readable for TSCC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tscc::W`](W) writer structure"] impl crate::Writable for TSCC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/tscv.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/tscv.rs index ef9437f7..a6ed82e7 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/tscv.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/tscv.rs @@ -1,43 +1,11 @@ #[doc = "Register `TSCV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSCV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TSC` reader - Timestamp Counter (cleared on write)"] pub type TSC_R = crate::FieldReader; #[doc = "Field `TSC` writer - Timestamp Counter (cleared on write)"] -pub type TSC_W<'a, const O: u8> = crate::FieldWriter<'a, TSCV_SPEC, 16, O, u16>; +pub type TSC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Timestamp Counter (cleared on write)"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Timestamp Counter (cleared on write)"] #[inline(always)] #[must_use] - pub fn tsc(&mut self) -> TSC_W<0> { + pub fn tsc(&mut self) -> TSC_W { TSC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Timestamp Counter Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tscv](index.html) module"] +#[doc = "Timestamp Counter Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSCV_SPEC; impl crate::RegisterSpec for TSCV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tscv::R](R) reader structure"] -impl crate::Readable for TSCV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tscv::W](W) writer structure"] +#[doc = "`read()` method returns [`tscv::R`](R) reader structure"] +impl crate::Readable for TSCV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tscv::W`](W) writer structure"] impl crate::Writable for TSCV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbar.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbar.rs index 1b600ca2..d8adaff4 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbar.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbar.rs @@ -1,167 +1,135 @@ #[doc = "Register `TXBAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXBAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `AR0` reader - Add Request for Transmit Buffer 0"] pub type AR0_R = crate::BitReader; #[doc = "Field `AR0` writer - Add Request for Transmit Buffer 0"] -pub type AR0_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR1` reader - Add Request for Transmit Buffer 1"] pub type AR1_R = crate::BitReader; #[doc = "Field `AR1` writer - Add Request for Transmit Buffer 1"] -pub type AR1_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR2` reader - Add Request for Transmit Buffer 2"] pub type AR2_R = crate::BitReader; #[doc = "Field `AR2` writer - Add Request for Transmit Buffer 2"] -pub type AR2_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR3` reader - Add Request for Transmit Buffer 3"] pub type AR3_R = crate::BitReader; #[doc = "Field `AR3` writer - Add Request for Transmit Buffer 3"] -pub type AR3_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR4` reader - Add Request for Transmit Buffer 4"] pub type AR4_R = crate::BitReader; #[doc = "Field `AR4` writer - Add Request for Transmit Buffer 4"] -pub type AR4_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR5` reader - Add Request for Transmit Buffer 5"] pub type AR5_R = crate::BitReader; #[doc = "Field `AR5` writer - Add Request for Transmit Buffer 5"] -pub type AR5_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR6` reader - Add Request for Transmit Buffer 6"] pub type AR6_R = crate::BitReader; #[doc = "Field `AR6` writer - Add Request for Transmit Buffer 6"] -pub type AR6_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR7` reader - Add Request for Transmit Buffer 7"] pub type AR7_R = crate::BitReader; #[doc = "Field `AR7` writer - Add Request for Transmit Buffer 7"] -pub type AR7_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR8` reader - Add Request for Transmit Buffer 8"] pub type AR8_R = crate::BitReader; #[doc = "Field `AR8` writer - Add Request for Transmit Buffer 8"] -pub type AR8_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR9` reader - Add Request for Transmit Buffer 9"] pub type AR9_R = crate::BitReader; #[doc = "Field `AR9` writer - Add Request for Transmit Buffer 9"] -pub type AR9_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR10` reader - Add Request for Transmit Buffer 10"] pub type AR10_R = crate::BitReader; #[doc = "Field `AR10` writer - Add Request for Transmit Buffer 10"] -pub type AR10_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR11` reader - Add Request for Transmit Buffer 11"] pub type AR11_R = crate::BitReader; #[doc = "Field `AR11` writer - Add Request for Transmit Buffer 11"] -pub type AR11_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR12` reader - Add Request for Transmit Buffer 12"] pub type AR12_R = crate::BitReader; #[doc = "Field `AR12` writer - Add Request for Transmit Buffer 12"] -pub type AR12_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR13` reader - Add Request for Transmit Buffer 13"] pub type AR13_R = crate::BitReader; #[doc = "Field `AR13` writer - Add Request for Transmit Buffer 13"] -pub type AR13_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR14` reader - Add Request for Transmit Buffer 14"] pub type AR14_R = crate::BitReader; #[doc = "Field `AR14` writer - Add Request for Transmit Buffer 14"] -pub type AR14_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR15` reader - Add Request for Transmit Buffer 15"] pub type AR15_R = crate::BitReader; #[doc = "Field `AR15` writer - Add Request for Transmit Buffer 15"] -pub type AR15_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR16` reader - Add Request for Transmit Buffer 16"] pub type AR16_R = crate::BitReader; #[doc = "Field `AR16` writer - Add Request for Transmit Buffer 16"] -pub type AR16_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR17` reader - Add Request for Transmit Buffer 17"] pub type AR17_R = crate::BitReader; #[doc = "Field `AR17` writer - Add Request for Transmit Buffer 17"] -pub type AR17_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR18` reader - Add Request for Transmit Buffer 18"] pub type AR18_R = crate::BitReader; #[doc = "Field `AR18` writer - Add Request for Transmit Buffer 18"] -pub type AR18_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR19` reader - Add Request for Transmit Buffer 19"] pub type AR19_R = crate::BitReader; #[doc = "Field `AR19` writer - Add Request for Transmit Buffer 19"] -pub type AR19_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR20` reader - Add Request for Transmit Buffer 20"] pub type AR20_R = crate::BitReader; #[doc = "Field `AR20` writer - Add Request for Transmit Buffer 20"] -pub type AR20_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR21` reader - Add Request for Transmit Buffer 21"] pub type AR21_R = crate::BitReader; #[doc = "Field `AR21` writer - Add Request for Transmit Buffer 21"] -pub type AR21_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR22` reader - Add Request for Transmit Buffer 22"] pub type AR22_R = crate::BitReader; #[doc = "Field `AR22` writer - Add Request for Transmit Buffer 22"] -pub type AR22_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR23` reader - Add Request for Transmit Buffer 23"] pub type AR23_R = crate::BitReader; #[doc = "Field `AR23` writer - Add Request for Transmit Buffer 23"] -pub type AR23_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR24` reader - Add Request for Transmit Buffer 24"] pub type AR24_R = crate::BitReader; #[doc = "Field `AR24` writer - Add Request for Transmit Buffer 24"] -pub type AR24_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR25` reader - Add Request for Transmit Buffer 25"] pub type AR25_R = crate::BitReader; #[doc = "Field `AR25` writer - Add Request for Transmit Buffer 25"] -pub type AR25_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR26` reader - Add Request for Transmit Buffer 26"] pub type AR26_R = crate::BitReader; #[doc = "Field `AR26` writer - Add Request for Transmit Buffer 26"] -pub type AR26_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR27` reader - Add Request for Transmit Buffer 27"] pub type AR27_R = crate::BitReader; #[doc = "Field `AR27` writer - Add Request for Transmit Buffer 27"] -pub type AR27_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR28` reader - Add Request for Transmit Buffer 28"] pub type AR28_R = crate::BitReader; #[doc = "Field `AR28` writer - Add Request for Transmit Buffer 28"] -pub type AR28_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR29` reader - Add Request for Transmit Buffer 29"] pub type AR29_R = crate::BitReader; #[doc = "Field `AR29` writer - Add Request for Transmit Buffer 29"] -pub type AR29_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR30` reader - Add Request for Transmit Buffer 30"] pub type AR30_R = crate::BitReader; #[doc = "Field `AR30` writer - Add Request for Transmit Buffer 30"] -pub type AR30_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AR31` reader - Add Request for Transmit Buffer 31"] pub type AR31_R = crate::BitReader; #[doc = "Field `AR31` writer - Add Request for Transmit Buffer 31"] -pub type AR31_W<'a, const O: u8> = crate::BitWriter<'a, TXBAR_SPEC, O>; +pub type AR31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Add Request for Transmit Buffer 0"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Add Request for Transmit Buffer 0"] #[inline(always)] #[must_use] - pub fn ar0(&mut self) -> AR0_W<0> { + pub fn ar0(&mut self) -> AR0_W { AR0_W::new(self) } #[doc = "Bit 1 - Add Request for Transmit Buffer 1"] #[inline(always)] #[must_use] - pub fn ar1(&mut self) -> AR1_W<1> { + pub fn ar1(&mut self) -> AR1_W { AR1_W::new(self) } #[doc = "Bit 2 - Add Request for Transmit Buffer 2"] #[inline(always)] #[must_use] - pub fn ar2(&mut self) -> AR2_W<2> { + pub fn ar2(&mut self) -> AR2_W { AR2_W::new(self) } #[doc = "Bit 3 - Add Request for Transmit Buffer 3"] #[inline(always)] #[must_use] - pub fn ar3(&mut self) -> AR3_W<3> { + pub fn ar3(&mut self) -> AR3_W { AR3_W::new(self) } #[doc = "Bit 4 - Add Request for Transmit Buffer 4"] #[inline(always)] #[must_use] - pub fn ar4(&mut self) -> AR4_W<4> { + pub fn ar4(&mut self) -> AR4_W { AR4_W::new(self) } #[doc = "Bit 5 - Add Request for Transmit Buffer 5"] #[inline(always)] #[must_use] - pub fn ar5(&mut self) -> AR5_W<5> { + pub fn ar5(&mut self) -> AR5_W { AR5_W::new(self) } #[doc = "Bit 6 - Add Request for Transmit Buffer 6"] #[inline(always)] #[must_use] - pub fn ar6(&mut self) -> AR6_W<6> { + pub fn ar6(&mut self) -> AR6_W { AR6_W::new(self) } #[doc = "Bit 7 - Add Request for Transmit Buffer 7"] #[inline(always)] #[must_use] - pub fn ar7(&mut self) -> AR7_W<7> { + pub fn ar7(&mut self) -> AR7_W { AR7_W::new(self) } #[doc = "Bit 8 - Add Request for Transmit Buffer 8"] #[inline(always)] #[must_use] - pub fn ar8(&mut self) -> AR8_W<8> { + pub fn ar8(&mut self) -> AR8_W { AR8_W::new(self) } #[doc = "Bit 9 - Add Request for Transmit Buffer 9"] #[inline(always)] #[must_use] - pub fn ar9(&mut self) -> AR9_W<9> { + pub fn ar9(&mut self) -> AR9_W { AR9_W::new(self) } #[doc = "Bit 10 - Add Request for Transmit Buffer 10"] #[inline(always)] #[must_use] - pub fn ar10(&mut self) -> AR10_W<10> { + pub fn ar10(&mut self) -> AR10_W { AR10_W::new(self) } #[doc = "Bit 11 - Add Request for Transmit Buffer 11"] #[inline(always)] #[must_use] - pub fn ar11(&mut self) -> AR11_W<11> { + pub fn ar11(&mut self) -> AR11_W { AR11_W::new(self) } #[doc = "Bit 12 - Add Request for Transmit Buffer 12"] #[inline(always)] #[must_use] - pub fn ar12(&mut self) -> AR12_W<12> { + pub fn ar12(&mut self) -> AR12_W { AR12_W::new(self) } #[doc = "Bit 13 - Add Request for Transmit Buffer 13"] #[inline(always)] #[must_use] - pub fn ar13(&mut self) -> AR13_W<13> { + pub fn ar13(&mut self) -> AR13_W { AR13_W::new(self) } #[doc = "Bit 14 - Add Request for Transmit Buffer 14"] #[inline(always)] #[must_use] - pub fn ar14(&mut self) -> AR14_W<14> { + pub fn ar14(&mut self) -> AR14_W { AR14_W::new(self) } #[doc = "Bit 15 - Add Request for Transmit Buffer 15"] #[inline(always)] #[must_use] - pub fn ar15(&mut self) -> AR15_W<15> { + pub fn ar15(&mut self) -> AR15_W { AR15_W::new(self) } #[doc = "Bit 16 - Add Request for Transmit Buffer 16"] #[inline(always)] #[must_use] - pub fn ar16(&mut self) -> AR16_W<16> { + pub fn ar16(&mut self) -> AR16_W { AR16_W::new(self) } #[doc = "Bit 17 - Add Request for Transmit Buffer 17"] #[inline(always)] #[must_use] - pub fn ar17(&mut self) -> AR17_W<17> { + pub fn ar17(&mut self) -> AR17_W { AR17_W::new(self) } #[doc = "Bit 18 - Add Request for Transmit Buffer 18"] #[inline(always)] #[must_use] - pub fn ar18(&mut self) -> AR18_W<18> { + pub fn ar18(&mut self) -> AR18_W { AR18_W::new(self) } #[doc = "Bit 19 - Add Request for Transmit Buffer 19"] #[inline(always)] #[must_use] - pub fn ar19(&mut self) -> AR19_W<19> { + pub fn ar19(&mut self) -> AR19_W { AR19_W::new(self) } #[doc = "Bit 20 - Add Request for Transmit Buffer 20"] #[inline(always)] #[must_use] - pub fn ar20(&mut self) -> AR20_W<20> { + pub fn ar20(&mut self) -> AR20_W { AR20_W::new(self) } #[doc = "Bit 21 - Add Request for Transmit Buffer 21"] #[inline(always)] #[must_use] - pub fn ar21(&mut self) -> AR21_W<21> { + pub fn ar21(&mut self) -> AR21_W { AR21_W::new(self) } #[doc = "Bit 22 - Add Request for Transmit Buffer 22"] #[inline(always)] #[must_use] - pub fn ar22(&mut self) -> AR22_W<22> { + pub fn ar22(&mut self) -> AR22_W { AR22_W::new(self) } #[doc = "Bit 23 - Add Request for Transmit Buffer 23"] #[inline(always)] #[must_use] - pub fn ar23(&mut self) -> AR23_W<23> { + pub fn ar23(&mut self) -> AR23_W { AR23_W::new(self) } #[doc = "Bit 24 - Add Request for Transmit Buffer 24"] #[inline(always)] #[must_use] - pub fn ar24(&mut self) -> AR24_W<24> { + pub fn ar24(&mut self) -> AR24_W { AR24_W::new(self) } #[doc = "Bit 25 - Add Request for Transmit Buffer 25"] #[inline(always)] #[must_use] - pub fn ar25(&mut self) -> AR25_W<25> { + pub fn ar25(&mut self) -> AR25_W { AR25_W::new(self) } #[doc = "Bit 26 - Add Request for Transmit Buffer 26"] #[inline(always)] #[must_use] - pub fn ar26(&mut self) -> AR26_W<26> { + pub fn ar26(&mut self) -> AR26_W { AR26_W::new(self) } #[doc = "Bit 27 - Add Request for Transmit Buffer 27"] #[inline(always)] #[must_use] - pub fn ar27(&mut self) -> AR27_W<27> { + pub fn ar27(&mut self) -> AR27_W { AR27_W::new(self) } #[doc = "Bit 28 - Add Request for Transmit Buffer 28"] #[inline(always)] #[must_use] - pub fn ar28(&mut self) -> AR28_W<28> { + pub fn ar28(&mut self) -> AR28_W { AR28_W::new(self) } #[doc = "Bit 29 - Add Request for Transmit Buffer 29"] #[inline(always)] #[must_use] - pub fn ar29(&mut self) -> AR29_W<29> { + pub fn ar29(&mut self) -> AR29_W { AR29_W::new(self) } #[doc = "Bit 30 - Add Request for Transmit Buffer 30"] #[inline(always)] #[must_use] - pub fn ar30(&mut self) -> AR30_W<30> { + pub fn ar30(&mut self) -> AR30_W { AR30_W::new(self) } #[doc = "Bit 31 - Add Request for Transmit Buffer 31"] #[inline(always)] #[must_use] - pub fn ar31(&mut self) -> AR31_W<31> { + pub fn ar31(&mut self) -> AR31_W { AR31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Add Request Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbar](index.html) module"] +#[doc = "Transmit Buffer Add Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBAR_SPEC; impl crate::RegisterSpec for TXBAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbar::R](R) reader structure"] -impl crate::Readable for TXBAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txbar::W](W) writer structure"] +#[doc = "`read()` method returns [`txbar::R`](R) reader structure"] +impl crate::Readable for TXBAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbar::W`](W) writer structure"] impl crate::Writable for TXBAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbc.rs index a0f921cb..c6eef35b 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbc.rs @@ -1,55 +1,23 @@ #[doc = "Register `TXBC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXBC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TBSA` reader - Tx Buffers Start Address"] pub type TBSA_R = crate::FieldReader; #[doc = "Field `TBSA` writer - Tx Buffers Start Address"] -pub type TBSA_W<'a, const O: u8> = crate::FieldWriter<'a, TXBC_SPEC, 14, O, u16>; +pub type TBSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `NDTB` reader - Number of Dedicated Transmit Buffers"] pub type NDTB_R = crate::FieldReader; #[doc = "Field `NDTB` writer - Number of Dedicated Transmit Buffers"] -pub type NDTB_W<'a, const O: u8> = crate::FieldWriter<'a, TXBC_SPEC, 6, O>; +pub type NDTB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `TFQS` reader - Transmit FIFO/Queue Size"] pub type TFQS_R = crate::FieldReader; #[doc = "Field `TFQS` writer - Transmit FIFO/Queue Size"] -pub type TFQS_W<'a, const O: u8> = crate::FieldWriter<'a, TXBC_SPEC, 6, O>; +pub type TFQS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `TFQM` reader - Tx FIFO/Queue Mode"] pub type TFQM_R = crate::BitReader; #[doc = "Field `TFQM` writer - Tx FIFO/Queue Mode"] -pub type TFQM_W<'a, const O: u8> = crate::BitWriter<'a, TXBC_SPEC, O>; +pub type TFQM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 2:15 - Tx Buffers Start Address"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 2:15 - Tx Buffers Start Address"] #[inline(always)] #[must_use] - pub fn tbsa(&mut self) -> TBSA_W<2> { + pub fn tbsa(&mut self) -> TBSA_W { TBSA_W::new(self) } #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers"] #[inline(always)] #[must_use] - pub fn ndtb(&mut self) -> NDTB_W<16> { + pub fn ndtb(&mut self) -> NDTB_W { NDTB_W::new(self) } #[doc = "Bits 24:29 - Transmit FIFO/Queue Size"] #[inline(always)] #[must_use] - pub fn tfqs(&mut self) -> TFQS_W<24> { + pub fn tfqs(&mut self) -> TFQS_W { TFQS_W::new(self) } #[doc = "Bit 30 - Tx FIFO/Queue Mode"] #[inline(always)] #[must_use] - pub fn tfqm(&mut self) -> TFQM_W<30> { + pub fn tfqm(&mut self) -> TFQM_W { TFQM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbc](index.html) module"] +#[doc = "Transmit Buffer Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBC_SPEC; impl crate::RegisterSpec for TXBC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbc::R](R) reader structure"] -impl crate::Readable for TXBC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txbc::W](W) writer structure"] +#[doc = "`read()` method returns [`txbc::R`](R) reader structure"] +impl crate::Readable for TXBC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbc::W`](W) writer structure"] impl crate::Writable for TXBC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbcf.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbcf.rs index 1a9e13aa..d5fa9b40 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbcf.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbcf.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXBCF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CF0` reader - Cancellation Finished for Transmit Buffer 0"] pub type CF0_R = crate::BitReader; #[doc = "Field `CF1` reader - Cancellation Finished for Transmit Buffer 1"] @@ -239,15 +226,13 @@ impl R { CF31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Transmit Buffer Cancellation Finished Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcf](index.html) module"] +#[doc = "Transmit Buffer Cancellation Finished Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcf::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBCF_SPEC; impl crate::RegisterSpec for TXBCF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbcf::R](R) reader structure"] -impl crate::Readable for TXBCF_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txbcf::R`](R) reader structure"] +impl crate::Readable for TXBCF_SPEC {} #[doc = "`reset()` method sets TXBCF to value 0"] impl crate::Resettable for TXBCF_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbcie.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbcie.rs index ea65c466..9656d572 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbcie.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbcie.rs @@ -1,167 +1,135 @@ #[doc = "Register `TXBCIE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXBCIE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CFIE0` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 0"] pub type CFIE0_R = crate::BitReader; #[doc = "Field `CFIE0` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 0"] -pub type CFIE0_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE1` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 1"] pub type CFIE1_R = crate::BitReader; #[doc = "Field `CFIE1` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 1"] -pub type CFIE1_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE2` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 2"] pub type CFIE2_R = crate::BitReader; #[doc = "Field `CFIE2` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 2"] -pub type CFIE2_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE3` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 3"] pub type CFIE3_R = crate::BitReader; #[doc = "Field `CFIE3` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 3"] -pub type CFIE3_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE4` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 4"] pub type CFIE4_R = crate::BitReader; #[doc = "Field `CFIE4` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 4"] -pub type CFIE4_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE5` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 5"] pub type CFIE5_R = crate::BitReader; #[doc = "Field `CFIE5` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 5"] -pub type CFIE5_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE6` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 6"] pub type CFIE6_R = crate::BitReader; #[doc = "Field `CFIE6` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 6"] -pub type CFIE6_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE7` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 7"] pub type CFIE7_R = crate::BitReader; #[doc = "Field `CFIE7` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 7"] -pub type CFIE7_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE8` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 8"] pub type CFIE8_R = crate::BitReader; #[doc = "Field `CFIE8` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 8"] -pub type CFIE8_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE9` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 9"] pub type CFIE9_R = crate::BitReader; #[doc = "Field `CFIE9` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 9"] -pub type CFIE9_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE10` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 10"] pub type CFIE10_R = crate::BitReader; #[doc = "Field `CFIE10` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 10"] -pub type CFIE10_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE11` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 11"] pub type CFIE11_R = crate::BitReader; #[doc = "Field `CFIE11` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 11"] -pub type CFIE11_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE12` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 12"] pub type CFIE12_R = crate::BitReader; #[doc = "Field `CFIE12` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 12"] -pub type CFIE12_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE13` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 13"] pub type CFIE13_R = crate::BitReader; #[doc = "Field `CFIE13` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 13"] -pub type CFIE13_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE14` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 14"] pub type CFIE14_R = crate::BitReader; #[doc = "Field `CFIE14` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 14"] -pub type CFIE14_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE15` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 15"] pub type CFIE15_R = crate::BitReader; #[doc = "Field `CFIE15` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 15"] -pub type CFIE15_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE16` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 16"] pub type CFIE16_R = crate::BitReader; #[doc = "Field `CFIE16` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 16"] -pub type CFIE16_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE17` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 17"] pub type CFIE17_R = crate::BitReader; #[doc = "Field `CFIE17` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 17"] -pub type CFIE17_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE18` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 18"] pub type CFIE18_R = crate::BitReader; #[doc = "Field `CFIE18` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 18"] -pub type CFIE18_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE19` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 19"] pub type CFIE19_R = crate::BitReader; #[doc = "Field `CFIE19` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 19"] -pub type CFIE19_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE20` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 20"] pub type CFIE20_R = crate::BitReader; #[doc = "Field `CFIE20` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 20"] -pub type CFIE20_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE21` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 21"] pub type CFIE21_R = crate::BitReader; #[doc = "Field `CFIE21` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 21"] -pub type CFIE21_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE22` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 22"] pub type CFIE22_R = crate::BitReader; #[doc = "Field `CFIE22` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 22"] -pub type CFIE22_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE23` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 23"] pub type CFIE23_R = crate::BitReader; #[doc = "Field `CFIE23` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 23"] -pub type CFIE23_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE24` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 24"] pub type CFIE24_R = crate::BitReader; #[doc = "Field `CFIE24` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 24"] -pub type CFIE24_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE25` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 25"] pub type CFIE25_R = crate::BitReader; #[doc = "Field `CFIE25` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 25"] -pub type CFIE25_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE26` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 26"] pub type CFIE26_R = crate::BitReader; #[doc = "Field `CFIE26` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 26"] -pub type CFIE26_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE27` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 27"] pub type CFIE27_R = crate::BitReader; #[doc = "Field `CFIE27` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 27"] -pub type CFIE27_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE28` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 28"] pub type CFIE28_R = crate::BitReader; #[doc = "Field `CFIE28` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 28"] -pub type CFIE28_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE29` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 29"] pub type CFIE29_R = crate::BitReader; #[doc = "Field `CFIE29` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 29"] -pub type CFIE29_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE30` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 30"] pub type CFIE30_R = crate::BitReader; #[doc = "Field `CFIE30` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 30"] -pub type CFIE30_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFIE31` reader - Cancellation Finished Interrupt Enable for Transmit Buffer 31"] pub type CFIE31_R = crate::BitReader; #[doc = "Field `CFIE31` writer - Cancellation Finished Interrupt Enable for Transmit Buffer 31"] -pub type CFIE31_W<'a, const O: u8> = crate::BitWriter<'a, TXBCIE_SPEC, O>; +pub type CFIE31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Cancellation Finished Interrupt Enable for Transmit Buffer 0"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Cancellation Finished Interrupt Enable for Transmit Buffer 0"] #[inline(always)] #[must_use] - pub fn cfie0(&mut self) -> CFIE0_W<0> { + pub fn cfie0(&mut self) -> CFIE0_W { CFIE0_W::new(self) } #[doc = "Bit 1 - Cancellation Finished Interrupt Enable for Transmit Buffer 1"] #[inline(always)] #[must_use] - pub fn cfie1(&mut self) -> CFIE1_W<1> { + pub fn cfie1(&mut self) -> CFIE1_W { CFIE1_W::new(self) } #[doc = "Bit 2 - Cancellation Finished Interrupt Enable for Transmit Buffer 2"] #[inline(always)] #[must_use] - pub fn cfie2(&mut self) -> CFIE2_W<2> { + pub fn cfie2(&mut self) -> CFIE2_W { CFIE2_W::new(self) } #[doc = "Bit 3 - Cancellation Finished Interrupt Enable for Transmit Buffer 3"] #[inline(always)] #[must_use] - pub fn cfie3(&mut self) -> CFIE3_W<3> { + pub fn cfie3(&mut self) -> CFIE3_W { CFIE3_W::new(self) } #[doc = "Bit 4 - Cancellation Finished Interrupt Enable for Transmit Buffer 4"] #[inline(always)] #[must_use] - pub fn cfie4(&mut self) -> CFIE4_W<4> { + pub fn cfie4(&mut self) -> CFIE4_W { CFIE4_W::new(self) } #[doc = "Bit 5 - Cancellation Finished Interrupt Enable for Transmit Buffer 5"] #[inline(always)] #[must_use] - pub fn cfie5(&mut self) -> CFIE5_W<5> { + pub fn cfie5(&mut self) -> CFIE5_W { CFIE5_W::new(self) } #[doc = "Bit 6 - Cancellation Finished Interrupt Enable for Transmit Buffer 6"] #[inline(always)] #[must_use] - pub fn cfie6(&mut self) -> CFIE6_W<6> { + pub fn cfie6(&mut self) -> CFIE6_W { CFIE6_W::new(self) } #[doc = "Bit 7 - Cancellation Finished Interrupt Enable for Transmit Buffer 7"] #[inline(always)] #[must_use] - pub fn cfie7(&mut self) -> CFIE7_W<7> { + pub fn cfie7(&mut self) -> CFIE7_W { CFIE7_W::new(self) } #[doc = "Bit 8 - Cancellation Finished Interrupt Enable for Transmit Buffer 8"] #[inline(always)] #[must_use] - pub fn cfie8(&mut self) -> CFIE8_W<8> { + pub fn cfie8(&mut self) -> CFIE8_W { CFIE8_W::new(self) } #[doc = "Bit 9 - Cancellation Finished Interrupt Enable for Transmit Buffer 9"] #[inline(always)] #[must_use] - pub fn cfie9(&mut self) -> CFIE9_W<9> { + pub fn cfie9(&mut self) -> CFIE9_W { CFIE9_W::new(self) } #[doc = "Bit 10 - Cancellation Finished Interrupt Enable for Transmit Buffer 10"] #[inline(always)] #[must_use] - pub fn cfie10(&mut self) -> CFIE10_W<10> { + pub fn cfie10(&mut self) -> CFIE10_W { CFIE10_W::new(self) } #[doc = "Bit 11 - Cancellation Finished Interrupt Enable for Transmit Buffer 11"] #[inline(always)] #[must_use] - pub fn cfie11(&mut self) -> CFIE11_W<11> { + pub fn cfie11(&mut self) -> CFIE11_W { CFIE11_W::new(self) } #[doc = "Bit 12 - Cancellation Finished Interrupt Enable for Transmit Buffer 12"] #[inline(always)] #[must_use] - pub fn cfie12(&mut self) -> CFIE12_W<12> { + pub fn cfie12(&mut self) -> CFIE12_W { CFIE12_W::new(self) } #[doc = "Bit 13 - Cancellation Finished Interrupt Enable for Transmit Buffer 13"] #[inline(always)] #[must_use] - pub fn cfie13(&mut self) -> CFIE13_W<13> { + pub fn cfie13(&mut self) -> CFIE13_W { CFIE13_W::new(self) } #[doc = "Bit 14 - Cancellation Finished Interrupt Enable for Transmit Buffer 14"] #[inline(always)] #[must_use] - pub fn cfie14(&mut self) -> CFIE14_W<14> { + pub fn cfie14(&mut self) -> CFIE14_W { CFIE14_W::new(self) } #[doc = "Bit 15 - Cancellation Finished Interrupt Enable for Transmit Buffer 15"] #[inline(always)] #[must_use] - pub fn cfie15(&mut self) -> CFIE15_W<15> { + pub fn cfie15(&mut self) -> CFIE15_W { CFIE15_W::new(self) } #[doc = "Bit 16 - Cancellation Finished Interrupt Enable for Transmit Buffer 16"] #[inline(always)] #[must_use] - pub fn cfie16(&mut self) -> CFIE16_W<16> { + pub fn cfie16(&mut self) -> CFIE16_W { CFIE16_W::new(self) } #[doc = "Bit 17 - Cancellation Finished Interrupt Enable for Transmit Buffer 17"] #[inline(always)] #[must_use] - pub fn cfie17(&mut self) -> CFIE17_W<17> { + pub fn cfie17(&mut self) -> CFIE17_W { CFIE17_W::new(self) } #[doc = "Bit 18 - Cancellation Finished Interrupt Enable for Transmit Buffer 18"] #[inline(always)] #[must_use] - pub fn cfie18(&mut self) -> CFIE18_W<18> { + pub fn cfie18(&mut self) -> CFIE18_W { CFIE18_W::new(self) } #[doc = "Bit 19 - Cancellation Finished Interrupt Enable for Transmit Buffer 19"] #[inline(always)] #[must_use] - pub fn cfie19(&mut self) -> CFIE19_W<19> { + pub fn cfie19(&mut self) -> CFIE19_W { CFIE19_W::new(self) } #[doc = "Bit 20 - Cancellation Finished Interrupt Enable for Transmit Buffer 20"] #[inline(always)] #[must_use] - pub fn cfie20(&mut self) -> CFIE20_W<20> { + pub fn cfie20(&mut self) -> CFIE20_W { CFIE20_W::new(self) } #[doc = "Bit 21 - Cancellation Finished Interrupt Enable for Transmit Buffer 21"] #[inline(always)] #[must_use] - pub fn cfie21(&mut self) -> CFIE21_W<21> { + pub fn cfie21(&mut self) -> CFIE21_W { CFIE21_W::new(self) } #[doc = "Bit 22 - Cancellation Finished Interrupt Enable for Transmit Buffer 22"] #[inline(always)] #[must_use] - pub fn cfie22(&mut self) -> CFIE22_W<22> { + pub fn cfie22(&mut self) -> CFIE22_W { CFIE22_W::new(self) } #[doc = "Bit 23 - Cancellation Finished Interrupt Enable for Transmit Buffer 23"] #[inline(always)] #[must_use] - pub fn cfie23(&mut self) -> CFIE23_W<23> { + pub fn cfie23(&mut self) -> CFIE23_W { CFIE23_W::new(self) } #[doc = "Bit 24 - Cancellation Finished Interrupt Enable for Transmit Buffer 24"] #[inline(always)] #[must_use] - pub fn cfie24(&mut self) -> CFIE24_W<24> { + pub fn cfie24(&mut self) -> CFIE24_W { CFIE24_W::new(self) } #[doc = "Bit 25 - Cancellation Finished Interrupt Enable for Transmit Buffer 25"] #[inline(always)] #[must_use] - pub fn cfie25(&mut self) -> CFIE25_W<25> { + pub fn cfie25(&mut self) -> CFIE25_W { CFIE25_W::new(self) } #[doc = "Bit 26 - Cancellation Finished Interrupt Enable for Transmit Buffer 26"] #[inline(always)] #[must_use] - pub fn cfie26(&mut self) -> CFIE26_W<26> { + pub fn cfie26(&mut self) -> CFIE26_W { CFIE26_W::new(self) } #[doc = "Bit 27 - Cancellation Finished Interrupt Enable for Transmit Buffer 27"] #[inline(always)] #[must_use] - pub fn cfie27(&mut self) -> CFIE27_W<27> { + pub fn cfie27(&mut self) -> CFIE27_W { CFIE27_W::new(self) } #[doc = "Bit 28 - Cancellation Finished Interrupt Enable for Transmit Buffer 28"] #[inline(always)] #[must_use] - pub fn cfie28(&mut self) -> CFIE28_W<28> { + pub fn cfie28(&mut self) -> CFIE28_W { CFIE28_W::new(self) } #[doc = "Bit 29 - Cancellation Finished Interrupt Enable for Transmit Buffer 29"] #[inline(always)] #[must_use] - pub fn cfie29(&mut self) -> CFIE29_W<29> { + pub fn cfie29(&mut self) -> CFIE29_W { CFIE29_W::new(self) } #[doc = "Bit 30 - Cancellation Finished Interrupt Enable for Transmit Buffer 30"] #[inline(always)] #[must_use] - pub fn cfie30(&mut self) -> CFIE30_W<30> { + pub fn cfie30(&mut self) -> CFIE30_W { CFIE30_W::new(self) } #[doc = "Bit 31 - Cancellation Finished Interrupt Enable for Transmit Buffer 31"] #[inline(always)] #[must_use] - pub fn cfie31(&mut self) -> CFIE31_W<31> { + pub fn cfie31(&mut self) -> CFIE31_W { CFIE31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Cancellation Finished Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcie](index.html) module"] +#[doc = "Transmit Buffer Cancellation Finished Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcie::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBCIE_SPEC; impl crate::RegisterSpec for TXBCIE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbcie::R](R) reader structure"] -impl crate::Readable for TXBCIE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txbcie::W](W) writer structure"] +#[doc = "`read()` method returns [`txbcie::R`](R) reader structure"] +impl crate::Readable for TXBCIE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbcie::W`](W) writer structure"] impl crate::Writable for TXBCIE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbcr.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbcr.rs index 2b60b9c0..93582a14 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbcr.rs @@ -1,167 +1,135 @@ #[doc = "Register `TXBCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXBCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CR0` reader - Cancellation Request for Transmit Buffer 0"] pub type CR0_R = crate::BitReader; #[doc = "Field `CR0` writer - Cancellation Request for Transmit Buffer 0"] -pub type CR0_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR1` reader - Cancellation Request for Transmit Buffer 1"] pub type CR1_R = crate::BitReader; #[doc = "Field `CR1` writer - Cancellation Request for Transmit Buffer 1"] -pub type CR1_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR2` reader - Cancellation Request for Transmit Buffer 2"] pub type CR2_R = crate::BitReader; #[doc = "Field `CR2` writer - Cancellation Request for Transmit Buffer 2"] -pub type CR2_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR3` reader - Cancellation Request for Transmit Buffer 3"] pub type CR3_R = crate::BitReader; #[doc = "Field `CR3` writer - Cancellation Request for Transmit Buffer 3"] -pub type CR3_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR4` reader - Cancellation Request for Transmit Buffer 4"] pub type CR4_R = crate::BitReader; #[doc = "Field `CR4` writer - Cancellation Request for Transmit Buffer 4"] -pub type CR4_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR5` reader - Cancellation Request for Transmit Buffer 5"] pub type CR5_R = crate::BitReader; #[doc = "Field `CR5` writer - Cancellation Request for Transmit Buffer 5"] -pub type CR5_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR6` reader - Cancellation Request for Transmit Buffer 6"] pub type CR6_R = crate::BitReader; #[doc = "Field `CR6` writer - Cancellation Request for Transmit Buffer 6"] -pub type CR6_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR7` reader - Cancellation Request for Transmit Buffer 7"] pub type CR7_R = crate::BitReader; #[doc = "Field `CR7` writer - Cancellation Request for Transmit Buffer 7"] -pub type CR7_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR8` reader - Cancellation Request for Transmit Buffer 8"] pub type CR8_R = crate::BitReader; #[doc = "Field `CR8` writer - Cancellation Request for Transmit Buffer 8"] -pub type CR8_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR9` reader - Cancellation Request for Transmit Buffer 9"] pub type CR9_R = crate::BitReader; #[doc = "Field `CR9` writer - Cancellation Request for Transmit Buffer 9"] -pub type CR9_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR10` reader - Cancellation Request for Transmit Buffer 10"] pub type CR10_R = crate::BitReader; #[doc = "Field `CR10` writer - Cancellation Request for Transmit Buffer 10"] -pub type CR10_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR11` reader - Cancellation Request for Transmit Buffer 11"] pub type CR11_R = crate::BitReader; #[doc = "Field `CR11` writer - Cancellation Request for Transmit Buffer 11"] -pub type CR11_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR12` reader - Cancellation Request for Transmit Buffer 12"] pub type CR12_R = crate::BitReader; #[doc = "Field `CR12` writer - Cancellation Request for Transmit Buffer 12"] -pub type CR12_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR13` reader - Cancellation Request for Transmit Buffer 13"] pub type CR13_R = crate::BitReader; #[doc = "Field `CR13` writer - Cancellation Request for Transmit Buffer 13"] -pub type CR13_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR14` reader - Cancellation Request for Transmit Buffer 14"] pub type CR14_R = crate::BitReader; #[doc = "Field `CR14` writer - Cancellation Request for Transmit Buffer 14"] -pub type CR14_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR15` reader - Cancellation Request for Transmit Buffer 15"] pub type CR15_R = crate::BitReader; #[doc = "Field `CR15` writer - Cancellation Request for Transmit Buffer 15"] -pub type CR15_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR16` reader - Cancellation Request for Transmit Buffer 16"] pub type CR16_R = crate::BitReader; #[doc = "Field `CR16` writer - Cancellation Request for Transmit Buffer 16"] -pub type CR16_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR17` reader - Cancellation Request for Transmit Buffer 17"] pub type CR17_R = crate::BitReader; #[doc = "Field `CR17` writer - Cancellation Request for Transmit Buffer 17"] -pub type CR17_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR18` reader - Cancellation Request for Transmit Buffer 18"] pub type CR18_R = crate::BitReader; #[doc = "Field `CR18` writer - Cancellation Request for Transmit Buffer 18"] -pub type CR18_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR19` reader - Cancellation Request for Transmit Buffer 19"] pub type CR19_R = crate::BitReader; #[doc = "Field `CR19` writer - Cancellation Request for Transmit Buffer 19"] -pub type CR19_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR20` reader - Cancellation Request for Transmit Buffer 20"] pub type CR20_R = crate::BitReader; #[doc = "Field `CR20` writer - Cancellation Request for Transmit Buffer 20"] -pub type CR20_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR21` reader - Cancellation Request for Transmit Buffer 21"] pub type CR21_R = crate::BitReader; #[doc = "Field `CR21` writer - Cancellation Request for Transmit Buffer 21"] -pub type CR21_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR22` reader - Cancellation Request for Transmit Buffer 22"] pub type CR22_R = crate::BitReader; #[doc = "Field `CR22` writer - Cancellation Request for Transmit Buffer 22"] -pub type CR22_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR23` reader - Cancellation Request for Transmit Buffer 23"] pub type CR23_R = crate::BitReader; #[doc = "Field `CR23` writer - Cancellation Request for Transmit Buffer 23"] -pub type CR23_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR24` reader - Cancellation Request for Transmit Buffer 24"] pub type CR24_R = crate::BitReader; #[doc = "Field `CR24` writer - Cancellation Request for Transmit Buffer 24"] -pub type CR24_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR25` reader - Cancellation Request for Transmit Buffer 25"] pub type CR25_R = crate::BitReader; #[doc = "Field `CR25` writer - Cancellation Request for Transmit Buffer 25"] -pub type CR25_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR26` reader - Cancellation Request for Transmit Buffer 26"] pub type CR26_R = crate::BitReader; #[doc = "Field `CR26` writer - Cancellation Request for Transmit Buffer 26"] -pub type CR26_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR27` reader - Cancellation Request for Transmit Buffer 27"] pub type CR27_R = crate::BitReader; #[doc = "Field `CR27` writer - Cancellation Request for Transmit Buffer 27"] -pub type CR27_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR28` reader - Cancellation Request for Transmit Buffer 28"] pub type CR28_R = crate::BitReader; #[doc = "Field `CR28` writer - Cancellation Request for Transmit Buffer 28"] -pub type CR28_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR29` reader - Cancellation Request for Transmit Buffer 29"] pub type CR29_R = crate::BitReader; #[doc = "Field `CR29` writer - Cancellation Request for Transmit Buffer 29"] -pub type CR29_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR30` reader - Cancellation Request for Transmit Buffer 30"] pub type CR30_R = crate::BitReader; #[doc = "Field `CR30` writer - Cancellation Request for Transmit Buffer 30"] -pub type CR30_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CR31` reader - Cancellation Request for Transmit Buffer 31"] pub type CR31_R = crate::BitReader; #[doc = "Field `CR31` writer - Cancellation Request for Transmit Buffer 31"] -pub type CR31_W<'a, const O: u8> = crate::BitWriter<'a, TXBCR_SPEC, O>; +pub type CR31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Cancellation Request for Transmit Buffer 0"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Cancellation Request for Transmit Buffer 0"] #[inline(always)] #[must_use] - pub fn cr0(&mut self) -> CR0_W<0> { + pub fn cr0(&mut self) -> CR0_W { CR0_W::new(self) } #[doc = "Bit 1 - Cancellation Request for Transmit Buffer 1"] #[inline(always)] #[must_use] - pub fn cr1(&mut self) -> CR1_W<1> { + pub fn cr1(&mut self) -> CR1_W { CR1_W::new(self) } #[doc = "Bit 2 - Cancellation Request for Transmit Buffer 2"] #[inline(always)] #[must_use] - pub fn cr2(&mut self) -> CR2_W<2> { + pub fn cr2(&mut self) -> CR2_W { CR2_W::new(self) } #[doc = "Bit 3 - Cancellation Request for Transmit Buffer 3"] #[inline(always)] #[must_use] - pub fn cr3(&mut self) -> CR3_W<3> { + pub fn cr3(&mut self) -> CR3_W { CR3_W::new(self) } #[doc = "Bit 4 - Cancellation Request for Transmit Buffer 4"] #[inline(always)] #[must_use] - pub fn cr4(&mut self) -> CR4_W<4> { + pub fn cr4(&mut self) -> CR4_W { CR4_W::new(self) } #[doc = "Bit 5 - Cancellation Request for Transmit Buffer 5"] #[inline(always)] #[must_use] - pub fn cr5(&mut self) -> CR5_W<5> { + pub fn cr5(&mut self) -> CR5_W { CR5_W::new(self) } #[doc = "Bit 6 - Cancellation Request for Transmit Buffer 6"] #[inline(always)] #[must_use] - pub fn cr6(&mut self) -> CR6_W<6> { + pub fn cr6(&mut self) -> CR6_W { CR6_W::new(self) } #[doc = "Bit 7 - Cancellation Request for Transmit Buffer 7"] #[inline(always)] #[must_use] - pub fn cr7(&mut self) -> CR7_W<7> { + pub fn cr7(&mut self) -> CR7_W { CR7_W::new(self) } #[doc = "Bit 8 - Cancellation Request for Transmit Buffer 8"] #[inline(always)] #[must_use] - pub fn cr8(&mut self) -> CR8_W<8> { + pub fn cr8(&mut self) -> CR8_W { CR8_W::new(self) } #[doc = "Bit 9 - Cancellation Request for Transmit Buffer 9"] #[inline(always)] #[must_use] - pub fn cr9(&mut self) -> CR9_W<9> { + pub fn cr9(&mut self) -> CR9_W { CR9_W::new(self) } #[doc = "Bit 10 - Cancellation Request for Transmit Buffer 10"] #[inline(always)] #[must_use] - pub fn cr10(&mut self) -> CR10_W<10> { + pub fn cr10(&mut self) -> CR10_W { CR10_W::new(self) } #[doc = "Bit 11 - Cancellation Request for Transmit Buffer 11"] #[inline(always)] #[must_use] - pub fn cr11(&mut self) -> CR11_W<11> { + pub fn cr11(&mut self) -> CR11_W { CR11_W::new(self) } #[doc = "Bit 12 - Cancellation Request for Transmit Buffer 12"] #[inline(always)] #[must_use] - pub fn cr12(&mut self) -> CR12_W<12> { + pub fn cr12(&mut self) -> CR12_W { CR12_W::new(self) } #[doc = "Bit 13 - Cancellation Request for Transmit Buffer 13"] #[inline(always)] #[must_use] - pub fn cr13(&mut self) -> CR13_W<13> { + pub fn cr13(&mut self) -> CR13_W { CR13_W::new(self) } #[doc = "Bit 14 - Cancellation Request for Transmit Buffer 14"] #[inline(always)] #[must_use] - pub fn cr14(&mut self) -> CR14_W<14> { + pub fn cr14(&mut self) -> CR14_W { CR14_W::new(self) } #[doc = "Bit 15 - Cancellation Request for Transmit Buffer 15"] #[inline(always)] #[must_use] - pub fn cr15(&mut self) -> CR15_W<15> { + pub fn cr15(&mut self) -> CR15_W { CR15_W::new(self) } #[doc = "Bit 16 - Cancellation Request for Transmit Buffer 16"] #[inline(always)] #[must_use] - pub fn cr16(&mut self) -> CR16_W<16> { + pub fn cr16(&mut self) -> CR16_W { CR16_W::new(self) } #[doc = "Bit 17 - Cancellation Request for Transmit Buffer 17"] #[inline(always)] #[must_use] - pub fn cr17(&mut self) -> CR17_W<17> { + pub fn cr17(&mut self) -> CR17_W { CR17_W::new(self) } #[doc = "Bit 18 - Cancellation Request for Transmit Buffer 18"] #[inline(always)] #[must_use] - pub fn cr18(&mut self) -> CR18_W<18> { + pub fn cr18(&mut self) -> CR18_W { CR18_W::new(self) } #[doc = "Bit 19 - Cancellation Request for Transmit Buffer 19"] #[inline(always)] #[must_use] - pub fn cr19(&mut self) -> CR19_W<19> { + pub fn cr19(&mut self) -> CR19_W { CR19_W::new(self) } #[doc = "Bit 20 - Cancellation Request for Transmit Buffer 20"] #[inline(always)] #[must_use] - pub fn cr20(&mut self) -> CR20_W<20> { + pub fn cr20(&mut self) -> CR20_W { CR20_W::new(self) } #[doc = "Bit 21 - Cancellation Request for Transmit Buffer 21"] #[inline(always)] #[must_use] - pub fn cr21(&mut self) -> CR21_W<21> { + pub fn cr21(&mut self) -> CR21_W { CR21_W::new(self) } #[doc = "Bit 22 - Cancellation Request for Transmit Buffer 22"] #[inline(always)] #[must_use] - pub fn cr22(&mut self) -> CR22_W<22> { + pub fn cr22(&mut self) -> CR22_W { CR22_W::new(self) } #[doc = "Bit 23 - Cancellation Request for Transmit Buffer 23"] #[inline(always)] #[must_use] - pub fn cr23(&mut self) -> CR23_W<23> { + pub fn cr23(&mut self) -> CR23_W { CR23_W::new(self) } #[doc = "Bit 24 - Cancellation Request for Transmit Buffer 24"] #[inline(always)] #[must_use] - pub fn cr24(&mut self) -> CR24_W<24> { + pub fn cr24(&mut self) -> CR24_W { CR24_W::new(self) } #[doc = "Bit 25 - Cancellation Request for Transmit Buffer 25"] #[inline(always)] #[must_use] - pub fn cr25(&mut self) -> CR25_W<25> { + pub fn cr25(&mut self) -> CR25_W { CR25_W::new(self) } #[doc = "Bit 26 - Cancellation Request for Transmit Buffer 26"] #[inline(always)] #[must_use] - pub fn cr26(&mut self) -> CR26_W<26> { + pub fn cr26(&mut self) -> CR26_W { CR26_W::new(self) } #[doc = "Bit 27 - Cancellation Request for Transmit Buffer 27"] #[inline(always)] #[must_use] - pub fn cr27(&mut self) -> CR27_W<27> { + pub fn cr27(&mut self) -> CR27_W { CR27_W::new(self) } #[doc = "Bit 28 - Cancellation Request for Transmit Buffer 28"] #[inline(always)] #[must_use] - pub fn cr28(&mut self) -> CR28_W<28> { + pub fn cr28(&mut self) -> CR28_W { CR28_W::new(self) } #[doc = "Bit 29 - Cancellation Request for Transmit Buffer 29"] #[inline(always)] #[must_use] - pub fn cr29(&mut self) -> CR29_W<29> { + pub fn cr29(&mut self) -> CR29_W { CR29_W::new(self) } #[doc = "Bit 30 - Cancellation Request for Transmit Buffer 30"] #[inline(always)] #[must_use] - pub fn cr30(&mut self) -> CR30_W<30> { + pub fn cr30(&mut self) -> CR30_W { CR30_W::new(self) } #[doc = "Bit 31 - Cancellation Request for Transmit Buffer 31"] #[inline(always)] #[must_use] - pub fn cr31(&mut self) -> CR31_W<31> { + pub fn cr31(&mut self) -> CR31_W { CR31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Cancellation Request Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbcr](index.html) module"] +#[doc = "Transmit Buffer Cancellation Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBCR_SPEC; impl crate::RegisterSpec for TXBCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbcr::R](R) reader structure"] -impl crate::Readable for TXBCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txbcr::W](W) writer structure"] +#[doc = "`read()` method returns [`txbcr::R`](R) reader structure"] +impl crate::Readable for TXBCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbcr::W`](W) writer structure"] impl crate::Writable for TXBCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbrp.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbrp.rs index f3419ed0..0674631b 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbrp.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbrp.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXBRP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TRP0` reader - Transmission Request Pending for Buffer 0"] pub type TRP0_R = crate::BitReader; #[doc = "Field `TRP1` reader - Transmission Request Pending for Buffer 1"] @@ -239,15 +226,13 @@ impl R { TRP31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Transmit Buffer Request Pending Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbrp](index.html) module"] +#[doc = "Transmit Buffer Request Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrp::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBRP_SPEC; impl crate::RegisterSpec for TXBRP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbrp::R](R) reader structure"] -impl crate::Readable for TXBRP_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txbrp::R`](R) reader structure"] +impl crate::Readable for TXBRP_SPEC {} #[doc = "`reset()` method sets TXBRP to value 0"] impl crate::Resettable for TXBRP_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbtie.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbtie.rs index bd3fc7bd..0a944c33 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbtie.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbtie.rs @@ -1,167 +1,135 @@ #[doc = "Register `TXBTIE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXBTIE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TIE0` reader - Transmission Interrupt Enable for Buffer 0"] pub type TIE0_R = crate::BitReader; #[doc = "Field `TIE0` writer - Transmission Interrupt Enable for Buffer 0"] -pub type TIE0_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE1` reader - Transmission Interrupt Enable for Buffer 1"] pub type TIE1_R = crate::BitReader; #[doc = "Field `TIE1` writer - Transmission Interrupt Enable for Buffer 1"] -pub type TIE1_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE2` reader - Transmission Interrupt Enable for Buffer 2"] pub type TIE2_R = crate::BitReader; #[doc = "Field `TIE2` writer - Transmission Interrupt Enable for Buffer 2"] -pub type TIE2_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE3` reader - Transmission Interrupt Enable for Buffer 3"] pub type TIE3_R = crate::BitReader; #[doc = "Field `TIE3` writer - Transmission Interrupt Enable for Buffer 3"] -pub type TIE3_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE4` reader - Transmission Interrupt Enable for Buffer 4"] pub type TIE4_R = crate::BitReader; #[doc = "Field `TIE4` writer - Transmission Interrupt Enable for Buffer 4"] -pub type TIE4_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE5` reader - Transmission Interrupt Enable for Buffer 5"] pub type TIE5_R = crate::BitReader; #[doc = "Field `TIE5` writer - Transmission Interrupt Enable for Buffer 5"] -pub type TIE5_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE6` reader - Transmission Interrupt Enable for Buffer 6"] pub type TIE6_R = crate::BitReader; #[doc = "Field `TIE6` writer - Transmission Interrupt Enable for Buffer 6"] -pub type TIE6_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE7` reader - Transmission Interrupt Enable for Buffer 7"] pub type TIE7_R = crate::BitReader; #[doc = "Field `TIE7` writer - Transmission Interrupt Enable for Buffer 7"] -pub type TIE7_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE8` reader - Transmission Interrupt Enable for Buffer 8"] pub type TIE8_R = crate::BitReader; #[doc = "Field `TIE8` writer - Transmission Interrupt Enable for Buffer 8"] -pub type TIE8_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE9` reader - Transmission Interrupt Enable for Buffer 9"] pub type TIE9_R = crate::BitReader; #[doc = "Field `TIE9` writer - Transmission Interrupt Enable for Buffer 9"] -pub type TIE9_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE10` reader - Transmission Interrupt Enable for Buffer 10"] pub type TIE10_R = crate::BitReader; #[doc = "Field `TIE10` writer - Transmission Interrupt Enable for Buffer 10"] -pub type TIE10_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE11` reader - Transmission Interrupt Enable for Buffer 11"] pub type TIE11_R = crate::BitReader; #[doc = "Field `TIE11` writer - Transmission Interrupt Enable for Buffer 11"] -pub type TIE11_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE12` reader - Transmission Interrupt Enable for Buffer 12"] pub type TIE12_R = crate::BitReader; #[doc = "Field `TIE12` writer - Transmission Interrupt Enable for Buffer 12"] -pub type TIE12_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE13` reader - Transmission Interrupt Enable for Buffer 13"] pub type TIE13_R = crate::BitReader; #[doc = "Field `TIE13` writer - Transmission Interrupt Enable for Buffer 13"] -pub type TIE13_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE14` reader - Transmission Interrupt Enable for Buffer 14"] pub type TIE14_R = crate::BitReader; #[doc = "Field `TIE14` writer - Transmission Interrupt Enable for Buffer 14"] -pub type TIE14_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE15` reader - Transmission Interrupt Enable for Buffer 15"] pub type TIE15_R = crate::BitReader; #[doc = "Field `TIE15` writer - Transmission Interrupt Enable for Buffer 15"] -pub type TIE15_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE16` reader - Transmission Interrupt Enable for Buffer 16"] pub type TIE16_R = crate::BitReader; #[doc = "Field `TIE16` writer - Transmission Interrupt Enable for Buffer 16"] -pub type TIE16_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE17` reader - Transmission Interrupt Enable for Buffer 17"] pub type TIE17_R = crate::BitReader; #[doc = "Field `TIE17` writer - Transmission Interrupt Enable for Buffer 17"] -pub type TIE17_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE18` reader - Transmission Interrupt Enable for Buffer 18"] pub type TIE18_R = crate::BitReader; #[doc = "Field `TIE18` writer - Transmission Interrupt Enable for Buffer 18"] -pub type TIE18_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE19` reader - Transmission Interrupt Enable for Buffer 19"] pub type TIE19_R = crate::BitReader; #[doc = "Field `TIE19` writer - Transmission Interrupt Enable for Buffer 19"] -pub type TIE19_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE20` reader - Transmission Interrupt Enable for Buffer 20"] pub type TIE20_R = crate::BitReader; #[doc = "Field `TIE20` writer - Transmission Interrupt Enable for Buffer 20"] -pub type TIE20_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE21` reader - Transmission Interrupt Enable for Buffer 21"] pub type TIE21_R = crate::BitReader; #[doc = "Field `TIE21` writer - Transmission Interrupt Enable for Buffer 21"] -pub type TIE21_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE22` reader - Transmission Interrupt Enable for Buffer 22"] pub type TIE22_R = crate::BitReader; #[doc = "Field `TIE22` writer - Transmission Interrupt Enable for Buffer 22"] -pub type TIE22_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE23` reader - Transmission Interrupt Enable for Buffer 23"] pub type TIE23_R = crate::BitReader; #[doc = "Field `TIE23` writer - Transmission Interrupt Enable for Buffer 23"] -pub type TIE23_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE24` reader - Transmission Interrupt Enable for Buffer 24"] pub type TIE24_R = crate::BitReader; #[doc = "Field `TIE24` writer - Transmission Interrupt Enable for Buffer 24"] -pub type TIE24_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE25` reader - Transmission Interrupt Enable for Buffer 25"] pub type TIE25_R = crate::BitReader; #[doc = "Field `TIE25` writer - Transmission Interrupt Enable for Buffer 25"] -pub type TIE25_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE26` reader - Transmission Interrupt Enable for Buffer 26"] pub type TIE26_R = crate::BitReader; #[doc = "Field `TIE26` writer - Transmission Interrupt Enable for Buffer 26"] -pub type TIE26_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE27` reader - Transmission Interrupt Enable for Buffer 27"] pub type TIE27_R = crate::BitReader; #[doc = "Field `TIE27` writer - Transmission Interrupt Enable for Buffer 27"] -pub type TIE27_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE28` reader - Transmission Interrupt Enable for Buffer 28"] pub type TIE28_R = crate::BitReader; #[doc = "Field `TIE28` writer - Transmission Interrupt Enable for Buffer 28"] -pub type TIE28_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE29` reader - Transmission Interrupt Enable for Buffer 29"] pub type TIE29_R = crate::BitReader; #[doc = "Field `TIE29` writer - Transmission Interrupt Enable for Buffer 29"] -pub type TIE29_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE30` reader - Transmission Interrupt Enable for Buffer 30"] pub type TIE30_R = crate::BitReader; #[doc = "Field `TIE30` writer - Transmission Interrupt Enable for Buffer 30"] -pub type TIE30_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIE31` reader - Transmission Interrupt Enable for Buffer 31"] pub type TIE31_R = crate::BitReader; #[doc = "Field `TIE31` writer - Transmission Interrupt Enable for Buffer 31"] -pub type TIE31_W<'a, const O: u8> = crate::BitWriter<'a, TXBTIE_SPEC, O>; +pub type TIE31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transmission Interrupt Enable for Buffer 0"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Transmission Interrupt Enable for Buffer 0"] #[inline(always)] #[must_use] - pub fn tie0(&mut self) -> TIE0_W<0> { + pub fn tie0(&mut self) -> TIE0_W { TIE0_W::new(self) } #[doc = "Bit 1 - Transmission Interrupt Enable for Buffer 1"] #[inline(always)] #[must_use] - pub fn tie1(&mut self) -> TIE1_W<1> { + pub fn tie1(&mut self) -> TIE1_W { TIE1_W::new(self) } #[doc = "Bit 2 - Transmission Interrupt Enable for Buffer 2"] #[inline(always)] #[must_use] - pub fn tie2(&mut self) -> TIE2_W<2> { + pub fn tie2(&mut self) -> TIE2_W { TIE2_W::new(self) } #[doc = "Bit 3 - Transmission Interrupt Enable for Buffer 3"] #[inline(always)] #[must_use] - pub fn tie3(&mut self) -> TIE3_W<3> { + pub fn tie3(&mut self) -> TIE3_W { TIE3_W::new(self) } #[doc = "Bit 4 - Transmission Interrupt Enable for Buffer 4"] #[inline(always)] #[must_use] - pub fn tie4(&mut self) -> TIE4_W<4> { + pub fn tie4(&mut self) -> TIE4_W { TIE4_W::new(self) } #[doc = "Bit 5 - Transmission Interrupt Enable for Buffer 5"] #[inline(always)] #[must_use] - pub fn tie5(&mut self) -> TIE5_W<5> { + pub fn tie5(&mut self) -> TIE5_W { TIE5_W::new(self) } #[doc = "Bit 6 - Transmission Interrupt Enable for Buffer 6"] #[inline(always)] #[must_use] - pub fn tie6(&mut self) -> TIE6_W<6> { + pub fn tie6(&mut self) -> TIE6_W { TIE6_W::new(self) } #[doc = "Bit 7 - Transmission Interrupt Enable for Buffer 7"] #[inline(always)] #[must_use] - pub fn tie7(&mut self) -> TIE7_W<7> { + pub fn tie7(&mut self) -> TIE7_W { TIE7_W::new(self) } #[doc = "Bit 8 - Transmission Interrupt Enable for Buffer 8"] #[inline(always)] #[must_use] - pub fn tie8(&mut self) -> TIE8_W<8> { + pub fn tie8(&mut self) -> TIE8_W { TIE8_W::new(self) } #[doc = "Bit 9 - Transmission Interrupt Enable for Buffer 9"] #[inline(always)] #[must_use] - pub fn tie9(&mut self) -> TIE9_W<9> { + pub fn tie9(&mut self) -> TIE9_W { TIE9_W::new(self) } #[doc = "Bit 10 - Transmission Interrupt Enable for Buffer 10"] #[inline(always)] #[must_use] - pub fn tie10(&mut self) -> TIE10_W<10> { + pub fn tie10(&mut self) -> TIE10_W { TIE10_W::new(self) } #[doc = "Bit 11 - Transmission Interrupt Enable for Buffer 11"] #[inline(always)] #[must_use] - pub fn tie11(&mut self) -> TIE11_W<11> { + pub fn tie11(&mut self) -> TIE11_W { TIE11_W::new(self) } #[doc = "Bit 12 - Transmission Interrupt Enable for Buffer 12"] #[inline(always)] #[must_use] - pub fn tie12(&mut self) -> TIE12_W<12> { + pub fn tie12(&mut self) -> TIE12_W { TIE12_W::new(self) } #[doc = "Bit 13 - Transmission Interrupt Enable for Buffer 13"] #[inline(always)] #[must_use] - pub fn tie13(&mut self) -> TIE13_W<13> { + pub fn tie13(&mut self) -> TIE13_W { TIE13_W::new(self) } #[doc = "Bit 14 - Transmission Interrupt Enable for Buffer 14"] #[inline(always)] #[must_use] - pub fn tie14(&mut self) -> TIE14_W<14> { + pub fn tie14(&mut self) -> TIE14_W { TIE14_W::new(self) } #[doc = "Bit 15 - Transmission Interrupt Enable for Buffer 15"] #[inline(always)] #[must_use] - pub fn tie15(&mut self) -> TIE15_W<15> { + pub fn tie15(&mut self) -> TIE15_W { TIE15_W::new(self) } #[doc = "Bit 16 - Transmission Interrupt Enable for Buffer 16"] #[inline(always)] #[must_use] - pub fn tie16(&mut self) -> TIE16_W<16> { + pub fn tie16(&mut self) -> TIE16_W { TIE16_W::new(self) } #[doc = "Bit 17 - Transmission Interrupt Enable for Buffer 17"] #[inline(always)] #[must_use] - pub fn tie17(&mut self) -> TIE17_W<17> { + pub fn tie17(&mut self) -> TIE17_W { TIE17_W::new(self) } #[doc = "Bit 18 - Transmission Interrupt Enable for Buffer 18"] #[inline(always)] #[must_use] - pub fn tie18(&mut self) -> TIE18_W<18> { + pub fn tie18(&mut self) -> TIE18_W { TIE18_W::new(self) } #[doc = "Bit 19 - Transmission Interrupt Enable for Buffer 19"] #[inline(always)] #[must_use] - pub fn tie19(&mut self) -> TIE19_W<19> { + pub fn tie19(&mut self) -> TIE19_W { TIE19_W::new(self) } #[doc = "Bit 20 - Transmission Interrupt Enable for Buffer 20"] #[inline(always)] #[must_use] - pub fn tie20(&mut self) -> TIE20_W<20> { + pub fn tie20(&mut self) -> TIE20_W { TIE20_W::new(self) } #[doc = "Bit 21 - Transmission Interrupt Enable for Buffer 21"] #[inline(always)] #[must_use] - pub fn tie21(&mut self) -> TIE21_W<21> { + pub fn tie21(&mut self) -> TIE21_W { TIE21_W::new(self) } #[doc = "Bit 22 - Transmission Interrupt Enable for Buffer 22"] #[inline(always)] #[must_use] - pub fn tie22(&mut self) -> TIE22_W<22> { + pub fn tie22(&mut self) -> TIE22_W { TIE22_W::new(self) } #[doc = "Bit 23 - Transmission Interrupt Enable for Buffer 23"] #[inline(always)] #[must_use] - pub fn tie23(&mut self) -> TIE23_W<23> { + pub fn tie23(&mut self) -> TIE23_W { TIE23_W::new(self) } #[doc = "Bit 24 - Transmission Interrupt Enable for Buffer 24"] #[inline(always)] #[must_use] - pub fn tie24(&mut self) -> TIE24_W<24> { + pub fn tie24(&mut self) -> TIE24_W { TIE24_W::new(self) } #[doc = "Bit 25 - Transmission Interrupt Enable for Buffer 25"] #[inline(always)] #[must_use] - pub fn tie25(&mut self) -> TIE25_W<25> { + pub fn tie25(&mut self) -> TIE25_W { TIE25_W::new(self) } #[doc = "Bit 26 - Transmission Interrupt Enable for Buffer 26"] #[inline(always)] #[must_use] - pub fn tie26(&mut self) -> TIE26_W<26> { + pub fn tie26(&mut self) -> TIE26_W { TIE26_W::new(self) } #[doc = "Bit 27 - Transmission Interrupt Enable for Buffer 27"] #[inline(always)] #[must_use] - pub fn tie27(&mut self) -> TIE27_W<27> { + pub fn tie27(&mut self) -> TIE27_W { TIE27_W::new(self) } #[doc = "Bit 28 - Transmission Interrupt Enable for Buffer 28"] #[inline(always)] #[must_use] - pub fn tie28(&mut self) -> TIE28_W<28> { + pub fn tie28(&mut self) -> TIE28_W { TIE28_W::new(self) } #[doc = "Bit 29 - Transmission Interrupt Enable for Buffer 29"] #[inline(always)] #[must_use] - pub fn tie29(&mut self) -> TIE29_W<29> { + pub fn tie29(&mut self) -> TIE29_W { TIE29_W::new(self) } #[doc = "Bit 30 - Transmission Interrupt Enable for Buffer 30"] #[inline(always)] #[must_use] - pub fn tie30(&mut self) -> TIE30_W<30> { + pub fn tie30(&mut self) -> TIE30_W { TIE30_W::new(self) } #[doc = "Bit 31 - Transmission Interrupt Enable for Buffer 31"] #[inline(always)] #[must_use] - pub fn tie31(&mut self) -> TIE31_W<31> { + pub fn tie31(&mut self) -> TIE31_W { TIE31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Transmission Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbtie](index.html) module"] +#[doc = "Transmit Buffer Transmission Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbtie::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbtie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBTIE_SPEC; impl crate::RegisterSpec for TXBTIE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbtie::R](R) reader structure"] -impl crate::Readable for TXBTIE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txbtie::W](W) writer structure"] +#[doc = "`read()` method returns [`txbtie::R`](R) reader structure"] +impl crate::Readable for TXBTIE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txbtie::W`](W) writer structure"] impl crate::Writable for TXBTIE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txbto.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txbto.rs index 43d098b9..cf2cc217 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txbto.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txbto.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXBTO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TO0` reader - Transmission Occurred for Buffer 0"] pub type TO0_R = crate::BitReader; #[doc = "Field `TO1` reader - Transmission Occurred for Buffer 1"] @@ -239,15 +226,13 @@ impl R { TO31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Transmit Buffer Transmission Occurred Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txbto](index.html) module"] +#[doc = "Transmit Buffer Transmission Occurred Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbto::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXBTO_SPEC; impl crate::RegisterSpec for TXBTO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txbto::R](R) reader structure"] -impl crate::Readable for TXBTO_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txbto::R`](R) reader structure"] +impl crate::Readable for TXBTO_SPEC {} #[doc = "`reset()` method sets TXBTO to value 0"] impl crate::Resettable for TXBTO_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txefa.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txefa.rs index cc70d55f..1e921268 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txefa.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txefa.rs @@ -1,43 +1,11 @@ #[doc = "Register `TXEFA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXEFA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EFAI` reader - Event FIFO Acknowledge Index"] pub type EFAI_R = crate::FieldReader; #[doc = "Field `EFAI` writer - Event FIFO Acknowledge Index"] -pub type EFAI_W<'a, const O: u8> = crate::FieldWriter<'a, TXEFA_SPEC, 5, O>; +pub type EFAI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; impl R { #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:4 - Event FIFO Acknowledge Index"] #[inline(always)] #[must_use] - pub fn efai(&mut self) -> EFAI_W<0> { + pub fn efai(&mut self) -> EFAI_W { EFAI_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Event FIFO Acknowledge Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefa](index.html) module"] +#[doc = "Transmit Event FIFO Acknowledge Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXEFA_SPEC; impl crate::RegisterSpec for TXEFA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txefa::R](R) reader structure"] -impl crate::Readable for TXEFA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txefa::W](W) writer structure"] +#[doc = "`read()` method returns [`txefa::R`](R) reader structure"] +impl crate::Readable for TXEFA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txefa::W`](W) writer structure"] impl crate::Writable for TXEFA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txefc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txefc.rs index 92463c0e..73c3ebe5 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txefc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txefc.rs @@ -1,51 +1,19 @@ #[doc = "Register `TXEFC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXEFC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EFSA` reader - Event FIFO Start Address"] pub type EFSA_R = crate::FieldReader; #[doc = "Field `EFSA` writer - Event FIFO Start Address"] -pub type EFSA_W<'a, const O: u8> = crate::FieldWriter<'a, TXEFC_SPEC, 14, O, u16>; +pub type EFSA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `EFS` reader - Event FIFO Size"] pub type EFS_R = crate::FieldReader; #[doc = "Field `EFS` writer - Event FIFO Size"] -pub type EFS_W<'a, const O: u8> = crate::FieldWriter<'a, TXEFC_SPEC, 6, O>; +pub type EFS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `EFWM` reader - Event FIFO Watermark"] pub type EFWM_R = crate::FieldReader; #[doc = "Field `EFWM` writer - Event FIFO Watermark"] -pub type EFWM_W<'a, const O: u8> = crate::FieldWriter<'a, TXEFC_SPEC, 6, O>; +pub type EFWM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 2:15 - Event FIFO Start Address"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bits 2:15 - Event FIFO Start Address"] #[inline(always)] #[must_use] - pub fn efsa(&mut self) -> EFSA_W<2> { + pub fn efsa(&mut self) -> EFSA_W { EFSA_W::new(self) } #[doc = "Bits 16:21 - Event FIFO Size"] #[inline(always)] #[must_use] - pub fn efs(&mut self) -> EFS_W<16> { + pub fn efs(&mut self) -> EFS_W { EFS_W::new(self) } #[doc = "Bits 24:29 - Event FIFO Watermark"] #[inline(always)] #[must_use] - pub fn efwm(&mut self) -> EFWM_W<24> { + pub fn efwm(&mut self) -> EFWM_W { EFWM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Event FIFO Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefc](index.html) module"] +#[doc = "Transmit Event FIFO Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXEFC_SPEC; impl crate::RegisterSpec for TXEFC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txefc::R](R) reader structure"] -impl crate::Readable for TXEFC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txefc::W](W) writer structure"] +#[doc = "`read()` method returns [`txefc::R`](R) reader structure"] +impl crate::Readable for TXEFC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txefc::W`](W) writer structure"] impl crate::Writable for TXEFC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txefs.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txefs.rs index 2988b980..59068d2f 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txefs.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txefs.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXEFS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `EFFL` reader - Event FIFO Fill Level"] pub type EFFL_R = crate::FieldReader; #[doc = "Field `EFGI` reader - Event FIFO Get Index"] @@ -50,15 +37,13 @@ impl R { TEFL_R::new(((self.bits >> 25) & 1) != 0) } } -#[doc = "Transmit Event FIFO Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txefs](index.html) module"] +#[doc = "Transmit Event FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXEFS_SPEC; impl crate::RegisterSpec for TXEFS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txefs::R](R) reader structure"] -impl crate::Readable for TXEFS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txefs::R`](R) reader structure"] +impl crate::Readable for TXEFS_SPEC {} #[doc = "`reset()` method sets TXEFS to value 0"] impl crate::Resettable for TXEFS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txesc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txesc.rs index 3b94f1fb..004709ff 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txesc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txesc.rs @@ -1,39 +1,7 @@ #[doc = "Register `TXESC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TXESC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TBDS` reader - Tx Buffer Data Field Size"] pub type TBDS_R = crate::FieldReader; #[doc = "Tx Buffer Data Field Size\n\nValue on reset: 0"] @@ -82,88 +50,92 @@ impl TBDS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8-byte data field"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == TBDSSELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_12_BYTE`"] + #[doc = "12-byte data field"] #[inline(always)] pub fn is_12_byte(&self) -> bool { *self == TBDSSELECT_A::_12_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16-byte data field"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == TBDSSELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_20_BYTE`"] + #[doc = "20-byte data field"] #[inline(always)] pub fn is_20_byte(&self) -> bool { *self == TBDSSELECT_A::_20_BYTE } - #[doc = "Checks if the value of the field is `_24_BYTE`"] + #[doc = "24-byte data field"] #[inline(always)] pub fn is_24_byte(&self) -> bool { *self == TBDSSELECT_A::_24_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32-byte data field"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == TBDSSELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_48_BYTE`"] + #[doc = "48-byte data field"] #[inline(always)] pub fn is_48_byte(&self) -> bool { *self == TBDSSELECT_A::_48_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64-byte data field"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == TBDSSELECT_A::_64_BYTE } } #[doc = "Field `TBDS` writer - Tx Buffer Data Field Size"] -pub type TBDS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, TXESC_SPEC, 3, O, TBDSSELECT_A>; -impl<'a, const O: u8> TBDS_W<'a, O> { +pub type TBDS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, TBDSSELECT_A>; +impl<'a, REG, const O: u8> TBDS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8-byte data field"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_8_BYTE) } #[doc = "12-byte data field"] #[inline(always)] - pub fn _12_byte(self) -> &'a mut W { + pub fn _12_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_12_BYTE) } #[doc = "16-byte data field"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_16_BYTE) } #[doc = "20-byte data field"] #[inline(always)] - pub fn _20_byte(self) -> &'a mut W { + pub fn _20_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_20_BYTE) } #[doc = "24-byte data field"] #[inline(always)] - pub fn _24_byte(self) -> &'a mut W { + pub fn _24_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_24_BYTE) } #[doc = "32-byte data field"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_32_BYTE) } #[doc = "48-byte data field"] #[inline(always)] - pub fn _48_byte(self) -> &'a mut W { + pub fn _48_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_48_BYTE) } #[doc = "64-byte data field"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(TBDSSELECT_A::_64_BYTE) } } @@ -178,28 +150,25 @@ impl W { #[doc = "Bits 0:2 - Tx Buffer Data Field Size"] #[inline(always)] #[must_use] - pub fn tbds(&mut self) -> TBDS_W<0> { + pub fn tbds(&mut self) -> TBDS_W { TBDS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Buffer Element Size Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txesc](index.html) module"] +#[doc = "Transmit Buffer Element Size Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txesc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txesc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXESC_SPEC; impl crate::RegisterSpec for TXESC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txesc::R](R) reader structure"] -impl crate::Readable for TXESC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [txesc::W](W) writer structure"] +#[doc = "`read()` method returns [`txesc::R`](R) reader structure"] +impl crate::Readable for TXESC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txesc::W`](W) writer structure"] impl crate::Writable for TXESC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/txfqs.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/txfqs.rs index 3c3bdfc4..680d8647 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/txfqs.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/txfqs.rs @@ -1,18 +1,5 @@ #[doc = "Register `TXFQS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TFFL` reader - Tx FIFO Free Level"] pub type TFFL_R = crate::FieldReader; #[doc = "Field `TFGI` reader - Tx FIFO Get Index"] @@ -43,15 +30,13 @@ impl R { TFQF_R::new(((self.bits >> 21) & 1) != 0) } } -#[doc = "Transmit FIFO/Queue Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfqs](index.html) module"] +#[doc = "Transmit FIFO/Queue Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfqs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TXFQS_SPEC; impl crate::RegisterSpec for TXFQS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [txfqs::R](R) reader structure"] -impl crate::Readable for TXFQS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`txfqs::R`](R) reader structure"] +impl crate::Readable for TXFQS_SPEC {} #[doc = "`reset()` method sets TXFQS to value 0"] impl crate::Resettable for TXFQS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/xidam.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/xidam.rs index f43e8913..d4bcfc19 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/xidam.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/xidam.rs @@ -1,43 +1,11 @@ #[doc = "Register `XIDAM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `XIDAM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EIDM` reader - Extended ID Mask"] pub type EIDM_R = crate::FieldReader; #[doc = "Field `EIDM` writer - Extended ID Mask"] -pub type EIDM_W<'a, const O: u8> = crate::FieldWriter<'a, XIDAM_SPEC, 29, O, u32>; +pub type EIDM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 29, O, u32>; impl R { #[doc = "Bits 0:28 - Extended ID Mask"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:28 - Extended ID Mask"] #[inline(always)] #[must_use] - pub fn eidm(&mut self) -> EIDM_W<0> { + pub fn eidm(&mut self) -> EIDM_W { EIDM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Extended ID AND Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidam](index.html) module"] +#[doc = "Extended ID AND Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidam::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidam::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct XIDAM_SPEC; impl crate::RegisterSpec for XIDAM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [xidam::R](R) reader structure"] -impl crate::Readable for XIDAM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [xidam::W](W) writer structure"] +#[doc = "`read()` method returns [`xidam::R`](R) reader structure"] +impl crate::Readable for XIDAM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xidam::W`](W) writer structure"] impl crate::Writable for XIDAM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0/xidfc.rs b/arch/cortex-m/samv71q21-pac/src/mcan0/xidfc.rs index 91c0b7bd..f7a79d4c 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0/xidfc.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0/xidfc.rs @@ -1,47 +1,15 @@ #[doc = "Register `XIDFC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `XIDFC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FLESA` reader - Filter List Extended Start Address"] pub type FLESA_R = crate::FieldReader; #[doc = "Field `FLESA` writer - Filter List Extended Start Address"] -pub type FLESA_W<'a, const O: u8> = crate::FieldWriter<'a, XIDFC_SPEC, 14, O, u16>; +pub type FLESA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `LSE` reader - List Size Extended"] pub type LSE_R = crate::FieldReader; #[doc = "Field `LSE` writer - List Size Extended"] -pub type LSE_W<'a, const O: u8> = crate::FieldWriter<'a, XIDFC_SPEC, 7, O>; +pub type LSE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 2:15 - Filter List Extended Start Address"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 2:15 - Filter List Extended Start Address"] #[inline(always)] #[must_use] - pub fn flesa(&mut self) -> FLESA_W<2> { + pub fn flesa(&mut self) -> FLESA_W { FLESA_W::new(self) } #[doc = "Bits 16:22 - List Size Extended"] #[inline(always)] #[must_use] - pub fn lse(&mut self) -> LSE_W<16> { + pub fn lse(&mut self) -> LSE_W { LSE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Extended ID Filter Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xidfc](index.html) module"] +#[doc = "Extended ID Filter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidfc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidfc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct XIDFC_SPEC; impl crate::RegisterSpec for XIDFC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [xidfc::R](R) reader structure"] -impl crate::Readable for XIDFC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [xidfc::W](W) writer structure"] +#[doc = "`read()` method returns [`xidfc::R`](R) reader structure"] +impl crate::Readable for XIDFC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xidfc::W`](W) writer structure"] impl crate::Writable for XIDFC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb.rs b/arch/cortex-m/samv71q21-pac/src/mlb.rs index e5d25363..e61a485f 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb.rs @@ -48,75 +48,93 @@ pub struct RegisterBlock { #[doc = "0x3d8..0x3e0 - AHB Channel Mask 0 Register 0"] pub acmr: [ACMR; 2], } -#[doc = "MLBC0 (rw) register accessor: an alias for `Reg`"] +#[doc = "MLBC0 (rw) register accessor: MediaLB Control 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mlbc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mlbc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mlbc0`] +module"] pub type MLBC0 = crate::Reg; #[doc = "MediaLB Control 0 Register"] pub mod mlbc0; -#[doc = "MS0 (rw) register accessor: an alias for `Reg`"] +#[doc = "MS0 (rw) register accessor: MediaLB Channel Status 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ms0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ms0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ms0`] +module"] pub type MS0 = crate::Reg; #[doc = "MediaLB Channel Status 0 Register"] pub mod ms0; -#[doc = "MS1 (rw) register accessor: an alias for `Reg`"] +#[doc = "MS1 (rw) register accessor: MediaLB Channel Status1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ms1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ms1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ms1`] +module"] pub type MS1 = crate::Reg; #[doc = "MediaLB Channel Status1 Register"] pub mod ms1; -#[doc = "MSS (rw) register accessor: an alias for `Reg`"] +#[doc = "MSS (rw) register accessor: MediaLB System Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mss::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mss::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mss`] +module"] pub type MSS = crate::Reg; #[doc = "MediaLB System Status Register"] pub mod mss; -#[doc = "MSD (r) register accessor: an alias for `Reg`"] +#[doc = "MSD (r) register accessor: MediaLB System Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`msd`] +module"] pub type MSD = crate::Reg; #[doc = "MediaLB System Data Register"] pub mod msd; -#[doc = "MIEN (rw) register accessor: an alias for `Reg`"] +#[doc = "MIEN (rw) register accessor: MediaLB Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mien::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mien::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mien`] +module"] pub type MIEN = crate::Reg; #[doc = "MediaLB Interrupt Enable Register"] pub mod mien; -#[doc = "MLBC1 (rw) register accessor: an alias for `Reg`"] +#[doc = "MLBC1 (rw) register accessor: MediaLB Control 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mlbc1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mlbc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mlbc1`] +module"] pub type MLBC1 = crate::Reg; #[doc = "MediaLB Control 1 Register"] pub mod mlbc1; -#[doc = "HCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "HCTL (rw) register accessor: HBI Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hctl`] +module"] pub type HCTL = crate::Reg; #[doc = "HBI Control Register"] pub mod hctl; -#[doc = "HCMR (rw) register accessor: an alias for `Reg`"] +#[doc = "HCMR (rw) register accessor: HBI Channel Mask 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hcmr`] +module"] pub type HCMR = crate::Reg; #[doc = "HBI Channel Mask 0 Register 0"] pub mod hcmr; -#[doc = "HCER (r) register accessor: an alias for `Reg`"] +#[doc = "HCER (r) register accessor: HBI Channel Error 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcer::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hcer`] +module"] pub type HCER = crate::Reg; #[doc = "HBI Channel Error 0 Register 0"] pub mod hcer; -#[doc = "HCBR (r) register accessor: an alias for `Reg`"] +#[doc = "HCBR (r) register accessor: HBI Channel Busy 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcbr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hcbr`] +module"] pub type HCBR = crate::Reg; #[doc = "HBI Channel Busy 0 Register 0"] pub mod hcbr; -#[doc = "MDAT (rw) register accessor: an alias for `Reg`"] +#[doc = "MDAT (rw) register accessor: MIF Data 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mdat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mdat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mdat`] +module"] pub type MDAT = crate::Reg; #[doc = "MIF Data 0 Register 0"] pub mod mdat; -#[doc = "MDWE (rw) register accessor: an alias for `Reg`"] +#[doc = "MDWE (rw) register accessor: MIF Data Write Enable 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mdwe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mdwe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mdwe`] +module"] pub type MDWE = crate::Reg; #[doc = "MIF Data Write Enable 0 Register 0"] pub mod mdwe; -#[doc = "MCTL (rw) register accessor: an alias for `Reg`"] +#[doc = "MCTL (rw) register accessor: MIF Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mctl`] +module"] pub type MCTL = crate::Reg; #[doc = "MIF Control Register"] pub mod mctl; -#[doc = "MADR (rw) register accessor: an alias for `Reg`"] +#[doc = "MADR (rw) register accessor: MIF Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`madr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`madr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`madr`] +module"] pub type MADR = crate::Reg; #[doc = "MIF Address Register"] pub mod madr; -#[doc = "ACTL (rw) register accessor: an alias for `Reg`"] +#[doc = "ACTL (rw) register accessor: AHB Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`actl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`actl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`actl`] +module"] pub type ACTL = crate::Reg; #[doc = "AHB Control Register"] pub mod actl; -#[doc = "ACSR (rw) register accessor: an alias for `Reg`"] +#[doc = "ACSR (rw) register accessor: AHB Channel Status 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`acsr`] +module"] pub type ACSR = crate::Reg; #[doc = "AHB Channel Status 0 Register 0"] pub mod acsr; -#[doc = "ACMR (rw) register accessor: an alias for `Reg`"] +#[doc = "ACMR (rw) register accessor: AHB Channel Mask 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`acmr`] +module"] pub type ACMR = crate::Reg; #[doc = "AHB Channel Mask 0 Register 0"] pub mod acmr; diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/acmr.rs b/arch/cortex-m/samv71q21-pac/src/mlb/acmr.rs index fd07ff6b..865b0f18 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/acmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/acmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `ACMR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACMR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHM` reader - Bitwise Channel Mask Bits 31 to 0"] pub type CHM_R = crate::FieldReader; #[doc = "Field `CHM` writer - Bitwise Channel Mask Bits 31 to 0"] -pub type CHM_W<'a, const O: u8> = crate::FieldWriter<'a, ACMR_SPEC, 32, O, u32>; +pub type CHM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Bitwise Channel Mask Bits 31 to 0"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Bitwise Channel Mask Bits 31 to 0"] #[inline(always)] #[must_use] - pub fn chm(&mut self) -> CHM_W<0> { + pub fn chm(&mut self) -> CHM_W { CHM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AHB Channel Mask 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acmr](index.html) module"] +#[doc = "AHB Channel Mask 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACMR_SPEC; impl crate::RegisterSpec for ACMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [acmr::R](R) reader structure"] -impl crate::Readable for ACMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [acmr::W](W) writer structure"] +#[doc = "`read()` method returns [`acmr::R`](R) reader structure"] +impl crate::Readable for ACMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`acmr::W`](W) writer structure"] impl crate::Writable for ACMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/acsr.rs b/arch/cortex-m/samv71q21-pac/src/mlb/acsr.rs index 3cd1eecf..bfabeb30 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/acsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/acsr.rs @@ -1,45 +1,13 @@ #[doc = "Register `ACSR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACSR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHS` reader - Interrupt Status for Logical Channels \\[31:0\\] (cleared by writing a 1)"] pub type CHS_R = crate::FieldReader; #[doc = "Field `CHS` writer - Interrupt Status for Logical Channels \\[31:0\\] (cleared by writing a 1)"] -pub type CHS_W<'a, const O: u8> = crate::FieldWriter<'a, ACSR_SPEC, 32, O, u32>; +pub type CHS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Interrupt Status for Logical Channels \\[31:0\\] (cleared by writing a 1)"] @@ -53,28 +21,25 @@ impl W { (cleared by writing a 1)"] #[inline(always)] #[must_use] - pub fn chs(&mut self) -> CHS_W<0> { + pub fn chs(&mut self) -> CHS_W { CHS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AHB Channel Status 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acsr](index.html) module"] +#[doc = "AHB Channel Status 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACSR_SPEC; impl crate::RegisterSpec for ACSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [acsr::R](R) reader structure"] -impl crate::Readable for ACSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [acsr::W](W) writer structure"] +#[doc = "`read()` method returns [`acsr::R`](R) reader structure"] +impl crate::Readable for ACSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`acsr::W`](W) writer structure"] impl crate::Writable for ACSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/actl.rs b/arch/cortex-m/samv71q21-pac/src/mlb/actl.rs index 884be9fa..b35f5f25 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/actl.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/actl.rs @@ -1,51 +1,19 @@ #[doc = "Register `ACTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SCE` reader - Software Clear Enable"] pub type SCE_R = crate::BitReader; #[doc = "Field `SCE` writer - Software Clear Enable"] -pub type SCE_W<'a, const O: u8> = crate::BitWriter<'a, ACTL_SPEC, O>; +pub type SCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMX` reader - AHB Interrupt Mux Enable"] pub type SMX_R = crate::BitReader; #[doc = "Field `SMX` writer - AHB Interrupt Mux Enable"] -pub type SMX_W<'a, const O: u8> = crate::BitWriter<'a, ACTL_SPEC, O>; +pub type SMX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_MODE` reader - DMA Mode"] pub type DMA_MODE_R = crate::BitReader; #[doc = "Field `DMA_MODE` writer - DMA Mode"] -pub type DMA_MODE_W<'a, const O: u8> = crate::BitWriter<'a, ACTL_SPEC, O>; +pub type DMA_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MPB` reader - DMA Packet Buffering Mode"] pub type MPB_R = crate::BitReader; #[doc = "DMA Packet Buffering Mode\n\nValue on reset: 0"] @@ -71,28 +39,31 @@ impl MPB_R { true => MPBSELECT_A::MULTIPLE_PACKET, } } - #[doc = "Checks if the value of the field is `SINGLE_PACKET`"] + #[doc = "Single-packet mode"] #[inline(always)] pub fn is_single_packet(&self) -> bool { *self == MPBSELECT_A::SINGLE_PACKET } - #[doc = "Checks if the value of the field is `MULTIPLE_PACKET`"] + #[doc = "Multiple-packet mode"] #[inline(always)] pub fn is_multiple_packet(&self) -> bool { *self == MPBSELECT_A::MULTIPLE_PACKET } } #[doc = "Field `MPB` writer - DMA Packet Buffering Mode"] -pub type MPB_W<'a, const O: u8> = crate::BitWriter<'a, ACTL_SPEC, O, MPBSELECT_A>; -impl<'a, const O: u8> MPB_W<'a, O> { +pub type MPB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MPBSELECT_A>; +impl<'a, REG, const O: u8> MPB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Single-packet mode"] #[inline(always)] - pub fn single_packet(self) -> &'a mut W { + pub fn single_packet(self) -> &'a mut crate::W { self.variant(MPBSELECT_A::SINGLE_PACKET) } #[doc = "Multiple-packet mode"] #[inline(always)] - pub fn multiple_packet(self) -> &'a mut W { + pub fn multiple_packet(self) -> &'a mut crate::W { self.variant(MPBSELECT_A::MULTIPLE_PACKET) } } @@ -122,46 +93,43 @@ impl W { #[doc = "Bit 0 - Software Clear Enable"] #[inline(always)] #[must_use] - pub fn sce(&mut self) -> SCE_W<0> { + pub fn sce(&mut self) -> SCE_W { SCE_W::new(self) } #[doc = "Bit 1 - AHB Interrupt Mux Enable"] #[inline(always)] #[must_use] - pub fn smx(&mut self) -> SMX_W<1> { + pub fn smx(&mut self) -> SMX_W { SMX_W::new(self) } #[doc = "Bit 2 - DMA Mode"] #[inline(always)] #[must_use] - pub fn dma_mode(&mut self) -> DMA_MODE_W<2> { + pub fn dma_mode(&mut self) -> DMA_MODE_W { DMA_MODE_W::new(self) } #[doc = "Bit 4 - DMA Packet Buffering Mode"] #[inline(always)] #[must_use] - pub fn mpb(&mut self) -> MPB_W<4> { + pub fn mpb(&mut self) -> MPB_W { MPB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "AHB Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [actl](index.html) module"] +#[doc = "AHB Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`actl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`actl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACTL_SPEC; impl crate::RegisterSpec for ACTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [actl::R](R) reader structure"] -impl crate::Readable for ACTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [actl::W](W) writer structure"] +#[doc = "`read()` method returns [`actl::R`](R) reader structure"] +impl crate::Readable for ACTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`actl::W`](W) writer structure"] impl crate::Writable for ACTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/hcbr.rs b/arch/cortex-m/samv71q21-pac/src/mlb/hcbr.rs index 768212fe..baf0509c 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/hcbr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/hcbr.rs @@ -1,18 +1,5 @@ #[doc = "Register `HCBR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHB` reader - Bitwise Channel Busy Bit \\[31:0\\]"] pub type CHB_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CHB_R::new(self.bits) } } -#[doc = "HBI Channel Busy 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcbr](index.html) module"] +#[doc = "HBI Channel Busy 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcbr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCBR_SPEC; impl crate::RegisterSpec for HCBR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcbr::R](R) reader structure"] -impl crate::Readable for HCBR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hcbr::R`](R) reader structure"] +impl crate::Readable for HCBR_SPEC {} #[doc = "`reset()` method sets HCBR[%s] to value 0"] impl crate::Resettable for HCBR_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/hcer.rs b/arch/cortex-m/samv71q21-pac/src/mlb/hcer.rs index bf820224..78e3bea8 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/hcer.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/hcer.rs @@ -1,18 +1,5 @@ #[doc = "Register `HCER[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CERR` reader - Bitwise Channel Error Bit \\[31:0\\]"] pub type CERR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CERR_R::new(self.bits) } } -#[doc = "HBI Channel Error 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcer](index.html) module"] +#[doc = "HBI Channel Error 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcer::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCER_SPEC; impl crate::RegisterSpec for HCER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcer::R](R) reader structure"] -impl crate::Readable for HCER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hcer::R`](R) reader structure"] +impl crate::Readable for HCER_SPEC {} #[doc = "`reset()` method sets HCER[%s] to value 0"] impl crate::Resettable for HCER_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/hcmr.rs b/arch/cortex-m/samv71q21-pac/src/mlb/hcmr.rs index f3ac0086..2a39ac42 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/hcmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/hcmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `HCMR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCMR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHM` reader - Bitwise Channel Mask Bit \\[31:0\\]"] pub type CHM_R = crate::FieldReader; #[doc = "Field `CHM` writer - Bitwise Channel Mask Bit \\[31:0\\]"] -pub type CHM_W<'a, const O: u8> = crate::FieldWriter<'a, HCMR_SPEC, 32, O, u32>; +pub type CHM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Bitwise Channel Mask Bit \\[31:0\\]"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Bitwise Channel Mask Bit \\[31:0\\]"] #[inline(always)] #[must_use] - pub fn chm(&mut self) -> CHM_W<0> { + pub fn chm(&mut self) -> CHM_W { CHM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "HBI Channel Mask 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcmr](index.html) module"] +#[doc = "HBI Channel Mask 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hcmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hcmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCMR_SPEC; impl crate::RegisterSpec for HCMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hcmr::R](R) reader structure"] -impl crate::Readable for HCMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hcmr::W](W) writer structure"] +#[doc = "`read()` method returns [`hcmr::R`](R) reader structure"] +impl crate::Readable for HCMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hcmr::W`](W) writer structure"] impl crate::Writable for HCMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/hctl.rs b/arch/cortex-m/samv71q21-pac/src/mlb/hctl.rs index a46d7ab1..2b475e49 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/hctl.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/hctl.rs @@ -1,51 +1,19 @@ #[doc = "Register `HCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RST0` reader - Address Generation Unit 0 Software Reset"] pub type RST0_R = crate::BitReader; #[doc = "Field `RST0` writer - Address Generation Unit 0 Software Reset"] -pub type RST0_W<'a, const O: u8> = crate::BitWriter<'a, HCTL_SPEC, O>; +pub type RST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RST1` reader - Address Generation Unit 1 Software Reset"] pub type RST1_R = crate::BitReader; #[doc = "Field `RST1` writer - Address Generation Unit 1 Software Reset"] -pub type RST1_W<'a, const O: u8> = crate::BitWriter<'a, HCTL_SPEC, O>; +pub type RST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN` reader - HBI Enable"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - HBI Enable"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, HCTL_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Address Generation Unit 0 Software Reset"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bit 0 - Address Generation Unit 0 Software Reset"] #[inline(always)] #[must_use] - pub fn rst0(&mut self) -> RST0_W<0> { + pub fn rst0(&mut self) -> RST0_W { RST0_W::new(self) } #[doc = "Bit 1 - Address Generation Unit 1 Software Reset"] #[inline(always)] #[must_use] - pub fn rst1(&mut self) -> RST1_W<1> { + pub fn rst1(&mut self) -> RST1_W { RST1_W::new(self) } #[doc = "Bit 15 - HBI Enable"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<15> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "HBI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hctl](index.html) module"] +#[doc = "HBI Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HCTL_SPEC; impl crate::RegisterSpec for HCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hctl::R](R) reader structure"] -impl crate::Readable for HCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hctl::W](W) writer structure"] +#[doc = "`read()` method returns [`hctl::R`](R) reader structure"] +impl crate::Readable for HCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hctl::W`](W) writer structure"] impl crate::Writable for HCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/madr.rs b/arch/cortex-m/samv71q21-pac/src/mlb/madr.rs index 567fd3f0..a6fccd41 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/madr.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/madr.rs @@ -1,43 +1,11 @@ #[doc = "Register `MADR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MADR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - CTR or DBR Address"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - CTR or DBR Address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, MADR_SPEC, 14, O, u16>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; #[doc = "Field `TB` reader - Target Location Bit"] pub type TB_R = crate::BitReader; #[doc = "Target Location Bit\n\nValue on reset: 0"] @@ -63,35 +31,38 @@ impl TB_R { true => TBSELECT_A::DBR, } } - #[doc = "Checks if the value of the field is `CTR`"] + #[doc = "Selects CTR"] #[inline(always)] pub fn is_ctr(&self) -> bool { *self == TBSELECT_A::CTR } - #[doc = "Checks if the value of the field is `DBR`"] + #[doc = "Selects DBR"] #[inline(always)] pub fn is_dbr(&self) -> bool { *self == TBSELECT_A::DBR } } #[doc = "Field `TB` writer - Target Location Bit"] -pub type TB_W<'a, const O: u8> = crate::BitWriter<'a, MADR_SPEC, O, TBSELECT_A>; -impl<'a, const O: u8> TB_W<'a, O> { +pub type TB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TBSELECT_A>; +impl<'a, REG, const O: u8> TB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Selects CTR"] #[inline(always)] - pub fn ctr(self) -> &'a mut W { + pub fn ctr(self) -> &'a mut crate::W { self.variant(TBSELECT_A::CTR) } #[doc = "Selects DBR"] #[inline(always)] - pub fn dbr(self) -> &'a mut W { + pub fn dbr(self) -> &'a mut crate::W { self.variant(TBSELECT_A::DBR) } } #[doc = "Field `WNR` reader - Write-Not-Read Selection"] pub type WNR_R = crate::BitReader; #[doc = "Field `WNR` writer - Write-Not-Read Selection"] -pub type WNR_W<'a, const O: u8> = crate::BitWriter<'a, MADR_SPEC, O>; +pub type WNR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:13 - CTR or DBR Address"] #[inline(always)] @@ -113,40 +84,37 @@ impl W { #[doc = "Bits 0:13 - CTR or DBR Address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Bit 30 - Target Location Bit"] #[inline(always)] #[must_use] - pub fn tb(&mut self) -> TB_W<30> { + pub fn tb(&mut self) -> TB_W { TB_W::new(self) } #[doc = "Bit 31 - Write-Not-Read Selection"] #[inline(always)] #[must_use] - pub fn wnr(&mut self) -> WNR_W<31> { + pub fn wnr(&mut self) -> WNR_W { WNR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MIF Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [madr](index.html) module"] +#[doc = "MIF Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`madr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`madr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MADR_SPEC; impl crate::RegisterSpec for MADR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [madr::R](R) reader structure"] -impl crate::Readable for MADR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [madr::W](W) writer structure"] +#[doc = "`read()` method returns [`madr::R`](R) reader structure"] +impl crate::Readable for MADR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`madr::W`](W) writer structure"] impl crate::Writable for MADR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mctl.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mctl.rs index df304caf..12566fda 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mctl.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mctl.rs @@ -1,43 +1,11 @@ #[doc = "Register `MCTL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MCTL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `XCMP` reader - Transfer Complete (Write 0 to Clear)"] pub type XCMP_R = crate::BitReader; #[doc = "Field `XCMP` writer - Transfer Complete (Write 0 to Clear)"] -pub type XCMP_W<'a, const O: u8> = crate::BitWriter<'a, MCTL_SPEC, O>; +pub type XCMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Transfer Complete (Write 0 to Clear)"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bit 0 - Transfer Complete (Write 0 to Clear)"] #[inline(always)] #[must_use] - pub fn xcmp(&mut self) -> XCMP_W<0> { + pub fn xcmp(&mut self) -> XCMP_W { XCMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MIF Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mctl](index.html) module"] +#[doc = "MIF Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCTL_SPEC; impl crate::RegisterSpec for MCTL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mctl::R](R) reader structure"] -impl crate::Readable for MCTL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mctl::W](W) writer structure"] +#[doc = "`read()` method returns [`mctl::R`](R) reader structure"] +impl crate::Readable for MCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mctl::W`](W) writer structure"] impl crate::Writable for MCTL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mdat.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mdat.rs index e7436e2d..5e56cf4e 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mdat.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mdat.rs @@ -1,43 +1,11 @@ #[doc = "Register `MDAT[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MDAT[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATA` reader - CRT or DBR Data"] pub type DATA_R = crate::FieldReader; #[doc = "Field `DATA` writer - CRT or DBR Data"] -pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, MDAT_SPEC, 32, O, u32>; +pub type DATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - CRT or DBR Data"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - CRT or DBR Data"] #[inline(always)] #[must_use] - pub fn data(&mut self) -> DATA_W<0> { + pub fn data(&mut self) -> DATA_W { DATA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MIF Data 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mdat](index.html) module"] +#[doc = "MIF Data 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mdat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mdat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MDAT_SPEC; impl crate::RegisterSpec for MDAT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mdat::R](R) reader structure"] -impl crate::Readable for MDAT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mdat::W](W) writer structure"] +#[doc = "`read()` method returns [`mdat::R`](R) reader structure"] +impl crate::Readable for MDAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mdat::W`](W) writer structure"] impl crate::Writable for MDAT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mdwe.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mdwe.rs index 558c6549..c33fa6a0 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mdwe.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mdwe.rs @@ -1,43 +1,11 @@ #[doc = "Register `MDWE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MDWE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MASK` reader - Bitwise Write Enable for CTR Data - bits\\[31:0\\]"] pub type MASK_R = crate::FieldReader; #[doc = "Field `MASK` writer - Bitwise Write Enable for CTR Data - bits\\[31:0\\]"] -pub type MASK_W<'a, const O: u8> = crate::FieldWriter<'a, MDWE_SPEC, 32, O, u32>; +pub type MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Bitwise Write Enable for CTR Data - bits\\[31:0\\]"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Bitwise Write Enable for CTR Data - bits\\[31:0\\]"] #[inline(always)] #[must_use] - pub fn mask(&mut self) -> MASK_W<0> { + pub fn mask(&mut self) -> MASK_W { MASK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MIF Data Write Enable 0 Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mdwe](index.html) module"] +#[doc = "MIF Data Write Enable 0 Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mdwe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mdwe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MDWE_SPEC; impl crate::RegisterSpec for MDWE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mdwe::R](R) reader structure"] -impl crate::Readable for MDWE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mdwe::W](W) writer structure"] +#[doc = "`read()` method returns [`mdwe::R`](R) reader structure"] +impl crate::Readable for MDWE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mdwe::W`](W) writer structure"] impl crate::Writable for MDWE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mien.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mien.rs index f545d256..84582aac 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mien.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mien.rs @@ -1,99 +1,67 @@ #[doc = "Register `MIEN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MIEN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ISOC_PE` reader - Isochronous Rx Protocol Error Enable"] pub type ISOC_PE_R = crate::BitReader; #[doc = "Field `ISOC_PE` writer - Isochronous Rx Protocol Error Enable"] -pub type ISOC_PE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ISOC_PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ISOC_BUFO` reader - Isochronous Rx Buffer Overflow Enable"] pub type ISOC_BUFO_R = crate::BitReader; #[doc = "Field `ISOC_BUFO` writer - Isochronous Rx Buffer Overflow Enable"] -pub type ISOC_BUFO_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ISOC_BUFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYNC_PE` reader - Synchronous Protocol Error Enable"] pub type SYNC_PE_R = crate::BitReader; #[doc = "Field `SYNC_PE` writer - Synchronous Protocol Error Enable"] -pub type SYNC_PE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type SYNC_PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARX_DONE` reader - Asynchronous Rx Done Enable"] pub type ARX_DONE_R = crate::BitReader; #[doc = "Field `ARX_DONE` writer - Asynchronous Rx Done Enable"] -pub type ARX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ARX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARX_PE` reader - Asynchronous Rx Protocol Error Enable"] pub type ARX_PE_R = crate::BitReader; #[doc = "Field `ARX_PE` writer - Asynchronous Rx Protocol Error Enable"] -pub type ARX_PE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ARX_PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARX_BREAK` reader - Asynchronous Rx Break Enable"] pub type ARX_BREAK_R = crate::BitReader; #[doc = "Field `ARX_BREAK` writer - Asynchronous Rx Break Enable"] -pub type ARX_BREAK_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ARX_BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ATX_DONE` reader - Asynchronous Tx Packet Done Enable"] pub type ATX_DONE_R = crate::BitReader; #[doc = "Field `ATX_DONE` writer - Asynchronous Tx Packet Done Enable"] -pub type ATX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ATX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ATX_PE` reader - Asynchronous Tx Protocol Error Enable"] pub type ATX_PE_R = crate::BitReader; #[doc = "Field `ATX_PE` writer - Asynchronous Tx Protocol Error Enable"] -pub type ATX_PE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ATX_PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ATX_BREAK` reader - Asynchronous Tx Break Enable"] pub type ATX_BREAK_R = crate::BitReader; #[doc = "Field `ATX_BREAK` writer - Asynchronous Tx Break Enable"] -pub type ATX_BREAK_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type ATX_BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRX_DONE` reader - Control Rx Packet Done Enable"] pub type CRX_DONE_R = crate::BitReader; #[doc = "Field `CRX_DONE` writer - Control Rx Packet Done Enable"] -pub type CRX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type CRX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRX_PE` reader - Control Rx Protocol Error Enable"] pub type CRX_PE_R = crate::BitReader; #[doc = "Field `CRX_PE` writer - Control Rx Protocol Error Enable"] -pub type CRX_PE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type CRX_PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRX_BREAK` reader - Control Rx Break Enable"] pub type CRX_BREAK_R = crate::BitReader; #[doc = "Field `CRX_BREAK` writer - Control Rx Break Enable"] -pub type CRX_BREAK_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type CRX_BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTX_DONE` reader - Control Tx Packet Done Enable"] pub type CTX_DONE_R = crate::BitReader; #[doc = "Field `CTX_DONE` writer - Control Tx Packet Done Enable"] -pub type CTX_DONE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type CTX_DONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTX_PE` reader - Control Tx Protocol Error Enable"] pub type CTX_PE_R = crate::BitReader; #[doc = "Field `CTX_PE` writer - Control Tx Protocol Error Enable"] -pub type CTX_PE_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type CTX_PE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTX_BREAK` reader - Control Tx Break Enable"] pub type CTX_BREAK_R = crate::BitReader; #[doc = "Field `CTX_BREAK` writer - Control Tx Break Enable"] -pub type CTX_BREAK_W<'a, const O: u8> = crate::BitWriter<'a, MIEN_SPEC, O>; +pub type CTX_BREAK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Isochronous Rx Protocol Error Enable"] #[inline(always)] @@ -175,112 +143,109 @@ impl W { #[doc = "Bit 0 - Isochronous Rx Protocol Error Enable"] #[inline(always)] #[must_use] - pub fn isoc_pe(&mut self) -> ISOC_PE_W<0> { + pub fn isoc_pe(&mut self) -> ISOC_PE_W { ISOC_PE_W::new(self) } #[doc = "Bit 1 - Isochronous Rx Buffer Overflow Enable"] #[inline(always)] #[must_use] - pub fn isoc_bufo(&mut self) -> ISOC_BUFO_W<1> { + pub fn isoc_bufo(&mut self) -> ISOC_BUFO_W { ISOC_BUFO_W::new(self) } #[doc = "Bit 16 - Synchronous Protocol Error Enable"] #[inline(always)] #[must_use] - pub fn sync_pe(&mut self) -> SYNC_PE_W<16> { + pub fn sync_pe(&mut self) -> SYNC_PE_W { SYNC_PE_W::new(self) } #[doc = "Bit 17 - Asynchronous Rx Done Enable"] #[inline(always)] #[must_use] - pub fn arx_done(&mut self) -> ARX_DONE_W<17> { + pub fn arx_done(&mut self) -> ARX_DONE_W { ARX_DONE_W::new(self) } #[doc = "Bit 18 - Asynchronous Rx Protocol Error Enable"] #[inline(always)] #[must_use] - pub fn arx_pe(&mut self) -> ARX_PE_W<18> { + pub fn arx_pe(&mut self) -> ARX_PE_W { ARX_PE_W::new(self) } #[doc = "Bit 19 - Asynchronous Rx Break Enable"] #[inline(always)] #[must_use] - pub fn arx_break(&mut self) -> ARX_BREAK_W<19> { + pub fn arx_break(&mut self) -> ARX_BREAK_W { ARX_BREAK_W::new(self) } #[doc = "Bit 20 - Asynchronous Tx Packet Done Enable"] #[inline(always)] #[must_use] - pub fn atx_done(&mut self) -> ATX_DONE_W<20> { + pub fn atx_done(&mut self) -> ATX_DONE_W { ATX_DONE_W::new(self) } #[doc = "Bit 21 - Asynchronous Tx Protocol Error Enable"] #[inline(always)] #[must_use] - pub fn atx_pe(&mut self) -> ATX_PE_W<21> { + pub fn atx_pe(&mut self) -> ATX_PE_W { ATX_PE_W::new(self) } #[doc = "Bit 22 - Asynchronous Tx Break Enable"] #[inline(always)] #[must_use] - pub fn atx_break(&mut self) -> ATX_BREAK_W<22> { + pub fn atx_break(&mut self) -> ATX_BREAK_W { ATX_BREAK_W::new(self) } #[doc = "Bit 24 - Control Rx Packet Done Enable"] #[inline(always)] #[must_use] - pub fn crx_done(&mut self) -> CRX_DONE_W<24> { + pub fn crx_done(&mut self) -> CRX_DONE_W { CRX_DONE_W::new(self) } #[doc = "Bit 25 - Control Rx Protocol Error Enable"] #[inline(always)] #[must_use] - pub fn crx_pe(&mut self) -> CRX_PE_W<25> { + pub fn crx_pe(&mut self) -> CRX_PE_W { CRX_PE_W::new(self) } #[doc = "Bit 26 - Control Rx Break Enable"] #[inline(always)] #[must_use] - pub fn crx_break(&mut self) -> CRX_BREAK_W<26> { + pub fn crx_break(&mut self) -> CRX_BREAK_W { CRX_BREAK_W::new(self) } #[doc = "Bit 27 - Control Tx Packet Done Enable"] #[inline(always)] #[must_use] - pub fn ctx_done(&mut self) -> CTX_DONE_W<27> { + pub fn ctx_done(&mut self) -> CTX_DONE_W { CTX_DONE_W::new(self) } #[doc = "Bit 28 - Control Tx Protocol Error Enable"] #[inline(always)] #[must_use] - pub fn ctx_pe(&mut self) -> CTX_PE_W<28> { + pub fn ctx_pe(&mut self) -> CTX_PE_W { CTX_PE_W::new(self) } #[doc = "Bit 29 - Control Tx Break Enable"] #[inline(always)] #[must_use] - pub fn ctx_break(&mut self) -> CTX_BREAK_W<29> { + pub fn ctx_break(&mut self) -> CTX_BREAK_W { CTX_BREAK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MediaLB Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mien](index.html) module"] +#[doc = "MediaLB Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mien::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mien::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MIEN_SPEC; impl crate::RegisterSpec for MIEN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mien::R](R) reader structure"] -impl crate::Readable for MIEN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mien::W](W) writer structure"] +#[doc = "`read()` method returns [`mien::R`](R) reader structure"] +impl crate::Readable for MIEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mien::W`](W) writer structure"] impl crate::Writable for MIEN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mlbc0.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mlbc0.rs index 7f11704b..ce8acca8 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mlbc0.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mlbc0.rs @@ -1,43 +1,11 @@ #[doc = "Register `MLBC0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MLBC0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MLBEN` reader - MediaLB Enable"] pub type MLBEN_R = crate::BitReader; #[doc = "Field `MLBEN` writer - MediaLB Enable"] -pub type MLBEN_W<'a, const O: u8> = crate::BitWriter<'a, MLBC0_SPEC, O>; +pub type MLBEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MLBCLK` reader - MLBCLK (MediaLB clock) Speed Select"] pub type MLBCLK_R = crate::FieldReader; #[doc = "MLBCLK (MediaLB clock) Speed Select\n\nValue on reset: 0"] @@ -71,57 +39,61 @@ impl MLBCLK_R { _ => None, } } - #[doc = "Checks if the value of the field is `_256_FS`"] + #[doc = "256xFs (for MLBPEN = 0)"] #[inline(always)] pub fn is_256_fs(&self) -> bool { *self == MLBCLKSELECT_A::_256_FS } - #[doc = "Checks if the value of the field is `_512_FS`"] + #[doc = "512xFs (for MLBPEN = 0)"] #[inline(always)] pub fn is_512_fs(&self) -> bool { *self == MLBCLKSELECT_A::_512_FS } - #[doc = "Checks if the value of the field is `_1024_FS`"] + #[doc = "1024xFs (for MLBPEN = 0)"] #[inline(always)] pub fn is_1024_fs(&self) -> bool { *self == MLBCLKSELECT_A::_1024_FS } } #[doc = "Field `MLBCLK` writer - MLBCLK (MediaLB clock) Speed Select"] -pub type MLBCLK_W<'a, const O: u8> = crate::FieldWriter<'a, MLBC0_SPEC, 3, O, MLBCLKSELECT_A>; -impl<'a, const O: u8> MLBCLK_W<'a, O> { +pub type MLBCLK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, MLBCLKSELECT_A>; +impl<'a, REG, const O: u8> MLBCLK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "256xFs (for MLBPEN = 0)"] #[inline(always)] - pub fn _256_fs(self) -> &'a mut W { + pub fn _256_fs(self) -> &'a mut crate::W { self.variant(MLBCLKSELECT_A::_256_FS) } #[doc = "512xFs (for MLBPEN = 0)"] #[inline(always)] - pub fn _512_fs(self) -> &'a mut W { + pub fn _512_fs(self) -> &'a mut crate::W { self.variant(MLBCLKSELECT_A::_512_FS) } #[doc = "1024xFs (for MLBPEN = 0)"] #[inline(always)] - pub fn _1024_fs(self) -> &'a mut W { + pub fn _1024_fs(self) -> &'a mut crate::W { self.variant(MLBCLKSELECT_A::_1024_FS) } } #[doc = "Field `ZERO` reader - Must be Written to 0"] pub type ZERO_R = crate::BitReader; #[doc = "Field `ZERO` writer - Must be Written to 0"] -pub type ZERO_W<'a, const O: u8> = crate::BitWriter<'a, MLBC0_SPEC, O>; +pub type ZERO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MLBLK` reader - MediaLB Lock Status (read-only)"] pub type MLBLK_R = crate::BitReader; #[doc = "Field `MLBLK` writer - MediaLB Lock Status (read-only)"] -pub type MLBLK_W<'a, const O: u8> = crate::BitWriter<'a, MLBC0_SPEC, O>; +pub type MLBLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ASYRETRY` reader - Asynchronous Tx Packet Retry"] pub type ASYRETRY_R = crate::BitReader; #[doc = "Field `ASYRETRY` writer - Asynchronous Tx Packet Retry"] -pub type ASYRETRY_W<'a, const O: u8> = crate::BitWriter<'a, MLBC0_SPEC, O>; +pub type ASYRETRY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTLRETRY` reader - Control Tx Packet Retry"] pub type CTLRETRY_R = crate::BitReader; #[doc = "Field `CTLRETRY` writer - Control Tx Packet Retry"] -pub type CTLRETRY_W<'a, const O: u8> = crate::BitWriter<'a, MLBC0_SPEC, O>; +pub type CTLRETRY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCNT` reader - The number of frames per sub-buffer for synchronous channels"] pub type FCNT_R = crate::FieldReader; #[doc = "The number of frames per sub-buffer for synchronous channels\n\nValue on reset: 0"] @@ -167,78 +139,82 @@ impl FCNT_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1_FRAME`"] + #[doc = "1 frame per sub-buffer (Operation is the same as Standard mode.)"] #[inline(always)] pub fn is_1_frame(&self) -> bool { *self == FCNTSELECT_A::_1_FRAME } - #[doc = "Checks if the value of the field is `_2_FRAMES`"] + #[doc = "2 frames per sub-buffer"] #[inline(always)] pub fn is_2_frames(&self) -> bool { *self == FCNTSELECT_A::_2_FRAMES } - #[doc = "Checks if the value of the field is `_4_FRAMES`"] + #[doc = "4 frames per sub-buffer"] #[inline(always)] pub fn is_4_frames(&self) -> bool { *self == FCNTSELECT_A::_4_FRAMES } - #[doc = "Checks if the value of the field is `_8_FRAMES`"] + #[doc = "8 frames per sub-buffer"] #[inline(always)] pub fn is_8_frames(&self) -> bool { *self == FCNTSELECT_A::_8_FRAMES } - #[doc = "Checks if the value of the field is `_16_FRAMES`"] + #[doc = "16 frames per sub-buffer"] #[inline(always)] pub fn is_16_frames(&self) -> bool { *self == FCNTSELECT_A::_16_FRAMES } - #[doc = "Checks if the value of the field is `_32_FRAMES`"] + #[doc = "32 frames per sub-buffer"] #[inline(always)] pub fn is_32_frames(&self) -> bool { *self == FCNTSELECT_A::_32_FRAMES } - #[doc = "Checks if the value of the field is `_64_FRAMES`"] + #[doc = "64 frames per sub-buffer"] #[inline(always)] pub fn is_64_frames(&self) -> bool { *self == FCNTSELECT_A::_64_FRAMES } } #[doc = "Field `FCNT` writer - The number of frames per sub-buffer for synchronous channels"] -pub type FCNT_W<'a, const O: u8> = crate::FieldWriter<'a, MLBC0_SPEC, 3, O, FCNTSELECT_A>; -impl<'a, const O: u8> FCNT_W<'a, O> { +pub type FCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, FCNTSELECT_A>; +impl<'a, REG, const O: u8> FCNT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "1 frame per sub-buffer (Operation is the same as Standard mode.)"] #[inline(always)] - pub fn _1_frame(self) -> &'a mut W { + pub fn _1_frame(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_1_FRAME) } #[doc = "2 frames per sub-buffer"] #[inline(always)] - pub fn _2_frames(self) -> &'a mut W { + pub fn _2_frames(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_2_FRAMES) } #[doc = "4 frames per sub-buffer"] #[inline(always)] - pub fn _4_frames(self) -> &'a mut W { + pub fn _4_frames(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_4_FRAMES) } #[doc = "8 frames per sub-buffer"] #[inline(always)] - pub fn _8_frames(self) -> &'a mut W { + pub fn _8_frames(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_8_FRAMES) } #[doc = "16 frames per sub-buffer"] #[inline(always)] - pub fn _16_frames(self) -> &'a mut W { + pub fn _16_frames(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_16_FRAMES) } #[doc = "32 frames per sub-buffer"] #[inline(always)] - pub fn _32_frames(self) -> &'a mut W { + pub fn _32_frames(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_32_FRAMES) } #[doc = "64 frames per sub-buffer"] #[inline(always)] - pub fn _64_frames(self) -> &'a mut W { + pub fn _64_frames(self) -> &'a mut crate::W { self.variant(FCNTSELECT_A::_64_FRAMES) } } @@ -283,64 +259,61 @@ impl W { #[doc = "Bit 0 - MediaLB Enable"] #[inline(always)] #[must_use] - pub fn mlben(&mut self) -> MLBEN_W<0> { + pub fn mlben(&mut self) -> MLBEN_W { MLBEN_W::new(self) } #[doc = "Bits 2:4 - MLBCLK (MediaLB clock) Speed Select"] #[inline(always)] #[must_use] - pub fn mlbclk(&mut self) -> MLBCLK_W<2> { + pub fn mlbclk(&mut self) -> MLBCLK_W { MLBCLK_W::new(self) } #[doc = "Bit 5 - Must be Written to 0"] #[inline(always)] #[must_use] - pub fn zero(&mut self) -> ZERO_W<5> { + pub fn zero(&mut self) -> ZERO_W { ZERO_W::new(self) } #[doc = "Bit 7 - MediaLB Lock Status (read-only)"] #[inline(always)] #[must_use] - pub fn mlblk(&mut self) -> MLBLK_W<7> { + pub fn mlblk(&mut self) -> MLBLK_W { MLBLK_W::new(self) } #[doc = "Bit 12 - Asynchronous Tx Packet Retry"] #[inline(always)] #[must_use] - pub fn asyretry(&mut self) -> ASYRETRY_W<12> { + pub fn asyretry(&mut self) -> ASYRETRY_W { ASYRETRY_W::new(self) } #[doc = "Bit 14 - Control Tx Packet Retry"] #[inline(always)] #[must_use] - pub fn ctlretry(&mut self) -> CTLRETRY_W<14> { + pub fn ctlretry(&mut self) -> CTLRETRY_W { CTLRETRY_W::new(self) } #[doc = "Bits 15:17 - The number of frames per sub-buffer for synchronous channels"] #[inline(always)] #[must_use] - pub fn fcnt(&mut self) -> FCNT_W<15> { + pub fn fcnt(&mut self) -> FCNT_W { FCNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MediaLB Control 0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mlbc0](index.html) module"] +#[doc = "MediaLB Control 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mlbc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mlbc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MLBC0_SPEC; impl crate::RegisterSpec for MLBC0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mlbc0::R](R) reader structure"] -impl crate::Readable for MLBC0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mlbc0::W](W) writer structure"] +#[doc = "`read()` method returns [`mlbc0::R`](R) reader structure"] +impl crate::Readable for MLBC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mlbc0::W`](W) writer structure"] impl crate::Writable for MLBC0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mlbc1.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mlbc1.rs index 18c6f4df..cda33ec6 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mlbc1.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mlbc1.rs @@ -1,51 +1,19 @@ #[doc = "Register `MLBC1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MLBC1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LOCK` reader - MediaLB Lock Error Status (cleared by writing a 0)"] pub type LOCK_R = crate::BitReader; #[doc = "Field `LOCK` writer - MediaLB Lock Error Status (cleared by writing a 0)"] -pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, MLBC1_SPEC, O>; +pub type LOCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLKM` reader - MediaLB Clock Missing Status (cleared by writing a 0)"] pub type CLKM_R = crate::BitReader; #[doc = "Field `CLKM` writer - MediaLB Clock Missing Status (cleared by writing a 0)"] -pub type CLKM_W<'a, const O: u8> = crate::BitWriter<'a, MLBC1_SPEC, O>; +pub type CLKM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NDA` reader - Node Device Address"] pub type NDA_R = crate::FieldReader; #[doc = "Field `NDA` writer - Node Device Address"] -pub type NDA_W<'a, const O: u8> = crate::FieldWriter<'a, MLBC1_SPEC, 8, O>; +pub type NDA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 6 - MediaLB Lock Error Status (cleared by writing a 0)"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bit 6 - MediaLB Lock Error Status (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn lock(&mut self) -> LOCK_W<6> { + pub fn lock(&mut self) -> LOCK_W { LOCK_W::new(self) } #[doc = "Bit 7 - MediaLB Clock Missing Status (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn clkm(&mut self) -> CLKM_W<7> { + pub fn clkm(&mut self) -> CLKM_W { CLKM_W::new(self) } #[doc = "Bits 8:15 - Node Device Address"] #[inline(always)] #[must_use] - pub fn nda(&mut self) -> NDA_W<8> { + pub fn nda(&mut self) -> NDA_W { NDA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MediaLB Control 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mlbc1](index.html) module"] +#[doc = "MediaLB Control 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mlbc1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mlbc1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MLBC1_SPEC; impl crate::RegisterSpec for MLBC1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mlbc1::R](R) reader structure"] -impl crate::Readable for MLBC1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mlbc1::W](W) writer structure"] +#[doc = "`read()` method returns [`mlbc1::R`](R) reader structure"] +impl crate::Readable for MLBC1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mlbc1::W`](W) writer structure"] impl crate::Writable for MLBC1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/ms0.rs b/arch/cortex-m/samv71q21-pac/src/mlb/ms0.rs index 9df30295..4e1e5d6d 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/ms0.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/ms0.rs @@ -1,45 +1,13 @@ #[doc = "Register `MS0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MS0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MCS` reader - MediaLB Channel Status \\[31:0\\] (cleared by writing a 0)"] pub type MCS_R = crate::FieldReader; #[doc = "Field `MCS` writer - MediaLB Channel Status \\[31:0\\] (cleared by writing a 0)"] -pub type MCS_W<'a, const O: u8> = crate::FieldWriter<'a, MS0_SPEC, 32, O, u32>; +pub type MCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - MediaLB Channel Status \\[31:0\\] (cleared by writing a 0)"] @@ -53,28 +21,25 @@ impl W { (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn mcs(&mut self) -> MCS_W<0> { + pub fn mcs(&mut self) -> MCS_W { MCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MediaLB Channel Status 0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ms0](index.html) module"] +#[doc = "MediaLB Channel Status 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ms0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ms0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MS0_SPEC; impl crate::RegisterSpec for MS0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ms0::R](R) reader structure"] -impl crate::Readable for MS0_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ms0::W](W) writer structure"] +#[doc = "`read()` method returns [`ms0::R`](R) reader structure"] +impl crate::Readable for MS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ms0::W`](W) writer structure"] impl crate::Writable for MS0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/ms1.rs b/arch/cortex-m/samv71q21-pac/src/mlb/ms1.rs index 71aaf2d3..f60601dd 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/ms1.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/ms1.rs @@ -1,45 +1,13 @@ #[doc = "Register `MS1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MS1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MCS` reader - MediaLB Channel Status \\[63:32\\] (cleared by writing a 0)"] pub type MCS_R = crate::FieldReader; #[doc = "Field `MCS` writer - MediaLB Channel Status \\[63:32\\] (cleared by writing a 0)"] -pub type MCS_W<'a, const O: u8> = crate::FieldWriter<'a, MS1_SPEC, 32, O, u32>; +pub type MCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - MediaLB Channel Status \\[63:32\\] (cleared by writing a 0)"] @@ -53,28 +21,25 @@ impl W { (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn mcs(&mut self) -> MCS_W<0> { + pub fn mcs(&mut self) -> MCS_W { MCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MediaLB Channel Status1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ms1](index.html) module"] +#[doc = "MediaLB Channel Status1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ms1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ms1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MS1_SPEC; impl crate::RegisterSpec for MS1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ms1::R](R) reader structure"] -impl crate::Readable for MS1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ms1::W](W) writer structure"] +#[doc = "`read()` method returns [`ms1::R`](R) reader structure"] +impl crate::Readable for MS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ms1::W`](W) writer structure"] impl crate::Writable for MS1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/msd.rs b/arch/cortex-m/samv71q21-pac/src/mlb/msd.rs index 8136ce7b..b579f7db 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/msd.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/msd.rs @@ -1,18 +1,5 @@ #[doc = "Register `MSD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SD0` reader - System Data (Byte 0)"] pub type SD0_R = crate::FieldReader; #[doc = "Field `SD1` reader - System Data (Byte 1)"] @@ -43,15 +30,13 @@ impl R { SD3_R::new(((self.bits >> 24) & 0xff) as u8) } } -#[doc = "MediaLB System Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [msd](index.html) module"] +#[doc = "MediaLB System Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSD_SPEC; impl crate::RegisterSpec for MSD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [msd::R](R) reader structure"] -impl crate::Readable for MSD_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`msd::R`](R) reader structure"] +impl crate::Readable for MSD_SPEC {} #[doc = "`reset()` method sets MSD to value 0"] impl crate::Resettable for MSD_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/mlb/mss.rs b/arch/cortex-m/samv71q21-pac/src/mlb/mss.rs index 74a0c382..18bbb9e2 100644 --- a/arch/cortex-m/samv71q21-pac/src/mlb/mss.rs +++ b/arch/cortex-m/samv71q21-pac/src/mlb/mss.rs @@ -1,63 +1,31 @@ #[doc = "Register `MSS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MSS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RSTSYSCMD` reader - Reset System Command Detected in the System Quadlet (cleared by writing a 0)"] pub type RSTSYSCMD_R = crate::BitReader; #[doc = "Field `RSTSYSCMD` writer - Reset System Command Detected in the System Quadlet (cleared by writing a 0)"] -pub type RSTSYSCMD_W<'a, const O: u8> = crate::BitWriter<'a, MSS_SPEC, O>; +pub type RSTSYSCMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LKSYSCMD` reader - Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)"] pub type LKSYSCMD_R = crate::BitReader; #[doc = "Field `LKSYSCMD` writer - Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)"] -pub type LKSYSCMD_W<'a, const O: u8> = crate::BitWriter<'a, MSS_SPEC, O>; +pub type LKSYSCMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ULKSYSCMD` reader - Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)"] pub type ULKSYSCMD_R = crate::BitReader; #[doc = "Field `ULKSYSCMD` writer - Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)"] -pub type ULKSYSCMD_W<'a, const O: u8> = crate::BitWriter<'a, MSS_SPEC, O>; +pub type ULKSYSCMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSSYSCMD` reader - Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)"] pub type CSSYSCMD_R = crate::BitReader; #[doc = "Field `CSSYSCMD` writer - Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)"] -pub type CSSYSCMD_W<'a, const O: u8> = crate::BitWriter<'a, MSS_SPEC, O>; +pub type CSSYSCMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWSYSCMD` reader - Software System Command Detected in the System Quadlet (cleared by writing a 0)"] pub type SWSYSCMD_R = crate::BitReader; #[doc = "Field `SWSYSCMD` writer - Software System Command Detected in the System Quadlet (cleared by writing a 0)"] -pub type SWSYSCMD_W<'a, const O: u8> = crate::BitWriter<'a, MSS_SPEC, O>; +pub type SWSYSCMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SERVREQ` reader - Service Request Enabled"] pub type SERVREQ_R = crate::BitReader; #[doc = "Field `SERVREQ` writer - Service Request Enabled"] -pub type SERVREQ_W<'a, const O: u8> = crate::BitWriter<'a, MSS_SPEC, O>; +pub type SERVREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Reset System Command Detected in the System Quadlet (cleared by writing a 0)"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bit 0 - Reset System Command Detected in the System Quadlet (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn rstsyscmd(&mut self) -> RSTSYSCMD_W<0> { + pub fn rstsyscmd(&mut self) -> RSTSYSCMD_W { RSTSYSCMD_W::new(self) } #[doc = "Bit 1 - Network Lock System Command Detected in the System Quadlet (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn lksyscmd(&mut self) -> LKSYSCMD_W<1> { + pub fn lksyscmd(&mut self) -> LKSYSCMD_W { LKSYSCMD_W::new(self) } #[doc = "Bit 2 - Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn ulksyscmd(&mut self) -> ULKSYSCMD_W<2> { + pub fn ulksyscmd(&mut self) -> ULKSYSCMD_W { ULKSYSCMD_W::new(self) } #[doc = "Bit 3 - Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn cssyscmd(&mut self) -> CSSYSCMD_W<3> { + pub fn cssyscmd(&mut self) -> CSSYSCMD_W { CSSYSCMD_W::new(self) } #[doc = "Bit 4 - Software System Command Detected in the System Quadlet (cleared by writing a 0)"] #[inline(always)] #[must_use] - pub fn swsyscmd(&mut self) -> SWSYSCMD_W<4> { + pub fn swsyscmd(&mut self) -> SWSYSCMD_W { SWSYSCMD_W::new(self) } #[doc = "Bit 5 - Service Request Enabled"] #[inline(always)] #[must_use] - pub fn servreq(&mut self) -> SERVREQ_W<5> { + pub fn servreq(&mut self) -> SERVREQ_W { SERVREQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "MediaLB System Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mss](index.html) module"] +#[doc = "MediaLB System Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mss::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mss::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MSS_SPEC; impl crate::RegisterSpec for MSS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mss::R](R) reader structure"] -impl crate::Readable for MSS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mss::W](W) writer structure"] +#[doc = "`read()` method returns [`mss::R`](R) reader structure"] +impl crate::Readable for MSS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mss::W`](W) writer structure"] impl crate::Writable for MSS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa.rs b/arch/cortex-m/samv71q21-pac/src/pioa.rs index 17175591..ff04bbbe 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa.rs @@ -124,219 +124,273 @@ pub struct RegisterBlock { #[doc = "0x164 - Parallel Capture Reception Holding Register"] pub pcrhr: PCRHR, } -#[doc = "PER (w) register accessor: an alias for `Reg`"] +#[doc = "PER (w) register accessor: PIO Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`per::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`per`] +module"] pub type PER = crate::Reg; #[doc = "PIO Enable Register"] pub mod per; -#[doc = "PDR (w) register accessor: an alias for `Reg`"] +#[doc = "PDR (w) register accessor: PIO Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdr`] +module"] pub type PDR = crate::Reg; #[doc = "PIO Disable Register"] pub mod pdr; -#[doc = "PSR (r) register accessor: an alias for `Reg`"] +#[doc = "PSR (r) register accessor: PIO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`psr`] +module"] pub type PSR = crate::Reg; #[doc = "PIO Status Register"] pub mod psr; -#[doc = "OER (w) register accessor: an alias for `Reg`"] +#[doc = "OER (w) register accessor: Output Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oer::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`oer`] +module"] pub type OER = crate::Reg; #[doc = "Output Enable Register"] pub mod oer; -#[doc = "ODR (w) register accessor: an alias for `Reg`"] +#[doc = "ODR (w) register accessor: Output Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`odr`] +module"] pub type ODR = crate::Reg; #[doc = "Output Disable Register"] pub mod odr; -#[doc = "OSR (r) register accessor: an alias for `Reg`"] +#[doc = "OSR (r) register accessor: Output Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`osr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`osr`] +module"] pub type OSR = crate::Reg; #[doc = "Output Status Register"] pub mod osr; -#[doc = "IFER (w) register accessor: an alias for `Reg`"] +#[doc = "IFER (w) register accessor: Glitch Input Filter Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifer::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifer`] +module"] pub type IFER = crate::Reg; #[doc = "Glitch Input Filter Enable Register"] pub mod ifer; -#[doc = "IFDR (w) register accessor: an alias for `Reg`"] +#[doc = "IFDR (w) register accessor: Glitch Input Filter Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifdr`] +module"] pub type IFDR = crate::Reg; #[doc = "Glitch Input Filter Disable Register"] pub mod ifdr; -#[doc = "IFSR (r) register accessor: an alias for `Reg`"] +#[doc = "IFSR (r) register accessor: Glitch Input Filter Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifsr`] +module"] pub type IFSR = crate::Reg; #[doc = "Glitch Input Filter Status Register"] pub mod ifsr; -#[doc = "SODR (w) register accessor: an alias for `Reg`"] +#[doc = "SODR (w) register accessor: Set Output Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sodr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sodr`] +module"] pub type SODR = crate::Reg; #[doc = "Set Output Data Register"] pub mod sodr; -#[doc = "CODR (w) register accessor: an alias for `Reg`"] +#[doc = "CODR (w) register accessor: Clear Output Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`codr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`codr`] +module"] pub type CODR = crate::Reg; #[doc = "Clear Output Data Register"] pub mod codr; -#[doc = "ODSR (rw) register accessor: an alias for `Reg`"] +#[doc = "ODSR (rw) register accessor: Output Data Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`odsr`] +module"] pub type ODSR = crate::Reg; #[doc = "Output Data Status Register"] pub mod odsr; -#[doc = "PDSR (r) register accessor: an alias for `Reg`"] +#[doc = "PDSR (r) register accessor: Pin Data Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pdsr`] +module"] pub type PDSR = crate::Reg; #[doc = "Pin Data Status Register"] pub mod pdsr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "MDER (w) register accessor: an alias for `Reg`"] +#[doc = "MDER (w) register accessor: Multi-driver Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mder::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mder`] +module"] pub type MDER = crate::Reg; #[doc = "Multi-driver Enable Register"] pub mod mder; -#[doc = "MDDR (w) register accessor: an alias for `Reg`"] +#[doc = "MDDR (w) register accessor: Multi-driver Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mddr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mddr`] +module"] pub type MDDR = crate::Reg; #[doc = "Multi-driver Disable Register"] pub mod mddr; -#[doc = "MDSR (r) register accessor: an alias for `Reg`"] +#[doc = "MDSR (r) register accessor: Multi-driver Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mdsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mdsr`] +module"] pub type MDSR = crate::Reg; #[doc = "Multi-driver Status Register"] pub mod mdsr; -#[doc = "PUDR (w) register accessor: an alias for `Reg`"] +#[doc = "PUDR (w) register accessor: Pull-up Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pudr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pudr`] +module"] pub type PUDR = crate::Reg; #[doc = "Pull-up Disable Register"] pub mod pudr; -#[doc = "PUER (w) register accessor: an alias for `Reg`"] +#[doc = "PUER (w) register accessor: Pull-up Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`puer::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`puer`] +module"] pub type PUER = crate::Reg; #[doc = "Pull-up Enable Register"] pub mod puer; -#[doc = "PUSR (r) register accessor: an alias for `Reg`"] +#[doc = "PUSR (r) register accessor: Pad Pull-up Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pusr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pusr`] +module"] pub type PUSR = crate::Reg; #[doc = "Pad Pull-up Status Register"] pub mod pusr; -#[doc = "ABCDSR (rw) register accessor: an alias for `Reg`"] +#[doc = "ABCDSR (rw) register accessor: Peripheral ABCD Select Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abcdsr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abcdsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`abcdsr`] +module"] pub type ABCDSR = crate::Reg; #[doc = "Peripheral ABCD Select Register 0"] pub mod abcdsr; -#[doc = "IFSCDR (w) register accessor: an alias for `Reg`"] +#[doc = "IFSCDR (w) register accessor: Input Filter Slow Clock Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifscdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifscdr`] +module"] pub type IFSCDR = crate::Reg; #[doc = "Input Filter Slow Clock Disable Register"] pub mod ifscdr; -#[doc = "IFSCER (w) register accessor: an alias for `Reg`"] +#[doc = "IFSCER (w) register accessor: Input Filter Slow Clock Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifscer::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifscer`] +module"] pub type IFSCER = crate::Reg; #[doc = "Input Filter Slow Clock Enable Register"] pub mod ifscer; -#[doc = "IFSCSR (r) register accessor: an alias for `Reg`"] +#[doc = "IFSCSR (r) register accessor: Input Filter Slow Clock Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifscsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifscsr`] +module"] pub type IFSCSR = crate::Reg; #[doc = "Input Filter Slow Clock Status Register"] pub mod ifscsr; -#[doc = "SCDR (rw) register accessor: an alias for `Reg`"] +#[doc = "SCDR (rw) register accessor: Slow Clock Divider Debouncing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scdr`] +module"] pub type SCDR = crate::Reg; #[doc = "Slow Clock Divider Debouncing Register"] pub mod scdr; -#[doc = "PPDDR (w) register accessor: an alias for `Reg`"] +#[doc = "PPDDR (w) register accessor: Pad Pull-down Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppddr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ppddr`] +module"] pub type PPDDR = crate::Reg; #[doc = "Pad Pull-down Disable Register"] pub mod ppddr; -#[doc = "PPDER (w) register accessor: an alias for `Reg`"] +#[doc = "PPDER (w) register accessor: Pad Pull-down Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppder::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ppder`] +module"] pub type PPDER = crate::Reg; #[doc = "Pad Pull-down Enable Register"] pub mod ppder; -#[doc = "PPDSR (r) register accessor: an alias for `Reg`"] +#[doc = "PPDSR (r) register accessor: Pad Pull-down Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppdsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ppdsr`] +module"] pub type PPDSR = crate::Reg; #[doc = "Pad Pull-down Status Register"] pub mod ppdsr; -#[doc = "OWER (w) register accessor: an alias for `Reg`"] +#[doc = "OWER (w) register accessor: Output Write Enable\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ower::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ower`] +module"] pub type OWER = crate::Reg; #[doc = "Output Write Enable"] pub mod ower; -#[doc = "OWDR (w) register accessor: an alias for `Reg`"] +#[doc = "OWDR (w) register accessor: Output Write Disable\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`owdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`owdr`] +module"] pub type OWDR = crate::Reg; #[doc = "Output Write Disable"] pub mod owdr; -#[doc = "OWSR (r) register accessor: an alias for `Reg`"] +#[doc = "OWSR (r) register accessor: Output Write Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`owsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`owsr`] +module"] pub type OWSR = crate::Reg; #[doc = "Output Write Status Register"] pub mod owsr; -#[doc = "AIMER (w) register accessor: an alias for `Reg`"] +#[doc = "AIMER (w) register accessor: Additional Interrupt Modes Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aimer::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aimer`] +module"] pub type AIMER = crate::Reg; #[doc = "Additional Interrupt Modes Enable Register"] pub mod aimer; -#[doc = "AIMDR (w) register accessor: an alias for `Reg`"] +#[doc = "AIMDR (w) register accessor: Additional Interrupt Modes Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aimdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aimdr`] +module"] pub type AIMDR = crate::Reg; #[doc = "Additional Interrupt Modes Disable Register"] pub mod aimdr; -#[doc = "AIMMR (r) register accessor: an alias for `Reg`"] +#[doc = "AIMMR (r) register accessor: Additional Interrupt Modes Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aimmr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`aimmr`] +module"] pub type AIMMR = crate::Reg; #[doc = "Additional Interrupt Modes Mask Register"] pub mod aimmr; -#[doc = "ESR (w) register accessor: an alias for `Reg`"] +#[doc = "ESR (w) register accessor: Edge Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`esr`] +module"] pub type ESR = crate::Reg; #[doc = "Edge Select Register"] pub mod esr; -#[doc = "LSR (w) register accessor: an alias for `Reg`"] +#[doc = "LSR (w) register accessor: Level Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lsr`] +module"] pub type LSR = crate::Reg; #[doc = "Level Select Register"] pub mod lsr; -#[doc = "ELSR (r) register accessor: an alias for `Reg`"] +#[doc = "ELSR (r) register accessor: Edge/Level Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`elsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`elsr`] +module"] pub type ELSR = crate::Reg; #[doc = "Edge/Level Status Register"] pub mod elsr; -#[doc = "FELLSR (w) register accessor: an alias for `Reg`"] +#[doc = "FELLSR (w) register accessor: Falling Edge/Low-Level Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fellsr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fellsr`] +module"] pub type FELLSR = crate::Reg; #[doc = "Falling Edge/Low-Level Select Register"] pub mod fellsr; -#[doc = "REHLSR (w) register accessor: an alias for `Reg`"] +#[doc = "REHLSR (w) register accessor: Rising Edge/High-Level Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rehlsr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rehlsr`] +module"] pub type REHLSR = crate::Reg; #[doc = "Rising Edge/High-Level Select Register"] pub mod rehlsr; -#[doc = "FRLHSR (r) register accessor: an alias for `Reg`"] +#[doc = "FRLHSR (r) register accessor: Fall/Rise - Low/High Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frlhsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`frlhsr`] +module"] pub type FRLHSR = crate::Reg; #[doc = "Fall/Rise - Low/High Status Register"] pub mod frlhsr; -#[doc = "LOCKSR (r) register accessor: an alias for `Reg`"] +#[doc = "LOCKSR (r) register accessor: Lock Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`locksr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`locksr`] +module"] pub type LOCKSR = crate::Reg; #[doc = "Lock Status"] pub mod locksr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; -#[doc = "SCHMITT (rw) register accessor: an alias for `Reg`"] +#[doc = "SCHMITT (rw) register accessor: Schmitt Trigger Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`schmitt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`schmitt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`schmitt`] +module"] pub type SCHMITT = crate::Reg; #[doc = "Schmitt Trigger Register"] pub mod schmitt; -#[doc = "DRIVER (rw) register accessor: an alias for `Reg`"] +#[doc = "DRIVER (rw) register accessor: I/O Drive Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`driver::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`driver::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`driver`] +module"] pub type DRIVER = crate::Reg; #[doc = "I/O Drive Register"] pub mod driver; -#[doc = "PCMR (rw) register accessor: an alias for `Reg`"] +#[doc = "PCMR (rw) register accessor: Parallel Capture Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcmr`] +module"] pub type PCMR = crate::Reg; #[doc = "Parallel Capture Mode Register"] pub mod pcmr; -#[doc = "PCIER (w) register accessor: an alias for `Reg`"] +#[doc = "PCIER (w) register accessor: Parallel Capture Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcier`] +module"] pub type PCIER = crate::Reg; #[doc = "Parallel Capture Interrupt Enable Register"] pub mod pcier; -#[doc = "PCIDR (w) register accessor: an alias for `Reg`"] +#[doc = "PCIDR (w) register accessor: Parallel Capture Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcidr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcidr`] +module"] pub type PCIDR = crate::Reg; #[doc = "Parallel Capture Interrupt Disable Register"] pub mod pcidr; -#[doc = "PCIMR (r) register accessor: an alias for `Reg`"] +#[doc = "PCIMR (r) register accessor: Parallel Capture Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcimr`] +module"] pub type PCIMR = crate::Reg; #[doc = "Parallel Capture Interrupt Mask Register"] pub mod pcimr; -#[doc = "PCISR (r) register accessor: an alias for `Reg`"] +#[doc = "PCISR (r) register accessor: Parallel Capture Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcisr`] +module"] pub type PCISR = crate::Reg; #[doc = "Parallel Capture Interrupt Status Register"] pub mod pcisr; -#[doc = "PCRHR (r) register accessor: an alias for `Reg`"] +#[doc = "PCRHR (r) register accessor: Parallel Capture Reception Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcrhr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcrhr`] +module"] pub type PCRHR = crate::Reg; #[doc = "Parallel Capture Reception Holding Register"] pub mod pcrhr; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/abcdsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/abcdsr.rs index 967a7002..e37195ef 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/abcdsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/abcdsr.rs @@ -1,167 +1,135 @@ #[doc = "Register `ABCDSR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ABCDSR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` reader - Peripheral Select"] pub type P0_R = crate::BitReader; #[doc = "Field `P0` writer - Peripheral Select"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` reader - Peripheral Select"] pub type P1_R = crate::BitReader; #[doc = "Field `P1` writer - Peripheral Select"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` reader - Peripheral Select"] pub type P2_R = crate::BitReader; #[doc = "Field `P2` writer - Peripheral Select"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` reader - Peripheral Select"] pub type P3_R = crate::BitReader; #[doc = "Field `P3` writer - Peripheral Select"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` reader - Peripheral Select"] pub type P4_R = crate::BitReader; #[doc = "Field `P4` writer - Peripheral Select"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` reader - Peripheral Select"] pub type P5_R = crate::BitReader; #[doc = "Field `P5` writer - Peripheral Select"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` reader - Peripheral Select"] pub type P6_R = crate::BitReader; #[doc = "Field `P6` writer - Peripheral Select"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` reader - Peripheral Select"] pub type P7_R = crate::BitReader; #[doc = "Field `P7` writer - Peripheral Select"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` reader - Peripheral Select"] pub type P8_R = crate::BitReader; #[doc = "Field `P8` writer - Peripheral Select"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` reader - Peripheral Select"] pub type P9_R = crate::BitReader; #[doc = "Field `P9` writer - Peripheral Select"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` reader - Peripheral Select"] pub type P10_R = crate::BitReader; #[doc = "Field `P10` writer - Peripheral Select"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` reader - Peripheral Select"] pub type P11_R = crate::BitReader; #[doc = "Field `P11` writer - Peripheral Select"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` reader - Peripheral Select"] pub type P12_R = crate::BitReader; #[doc = "Field `P12` writer - Peripheral Select"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` reader - Peripheral Select"] pub type P13_R = crate::BitReader; #[doc = "Field `P13` writer - Peripheral Select"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` reader - Peripheral Select"] pub type P14_R = crate::BitReader; #[doc = "Field `P14` writer - Peripheral Select"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` reader - Peripheral Select"] pub type P15_R = crate::BitReader; #[doc = "Field `P15` writer - Peripheral Select"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` reader - Peripheral Select"] pub type P16_R = crate::BitReader; #[doc = "Field `P16` writer - Peripheral Select"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` reader - Peripheral Select"] pub type P17_R = crate::BitReader; #[doc = "Field `P17` writer - Peripheral Select"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` reader - Peripheral Select"] pub type P18_R = crate::BitReader; #[doc = "Field `P18` writer - Peripheral Select"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` reader - Peripheral Select"] pub type P19_R = crate::BitReader; #[doc = "Field `P19` writer - Peripheral Select"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` reader - Peripheral Select"] pub type P20_R = crate::BitReader; #[doc = "Field `P20` writer - Peripheral Select"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` reader - Peripheral Select"] pub type P21_R = crate::BitReader; #[doc = "Field `P21` writer - Peripheral Select"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` reader - Peripheral Select"] pub type P22_R = crate::BitReader; #[doc = "Field `P22` writer - Peripheral Select"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` reader - Peripheral Select"] pub type P23_R = crate::BitReader; #[doc = "Field `P23` writer - Peripheral Select"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` reader - Peripheral Select"] pub type P24_R = crate::BitReader; #[doc = "Field `P24` writer - Peripheral Select"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` reader - Peripheral Select"] pub type P25_R = crate::BitReader; #[doc = "Field `P25` writer - Peripheral Select"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` reader - Peripheral Select"] pub type P26_R = crate::BitReader; #[doc = "Field `P26` writer - Peripheral Select"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` reader - Peripheral Select"] pub type P27_R = crate::BitReader; #[doc = "Field `P27` writer - Peripheral Select"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` reader - Peripheral Select"] pub type P28_R = crate::BitReader; #[doc = "Field `P28` writer - Peripheral Select"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` reader - Peripheral Select"] pub type P29_R = crate::BitReader; #[doc = "Field `P29` writer - Peripheral Select"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` reader - Peripheral Select"] pub type P30_R = crate::BitReader; #[doc = "Field `P30` writer - Peripheral Select"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` reader - Peripheral Select"] pub type P31_R = crate::BitReader; #[doc = "Field `P31` writer - Peripheral Select"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, ABCDSR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Peripheral Select"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral ABCD Select Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [abcdsr](index.html) module"] +#[doc = "Peripheral ABCD Select Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abcdsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abcdsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ABCDSR_SPEC; impl crate::RegisterSpec for ABCDSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [abcdsr::R](R) reader structure"] -impl crate::Readable for ABCDSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [abcdsr::W](W) writer structure"] +#[doc = "`read()` method returns [`abcdsr::R`](R) reader structure"] +impl crate::Readable for ABCDSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`abcdsr::W`](W) writer structure"] impl crate::Writable for ABCDSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/aimdr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/aimdr.rs index 7e03d416..de13fdf6 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/aimdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/aimdr.rs @@ -1,296 +1,276 @@ #[doc = "Register `AIMDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Additional Interrupt Modes Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Additional Interrupt Modes Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Additional Interrupt Modes Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Additional Interrupt Modes Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Additional Interrupt Modes Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Additional Interrupt Modes Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Additional Interrupt Modes Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Additional Interrupt Modes Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Additional Interrupt Modes Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Additional Interrupt Modes Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Additional Interrupt Modes Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Additional Interrupt Modes Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Additional Interrupt Modes Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Additional Interrupt Modes Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Additional Interrupt Modes Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Additional Interrupt Modes Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Additional Interrupt Modes Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Additional Interrupt Modes Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Additional Interrupt Modes Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Additional Interrupt Modes Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Additional Interrupt Modes Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Additional Interrupt Modes Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Additional Interrupt Modes Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Additional Interrupt Modes Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Additional Interrupt Modes Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Additional Interrupt Modes Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Additional Interrupt Modes Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Additional Interrupt Modes Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Additional Interrupt Modes Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Additional Interrupt Modes Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Additional Interrupt Modes Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Additional Interrupt Modes Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, AIMDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Additional Interrupt Modes Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Additional Interrupt Modes Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aimdr](index.html) module"] +#[doc = "Additional Interrupt Modes Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aimdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AIMDR_SPEC; impl crate::RegisterSpec for AIMDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [aimdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`aimdr::W`](W) writer structure"] impl crate::Writable for AIMDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/aimer.rs b/arch/cortex-m/samv71q21-pac/src/pioa/aimer.rs index 325fad69..b2eba071 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/aimer.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/aimer.rs @@ -1,296 +1,276 @@ #[doc = "Register `AIMER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Additional Interrupt Modes Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Additional Interrupt Modes Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Additional Interrupt Modes Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Additional Interrupt Modes Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Additional Interrupt Modes Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Additional Interrupt Modes Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Additional Interrupt Modes Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Additional Interrupt Modes Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Additional Interrupt Modes Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Additional Interrupt Modes Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Additional Interrupt Modes Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Additional Interrupt Modes Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Additional Interrupt Modes Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Additional Interrupt Modes Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Additional Interrupt Modes Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Additional Interrupt Modes Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Additional Interrupt Modes Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Additional Interrupt Modes Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Additional Interrupt Modes Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Additional Interrupt Modes Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Additional Interrupt Modes Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Additional Interrupt Modes Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Additional Interrupt Modes Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Additional Interrupt Modes Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Additional Interrupt Modes Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Additional Interrupt Modes Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Additional Interrupt Modes Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Additional Interrupt Modes Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Additional Interrupt Modes Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Additional Interrupt Modes Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Additional Interrupt Modes Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Additional Interrupt Modes Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, AIMER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Additional Interrupt Modes Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Additional Interrupt Modes Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aimer](index.html) module"] +#[doc = "Additional Interrupt Modes Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`aimer::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AIMER_SPEC; impl crate::RegisterSpec for AIMER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [aimer::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`aimer::W`](W) writer structure"] impl crate::Writable for AIMER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/aimmr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/aimmr.rs index 5aac97c6..ec859d58 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/aimmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/aimmr.rs @@ -1,18 +1,5 @@ #[doc = "Register `AIMMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - IO Line Index"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - IO Line Index"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Additional Interrupt Modes Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [aimmr](index.html) module"] +#[doc = "Additional Interrupt Modes Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`aimmr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AIMMR_SPEC; impl crate::RegisterSpec for AIMMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [aimmr::R](R) reader structure"] -impl crate::Readable for AIMMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`aimmr::R`](R) reader structure"] +impl crate::Readable for AIMMR_SPEC {} #[doc = "`reset()` method sets AIMMR to value 0"] impl crate::Resettable for AIMMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/codr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/codr.rs index 6af3e449..94c9199b 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/codr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/codr.rs @@ -1,296 +1,276 @@ #[doc = "Register `CODR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Clear Output Data"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Clear Output Data"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Clear Output Data"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Clear Output Data"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Clear Output Data"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Clear Output Data"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Clear Output Data"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Clear Output Data"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Clear Output Data"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Clear Output Data"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Clear Output Data"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Clear Output Data"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Clear Output Data"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Clear Output Data"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Clear Output Data"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Clear Output Data"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Clear Output Data"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Clear Output Data"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Clear Output Data"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Clear Output Data"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Clear Output Data"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Clear Output Data"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Clear Output Data"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Clear Output Data"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Clear Output Data"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Clear Output Data"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Clear Output Data"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Clear Output Data"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Clear Output Data"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Clear Output Data"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Clear Output Data"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Clear Output Data"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, CODR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Clear Output Data"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clear Output Data Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [codr](index.html) module"] +#[doc = "Clear Output Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`codr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CODR_SPEC; impl crate::RegisterSpec for CODR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [codr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`codr::W`](W) writer structure"] impl crate::Writable for CODR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/driver.rs b/arch/cortex-m/samv71q21-pac/src/pioa/driver.rs index 6749b2bf..8ee240ef 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/driver.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/driver.rs @@ -1,39 +1,7 @@ #[doc = "Register `DRIVER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DRIVER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LINE0` reader - Drive of PIO Line 0"] pub type LINE0_R = crate::BitReader; #[doc = "Drive of PIO Line 0\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl LINE0_R { true => LINE0SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE0SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE0SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE0` writer - Drive of PIO Line 0"] -pub type LINE0_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE0SELECT_A>; -impl<'a, const O: u8> LINE0_W<'a, O> { +pub type LINE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE0SELECT_A>; +impl<'a, REG, const O: u8> LINE0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE0SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE0SELECT_A::HIGH_DRIVE) } } @@ -109,28 +80,31 @@ impl LINE1_R { true => LINE1SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE1SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE1SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE1` writer - Drive of PIO Line 1"] -pub type LINE1_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE1SELECT_A>; -impl<'a, const O: u8> LINE1_W<'a, O> { +pub type LINE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE1SELECT_A>; +impl<'a, REG, const O: u8> LINE1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE1SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE1SELECT_A::HIGH_DRIVE) } } @@ -159,28 +133,31 @@ impl LINE2_R { true => LINE2SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE2SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE2SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE2` writer - Drive of PIO Line 2"] -pub type LINE2_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE2SELECT_A>; -impl<'a, const O: u8> LINE2_W<'a, O> { +pub type LINE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE2SELECT_A>; +impl<'a, REG, const O: u8> LINE2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE2SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE2SELECT_A::HIGH_DRIVE) } } @@ -209,28 +186,31 @@ impl LINE3_R { true => LINE3SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE3SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE3SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE3` writer - Drive of PIO Line 3"] -pub type LINE3_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE3SELECT_A>; -impl<'a, const O: u8> LINE3_W<'a, O> { +pub type LINE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE3SELECT_A>; +impl<'a, REG, const O: u8> LINE3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE3SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE3SELECT_A::HIGH_DRIVE) } } @@ -259,28 +239,31 @@ impl LINE4_R { true => LINE4SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE4SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE4SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE4` writer - Drive of PIO Line 4"] -pub type LINE4_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE4SELECT_A>; -impl<'a, const O: u8> LINE4_W<'a, O> { +pub type LINE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE4SELECT_A>; +impl<'a, REG, const O: u8> LINE4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE4SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE4SELECT_A::HIGH_DRIVE) } } @@ -309,28 +292,31 @@ impl LINE5_R { true => LINE5SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE5SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE5SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE5` writer - Drive of PIO Line 5"] -pub type LINE5_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE5SELECT_A>; -impl<'a, const O: u8> LINE5_W<'a, O> { +pub type LINE5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE5SELECT_A>; +impl<'a, REG, const O: u8> LINE5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE5SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE5SELECT_A::HIGH_DRIVE) } } @@ -359,28 +345,31 @@ impl LINE6_R { true => LINE6SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE6SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE6SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE6` writer - Drive of PIO Line 6"] -pub type LINE6_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE6SELECT_A>; -impl<'a, const O: u8> LINE6_W<'a, O> { +pub type LINE6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE6SELECT_A>; +impl<'a, REG, const O: u8> LINE6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE6SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE6SELECT_A::HIGH_DRIVE) } } @@ -409,28 +398,31 @@ impl LINE7_R { true => LINE7SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE7SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE7SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE7` writer - Drive of PIO Line 7"] -pub type LINE7_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE7SELECT_A>; -impl<'a, const O: u8> LINE7_W<'a, O> { +pub type LINE7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE7SELECT_A>; +impl<'a, REG, const O: u8> LINE7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE7SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE7SELECT_A::HIGH_DRIVE) } } @@ -459,28 +451,31 @@ impl LINE8_R { true => LINE8SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE8SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE8SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE8` writer - Drive of PIO Line 8"] -pub type LINE8_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE8SELECT_A>; -impl<'a, const O: u8> LINE8_W<'a, O> { +pub type LINE8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE8SELECT_A>; +impl<'a, REG, const O: u8> LINE8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE8SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE8SELECT_A::HIGH_DRIVE) } } @@ -509,28 +504,31 @@ impl LINE9_R { true => LINE9SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE9SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE9SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE9` writer - Drive of PIO Line 9"] -pub type LINE9_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE9SELECT_A>; -impl<'a, const O: u8> LINE9_W<'a, O> { +pub type LINE9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE9SELECT_A>; +impl<'a, REG, const O: u8> LINE9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE9SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE9SELECT_A::HIGH_DRIVE) } } @@ -559,28 +557,31 @@ impl LINE10_R { true => LINE10SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE10SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE10SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE10` writer - Drive of PIO Line 10"] -pub type LINE10_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE10SELECT_A>; -impl<'a, const O: u8> LINE10_W<'a, O> { +pub type LINE10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE10SELECT_A>; +impl<'a, REG, const O: u8> LINE10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE10SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE10SELECT_A::HIGH_DRIVE) } } @@ -609,28 +610,31 @@ impl LINE11_R { true => LINE11SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE11SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE11SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE11` writer - Drive of PIO Line 11"] -pub type LINE11_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE11SELECT_A>; -impl<'a, const O: u8> LINE11_W<'a, O> { +pub type LINE11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE11SELECT_A>; +impl<'a, REG, const O: u8> LINE11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE11SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE11SELECT_A::HIGH_DRIVE) } } @@ -659,28 +663,31 @@ impl LINE12_R { true => LINE12SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE12SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE12SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE12` writer - Drive of PIO Line 12"] -pub type LINE12_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE12SELECT_A>; -impl<'a, const O: u8> LINE12_W<'a, O> { +pub type LINE12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE12SELECT_A>; +impl<'a, REG, const O: u8> LINE12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE12SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE12SELECT_A::HIGH_DRIVE) } } @@ -709,28 +716,31 @@ impl LINE13_R { true => LINE13SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE13SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE13SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE13` writer - Drive of PIO Line 13"] -pub type LINE13_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE13SELECT_A>; -impl<'a, const O: u8> LINE13_W<'a, O> { +pub type LINE13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE13SELECT_A>; +impl<'a, REG, const O: u8> LINE13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE13SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE13SELECT_A::HIGH_DRIVE) } } @@ -759,28 +769,31 @@ impl LINE14_R { true => LINE14SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE14SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE14SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE14` writer - Drive of PIO Line 14"] -pub type LINE14_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE14SELECT_A>; -impl<'a, const O: u8> LINE14_W<'a, O> { +pub type LINE14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE14SELECT_A>; +impl<'a, REG, const O: u8> LINE14_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE14SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE14SELECT_A::HIGH_DRIVE) } } @@ -809,28 +822,31 @@ impl LINE15_R { true => LINE15SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE15SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE15SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE15` writer - Drive of PIO Line 15"] -pub type LINE15_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE15SELECT_A>; -impl<'a, const O: u8> LINE15_W<'a, O> { +pub type LINE15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE15SELECT_A>; +impl<'a, REG, const O: u8> LINE15_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE15SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE15SELECT_A::HIGH_DRIVE) } } @@ -859,28 +875,31 @@ impl LINE16_R { true => LINE16SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE16SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE16SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE16` writer - Drive of PIO Line 16"] -pub type LINE16_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE16SELECT_A>; -impl<'a, const O: u8> LINE16_W<'a, O> { +pub type LINE16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE16SELECT_A>; +impl<'a, REG, const O: u8> LINE16_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE16SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE16SELECT_A::HIGH_DRIVE) } } @@ -909,28 +928,31 @@ impl LINE17_R { true => LINE17SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE17SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE17SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE17` writer - Drive of PIO Line 17"] -pub type LINE17_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE17SELECT_A>; -impl<'a, const O: u8> LINE17_W<'a, O> { +pub type LINE17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE17SELECT_A>; +impl<'a, REG, const O: u8> LINE17_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE17SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE17SELECT_A::HIGH_DRIVE) } } @@ -959,28 +981,31 @@ impl LINE18_R { true => LINE18SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE18SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE18SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE18` writer - Drive of PIO Line 18"] -pub type LINE18_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE18SELECT_A>; -impl<'a, const O: u8> LINE18_W<'a, O> { +pub type LINE18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE18SELECT_A>; +impl<'a, REG, const O: u8> LINE18_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE18SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE18SELECT_A::HIGH_DRIVE) } } @@ -1009,28 +1034,31 @@ impl LINE19_R { true => LINE19SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE19SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE19SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE19` writer - Drive of PIO Line 19"] -pub type LINE19_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE19SELECT_A>; -impl<'a, const O: u8> LINE19_W<'a, O> { +pub type LINE19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE19SELECT_A>; +impl<'a, REG, const O: u8> LINE19_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE19SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE19SELECT_A::HIGH_DRIVE) } } @@ -1059,28 +1087,31 @@ impl LINE20_R { true => LINE20SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE20SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE20SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE20` writer - Drive of PIO Line 20"] -pub type LINE20_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE20SELECT_A>; -impl<'a, const O: u8> LINE20_W<'a, O> { +pub type LINE20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE20SELECT_A>; +impl<'a, REG, const O: u8> LINE20_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE20SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE20SELECT_A::HIGH_DRIVE) } } @@ -1109,28 +1140,31 @@ impl LINE21_R { true => LINE21SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE21SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE21SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE21` writer - Drive of PIO Line 21"] -pub type LINE21_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE21SELECT_A>; -impl<'a, const O: u8> LINE21_W<'a, O> { +pub type LINE21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE21SELECT_A>; +impl<'a, REG, const O: u8> LINE21_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE21SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE21SELECT_A::HIGH_DRIVE) } } @@ -1159,28 +1193,31 @@ impl LINE22_R { true => LINE22SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE22SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE22SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE22` writer - Drive of PIO Line 22"] -pub type LINE22_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE22SELECT_A>; -impl<'a, const O: u8> LINE22_W<'a, O> { +pub type LINE22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE22SELECT_A>; +impl<'a, REG, const O: u8> LINE22_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE22SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE22SELECT_A::HIGH_DRIVE) } } @@ -1209,28 +1246,31 @@ impl LINE23_R { true => LINE23SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE23SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE23SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE23` writer - Drive of PIO Line 23"] -pub type LINE23_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE23SELECT_A>; -impl<'a, const O: u8> LINE23_W<'a, O> { +pub type LINE23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE23SELECT_A>; +impl<'a, REG, const O: u8> LINE23_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE23SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE23SELECT_A::HIGH_DRIVE) } } @@ -1259,28 +1299,31 @@ impl LINE24_R { true => LINE24SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE24SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE24SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE24` writer - Drive of PIO Line 24"] -pub type LINE24_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE24SELECT_A>; -impl<'a, const O: u8> LINE24_W<'a, O> { +pub type LINE24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE24SELECT_A>; +impl<'a, REG, const O: u8> LINE24_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE24SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE24SELECT_A::HIGH_DRIVE) } } @@ -1309,28 +1352,31 @@ impl LINE25_R { true => LINE25SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE25SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE25SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE25` writer - Drive of PIO Line 25"] -pub type LINE25_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE25SELECT_A>; -impl<'a, const O: u8> LINE25_W<'a, O> { +pub type LINE25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE25SELECT_A>; +impl<'a, REG, const O: u8> LINE25_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE25SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE25SELECT_A::HIGH_DRIVE) } } @@ -1359,28 +1405,31 @@ impl LINE26_R { true => LINE26SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE26SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE26SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE26` writer - Drive of PIO Line 26"] -pub type LINE26_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE26SELECT_A>; -impl<'a, const O: u8> LINE26_W<'a, O> { +pub type LINE26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE26SELECT_A>; +impl<'a, REG, const O: u8> LINE26_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE26SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE26SELECT_A::HIGH_DRIVE) } } @@ -1409,28 +1458,31 @@ impl LINE27_R { true => LINE27SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE27SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE27SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE27` writer - Drive of PIO Line 27"] -pub type LINE27_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE27SELECT_A>; -impl<'a, const O: u8> LINE27_W<'a, O> { +pub type LINE27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE27SELECT_A>; +impl<'a, REG, const O: u8> LINE27_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE27SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE27SELECT_A::HIGH_DRIVE) } } @@ -1459,28 +1511,31 @@ impl LINE28_R { true => LINE28SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE28SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE28SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE28` writer - Drive of PIO Line 28"] -pub type LINE28_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE28SELECT_A>; -impl<'a, const O: u8> LINE28_W<'a, O> { +pub type LINE28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE28SELECT_A>; +impl<'a, REG, const O: u8> LINE28_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE28SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE28SELECT_A::HIGH_DRIVE) } } @@ -1509,28 +1564,31 @@ impl LINE29_R { true => LINE29SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE29SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE29SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE29` writer - Drive of PIO Line 29"] -pub type LINE29_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE29SELECT_A>; -impl<'a, const O: u8> LINE29_W<'a, O> { +pub type LINE29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE29SELECT_A>; +impl<'a, REG, const O: u8> LINE29_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE29SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE29SELECT_A::HIGH_DRIVE) } } @@ -1559,28 +1617,31 @@ impl LINE30_R { true => LINE30SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE30SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE30SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE30` writer - Drive of PIO Line 30"] -pub type LINE30_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE30SELECT_A>; -impl<'a, const O: u8> LINE30_W<'a, O> { +pub type LINE30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE30SELECT_A>; +impl<'a, REG, const O: u8> LINE30_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE30SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE30SELECT_A::HIGH_DRIVE) } } @@ -1609,28 +1670,31 @@ impl LINE31_R { true => LINE31SELECT_A::HIGH_DRIVE, } } - #[doc = "Checks if the value of the field is `LOW_DRIVE`"] + #[doc = "Lowest drive"] #[inline(always)] pub fn is_low_drive(&self) -> bool { *self == LINE31SELECT_A::LOW_DRIVE } - #[doc = "Checks if the value of the field is `HIGH_DRIVE`"] + #[doc = "Highest drive"] #[inline(always)] pub fn is_high_drive(&self) -> bool { *self == LINE31SELECT_A::HIGH_DRIVE } } #[doc = "Field `LINE31` writer - Drive of PIO Line 31"] -pub type LINE31_W<'a, const O: u8> = crate::BitWriter<'a, DRIVER_SPEC, O, LINE31SELECT_A>; -impl<'a, const O: u8> LINE31_W<'a, O> { +pub type LINE31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LINE31SELECT_A>; +impl<'a, REG, const O: u8> LINE31_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Lowest drive"] #[inline(always)] - pub fn low_drive(self) -> &'a mut W { + pub fn low_drive(self) -> &'a mut crate::W { self.variant(LINE31SELECT_A::LOW_DRIVE) } #[doc = "Highest drive"] #[inline(always)] - pub fn high_drive(self) -> &'a mut W { + pub fn high_drive(self) -> &'a mut crate::W { self.variant(LINE31SELECT_A::HIGH_DRIVE) } } @@ -1800,214 +1864,211 @@ impl W { #[doc = "Bit 0 - Drive of PIO Line 0"] #[inline(always)] #[must_use] - pub fn line0(&mut self) -> LINE0_W<0> { + pub fn line0(&mut self) -> LINE0_W { LINE0_W::new(self) } #[doc = "Bit 1 - Drive of PIO Line 1"] #[inline(always)] #[must_use] - pub fn line1(&mut self) -> LINE1_W<1> { + pub fn line1(&mut self) -> LINE1_W { LINE1_W::new(self) } #[doc = "Bit 2 - Drive of PIO Line 2"] #[inline(always)] #[must_use] - pub fn line2(&mut self) -> LINE2_W<2> { + pub fn line2(&mut self) -> LINE2_W { LINE2_W::new(self) } #[doc = "Bit 3 - Drive of PIO Line 3"] #[inline(always)] #[must_use] - pub fn line3(&mut self) -> LINE3_W<3> { + pub fn line3(&mut self) -> LINE3_W { LINE3_W::new(self) } #[doc = "Bit 4 - Drive of PIO Line 4"] #[inline(always)] #[must_use] - pub fn line4(&mut self) -> LINE4_W<4> { + pub fn line4(&mut self) -> LINE4_W { LINE4_W::new(self) } #[doc = "Bit 5 - Drive of PIO Line 5"] #[inline(always)] #[must_use] - pub fn line5(&mut self) -> LINE5_W<5> { + pub fn line5(&mut self) -> LINE5_W { LINE5_W::new(self) } #[doc = "Bit 6 - Drive of PIO Line 6"] #[inline(always)] #[must_use] - pub fn line6(&mut self) -> LINE6_W<6> { + pub fn line6(&mut self) -> LINE6_W { LINE6_W::new(self) } #[doc = "Bit 7 - Drive of PIO Line 7"] #[inline(always)] #[must_use] - pub fn line7(&mut self) -> LINE7_W<7> { + pub fn line7(&mut self) -> LINE7_W { LINE7_W::new(self) } #[doc = "Bit 8 - Drive of PIO Line 8"] #[inline(always)] #[must_use] - pub fn line8(&mut self) -> LINE8_W<8> { + pub fn line8(&mut self) -> LINE8_W { LINE8_W::new(self) } #[doc = "Bit 9 - Drive of PIO Line 9"] #[inline(always)] #[must_use] - pub fn line9(&mut self) -> LINE9_W<9> { + pub fn line9(&mut self) -> LINE9_W { LINE9_W::new(self) } #[doc = "Bit 10 - Drive of PIO Line 10"] #[inline(always)] #[must_use] - pub fn line10(&mut self) -> LINE10_W<10> { + pub fn line10(&mut self) -> LINE10_W { LINE10_W::new(self) } #[doc = "Bit 11 - Drive of PIO Line 11"] #[inline(always)] #[must_use] - pub fn line11(&mut self) -> LINE11_W<11> { + pub fn line11(&mut self) -> LINE11_W { LINE11_W::new(self) } #[doc = "Bit 12 - Drive of PIO Line 12"] #[inline(always)] #[must_use] - pub fn line12(&mut self) -> LINE12_W<12> { + pub fn line12(&mut self) -> LINE12_W { LINE12_W::new(self) } #[doc = "Bit 13 - Drive of PIO Line 13"] #[inline(always)] #[must_use] - pub fn line13(&mut self) -> LINE13_W<13> { + pub fn line13(&mut self) -> LINE13_W { LINE13_W::new(self) } #[doc = "Bit 14 - Drive of PIO Line 14"] #[inline(always)] #[must_use] - pub fn line14(&mut self) -> LINE14_W<14> { + pub fn line14(&mut self) -> LINE14_W { LINE14_W::new(self) } #[doc = "Bit 15 - Drive of PIO Line 15"] #[inline(always)] #[must_use] - pub fn line15(&mut self) -> LINE15_W<15> { + pub fn line15(&mut self) -> LINE15_W { LINE15_W::new(self) } #[doc = "Bit 16 - Drive of PIO Line 16"] #[inline(always)] #[must_use] - pub fn line16(&mut self) -> LINE16_W<16> { + pub fn line16(&mut self) -> LINE16_W { LINE16_W::new(self) } #[doc = "Bit 17 - Drive of PIO Line 17"] #[inline(always)] #[must_use] - pub fn line17(&mut self) -> LINE17_W<17> { + pub fn line17(&mut self) -> LINE17_W { LINE17_W::new(self) } #[doc = "Bit 18 - Drive of PIO Line 18"] #[inline(always)] #[must_use] - pub fn line18(&mut self) -> LINE18_W<18> { + pub fn line18(&mut self) -> LINE18_W { LINE18_W::new(self) } #[doc = "Bit 19 - Drive of PIO Line 19"] #[inline(always)] #[must_use] - pub fn line19(&mut self) -> LINE19_W<19> { + pub fn line19(&mut self) -> LINE19_W { LINE19_W::new(self) } #[doc = "Bit 20 - Drive of PIO Line 20"] #[inline(always)] #[must_use] - pub fn line20(&mut self) -> LINE20_W<20> { + pub fn line20(&mut self) -> LINE20_W { LINE20_W::new(self) } #[doc = "Bit 21 - Drive of PIO Line 21"] #[inline(always)] #[must_use] - pub fn line21(&mut self) -> LINE21_W<21> { + pub fn line21(&mut self) -> LINE21_W { LINE21_W::new(self) } #[doc = "Bit 22 - Drive of PIO Line 22"] #[inline(always)] #[must_use] - pub fn line22(&mut self) -> LINE22_W<22> { + pub fn line22(&mut self) -> LINE22_W { LINE22_W::new(self) } #[doc = "Bit 23 - Drive of PIO Line 23"] #[inline(always)] #[must_use] - pub fn line23(&mut self) -> LINE23_W<23> { + pub fn line23(&mut self) -> LINE23_W { LINE23_W::new(self) } #[doc = "Bit 24 - Drive of PIO Line 24"] #[inline(always)] #[must_use] - pub fn line24(&mut self) -> LINE24_W<24> { + pub fn line24(&mut self) -> LINE24_W { LINE24_W::new(self) } #[doc = "Bit 25 - Drive of PIO Line 25"] #[inline(always)] #[must_use] - pub fn line25(&mut self) -> LINE25_W<25> { + pub fn line25(&mut self) -> LINE25_W { LINE25_W::new(self) } #[doc = "Bit 26 - Drive of PIO Line 26"] #[inline(always)] #[must_use] - pub fn line26(&mut self) -> LINE26_W<26> { + pub fn line26(&mut self) -> LINE26_W { LINE26_W::new(self) } #[doc = "Bit 27 - Drive of PIO Line 27"] #[inline(always)] #[must_use] - pub fn line27(&mut self) -> LINE27_W<27> { + pub fn line27(&mut self) -> LINE27_W { LINE27_W::new(self) } #[doc = "Bit 28 - Drive of PIO Line 28"] #[inline(always)] #[must_use] - pub fn line28(&mut self) -> LINE28_W<28> { + pub fn line28(&mut self) -> LINE28_W { LINE28_W::new(self) } #[doc = "Bit 29 - Drive of PIO Line 29"] #[inline(always)] #[must_use] - pub fn line29(&mut self) -> LINE29_W<29> { + pub fn line29(&mut self) -> LINE29_W { LINE29_W::new(self) } #[doc = "Bit 30 - Drive of PIO Line 30"] #[inline(always)] #[must_use] - pub fn line30(&mut self) -> LINE30_W<30> { + pub fn line30(&mut self) -> LINE30_W { LINE30_W::new(self) } #[doc = "Bit 31 - Drive of PIO Line 31"] #[inline(always)] #[must_use] - pub fn line31(&mut self) -> LINE31_W<31> { + pub fn line31(&mut self) -> LINE31_W { LINE31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "I/O Drive Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [driver](index.html) module"] +#[doc = "I/O Drive Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`driver::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`driver::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DRIVER_SPEC; impl crate::RegisterSpec for DRIVER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [driver::R](R) reader structure"] -impl crate::Readable for DRIVER_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [driver::W](W) writer structure"] +#[doc = "`read()` method returns [`driver::R`](R) reader structure"] +impl crate::Readable for DRIVER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`driver::W`](W) writer structure"] impl crate::Writable for DRIVER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/elsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/elsr.rs index e6863849..f87db29f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/elsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/elsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ELSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Edge/Level Interrupt Source Selection"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Edge/Level Interrupt Source Selection"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Edge/Level Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [elsr](index.html) module"] +#[doc = "Edge/Level Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`elsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ELSR_SPEC; impl crate::RegisterSpec for ELSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [elsr::R](R) reader structure"] -impl crate::Readable for ELSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`elsr::R`](R) reader structure"] +impl crate::Readable for ELSR_SPEC {} #[doc = "`reset()` method sets ELSR to value 0"] impl crate::Resettable for ELSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/esr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/esr.rs index 22e93d41..dc56edf5 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/esr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/esr.rs @@ -1,296 +1,276 @@ #[doc = "Register `ESR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Edge Interrupt Selection"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Edge Interrupt Selection"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Edge Interrupt Selection"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Edge Interrupt Selection"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Edge Interrupt Selection"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Edge Interrupt Selection"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Edge Interrupt Selection"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Edge Interrupt Selection"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Edge Interrupt Selection"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Edge Interrupt Selection"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Edge Interrupt Selection"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Edge Interrupt Selection"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Edge Interrupt Selection"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Edge Interrupt Selection"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Edge Interrupt Selection"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Edge Interrupt Selection"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Edge Interrupt Selection"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Edge Interrupt Selection"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Edge Interrupt Selection"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Edge Interrupt Selection"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Edge Interrupt Selection"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Edge Interrupt Selection"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Edge Interrupt Selection"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Edge Interrupt Selection"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Edge Interrupt Selection"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Edge Interrupt Selection"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Edge Interrupt Selection"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Edge Interrupt Selection"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Edge Interrupt Selection"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Edge Interrupt Selection"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Edge Interrupt Selection"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Edge Interrupt Selection"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, ESR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Edge Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Edge Select Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [esr](index.html) module"] +#[doc = "Edge Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`esr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ESR_SPEC; impl crate::RegisterSpec for ESR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [esr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`esr::W`](W) writer structure"] impl crate::Writable for ESR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/fellsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/fellsr.rs index ca6098fa..f9da37b3 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/fellsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/fellsr.rs @@ -1,296 +1,276 @@ #[doc = "Register `FELLSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Falling Edge/Low-Level Interrupt Selection"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, FELLSR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Falling Edge/Low-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Falling Edge/Low-Level Select Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fellsr](index.html) module"] +#[doc = "Falling Edge/Low-Level Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fellsr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FELLSR_SPEC; impl crate::RegisterSpec for FELLSR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [fellsr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`fellsr::W`](W) writer structure"] impl crate::Writable for FELLSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/frlhsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/frlhsr.rs index 3aa82254..eaff51e2 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/frlhsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/frlhsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `FRLHSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Edge/Level Interrupt Source Selection"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Edge/Level Interrupt Source Selection"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Fall/Rise - Low/High Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [frlhsr](index.html) module"] +#[doc = "Fall/Rise - Low/High Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frlhsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FRLHSR_SPEC; impl crate::RegisterSpec for FRLHSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [frlhsr::R](R) reader structure"] -impl crate::Readable for FRLHSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`frlhsr::R`](R) reader structure"] +impl crate::Readable for FRLHSR_SPEC {} #[doc = "`reset()` method sets FRLHSR to value 0"] impl crate::Resettable for FRLHSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/idr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/idr.rs index 1c5f4d0b..485db9ce 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/idr.rs @@ -1,296 +1,276 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Input Change Interrupt Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Input Change Interrupt Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Input Change Interrupt Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Input Change Interrupt Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Input Change Interrupt Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Input Change Interrupt Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Input Change Interrupt Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Input Change Interrupt Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Input Change Interrupt Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Input Change Interrupt Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Input Change Interrupt Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Input Change Interrupt Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Input Change Interrupt Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Input Change Interrupt Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Input Change Interrupt Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Input Change Interrupt Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Input Change Interrupt Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Input Change Interrupt Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Input Change Interrupt Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Input Change Interrupt Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Input Change Interrupt Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Input Change Interrupt Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Input Change Interrupt Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Input Change Interrupt Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Input Change Interrupt Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Input Change Interrupt Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Input Change Interrupt Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Input Change Interrupt Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Input Change Interrupt Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Input Change Interrupt Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Input Change Interrupt Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Input Change Interrupt Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ier.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ier.rs index ada6cbaa..8894e4ea 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ier.rs @@ -1,296 +1,276 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Input Change Interrupt Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Input Change Interrupt Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Input Change Interrupt Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Input Change Interrupt Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Input Change Interrupt Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Input Change Interrupt Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Input Change Interrupt Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Input Change Interrupt Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Input Change Interrupt Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Input Change Interrupt Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Input Change Interrupt Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Input Change Interrupt Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Input Change Interrupt Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Input Change Interrupt Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Input Change Interrupt Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Input Change Interrupt Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Input Change Interrupt Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Input Change Interrupt Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Input Change Interrupt Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Input Change Interrupt Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Input Change Interrupt Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Input Change Interrupt Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Input Change Interrupt Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Input Change Interrupt Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Input Change Interrupt Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Input Change Interrupt Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Input Change Interrupt Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Input Change Interrupt Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Input Change Interrupt Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Input Change Interrupt Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Input Change Interrupt Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Input Change Interrupt Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ifdr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ifdr.rs index 7d70e212..89d41634 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ifdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ifdr.rs @@ -1,296 +1,276 @@ #[doc = "Register `IFDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Input Filter Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Input Filter Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Input Filter Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Input Filter Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Input Filter Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Input Filter Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Input Filter Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Input Filter Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Input Filter Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Input Filter Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Input Filter Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Input Filter Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Input Filter Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Input Filter Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Input Filter Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Input Filter Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Input Filter Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Input Filter Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Input Filter Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Input Filter Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Input Filter Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Input Filter Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Input Filter Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Input Filter Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Input Filter Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Input Filter Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Input Filter Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Input Filter Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Input Filter Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Input Filter Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Input Filter Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Input Filter Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, IFDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Input Filter Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Glitch Input Filter Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifdr](index.html) module"] +#[doc = "Glitch Input Filter Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFDR_SPEC; impl crate::RegisterSpec for IFDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ifdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ifdr::W`](W) writer structure"] impl crate::Writable for IFDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ifer.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ifer.rs index b92115a1..758a4327 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ifer.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ifer.rs @@ -1,296 +1,276 @@ #[doc = "Register `IFER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Input Filter Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Input Filter Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Input Filter Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Input Filter Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Input Filter Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Input Filter Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Input Filter Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Input Filter Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Input Filter Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Input Filter Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Input Filter Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Input Filter Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Input Filter Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Input Filter Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Input Filter Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Input Filter Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Input Filter Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Input Filter Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Input Filter Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Input Filter Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Input Filter Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Input Filter Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Input Filter Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Input Filter Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Input Filter Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Input Filter Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Input Filter Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Input Filter Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Input Filter Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Input Filter Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Input Filter Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Input Filter Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, IFER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Input Filter Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Glitch Input Filter Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifer](index.html) module"] +#[doc = "Glitch Input Filter Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifer::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFER_SPEC; impl crate::RegisterSpec for IFER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ifer::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ifer::W`](W) writer structure"] impl crate::Writable for IFER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ifscdr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ifscdr.rs index 24b69c84..7d3ffd33 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ifscdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ifscdr.rs @@ -1,296 +1,276 @@ #[doc = "Register `IFSCDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Peripheral Clock Glitch Filtering Select"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Peripheral Clock Glitch Filtering Select"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Peripheral Clock Glitch Filtering Select"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Peripheral Clock Glitch Filtering Select"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Peripheral Clock Glitch Filtering Select"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Peripheral Clock Glitch Filtering Select"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Peripheral Clock Glitch Filtering Select"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Peripheral Clock Glitch Filtering Select"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Peripheral Clock Glitch Filtering Select"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Peripheral Clock Glitch Filtering Select"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Peripheral Clock Glitch Filtering Select"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Peripheral Clock Glitch Filtering Select"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Peripheral Clock Glitch Filtering Select"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Peripheral Clock Glitch Filtering Select"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Peripheral Clock Glitch Filtering Select"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Peripheral Clock Glitch Filtering Select"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Peripheral Clock Glitch Filtering Select"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Peripheral Clock Glitch Filtering Select"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Peripheral Clock Glitch Filtering Select"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Peripheral Clock Glitch Filtering Select"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Peripheral Clock Glitch Filtering Select"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Peripheral Clock Glitch Filtering Select"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Peripheral Clock Glitch Filtering Select"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Peripheral Clock Glitch Filtering Select"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Peripheral Clock Glitch Filtering Select"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Peripheral Clock Glitch Filtering Select"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Peripheral Clock Glitch Filtering Select"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Peripheral Clock Glitch Filtering Select"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Peripheral Clock Glitch Filtering Select"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Peripheral Clock Glitch Filtering Select"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Peripheral Clock Glitch Filtering Select"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Peripheral Clock Glitch Filtering Select"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, IFSCDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Peripheral Clock Glitch Filtering Select"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Input Filter Slow Clock Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifscdr](index.html) module"] +#[doc = "Input Filter Slow Clock Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifscdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFSCDR_SPEC; impl crate::RegisterSpec for IFSCDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ifscdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ifscdr::W`](W) writer structure"] impl crate::Writable for IFSCDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ifscer.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ifscer.rs index f4d7dab4..0dd1f729 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ifscer.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ifscer.rs @@ -1,296 +1,276 @@ #[doc = "Register `IFSCER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Slow Clock Debouncing Filtering Select"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Slow Clock Debouncing Filtering Select"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Slow Clock Debouncing Filtering Select"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Slow Clock Debouncing Filtering Select"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Slow Clock Debouncing Filtering Select"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Slow Clock Debouncing Filtering Select"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Slow Clock Debouncing Filtering Select"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Slow Clock Debouncing Filtering Select"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Slow Clock Debouncing Filtering Select"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Slow Clock Debouncing Filtering Select"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Slow Clock Debouncing Filtering Select"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Slow Clock Debouncing Filtering Select"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Slow Clock Debouncing Filtering Select"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Slow Clock Debouncing Filtering Select"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Slow Clock Debouncing Filtering Select"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Slow Clock Debouncing Filtering Select"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Slow Clock Debouncing Filtering Select"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Slow Clock Debouncing Filtering Select"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Slow Clock Debouncing Filtering Select"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Slow Clock Debouncing Filtering Select"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Slow Clock Debouncing Filtering Select"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Slow Clock Debouncing Filtering Select"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Slow Clock Debouncing Filtering Select"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Slow Clock Debouncing Filtering Select"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Slow Clock Debouncing Filtering Select"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Slow Clock Debouncing Filtering Select"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Slow Clock Debouncing Filtering Select"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Slow Clock Debouncing Filtering Select"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Slow Clock Debouncing Filtering Select"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Slow Clock Debouncing Filtering Select"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Slow Clock Debouncing Filtering Select"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Slow Clock Debouncing Filtering Select"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, IFSCER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Slow Clock Debouncing Filtering Select"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Input Filter Slow Clock Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifscer](index.html) module"] +#[doc = "Input Filter Slow Clock Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifscer::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFSCER_SPEC; impl crate::RegisterSpec for IFSCER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ifscer::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ifscer::W`](W) writer structure"] impl crate::Writable for IFSCER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ifscsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ifscsr.rs index cc59c760..336340c7 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ifscsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ifscsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IFSCSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Glitch or Debouncing Filter Selection Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Glitch or Debouncing Filter Selection Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Input Filter Slow Clock Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifscsr](index.html) module"] +#[doc = "Input Filter Slow Clock Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifscsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFSCSR_SPEC; impl crate::RegisterSpec for IFSCSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ifscsr::R](R) reader structure"] -impl crate::Readable for IFSCSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ifscsr::R`](R) reader structure"] +impl crate::Readable for IFSCSR_SPEC {} #[doc = "`reset()` method sets IFSCSR to value 0"] impl crate::Resettable for IFSCSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ifsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ifsr.rs index ac34d283..20caf4da 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ifsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ifsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IFSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Input Filter Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Input Filter Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Glitch Input Filter Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifsr](index.html) module"] +#[doc = "Glitch Input Filter Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFSR_SPEC; impl crate::RegisterSpec for IFSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ifsr::R](R) reader structure"] -impl crate::Readable for IFSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ifsr::R`](R) reader structure"] +impl crate::Readable for IFSR_SPEC {} #[doc = "`reset()` method sets IFSR to value 0"] impl crate::Resettable for IFSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/imr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/imr.rs index 9e2f17ee..ca61decf 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Input Change Interrupt Mask"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Input Change Interrupt Mask"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/isr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/isr.rs index a3de43b4..41c0dc45 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Input Change Interrupt Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Input Change Interrupt Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/locksr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/locksr.rs index e07aa88d..55432af6 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/locksr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/locksr.rs @@ -1,18 +1,5 @@ #[doc = "Register `LOCKSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Lock Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Lock Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [locksr](index.html) module"] +#[doc = "Lock Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`locksr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LOCKSR_SPEC; impl crate::RegisterSpec for LOCKSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [locksr::R](R) reader structure"] -impl crate::Readable for LOCKSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`locksr::R`](R) reader structure"] +impl crate::Readable for LOCKSR_SPEC {} #[doc = "`reset()` method sets LOCKSR to value 0"] impl crate::Resettable for LOCKSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/lsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/lsr.rs index d93a6ce8..7d8c01e3 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/lsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/lsr.rs @@ -1,296 +1,276 @@ #[doc = "Register `LSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Level Interrupt Selection"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Level Interrupt Selection"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Level Interrupt Selection"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Level Interrupt Selection"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Level Interrupt Selection"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Level Interrupt Selection"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Level Interrupt Selection"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Level Interrupt Selection"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Level Interrupt Selection"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Level Interrupt Selection"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Level Interrupt Selection"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Level Interrupt Selection"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Level Interrupt Selection"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Level Interrupt Selection"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Level Interrupt Selection"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Level Interrupt Selection"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Level Interrupt Selection"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Level Interrupt Selection"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Level Interrupt Selection"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Level Interrupt Selection"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Level Interrupt Selection"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Level Interrupt Selection"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Level Interrupt Selection"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Level Interrupt Selection"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Level Interrupt Selection"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Level Interrupt Selection"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Level Interrupt Selection"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Level Interrupt Selection"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Level Interrupt Selection"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Level Interrupt Selection"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Level Interrupt Selection"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Level Interrupt Selection"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, LSR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Level Select Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lsr](index.html) module"] +#[doc = "Level Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LSR_SPEC; impl crate::RegisterSpec for LSR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [lsr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`lsr::W`](W) writer structure"] impl crate::Writable for LSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/mddr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/mddr.rs index 770ae40d..76baecb6 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/mddr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/mddr.rs @@ -1,296 +1,276 @@ #[doc = "Register `MDDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Multi-drive Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Multi-drive Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Multi-drive Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Multi-drive Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Multi-drive Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Multi-drive Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Multi-drive Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Multi-drive Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Multi-drive Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Multi-drive Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Multi-drive Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Multi-drive Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Multi-drive Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Multi-drive Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Multi-drive Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Multi-drive Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Multi-drive Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Multi-drive Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Multi-drive Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Multi-drive Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Multi-drive Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Multi-drive Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Multi-drive Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Multi-drive Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Multi-drive Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Multi-drive Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Multi-drive Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Multi-drive Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Multi-drive Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Multi-drive Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Multi-drive Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Multi-drive Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, MDDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Multi-drive Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Multi-driver Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mddr](index.html) module"] +#[doc = "Multi-driver Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mddr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MDDR_SPEC; impl crate::RegisterSpec for MDDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [mddr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`mddr::W`](W) writer structure"] impl crate::Writable for MDDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/mder.rs b/arch/cortex-m/samv71q21-pac/src/pioa/mder.rs index b94f4dc7..2617aad8 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/mder.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/mder.rs @@ -1,296 +1,276 @@ #[doc = "Register `MDER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Multi-drive Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Multi-drive Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Multi-drive Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Multi-drive Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Multi-drive Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Multi-drive Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Multi-drive Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Multi-drive Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Multi-drive Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Multi-drive Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Multi-drive Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Multi-drive Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Multi-drive Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Multi-drive Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Multi-drive Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Multi-drive Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Multi-drive Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Multi-drive Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Multi-drive Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Multi-drive Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Multi-drive Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Multi-drive Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Multi-drive Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Multi-drive Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Multi-drive Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Multi-drive Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Multi-drive Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Multi-drive Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Multi-drive Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Multi-drive Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Multi-drive Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Multi-drive Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, MDER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Multi-drive Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Multi-driver Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mder](index.html) module"] +#[doc = "Multi-driver Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mder::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MDER_SPEC; impl crate::RegisterSpec for MDER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [mder::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`mder::W`](W) writer structure"] impl crate::Writable for MDER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/mdsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/mdsr.rs index c0800df7..0228c4f9 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/mdsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/mdsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `MDSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Multi-drive Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Multi-drive Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Multi-driver Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mdsr](index.html) module"] +#[doc = "Multi-driver Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mdsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MDSR_SPEC; impl crate::RegisterSpec for MDSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mdsr::R](R) reader structure"] -impl crate::Readable for MDSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`mdsr::R`](R) reader structure"] +impl crate::Readable for MDSR_SPEC {} #[doc = "`reset()` method sets MDSR to value 0"] impl crate::Resettable for MDSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/odr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/odr.rs index 68a65e2c..5812da80 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/odr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/odr.rs @@ -1,296 +1,276 @@ #[doc = "Register `ODR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Output Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Output Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Output Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Output Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Output Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Output Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Output Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Output Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Output Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Output Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Output Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Output Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Output Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Output Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Output Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Output Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Output Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Output Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Output Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Output Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Output Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Output Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Output Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Output Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Output Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Output Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Output Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Output Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Output Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Output Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Output Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Output Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, ODR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Output Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Output Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Output Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Output Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Output Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Output Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Output Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Output Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Output Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Output Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Output Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Output Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Output Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Output Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Output Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Output Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Output Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Output Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Output Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Output Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Output Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Output Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Output Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Output Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Output Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Output Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Output Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Output Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Output Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Output Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Output Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Output Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odr](index.html) module"] +#[doc = "Output Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ODR_SPEC; impl crate::RegisterSpec for ODR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [odr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`odr::W`](W) writer structure"] impl crate::Writable for ODR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/odsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/odsr.rs index 499da476..584ae8fe 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/odsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/odsr.rs @@ -1,167 +1,135 @@ #[doc = "Register `ODSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ODSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` reader - Output Data Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P0` writer - Output Data Status"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` reader - Output Data Status"] pub type P1_R = crate::BitReader; #[doc = "Field `P1` writer - Output Data Status"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` reader - Output Data Status"] pub type P2_R = crate::BitReader; #[doc = "Field `P2` writer - Output Data Status"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` reader - Output Data Status"] pub type P3_R = crate::BitReader; #[doc = "Field `P3` writer - Output Data Status"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` reader - Output Data Status"] pub type P4_R = crate::BitReader; #[doc = "Field `P4` writer - Output Data Status"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` reader - Output Data Status"] pub type P5_R = crate::BitReader; #[doc = "Field `P5` writer - Output Data Status"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` reader - Output Data Status"] pub type P6_R = crate::BitReader; #[doc = "Field `P6` writer - Output Data Status"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` reader - Output Data Status"] pub type P7_R = crate::BitReader; #[doc = "Field `P7` writer - Output Data Status"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` reader - Output Data Status"] pub type P8_R = crate::BitReader; #[doc = "Field `P8` writer - Output Data Status"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` reader - Output Data Status"] pub type P9_R = crate::BitReader; #[doc = "Field `P9` writer - Output Data Status"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` reader - Output Data Status"] pub type P10_R = crate::BitReader; #[doc = "Field `P10` writer - Output Data Status"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` reader - Output Data Status"] pub type P11_R = crate::BitReader; #[doc = "Field `P11` writer - Output Data Status"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` reader - Output Data Status"] pub type P12_R = crate::BitReader; #[doc = "Field `P12` writer - Output Data Status"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` reader - Output Data Status"] pub type P13_R = crate::BitReader; #[doc = "Field `P13` writer - Output Data Status"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` reader - Output Data Status"] pub type P14_R = crate::BitReader; #[doc = "Field `P14` writer - Output Data Status"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` reader - Output Data Status"] pub type P15_R = crate::BitReader; #[doc = "Field `P15` writer - Output Data Status"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` reader - Output Data Status"] pub type P16_R = crate::BitReader; #[doc = "Field `P16` writer - Output Data Status"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` reader - Output Data Status"] pub type P17_R = crate::BitReader; #[doc = "Field `P17` writer - Output Data Status"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` reader - Output Data Status"] pub type P18_R = crate::BitReader; #[doc = "Field `P18` writer - Output Data Status"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` reader - Output Data Status"] pub type P19_R = crate::BitReader; #[doc = "Field `P19` writer - Output Data Status"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` reader - Output Data Status"] pub type P20_R = crate::BitReader; #[doc = "Field `P20` writer - Output Data Status"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` reader - Output Data Status"] pub type P21_R = crate::BitReader; #[doc = "Field `P21` writer - Output Data Status"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` reader - Output Data Status"] pub type P22_R = crate::BitReader; #[doc = "Field `P22` writer - Output Data Status"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` reader - Output Data Status"] pub type P23_R = crate::BitReader; #[doc = "Field `P23` writer - Output Data Status"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` reader - Output Data Status"] pub type P24_R = crate::BitReader; #[doc = "Field `P24` writer - Output Data Status"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` reader - Output Data Status"] pub type P25_R = crate::BitReader; #[doc = "Field `P25` writer - Output Data Status"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` reader - Output Data Status"] pub type P26_R = crate::BitReader; #[doc = "Field `P26` writer - Output Data Status"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` reader - Output Data Status"] pub type P27_R = crate::BitReader; #[doc = "Field `P27` writer - Output Data Status"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` reader - Output Data Status"] pub type P28_R = crate::BitReader; #[doc = "Field `P28` writer - Output Data Status"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` reader - Output Data Status"] pub type P29_R = crate::BitReader; #[doc = "Field `P29` writer - Output Data Status"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` reader - Output Data Status"] pub type P30_R = crate::BitReader; #[doc = "Field `P30` writer - Output Data Status"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` reader - Output Data Status"] pub type P31_R = crate::BitReader; #[doc = "Field `P31` writer - Output Data Status"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, ODSR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Output Data Status"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Output Data Status"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Output Data Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odsr](index.html) module"] +#[doc = "Output Data Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odsr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ODSR_SPEC; impl crate::RegisterSpec for ODSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [odsr::R](R) reader structure"] -impl crate::Readable for ODSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [odsr::W](W) writer structure"] +#[doc = "`read()` method returns [`odsr::R`](R) reader structure"] +impl crate::Readable for ODSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`odsr::W`](W) writer structure"] impl crate::Writable for ODSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/oer.rs b/arch/cortex-m/samv71q21-pac/src/pioa/oer.rs index 29f222ee..91dff200 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/oer.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/oer.rs @@ -1,296 +1,276 @@ #[doc = "Register `OER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Output Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Output Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Output Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Output Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Output Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Output Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Output Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Output Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Output Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Output Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Output Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Output Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Output Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Output Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Output Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Output Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Output Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Output Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Output Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Output Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Output Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Output Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Output Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Output Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Output Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Output Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Output Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Output Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Output Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Output Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Output Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Output Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, OER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Output Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Output Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Output Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Output Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Output Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Output Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Output Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Output Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Output Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Output Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Output Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Output Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Output Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Output Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Output Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Output Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Output Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Output Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Output Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Output Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Output Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Output Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Output Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Output Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Output Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Output Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Output Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Output Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Output Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Output Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Output Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Output Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oer](index.html) module"] +#[doc = "Output Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oer::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OER_SPEC; impl crate::RegisterSpec for OER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [oer::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`oer::W`](W) writer structure"] impl crate::Writable for OER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/osr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/osr.rs index 8b5e7440..5b99d6ff 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/osr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/osr.rs @@ -1,18 +1,5 @@ #[doc = "Register `OSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Output Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Output Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Output Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osr](index.html) module"] +#[doc = "Output Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`osr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OSR_SPEC; impl crate::RegisterSpec for OSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [osr::R](R) reader structure"] -impl crate::Readable for OSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`osr::R`](R) reader structure"] +impl crate::Readable for OSR_SPEC {} #[doc = "`reset()` method sets OSR to value 0"] impl crate::Resettable for OSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/owdr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/owdr.rs index 9e19580a..d3599022 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/owdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/owdr.rs @@ -1,296 +1,276 @@ #[doc = "Register `OWDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Output Write Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Output Write Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Output Write Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Output Write Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Output Write Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Output Write Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Output Write Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Output Write Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Output Write Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Output Write Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Output Write Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Output Write Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Output Write Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Output Write Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Output Write Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Output Write Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Output Write Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Output Write Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Output Write Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Output Write Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Output Write Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Output Write Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Output Write Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Output Write Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Output Write Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Output Write Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Output Write Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Output Write Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Output Write Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Output Write Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Output Write Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Output Write Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, OWDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Output Write Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Output Write Disable\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [owdr](index.html) module"] +#[doc = "Output Write Disable\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`owdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OWDR_SPEC; impl crate::RegisterSpec for OWDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [owdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`owdr::W`](W) writer structure"] impl crate::Writable for OWDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ower.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ower.rs index 215d1034..1ea0e9f0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ower.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ower.rs @@ -1,296 +1,276 @@ #[doc = "Register `OWER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Output Write Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Output Write Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Output Write Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Output Write Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Output Write Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Output Write Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Output Write Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Output Write Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Output Write Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Output Write Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Output Write Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Output Write Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Output Write Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Output Write Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Output Write Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Output Write Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Output Write Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Output Write Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Output Write Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Output Write Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Output Write Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Output Write Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Output Write Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Output Write Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Output Write Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Output Write Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Output Write Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Output Write Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Output Write Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Output Write Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Output Write Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Output Write Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, OWER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Output Write Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Output Write Enable\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ower](index.html) module"] +#[doc = "Output Write Enable\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ower::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OWER_SPEC; impl crate::RegisterSpec for OWER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ower::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ower::W`](W) writer structure"] impl crate::Writable for OWER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/owsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/owsr.rs index be743a5b..100abb3e 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/owsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/owsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `OWSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Output Write Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Output Write Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Output Write Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [owsr](index.html) module"] +#[doc = "Output Write Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`owsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OWSR_SPEC; impl crate::RegisterSpec for OWSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [owsr::R](R) reader structure"] -impl crate::Readable for OWSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`owsr::R`](R) reader structure"] +impl crate::Readable for OWSR_SPEC {} #[doc = "`reset()` method sets OWSR to value 0"] impl crate::Resettable for OWSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pcidr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pcidr.rs index 19fee78e..8fa60ad9 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pcidr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pcidr.rs @@ -1,72 +1,52 @@ #[doc = "Register `PCIDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DRDY` writer - Parallel Capture Mode Data Ready Interrupt Disable"] -pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, PCIDR_SPEC, O>; +pub type DRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Parallel Capture Mode Overrun Error Interrupt Disable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, PCIDR_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDRX` writer - End of Reception Transfer Interrupt Disable"] -pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, PCIDR_SPEC, O>; +pub type ENDRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBUFF` writer - Reception Buffer Full Interrupt Disable"] -pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, PCIDR_SPEC, O>; +pub type RXBUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Parallel Capture Mode Data Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn drdy(&mut self) -> DRDY_W<0> { + pub fn drdy(&mut self) -> DRDY_W { DRDY_W::new(self) } #[doc = "Bit 1 - Parallel Capture Mode Overrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<1> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 2 - End of Reception Transfer Interrupt Disable"] #[inline(always)] #[must_use] - pub fn endrx(&mut self) -> ENDRX_W<2> { + pub fn endrx(&mut self) -> ENDRX_W { ENDRX_W::new(self) } #[doc = "Bit 3 - Reception Buffer Full Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxbuff(&mut self) -> RXBUFF_W<3> { + pub fn rxbuff(&mut self) -> RXBUFF_W { RXBUFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Parallel Capture Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcidr](index.html) module"] +#[doc = "Parallel Capture Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcidr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCIDR_SPEC; impl crate::RegisterSpec for PCIDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pcidr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pcidr::W`](W) writer structure"] impl crate::Writable for PCIDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pcier.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pcier.rs index c6df2415..40504014 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pcier.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pcier.rs @@ -1,72 +1,52 @@ #[doc = "Register `PCIER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DRDY` writer - Parallel Capture Mode Data Ready Interrupt Enable"] -pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, PCIER_SPEC, O>; +pub type DRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Parallel Capture Mode Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, PCIER_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENDRX` writer - End of Reception Transfer Interrupt Enable"] -pub type ENDRX_W<'a, const O: u8> = crate::BitWriter<'a, PCIER_SPEC, O>; +pub type ENDRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBUFF` writer - Reception Buffer Full Interrupt Enable"] -pub type RXBUFF_W<'a, const O: u8> = crate::BitWriter<'a, PCIER_SPEC, O>; +pub type RXBUFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Parallel Capture Mode Data Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn drdy(&mut self) -> DRDY_W<0> { + pub fn drdy(&mut self) -> DRDY_W { DRDY_W::new(self) } #[doc = "Bit 1 - Parallel Capture Mode Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<1> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 2 - End of Reception Transfer Interrupt Enable"] #[inline(always)] #[must_use] - pub fn endrx(&mut self) -> ENDRX_W<2> { + pub fn endrx(&mut self) -> ENDRX_W { ENDRX_W::new(self) } #[doc = "Bit 3 - Reception Buffer Full Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxbuff(&mut self) -> RXBUFF_W<3> { + pub fn rxbuff(&mut self) -> RXBUFF_W { RXBUFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Parallel Capture Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcier](index.html) module"] +#[doc = "Parallel Capture Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCIER_SPEC; impl crate::RegisterSpec for PCIER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pcier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pcier::W`](W) writer structure"] impl crate::Writable for PCIER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pcimr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pcimr.rs index fc3be246..a3781d48 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pcimr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pcimr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PCIMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DRDY` reader - Parallel Capture Mode Data Ready Interrupt Mask"] pub type DRDY_R = crate::BitReader; #[doc = "Field `OVRE` reader - Parallel Capture Mode Overrun Error Interrupt Mask"] @@ -43,15 +30,13 @@ impl R { RXBUFF_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "Parallel Capture Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcimr](index.html) module"] +#[doc = "Parallel Capture Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcimr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCIMR_SPEC; impl crate::RegisterSpec for PCIMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcimr::R](R) reader structure"] -impl crate::Readable for PCIMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pcimr::R`](R) reader structure"] +impl crate::Readable for PCIMR_SPEC {} #[doc = "`reset()` method sets PCIMR to value 0"] impl crate::Resettable for PCIMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pcisr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pcisr.rs index 1b2231b4..0e6268b8 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pcisr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pcisr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PCISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DRDY` reader - Parallel Capture Mode Data Ready"] pub type DRDY_R = crate::BitReader; #[doc = "Field `OVRE` reader - Parallel Capture Mode Overrun Error"] @@ -29,15 +16,13 @@ impl R { OVRE_R::new(((self.bits >> 1) & 1) != 0) } } -#[doc = "Parallel Capture Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcisr](index.html) module"] +#[doc = "Parallel Capture Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCISR_SPEC; impl crate::RegisterSpec for PCISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcisr::R](R) reader structure"] -impl crate::Readable for PCISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pcisr::R`](R) reader structure"] +impl crate::Readable for PCISR_SPEC {} #[doc = "`reset()` method sets PCISR to value 0"] impl crate::Resettable for PCISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pcmr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pcmr.rs index 047b1b2c..d051d34e 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pcmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pcmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `PCMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PCMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PCEN` reader - Parallel Capture Mode Enable"] pub type PCEN_R = crate::BitReader; #[doc = "Field `PCEN` writer - Parallel Capture Mode Enable"] -pub type PCEN_W<'a, const O: u8> = crate::BitWriter<'a, PCMR_SPEC, O>; +pub type PCEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSIZE` reader - Parallel Capture Mode Data Size"] pub type DSIZE_R = crate::FieldReader; #[doc = "Parallel Capture Mode Data Size\n\nValue on reset: 0"] @@ -71,53 +39,57 @@ impl DSIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `BYTE`"] + #[doc = "The reception data in the PIO_PCRHR is a byte (8-bit)"] #[inline(always)] pub fn is_byte(&self) -> bool { *self == DSIZESELECT_A::BYTE } - #[doc = "Checks if the value of the field is `HALFWORD`"] + #[doc = "The reception data in the PIO_PCRHR is a half-word (16-bit)"] #[inline(always)] pub fn is_halfword(&self) -> bool { *self == DSIZESELECT_A::HALFWORD } - #[doc = "Checks if the value of the field is `WORD`"] + #[doc = "The reception data in the PIO_PCRHR is a word (32-bit)"] #[inline(always)] pub fn is_word(&self) -> bool { *self == DSIZESELECT_A::WORD } } #[doc = "Field `DSIZE` writer - Parallel Capture Mode Data Size"] -pub type DSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, PCMR_SPEC, 2, O, DSIZESELECT_A>; -impl<'a, const O: u8> DSIZE_W<'a, O> { +pub type DSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, DSIZESELECT_A>; +impl<'a, REG, const O: u8> DSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The reception data in the PIO_PCRHR is a byte (8-bit)"] #[inline(always)] - pub fn byte(self) -> &'a mut W { + pub fn byte(self) -> &'a mut crate::W { self.variant(DSIZESELECT_A::BYTE) } #[doc = "The reception data in the PIO_PCRHR is a half-word (16-bit)"] #[inline(always)] - pub fn halfword(self) -> &'a mut W { + pub fn halfword(self) -> &'a mut crate::W { self.variant(DSIZESELECT_A::HALFWORD) } #[doc = "The reception data in the PIO_PCRHR is a word (32-bit)"] #[inline(always)] - pub fn word(self) -> &'a mut W { + pub fn word(self) -> &'a mut crate::W { self.variant(DSIZESELECT_A::WORD) } } #[doc = "Field `ALWYS` reader - Parallel Capture Mode Always Sampling"] pub type ALWYS_R = crate::BitReader; #[doc = "Field `ALWYS` writer - Parallel Capture Mode Always Sampling"] -pub type ALWYS_W<'a, const O: u8> = crate::BitWriter<'a, PCMR_SPEC, O>; +pub type ALWYS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HALFS` reader - Parallel Capture Mode Half Sampling"] pub type HALFS_R = crate::BitReader; #[doc = "Field `HALFS` writer - Parallel Capture Mode Half Sampling"] -pub type HALFS_W<'a, const O: u8> = crate::BitWriter<'a, PCMR_SPEC, O>; +pub type HALFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRSTS` reader - Parallel Capture Mode First Sample"] pub type FRSTS_R = crate::BitReader; #[doc = "Field `FRSTS` writer - Parallel Capture Mode First Sample"] -pub type FRSTS_W<'a, const O: u8> = crate::BitWriter<'a, PCMR_SPEC, O>; +pub type FRSTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Parallel Capture Mode Enable"] #[inline(always)] @@ -149,52 +121,49 @@ impl W { #[doc = "Bit 0 - Parallel Capture Mode Enable"] #[inline(always)] #[must_use] - pub fn pcen(&mut self) -> PCEN_W<0> { + pub fn pcen(&mut self) -> PCEN_W { PCEN_W::new(self) } #[doc = "Bits 4:5 - Parallel Capture Mode Data Size"] #[inline(always)] #[must_use] - pub fn dsize(&mut self) -> DSIZE_W<4> { + pub fn dsize(&mut self) -> DSIZE_W { DSIZE_W::new(self) } #[doc = "Bit 9 - Parallel Capture Mode Always Sampling"] #[inline(always)] #[must_use] - pub fn alwys(&mut self) -> ALWYS_W<9> { + pub fn alwys(&mut self) -> ALWYS_W { ALWYS_W::new(self) } #[doc = "Bit 10 - Parallel Capture Mode Half Sampling"] #[inline(always)] #[must_use] - pub fn halfs(&mut self) -> HALFS_W<10> { + pub fn halfs(&mut self) -> HALFS_W { HALFS_W::new(self) } #[doc = "Bit 11 - Parallel Capture Mode First Sample"] #[inline(always)] #[must_use] - pub fn frsts(&mut self) -> FRSTS_W<11> { + pub fn frsts(&mut self) -> FRSTS_W { FRSTS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Parallel Capture Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcmr](index.html) module"] +#[doc = "Parallel Capture Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCMR_SPEC; impl crate::RegisterSpec for PCMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcmr::R](R) reader structure"] -impl crate::Readable for PCMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pcmr::W](W) writer structure"] +#[doc = "`read()` method returns [`pcmr::R`](R) reader structure"] +impl crate::Readable for PCMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcmr::W`](W) writer structure"] impl crate::Writable for PCMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pcrhr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pcrhr.rs index 6e1e46b0..4cfa825a 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pcrhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pcrhr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PCRHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDATA` reader - Parallel Capture Mode Reception Data"] pub type RDATA_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RDATA_R::new(self.bits) } } -#[doc = "Parallel Capture Reception Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcrhr](index.html) module"] +#[doc = "Parallel Capture Reception Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcrhr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCRHR_SPEC; impl crate::RegisterSpec for PCRHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcrhr::R](R) reader structure"] -impl crate::Readable for PCRHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pcrhr::R`](R) reader structure"] +impl crate::Readable for PCRHR_SPEC {} #[doc = "`reset()` method sets PCRHR to value 0"] impl crate::Resettable for PCRHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pdr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pdr.rs index db4bc33d..55d1599b 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pdr.rs @@ -1,296 +1,276 @@ #[doc = "Register `PDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - PIO Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - PIO Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - PIO Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - PIO Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - PIO Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - PIO Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - PIO Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - PIO Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - PIO Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - PIO Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - PIO Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - PIO Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - PIO Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - PIO Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - PIO Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - PIO Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - PIO Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - PIO Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - PIO Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - PIO Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - PIO Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - PIO Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - PIO Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - PIO Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - PIO Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - PIO Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - PIO Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - PIO Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - PIO Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - PIO Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - PIO Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - PIO Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, PDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - PIO Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PIO Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdr](index.html) module"] +#[doc = "PIO Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDR_SPEC; impl crate::RegisterSpec for PDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pdr::W`](W) writer structure"] impl crate::Writable for PDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pdsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pdsr.rs index eb690299..317607ac 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pdsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pdsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PDSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Output Data Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Output Data Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pin Data Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdsr](index.html) module"] +#[doc = "Pin Data Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PDSR_SPEC; impl crate::RegisterSpec for PDSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pdsr::R](R) reader structure"] -impl crate::Readable for PDSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pdsr::R`](R) reader structure"] +impl crate::Readable for PDSR_SPEC {} #[doc = "`reset()` method sets PDSR to value 0"] impl crate::Resettable for PDSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/per.rs b/arch/cortex-m/samv71q21-pac/src/pioa/per.rs index c9b1c23d..54992129 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/per.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/per.rs @@ -1,296 +1,276 @@ #[doc = "Register `PER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - PIO Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - PIO Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - PIO Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - PIO Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - PIO Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - PIO Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - PIO Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - PIO Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - PIO Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - PIO Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - PIO Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - PIO Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - PIO Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - PIO Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - PIO Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - PIO Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - PIO Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - PIO Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - PIO Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - PIO Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - PIO Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - PIO Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - PIO Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - PIO Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - PIO Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - PIO Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - PIO Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - PIO Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - PIO Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - PIO Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - PIO Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - PIO Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, PER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - PIO Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PIO Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +#[doc = "PIO Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`per::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PER_SPEC; impl crate::RegisterSpec for PER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`per::W`](W) writer structure"] impl crate::Writable for PER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ppddr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ppddr.rs index e99a9680..8f70a010 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ppddr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ppddr.rs @@ -1,296 +1,276 @@ #[doc = "Register `PPDDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Pull-Down Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Pull-Down Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Pull-Down Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Pull-Down Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Pull-Down Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Pull-Down Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Pull-Down Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Pull-Down Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Pull-Down Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Pull-Down Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Pull-Down Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Pull-Down Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Pull-Down Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Pull-Down Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Pull-Down Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Pull-Down Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Pull-Down Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Pull-Down Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Pull-Down Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Pull-Down Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Pull-Down Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Pull-Down Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Pull-Down Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Pull-Down Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Pull-Down Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Pull-Down Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Pull-Down Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Pull-Down Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Pull-Down Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Pull-Down Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Pull-Down Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Pull-Down Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, PPDDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Pull-Down Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Pad Pull-down Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppddr](index.html) module"] +#[doc = "Pad Pull-down Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppddr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PPDDR_SPEC; impl crate::RegisterSpec for PPDDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ppddr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ppddr::W`](W) writer structure"] impl crate::Writable for PPDDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ppder.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ppder.rs index 443c7f1a..cda1ff43 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ppder.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ppder.rs @@ -1,296 +1,276 @@ #[doc = "Register `PPDER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Pull-Down Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Pull-Down Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Pull-Down Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Pull-Down Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Pull-Down Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Pull-Down Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Pull-Down Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Pull-Down Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Pull-Down Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Pull-Down Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Pull-Down Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Pull-Down Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Pull-Down Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Pull-Down Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Pull-Down Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Pull-Down Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Pull-Down Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Pull-Down Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Pull-Down Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Pull-Down Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Pull-Down Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Pull-Down Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Pull-Down Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Pull-Down Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Pull-Down Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Pull-Down Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Pull-Down Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Pull-Down Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Pull-Down Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Pull-Down Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Pull-Down Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Pull-Down Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, PPDER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Pull-Down Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Pad Pull-down Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppder](index.html) module"] +#[doc = "Pad Pull-down Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppder::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PPDER_SPEC; impl crate::RegisterSpec for PPDER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ppder::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ppder::W`](W) writer structure"] impl crate::Writable for PPDER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/ppdsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/ppdsr.rs index ce81e624..1b8e0a65 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/ppdsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/ppdsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PPDSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Pull-Down Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Pull-Down Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pad Pull-down Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppdsr](index.html) module"] +#[doc = "Pad Pull-down Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppdsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PPDSR_SPEC; impl crate::RegisterSpec for PPDSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ppdsr::R](R) reader structure"] -impl crate::Readable for PPDSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ppdsr::R`](R) reader structure"] +impl crate::Readable for PPDSR_SPEC {} #[doc = "`reset()` method sets PPDSR to value 0"] impl crate::Resettable for PPDSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/psr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/psr.rs index 0dc2f541..29bfa10d 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/psr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/psr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - PIO Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - PIO Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "PIO Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [psr](index.html) module"] +#[doc = "PIO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PSR_SPEC; impl crate::RegisterSpec for PSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [psr::R](R) reader structure"] -impl crate::Readable for PSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`psr::R`](R) reader structure"] +impl crate::Readable for PSR_SPEC {} #[doc = "`reset()` method sets PSR to value 0"] impl crate::Resettable for PSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pudr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pudr.rs index 63c668bf..5ab90e9f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pudr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pudr.rs @@ -1,296 +1,276 @@ #[doc = "Register `PUDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Pull-Up Disable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Pull-Up Disable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Pull-Up Disable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Pull-Up Disable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Pull-Up Disable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Pull-Up Disable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Pull-Up Disable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Pull-Up Disable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Pull-Up Disable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Pull-Up Disable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Pull-Up Disable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Pull-Up Disable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Pull-Up Disable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Pull-Up Disable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Pull-Up Disable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Pull-Up Disable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Pull-Up Disable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Pull-Up Disable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Pull-Up Disable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Pull-Up Disable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Pull-Up Disable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Pull-Up Disable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Pull-Up Disable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Pull-Up Disable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Pull-Up Disable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Pull-Up Disable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Pull-Up Disable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Pull-Up Disable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Pull-Up Disable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Pull-Up Disable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Pull-Up Disable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Pull-Up Disable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, PUDR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Pull-Up Disable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Pull-up Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pudr](index.html) module"] +#[doc = "Pull-up Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pudr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PUDR_SPEC; impl crate::RegisterSpec for PUDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pudr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pudr::W`](W) writer structure"] impl crate::Writable for PUDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/puer.rs b/arch/cortex-m/samv71q21-pac/src/pioa/puer.rs index a1b136ab..27828a57 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/puer.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/puer.rs @@ -1,296 +1,276 @@ #[doc = "Register `PUER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Pull-Up Enable"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Pull-Up Enable"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Pull-Up Enable"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Pull-Up Enable"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Pull-Up Enable"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Pull-Up Enable"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Pull-Up Enable"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Pull-Up Enable"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Pull-Up Enable"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Pull-Up Enable"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Pull-Up Enable"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Pull-Up Enable"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Pull-Up Enable"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Pull-Up Enable"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Pull-Up Enable"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Pull-Up Enable"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Pull-Up Enable"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Pull-Up Enable"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Pull-Up Enable"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Pull-Up Enable"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Pull-Up Enable"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Pull-Up Enable"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Pull-Up Enable"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Pull-Up Enable"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Pull-Up Enable"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Pull-Up Enable"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Pull-Up Enable"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Pull-Up Enable"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Pull-Up Enable"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Pull-Up Enable"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Pull-Up Enable"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Pull-Up Enable"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, PUER_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Pull-Up Enable"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Pull-up Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [puer](index.html) module"] +#[doc = "Pull-up Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`puer::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PUER_SPEC; impl crate::RegisterSpec for PUER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [puer::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`puer::W`](W) writer structure"] impl crate::Writable for PUER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/pusr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/pusr.rs index 517a6db2..ac239454 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/pusr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/pusr.rs @@ -1,18 +1,5 @@ #[doc = "Register `PUSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `P0` reader - Pull-Up Status"] pub type P0_R = crate::BitReader; #[doc = "Field `P1` reader - Pull-Up Status"] @@ -239,15 +226,13 @@ impl R { P31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Pad Pull-up Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pusr](index.html) module"] +#[doc = "Pad Pull-up Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pusr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PUSR_SPEC; impl crate::RegisterSpec for PUSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pusr::R](R) reader structure"] -impl crate::Readable for PUSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pusr::R`](R) reader structure"] +impl crate::Readable for PUSR_SPEC {} #[doc = "`reset()` method sets PUSR to value 0"] impl crate::Resettable for PUSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/rehlsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/rehlsr.rs index 43a89b88..834385d0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/rehlsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/rehlsr.rs @@ -1,296 +1,276 @@ #[doc = "Register `REHLSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Rising Edge/High-Level Interrupt Selection"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, REHLSR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Rising Edge/High-Level Interrupt Selection"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Rising Edge/High-Level Select Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rehlsr](index.html) module"] +#[doc = "Rising Edge/High-Level Select Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rehlsr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct REHLSR_SPEC; impl crate::RegisterSpec for REHLSR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [rehlsr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`rehlsr::W`](W) writer structure"] impl crate::Writable for REHLSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/scdr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/scdr.rs index d3dc972a..ba6cc011 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/scdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/scdr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SCDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIV` reader - Slow Clock Divider Selection for Debouncing"] pub type DIV_R = crate::FieldReader; #[doc = "Field `DIV` writer - Slow Clock Divider Selection for Debouncing"] -pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, SCDR_SPEC, 14, O, u16>; +pub type DIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; impl R { #[doc = "Bits 0:13 - Slow Clock Divider Selection for Debouncing"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:13 - Slow Clock Divider Selection for Debouncing"] #[inline(always)] #[must_use] - pub fn div(&mut self) -> DIV_W<0> { + pub fn div(&mut self) -> DIV_W { DIV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Slow Clock Divider Debouncing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scdr](index.html) module"] +#[doc = "Slow Clock Divider Debouncing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCDR_SPEC; impl crate::RegisterSpec for SCDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scdr::R](R) reader structure"] -impl crate::Readable for SCDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scdr::W](W) writer structure"] +#[doc = "`read()` method returns [`scdr::R`](R) reader structure"] +impl crate::Readable for SCDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scdr::W`](W) writer structure"] impl crate::Writable for SCDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/schmitt.rs b/arch/cortex-m/samv71q21-pac/src/pioa/schmitt.rs index 689a18c9..044c016f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/schmitt.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/schmitt.rs @@ -1,167 +1,135 @@ #[doc = "Register `SCHMITT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCHMITT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SCHMITT0` reader - Schmitt Trigger Control"] pub type SCHMITT0_R = crate::BitReader; #[doc = "Field `SCHMITT0` writer - Schmitt Trigger Control"] -pub type SCHMITT0_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT1` reader - Schmitt Trigger Control"] pub type SCHMITT1_R = crate::BitReader; #[doc = "Field `SCHMITT1` writer - Schmitt Trigger Control"] -pub type SCHMITT1_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT2` reader - Schmitt Trigger Control"] pub type SCHMITT2_R = crate::BitReader; #[doc = "Field `SCHMITT2` writer - Schmitt Trigger Control"] -pub type SCHMITT2_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT3` reader - Schmitt Trigger Control"] pub type SCHMITT3_R = crate::BitReader; #[doc = "Field `SCHMITT3` writer - Schmitt Trigger Control"] -pub type SCHMITT3_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT4` reader - Schmitt Trigger Control"] pub type SCHMITT4_R = crate::BitReader; #[doc = "Field `SCHMITT4` writer - Schmitt Trigger Control"] -pub type SCHMITT4_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT5` reader - Schmitt Trigger Control"] pub type SCHMITT5_R = crate::BitReader; #[doc = "Field `SCHMITT5` writer - Schmitt Trigger Control"] -pub type SCHMITT5_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT6` reader - Schmitt Trigger Control"] pub type SCHMITT6_R = crate::BitReader; #[doc = "Field `SCHMITT6` writer - Schmitt Trigger Control"] -pub type SCHMITT6_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT7` reader - Schmitt Trigger Control"] pub type SCHMITT7_R = crate::BitReader; #[doc = "Field `SCHMITT7` writer - Schmitt Trigger Control"] -pub type SCHMITT7_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT8` reader - Schmitt Trigger Control"] pub type SCHMITT8_R = crate::BitReader; #[doc = "Field `SCHMITT8` writer - Schmitt Trigger Control"] -pub type SCHMITT8_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT9` reader - Schmitt Trigger Control"] pub type SCHMITT9_R = crate::BitReader; #[doc = "Field `SCHMITT9` writer - Schmitt Trigger Control"] -pub type SCHMITT9_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT10` reader - Schmitt Trigger Control"] pub type SCHMITT10_R = crate::BitReader; #[doc = "Field `SCHMITT10` writer - Schmitt Trigger Control"] -pub type SCHMITT10_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT11` reader - Schmitt Trigger Control"] pub type SCHMITT11_R = crate::BitReader; #[doc = "Field `SCHMITT11` writer - Schmitt Trigger Control"] -pub type SCHMITT11_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT12` reader - Schmitt Trigger Control"] pub type SCHMITT12_R = crate::BitReader; #[doc = "Field `SCHMITT12` writer - Schmitt Trigger Control"] -pub type SCHMITT12_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT13` reader - Schmitt Trigger Control"] pub type SCHMITT13_R = crate::BitReader; #[doc = "Field `SCHMITT13` writer - Schmitt Trigger Control"] -pub type SCHMITT13_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT14` reader - Schmitt Trigger Control"] pub type SCHMITT14_R = crate::BitReader; #[doc = "Field `SCHMITT14` writer - Schmitt Trigger Control"] -pub type SCHMITT14_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT15` reader - Schmitt Trigger Control"] pub type SCHMITT15_R = crate::BitReader; #[doc = "Field `SCHMITT15` writer - Schmitt Trigger Control"] -pub type SCHMITT15_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT16` reader - Schmitt Trigger Control"] pub type SCHMITT16_R = crate::BitReader; #[doc = "Field `SCHMITT16` writer - Schmitt Trigger Control"] -pub type SCHMITT16_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT17` reader - Schmitt Trigger Control"] pub type SCHMITT17_R = crate::BitReader; #[doc = "Field `SCHMITT17` writer - Schmitt Trigger Control"] -pub type SCHMITT17_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT18` reader - Schmitt Trigger Control"] pub type SCHMITT18_R = crate::BitReader; #[doc = "Field `SCHMITT18` writer - Schmitt Trigger Control"] -pub type SCHMITT18_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT19` reader - Schmitt Trigger Control"] pub type SCHMITT19_R = crate::BitReader; #[doc = "Field `SCHMITT19` writer - Schmitt Trigger Control"] -pub type SCHMITT19_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT20` reader - Schmitt Trigger Control"] pub type SCHMITT20_R = crate::BitReader; #[doc = "Field `SCHMITT20` writer - Schmitt Trigger Control"] -pub type SCHMITT20_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT21` reader - Schmitt Trigger Control"] pub type SCHMITT21_R = crate::BitReader; #[doc = "Field `SCHMITT21` writer - Schmitt Trigger Control"] -pub type SCHMITT21_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT22` reader - Schmitt Trigger Control"] pub type SCHMITT22_R = crate::BitReader; #[doc = "Field `SCHMITT22` writer - Schmitt Trigger Control"] -pub type SCHMITT22_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT23` reader - Schmitt Trigger Control"] pub type SCHMITT23_R = crate::BitReader; #[doc = "Field `SCHMITT23` writer - Schmitt Trigger Control"] -pub type SCHMITT23_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT24` reader - Schmitt Trigger Control"] pub type SCHMITT24_R = crate::BitReader; #[doc = "Field `SCHMITT24` writer - Schmitt Trigger Control"] -pub type SCHMITT24_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT25` reader - Schmitt Trigger Control"] pub type SCHMITT25_R = crate::BitReader; #[doc = "Field `SCHMITT25` writer - Schmitt Trigger Control"] -pub type SCHMITT25_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT26` reader - Schmitt Trigger Control"] pub type SCHMITT26_R = crate::BitReader; #[doc = "Field `SCHMITT26` writer - Schmitt Trigger Control"] -pub type SCHMITT26_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT27` reader - Schmitt Trigger Control"] pub type SCHMITT27_R = crate::BitReader; #[doc = "Field `SCHMITT27` writer - Schmitt Trigger Control"] -pub type SCHMITT27_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT28` reader - Schmitt Trigger Control"] pub type SCHMITT28_R = crate::BitReader; #[doc = "Field `SCHMITT28` writer - Schmitt Trigger Control"] -pub type SCHMITT28_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT29` reader - Schmitt Trigger Control"] pub type SCHMITT29_R = crate::BitReader; #[doc = "Field `SCHMITT29` writer - Schmitt Trigger Control"] -pub type SCHMITT29_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT30` reader - Schmitt Trigger Control"] pub type SCHMITT30_R = crate::BitReader; #[doc = "Field `SCHMITT30` writer - Schmitt Trigger Control"] -pub type SCHMITT30_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCHMITT31` reader - Schmitt Trigger Control"] pub type SCHMITT31_R = crate::BitReader; #[doc = "Field `SCHMITT31` writer - Schmitt Trigger Control"] -pub type SCHMITT31_W<'a, const O: u8> = crate::BitWriter<'a, SCHMITT_SPEC, O>; +pub type SCHMITT31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Schmitt Trigger Control"] #[inline(always)] @@ -328,214 +296,211 @@ impl W { #[doc = "Bit 0 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt0(&mut self) -> SCHMITT0_W<0> { + pub fn schmitt0(&mut self) -> SCHMITT0_W { SCHMITT0_W::new(self) } #[doc = "Bit 1 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt1(&mut self) -> SCHMITT1_W<1> { + pub fn schmitt1(&mut self) -> SCHMITT1_W { SCHMITT1_W::new(self) } #[doc = "Bit 2 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt2(&mut self) -> SCHMITT2_W<2> { + pub fn schmitt2(&mut self) -> SCHMITT2_W { SCHMITT2_W::new(self) } #[doc = "Bit 3 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt3(&mut self) -> SCHMITT3_W<3> { + pub fn schmitt3(&mut self) -> SCHMITT3_W { SCHMITT3_W::new(self) } #[doc = "Bit 4 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt4(&mut self) -> SCHMITT4_W<4> { + pub fn schmitt4(&mut self) -> SCHMITT4_W { SCHMITT4_W::new(self) } #[doc = "Bit 5 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt5(&mut self) -> SCHMITT5_W<5> { + pub fn schmitt5(&mut self) -> SCHMITT5_W { SCHMITT5_W::new(self) } #[doc = "Bit 6 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt6(&mut self) -> SCHMITT6_W<6> { + pub fn schmitt6(&mut self) -> SCHMITT6_W { SCHMITT6_W::new(self) } #[doc = "Bit 7 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt7(&mut self) -> SCHMITT7_W<7> { + pub fn schmitt7(&mut self) -> SCHMITT7_W { SCHMITT7_W::new(self) } #[doc = "Bit 8 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt8(&mut self) -> SCHMITT8_W<8> { + pub fn schmitt8(&mut self) -> SCHMITT8_W { SCHMITT8_W::new(self) } #[doc = "Bit 9 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt9(&mut self) -> SCHMITT9_W<9> { + pub fn schmitt9(&mut self) -> SCHMITT9_W { SCHMITT9_W::new(self) } #[doc = "Bit 10 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt10(&mut self) -> SCHMITT10_W<10> { + pub fn schmitt10(&mut self) -> SCHMITT10_W { SCHMITT10_W::new(self) } #[doc = "Bit 11 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt11(&mut self) -> SCHMITT11_W<11> { + pub fn schmitt11(&mut self) -> SCHMITT11_W { SCHMITT11_W::new(self) } #[doc = "Bit 12 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt12(&mut self) -> SCHMITT12_W<12> { + pub fn schmitt12(&mut self) -> SCHMITT12_W { SCHMITT12_W::new(self) } #[doc = "Bit 13 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt13(&mut self) -> SCHMITT13_W<13> { + pub fn schmitt13(&mut self) -> SCHMITT13_W { SCHMITT13_W::new(self) } #[doc = "Bit 14 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt14(&mut self) -> SCHMITT14_W<14> { + pub fn schmitt14(&mut self) -> SCHMITT14_W { SCHMITT14_W::new(self) } #[doc = "Bit 15 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt15(&mut self) -> SCHMITT15_W<15> { + pub fn schmitt15(&mut self) -> SCHMITT15_W { SCHMITT15_W::new(self) } #[doc = "Bit 16 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt16(&mut self) -> SCHMITT16_W<16> { + pub fn schmitt16(&mut self) -> SCHMITT16_W { SCHMITT16_W::new(self) } #[doc = "Bit 17 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt17(&mut self) -> SCHMITT17_W<17> { + pub fn schmitt17(&mut self) -> SCHMITT17_W { SCHMITT17_W::new(self) } #[doc = "Bit 18 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt18(&mut self) -> SCHMITT18_W<18> { + pub fn schmitt18(&mut self) -> SCHMITT18_W { SCHMITT18_W::new(self) } #[doc = "Bit 19 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt19(&mut self) -> SCHMITT19_W<19> { + pub fn schmitt19(&mut self) -> SCHMITT19_W { SCHMITT19_W::new(self) } #[doc = "Bit 20 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt20(&mut self) -> SCHMITT20_W<20> { + pub fn schmitt20(&mut self) -> SCHMITT20_W { SCHMITT20_W::new(self) } #[doc = "Bit 21 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt21(&mut self) -> SCHMITT21_W<21> { + pub fn schmitt21(&mut self) -> SCHMITT21_W { SCHMITT21_W::new(self) } #[doc = "Bit 22 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt22(&mut self) -> SCHMITT22_W<22> { + pub fn schmitt22(&mut self) -> SCHMITT22_W { SCHMITT22_W::new(self) } #[doc = "Bit 23 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt23(&mut self) -> SCHMITT23_W<23> { + pub fn schmitt23(&mut self) -> SCHMITT23_W { SCHMITT23_W::new(self) } #[doc = "Bit 24 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt24(&mut self) -> SCHMITT24_W<24> { + pub fn schmitt24(&mut self) -> SCHMITT24_W { SCHMITT24_W::new(self) } #[doc = "Bit 25 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt25(&mut self) -> SCHMITT25_W<25> { + pub fn schmitt25(&mut self) -> SCHMITT25_W { SCHMITT25_W::new(self) } #[doc = "Bit 26 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt26(&mut self) -> SCHMITT26_W<26> { + pub fn schmitt26(&mut self) -> SCHMITT26_W { SCHMITT26_W::new(self) } #[doc = "Bit 27 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt27(&mut self) -> SCHMITT27_W<27> { + pub fn schmitt27(&mut self) -> SCHMITT27_W { SCHMITT27_W::new(self) } #[doc = "Bit 28 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt28(&mut self) -> SCHMITT28_W<28> { + pub fn schmitt28(&mut self) -> SCHMITT28_W { SCHMITT28_W::new(self) } #[doc = "Bit 29 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt29(&mut self) -> SCHMITT29_W<29> { + pub fn schmitt29(&mut self) -> SCHMITT29_W { SCHMITT29_W::new(self) } #[doc = "Bit 30 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt30(&mut self) -> SCHMITT30_W<30> { + pub fn schmitt30(&mut self) -> SCHMITT30_W { SCHMITT30_W::new(self) } #[doc = "Bit 31 - Schmitt Trigger Control"] #[inline(always)] #[must_use] - pub fn schmitt31(&mut self) -> SCHMITT31_W<31> { + pub fn schmitt31(&mut self) -> SCHMITT31_W { SCHMITT31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Schmitt Trigger Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [schmitt](index.html) module"] +#[doc = "Schmitt Trigger Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`schmitt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`schmitt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCHMITT_SPEC; impl crate::RegisterSpec for SCHMITT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [schmitt::R](R) reader structure"] -impl crate::Readable for SCHMITT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [schmitt::W](W) writer structure"] +#[doc = "`read()` method returns [`schmitt::R`](R) reader structure"] +impl crate::Readable for SCHMITT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`schmitt::W`](W) writer structure"] impl crate::Writable for SCHMITT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/sodr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/sodr.rs index f0632515..3c3a4e3e 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/sodr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/sodr.rs @@ -1,296 +1,276 @@ #[doc = "Register `SODR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `P0` writer - Set Output Data"] -pub type P0_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P1` writer - Set Output Data"] -pub type P1_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P2` writer - Set Output Data"] -pub type P2_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P3` writer - Set Output Data"] -pub type P3_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P4` writer - Set Output Data"] -pub type P4_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P5` writer - Set Output Data"] -pub type P5_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P6` writer - Set Output Data"] -pub type P6_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P7` writer - Set Output Data"] -pub type P7_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P8` writer - Set Output Data"] -pub type P8_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P9` writer - Set Output Data"] -pub type P9_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P10` writer - Set Output Data"] -pub type P10_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P11` writer - Set Output Data"] -pub type P11_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P12` writer - Set Output Data"] -pub type P12_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P13` writer - Set Output Data"] -pub type P13_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P14` writer - Set Output Data"] -pub type P14_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P15` writer - Set Output Data"] -pub type P15_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P16` writer - Set Output Data"] -pub type P16_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P17` writer - Set Output Data"] -pub type P17_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P18` writer - Set Output Data"] -pub type P18_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P19` writer - Set Output Data"] -pub type P19_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P20` writer - Set Output Data"] -pub type P20_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P21` writer - Set Output Data"] -pub type P21_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P22` writer - Set Output Data"] -pub type P22_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P23` writer - Set Output Data"] -pub type P23_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P24` writer - Set Output Data"] -pub type P24_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P25` writer - Set Output Data"] -pub type P25_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P26` writer - Set Output Data"] -pub type P26_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P27` writer - Set Output Data"] -pub type P27_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P28` writer - Set Output Data"] -pub type P28_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P29` writer - Set Output Data"] -pub type P29_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P30` writer - Set Output Data"] -pub type P30_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `P31` writer - Set Output Data"] -pub type P31_W<'a, const O: u8> = crate::BitWriter<'a, SODR_SPEC, O>; +pub type P31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p0(&mut self) -> P0_W<0> { + pub fn p0(&mut self) -> P0_W { P0_W::new(self) } #[doc = "Bit 1 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p1(&mut self) -> P1_W<1> { + pub fn p1(&mut self) -> P1_W { P1_W::new(self) } #[doc = "Bit 2 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p2(&mut self) -> P2_W<2> { + pub fn p2(&mut self) -> P2_W { P2_W::new(self) } #[doc = "Bit 3 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p3(&mut self) -> P3_W<3> { + pub fn p3(&mut self) -> P3_W { P3_W::new(self) } #[doc = "Bit 4 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p4(&mut self) -> P4_W<4> { + pub fn p4(&mut self) -> P4_W { P4_W::new(self) } #[doc = "Bit 5 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p5(&mut self) -> P5_W<5> { + pub fn p5(&mut self) -> P5_W { P5_W::new(self) } #[doc = "Bit 6 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p6(&mut self) -> P6_W<6> { + pub fn p6(&mut self) -> P6_W { P6_W::new(self) } #[doc = "Bit 7 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p7(&mut self) -> P7_W<7> { + pub fn p7(&mut self) -> P7_W { P7_W::new(self) } #[doc = "Bit 8 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p8(&mut self) -> P8_W<8> { + pub fn p8(&mut self) -> P8_W { P8_W::new(self) } #[doc = "Bit 9 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p9(&mut self) -> P9_W<9> { + pub fn p9(&mut self) -> P9_W { P9_W::new(self) } #[doc = "Bit 10 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p10(&mut self) -> P10_W<10> { + pub fn p10(&mut self) -> P10_W { P10_W::new(self) } #[doc = "Bit 11 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p11(&mut self) -> P11_W<11> { + pub fn p11(&mut self) -> P11_W { P11_W::new(self) } #[doc = "Bit 12 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p12(&mut self) -> P12_W<12> { + pub fn p12(&mut self) -> P12_W { P12_W::new(self) } #[doc = "Bit 13 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p13(&mut self) -> P13_W<13> { + pub fn p13(&mut self) -> P13_W { P13_W::new(self) } #[doc = "Bit 14 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p14(&mut self) -> P14_W<14> { + pub fn p14(&mut self) -> P14_W { P14_W::new(self) } #[doc = "Bit 15 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p15(&mut self) -> P15_W<15> { + pub fn p15(&mut self) -> P15_W { P15_W::new(self) } #[doc = "Bit 16 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p16(&mut self) -> P16_W<16> { + pub fn p16(&mut self) -> P16_W { P16_W::new(self) } #[doc = "Bit 17 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p17(&mut self) -> P17_W<17> { + pub fn p17(&mut self) -> P17_W { P17_W::new(self) } #[doc = "Bit 18 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p18(&mut self) -> P18_W<18> { + pub fn p18(&mut self) -> P18_W { P18_W::new(self) } #[doc = "Bit 19 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p19(&mut self) -> P19_W<19> { + pub fn p19(&mut self) -> P19_W { P19_W::new(self) } #[doc = "Bit 20 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p20(&mut self) -> P20_W<20> { + pub fn p20(&mut self) -> P20_W { P20_W::new(self) } #[doc = "Bit 21 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p21(&mut self) -> P21_W<21> { + pub fn p21(&mut self) -> P21_W { P21_W::new(self) } #[doc = "Bit 22 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p22(&mut self) -> P22_W<22> { + pub fn p22(&mut self) -> P22_W { P22_W::new(self) } #[doc = "Bit 23 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p23(&mut self) -> P23_W<23> { + pub fn p23(&mut self) -> P23_W { P23_W::new(self) } #[doc = "Bit 24 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p24(&mut self) -> P24_W<24> { + pub fn p24(&mut self) -> P24_W { P24_W::new(self) } #[doc = "Bit 25 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p25(&mut self) -> P25_W<25> { + pub fn p25(&mut self) -> P25_W { P25_W::new(self) } #[doc = "Bit 26 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p26(&mut self) -> P26_W<26> { + pub fn p26(&mut self) -> P26_W { P26_W::new(self) } #[doc = "Bit 27 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p27(&mut self) -> P27_W<27> { + pub fn p27(&mut self) -> P27_W { P27_W::new(self) } #[doc = "Bit 28 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p28(&mut self) -> P28_W<28> { + pub fn p28(&mut self) -> P28_W { P28_W::new(self) } #[doc = "Bit 29 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p29(&mut self) -> P29_W<29> { + pub fn p29(&mut self) -> P29_W { P29_W::new(self) } #[doc = "Bit 30 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p30(&mut self) -> P30_W<30> { + pub fn p30(&mut self) -> P30_W { P30_W::new(self) } #[doc = "Bit 31 - Set Output Data"] #[inline(always)] #[must_use] - pub fn p31(&mut self) -> P31_W<31> { + pub fn p31(&mut self) -> P31_W { P31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Set Output Data Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sodr](index.html) module"] +#[doc = "Set Output Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sodr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SODR_SPEC; impl crate::RegisterSpec for SODR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [sodr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`sodr::W`](W) writer structure"] impl crate::Writable for SODR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/wpmr.rs index d5adc457..ef89efd3 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pioa/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/pioa/wpsr.rs index 69b9952f..216a7a8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/pioa/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pioa/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc.rs b/arch/cortex-m/samv71q21-pac/src/pmc.rs index 5ad5ab80..b041482c 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc.rs @@ -83,151 +83,188 @@ pub struct RegisterBlock { #[doc = "0x144 - SleepWalking Activity In Progress Register"] pub slpwk_aipr: SLPWK_AIPR, } -#[doc = "SCER (w) register accessor: an alias for `Reg`"] +#[doc = "SCER (w) register accessor: System Clock Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scer::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scer`] +module"] pub type SCER = crate::Reg; #[doc = "System Clock Enable Register"] pub mod scer; -#[doc = "SCDR (w) register accessor: an alias for `Reg`"] +#[doc = "SCDR (w) register accessor: System Clock Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scdr`] +module"] pub type SCDR = crate::Reg; #[doc = "System Clock Disable Register"] pub mod scdr; -#[doc = "SCSR (r) register accessor: an alias for `Reg`"] +#[doc = "SCSR (r) register accessor: System Clock Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scsr`] +module"] pub type SCSR = crate::Reg; #[doc = "System Clock Status Register"] pub mod scsr; -#[doc = "PCER0 (w) register accessor: an alias for `Reg`"] +#[doc = "PCER0 (w) register accessor: Peripheral Clock Enable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcer0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcer0`] +module"] pub type PCER0 = crate::Reg; #[doc = "Peripheral Clock Enable Register 0"] pub mod pcer0; -#[doc = "PCDR0 (w) register accessor: an alias for `Reg`"] +#[doc = "PCDR0 (w) register accessor: Peripheral Clock Disable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcdr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcdr0`] +module"] pub type PCDR0 = crate::Reg; #[doc = "Peripheral Clock Disable Register 0"] pub mod pcdr0; -#[doc = "PCSR0 (r) register accessor: an alias for `Reg`"] +#[doc = "PCSR0 (r) register accessor: Peripheral Clock Status Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcsr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcsr0`] +module"] pub type PCSR0 = crate::Reg; #[doc = "Peripheral Clock Status Register 0"] pub mod pcsr0; -#[doc = "CKGR_UCKR (rw) register accessor: an alias for `Reg`"] +#[doc = "CKGR_UCKR (rw) register accessor: UTMI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_uckr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_uckr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ckgr_uckr`] +module"] pub type CKGR_UCKR = crate::Reg; #[doc = "UTMI Clock Register"] pub mod ckgr_uckr; -#[doc = "CKGR_MOR (rw) register accessor: an alias for `Reg`"] +#[doc = "CKGR_MOR (rw) register accessor: Main Oscillator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_mor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_mor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ckgr_mor`] +module"] pub type CKGR_MOR = crate::Reg; #[doc = "Main Oscillator Register"] pub mod ckgr_mor; -#[doc = "CKGR_MCFR (rw) register accessor: an alias for `Reg`"] +#[doc = "CKGR_MCFR (rw) register accessor: Main Clock Frequency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_mcfr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_mcfr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ckgr_mcfr`] +module"] pub type CKGR_MCFR = crate::Reg; #[doc = "Main Clock Frequency Register"] pub mod ckgr_mcfr; -#[doc = "CKGR_PLLAR (rw) register accessor: an alias for `Reg`"] +#[doc = "CKGR_PLLAR (rw) register accessor: PLLA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_pllar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_pllar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ckgr_pllar`] +module"] pub type CKGR_PLLAR = crate::Reg; #[doc = "PLLA Register"] pub mod ckgr_pllar; -#[doc = "MCKR (rw) register accessor: an alias for `Reg`"] +#[doc = "MCKR (rw) register accessor: Master Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mckr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mckr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mckr`] +module"] pub type MCKR = crate::Reg; #[doc = "Master Clock Register"] pub mod mckr; -#[doc = "USB (rw) register accessor: an alias for `Reg`"] +#[doc = "USB (rw) register accessor: USB Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`usb`] +module"] pub type USB = crate::Reg; #[doc = "USB Clock Register"] pub mod usb; -#[doc = "PCK (rw) register accessor: an alias for `Reg`"] +#[doc = "PCK (rw) register accessor: Programmable Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pck::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pck::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pck`] +module"] pub type PCK = crate::Reg; #[doc = "Programmable Clock Register"] pub mod pck; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "FSMR (rw) register accessor: an alias for `Reg`"] +#[doc = "FSMR (rw) register accessor: Fast Startup Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fsmr`] +module"] pub type FSMR = crate::Reg; #[doc = "Fast Startup Mode Register"] pub mod fsmr; -#[doc = "FSPR (rw) register accessor: an alias for `Reg`"] +#[doc = "FSPR (rw) register accessor: Fast Startup Polarity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fspr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fspr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fspr`] +module"] pub type FSPR = crate::Reg; #[doc = "Fast Startup Polarity Register"] pub mod fspr; -#[doc = "FOCR (w) register accessor: an alias for `Reg`"] +#[doc = "FOCR (w) register accessor: Fault Output Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`focr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`focr`] +module"] pub type FOCR = crate::Reg; #[doc = "Fault Output Clear Register"] pub mod focr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; -#[doc = "PCER1 (w) register accessor: an alias for `Reg`"] +#[doc = "PCER1 (w) register accessor: Peripheral Clock Enable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcer1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcer1`] +module"] pub type PCER1 = crate::Reg; #[doc = "Peripheral Clock Enable Register 1"] pub mod pcer1; -#[doc = "PCDR1 (w) register accessor: an alias for `Reg`"] +#[doc = "PCDR1 (w) register accessor: Peripheral Clock Disable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcdr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcdr1`] +module"] pub type PCDR1 = crate::Reg; #[doc = "Peripheral Clock Disable Register 1"] pub mod pcdr1; -#[doc = "PCSR1 (r) register accessor: an alias for `Reg`"] +#[doc = "PCSR1 (r) register accessor: Peripheral Clock Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcsr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcsr1`] +module"] pub type PCSR1 = crate::Reg; #[doc = "Peripheral Clock Status Register 1"] pub mod pcsr1; -#[doc = "PCR (rw) register accessor: an alias for `Reg`"] +#[doc = "PCR (rw) register accessor: Peripheral Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pcr`] +module"] pub type PCR = crate::Reg; #[doc = "Peripheral Control Register"] pub mod pcr; -#[doc = "OCR (rw) register accessor: an alias for `Reg`"] +#[doc = "OCR (rw) register accessor: Oscillator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ocr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ocr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ocr`] +module"] pub type OCR = crate::Reg; #[doc = "Oscillator Calibration Register"] pub mod ocr; -#[doc = "SLPWK_ER0 (w) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_ER0 (w) register accessor: SleepWalking Enable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_er0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_er0`] +module"] pub type SLPWK_ER0 = crate::Reg; #[doc = "SleepWalking Enable Register 0"] pub mod slpwk_er0; -#[doc = "SLPWK_DR0 (w) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_DR0 (w) register accessor: SleepWalking Disable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_dr0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_dr0`] +module"] pub type SLPWK_DR0 = crate::Reg; #[doc = "SleepWalking Disable Register 0"] pub mod slpwk_dr0; -#[doc = "SLPWK_SR0 (r) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_SR0 (r) register accessor: SleepWalking Status Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_sr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_sr0`] +module"] pub type SLPWK_SR0 = crate::Reg; #[doc = "SleepWalking Status Register 0"] pub mod slpwk_sr0; -#[doc = "SLPWK_ASR0 (r) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_ASR0 (r) register accessor: SleepWalking Activity Status Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_asr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_asr0`] +module"] pub type SLPWK_ASR0 = crate::Reg; #[doc = "SleepWalking Activity Status Register 0"] pub mod slpwk_asr0; -#[doc = "PMMR (rw) register accessor: an alias for `Reg`"] +#[doc = "PMMR (rw) register accessor: PLL Maximum Multiplier Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pmmr`] +module"] pub type PMMR = crate::Reg; #[doc = "PLL Maximum Multiplier Value Register"] pub mod pmmr; -#[doc = "SLPWK_ER1 (w) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_ER1 (w) register accessor: SleepWalking Enable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_er1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_er1`] +module"] pub type SLPWK_ER1 = crate::Reg; #[doc = "SleepWalking Enable Register 1"] pub mod slpwk_er1; -#[doc = "SLPWK_DR1 (w) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_DR1 (w) register accessor: SleepWalking Disable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_dr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_dr1`] +module"] pub type SLPWK_DR1 = crate::Reg; #[doc = "SleepWalking Disable Register 1"] pub mod slpwk_dr1; -#[doc = "SLPWK_SR1 (r) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_SR1 (r) register accessor: SleepWalking Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_sr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_sr1`] +module"] pub type SLPWK_SR1 = crate::Reg; #[doc = "SleepWalking Status Register 1"] pub mod slpwk_sr1; -#[doc = "SLPWK_ASR1 (r) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_ASR1 (r) register accessor: SleepWalking Activity Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_asr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_asr1`] +module"] pub type SLPWK_ASR1 = crate::Reg; #[doc = "SleepWalking Activity Status Register 1"] pub mod slpwk_asr1; -#[doc = "SLPWK_AIPR (r) register accessor: an alias for `Reg`"] +#[doc = "SLPWK_AIPR (r) register accessor: SleepWalking Activity In Progress Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_aipr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`slpwk_aipr`] +module"] pub type SLPWK_AIPR = crate::Reg; #[doc = "SleepWalking Activity In Progress Register"] pub mod slpwk_aipr; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mcfr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mcfr.rs index d82b8a94..55ac61e6 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mcfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mcfr.rs @@ -1,55 +1,23 @@ #[doc = "Register `CKGR_MCFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CKGR_MCFR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MAINF` reader - Main Clock Frequency"] pub type MAINF_R = crate::FieldReader; #[doc = "Field `MAINF` writer - Main Clock Frequency"] -pub type MAINF_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_MCFR_SPEC, 16, O, u16>; +pub type MAINF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `MAINFRDY` reader - Main Clock Frequency Measure Ready"] pub type MAINFRDY_R = crate::BitReader; #[doc = "Field `MAINFRDY` writer - Main Clock Frequency Measure Ready"] -pub type MAINFRDY_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MCFR_SPEC, O>; +pub type MAINFRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCMEAS` reader - RC Oscillator Frequency Measure (write-only)"] pub type RCMEAS_R = crate::BitReader; #[doc = "Field `RCMEAS` writer - RC Oscillator Frequency Measure (write-only)"] -pub type RCMEAS_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MCFR_SPEC, O>; +pub type RCMEAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CCSS` reader - Counter Clock Source Selection"] pub type CCSS_R = crate::BitReader; #[doc = "Field `CCSS` writer - Counter Clock Source Selection"] -pub type CCSS_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MCFR_SPEC, O>; +pub type CCSS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - Main Clock Frequency"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:15 - Main Clock Frequency"] #[inline(always)] #[must_use] - pub fn mainf(&mut self) -> MAINF_W<0> { + pub fn mainf(&mut self) -> MAINF_W { MAINF_W::new(self) } #[doc = "Bit 16 - Main Clock Frequency Measure Ready"] #[inline(always)] #[must_use] - pub fn mainfrdy(&mut self) -> MAINFRDY_W<16> { + pub fn mainfrdy(&mut self) -> MAINFRDY_W { MAINFRDY_W::new(self) } #[doc = "Bit 20 - RC Oscillator Frequency Measure (write-only)"] #[inline(always)] #[must_use] - pub fn rcmeas(&mut self) -> RCMEAS_W<20> { + pub fn rcmeas(&mut self) -> RCMEAS_W { RCMEAS_W::new(self) } #[doc = "Bit 24 - Counter Clock Source Selection"] #[inline(always)] #[must_use] - pub fn ccss(&mut self) -> CCSS_W<24> { + pub fn ccss(&mut self) -> CCSS_W { CCSS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Main Clock Frequency Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ckgr_mcfr](index.html) module"] +#[doc = "Main Clock Frequency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_mcfr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_mcfr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CKGR_MCFR_SPEC; impl crate::RegisterSpec for CKGR_MCFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ckgr_mcfr::R](R) reader structure"] -impl crate::Readable for CKGR_MCFR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ckgr_mcfr::W](W) writer structure"] +#[doc = "`read()` method returns [`ckgr_mcfr::R`](R) reader structure"] +impl crate::Readable for CKGR_MCFR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ckgr_mcfr::W`](W) writer structure"] impl crate::Writable for CKGR_MCFR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mor.rs b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mor.rs index c590706c..ad1fce35 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mor.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_mor.rs @@ -1,55 +1,23 @@ #[doc = "Register `CKGR_MOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CKGR_MOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MOSCXTEN` reader - Main Crystal Oscillator Enable"] pub type MOSCXTEN_R = crate::BitReader; #[doc = "Field `MOSCXTEN` writer - Main Crystal Oscillator Enable"] -pub type MOSCXTEN_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type MOSCXTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCXTBY` reader - Main Crystal Oscillator Bypass"] pub type MOSCXTBY_R = crate::BitReader; #[doc = "Field `MOSCXTBY` writer - Main Crystal Oscillator Bypass"] -pub type MOSCXTBY_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type MOSCXTBY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAITMODE` reader - Wait Mode Command (Write-only)"] pub type WAITMODE_R = crate::BitReader; #[doc = "Field `WAITMODE` writer - Wait Mode Command (Write-only)"] -pub type WAITMODE_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type WAITMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCRCEN` reader - Main RC Oscillator Enable"] pub type MOSCRCEN_R = crate::BitReader; #[doc = "Field `MOSCRCEN` writer - Main RC Oscillator Enable"] -pub type MOSCRCEN_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type MOSCRCEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCRCF` reader - Main RC Oscillator Frequency Selection"] pub type MOSCRCF_R = crate::FieldReader; #[doc = "Main RC Oscillator Frequency Selection\n\nValue on reset: 0"] @@ -83,45 +51,49 @@ impl MOSCRCF_R { _ => None, } } - #[doc = "Checks if the value of the field is `_4_MHZ`"] + #[doc = "The RC oscillator frequency is at 4 MHz"] #[inline(always)] pub fn is_4_mhz(&self) -> bool { *self == MOSCRCFSELECT_A::_4_MHZ } - #[doc = "Checks if the value of the field is `_8_MHZ`"] + #[doc = "The RC oscillator frequency is at 8 MHz"] #[inline(always)] pub fn is_8_mhz(&self) -> bool { *self == MOSCRCFSELECT_A::_8_MHZ } - #[doc = "Checks if the value of the field is `_12_MHZ`"] + #[doc = "The RC oscillator frequency is at 12 MHz"] #[inline(always)] pub fn is_12_mhz(&self) -> bool { *self == MOSCRCFSELECT_A::_12_MHZ } } #[doc = "Field `MOSCRCF` writer - Main RC Oscillator Frequency Selection"] -pub type MOSCRCF_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_MOR_SPEC, 3, O, MOSCRCFSELECT_A>; -impl<'a, const O: u8> MOSCRCF_W<'a, O> { +pub type MOSCRCF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, MOSCRCFSELECT_A>; +impl<'a, REG, const O: u8> MOSCRCF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The RC oscillator frequency is at 4 MHz"] #[inline(always)] - pub fn _4_mhz(self) -> &'a mut W { + pub fn _4_mhz(self) -> &'a mut crate::W { self.variant(MOSCRCFSELECT_A::_4_MHZ) } #[doc = "The RC oscillator frequency is at 8 MHz"] #[inline(always)] - pub fn _8_mhz(self) -> &'a mut W { + pub fn _8_mhz(self) -> &'a mut crate::W { self.variant(MOSCRCFSELECT_A::_8_MHZ) } #[doc = "The RC oscillator frequency is at 12 MHz"] #[inline(always)] - pub fn _12_mhz(self) -> &'a mut W { + pub fn _12_mhz(self) -> &'a mut crate::W { self.variant(MOSCRCFSELECT_A::_12_MHZ) } } #[doc = "Field `MOSCXTST` reader - Main Crystal Oscillator Startup Time"] pub type MOSCXTST_R = crate::FieldReader; #[doc = "Field `MOSCXTST` writer - Main Crystal Oscillator Startup Time"] -pub type MOSCXTST_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_MOR_SPEC, 8, O>; +pub type MOSCXTST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `KEY` reader - Write Access Password"] pub type KEY_R = crate::FieldReader; #[doc = "Write Access Password\n\nValue on reset: 0"] @@ -149,33 +121,37 @@ impl KEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == KEYSELECT_A::PASSWD } } #[doc = "Field `KEY` writer - Write Access Password"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_MOR_SPEC, 8, O, KEYSELECT_A>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_A>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_A::PASSWD) } } #[doc = "Field `MOSCSEL` reader - Main Clock Oscillator Selection"] pub type MOSCSEL_R = crate::BitReader; #[doc = "Field `MOSCSEL` writer - Main Clock Oscillator Selection"] -pub type MOSCSEL_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type MOSCSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] pub type CFDEN_R = crate::BitReader; #[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] -pub type CFDEN_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type CFDEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `XT32KFME` reader - 32.768 kHz Crystal Oscillator Frequency Monitoring Enable"] pub type XT32KFME_R = crate::BitReader; #[doc = "Field `XT32KFME` writer - 32.768 kHz Crystal Oscillator Frequency Monitoring Enable"] -pub type XT32KFME_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_MOR_SPEC, O>; +pub type XT32KFME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Main Crystal Oscillator Enable"] #[inline(always)] @@ -232,82 +208,79 @@ impl W { #[doc = "Bit 0 - Main Crystal Oscillator Enable"] #[inline(always)] #[must_use] - pub fn moscxten(&mut self) -> MOSCXTEN_W<0> { + pub fn moscxten(&mut self) -> MOSCXTEN_W { MOSCXTEN_W::new(self) } #[doc = "Bit 1 - Main Crystal Oscillator Bypass"] #[inline(always)] #[must_use] - pub fn moscxtby(&mut self) -> MOSCXTBY_W<1> { + pub fn moscxtby(&mut self) -> MOSCXTBY_W { MOSCXTBY_W::new(self) } #[doc = "Bit 2 - Wait Mode Command (Write-only)"] #[inline(always)] #[must_use] - pub fn waitmode(&mut self) -> WAITMODE_W<2> { + pub fn waitmode(&mut self) -> WAITMODE_W { WAITMODE_W::new(self) } #[doc = "Bit 3 - Main RC Oscillator Enable"] #[inline(always)] #[must_use] - pub fn moscrcen(&mut self) -> MOSCRCEN_W<3> { + pub fn moscrcen(&mut self) -> MOSCRCEN_W { MOSCRCEN_W::new(self) } #[doc = "Bits 4:6 - Main RC Oscillator Frequency Selection"] #[inline(always)] #[must_use] - pub fn moscrcf(&mut self) -> MOSCRCF_W<4> { + pub fn moscrcf(&mut self) -> MOSCRCF_W { MOSCRCF_W::new(self) } #[doc = "Bits 8:15 - Main Crystal Oscillator Startup Time"] #[inline(always)] #[must_use] - pub fn moscxtst(&mut self) -> MOSCXTST_W<8> { + pub fn moscxtst(&mut self) -> MOSCXTST_W { MOSCXTST_W::new(self) } #[doc = "Bits 16:23 - Write Access Password"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<16> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Bit 24 - Main Clock Oscillator Selection"] #[inline(always)] #[must_use] - pub fn moscsel(&mut self) -> MOSCSEL_W<24> { + pub fn moscsel(&mut self) -> MOSCSEL_W { MOSCSEL_W::new(self) } #[doc = "Bit 25 - Clock Failure Detector Enable"] #[inline(always)] #[must_use] - pub fn cfden(&mut self) -> CFDEN_W<25> { + pub fn cfden(&mut self) -> CFDEN_W { CFDEN_W::new(self) } #[doc = "Bit 26 - 32.768 kHz Crystal Oscillator Frequency Monitoring Enable"] #[inline(always)] #[must_use] - pub fn xt32kfme(&mut self) -> XT32KFME_W<26> { + pub fn xt32kfme(&mut self) -> XT32KFME_W { XT32KFME_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Main Oscillator Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ckgr_mor](index.html) module"] +#[doc = "Main Oscillator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_mor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_mor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CKGR_MOR_SPEC; impl crate::RegisterSpec for CKGR_MOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ckgr_mor::R](R) reader structure"] -impl crate::Readable for CKGR_MOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ckgr_mor::W](W) writer structure"] +#[doc = "`read()` method returns [`ckgr_mor::R`](R) reader structure"] +impl crate::Readable for CKGR_MOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ckgr_mor::W`](W) writer structure"] impl crate::Writable for CKGR_MOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_pllar.rs b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_pllar.rs index fd0f1c7a..f7df7363 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_pllar.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_pllar.rs @@ -1,39 +1,7 @@ #[doc = "Register `CKGR_PLLAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CKGR_PLLAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIVA` reader - PLLA Front End Divider"] pub type DIVA_R = crate::FieldReader; #[doc = "PLLA Front End Divider\n\nValue on reset: 0"] @@ -64,43 +32,47 @@ impl DIVA_R { _ => None, } } - #[doc = "Checks if the value of the field is `_0`"] + #[doc = "Divider output is 0 and PLLA is disabled."] #[inline(always)] pub fn is_0(&self) -> bool { *self == DIVASELECT_A::_0 } - #[doc = "Checks if the value of the field is `BYPASS`"] + #[doc = "Divider is bypassed (divide by 1) and PLLA is enabled."] #[inline(always)] pub fn is_bypass(&self) -> bool { *self == DIVASELECT_A::BYPASS } } #[doc = "Field `DIVA` writer - PLLA Front End Divider"] -pub type DIVA_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_PLLAR_SPEC, 8, O, DIVASELECT_A>; -impl<'a, const O: u8> DIVA_W<'a, O> { +pub type DIVA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, DIVASELECT_A>; +impl<'a, REG, const O: u8> DIVA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Divider output is 0 and PLLA is disabled."] #[inline(always)] - pub fn _0(self) -> &'a mut W { + pub fn _0(self) -> &'a mut crate::W { self.variant(DIVASELECT_A::_0) } #[doc = "Divider is bypassed (divide by 1) and PLLA is enabled."] #[inline(always)] - pub fn bypass(self) -> &'a mut W { + pub fn bypass(self) -> &'a mut crate::W { self.variant(DIVASELECT_A::BYPASS) } } #[doc = "Field `PLLACOUNT` reader - PLLA Counter"] pub type PLLACOUNT_R = crate::FieldReader; #[doc = "Field `PLLACOUNT` writer - PLLA Counter"] -pub type PLLACOUNT_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_PLLAR_SPEC, 6, O>; +pub type PLLACOUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MULA` reader - PLLA Multiplier"] pub type MULA_R = crate::FieldReader; #[doc = "Field `MULA` writer - PLLA Multiplier"] -pub type MULA_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_PLLAR_SPEC, 11, O, u16>; +pub type MULA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `ONE` reader - Must Be Set to 1"] pub type ONE_R = crate::BitReader; #[doc = "Field `ONE` writer - Must Be Set to 1"] -pub type ONE_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_PLLAR_SPEC, O>; +pub type ONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - PLLA Front End Divider"] #[inline(always)] @@ -127,46 +99,43 @@ impl W { #[doc = "Bits 0:7 - PLLA Front End Divider"] #[inline(always)] #[must_use] - pub fn diva(&mut self) -> DIVA_W<0> { + pub fn diva(&mut self) -> DIVA_W { DIVA_W::new(self) } #[doc = "Bits 8:13 - PLLA Counter"] #[inline(always)] #[must_use] - pub fn pllacount(&mut self) -> PLLACOUNT_W<8> { + pub fn pllacount(&mut self) -> PLLACOUNT_W { PLLACOUNT_W::new(self) } #[doc = "Bits 16:26 - PLLA Multiplier"] #[inline(always)] #[must_use] - pub fn mula(&mut self) -> MULA_W<16> { + pub fn mula(&mut self) -> MULA_W { MULA_W::new(self) } #[doc = "Bit 29 - Must Be Set to 1"] #[inline(always)] #[must_use] - pub fn one(&mut self) -> ONE_W<29> { + pub fn one(&mut self) -> ONE_W { ONE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PLLA Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ckgr_pllar](index.html) module"] +#[doc = "PLLA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_pllar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_pllar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CKGR_PLLAR_SPEC; impl crate::RegisterSpec for CKGR_PLLAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ckgr_pllar::R](R) reader structure"] -impl crate::Readable for CKGR_PLLAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ckgr_pllar::W](W) writer structure"] +#[doc = "`read()` method returns [`ckgr_pllar::R`](R) reader structure"] +impl crate::Readable for CKGR_PLLAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ckgr_pllar::W`](W) writer structure"] impl crate::Writable for CKGR_PLLAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_uckr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_uckr.rs index 4475a88a..c06aebbc 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_uckr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/ckgr_uckr.rs @@ -1,47 +1,15 @@ #[doc = "Register `CKGR_UCKR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CKGR_UCKR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UPLLEN` reader - UTMI PLL Enable"] pub type UPLLEN_R = crate::BitReader; #[doc = "Field `UPLLEN` writer - UTMI PLL Enable"] -pub type UPLLEN_W<'a, const O: u8> = crate::BitWriter<'a, CKGR_UCKR_SPEC, O>; +pub type UPLLEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPLLCOUNT` reader - UTMI PLL Start-up Time"] pub type UPLLCOUNT_R = crate::FieldReader; #[doc = "Field `UPLLCOUNT` writer - UTMI PLL Start-up Time"] -pub type UPLLCOUNT_W<'a, const O: u8> = crate::FieldWriter<'a, CKGR_UCKR_SPEC, 4, O>; +pub type UPLLCOUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 16 - UTMI PLL Enable"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 16 - UTMI PLL Enable"] #[inline(always)] #[must_use] - pub fn upllen(&mut self) -> UPLLEN_W<16> { + pub fn upllen(&mut self) -> UPLLEN_W { UPLLEN_W::new(self) } #[doc = "Bits 20:23 - UTMI PLL Start-up Time"] #[inline(always)] #[must_use] - pub fn upllcount(&mut self) -> UPLLCOUNT_W<20> { + pub fn upllcount(&mut self) -> UPLLCOUNT_W { UPLLCOUNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "UTMI Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ckgr_uckr](index.html) module"] +#[doc = "UTMI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ckgr_uckr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ckgr_uckr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CKGR_UCKR_SPEC; impl crate::RegisterSpec for CKGR_UCKR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ckgr_uckr::R](R) reader structure"] -impl crate::Readable for CKGR_UCKR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ckgr_uckr::W](W) writer structure"] +#[doc = "`read()` method returns [`ckgr_uckr::R`](R) reader structure"] +impl crate::Readable for CKGR_UCKR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ckgr_uckr::W`](W) writer structure"] impl crate::Writable for CKGR_UCKR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/focr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/focr.rs index c1cc638b..46ead884 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/focr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/focr.rs @@ -1,48 +1,28 @@ #[doc = "Register `FOCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FOCLR` writer - Fault Output Clear"] -pub type FOCLR_W<'a, const O: u8> = crate::BitWriter<'a, FOCR_SPEC, O>; +pub type FOCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Fault Output Clear"] #[inline(always)] #[must_use] - pub fn foclr(&mut self) -> FOCLR_W<0> { + pub fn foclr(&mut self) -> FOCLR_W { FOCLR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fault Output Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [focr](index.html) module"] +#[doc = "Fault Output Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`focr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FOCR_SPEC; impl crate::RegisterSpec for FOCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [focr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`focr::W`](W) writer structure"] impl crate::Writable for FOCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/fsmr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/fsmr.rs index 394174ba..70817784 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/fsmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/fsmr.rs @@ -1,119 +1,87 @@ #[doc = "Register `FSMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FSMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSTT0` reader - Fast Startup Input Enable 0"] pub type FSTT0_R = crate::BitReader; #[doc = "Field `FSTT0` writer - Fast Startup Input Enable 0"] -pub type FSTT0_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT1` reader - Fast Startup Input Enable 1"] pub type FSTT1_R = crate::BitReader; #[doc = "Field `FSTT1` writer - Fast Startup Input Enable 1"] -pub type FSTT1_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT2` reader - Fast Startup Input Enable 2"] pub type FSTT2_R = crate::BitReader; #[doc = "Field `FSTT2` writer - Fast Startup Input Enable 2"] -pub type FSTT2_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT3` reader - Fast Startup Input Enable 3"] pub type FSTT3_R = crate::BitReader; #[doc = "Field `FSTT3` writer - Fast Startup Input Enable 3"] -pub type FSTT3_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT4` reader - Fast Startup Input Enable 4"] pub type FSTT4_R = crate::BitReader; #[doc = "Field `FSTT4` writer - Fast Startup Input Enable 4"] -pub type FSTT4_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT5` reader - Fast Startup Input Enable 5"] pub type FSTT5_R = crate::BitReader; #[doc = "Field `FSTT5` writer - Fast Startup Input Enable 5"] -pub type FSTT5_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT6` reader - Fast Startup Input Enable 6"] pub type FSTT6_R = crate::BitReader; #[doc = "Field `FSTT6` writer - Fast Startup Input Enable 6"] -pub type FSTT6_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT7` reader - Fast Startup Input Enable 7"] pub type FSTT7_R = crate::BitReader; #[doc = "Field `FSTT7` writer - Fast Startup Input Enable 7"] -pub type FSTT7_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT8` reader - Fast Startup Input Enable 8"] pub type FSTT8_R = crate::BitReader; #[doc = "Field `FSTT8` writer - Fast Startup Input Enable 8"] -pub type FSTT8_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT9` reader - Fast Startup Input Enable 9"] pub type FSTT9_R = crate::BitReader; #[doc = "Field `FSTT9` writer - Fast Startup Input Enable 9"] -pub type FSTT9_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT10` reader - Fast Startup Input Enable 10"] pub type FSTT10_R = crate::BitReader; #[doc = "Field `FSTT10` writer - Fast Startup Input Enable 10"] -pub type FSTT10_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT11` reader - Fast Startup Input Enable 11"] pub type FSTT11_R = crate::BitReader; #[doc = "Field `FSTT11` writer - Fast Startup Input Enable 11"] -pub type FSTT11_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT12` reader - Fast Startup Input Enable 12"] pub type FSTT12_R = crate::BitReader; #[doc = "Field `FSTT12` writer - Fast Startup Input Enable 12"] -pub type FSTT12_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT13` reader - Fast Startup Input Enable 13"] pub type FSTT13_R = crate::BitReader; #[doc = "Field `FSTT13` writer - Fast Startup Input Enable 13"] -pub type FSTT13_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT14` reader - Fast Startup Input Enable 14"] pub type FSTT14_R = crate::BitReader; #[doc = "Field `FSTT14` writer - Fast Startup Input Enable 14"] -pub type FSTT14_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTT15` reader - Fast Startup Input Enable 15"] pub type FSTT15_R = crate::BitReader; #[doc = "Field `FSTT15` writer - Fast Startup Input Enable 15"] -pub type FSTT15_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FSTT15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTTAL` reader - RTT Alarm Enable"] pub type RTTAL_R = crate::BitReader; #[doc = "Field `RTTAL` writer - RTT Alarm Enable"] -pub type RTTAL_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type RTTAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTCAL` reader - RTC Alarm Enable"] pub type RTCAL_R = crate::BitReader; #[doc = "Field `RTCAL` writer - RTC Alarm Enable"] -pub type RTCAL_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type RTCAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBAL` reader - USB Alarm Enable"] pub type USBAL_R = crate::BitReader; #[doc = "Field `USBAL` writer - USB Alarm Enable"] -pub type USBAL_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type USBAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LPM` reader - Low-power Mode"] pub type LPM_R = crate::BitReader; #[doc = "Field `LPM` writer - Low-power Mode"] -pub type LPM_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type LPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FLPM` reader - Flash Low-power Mode"] pub type FLPM_R = crate::FieldReader; #[doc = "Flash Low-power Mode\n\nValue on reset: 0"] @@ -147,45 +115,49 @@ impl FLPM_R { _ => None, } } - #[doc = "Checks if the value of the field is `FLASH_STANDBY`"] + #[doc = "Flash is in Standby Mode when system enters Wait Mode"] #[inline(always)] pub fn is_flash_standby(&self) -> bool { *self == FLPMSELECT_A::FLASH_STANDBY } - #[doc = "Checks if the value of the field is `FLASH_DEEP_POWERDOWN`"] + #[doc = "Flash is in Deep-power-down mode when system enters Wait Mode"] #[inline(always)] pub fn is_flash_deep_powerdown(&self) -> bool { *self == FLPMSELECT_A::FLASH_DEEP_POWERDOWN } - #[doc = "Checks if the value of the field is `FLASH_IDLE`"] + #[doc = "Idle mode"] #[inline(always)] pub fn is_flash_idle(&self) -> bool { *self == FLPMSELECT_A::FLASH_IDLE } } #[doc = "Field `FLPM` writer - Flash Low-power Mode"] -pub type FLPM_W<'a, const O: u8> = crate::FieldWriter<'a, FSMR_SPEC, 2, O, FLPMSELECT_A>; -impl<'a, const O: u8> FLPM_W<'a, O> { +pub type FLPM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, FLPMSELECT_A>; +impl<'a, REG, const O: u8> FLPM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Flash is in Standby Mode when system enters Wait Mode"] #[inline(always)] - pub fn flash_standby(self) -> &'a mut W { + pub fn flash_standby(self) -> &'a mut crate::W { self.variant(FLPMSELECT_A::FLASH_STANDBY) } #[doc = "Flash is in Deep-power-down mode when system enters Wait Mode"] #[inline(always)] - pub fn flash_deep_powerdown(self) -> &'a mut W { + pub fn flash_deep_powerdown(self) -> &'a mut crate::W { self.variant(FLPMSELECT_A::FLASH_DEEP_POWERDOWN) } #[doc = "Idle mode"] #[inline(always)] - pub fn flash_idle(self) -> &'a mut W { + pub fn flash_idle(self) -> &'a mut crate::W { self.variant(FLPMSELECT_A::FLASH_IDLE) } } #[doc = "Field `FFLPM` reader - Force Flash Low-power Mode"] pub type FFLPM_R = crate::BitReader; #[doc = "Field `FFLPM` writer - Force Flash Low-power Mode"] -pub type FFLPM_W<'a, const O: u8> = crate::BitWriter<'a, FSMR_SPEC, O>; +pub type FFLPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Fast Startup Input Enable 0"] #[inline(always)] @@ -302,154 +274,151 @@ impl W { #[doc = "Bit 0 - Fast Startup Input Enable 0"] #[inline(always)] #[must_use] - pub fn fstt0(&mut self) -> FSTT0_W<0> { + pub fn fstt0(&mut self) -> FSTT0_W { FSTT0_W::new(self) } #[doc = "Bit 1 - Fast Startup Input Enable 1"] #[inline(always)] #[must_use] - pub fn fstt1(&mut self) -> FSTT1_W<1> { + pub fn fstt1(&mut self) -> FSTT1_W { FSTT1_W::new(self) } #[doc = "Bit 2 - Fast Startup Input Enable 2"] #[inline(always)] #[must_use] - pub fn fstt2(&mut self) -> FSTT2_W<2> { + pub fn fstt2(&mut self) -> FSTT2_W { FSTT2_W::new(self) } #[doc = "Bit 3 - Fast Startup Input Enable 3"] #[inline(always)] #[must_use] - pub fn fstt3(&mut self) -> FSTT3_W<3> { + pub fn fstt3(&mut self) -> FSTT3_W { FSTT3_W::new(self) } #[doc = "Bit 4 - Fast Startup Input Enable 4"] #[inline(always)] #[must_use] - pub fn fstt4(&mut self) -> FSTT4_W<4> { + pub fn fstt4(&mut self) -> FSTT4_W { FSTT4_W::new(self) } #[doc = "Bit 5 - Fast Startup Input Enable 5"] #[inline(always)] #[must_use] - pub fn fstt5(&mut self) -> FSTT5_W<5> { + pub fn fstt5(&mut self) -> FSTT5_W { FSTT5_W::new(self) } #[doc = "Bit 6 - Fast Startup Input Enable 6"] #[inline(always)] #[must_use] - pub fn fstt6(&mut self) -> FSTT6_W<6> { + pub fn fstt6(&mut self) -> FSTT6_W { FSTT6_W::new(self) } #[doc = "Bit 7 - Fast Startup Input Enable 7"] #[inline(always)] #[must_use] - pub fn fstt7(&mut self) -> FSTT7_W<7> { + pub fn fstt7(&mut self) -> FSTT7_W { FSTT7_W::new(self) } #[doc = "Bit 8 - Fast Startup Input Enable 8"] #[inline(always)] #[must_use] - pub fn fstt8(&mut self) -> FSTT8_W<8> { + pub fn fstt8(&mut self) -> FSTT8_W { FSTT8_W::new(self) } #[doc = "Bit 9 - Fast Startup Input Enable 9"] #[inline(always)] #[must_use] - pub fn fstt9(&mut self) -> FSTT9_W<9> { + pub fn fstt9(&mut self) -> FSTT9_W { FSTT9_W::new(self) } #[doc = "Bit 10 - Fast Startup Input Enable 10"] #[inline(always)] #[must_use] - pub fn fstt10(&mut self) -> FSTT10_W<10> { + pub fn fstt10(&mut self) -> FSTT10_W { FSTT10_W::new(self) } #[doc = "Bit 11 - Fast Startup Input Enable 11"] #[inline(always)] #[must_use] - pub fn fstt11(&mut self) -> FSTT11_W<11> { + pub fn fstt11(&mut self) -> FSTT11_W { FSTT11_W::new(self) } #[doc = "Bit 12 - Fast Startup Input Enable 12"] #[inline(always)] #[must_use] - pub fn fstt12(&mut self) -> FSTT12_W<12> { + pub fn fstt12(&mut self) -> FSTT12_W { FSTT12_W::new(self) } #[doc = "Bit 13 - Fast Startup Input Enable 13"] #[inline(always)] #[must_use] - pub fn fstt13(&mut self) -> FSTT13_W<13> { + pub fn fstt13(&mut self) -> FSTT13_W { FSTT13_W::new(self) } #[doc = "Bit 14 - Fast Startup Input Enable 14"] #[inline(always)] #[must_use] - pub fn fstt14(&mut self) -> FSTT14_W<14> { + pub fn fstt14(&mut self) -> FSTT14_W { FSTT14_W::new(self) } #[doc = "Bit 15 - Fast Startup Input Enable 15"] #[inline(always)] #[must_use] - pub fn fstt15(&mut self) -> FSTT15_W<15> { + pub fn fstt15(&mut self) -> FSTT15_W { FSTT15_W::new(self) } #[doc = "Bit 16 - RTT Alarm Enable"] #[inline(always)] #[must_use] - pub fn rttal(&mut self) -> RTTAL_W<16> { + pub fn rttal(&mut self) -> RTTAL_W { RTTAL_W::new(self) } #[doc = "Bit 17 - RTC Alarm Enable"] #[inline(always)] #[must_use] - pub fn rtcal(&mut self) -> RTCAL_W<17> { + pub fn rtcal(&mut self) -> RTCAL_W { RTCAL_W::new(self) } #[doc = "Bit 18 - USB Alarm Enable"] #[inline(always)] #[must_use] - pub fn usbal(&mut self) -> USBAL_W<18> { + pub fn usbal(&mut self) -> USBAL_W { USBAL_W::new(self) } #[doc = "Bit 20 - Low-power Mode"] #[inline(always)] #[must_use] - pub fn lpm(&mut self) -> LPM_W<20> { + pub fn lpm(&mut self) -> LPM_W { LPM_W::new(self) } #[doc = "Bits 21:22 - Flash Low-power Mode"] #[inline(always)] #[must_use] - pub fn flpm(&mut self) -> FLPM_W<21> { + pub fn flpm(&mut self) -> FLPM_W { FLPM_W::new(self) } #[doc = "Bit 23 - Force Flash Low-power Mode"] #[inline(always)] #[must_use] - pub fn fflpm(&mut self) -> FFLPM_W<23> { + pub fn fflpm(&mut self) -> FFLPM_W { FFLPM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fast Startup Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmr](index.html) module"] +#[doc = "Fast Startup Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSMR_SPEC; impl crate::RegisterSpec for FSMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fsmr::R](R) reader structure"] -impl crate::Readable for FSMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fsmr::W](W) writer structure"] +#[doc = "`read()` method returns [`fsmr::R`](R) reader structure"] +impl crate::Readable for FSMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fsmr::W`](W) writer structure"] impl crate::Writable for FSMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/fspr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/fspr.rs index f20e309c..d4935ad2 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/fspr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/fspr.rs @@ -1,103 +1,71 @@ #[doc = "Register `FSPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FSPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FSTP0` reader - Fast Startup Input Polarity 0"] pub type FSTP0_R = crate::BitReader; #[doc = "Field `FSTP0` writer - Fast Startup Input Polarity 0"] -pub type FSTP0_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP1` reader - Fast Startup Input Polarity 1"] pub type FSTP1_R = crate::BitReader; #[doc = "Field `FSTP1` writer - Fast Startup Input Polarity 1"] -pub type FSTP1_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP2` reader - Fast Startup Input Polarity 2"] pub type FSTP2_R = crate::BitReader; #[doc = "Field `FSTP2` writer - Fast Startup Input Polarity 2"] -pub type FSTP2_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP3` reader - Fast Startup Input Polarity 3"] pub type FSTP3_R = crate::BitReader; #[doc = "Field `FSTP3` writer - Fast Startup Input Polarity 3"] -pub type FSTP3_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP4` reader - Fast Startup Input Polarity 4"] pub type FSTP4_R = crate::BitReader; #[doc = "Field `FSTP4` writer - Fast Startup Input Polarity 4"] -pub type FSTP4_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP5` reader - Fast Startup Input Polarity 5"] pub type FSTP5_R = crate::BitReader; #[doc = "Field `FSTP5` writer - Fast Startup Input Polarity 5"] -pub type FSTP5_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP6` reader - Fast Startup Input Polarity 6"] pub type FSTP6_R = crate::BitReader; #[doc = "Field `FSTP6` writer - Fast Startup Input Polarity 6"] -pub type FSTP6_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP7` reader - Fast Startup Input Polarity 7"] pub type FSTP7_R = crate::BitReader; #[doc = "Field `FSTP7` writer - Fast Startup Input Polarity 7"] -pub type FSTP7_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP8` reader - Fast Startup Input Polarity 8"] pub type FSTP8_R = crate::BitReader; #[doc = "Field `FSTP8` writer - Fast Startup Input Polarity 8"] -pub type FSTP8_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP9` reader - Fast Startup Input Polarity 9"] pub type FSTP9_R = crate::BitReader; #[doc = "Field `FSTP9` writer - Fast Startup Input Polarity 9"] -pub type FSTP9_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP10` reader - Fast Startup Input Polarity 10"] pub type FSTP10_R = crate::BitReader; #[doc = "Field `FSTP10` writer - Fast Startup Input Polarity 10"] -pub type FSTP10_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP11` reader - Fast Startup Input Polarity 11"] pub type FSTP11_R = crate::BitReader; #[doc = "Field `FSTP11` writer - Fast Startup Input Polarity 11"] -pub type FSTP11_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP12` reader - Fast Startup Input Polarity 12"] pub type FSTP12_R = crate::BitReader; #[doc = "Field `FSTP12` writer - Fast Startup Input Polarity 12"] -pub type FSTP12_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP13` reader - Fast Startup Input Polarity 13"] pub type FSTP13_R = crate::BitReader; #[doc = "Field `FSTP13` writer - Fast Startup Input Polarity 13"] -pub type FSTP13_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP14` reader - Fast Startup Input Polarity 14"] pub type FSTP14_R = crate::BitReader; #[doc = "Field `FSTP14` writer - Fast Startup Input Polarity 14"] -pub type FSTP14_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSTP15` reader - Fast Startup Input Polarity 15"] pub type FSTP15_R = crate::BitReader; #[doc = "Field `FSTP15` writer - Fast Startup Input Polarity 15"] -pub type FSTP15_W<'a, const O: u8> = crate::BitWriter<'a, FSPR_SPEC, O>; +pub type FSTP15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Fast Startup Input Polarity 0"] #[inline(always)] @@ -184,118 +152,115 @@ impl W { #[doc = "Bit 0 - Fast Startup Input Polarity 0"] #[inline(always)] #[must_use] - pub fn fstp0(&mut self) -> FSTP0_W<0> { + pub fn fstp0(&mut self) -> FSTP0_W { FSTP0_W::new(self) } #[doc = "Bit 1 - Fast Startup Input Polarity 1"] #[inline(always)] #[must_use] - pub fn fstp1(&mut self) -> FSTP1_W<1> { + pub fn fstp1(&mut self) -> FSTP1_W { FSTP1_W::new(self) } #[doc = "Bit 2 - Fast Startup Input Polarity 2"] #[inline(always)] #[must_use] - pub fn fstp2(&mut self) -> FSTP2_W<2> { + pub fn fstp2(&mut self) -> FSTP2_W { FSTP2_W::new(self) } #[doc = "Bit 3 - Fast Startup Input Polarity 3"] #[inline(always)] #[must_use] - pub fn fstp3(&mut self) -> FSTP3_W<3> { + pub fn fstp3(&mut self) -> FSTP3_W { FSTP3_W::new(self) } #[doc = "Bit 4 - Fast Startup Input Polarity 4"] #[inline(always)] #[must_use] - pub fn fstp4(&mut self) -> FSTP4_W<4> { + pub fn fstp4(&mut self) -> FSTP4_W { FSTP4_W::new(self) } #[doc = "Bit 5 - Fast Startup Input Polarity 5"] #[inline(always)] #[must_use] - pub fn fstp5(&mut self) -> FSTP5_W<5> { + pub fn fstp5(&mut self) -> FSTP5_W { FSTP5_W::new(self) } #[doc = "Bit 6 - Fast Startup Input Polarity 6"] #[inline(always)] #[must_use] - pub fn fstp6(&mut self) -> FSTP6_W<6> { + pub fn fstp6(&mut self) -> FSTP6_W { FSTP6_W::new(self) } #[doc = "Bit 7 - Fast Startup Input Polarity 7"] #[inline(always)] #[must_use] - pub fn fstp7(&mut self) -> FSTP7_W<7> { + pub fn fstp7(&mut self) -> FSTP7_W { FSTP7_W::new(self) } #[doc = "Bit 8 - Fast Startup Input Polarity 8"] #[inline(always)] #[must_use] - pub fn fstp8(&mut self) -> FSTP8_W<8> { + pub fn fstp8(&mut self) -> FSTP8_W { FSTP8_W::new(self) } #[doc = "Bit 9 - Fast Startup Input Polarity 9"] #[inline(always)] #[must_use] - pub fn fstp9(&mut self) -> FSTP9_W<9> { + pub fn fstp9(&mut self) -> FSTP9_W { FSTP9_W::new(self) } #[doc = "Bit 10 - Fast Startup Input Polarity 10"] #[inline(always)] #[must_use] - pub fn fstp10(&mut self) -> FSTP10_W<10> { + pub fn fstp10(&mut self) -> FSTP10_W { FSTP10_W::new(self) } #[doc = "Bit 11 - Fast Startup Input Polarity 11"] #[inline(always)] #[must_use] - pub fn fstp11(&mut self) -> FSTP11_W<11> { + pub fn fstp11(&mut self) -> FSTP11_W { FSTP11_W::new(self) } #[doc = "Bit 12 - Fast Startup Input Polarity 12"] #[inline(always)] #[must_use] - pub fn fstp12(&mut self) -> FSTP12_W<12> { + pub fn fstp12(&mut self) -> FSTP12_W { FSTP12_W::new(self) } #[doc = "Bit 13 - Fast Startup Input Polarity 13"] #[inline(always)] #[must_use] - pub fn fstp13(&mut self) -> FSTP13_W<13> { + pub fn fstp13(&mut self) -> FSTP13_W { FSTP13_W::new(self) } #[doc = "Bit 14 - Fast Startup Input Polarity 14"] #[inline(always)] #[must_use] - pub fn fstp14(&mut self) -> FSTP14_W<14> { + pub fn fstp14(&mut self) -> FSTP14_W { FSTP14_W::new(self) } #[doc = "Bit 15 - Fast Startup Input Polarity 15"] #[inline(always)] #[must_use] - pub fn fstp15(&mut self) -> FSTP15_W<15> { + pub fn fstp15(&mut self) -> FSTP15_W { FSTP15_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fast Startup Polarity Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fspr](index.html) module"] +#[doc = "Fast Startup Polarity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fspr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fspr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSPR_SPEC; impl crate::RegisterSpec for FSPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fspr::R](R) reader structure"] -impl crate::Readable for FSPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fspr::W](W) writer structure"] +#[doc = "`read()` method returns [`fspr::R`](R) reader structure"] +impl crate::Readable for FSPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fspr::W`](W) writer structure"] impl crate::Writable for FSPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/idr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/idr.rs index c3280cc5..64ef3fee 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/idr.rs @@ -1,168 +1,148 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MOSCXTS` writer - Main Crystal Oscillator Status Interrupt Disable"] -pub type MOSCXTS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MOSCXTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCKA` writer - PLLA Lock Interrupt Disable"] -pub type LOCKA_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type LOCKA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MCKRDY` writer - Master Clock Ready Interrupt Disable"] -pub type MCKRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MCKRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCKU` writer - UTMI PLL Lock Interrupt Disable"] -pub type LOCKU_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type LOCKU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY0` writer - Programmable Clock Ready 0 Interrupt Disable"] -pub type PCKRDY0_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY1` writer - Programmable Clock Ready 1 Interrupt Disable"] -pub type PCKRDY1_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY2` writer - Programmable Clock Ready 2 Interrupt Disable"] -pub type PCKRDY2_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY3` writer - Programmable Clock Ready 3 Interrupt Disable"] -pub type PCKRDY3_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY4` writer - Programmable Clock Ready 4 Interrupt Disable"] -pub type PCKRDY4_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY5` writer - Programmable Clock Ready 5 Interrupt Disable"] -pub type PCKRDY5_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY6` writer - Programmable Clock Ready 6 Interrupt Disable"] -pub type PCKRDY6_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY7` writer - Programmable Clock Ready 7 Interrupt Disable"] -pub type PCKRDY7_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PCKRDY7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCSELS` writer - Main Clock Source Oscillator Selection Status Interrupt Disable"] -pub type MOSCSELS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MOSCSELS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCRCS` writer - Main RC Status Interrupt Disable"] -pub type MOSCRCS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MOSCRCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFDEV` writer - Clock Failure Detector Event Interrupt Disable"] -pub type CFDEV_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CFDEV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `XT32KERR` writer - 32.768 kHz Crystal Oscillator Error Interrupt Disable"] -pub type XT32KERR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type XT32KERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Main Crystal Oscillator Status Interrupt Disable"] #[inline(always)] #[must_use] - pub fn moscxts(&mut self) -> MOSCXTS_W<0> { + pub fn moscxts(&mut self) -> MOSCXTS_W { MOSCXTS_W::new(self) } #[doc = "Bit 1 - PLLA Lock Interrupt Disable"] #[inline(always)] #[must_use] - pub fn locka(&mut self) -> LOCKA_W<1> { + pub fn locka(&mut self) -> LOCKA_W { LOCKA_W::new(self) } #[doc = "Bit 3 - Master Clock Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn mckrdy(&mut self) -> MCKRDY_W<3> { + pub fn mckrdy(&mut self) -> MCKRDY_W { MCKRDY_W::new(self) } #[doc = "Bit 6 - UTMI PLL Lock Interrupt Disable"] #[inline(always)] #[must_use] - pub fn locku(&mut self) -> LOCKU_W<6> { + pub fn locku(&mut self) -> LOCKU_W { LOCKU_W::new(self) } #[doc = "Bit 8 - Programmable Clock Ready 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy0(&mut self) -> PCKRDY0_W<8> { + pub fn pckrdy0(&mut self) -> PCKRDY0_W { PCKRDY0_W::new(self) } #[doc = "Bit 9 - Programmable Clock Ready 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy1(&mut self) -> PCKRDY1_W<9> { + pub fn pckrdy1(&mut self) -> PCKRDY1_W { PCKRDY1_W::new(self) } #[doc = "Bit 10 - Programmable Clock Ready 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy2(&mut self) -> PCKRDY2_W<10> { + pub fn pckrdy2(&mut self) -> PCKRDY2_W { PCKRDY2_W::new(self) } #[doc = "Bit 11 - Programmable Clock Ready 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy3(&mut self) -> PCKRDY3_W<11> { + pub fn pckrdy3(&mut self) -> PCKRDY3_W { PCKRDY3_W::new(self) } #[doc = "Bit 12 - Programmable Clock Ready 4 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy4(&mut self) -> PCKRDY4_W<12> { + pub fn pckrdy4(&mut self) -> PCKRDY4_W { PCKRDY4_W::new(self) } #[doc = "Bit 13 - Programmable Clock Ready 5 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy5(&mut self) -> PCKRDY5_W<13> { + pub fn pckrdy5(&mut self) -> PCKRDY5_W { PCKRDY5_W::new(self) } #[doc = "Bit 14 - Programmable Clock Ready 6 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy6(&mut self) -> PCKRDY6_W<14> { + pub fn pckrdy6(&mut self) -> PCKRDY6_W { PCKRDY6_W::new(self) } #[doc = "Bit 15 - Programmable Clock Ready 7 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pckrdy7(&mut self) -> PCKRDY7_W<15> { + pub fn pckrdy7(&mut self) -> PCKRDY7_W { PCKRDY7_W::new(self) } #[doc = "Bit 16 - Main Clock Source Oscillator Selection Status Interrupt Disable"] #[inline(always)] #[must_use] - pub fn moscsels(&mut self) -> MOSCSELS_W<16> { + pub fn moscsels(&mut self) -> MOSCSELS_W { MOSCSELS_W::new(self) } #[doc = "Bit 17 - Main RC Status Interrupt Disable"] #[inline(always)] #[must_use] - pub fn moscrcs(&mut self) -> MOSCRCS_W<17> { + pub fn moscrcs(&mut self) -> MOSCRCS_W { MOSCRCS_W::new(self) } #[doc = "Bit 18 - Clock Failure Detector Event Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cfdev(&mut self) -> CFDEV_W<18> { + pub fn cfdev(&mut self) -> CFDEV_W { CFDEV_W::new(self) } #[doc = "Bit 21 - 32.768 kHz Crystal Oscillator Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn xt32kerr(&mut self) -> XT32KERR_W<21> { + pub fn xt32kerr(&mut self) -> XT32KERR_W { XT32KERR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/ier.rs b/arch/cortex-m/samv71q21-pac/src/pmc/ier.rs index 061874ea..6fe609f8 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/ier.rs @@ -1,168 +1,148 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MOSCXTS` writer - Main Crystal Oscillator Status Interrupt Enable"] -pub type MOSCXTS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MOSCXTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCKA` writer - PLLA Lock Interrupt Enable"] -pub type LOCKA_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type LOCKA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MCKRDY` writer - Master Clock Ready Interrupt Enable"] -pub type MCKRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MCKRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCKU` writer - UTMI PLL Lock Interrupt Enable"] -pub type LOCKU_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type LOCKU_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY0` writer - Programmable Clock Ready 0 Interrupt Enable"] -pub type PCKRDY0_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY1` writer - Programmable Clock Ready 1 Interrupt Enable"] -pub type PCKRDY1_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY2` writer - Programmable Clock Ready 2 Interrupt Enable"] -pub type PCKRDY2_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY3` writer - Programmable Clock Ready 3 Interrupt Enable"] -pub type PCKRDY3_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY4` writer - Programmable Clock Ready 4 Interrupt Enable"] -pub type PCKRDY4_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY5` writer - Programmable Clock Ready 5 Interrupt Enable"] -pub type PCKRDY5_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY6` writer - Programmable Clock Ready 6 Interrupt Enable"] -pub type PCKRDY6_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCKRDY7` writer - Programmable Clock Ready 7 Interrupt Enable"] -pub type PCKRDY7_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PCKRDY7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCSELS` writer - Main Clock Source Oscillator Selection Status Interrupt Enable"] -pub type MOSCSELS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MOSCSELS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MOSCRCS` writer - Main RC Oscillator Status Interrupt Enable"] -pub type MOSCRCS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MOSCRCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CFDEV` writer - Clock Failure Detector Event Interrupt Enable"] -pub type CFDEV_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CFDEV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `XT32KERR` writer - 32.768 kHz Crystal Oscillator Error Interrupt Enable"] -pub type XT32KERR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type XT32KERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Main Crystal Oscillator Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn moscxts(&mut self) -> MOSCXTS_W<0> { + pub fn moscxts(&mut self) -> MOSCXTS_W { MOSCXTS_W::new(self) } #[doc = "Bit 1 - PLLA Lock Interrupt Enable"] #[inline(always)] #[must_use] - pub fn locka(&mut self) -> LOCKA_W<1> { + pub fn locka(&mut self) -> LOCKA_W { LOCKA_W::new(self) } #[doc = "Bit 3 - Master Clock Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn mckrdy(&mut self) -> MCKRDY_W<3> { + pub fn mckrdy(&mut self) -> MCKRDY_W { MCKRDY_W::new(self) } #[doc = "Bit 6 - UTMI PLL Lock Interrupt Enable"] #[inline(always)] #[must_use] - pub fn locku(&mut self) -> LOCKU_W<6> { + pub fn locku(&mut self) -> LOCKU_W { LOCKU_W::new(self) } #[doc = "Bit 8 - Programmable Clock Ready 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy0(&mut self) -> PCKRDY0_W<8> { + pub fn pckrdy0(&mut self) -> PCKRDY0_W { PCKRDY0_W::new(self) } #[doc = "Bit 9 - Programmable Clock Ready 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy1(&mut self) -> PCKRDY1_W<9> { + pub fn pckrdy1(&mut self) -> PCKRDY1_W { PCKRDY1_W::new(self) } #[doc = "Bit 10 - Programmable Clock Ready 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy2(&mut self) -> PCKRDY2_W<10> { + pub fn pckrdy2(&mut self) -> PCKRDY2_W { PCKRDY2_W::new(self) } #[doc = "Bit 11 - Programmable Clock Ready 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy3(&mut self) -> PCKRDY3_W<11> { + pub fn pckrdy3(&mut self) -> PCKRDY3_W { PCKRDY3_W::new(self) } #[doc = "Bit 12 - Programmable Clock Ready 4 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy4(&mut self) -> PCKRDY4_W<12> { + pub fn pckrdy4(&mut self) -> PCKRDY4_W { PCKRDY4_W::new(self) } #[doc = "Bit 13 - Programmable Clock Ready 5 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy5(&mut self) -> PCKRDY5_W<13> { + pub fn pckrdy5(&mut self) -> PCKRDY5_W { PCKRDY5_W::new(self) } #[doc = "Bit 14 - Programmable Clock Ready 6 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy6(&mut self) -> PCKRDY6_W<14> { + pub fn pckrdy6(&mut self) -> PCKRDY6_W { PCKRDY6_W::new(self) } #[doc = "Bit 15 - Programmable Clock Ready 7 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pckrdy7(&mut self) -> PCKRDY7_W<15> { + pub fn pckrdy7(&mut self) -> PCKRDY7_W { PCKRDY7_W::new(self) } #[doc = "Bit 16 - Main Clock Source Oscillator Selection Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn moscsels(&mut self) -> MOSCSELS_W<16> { + pub fn moscsels(&mut self) -> MOSCSELS_W { MOSCSELS_W::new(self) } #[doc = "Bit 17 - Main RC Oscillator Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn moscrcs(&mut self) -> MOSCRCS_W<17> { + pub fn moscrcs(&mut self) -> MOSCRCS_W { MOSCRCS_W::new(self) } #[doc = "Bit 18 - Clock Failure Detector Event Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cfdev(&mut self) -> CFDEV_W<18> { + pub fn cfdev(&mut self) -> CFDEV_W { CFDEV_W::new(self) } #[doc = "Bit 21 - 32.768 kHz Crystal Oscillator Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn xt32kerr(&mut self) -> XT32KERR_W<21> { + pub fn xt32kerr(&mut self) -> XT32KERR_W { XT32KERR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/imr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/imr.rs index bf6cda12..8ed1a13f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MOSCXTS` reader - Main Crystal Oscillator Status Interrupt Mask"] pub type MOSCXTS_R = crate::BitReader; #[doc = "Field `LOCKA` reader - PLLA Lock Interrupt Mask"] @@ -127,15 +114,13 @@ impl R { XT32KERR_R::new(((self.bits >> 21) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/mckr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/mckr.rs index d11856c6..db5d91d9 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/mckr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/mckr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MCKR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MCKR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSS` reader - Master Clock Source Selection"] pub type CSS_R = crate::FieldReader; #[doc = "Master Clock Source Selection\n\nValue on reset: 0"] @@ -70,48 +38,52 @@ impl CSS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SLOW_CLK`"] + #[doc = "Slow Clock is selected"] #[inline(always)] pub fn is_slow_clk(&self) -> bool { *self == CSSSELECT_A::SLOW_CLK } - #[doc = "Checks if the value of the field is `MAIN_CLK`"] + #[doc = "Main Clock is selected"] #[inline(always)] pub fn is_main_clk(&self) -> bool { *self == CSSSELECT_A::MAIN_CLK } - #[doc = "Checks if the value of the field is `PLLA_CLK`"] + #[doc = "PLLA Clock is selected"] #[inline(always)] pub fn is_plla_clk(&self) -> bool { *self == CSSSELECT_A::PLLA_CLK } - #[doc = "Checks if the value of the field is `UPLL_CLK`"] + #[doc = "Divided UPLL Clock is selected"] #[inline(always)] pub fn is_upll_clk(&self) -> bool { *self == CSSSELECT_A::UPLL_CLK } } #[doc = "Field `CSS` writer - Master Clock Source Selection"] -pub type CSS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MCKR_SPEC, 2, O, CSSSELECT_A>; -impl<'a, const O: u8> CSS_W<'a, O> { +pub type CSS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CSSSELECT_A>; +impl<'a, REG, const O: u8> CSS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Slow Clock is selected"] #[inline(always)] - pub fn slow_clk(self) -> &'a mut W { + pub fn slow_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::SLOW_CLK) } #[doc = "Main Clock is selected"] #[inline(always)] - pub fn main_clk(self) -> &'a mut W { + pub fn main_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::MAIN_CLK) } #[doc = "PLLA Clock is selected"] #[inline(always)] - pub fn plla_clk(self) -> &'a mut W { + pub fn plla_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::PLLA_CLK) } #[doc = "Divided UPLL Clock is selected"] #[inline(always)] - pub fn upll_clk(self) -> &'a mut W { + pub fn upll_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::UPLL_CLK) } } @@ -163,88 +135,92 @@ impl PRES_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CLK_1`"] + #[doc = "Selected clock"] #[inline(always)] pub fn is_clk_1(&self) -> bool { *self == PRESSELECT_A::CLK_1 } - #[doc = "Checks if the value of the field is `CLK_2`"] + #[doc = "Selected clock divided by 2"] #[inline(always)] pub fn is_clk_2(&self) -> bool { *self == PRESSELECT_A::CLK_2 } - #[doc = "Checks if the value of the field is `CLK_4`"] + #[doc = "Selected clock divided by 4"] #[inline(always)] pub fn is_clk_4(&self) -> bool { *self == PRESSELECT_A::CLK_4 } - #[doc = "Checks if the value of the field is `CLK_8`"] + #[doc = "Selected clock divided by 8"] #[inline(always)] pub fn is_clk_8(&self) -> bool { *self == PRESSELECT_A::CLK_8 } - #[doc = "Checks if the value of the field is `CLK_16`"] + #[doc = "Selected clock divided by 16"] #[inline(always)] pub fn is_clk_16(&self) -> bool { *self == PRESSELECT_A::CLK_16 } - #[doc = "Checks if the value of the field is `CLK_32`"] + #[doc = "Selected clock divided by 32"] #[inline(always)] pub fn is_clk_32(&self) -> bool { *self == PRESSELECT_A::CLK_32 } - #[doc = "Checks if the value of the field is `CLK_64`"] + #[doc = "Selected clock divided by 64"] #[inline(always)] pub fn is_clk_64(&self) -> bool { *self == PRESSELECT_A::CLK_64 } - #[doc = "Checks if the value of the field is `CLK_3`"] + #[doc = "Selected clock divided by 3"] #[inline(always)] pub fn is_clk_3(&self) -> bool { *self == PRESSELECT_A::CLK_3 } } #[doc = "Field `PRES` writer - Processor Clock Prescaler"] -pub type PRES_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MCKR_SPEC, 3, O, PRESSELECT_A>; -impl<'a, const O: u8> PRES_W<'a, O> { +pub type PRES_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, PRESSELECT_A>; +impl<'a, REG, const O: u8> PRES_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Selected clock"] #[inline(always)] - pub fn clk_1(self) -> &'a mut W { + pub fn clk_1(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_1) } #[doc = "Selected clock divided by 2"] #[inline(always)] - pub fn clk_2(self) -> &'a mut W { + pub fn clk_2(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_2) } #[doc = "Selected clock divided by 4"] #[inline(always)] - pub fn clk_4(self) -> &'a mut W { + pub fn clk_4(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_4) } #[doc = "Selected clock divided by 8"] #[inline(always)] - pub fn clk_8(self) -> &'a mut W { + pub fn clk_8(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_8) } #[doc = "Selected clock divided by 16"] #[inline(always)] - pub fn clk_16(self) -> &'a mut W { + pub fn clk_16(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_16) } #[doc = "Selected clock divided by 32"] #[inline(always)] - pub fn clk_32(self) -> &'a mut W { + pub fn clk_32(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_32) } #[doc = "Selected clock divided by 64"] #[inline(always)] - pub fn clk_64(self) -> &'a mut W { + pub fn clk_64(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_64) } #[doc = "Selected clock divided by 3"] #[inline(always)] - pub fn clk_3(self) -> &'a mut W { + pub fn clk_3(self) -> &'a mut crate::W { self.variant(PRESSELECT_A::CLK_3) } } @@ -284,55 +260,59 @@ impl MDIV_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `EQ_PCK`"] + #[doc = "Master Clock is Prescaler Output Clock divided by 1."] #[inline(always)] pub fn is_eq_pck(&self) -> bool { *self == MDIVSELECT_A::EQ_PCK } - #[doc = "Checks if the value of the field is `PCK_DIV2`"] + #[doc = "Master Clock is Prescaler Output Clock divided by 2."] #[inline(always)] pub fn is_pck_div2(&self) -> bool { *self == MDIVSELECT_A::PCK_DIV2 } - #[doc = "Checks if the value of the field is `PCK_DIV4`"] + #[doc = "Master Clock is Prescaler Output Clock divided by 4."] #[inline(always)] pub fn is_pck_div4(&self) -> bool { *self == MDIVSELECT_A::PCK_DIV4 } - #[doc = "Checks if the value of the field is `PCK_DIV3`"] + #[doc = "Master Clock is Prescaler Output Clock divided by 3."] #[inline(always)] pub fn is_pck_div3(&self) -> bool { *self == MDIVSELECT_A::PCK_DIV3 } } #[doc = "Field `MDIV` writer - Master Clock Division"] -pub type MDIV_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MCKR_SPEC, 2, O, MDIVSELECT_A>; -impl<'a, const O: u8> MDIV_W<'a, O> { +pub type MDIV_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, MDIVSELECT_A>; +impl<'a, REG, const O: u8> MDIV_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Master Clock is Prescaler Output Clock divided by 1."] #[inline(always)] - pub fn eq_pck(self) -> &'a mut W { + pub fn eq_pck(self) -> &'a mut crate::W { self.variant(MDIVSELECT_A::EQ_PCK) } #[doc = "Master Clock is Prescaler Output Clock divided by 2."] #[inline(always)] - pub fn pck_div2(self) -> &'a mut W { + pub fn pck_div2(self) -> &'a mut crate::W { self.variant(MDIVSELECT_A::PCK_DIV2) } #[doc = "Master Clock is Prescaler Output Clock divided by 4."] #[inline(always)] - pub fn pck_div4(self) -> &'a mut W { + pub fn pck_div4(self) -> &'a mut crate::W { self.variant(MDIVSELECT_A::PCK_DIV4) } #[doc = "Master Clock is Prescaler Output Clock divided by 3."] #[inline(always)] - pub fn pck_div3(self) -> &'a mut W { + pub fn pck_div3(self) -> &'a mut crate::W { self.variant(MDIVSELECT_A::PCK_DIV3) } } #[doc = "Field `UPLLDIV2` reader - UPLL Divider by 2"] pub type UPLLDIV2_R = crate::BitReader; #[doc = "Field `UPLLDIV2` writer - UPLL Divider by 2"] -pub type UPLLDIV2_W<'a, const O: u8> = crate::BitWriter<'a, MCKR_SPEC, O>; +pub type UPLLDIV2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Master Clock Source Selection"] #[inline(always)] @@ -359,46 +339,43 @@ impl W { #[doc = "Bits 0:1 - Master Clock Source Selection"] #[inline(always)] #[must_use] - pub fn css(&mut self) -> CSS_W<0> { + pub fn css(&mut self) -> CSS_W { CSS_W::new(self) } #[doc = "Bits 4:6 - Processor Clock Prescaler"] #[inline(always)] #[must_use] - pub fn pres(&mut self) -> PRES_W<4> { + pub fn pres(&mut self) -> PRES_W { PRES_W::new(self) } #[doc = "Bits 8:9 - Master Clock Division"] #[inline(always)] #[must_use] - pub fn mdiv(&mut self) -> MDIV_W<8> { + pub fn mdiv(&mut self) -> MDIV_W { MDIV_W::new(self) } #[doc = "Bit 13 - UPLL Divider by 2"] #[inline(always)] #[must_use] - pub fn uplldiv2(&mut self) -> UPLLDIV2_W<13> { + pub fn uplldiv2(&mut self) -> UPLLDIV2_W { UPLLDIV2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Master Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mckr](index.html) module"] +#[doc = "Master Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mckr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mckr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MCKR_SPEC; impl crate::RegisterSpec for MCKR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mckr::R](R) reader structure"] -impl crate::Readable for MCKR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mckr::W](W) writer structure"] +#[doc = "`read()` method returns [`mckr::R`](R) reader structure"] +impl crate::Readable for MCKR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mckr::W`](W) writer structure"] impl crate::Writable for MCKR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/ocr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/ocr.rs index fcb3da9e..f236d4d1 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/ocr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/ocr.rs @@ -1,63 +1,31 @@ #[doc = "Register `OCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `OCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CAL4` reader - Main RC Oscillator Calibration Bits for 4 MHz"] pub type CAL4_R = crate::FieldReader; #[doc = "Field `CAL4` writer - Main RC Oscillator Calibration Bits for 4 MHz"] -pub type CAL4_W<'a, const O: u8> = crate::FieldWriter<'a, OCR_SPEC, 7, O>; +pub type CAL4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SEL4` reader - Selection of Main RC Oscillator Calibration Bits for 4 MHz"] pub type SEL4_R = crate::BitReader; #[doc = "Field `SEL4` writer - Selection of Main RC Oscillator Calibration Bits for 4 MHz"] -pub type SEL4_W<'a, const O: u8> = crate::BitWriter<'a, OCR_SPEC, O>; +pub type SEL4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAL8` reader - Main RC Oscillator Calibration Bits for 8 MHz"] pub type CAL8_R = crate::FieldReader; #[doc = "Field `CAL8` writer - Main RC Oscillator Calibration Bits for 8 MHz"] -pub type CAL8_W<'a, const O: u8> = crate::FieldWriter<'a, OCR_SPEC, 7, O>; +pub type CAL8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SEL8` reader - Selection of Main RC Oscillator Calibration Bits for 8 MHz"] pub type SEL8_R = crate::BitReader; #[doc = "Field `SEL8` writer - Selection of Main RC Oscillator Calibration Bits for 8 MHz"] -pub type SEL8_W<'a, const O: u8> = crate::BitWriter<'a, OCR_SPEC, O>; +pub type SEL8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CAL12` reader - Main RC Oscillator Calibration Bits for 12 MHz"] pub type CAL12_R = crate::FieldReader; #[doc = "Field `CAL12` writer - Main RC Oscillator Calibration Bits for 12 MHz"] -pub type CAL12_W<'a, const O: u8> = crate::FieldWriter<'a, OCR_SPEC, 7, O>; +pub type CAL12_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SEL12` reader - Selection of Main RC Oscillator Calibration Bits for 12 MHz"] pub type SEL12_R = crate::BitReader; #[doc = "Field `SEL12` writer - Selection of Main RC Oscillator Calibration Bits for 12 MHz"] -pub type SEL12_W<'a, const O: u8> = crate::BitWriter<'a, OCR_SPEC, O>; +pub type SEL12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Main RC Oscillator Calibration Bits for 4 MHz"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bits 0:6 - Main RC Oscillator Calibration Bits for 4 MHz"] #[inline(always)] #[must_use] - pub fn cal4(&mut self) -> CAL4_W<0> { + pub fn cal4(&mut self) -> CAL4_W { CAL4_W::new(self) } #[doc = "Bit 7 - Selection of Main RC Oscillator Calibration Bits for 4 MHz"] #[inline(always)] #[must_use] - pub fn sel4(&mut self) -> SEL4_W<7> { + pub fn sel4(&mut self) -> SEL4_W { SEL4_W::new(self) } #[doc = "Bits 8:14 - Main RC Oscillator Calibration Bits for 8 MHz"] #[inline(always)] #[must_use] - pub fn cal8(&mut self) -> CAL8_W<8> { + pub fn cal8(&mut self) -> CAL8_W { CAL8_W::new(self) } #[doc = "Bit 15 - Selection of Main RC Oscillator Calibration Bits for 8 MHz"] #[inline(always)] #[must_use] - pub fn sel8(&mut self) -> SEL8_W<15> { + pub fn sel8(&mut self) -> SEL8_W { SEL8_W::new(self) } #[doc = "Bits 16:22 - Main RC Oscillator Calibration Bits for 12 MHz"] #[inline(always)] #[must_use] - pub fn cal12(&mut self) -> CAL12_W<16> { + pub fn cal12(&mut self) -> CAL12_W { CAL12_W::new(self) } #[doc = "Bit 23 - Selection of Main RC Oscillator Calibration Bits for 12 MHz"] #[inline(always)] #[must_use] - pub fn sel12(&mut self) -> SEL12_W<23> { + pub fn sel12(&mut self) -> SEL12_W { SEL12_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Oscillator Calibration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ocr](index.html) module"] +#[doc = "Oscillator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ocr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ocr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OCR_SPEC; impl crate::RegisterSpec for OCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ocr::R](R) reader structure"] -impl crate::Readable for OCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ocr::W](W) writer structure"] +#[doc = "`read()` method returns [`ocr::R`](R) reader structure"] +impl crate::Readable for OCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ocr::W`](W) writer structure"] impl crate::Writable for OCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcdr0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcdr0.rs index 54ecc78e..47ced180 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcdr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcdr0.rs @@ -1,240 +1,220 @@ #[doc = "Register `PCDR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID7` writer - Peripheral Clock 7 Disable"] -pub type PID7_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID8` writer - Peripheral Clock 8 Disable"] -pub type PID8_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID9` writer - Peripheral Clock 9 Disable"] -pub type PID9_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID10` writer - Peripheral Clock 10 Disable"] -pub type PID10_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID11` writer - Peripheral Clock 11 Disable"] -pub type PID11_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID12` writer - Peripheral Clock 12 Disable"] -pub type PID12_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID13` writer - Peripheral Clock 13 Disable"] -pub type PID13_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID14` writer - Peripheral Clock 14 Disable"] -pub type PID14_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID15` writer - Peripheral Clock 15 Disable"] -pub type PID15_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID16` writer - Peripheral Clock 16 Disable"] -pub type PID16_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID17` writer - Peripheral Clock 17 Disable"] -pub type PID17_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID18` writer - Peripheral Clock 18 Disable"] -pub type PID18_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID19` writer - Peripheral Clock 19 Disable"] -pub type PID19_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID20` writer - Peripheral Clock 20 Disable"] -pub type PID20_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID21` writer - Peripheral Clock 21 Disable"] -pub type PID21_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID22` writer - Peripheral Clock 22 Disable"] -pub type PID22_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID23` writer - Peripheral Clock 23 Disable"] -pub type PID23_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID24` writer - Peripheral Clock 24 Disable"] -pub type PID24_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID25` writer - Peripheral Clock 25 Disable"] -pub type PID25_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID26` writer - Peripheral Clock 26 Disable"] -pub type PID26_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID27` writer - Peripheral Clock 27 Disable"] -pub type PID27_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID28` writer - Peripheral Clock 28 Disable"] -pub type PID28_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID29` writer - Peripheral Clock 29 Disable"] -pub type PID29_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID30` writer - Peripheral Clock 30 Disable"] -pub type PID30_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID31` writer - Peripheral Clock 31 Disable"] -pub type PID31_W<'a, const O: u8> = crate::BitWriter<'a, PCDR0_SPEC, O>; +pub type PID31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 7 - Peripheral Clock 7 Disable"] #[inline(always)] #[must_use] - pub fn pid7(&mut self) -> PID7_W<7> { + pub fn pid7(&mut self) -> PID7_W { PID7_W::new(self) } #[doc = "Bit 8 - Peripheral Clock 8 Disable"] #[inline(always)] #[must_use] - pub fn pid8(&mut self) -> PID8_W<8> { + pub fn pid8(&mut self) -> PID8_W { PID8_W::new(self) } #[doc = "Bit 9 - Peripheral Clock 9 Disable"] #[inline(always)] #[must_use] - pub fn pid9(&mut self) -> PID9_W<9> { + pub fn pid9(&mut self) -> PID9_W { PID9_W::new(self) } #[doc = "Bit 10 - Peripheral Clock 10 Disable"] #[inline(always)] #[must_use] - pub fn pid10(&mut self) -> PID10_W<10> { + pub fn pid10(&mut self) -> PID10_W { PID10_W::new(self) } #[doc = "Bit 11 - Peripheral Clock 11 Disable"] #[inline(always)] #[must_use] - pub fn pid11(&mut self) -> PID11_W<11> { + pub fn pid11(&mut self) -> PID11_W { PID11_W::new(self) } #[doc = "Bit 12 - Peripheral Clock 12 Disable"] #[inline(always)] #[must_use] - pub fn pid12(&mut self) -> PID12_W<12> { + pub fn pid12(&mut self) -> PID12_W { PID12_W::new(self) } #[doc = "Bit 13 - Peripheral Clock 13 Disable"] #[inline(always)] #[must_use] - pub fn pid13(&mut self) -> PID13_W<13> { + pub fn pid13(&mut self) -> PID13_W { PID13_W::new(self) } #[doc = "Bit 14 - Peripheral Clock 14 Disable"] #[inline(always)] #[must_use] - pub fn pid14(&mut self) -> PID14_W<14> { + pub fn pid14(&mut self) -> PID14_W { PID14_W::new(self) } #[doc = "Bit 15 - Peripheral Clock 15 Disable"] #[inline(always)] #[must_use] - pub fn pid15(&mut self) -> PID15_W<15> { + pub fn pid15(&mut self) -> PID15_W { PID15_W::new(self) } #[doc = "Bit 16 - Peripheral Clock 16 Disable"] #[inline(always)] #[must_use] - pub fn pid16(&mut self) -> PID16_W<16> { + pub fn pid16(&mut self) -> PID16_W { PID16_W::new(self) } #[doc = "Bit 17 - Peripheral Clock 17 Disable"] #[inline(always)] #[must_use] - pub fn pid17(&mut self) -> PID17_W<17> { + pub fn pid17(&mut self) -> PID17_W { PID17_W::new(self) } #[doc = "Bit 18 - Peripheral Clock 18 Disable"] #[inline(always)] #[must_use] - pub fn pid18(&mut self) -> PID18_W<18> { + pub fn pid18(&mut self) -> PID18_W { PID18_W::new(self) } #[doc = "Bit 19 - Peripheral Clock 19 Disable"] #[inline(always)] #[must_use] - pub fn pid19(&mut self) -> PID19_W<19> { + pub fn pid19(&mut self) -> PID19_W { PID19_W::new(self) } #[doc = "Bit 20 - Peripheral Clock 20 Disable"] #[inline(always)] #[must_use] - pub fn pid20(&mut self) -> PID20_W<20> { + pub fn pid20(&mut self) -> PID20_W { PID20_W::new(self) } #[doc = "Bit 21 - Peripheral Clock 21 Disable"] #[inline(always)] #[must_use] - pub fn pid21(&mut self) -> PID21_W<21> { + pub fn pid21(&mut self) -> PID21_W { PID21_W::new(self) } #[doc = "Bit 22 - Peripheral Clock 22 Disable"] #[inline(always)] #[must_use] - pub fn pid22(&mut self) -> PID22_W<22> { + pub fn pid22(&mut self) -> PID22_W { PID22_W::new(self) } #[doc = "Bit 23 - Peripheral Clock 23 Disable"] #[inline(always)] #[must_use] - pub fn pid23(&mut self) -> PID23_W<23> { + pub fn pid23(&mut self) -> PID23_W { PID23_W::new(self) } #[doc = "Bit 24 - Peripheral Clock 24 Disable"] #[inline(always)] #[must_use] - pub fn pid24(&mut self) -> PID24_W<24> { + pub fn pid24(&mut self) -> PID24_W { PID24_W::new(self) } #[doc = "Bit 25 - Peripheral Clock 25 Disable"] #[inline(always)] #[must_use] - pub fn pid25(&mut self) -> PID25_W<25> { + pub fn pid25(&mut self) -> PID25_W { PID25_W::new(self) } #[doc = "Bit 26 - Peripheral Clock 26 Disable"] #[inline(always)] #[must_use] - pub fn pid26(&mut self) -> PID26_W<26> { + pub fn pid26(&mut self) -> PID26_W { PID26_W::new(self) } #[doc = "Bit 27 - Peripheral Clock 27 Disable"] #[inline(always)] #[must_use] - pub fn pid27(&mut self) -> PID27_W<27> { + pub fn pid27(&mut self) -> PID27_W { PID27_W::new(self) } #[doc = "Bit 28 - Peripheral Clock 28 Disable"] #[inline(always)] #[must_use] - pub fn pid28(&mut self) -> PID28_W<28> { + pub fn pid28(&mut self) -> PID28_W { PID28_W::new(self) } #[doc = "Bit 29 - Peripheral Clock 29 Disable"] #[inline(always)] #[must_use] - pub fn pid29(&mut self) -> PID29_W<29> { + pub fn pid29(&mut self) -> PID29_W { PID29_W::new(self) } #[doc = "Bit 30 - Peripheral Clock 30 Disable"] #[inline(always)] #[must_use] - pub fn pid30(&mut self) -> PID30_W<30> { + pub fn pid30(&mut self) -> PID30_W { PID30_W::new(self) } #[doc = "Bit 31 - Peripheral Clock 31 Disable"] #[inline(always)] #[must_use] - pub fn pid31(&mut self) -> PID31_W<31> { + pub fn pid31(&mut self) -> PID31_W { PID31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral Clock Disable Register 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcdr0](index.html) module"] +#[doc = "Peripheral Clock Disable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcdr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCDR0_SPEC; impl crate::RegisterSpec for PCDR0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pcdr0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pcdr0::W`](W) writer structure"] impl crate::Writable for PCDR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcdr1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcdr1.rs index 358e8a36..db4e1dc1 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcdr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcdr1.rs @@ -1,240 +1,220 @@ #[doc = "Register `PCDR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID32` writer - Peripheral Clock 32 Disable"] -pub type PID32_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID33` writer - Peripheral Clock 33 Disable"] -pub type PID33_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID34` writer - Peripheral Clock 34 Disable"] -pub type PID34_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID35` writer - Peripheral Clock 35 Disable"] -pub type PID35_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID37` writer - Peripheral Clock 37 Disable"] -pub type PID37_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID39` writer - Peripheral Clock 39 Disable"] -pub type PID39_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID40` writer - Peripheral Clock 40 Disable"] -pub type PID40_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID41` writer - Peripheral Clock 41 Disable"] -pub type PID41_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID42` writer - Peripheral Clock 42 Disable"] -pub type PID42_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID43` writer - Peripheral Clock 43 Disable"] -pub type PID43_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID44` writer - Peripheral Clock 44 Disable"] -pub type PID44_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID45` writer - Peripheral Clock 45 Disable"] -pub type PID45_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID46` writer - Peripheral Clock 46 Disable"] -pub type PID46_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID47` writer - Peripheral Clock 47 Disable"] -pub type PID47_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID48` writer - Peripheral Clock 48 Disable"] -pub type PID48_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID49` writer - Peripheral Clock 49 Disable"] -pub type PID49_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID50` writer - Peripheral Clock 50 Disable"] -pub type PID50_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID51` writer - Peripheral Clock 51 Disable"] -pub type PID51_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID52` writer - Peripheral Clock 52 Disable"] -pub type PID52_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID53` writer - Peripheral Clock 53 Disable"] -pub type PID53_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID56` writer - Peripheral Clock 56 Disable"] -pub type PID56_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID57` writer - Peripheral Clock 57 Disable"] -pub type PID57_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID58` writer - Peripheral Clock 58 Disable"] -pub type PID58_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID59` writer - Peripheral Clock 59 Disable"] -pub type PID59_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID60` writer - Peripheral Clock 60 Disable"] -pub type PID60_W<'a, const O: u8> = crate::BitWriter<'a, PCDR1_SPEC, O>; +pub type PID60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Peripheral Clock 32 Disable"] #[inline(always)] #[must_use] - pub fn pid32(&mut self) -> PID32_W<0> { + pub fn pid32(&mut self) -> PID32_W { PID32_W::new(self) } #[doc = "Bit 1 - Peripheral Clock 33 Disable"] #[inline(always)] #[must_use] - pub fn pid33(&mut self) -> PID33_W<1> { + pub fn pid33(&mut self) -> PID33_W { PID33_W::new(self) } #[doc = "Bit 2 - Peripheral Clock 34 Disable"] #[inline(always)] #[must_use] - pub fn pid34(&mut self) -> PID34_W<2> { + pub fn pid34(&mut self) -> PID34_W { PID34_W::new(self) } #[doc = "Bit 3 - Peripheral Clock 35 Disable"] #[inline(always)] #[must_use] - pub fn pid35(&mut self) -> PID35_W<3> { + pub fn pid35(&mut self) -> PID35_W { PID35_W::new(self) } #[doc = "Bit 5 - Peripheral Clock 37 Disable"] #[inline(always)] #[must_use] - pub fn pid37(&mut self) -> PID37_W<5> { + pub fn pid37(&mut self) -> PID37_W { PID37_W::new(self) } #[doc = "Bit 7 - Peripheral Clock 39 Disable"] #[inline(always)] #[must_use] - pub fn pid39(&mut self) -> PID39_W<7> { + pub fn pid39(&mut self) -> PID39_W { PID39_W::new(self) } #[doc = "Bit 8 - Peripheral Clock 40 Disable"] #[inline(always)] #[must_use] - pub fn pid40(&mut self) -> PID40_W<8> { + pub fn pid40(&mut self) -> PID40_W { PID40_W::new(self) } #[doc = "Bit 9 - Peripheral Clock 41 Disable"] #[inline(always)] #[must_use] - pub fn pid41(&mut self) -> PID41_W<9> { + pub fn pid41(&mut self) -> PID41_W { PID41_W::new(self) } #[doc = "Bit 10 - Peripheral Clock 42 Disable"] #[inline(always)] #[must_use] - pub fn pid42(&mut self) -> PID42_W<10> { + pub fn pid42(&mut self) -> PID42_W { PID42_W::new(self) } #[doc = "Bit 11 - Peripheral Clock 43 Disable"] #[inline(always)] #[must_use] - pub fn pid43(&mut self) -> PID43_W<11> { + pub fn pid43(&mut self) -> PID43_W { PID43_W::new(self) } #[doc = "Bit 12 - Peripheral Clock 44 Disable"] #[inline(always)] #[must_use] - pub fn pid44(&mut self) -> PID44_W<12> { + pub fn pid44(&mut self) -> PID44_W { PID44_W::new(self) } #[doc = "Bit 13 - Peripheral Clock 45 Disable"] #[inline(always)] #[must_use] - pub fn pid45(&mut self) -> PID45_W<13> { + pub fn pid45(&mut self) -> PID45_W { PID45_W::new(self) } #[doc = "Bit 14 - Peripheral Clock 46 Disable"] #[inline(always)] #[must_use] - pub fn pid46(&mut self) -> PID46_W<14> { + pub fn pid46(&mut self) -> PID46_W { PID46_W::new(self) } #[doc = "Bit 15 - Peripheral Clock 47 Disable"] #[inline(always)] #[must_use] - pub fn pid47(&mut self) -> PID47_W<15> { + pub fn pid47(&mut self) -> PID47_W { PID47_W::new(self) } #[doc = "Bit 16 - Peripheral Clock 48 Disable"] #[inline(always)] #[must_use] - pub fn pid48(&mut self) -> PID48_W<16> { + pub fn pid48(&mut self) -> PID48_W { PID48_W::new(self) } #[doc = "Bit 17 - Peripheral Clock 49 Disable"] #[inline(always)] #[must_use] - pub fn pid49(&mut self) -> PID49_W<17> { + pub fn pid49(&mut self) -> PID49_W { PID49_W::new(self) } #[doc = "Bit 18 - Peripheral Clock 50 Disable"] #[inline(always)] #[must_use] - pub fn pid50(&mut self) -> PID50_W<18> { + pub fn pid50(&mut self) -> PID50_W { PID50_W::new(self) } #[doc = "Bit 19 - Peripheral Clock 51 Disable"] #[inline(always)] #[must_use] - pub fn pid51(&mut self) -> PID51_W<19> { + pub fn pid51(&mut self) -> PID51_W { PID51_W::new(self) } #[doc = "Bit 20 - Peripheral Clock 52 Disable"] #[inline(always)] #[must_use] - pub fn pid52(&mut self) -> PID52_W<20> { + pub fn pid52(&mut self) -> PID52_W { PID52_W::new(self) } #[doc = "Bit 21 - Peripheral Clock 53 Disable"] #[inline(always)] #[must_use] - pub fn pid53(&mut self) -> PID53_W<21> { + pub fn pid53(&mut self) -> PID53_W { PID53_W::new(self) } #[doc = "Bit 24 - Peripheral Clock 56 Disable"] #[inline(always)] #[must_use] - pub fn pid56(&mut self) -> PID56_W<24> { + pub fn pid56(&mut self) -> PID56_W { PID56_W::new(self) } #[doc = "Bit 25 - Peripheral Clock 57 Disable"] #[inline(always)] #[must_use] - pub fn pid57(&mut self) -> PID57_W<25> { + pub fn pid57(&mut self) -> PID57_W { PID57_W::new(self) } #[doc = "Bit 26 - Peripheral Clock 58 Disable"] #[inline(always)] #[must_use] - pub fn pid58(&mut self) -> PID58_W<26> { + pub fn pid58(&mut self) -> PID58_W { PID58_W::new(self) } #[doc = "Bit 27 - Peripheral Clock 59 Disable"] #[inline(always)] #[must_use] - pub fn pid59(&mut self) -> PID59_W<27> { + pub fn pid59(&mut self) -> PID59_W { PID59_W::new(self) } #[doc = "Bit 28 - Peripheral Clock 60 Disable"] #[inline(always)] #[must_use] - pub fn pid60(&mut self) -> PID60_W<28> { + pub fn pid60(&mut self) -> PID60_W { PID60_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral Clock Disable Register 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcdr1](index.html) module"] +#[doc = "Peripheral Clock Disable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcdr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCDR1_SPEC; impl crate::RegisterSpec for PCDR1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pcdr1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pcdr1::W`](W) writer structure"] impl crate::Writable for PCDR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcer0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcer0.rs index 3aa1a1ca..8c3a05e7 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcer0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcer0.rs @@ -1,240 +1,220 @@ #[doc = "Register `PCER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID7` writer - Peripheral Clock 7 Enable"] -pub type PID7_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID8` writer - Peripheral Clock 8 Enable"] -pub type PID8_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID9` writer - Peripheral Clock 9 Enable"] -pub type PID9_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID10` writer - Peripheral Clock 10 Enable"] -pub type PID10_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID11` writer - Peripheral Clock 11 Enable"] -pub type PID11_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID12` writer - Peripheral Clock 12 Enable"] -pub type PID12_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID13` writer - Peripheral Clock 13 Enable"] -pub type PID13_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID14` writer - Peripheral Clock 14 Enable"] -pub type PID14_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID15` writer - Peripheral Clock 15 Enable"] -pub type PID15_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID16` writer - Peripheral Clock 16 Enable"] -pub type PID16_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID17` writer - Peripheral Clock 17 Enable"] -pub type PID17_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID18` writer - Peripheral Clock 18 Enable"] -pub type PID18_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID19` writer - Peripheral Clock 19 Enable"] -pub type PID19_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID20` writer - Peripheral Clock 20 Enable"] -pub type PID20_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID21` writer - Peripheral Clock 21 Enable"] -pub type PID21_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID22` writer - Peripheral Clock 22 Enable"] -pub type PID22_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID23` writer - Peripheral Clock 23 Enable"] -pub type PID23_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID24` writer - Peripheral Clock 24 Enable"] -pub type PID24_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID25` writer - Peripheral Clock 25 Enable"] -pub type PID25_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID26` writer - Peripheral Clock 26 Enable"] -pub type PID26_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID27` writer - Peripheral Clock 27 Enable"] -pub type PID27_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID28` writer - Peripheral Clock 28 Enable"] -pub type PID28_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID29` writer - Peripheral Clock 29 Enable"] -pub type PID29_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID30` writer - Peripheral Clock 30 Enable"] -pub type PID30_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID31` writer - Peripheral Clock 31 Enable"] -pub type PID31_W<'a, const O: u8> = crate::BitWriter<'a, PCER0_SPEC, O>; +pub type PID31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 7 - Peripheral Clock 7 Enable"] #[inline(always)] #[must_use] - pub fn pid7(&mut self) -> PID7_W<7> { + pub fn pid7(&mut self) -> PID7_W { PID7_W::new(self) } #[doc = "Bit 8 - Peripheral Clock 8 Enable"] #[inline(always)] #[must_use] - pub fn pid8(&mut self) -> PID8_W<8> { + pub fn pid8(&mut self) -> PID8_W { PID8_W::new(self) } #[doc = "Bit 9 - Peripheral Clock 9 Enable"] #[inline(always)] #[must_use] - pub fn pid9(&mut self) -> PID9_W<9> { + pub fn pid9(&mut self) -> PID9_W { PID9_W::new(self) } #[doc = "Bit 10 - Peripheral Clock 10 Enable"] #[inline(always)] #[must_use] - pub fn pid10(&mut self) -> PID10_W<10> { + pub fn pid10(&mut self) -> PID10_W { PID10_W::new(self) } #[doc = "Bit 11 - Peripheral Clock 11 Enable"] #[inline(always)] #[must_use] - pub fn pid11(&mut self) -> PID11_W<11> { + pub fn pid11(&mut self) -> PID11_W { PID11_W::new(self) } #[doc = "Bit 12 - Peripheral Clock 12 Enable"] #[inline(always)] #[must_use] - pub fn pid12(&mut self) -> PID12_W<12> { + pub fn pid12(&mut self) -> PID12_W { PID12_W::new(self) } #[doc = "Bit 13 - Peripheral Clock 13 Enable"] #[inline(always)] #[must_use] - pub fn pid13(&mut self) -> PID13_W<13> { + pub fn pid13(&mut self) -> PID13_W { PID13_W::new(self) } #[doc = "Bit 14 - Peripheral Clock 14 Enable"] #[inline(always)] #[must_use] - pub fn pid14(&mut self) -> PID14_W<14> { + pub fn pid14(&mut self) -> PID14_W { PID14_W::new(self) } #[doc = "Bit 15 - Peripheral Clock 15 Enable"] #[inline(always)] #[must_use] - pub fn pid15(&mut self) -> PID15_W<15> { + pub fn pid15(&mut self) -> PID15_W { PID15_W::new(self) } #[doc = "Bit 16 - Peripheral Clock 16 Enable"] #[inline(always)] #[must_use] - pub fn pid16(&mut self) -> PID16_W<16> { + pub fn pid16(&mut self) -> PID16_W { PID16_W::new(self) } #[doc = "Bit 17 - Peripheral Clock 17 Enable"] #[inline(always)] #[must_use] - pub fn pid17(&mut self) -> PID17_W<17> { + pub fn pid17(&mut self) -> PID17_W { PID17_W::new(self) } #[doc = "Bit 18 - Peripheral Clock 18 Enable"] #[inline(always)] #[must_use] - pub fn pid18(&mut self) -> PID18_W<18> { + pub fn pid18(&mut self) -> PID18_W { PID18_W::new(self) } #[doc = "Bit 19 - Peripheral Clock 19 Enable"] #[inline(always)] #[must_use] - pub fn pid19(&mut self) -> PID19_W<19> { + pub fn pid19(&mut self) -> PID19_W { PID19_W::new(self) } #[doc = "Bit 20 - Peripheral Clock 20 Enable"] #[inline(always)] #[must_use] - pub fn pid20(&mut self) -> PID20_W<20> { + pub fn pid20(&mut self) -> PID20_W { PID20_W::new(self) } #[doc = "Bit 21 - Peripheral Clock 21 Enable"] #[inline(always)] #[must_use] - pub fn pid21(&mut self) -> PID21_W<21> { + pub fn pid21(&mut self) -> PID21_W { PID21_W::new(self) } #[doc = "Bit 22 - Peripheral Clock 22 Enable"] #[inline(always)] #[must_use] - pub fn pid22(&mut self) -> PID22_W<22> { + pub fn pid22(&mut self) -> PID22_W { PID22_W::new(self) } #[doc = "Bit 23 - Peripheral Clock 23 Enable"] #[inline(always)] #[must_use] - pub fn pid23(&mut self) -> PID23_W<23> { + pub fn pid23(&mut self) -> PID23_W { PID23_W::new(self) } #[doc = "Bit 24 - Peripheral Clock 24 Enable"] #[inline(always)] #[must_use] - pub fn pid24(&mut self) -> PID24_W<24> { + pub fn pid24(&mut self) -> PID24_W { PID24_W::new(self) } #[doc = "Bit 25 - Peripheral Clock 25 Enable"] #[inline(always)] #[must_use] - pub fn pid25(&mut self) -> PID25_W<25> { + pub fn pid25(&mut self) -> PID25_W { PID25_W::new(self) } #[doc = "Bit 26 - Peripheral Clock 26 Enable"] #[inline(always)] #[must_use] - pub fn pid26(&mut self) -> PID26_W<26> { + pub fn pid26(&mut self) -> PID26_W { PID26_W::new(self) } #[doc = "Bit 27 - Peripheral Clock 27 Enable"] #[inline(always)] #[must_use] - pub fn pid27(&mut self) -> PID27_W<27> { + pub fn pid27(&mut self) -> PID27_W { PID27_W::new(self) } #[doc = "Bit 28 - Peripheral Clock 28 Enable"] #[inline(always)] #[must_use] - pub fn pid28(&mut self) -> PID28_W<28> { + pub fn pid28(&mut self) -> PID28_W { PID28_W::new(self) } #[doc = "Bit 29 - Peripheral Clock 29 Enable"] #[inline(always)] #[must_use] - pub fn pid29(&mut self) -> PID29_W<29> { + pub fn pid29(&mut self) -> PID29_W { PID29_W::new(self) } #[doc = "Bit 30 - Peripheral Clock 30 Enable"] #[inline(always)] #[must_use] - pub fn pid30(&mut self) -> PID30_W<30> { + pub fn pid30(&mut self) -> PID30_W { PID30_W::new(self) } #[doc = "Bit 31 - Peripheral Clock 31 Enable"] #[inline(always)] #[must_use] - pub fn pid31(&mut self) -> PID31_W<31> { + pub fn pid31(&mut self) -> PID31_W { PID31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral Clock Enable Register 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcer0](index.html) module"] +#[doc = "Peripheral Clock Enable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcer0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCER0_SPEC; impl crate::RegisterSpec for PCER0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pcer0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pcer0::W`](W) writer structure"] impl crate::Writable for PCER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcer1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcer1.rs index 2b721dd5..2b1cf96b 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcer1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcer1.rs @@ -1,240 +1,220 @@ #[doc = "Register `PCER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID32` writer - Peripheral Clock 32 Enable"] -pub type PID32_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID33` writer - Peripheral Clock 33 Enable"] -pub type PID33_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID34` writer - Peripheral Clock 34 Enable"] -pub type PID34_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID35` writer - Peripheral Clock 35 Enable"] -pub type PID35_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID37` writer - Peripheral Clock 37 Enable"] -pub type PID37_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID39` writer - Peripheral Clock 39 Enable"] -pub type PID39_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID40` writer - Peripheral Clock 40 Enable"] -pub type PID40_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID41` writer - Peripheral Clock 41 Enable"] -pub type PID41_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID42` writer - Peripheral Clock 42 Enable"] -pub type PID42_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID43` writer - Peripheral Clock 43 Enable"] -pub type PID43_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID44` writer - Peripheral Clock 44 Enable"] -pub type PID44_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID45` writer - Peripheral Clock 45 Enable"] -pub type PID45_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID46` writer - Peripheral Clock 46 Enable"] -pub type PID46_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID47` writer - Peripheral Clock 47 Enable"] -pub type PID47_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID48` writer - Peripheral Clock 48 Enable"] -pub type PID48_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID49` writer - Peripheral Clock 49 Enable"] -pub type PID49_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID50` writer - Peripheral Clock 50 Enable"] -pub type PID50_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID51` writer - Peripheral Clock 51 Enable"] -pub type PID51_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID52` writer - Peripheral Clock 52 Enable"] -pub type PID52_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID53` writer - Peripheral Clock 53 Enable"] -pub type PID53_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID56` writer - Peripheral Clock 56 Enable"] -pub type PID56_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID57` writer - Peripheral Clock 57 Enable"] -pub type PID57_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID58` writer - Peripheral Clock 58 Enable"] -pub type PID58_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID59` writer - Peripheral Clock 59 Enable"] -pub type PID59_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID60` writer - Peripheral Clock 60 Enable"] -pub type PID60_W<'a, const O: u8> = crate::BitWriter<'a, PCER1_SPEC, O>; +pub type PID60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Peripheral Clock 32 Enable"] #[inline(always)] #[must_use] - pub fn pid32(&mut self) -> PID32_W<0> { + pub fn pid32(&mut self) -> PID32_W { PID32_W::new(self) } #[doc = "Bit 1 - Peripheral Clock 33 Enable"] #[inline(always)] #[must_use] - pub fn pid33(&mut self) -> PID33_W<1> { + pub fn pid33(&mut self) -> PID33_W { PID33_W::new(self) } #[doc = "Bit 2 - Peripheral Clock 34 Enable"] #[inline(always)] #[must_use] - pub fn pid34(&mut self) -> PID34_W<2> { + pub fn pid34(&mut self) -> PID34_W { PID34_W::new(self) } #[doc = "Bit 3 - Peripheral Clock 35 Enable"] #[inline(always)] #[must_use] - pub fn pid35(&mut self) -> PID35_W<3> { + pub fn pid35(&mut self) -> PID35_W { PID35_W::new(self) } #[doc = "Bit 5 - Peripheral Clock 37 Enable"] #[inline(always)] #[must_use] - pub fn pid37(&mut self) -> PID37_W<5> { + pub fn pid37(&mut self) -> PID37_W { PID37_W::new(self) } #[doc = "Bit 7 - Peripheral Clock 39 Enable"] #[inline(always)] #[must_use] - pub fn pid39(&mut self) -> PID39_W<7> { + pub fn pid39(&mut self) -> PID39_W { PID39_W::new(self) } #[doc = "Bit 8 - Peripheral Clock 40 Enable"] #[inline(always)] #[must_use] - pub fn pid40(&mut self) -> PID40_W<8> { + pub fn pid40(&mut self) -> PID40_W { PID40_W::new(self) } #[doc = "Bit 9 - Peripheral Clock 41 Enable"] #[inline(always)] #[must_use] - pub fn pid41(&mut self) -> PID41_W<9> { + pub fn pid41(&mut self) -> PID41_W { PID41_W::new(self) } #[doc = "Bit 10 - Peripheral Clock 42 Enable"] #[inline(always)] #[must_use] - pub fn pid42(&mut self) -> PID42_W<10> { + pub fn pid42(&mut self) -> PID42_W { PID42_W::new(self) } #[doc = "Bit 11 - Peripheral Clock 43 Enable"] #[inline(always)] #[must_use] - pub fn pid43(&mut self) -> PID43_W<11> { + pub fn pid43(&mut self) -> PID43_W { PID43_W::new(self) } #[doc = "Bit 12 - Peripheral Clock 44 Enable"] #[inline(always)] #[must_use] - pub fn pid44(&mut self) -> PID44_W<12> { + pub fn pid44(&mut self) -> PID44_W { PID44_W::new(self) } #[doc = "Bit 13 - Peripheral Clock 45 Enable"] #[inline(always)] #[must_use] - pub fn pid45(&mut self) -> PID45_W<13> { + pub fn pid45(&mut self) -> PID45_W { PID45_W::new(self) } #[doc = "Bit 14 - Peripheral Clock 46 Enable"] #[inline(always)] #[must_use] - pub fn pid46(&mut self) -> PID46_W<14> { + pub fn pid46(&mut self) -> PID46_W { PID46_W::new(self) } #[doc = "Bit 15 - Peripheral Clock 47 Enable"] #[inline(always)] #[must_use] - pub fn pid47(&mut self) -> PID47_W<15> { + pub fn pid47(&mut self) -> PID47_W { PID47_W::new(self) } #[doc = "Bit 16 - Peripheral Clock 48 Enable"] #[inline(always)] #[must_use] - pub fn pid48(&mut self) -> PID48_W<16> { + pub fn pid48(&mut self) -> PID48_W { PID48_W::new(self) } #[doc = "Bit 17 - Peripheral Clock 49 Enable"] #[inline(always)] #[must_use] - pub fn pid49(&mut self) -> PID49_W<17> { + pub fn pid49(&mut self) -> PID49_W { PID49_W::new(self) } #[doc = "Bit 18 - Peripheral Clock 50 Enable"] #[inline(always)] #[must_use] - pub fn pid50(&mut self) -> PID50_W<18> { + pub fn pid50(&mut self) -> PID50_W { PID50_W::new(self) } #[doc = "Bit 19 - Peripheral Clock 51 Enable"] #[inline(always)] #[must_use] - pub fn pid51(&mut self) -> PID51_W<19> { + pub fn pid51(&mut self) -> PID51_W { PID51_W::new(self) } #[doc = "Bit 20 - Peripheral Clock 52 Enable"] #[inline(always)] #[must_use] - pub fn pid52(&mut self) -> PID52_W<20> { + pub fn pid52(&mut self) -> PID52_W { PID52_W::new(self) } #[doc = "Bit 21 - Peripheral Clock 53 Enable"] #[inline(always)] #[must_use] - pub fn pid53(&mut self) -> PID53_W<21> { + pub fn pid53(&mut self) -> PID53_W { PID53_W::new(self) } #[doc = "Bit 24 - Peripheral Clock 56 Enable"] #[inline(always)] #[must_use] - pub fn pid56(&mut self) -> PID56_W<24> { + pub fn pid56(&mut self) -> PID56_W { PID56_W::new(self) } #[doc = "Bit 25 - Peripheral Clock 57 Enable"] #[inline(always)] #[must_use] - pub fn pid57(&mut self) -> PID57_W<25> { + pub fn pid57(&mut self) -> PID57_W { PID57_W::new(self) } #[doc = "Bit 26 - Peripheral Clock 58 Enable"] #[inline(always)] #[must_use] - pub fn pid58(&mut self) -> PID58_W<26> { + pub fn pid58(&mut self) -> PID58_W { PID58_W::new(self) } #[doc = "Bit 27 - Peripheral Clock 59 Enable"] #[inline(always)] #[must_use] - pub fn pid59(&mut self) -> PID59_W<27> { + pub fn pid59(&mut self) -> PID59_W { PID59_W::new(self) } #[doc = "Bit 28 - Peripheral Clock 60 Enable"] #[inline(always)] #[must_use] - pub fn pid60(&mut self) -> PID60_W<28> { + pub fn pid60(&mut self) -> PID60_W { PID60_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral Clock Enable Register 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcer1](index.html) module"] +#[doc = "Peripheral Clock Enable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcer1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCER1_SPEC; impl crate::RegisterSpec for PCER1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [pcer1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`pcer1::W`](W) writer structure"] impl crate::Writable for PCER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pck.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pck.rs index ee8074b4..1a6ef9a6 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pck.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pck.rs @@ -1,39 +1,7 @@ #[doc = "Register `PCK[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PCK[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSS` reader - Programmable Clock Source Selection"] pub type CSS_R = crate::FieldReader; #[doc = "Programmable Clock Source Selection\n\nValue on reset: 0"] @@ -73,65 +41,69 @@ impl CSS_R { _ => None, } } - #[doc = "Checks if the value of the field is `SLOW_CLK`"] + #[doc = "SLCK is selected"] #[inline(always)] pub fn is_slow_clk(&self) -> bool { *self == CSSSELECT_A::SLOW_CLK } - #[doc = "Checks if the value of the field is `MAIN_CLK`"] + #[doc = "MAINCK is selected"] #[inline(always)] pub fn is_main_clk(&self) -> bool { *self == CSSSELECT_A::MAIN_CLK } - #[doc = "Checks if the value of the field is `PLLA_CLK`"] + #[doc = "PLLACK is selected"] #[inline(always)] pub fn is_plla_clk(&self) -> bool { *self == CSSSELECT_A::PLLA_CLK } - #[doc = "Checks if the value of the field is `UPLL_CLK`"] + #[doc = "UPLLCKDIV is selected"] #[inline(always)] pub fn is_upll_clk(&self) -> bool { *self == CSSSELECT_A::UPLL_CLK } - #[doc = "Checks if the value of the field is `MCK`"] + #[doc = "MCK is selected"] #[inline(always)] pub fn is_mck(&self) -> bool { *self == CSSSELECT_A::MCK } } #[doc = "Field `CSS` writer - Programmable Clock Source Selection"] -pub type CSS_W<'a, const O: u8> = crate::FieldWriter<'a, PCK_SPEC, 3, O, CSSSELECT_A>; -impl<'a, const O: u8> CSS_W<'a, O> { +pub type CSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CSSSELECT_A>; +impl<'a, REG, const O: u8> CSS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "SLCK is selected"] #[inline(always)] - pub fn slow_clk(self) -> &'a mut W { + pub fn slow_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::SLOW_CLK) } #[doc = "MAINCK is selected"] #[inline(always)] - pub fn main_clk(self) -> &'a mut W { + pub fn main_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::MAIN_CLK) } #[doc = "PLLACK is selected"] #[inline(always)] - pub fn plla_clk(self) -> &'a mut W { + pub fn plla_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::PLLA_CLK) } #[doc = "UPLLCKDIV is selected"] #[inline(always)] - pub fn upll_clk(self) -> &'a mut W { + pub fn upll_clk(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::UPLL_CLK) } #[doc = "MCK is selected"] #[inline(always)] - pub fn mck(self) -> &'a mut W { + pub fn mck(self) -> &'a mut crate::W { self.variant(CSSSELECT_A::MCK) } } #[doc = "Field `PRES` reader - Programmable Clock Prescaler"] pub type PRES_R = crate::FieldReader; #[doc = "Field `PRES` writer - Programmable Clock Prescaler"] -pub type PRES_W<'a, const O: u8> = crate::FieldWriter<'a, PCK_SPEC, 8, O>; +pub type PRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:2 - Programmable Clock Source Selection"] #[inline(always)] @@ -148,34 +120,31 @@ impl W { #[doc = "Bits 0:2 - Programmable Clock Source Selection"] #[inline(always)] #[must_use] - pub fn css(&mut self) -> CSS_W<0> { + pub fn css(&mut self) -> CSS_W { CSS_W::new(self) } #[doc = "Bits 4:11 - Programmable Clock Prescaler"] #[inline(always)] #[must_use] - pub fn pres(&mut self) -> PRES_W<4> { + pub fn pres(&mut self) -> PRES_W { PRES_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Programmable Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pck](index.html) module"] +#[doc = "Programmable Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pck::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pck::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCK_SPEC; impl crate::RegisterSpec for PCK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pck::R](R) reader structure"] -impl crate::Readable for PCK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pck::W](W) writer structure"] +#[doc = "`read()` method returns [`pck::R`](R) reader structure"] +impl crate::Readable for PCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pck::W`](W) writer structure"] impl crate::Writable for PCK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcr.rs index 73833e48..02cfc2c5 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcr.rs @@ -1,43 +1,11 @@ #[doc = "Register `PCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID` reader - Peripheral ID"] pub type PID_R = crate::FieldReader; #[doc = "Field `PID` writer - Peripheral ID"] -pub type PID_W<'a, const O: u8> = crate::FieldWriter<'a, PCR_SPEC, 7, O>; +pub type PID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `GCLKCSS` reader - Generic Clock Source Selection"] pub type GCLKCSS_R = crate::FieldReader; #[doc = "Generic Clock Source Selection\n\nValue on reset: 0"] @@ -77,77 +45,81 @@ impl GCLKCSS_R { _ => None, } } - #[doc = "Checks if the value of the field is `SLOW_CLK`"] + #[doc = "Slow clock is selected"] #[inline(always)] pub fn is_slow_clk(&self) -> bool { *self == GCLKCSSSELECT_A::SLOW_CLK } - #[doc = "Checks if the value of the field is `MAIN_CLK`"] + #[doc = "Main clock is selected"] #[inline(always)] pub fn is_main_clk(&self) -> bool { *self == GCLKCSSSELECT_A::MAIN_CLK } - #[doc = "Checks if the value of the field is `PLLA_CLK`"] + #[doc = "PLLACK is selected"] #[inline(always)] pub fn is_plla_clk(&self) -> bool { *self == GCLKCSSSELECT_A::PLLA_CLK } - #[doc = "Checks if the value of the field is `UPLL_CLK`"] + #[doc = "UPLL Clock is selected"] #[inline(always)] pub fn is_upll_clk(&self) -> bool { *self == GCLKCSSSELECT_A::UPLL_CLK } - #[doc = "Checks if the value of the field is `MCK_CLK`"] + #[doc = "Master Clock is selected"] #[inline(always)] pub fn is_mck_clk(&self) -> bool { *self == GCLKCSSSELECT_A::MCK_CLK } } #[doc = "Field `GCLKCSS` writer - Generic Clock Source Selection"] -pub type GCLKCSS_W<'a, const O: u8> = crate::FieldWriter<'a, PCR_SPEC, 3, O, GCLKCSSSELECT_A>; -impl<'a, const O: u8> GCLKCSS_W<'a, O> { +pub type GCLKCSS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, GCLKCSSSELECT_A>; +impl<'a, REG, const O: u8> GCLKCSS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Slow clock is selected"] #[inline(always)] - pub fn slow_clk(self) -> &'a mut W { + pub fn slow_clk(self) -> &'a mut crate::W { self.variant(GCLKCSSSELECT_A::SLOW_CLK) } #[doc = "Main clock is selected"] #[inline(always)] - pub fn main_clk(self) -> &'a mut W { + pub fn main_clk(self) -> &'a mut crate::W { self.variant(GCLKCSSSELECT_A::MAIN_CLK) } #[doc = "PLLACK is selected"] #[inline(always)] - pub fn plla_clk(self) -> &'a mut W { + pub fn plla_clk(self) -> &'a mut crate::W { self.variant(GCLKCSSSELECT_A::PLLA_CLK) } #[doc = "UPLL Clock is selected"] #[inline(always)] - pub fn upll_clk(self) -> &'a mut W { + pub fn upll_clk(self) -> &'a mut crate::W { self.variant(GCLKCSSSELECT_A::UPLL_CLK) } #[doc = "Master Clock is selected"] #[inline(always)] - pub fn mck_clk(self) -> &'a mut W { + pub fn mck_clk(self) -> &'a mut crate::W { self.variant(GCLKCSSSELECT_A::MCK_CLK) } } #[doc = "Field `CMD` reader - Command"] pub type CMD_R = crate::BitReader; #[doc = "Field `CMD` writer - Command"] -pub type CMD_W<'a, const O: u8> = crate::BitWriter<'a, PCR_SPEC, O>; +pub type CMD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GCLKDIV` reader - Generic Clock Division Ratio"] pub type GCLKDIV_R = crate::FieldReader; #[doc = "Field `GCLKDIV` writer - Generic Clock Division Ratio"] -pub type GCLKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, PCR_SPEC, 8, O>; +pub type GCLKDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `EN` reader - Enable"] pub type EN_R = crate::BitReader; #[doc = "Field `EN` writer - Enable"] -pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, PCR_SPEC, O>; +pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GCLKEN` reader - Generic Clock Enable"] pub type GCLKEN_R = crate::BitReader; #[doc = "Field `GCLKEN` writer - Generic Clock Enable"] -pub type GCLKEN_W<'a, const O: u8> = crate::BitWriter<'a, PCR_SPEC, O>; +pub type GCLKEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Peripheral ID"] #[inline(always)] @@ -184,58 +156,55 @@ impl W { #[doc = "Bits 0:6 - Peripheral ID"] #[inline(always)] #[must_use] - pub fn pid(&mut self) -> PID_W<0> { + pub fn pid(&mut self) -> PID_W { PID_W::new(self) } #[doc = "Bits 8:10 - Generic Clock Source Selection"] #[inline(always)] #[must_use] - pub fn gclkcss(&mut self) -> GCLKCSS_W<8> { + pub fn gclkcss(&mut self) -> GCLKCSS_W { GCLKCSS_W::new(self) } #[doc = "Bit 12 - Command"] #[inline(always)] #[must_use] - pub fn cmd(&mut self) -> CMD_W<12> { + pub fn cmd(&mut self) -> CMD_W { CMD_W::new(self) } #[doc = "Bits 20:27 - Generic Clock Division Ratio"] #[inline(always)] #[must_use] - pub fn gclkdiv(&mut self) -> GCLKDIV_W<20> { + pub fn gclkdiv(&mut self) -> GCLKDIV_W { GCLKDIV_W::new(self) } #[doc = "Bit 28 - Enable"] #[inline(always)] #[must_use] - pub fn en(&mut self) -> EN_W<28> { + pub fn en(&mut self) -> EN_W { EN_W::new(self) } #[doc = "Bit 29 - Generic Clock Enable"] #[inline(always)] #[must_use] - pub fn gclken(&mut self) -> GCLKEN_W<29> { + pub fn gclken(&mut self) -> GCLKEN_W { GCLKEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Peripheral Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcr](index.html) module"] +#[doc = "Peripheral Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCR_SPEC; impl crate::RegisterSpec for PCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcr::R](R) reader structure"] -impl crate::Readable for PCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pcr::W](W) writer structure"] +#[doc = "`read()` method returns [`pcr::R`](R) reader structure"] +impl crate::Readable for PCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pcr::W`](W) writer structure"] impl crate::Writable for PCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcsr0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcsr0.rs index 22f8b465..8f437203 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcsr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcsr0.rs @@ -1,18 +1,5 @@ #[doc = "Register `PCSR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PID7` reader - Peripheral Clock 7 Status"] pub type PID7_R = crate::BitReader; #[doc = "Field `PID8` reader - Peripheral Clock 8 Status"] @@ -190,15 +177,13 @@ impl R { PID31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Peripheral Clock Status Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcsr0](index.html) module"] +#[doc = "Peripheral Clock Status Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcsr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCSR0_SPEC; impl crate::RegisterSpec for PCSR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcsr0::R](R) reader structure"] -impl crate::Readable for PCSR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pcsr0::R`](R) reader structure"] +impl crate::Readable for PCSR0_SPEC {} #[doc = "`reset()` method sets PCSR0 to value 0"] impl crate::Resettable for PCSR0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pcsr1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pcsr1.rs index eff89468..f185bc80 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pcsr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pcsr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `PCSR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PID32` reader - Peripheral Clock 32 Status"] pub type PID32_R = crate::BitReader; #[doc = "Field `PID33` reader - Peripheral Clock 33 Status"] @@ -190,15 +177,13 @@ impl R { PID60_R::new(((self.bits >> 28) & 1) != 0) } } -#[doc = "Peripheral Clock Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcsr1](index.html) module"] +#[doc = "Peripheral Clock Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pcsr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PCSR1_SPEC; impl crate::RegisterSpec for PCSR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pcsr1::R](R) reader structure"] -impl crate::Readable for PCSR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`pcsr1::R`](R) reader structure"] +impl crate::Readable for PCSR1_SPEC {} #[doc = "`reset()` method sets PCSR1 to value 0"] impl crate::Resettable for PCSR1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/pmmr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/pmmr.rs index 8127e7f2..ab92dbe4 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/pmmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/pmmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `PMMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PMMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PLLA_MMAX` reader - PLLA Maximum Allowed Multiplier Value"] pub type PLLA_MMAX_R = crate::FieldReader; #[doc = "Field `PLLA_MMAX` writer - PLLA Maximum Allowed Multiplier Value"] -pub type PLLA_MMAX_W<'a, const O: u8> = crate::FieldWriter<'a, PMMR_SPEC, 11, O, u16>; +pub type PLLA_MMAX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; impl R { #[doc = "Bits 0:10 - PLLA Maximum Allowed Multiplier Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:10 - PLLA Maximum Allowed Multiplier Value"] #[inline(always)] #[must_use] - pub fn plla_mmax(&mut self) -> PLLA_MMAX_W<0> { + pub fn plla_mmax(&mut self) -> PLLA_MMAX_W { PLLA_MMAX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PLL Maximum Multiplier Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmmr](index.html) module"] +#[doc = "PLL Maximum Multiplier Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PMMR_SPEC; impl crate::RegisterSpec for PMMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pmmr::R](R) reader structure"] -impl crate::Readable for PMMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pmmr::W](W) writer structure"] +#[doc = "`read()` method returns [`pmmr::R`](R) reader structure"] +impl crate::Readable for PMMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pmmr::W`](W) writer structure"] impl crate::Writable for PMMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/scdr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/scdr.rs index f19b28bf..ff414830 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/scdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/scdr.rs @@ -1,112 +1,92 @@ #[doc = "Register `SCDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USBCLK` writer - Disable USB FS Clock"] -pub type USBCLK_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type USBCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK0` writer - Programmable Clock 0 Output Disable"] -pub type PCK0_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK1` writer - Programmable Clock 1 Output Disable"] -pub type PCK1_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK2` writer - Programmable Clock 2 Output Disable"] -pub type PCK2_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK3` writer - Programmable Clock 3 Output Disable"] -pub type PCK3_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK4` writer - Programmable Clock 4 Output Disable"] -pub type PCK4_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK5` writer - Programmable Clock 5 Output Disable"] -pub type PCK5_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK6` writer - Programmable Clock 6 Output Disable"] -pub type PCK6_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK7` writer - Programmable Clock 7 Output Disable"] -pub type PCK7_W<'a, const O: u8> = crate::BitWriter<'a, SCDR_SPEC, O>; +pub type PCK7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 5 - Disable USB FS Clock"] #[inline(always)] #[must_use] - pub fn usbclk(&mut self) -> USBCLK_W<5> { + pub fn usbclk(&mut self) -> USBCLK_W { USBCLK_W::new(self) } #[doc = "Bit 8 - Programmable Clock 0 Output Disable"] #[inline(always)] #[must_use] - pub fn pck0(&mut self) -> PCK0_W<8> { + pub fn pck0(&mut self) -> PCK0_W { PCK0_W::new(self) } #[doc = "Bit 9 - Programmable Clock 1 Output Disable"] #[inline(always)] #[must_use] - pub fn pck1(&mut self) -> PCK1_W<9> { + pub fn pck1(&mut self) -> PCK1_W { PCK1_W::new(self) } #[doc = "Bit 10 - Programmable Clock 2 Output Disable"] #[inline(always)] #[must_use] - pub fn pck2(&mut self) -> PCK2_W<10> { + pub fn pck2(&mut self) -> PCK2_W { PCK2_W::new(self) } #[doc = "Bit 11 - Programmable Clock 3 Output Disable"] #[inline(always)] #[must_use] - pub fn pck3(&mut self) -> PCK3_W<11> { + pub fn pck3(&mut self) -> PCK3_W { PCK3_W::new(self) } #[doc = "Bit 12 - Programmable Clock 4 Output Disable"] #[inline(always)] #[must_use] - pub fn pck4(&mut self) -> PCK4_W<12> { + pub fn pck4(&mut self) -> PCK4_W { PCK4_W::new(self) } #[doc = "Bit 13 - Programmable Clock 5 Output Disable"] #[inline(always)] #[must_use] - pub fn pck5(&mut self) -> PCK5_W<13> { + pub fn pck5(&mut self) -> PCK5_W { PCK5_W::new(self) } #[doc = "Bit 14 - Programmable Clock 6 Output Disable"] #[inline(always)] #[must_use] - pub fn pck6(&mut self) -> PCK6_W<14> { + pub fn pck6(&mut self) -> PCK6_W { PCK6_W::new(self) } #[doc = "Bit 15 - Programmable Clock 7 Output Disable"] #[inline(always)] #[must_use] - pub fn pck7(&mut self) -> PCK7_W<15> { + pub fn pck7(&mut self) -> PCK7_W { PCK7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "System Clock Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scdr](index.html) module"] +#[doc = "System Clock Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCDR_SPEC; impl crate::RegisterSpec for SCDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [scdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`scdr::W`](W) writer structure"] impl crate::Writable for SCDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/scer.rs b/arch/cortex-m/samv71q21-pac/src/pmc/scer.rs index 6ec97ac7..afabe6b6 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/scer.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/scer.rs @@ -1,112 +1,92 @@ #[doc = "Register `SCER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USBCLK` writer - Enable USB FS Clock"] -pub type USBCLK_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type USBCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK0` writer - Programmable Clock 0 Output Enable"] -pub type PCK0_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK1` writer - Programmable Clock 1 Output Enable"] -pub type PCK1_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK2` writer - Programmable Clock 2 Output Enable"] -pub type PCK2_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK3` writer - Programmable Clock 3 Output Enable"] -pub type PCK3_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK4` writer - Programmable Clock 4 Output Enable"] -pub type PCK4_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK5` writer - Programmable Clock 5 Output Enable"] -pub type PCK5_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK6` writer - Programmable Clock 6 Output Enable"] -pub type PCK6_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCK7` writer - Programmable Clock 7 Output Enable"] -pub type PCK7_W<'a, const O: u8> = crate::BitWriter<'a, SCER_SPEC, O>; +pub type PCK7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 5 - Enable USB FS Clock"] #[inline(always)] #[must_use] - pub fn usbclk(&mut self) -> USBCLK_W<5> { + pub fn usbclk(&mut self) -> USBCLK_W { USBCLK_W::new(self) } #[doc = "Bit 8 - Programmable Clock 0 Output Enable"] #[inline(always)] #[must_use] - pub fn pck0(&mut self) -> PCK0_W<8> { + pub fn pck0(&mut self) -> PCK0_W { PCK0_W::new(self) } #[doc = "Bit 9 - Programmable Clock 1 Output Enable"] #[inline(always)] #[must_use] - pub fn pck1(&mut self) -> PCK1_W<9> { + pub fn pck1(&mut self) -> PCK1_W { PCK1_W::new(self) } #[doc = "Bit 10 - Programmable Clock 2 Output Enable"] #[inline(always)] #[must_use] - pub fn pck2(&mut self) -> PCK2_W<10> { + pub fn pck2(&mut self) -> PCK2_W { PCK2_W::new(self) } #[doc = "Bit 11 - Programmable Clock 3 Output Enable"] #[inline(always)] #[must_use] - pub fn pck3(&mut self) -> PCK3_W<11> { + pub fn pck3(&mut self) -> PCK3_W { PCK3_W::new(self) } #[doc = "Bit 12 - Programmable Clock 4 Output Enable"] #[inline(always)] #[must_use] - pub fn pck4(&mut self) -> PCK4_W<12> { + pub fn pck4(&mut self) -> PCK4_W { PCK4_W::new(self) } #[doc = "Bit 13 - Programmable Clock 5 Output Enable"] #[inline(always)] #[must_use] - pub fn pck5(&mut self) -> PCK5_W<13> { + pub fn pck5(&mut self) -> PCK5_W { PCK5_W::new(self) } #[doc = "Bit 14 - Programmable Clock 6 Output Enable"] #[inline(always)] #[must_use] - pub fn pck6(&mut self) -> PCK6_W<14> { + pub fn pck6(&mut self) -> PCK6_W { PCK6_W::new(self) } #[doc = "Bit 15 - Programmable Clock 7 Output Enable"] #[inline(always)] #[must_use] - pub fn pck7(&mut self) -> PCK7_W<15> { + pub fn pck7(&mut self) -> PCK7_W { PCK7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "System Clock Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scer](index.html) module"] +#[doc = "System Clock Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scer::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCER_SPEC; impl crate::RegisterSpec for SCER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [scer::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`scer::W`](W) writer structure"] impl crate::Writable for SCER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/scsr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/scsr.rs index f615ff40..09b96870 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/scsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/scsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SCSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `HCLKS` reader - HCLK Status"] pub type HCLKS_R = crate::BitReader; #[doc = "Field `USBCLK` reader - USB FS Clock Status"] @@ -85,15 +72,13 @@ impl R { PCK7_R::new(((self.bits >> 15) & 1) != 0) } } -#[doc = "System Clock Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scsr](index.html) module"] +#[doc = "System Clock Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCSR_SPEC; impl crate::RegisterSpec for SCSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scsr::R](R) reader structure"] -impl crate::Readable for SCSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`scsr::R`](R) reader structure"] +impl crate::Readable for SCSR_SPEC {} #[doc = "`reset()` method sets SCSR to value 0"] impl crate::Resettable for SCSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_aipr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_aipr.rs index 7a598390..e483839d 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_aipr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_aipr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SLPWK_AIPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `AIP` reader - Activity In Progress"] pub type AIP_R = crate::BitReader; impl R { @@ -22,15 +9,13 @@ impl R { AIP_R::new((self.bits & 1) != 0) } } -#[doc = "SleepWalking Activity In Progress Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_aipr](index.html) module"] +#[doc = "SleepWalking Activity In Progress Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_aipr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_AIPR_SPEC; impl crate::RegisterSpec for SLPWK_AIPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slpwk_aipr::R](R) reader structure"] -impl crate::Readable for SLPWK_AIPR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`slpwk_aipr::R`](R) reader structure"] +impl crate::Readable for SLPWK_AIPR_SPEC {} #[doc = "`reset()` method sets SLPWK_AIPR to value 0"] impl crate::Resettable for SLPWK_AIPR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr0.rs index db5d38d6..18588a90 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr0.rs @@ -1,18 +1,5 @@ #[doc = "Register `SLPWK_ASR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PID7` reader - Peripheral 7 Activity Status"] pub type PID7_R = crate::BitReader; #[doc = "Field `PID8` reader - Peripheral 8 Activity Status"] @@ -190,15 +177,13 @@ impl R { PID31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "SleepWalking Activity Status Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_asr0](index.html) module"] +#[doc = "SleepWalking Activity Status Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_asr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_ASR0_SPEC; impl crate::RegisterSpec for SLPWK_ASR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slpwk_asr0::R](R) reader structure"] -impl crate::Readable for SLPWK_ASR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`slpwk_asr0::R`](R) reader structure"] +impl crate::Readable for SLPWK_ASR0_SPEC {} #[doc = "`reset()` method sets SLPWK_ASR0 to value 0"] impl crate::Resettable for SLPWK_ASR0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr1.rs index e7917c57..2a26d287 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_asr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `SLPWK_ASR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PID32` reader - Peripheral 32 Activity Status"] pub type PID32_R = crate::BitReader; #[doc = "Field `PID33` reader - Peripheral 33 Activity Status"] @@ -190,15 +177,13 @@ impl R { PID60_R::new(((self.bits >> 28) & 1) != 0) } } -#[doc = "SleepWalking Activity Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_asr1](index.html) module"] +#[doc = "SleepWalking Activity Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_asr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_ASR1_SPEC; impl crate::RegisterSpec for SLPWK_ASR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slpwk_asr1::R](R) reader structure"] -impl crate::Readable for SLPWK_ASR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`slpwk_asr1::R`](R) reader structure"] +impl crate::Readable for SLPWK_ASR1_SPEC {} #[doc = "`reset()` method sets SLPWK_ASR1 to value 0"] impl crate::Resettable for SLPWK_ASR1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr0.rs index 8ae60e38..8c232f6a 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr0.rs @@ -1,240 +1,220 @@ #[doc = "Register `SLPWK_DR0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID7` writer - Peripheral 7 SleepWalking Disable"] -pub type PID7_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID8` writer - Peripheral 8 SleepWalking Disable"] -pub type PID8_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID9` writer - Peripheral 9 SleepWalking Disable"] -pub type PID9_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID10` writer - Peripheral 10 SleepWalking Disable"] -pub type PID10_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID11` writer - Peripheral 11 SleepWalking Disable"] -pub type PID11_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID12` writer - Peripheral 12 SleepWalking Disable"] -pub type PID12_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID13` writer - Peripheral 13 SleepWalking Disable"] -pub type PID13_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID14` writer - Peripheral 14 SleepWalking Disable"] -pub type PID14_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID15` writer - Peripheral 15 SleepWalking Disable"] -pub type PID15_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID16` writer - Peripheral 16 SleepWalking Disable"] -pub type PID16_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID17` writer - Peripheral 17 SleepWalking Disable"] -pub type PID17_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID18` writer - Peripheral 18 SleepWalking Disable"] -pub type PID18_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID19` writer - Peripheral 19 SleepWalking Disable"] -pub type PID19_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID20` writer - Peripheral 20 SleepWalking Disable"] -pub type PID20_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID21` writer - Peripheral 21 SleepWalking Disable"] -pub type PID21_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID22` writer - Peripheral 22 SleepWalking Disable"] -pub type PID22_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID23` writer - Peripheral 23 SleepWalking Disable"] -pub type PID23_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID24` writer - Peripheral 24 SleepWalking Disable"] -pub type PID24_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID25` writer - Peripheral 25 SleepWalking Disable"] -pub type PID25_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID26` writer - Peripheral 26 SleepWalking Disable"] -pub type PID26_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID27` writer - Peripheral 27 SleepWalking Disable"] -pub type PID27_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID28` writer - Peripheral 28 SleepWalking Disable"] -pub type PID28_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID29` writer - Peripheral 29 SleepWalking Disable"] -pub type PID29_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID30` writer - Peripheral 30 SleepWalking Disable"] -pub type PID30_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID31` writer - Peripheral 31 SleepWalking Disable"] -pub type PID31_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR0_SPEC, O>; +pub type PID31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 7 - Peripheral 7 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid7(&mut self) -> PID7_W<7> { + pub fn pid7(&mut self) -> PID7_W { PID7_W::new(self) } #[doc = "Bit 8 - Peripheral 8 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid8(&mut self) -> PID8_W<8> { + pub fn pid8(&mut self) -> PID8_W { PID8_W::new(self) } #[doc = "Bit 9 - Peripheral 9 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid9(&mut self) -> PID9_W<9> { + pub fn pid9(&mut self) -> PID9_W { PID9_W::new(self) } #[doc = "Bit 10 - Peripheral 10 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid10(&mut self) -> PID10_W<10> { + pub fn pid10(&mut self) -> PID10_W { PID10_W::new(self) } #[doc = "Bit 11 - Peripheral 11 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid11(&mut self) -> PID11_W<11> { + pub fn pid11(&mut self) -> PID11_W { PID11_W::new(self) } #[doc = "Bit 12 - Peripheral 12 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid12(&mut self) -> PID12_W<12> { + pub fn pid12(&mut self) -> PID12_W { PID12_W::new(self) } #[doc = "Bit 13 - Peripheral 13 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid13(&mut self) -> PID13_W<13> { + pub fn pid13(&mut self) -> PID13_W { PID13_W::new(self) } #[doc = "Bit 14 - Peripheral 14 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid14(&mut self) -> PID14_W<14> { + pub fn pid14(&mut self) -> PID14_W { PID14_W::new(self) } #[doc = "Bit 15 - Peripheral 15 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid15(&mut self) -> PID15_W<15> { + pub fn pid15(&mut self) -> PID15_W { PID15_W::new(self) } #[doc = "Bit 16 - Peripheral 16 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid16(&mut self) -> PID16_W<16> { + pub fn pid16(&mut self) -> PID16_W { PID16_W::new(self) } #[doc = "Bit 17 - Peripheral 17 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid17(&mut self) -> PID17_W<17> { + pub fn pid17(&mut self) -> PID17_W { PID17_W::new(self) } #[doc = "Bit 18 - Peripheral 18 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid18(&mut self) -> PID18_W<18> { + pub fn pid18(&mut self) -> PID18_W { PID18_W::new(self) } #[doc = "Bit 19 - Peripheral 19 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid19(&mut self) -> PID19_W<19> { + pub fn pid19(&mut self) -> PID19_W { PID19_W::new(self) } #[doc = "Bit 20 - Peripheral 20 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid20(&mut self) -> PID20_W<20> { + pub fn pid20(&mut self) -> PID20_W { PID20_W::new(self) } #[doc = "Bit 21 - Peripheral 21 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid21(&mut self) -> PID21_W<21> { + pub fn pid21(&mut self) -> PID21_W { PID21_W::new(self) } #[doc = "Bit 22 - Peripheral 22 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid22(&mut self) -> PID22_W<22> { + pub fn pid22(&mut self) -> PID22_W { PID22_W::new(self) } #[doc = "Bit 23 - Peripheral 23 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid23(&mut self) -> PID23_W<23> { + pub fn pid23(&mut self) -> PID23_W { PID23_W::new(self) } #[doc = "Bit 24 - Peripheral 24 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid24(&mut self) -> PID24_W<24> { + pub fn pid24(&mut self) -> PID24_W { PID24_W::new(self) } #[doc = "Bit 25 - Peripheral 25 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid25(&mut self) -> PID25_W<25> { + pub fn pid25(&mut self) -> PID25_W { PID25_W::new(self) } #[doc = "Bit 26 - Peripheral 26 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid26(&mut self) -> PID26_W<26> { + pub fn pid26(&mut self) -> PID26_W { PID26_W::new(self) } #[doc = "Bit 27 - Peripheral 27 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid27(&mut self) -> PID27_W<27> { + pub fn pid27(&mut self) -> PID27_W { PID27_W::new(self) } #[doc = "Bit 28 - Peripheral 28 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid28(&mut self) -> PID28_W<28> { + pub fn pid28(&mut self) -> PID28_W { PID28_W::new(self) } #[doc = "Bit 29 - Peripheral 29 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid29(&mut self) -> PID29_W<29> { + pub fn pid29(&mut self) -> PID29_W { PID29_W::new(self) } #[doc = "Bit 30 - Peripheral 30 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid30(&mut self) -> PID30_W<30> { + pub fn pid30(&mut self) -> PID30_W { PID30_W::new(self) } #[doc = "Bit 31 - Peripheral 31 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid31(&mut self) -> PID31_W<31> { + pub fn pid31(&mut self) -> PID31_W { PID31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SleepWalking Disable Register 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_dr0](index.html) module"] +#[doc = "SleepWalking Disable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_dr0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_DR0_SPEC; impl crate::RegisterSpec for SLPWK_DR0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [slpwk_dr0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`slpwk_dr0::W`](W) writer structure"] impl crate::Writable for SLPWK_DR0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr1.rs index 29253c8b..e42c6568 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_dr1.rs @@ -1,240 +1,220 @@ #[doc = "Register `SLPWK_DR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID32` writer - Peripheral 32 SleepWalking Disable"] -pub type PID32_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID33` writer - Peripheral 33 SleepWalking Disable"] -pub type PID33_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID34` writer - Peripheral 34 SleepWalking Disable"] -pub type PID34_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID35` writer - Peripheral 35 SleepWalking Disable"] -pub type PID35_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID37` writer - Peripheral 37 SleepWalking Disable"] -pub type PID37_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID39` writer - Peripheral 39 SleepWalking Disable"] -pub type PID39_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID40` writer - Peripheral 40 SleepWalking Disable"] -pub type PID40_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID41` writer - Peripheral 41 SleepWalking Disable"] -pub type PID41_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID42` writer - Peripheral 42 SleepWalking Disable"] -pub type PID42_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID43` writer - Peripheral 43 SleepWalking Disable"] -pub type PID43_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID44` writer - Peripheral 44 SleepWalking Disable"] -pub type PID44_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID45` writer - Peripheral 45 SleepWalking Disable"] -pub type PID45_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID46` writer - Peripheral 46 SleepWalking Disable"] -pub type PID46_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID47` writer - Peripheral 47 SleepWalking Disable"] -pub type PID47_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID48` writer - Peripheral 48 SleepWalking Disable"] -pub type PID48_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID49` writer - Peripheral 49 SleepWalking Disable"] -pub type PID49_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID50` writer - Peripheral 50 SleepWalking Disable"] -pub type PID50_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID51` writer - Peripheral 51 SleepWalking Disable"] -pub type PID51_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID52` writer - Peripheral 52 SleepWalking Disable"] -pub type PID52_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID53` writer - Peripheral 53 SleepWalking Disable"] -pub type PID53_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID56` writer - Peripheral 56 SleepWalking Disable"] -pub type PID56_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID57` writer - Peripheral 57 SleepWalking Disable"] -pub type PID57_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID58` writer - Peripheral 58 SleepWalking Disable"] -pub type PID58_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID59` writer - Peripheral 59 SleepWalking Disable"] -pub type PID59_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID60` writer - Peripheral 60 SleepWalking Disable"] -pub type PID60_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_DR1_SPEC, O>; +pub type PID60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Peripheral 32 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid32(&mut self) -> PID32_W<0> { + pub fn pid32(&mut self) -> PID32_W { PID32_W::new(self) } #[doc = "Bit 1 - Peripheral 33 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid33(&mut self) -> PID33_W<1> { + pub fn pid33(&mut self) -> PID33_W { PID33_W::new(self) } #[doc = "Bit 2 - Peripheral 34 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid34(&mut self) -> PID34_W<2> { + pub fn pid34(&mut self) -> PID34_W { PID34_W::new(self) } #[doc = "Bit 3 - Peripheral 35 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid35(&mut self) -> PID35_W<3> { + pub fn pid35(&mut self) -> PID35_W { PID35_W::new(self) } #[doc = "Bit 5 - Peripheral 37 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid37(&mut self) -> PID37_W<5> { + pub fn pid37(&mut self) -> PID37_W { PID37_W::new(self) } #[doc = "Bit 7 - Peripheral 39 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid39(&mut self) -> PID39_W<7> { + pub fn pid39(&mut self) -> PID39_W { PID39_W::new(self) } #[doc = "Bit 8 - Peripheral 40 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid40(&mut self) -> PID40_W<8> { + pub fn pid40(&mut self) -> PID40_W { PID40_W::new(self) } #[doc = "Bit 9 - Peripheral 41 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid41(&mut self) -> PID41_W<9> { + pub fn pid41(&mut self) -> PID41_W { PID41_W::new(self) } #[doc = "Bit 10 - Peripheral 42 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid42(&mut self) -> PID42_W<10> { + pub fn pid42(&mut self) -> PID42_W { PID42_W::new(self) } #[doc = "Bit 11 - Peripheral 43 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid43(&mut self) -> PID43_W<11> { + pub fn pid43(&mut self) -> PID43_W { PID43_W::new(self) } #[doc = "Bit 12 - Peripheral 44 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid44(&mut self) -> PID44_W<12> { + pub fn pid44(&mut self) -> PID44_W { PID44_W::new(self) } #[doc = "Bit 13 - Peripheral 45 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid45(&mut self) -> PID45_W<13> { + pub fn pid45(&mut self) -> PID45_W { PID45_W::new(self) } #[doc = "Bit 14 - Peripheral 46 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid46(&mut self) -> PID46_W<14> { + pub fn pid46(&mut self) -> PID46_W { PID46_W::new(self) } #[doc = "Bit 15 - Peripheral 47 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid47(&mut self) -> PID47_W<15> { + pub fn pid47(&mut self) -> PID47_W { PID47_W::new(self) } #[doc = "Bit 16 - Peripheral 48 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid48(&mut self) -> PID48_W<16> { + pub fn pid48(&mut self) -> PID48_W { PID48_W::new(self) } #[doc = "Bit 17 - Peripheral 49 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid49(&mut self) -> PID49_W<17> { + pub fn pid49(&mut self) -> PID49_W { PID49_W::new(self) } #[doc = "Bit 18 - Peripheral 50 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid50(&mut self) -> PID50_W<18> { + pub fn pid50(&mut self) -> PID50_W { PID50_W::new(self) } #[doc = "Bit 19 - Peripheral 51 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid51(&mut self) -> PID51_W<19> { + pub fn pid51(&mut self) -> PID51_W { PID51_W::new(self) } #[doc = "Bit 20 - Peripheral 52 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid52(&mut self) -> PID52_W<20> { + pub fn pid52(&mut self) -> PID52_W { PID52_W::new(self) } #[doc = "Bit 21 - Peripheral 53 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid53(&mut self) -> PID53_W<21> { + pub fn pid53(&mut self) -> PID53_W { PID53_W::new(self) } #[doc = "Bit 24 - Peripheral 56 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid56(&mut self) -> PID56_W<24> { + pub fn pid56(&mut self) -> PID56_W { PID56_W::new(self) } #[doc = "Bit 25 - Peripheral 57 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid57(&mut self) -> PID57_W<25> { + pub fn pid57(&mut self) -> PID57_W { PID57_W::new(self) } #[doc = "Bit 26 - Peripheral 58 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid58(&mut self) -> PID58_W<26> { + pub fn pid58(&mut self) -> PID58_W { PID58_W::new(self) } #[doc = "Bit 27 - Peripheral 59 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid59(&mut self) -> PID59_W<27> { + pub fn pid59(&mut self) -> PID59_W { PID59_W::new(self) } #[doc = "Bit 28 - Peripheral 60 SleepWalking Disable"] #[inline(always)] #[must_use] - pub fn pid60(&mut self) -> PID60_W<28> { + pub fn pid60(&mut self) -> PID60_W { PID60_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SleepWalking Disable Register 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_dr1](index.html) module"] +#[doc = "SleepWalking Disable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_dr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_DR1_SPEC; impl crate::RegisterSpec for SLPWK_DR1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [slpwk_dr1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`slpwk_dr1::W`](W) writer structure"] impl crate::Writable for SLPWK_DR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er0.rs index c4c243ae..164b3b39 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er0.rs @@ -1,240 +1,220 @@ #[doc = "Register `SLPWK_ER0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID7` writer - Peripheral 7 SleepWalking Enable"] -pub type PID7_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID8` writer - Peripheral 8 SleepWalking Enable"] -pub type PID8_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID9` writer - Peripheral 9 SleepWalking Enable"] -pub type PID9_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID10` writer - Peripheral 10 SleepWalking Enable"] -pub type PID10_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID11` writer - Peripheral 11 SleepWalking Enable"] -pub type PID11_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID12` writer - Peripheral 12 SleepWalking Enable"] -pub type PID12_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID13` writer - Peripheral 13 SleepWalking Enable"] -pub type PID13_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID14` writer - Peripheral 14 SleepWalking Enable"] -pub type PID14_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID15` writer - Peripheral 15 SleepWalking Enable"] -pub type PID15_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID16` writer - Peripheral 16 SleepWalking Enable"] -pub type PID16_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID17` writer - Peripheral 17 SleepWalking Enable"] -pub type PID17_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID18` writer - Peripheral 18 SleepWalking Enable"] -pub type PID18_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID19` writer - Peripheral 19 SleepWalking Enable"] -pub type PID19_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID20` writer - Peripheral 20 SleepWalking Enable"] -pub type PID20_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID21` writer - Peripheral 21 SleepWalking Enable"] -pub type PID21_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID22` writer - Peripheral 22 SleepWalking Enable"] -pub type PID22_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID23` writer - Peripheral 23 SleepWalking Enable"] -pub type PID23_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID24` writer - Peripheral 24 SleepWalking Enable"] -pub type PID24_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID24_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID25` writer - Peripheral 25 SleepWalking Enable"] -pub type PID25_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID25_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID26` writer - Peripheral 26 SleepWalking Enable"] -pub type PID26_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID26_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID27` writer - Peripheral 27 SleepWalking Enable"] -pub type PID27_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID27_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID28` writer - Peripheral 28 SleepWalking Enable"] -pub type PID28_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID28_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID29` writer - Peripheral 29 SleepWalking Enable"] -pub type PID29_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID29_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID30` writer - Peripheral 30 SleepWalking Enable"] -pub type PID30_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID30_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID31` writer - Peripheral 31 SleepWalking Enable"] -pub type PID31_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER0_SPEC, O>; +pub type PID31_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 7 - Peripheral 7 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid7(&mut self) -> PID7_W<7> { + pub fn pid7(&mut self) -> PID7_W { PID7_W::new(self) } #[doc = "Bit 8 - Peripheral 8 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid8(&mut self) -> PID8_W<8> { + pub fn pid8(&mut self) -> PID8_W { PID8_W::new(self) } #[doc = "Bit 9 - Peripheral 9 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid9(&mut self) -> PID9_W<9> { + pub fn pid9(&mut self) -> PID9_W { PID9_W::new(self) } #[doc = "Bit 10 - Peripheral 10 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid10(&mut self) -> PID10_W<10> { + pub fn pid10(&mut self) -> PID10_W { PID10_W::new(self) } #[doc = "Bit 11 - Peripheral 11 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid11(&mut self) -> PID11_W<11> { + pub fn pid11(&mut self) -> PID11_W { PID11_W::new(self) } #[doc = "Bit 12 - Peripheral 12 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid12(&mut self) -> PID12_W<12> { + pub fn pid12(&mut self) -> PID12_W { PID12_W::new(self) } #[doc = "Bit 13 - Peripheral 13 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid13(&mut self) -> PID13_W<13> { + pub fn pid13(&mut self) -> PID13_W { PID13_W::new(self) } #[doc = "Bit 14 - Peripheral 14 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid14(&mut self) -> PID14_W<14> { + pub fn pid14(&mut self) -> PID14_W { PID14_W::new(self) } #[doc = "Bit 15 - Peripheral 15 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid15(&mut self) -> PID15_W<15> { + pub fn pid15(&mut self) -> PID15_W { PID15_W::new(self) } #[doc = "Bit 16 - Peripheral 16 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid16(&mut self) -> PID16_W<16> { + pub fn pid16(&mut self) -> PID16_W { PID16_W::new(self) } #[doc = "Bit 17 - Peripheral 17 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid17(&mut self) -> PID17_W<17> { + pub fn pid17(&mut self) -> PID17_W { PID17_W::new(self) } #[doc = "Bit 18 - Peripheral 18 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid18(&mut self) -> PID18_W<18> { + pub fn pid18(&mut self) -> PID18_W { PID18_W::new(self) } #[doc = "Bit 19 - Peripheral 19 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid19(&mut self) -> PID19_W<19> { + pub fn pid19(&mut self) -> PID19_W { PID19_W::new(self) } #[doc = "Bit 20 - Peripheral 20 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid20(&mut self) -> PID20_W<20> { + pub fn pid20(&mut self) -> PID20_W { PID20_W::new(self) } #[doc = "Bit 21 - Peripheral 21 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid21(&mut self) -> PID21_W<21> { + pub fn pid21(&mut self) -> PID21_W { PID21_W::new(self) } #[doc = "Bit 22 - Peripheral 22 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid22(&mut self) -> PID22_W<22> { + pub fn pid22(&mut self) -> PID22_W { PID22_W::new(self) } #[doc = "Bit 23 - Peripheral 23 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid23(&mut self) -> PID23_W<23> { + pub fn pid23(&mut self) -> PID23_W { PID23_W::new(self) } #[doc = "Bit 24 - Peripheral 24 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid24(&mut self) -> PID24_W<24> { + pub fn pid24(&mut self) -> PID24_W { PID24_W::new(self) } #[doc = "Bit 25 - Peripheral 25 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid25(&mut self) -> PID25_W<25> { + pub fn pid25(&mut self) -> PID25_W { PID25_W::new(self) } #[doc = "Bit 26 - Peripheral 26 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid26(&mut self) -> PID26_W<26> { + pub fn pid26(&mut self) -> PID26_W { PID26_W::new(self) } #[doc = "Bit 27 - Peripheral 27 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid27(&mut self) -> PID27_W<27> { + pub fn pid27(&mut self) -> PID27_W { PID27_W::new(self) } #[doc = "Bit 28 - Peripheral 28 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid28(&mut self) -> PID28_W<28> { + pub fn pid28(&mut self) -> PID28_W { PID28_W::new(self) } #[doc = "Bit 29 - Peripheral 29 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid29(&mut self) -> PID29_W<29> { + pub fn pid29(&mut self) -> PID29_W { PID29_W::new(self) } #[doc = "Bit 30 - Peripheral 30 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid30(&mut self) -> PID30_W<30> { + pub fn pid30(&mut self) -> PID30_W { PID30_W::new(self) } #[doc = "Bit 31 - Peripheral 31 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid31(&mut self) -> PID31_W<31> { + pub fn pid31(&mut self) -> PID31_W { PID31_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SleepWalking Enable Register 0\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_er0](index.html) module"] +#[doc = "SleepWalking Enable Register 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_er0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_ER0_SPEC; impl crate::RegisterSpec for SLPWK_ER0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [slpwk_er0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`slpwk_er0::W`](W) writer structure"] impl crate::Writable for SLPWK_ER0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er1.rs index 2c1dcc28..8cd5edd0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_er1.rs @@ -1,240 +1,220 @@ #[doc = "Register `SLPWK_ER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PID32` writer - Peripheral 32 SleepWalking Enable"] -pub type PID32_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID32_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID33` writer - Peripheral 33 SleepWalking Enable"] -pub type PID33_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID33_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID34` writer - Peripheral 34 SleepWalking Enable"] -pub type PID34_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID34_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID35` writer - Peripheral 35 SleepWalking Enable"] -pub type PID35_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID35_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID37` writer - Peripheral 37 SleepWalking Enable"] -pub type PID37_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID37_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID39` writer - Peripheral 39 SleepWalking Enable"] -pub type PID39_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID39_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID40` writer - Peripheral 40 SleepWalking Enable"] -pub type PID40_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID40_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID41` writer - Peripheral 41 SleepWalking Enable"] -pub type PID41_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID41_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID42` writer - Peripheral 42 SleepWalking Enable"] -pub type PID42_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID42_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID43` writer - Peripheral 43 SleepWalking Enable"] -pub type PID43_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID43_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID44` writer - Peripheral 44 SleepWalking Enable"] -pub type PID44_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID44_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID45` writer - Peripheral 45 SleepWalking Enable"] -pub type PID45_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID45_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID46` writer - Peripheral 46 SleepWalking Enable"] -pub type PID46_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID46_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID47` writer - Peripheral 47 SleepWalking Enable"] -pub type PID47_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID47_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID48` writer - Peripheral 48 SleepWalking Enable"] -pub type PID48_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID48_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID49` writer - Peripheral 49 SleepWalking Enable"] -pub type PID49_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID49_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID50` writer - Peripheral 50 SleepWalking Enable"] -pub type PID50_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID50_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID51` writer - Peripheral 51 SleepWalking Enable"] -pub type PID51_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID51_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID52` writer - Peripheral 52 SleepWalking Enable"] -pub type PID52_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID52_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID53` writer - Peripheral 53 SleepWalking Enable"] -pub type PID53_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID53_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID56` writer - Peripheral 56 SleepWalking Enable"] -pub type PID56_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID56_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID57` writer - Peripheral 57 SleepWalking Enable"] -pub type PID57_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID57_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID58` writer - Peripheral 58 SleepWalking Enable"] -pub type PID58_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID58_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID59` writer - Peripheral 59 SleepWalking Enable"] -pub type PID59_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID59_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID60` writer - Peripheral 60 SleepWalking Enable"] -pub type PID60_W<'a, const O: u8> = crate::BitWriter<'a, SLPWK_ER1_SPEC, O>; +pub type PID60_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Peripheral 32 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid32(&mut self) -> PID32_W<0> { + pub fn pid32(&mut self) -> PID32_W { PID32_W::new(self) } #[doc = "Bit 1 - Peripheral 33 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid33(&mut self) -> PID33_W<1> { + pub fn pid33(&mut self) -> PID33_W { PID33_W::new(self) } #[doc = "Bit 2 - Peripheral 34 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid34(&mut self) -> PID34_W<2> { + pub fn pid34(&mut self) -> PID34_W { PID34_W::new(self) } #[doc = "Bit 3 - Peripheral 35 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid35(&mut self) -> PID35_W<3> { + pub fn pid35(&mut self) -> PID35_W { PID35_W::new(self) } #[doc = "Bit 5 - Peripheral 37 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid37(&mut self) -> PID37_W<5> { + pub fn pid37(&mut self) -> PID37_W { PID37_W::new(self) } #[doc = "Bit 7 - Peripheral 39 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid39(&mut self) -> PID39_W<7> { + pub fn pid39(&mut self) -> PID39_W { PID39_W::new(self) } #[doc = "Bit 8 - Peripheral 40 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid40(&mut self) -> PID40_W<8> { + pub fn pid40(&mut self) -> PID40_W { PID40_W::new(self) } #[doc = "Bit 9 - Peripheral 41 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid41(&mut self) -> PID41_W<9> { + pub fn pid41(&mut self) -> PID41_W { PID41_W::new(self) } #[doc = "Bit 10 - Peripheral 42 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid42(&mut self) -> PID42_W<10> { + pub fn pid42(&mut self) -> PID42_W { PID42_W::new(self) } #[doc = "Bit 11 - Peripheral 43 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid43(&mut self) -> PID43_W<11> { + pub fn pid43(&mut self) -> PID43_W { PID43_W::new(self) } #[doc = "Bit 12 - Peripheral 44 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid44(&mut self) -> PID44_W<12> { + pub fn pid44(&mut self) -> PID44_W { PID44_W::new(self) } #[doc = "Bit 13 - Peripheral 45 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid45(&mut self) -> PID45_W<13> { + pub fn pid45(&mut self) -> PID45_W { PID45_W::new(self) } #[doc = "Bit 14 - Peripheral 46 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid46(&mut self) -> PID46_W<14> { + pub fn pid46(&mut self) -> PID46_W { PID46_W::new(self) } #[doc = "Bit 15 - Peripheral 47 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid47(&mut self) -> PID47_W<15> { + pub fn pid47(&mut self) -> PID47_W { PID47_W::new(self) } #[doc = "Bit 16 - Peripheral 48 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid48(&mut self) -> PID48_W<16> { + pub fn pid48(&mut self) -> PID48_W { PID48_W::new(self) } #[doc = "Bit 17 - Peripheral 49 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid49(&mut self) -> PID49_W<17> { + pub fn pid49(&mut self) -> PID49_W { PID49_W::new(self) } #[doc = "Bit 18 - Peripheral 50 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid50(&mut self) -> PID50_W<18> { + pub fn pid50(&mut self) -> PID50_W { PID50_W::new(self) } #[doc = "Bit 19 - Peripheral 51 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid51(&mut self) -> PID51_W<19> { + pub fn pid51(&mut self) -> PID51_W { PID51_W::new(self) } #[doc = "Bit 20 - Peripheral 52 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid52(&mut self) -> PID52_W<20> { + pub fn pid52(&mut self) -> PID52_W { PID52_W::new(self) } #[doc = "Bit 21 - Peripheral 53 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid53(&mut self) -> PID53_W<21> { + pub fn pid53(&mut self) -> PID53_W { PID53_W::new(self) } #[doc = "Bit 24 - Peripheral 56 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid56(&mut self) -> PID56_W<24> { + pub fn pid56(&mut self) -> PID56_W { PID56_W::new(self) } #[doc = "Bit 25 - Peripheral 57 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid57(&mut self) -> PID57_W<25> { + pub fn pid57(&mut self) -> PID57_W { PID57_W::new(self) } #[doc = "Bit 26 - Peripheral 58 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid58(&mut self) -> PID58_W<26> { + pub fn pid58(&mut self) -> PID58_W { PID58_W::new(self) } #[doc = "Bit 27 - Peripheral 59 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid59(&mut self) -> PID59_W<27> { + pub fn pid59(&mut self) -> PID59_W { PID59_W::new(self) } #[doc = "Bit 28 - Peripheral 60 SleepWalking Enable"] #[inline(always)] #[must_use] - pub fn pid60(&mut self) -> PID60_W<28> { + pub fn pid60(&mut self) -> PID60_W { PID60_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SleepWalking Enable Register 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_er1](index.html) module"] +#[doc = "SleepWalking Enable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slpwk_er1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_ER1_SPEC; impl crate::RegisterSpec for SLPWK_ER1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [slpwk_er1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`slpwk_er1::W`](W) writer structure"] impl crate::Writable for SLPWK_ER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr0.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr0.rs index 02140c47..316318a0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr0.rs @@ -1,18 +1,5 @@ #[doc = "Register `SLPWK_SR0` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PID7` reader - Peripheral 7 SleepWalking Status"] pub type PID7_R = crate::BitReader; #[doc = "Field `PID8` reader - Peripheral 8 SleepWalking Status"] @@ -190,15 +177,13 @@ impl R { PID31_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "SleepWalking Status Register 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_sr0](index.html) module"] +#[doc = "SleepWalking Status Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_sr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_SR0_SPEC; impl crate::RegisterSpec for SLPWK_SR0_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slpwk_sr0::R](R) reader structure"] -impl crate::Readable for SLPWK_SR0_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`slpwk_sr0::R`](R) reader structure"] +impl crate::Readable for SLPWK_SR0_SPEC {} #[doc = "`reset()` method sets SLPWK_SR0 to value 0"] impl crate::Resettable for SLPWK_SR0_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr1.rs b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr1.rs index 6cc72d8c..7483d18e 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/slpwk_sr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `SLPWK_SR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `PID32` reader - Peripheral 32 SleepWalking Status"] pub type PID32_R = crate::BitReader; #[doc = "Field `PID33` reader - Peripheral 33 SleepWalking Status"] @@ -190,15 +177,13 @@ impl R { PID60_R::new(((self.bits >> 28) & 1) != 0) } } -#[doc = "SleepWalking Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slpwk_sr1](index.html) module"] +#[doc = "SleepWalking Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slpwk_sr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SLPWK_SR1_SPEC; impl crate::RegisterSpec for SLPWK_SR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [slpwk_sr1::R](R) reader structure"] -impl crate::Readable for SLPWK_SR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`slpwk_sr1::R`](R) reader structure"] +impl crate::Readable for SLPWK_SR1_SPEC {} #[doc = "`reset()` method sets SLPWK_SR1 to value 0"] impl crate::Resettable for SLPWK_SR1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/sr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/sr.rs index cc14d952..ac89e47b 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MOSCXTS` reader - Main Crystal Oscillator Status"] pub type MOSCXTS_R = crate::BitReader; #[doc = "Field `LOCKA` reader - PLLA Lock Status"] @@ -148,15 +135,13 @@ impl R { XT32KERR_R::new(((self.bits >> 21) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/usb.rs b/arch/cortex-m/samv71q21-pac/src/pmc/usb.rs index c80d2fcc..8ecb07da 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/usb.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/usb.rs @@ -1,47 +1,15 @@ #[doc = "Register `USB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `USB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USBS` reader - USB Input Clock Selection"] pub type USBS_R = crate::BitReader; #[doc = "Field `USBS` writer - USB Input Clock Selection"] -pub type USBS_W<'a, const O: u8> = crate::BitWriter<'a, USB_SPEC, O>; +pub type USBS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBDIV` reader - Divider for USB_48M"] pub type USBDIV_R = crate::FieldReader; #[doc = "Field `USBDIV` writer - Divider for USB_48M"] -pub type USBDIV_W<'a, const O: u8> = crate::FieldWriter<'a, USB_SPEC, 4, O>; +pub type USBDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - USB Input Clock Selection"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 0 - USB Input Clock Selection"] #[inline(always)] #[must_use] - pub fn usbs(&mut self) -> USBS_W<0> { + pub fn usbs(&mut self) -> USBS_W { USBS_W::new(self) } #[doc = "Bits 8:11 - Divider for USB_48M"] #[inline(always)] #[must_use] - pub fn usbdiv(&mut self) -> USBDIV_W<8> { + pub fn usbdiv(&mut self) -> USBDIV_W { USBDIV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "USB Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usb](index.html) module"] +#[doc = "USB Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct USB_SPEC; impl crate::RegisterSpec for USB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [usb::R](R) reader structure"] -impl crate::Readable for USB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [usb::W](W) writer structure"] +#[doc = "`read()` method returns [`usb::R`](R) reader structure"] +impl crate::Readable for USB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb::W`](W) writer structure"] impl crate::Writable for USB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/wpmr.rs index acc4de19..4d0548f7 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pmc/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/pmc/wpsr.rs index 69b9952f..216a7a8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/pmc/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pmc/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0.rs b/arch/cortex-m/samv71q21-pac/src/pwm0.rs index 1ac23610..349bb1dc 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0.rs @@ -105,143 +105,178 @@ pub struct RegisterBlock { #[doc = "0x460 - PWM Channel Mode Update Register (ch_num = 3)"] pub cmupd3: CMUPD3, } -#[doc = "CLK (rw) register accessor: an alias for `Reg`"] +#[doc = "CLK (rw) register accessor: PWM Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`clk`] +module"] pub type CLK = crate::Reg; #[doc = "PWM Clock Register"] pub mod clk; -#[doc = "ENA (w) register accessor: an alias for `Reg`"] +#[doc = "ENA (w) register accessor: PWM Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ena::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ena`] +module"] pub type ENA = crate::Reg; #[doc = "PWM Enable Register"] pub mod ena; -#[doc = "DIS (w) register accessor: an alias for `Reg`"] +#[doc = "DIS (w) register accessor: PWM Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dis::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dis`] +module"] pub type DIS = crate::Reg; #[doc = "PWM Disable Register"] pub mod dis; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: PWM Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "PWM Status Register"] pub mod sr; -#[doc = "IER1 (w) register accessor: an alias for `Reg`"] +#[doc = "IER1 (w) register accessor: PWM Interrupt Enable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier1`] +module"] pub type IER1 = crate::Reg; #[doc = "PWM Interrupt Enable Register 1"] pub mod ier1; -#[doc = "IDR1 (w) register accessor: an alias for `Reg`"] +#[doc = "IDR1 (w) register accessor: PWM Interrupt Disable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr1`] +module"] pub type IDR1 = crate::Reg; #[doc = "PWM Interrupt Disable Register 1"] pub mod idr1; -#[doc = "IMR1 (r) register accessor: an alias for `Reg`"] +#[doc = "IMR1 (r) register accessor: PWM Interrupt Mask Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr1`] +module"] pub type IMR1 = crate::Reg; #[doc = "PWM Interrupt Mask Register 1"] pub mod imr1; -#[doc = "ISR1 (r) register accessor: an alias for `Reg`"] +#[doc = "ISR1 (r) register accessor: PWM Interrupt Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr1`] +module"] pub type ISR1 = crate::Reg; #[doc = "PWM Interrupt Status Register 1"] pub mod isr1; -#[doc = "SCM (rw) register accessor: an alias for `Reg`"] +#[doc = "SCM (rw) register accessor: PWM Sync Channels Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scm`] +module"] pub type SCM = crate::Reg; #[doc = "PWM Sync Channels Mode Register"] pub mod scm; -#[doc = "DMAR (w) register accessor: an alias for `Reg`"] +#[doc = "DMAR (w) register accessor: PWM DMA Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmar::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dmar`] +module"] pub type DMAR = crate::Reg; #[doc = "PWM DMA Register"] pub mod dmar; -#[doc = "SCUC (rw) register accessor: an alias for `Reg`"] +#[doc = "SCUC (rw) register accessor: PWM Sync Channels Update Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scuc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scuc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scuc`] +module"] pub type SCUC = crate::Reg; #[doc = "PWM Sync Channels Update Control Register"] pub mod scuc; -#[doc = "SCUP (rw) register accessor: an alias for `Reg`"] +#[doc = "SCUP (rw) register accessor: PWM Sync Channels Update Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scup`] +module"] pub type SCUP = crate::Reg; #[doc = "PWM Sync Channels Update Period Register"] pub mod scup; -#[doc = "SCUPUPD (w) register accessor: an alias for `Reg`"] +#[doc = "SCUPUPD (w) register accessor: PWM Sync Channels Update Period Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scupupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scupupd`] +module"] pub type SCUPUPD = crate::Reg; #[doc = "PWM Sync Channels Update Period Update Register"] pub mod scupupd; -#[doc = "IER2 (w) register accessor: an alias for `Reg`"] +#[doc = "IER2 (w) register accessor: PWM Interrupt Enable Register 2\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier2`] +module"] pub type IER2 = crate::Reg; #[doc = "PWM Interrupt Enable Register 2"] pub mod ier2; -#[doc = "IDR2 (w) register accessor: an alias for `Reg`"] +#[doc = "IDR2 (w) register accessor: PWM Interrupt Disable Register 2\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr2`] +module"] pub type IDR2 = crate::Reg; #[doc = "PWM Interrupt Disable Register 2"] pub mod idr2; -#[doc = "IMR2 (r) register accessor: an alias for `Reg`"] +#[doc = "IMR2 (r) register accessor: PWM Interrupt Mask Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr2`] +module"] pub type IMR2 = crate::Reg; #[doc = "PWM Interrupt Mask Register 2"] pub mod imr2; -#[doc = "ISR2 (r) register accessor: an alias for `Reg`"] +#[doc = "ISR2 (r) register accessor: PWM Interrupt Status Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr2`] +module"] pub type ISR2 = crate::Reg; #[doc = "PWM Interrupt Status Register 2"] pub mod isr2; -#[doc = "OOV (rw) register accessor: an alias for `Reg`"] +#[doc = "OOV (rw) register accessor: PWM Output Override Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oov::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oov::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`oov`] +module"] pub type OOV = crate::Reg; #[doc = "PWM Output Override Value Register"] pub mod oov; -#[doc = "OS (rw) register accessor: an alias for `Reg`"] +#[doc = "OS (rw) register accessor: PWM Output Selection Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`os::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`os::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`os`] +module"] pub type OS = crate::Reg; #[doc = "PWM Output Selection Register"] pub mod os; -#[doc = "OSS (w) register accessor: an alias for `Reg`"] +#[doc = "OSS (w) register accessor: PWM Output Selection Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oss::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`oss`] +module"] pub type OSS = crate::Reg; #[doc = "PWM Output Selection Set Register"] pub mod oss; -#[doc = "OSC (w) register accessor: an alias for `Reg`"] +#[doc = "OSC (w) register accessor: PWM Output Selection Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`osc::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`osc`] +module"] pub type OSC = crate::Reg; #[doc = "PWM Output Selection Clear Register"] pub mod osc; -#[doc = "OSSUPD (w) register accessor: an alias for `Reg`"] +#[doc = "OSSUPD (w) register accessor: PWM Output Selection Set Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ossupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ossupd`] +module"] pub type OSSUPD = crate::Reg; #[doc = "PWM Output Selection Set Update Register"] pub mod ossupd; -#[doc = "OSCUPD (w) register accessor: an alias for `Reg`"] +#[doc = "OSCUPD (w) register accessor: PWM Output Selection Clear Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oscupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`oscupd`] +module"] pub type OSCUPD = crate::Reg; #[doc = "PWM Output Selection Clear Update Register"] pub mod oscupd; -#[doc = "FMR (rw) register accessor: an alias for `Reg`"] +#[doc = "FMR (rw) register accessor: PWM Fault Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fmr`] +module"] pub type FMR = crate::Reg; #[doc = "PWM Fault Mode Register"] pub mod fmr; -#[doc = "FSR (r) register accessor: an alias for `Reg`"] +#[doc = "FSR (r) register accessor: PWM Fault Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fsr`] +module"] pub type FSR = crate::Reg; #[doc = "PWM Fault Status Register"] pub mod fsr; -#[doc = "FCR (w) register accessor: an alias for `Reg`"] +#[doc = "FCR (w) register accessor: PWM Fault Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fcr`] +module"] pub type FCR = crate::Reg; #[doc = "PWM Fault Clear Register"] pub mod fcr; -#[doc = "FPV1 (rw) register accessor: an alias for `Reg`"] +#[doc = "FPV1 (rw) register accessor: PWM Fault Protection Value Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpv1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpv1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fpv1`] +module"] pub type FPV1 = crate::Reg; #[doc = "PWM Fault Protection Value Register 1"] pub mod fpv1; -#[doc = "FPE (rw) register accessor: an alias for `Reg`"] +#[doc = "FPE (rw) register accessor: PWM Fault Protection Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fpe`] +module"] pub type FPE = crate::Reg; #[doc = "PWM Fault Protection Enable Register"] pub mod fpe; -#[doc = "ELMR (rw) register accessor: an alias for `Reg`"] +#[doc = "ELMR (rw) register accessor: PWM Event Line 0 Mode Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`elmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`elmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`elmr`] +module"] pub type ELMR = crate::Reg; #[doc = "PWM Event Line 0 Mode Register 0"] pub mod elmr; -#[doc = "SSPR (rw) register accessor: an alias for `Reg`"] +#[doc = "SSPR (rw) register accessor: PWM Spread Spectrum Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sspr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sspr`] +module"] pub type SSPR = crate::Reg; #[doc = "PWM Spread Spectrum Register"] pub mod sspr; -#[doc = "SSPUP (w) register accessor: an alias for `Reg`"] +#[doc = "SSPUP (w) register accessor: PWM Spread Spectrum Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspup::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sspup`] +module"] pub type SSPUP = crate::Reg; #[doc = "PWM Spread Spectrum Update Register"] pub mod sspup; -#[doc = "SMMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SMMR (rw) register accessor: PWM Stepper Motor Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smmr`] +module"] pub type SMMR = crate::Reg; #[doc = "PWM Stepper Motor Mode Register"] pub mod smmr; -#[doc = "FPV2 (rw) register accessor: an alias for `Reg`"] +#[doc = "FPV2 (rw) register accessor: PWM Fault Protection Value 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpv2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpv2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fpv2`] +module"] pub type FPV2 = crate::Reg; #[doc = "PWM Fault Protection Value 2 Register"] pub mod fpv2; -#[doc = "WPCR (w) register accessor: an alias for `Reg`"] +#[doc = "WPCR (w) register accessor: PWM Write Protection Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpcr`] +module"] pub type WPCR = crate::Reg; #[doc = "PWM Write Protection Control Register"] pub mod wpcr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: PWM Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "PWM Write Protection Status Register"] pub mod wpsr; @@ -255,35 +290,43 @@ pub use self::pwm_ch_num::PWM_CH_NUM; #[doc = r"Cluster"] #[doc = "PWM Channel Mode Register"] pub mod pwm_ch_num; -#[doc = "CMUPD0 (w) register accessor: an alias for `Reg`"] +#[doc = "CMUPD0 (w) register accessor: PWM Channel Mode Update Register (ch_num = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmupd0`] +module"] pub type CMUPD0 = crate::Reg; #[doc = "PWM Channel Mode Update Register (ch_num = 0)"] pub mod cmupd0; -#[doc = "CMUPD1 (w) register accessor: an alias for `Reg`"] +#[doc = "CMUPD1 (w) register accessor: PWM Channel Mode Update Register (ch_num = 1)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmupd1`] +module"] pub type CMUPD1 = crate::Reg; #[doc = "PWM Channel Mode Update Register (ch_num = 1)"] pub mod cmupd1; -#[doc = "ETRG1 (rw) register accessor: an alias for `Reg`"] +#[doc = "ETRG1 (rw) register accessor: PWM External Trigger Register (trg_num = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etrg1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etrg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etrg1`] +module"] pub type ETRG1 = crate::Reg; #[doc = "PWM External Trigger Register (trg_num = 1)"] pub mod etrg1; -#[doc = "LEBR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "LEBR1 (rw) register accessor: PWM Leading-Edge Blanking Register (trg_num = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lebr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lebr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lebr1`] +module"] pub type LEBR1 = crate::Reg; #[doc = "PWM Leading-Edge Blanking Register (trg_num = 1)"] pub mod lebr1; -#[doc = "CMUPD2 (w) register accessor: an alias for `Reg`"] +#[doc = "CMUPD2 (w) register accessor: PWM Channel Mode Update Register (ch_num = 2)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmupd2`] +module"] pub type CMUPD2 = crate::Reg; #[doc = "PWM Channel Mode Update Register (ch_num = 2)"] pub mod cmupd2; -#[doc = "ETRG2 (rw) register accessor: an alias for `Reg`"] +#[doc = "ETRG2 (rw) register accessor: PWM External Trigger Register (trg_num = 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etrg2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etrg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`etrg2`] +module"] pub type ETRG2 = crate::Reg; #[doc = "PWM External Trigger Register (trg_num = 2)"] pub mod etrg2; -#[doc = "LEBR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "LEBR2 (rw) register accessor: PWM Leading-Edge Blanking Register (trg_num = 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lebr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lebr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`lebr2`] +module"] pub type LEBR2 = crate::Reg; #[doc = "PWM Leading-Edge Blanking Register (trg_num = 2)"] pub mod lebr2; -#[doc = "CMUPD3 (w) register accessor: an alias for `Reg`"] +#[doc = "CMUPD3 (w) register accessor: PWM Channel Mode Update Register (ch_num = 3)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd3::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmupd3`] +module"] pub type CMUPD3 = crate::Reg; #[doc = "PWM Channel Mode Update Register (ch_num = 3)"] pub mod cmupd3; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/clk.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/clk.rs index 430ab195..f22f1e44 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/clk.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/clk.rs @@ -1,39 +1,7 @@ #[doc = "Register `CLK` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CLK` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIVA` reader - CLKA Divide Factor"] pub type DIVA_R = crate::FieldReader; #[doc = "CLKA Divide Factor\n\nValue on reset: 0"] @@ -64,28 +32,32 @@ impl DIVA_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKA_POFF`"] + #[doc = "CLKA clock is turned off"] #[inline(always)] pub fn is_clka_poff(&self) -> bool { *self == DIVASELECT_A::CLKA_POFF } - #[doc = "Checks if the value of the field is `PREA`"] + #[doc = "CLKA clock is clock selected by PREA"] #[inline(always)] pub fn is_prea(&self) -> bool { *self == DIVASELECT_A::PREA } } #[doc = "Field `DIVA` writer - CLKA Divide Factor"] -pub type DIVA_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SPEC, 8, O, DIVASELECT_A>; -impl<'a, const O: u8> DIVA_W<'a, O> { +pub type DIVA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, DIVASELECT_A>; +impl<'a, REG, const O: u8> DIVA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "CLKA clock is turned off"] #[inline(always)] - pub fn clka_poff(self) -> &'a mut W { + pub fn clka_poff(self) -> &'a mut crate::W { self.variant(DIVASELECT_A::CLKA_POFF) } #[doc = "CLKA clock is clock selected by PREA"] #[inline(always)] - pub fn prea(self) -> &'a mut W { + pub fn prea(self) -> &'a mut crate::W { self.variant(DIVASELECT_A::PREA) } } @@ -146,118 +118,122 @@ impl PREA_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLK`"] + #[doc = "Peripheral clock"] #[inline(always)] pub fn is_clk(&self) -> bool { *self == PREASELECT_A::CLK } - #[doc = "Checks if the value of the field is `CLK_DIV2`"] + #[doc = "Peripheral clock/2"] #[inline(always)] pub fn is_clk_div2(&self) -> bool { *self == PREASELECT_A::CLK_DIV2 } - #[doc = "Checks if the value of the field is `CLK_DIV4`"] + #[doc = "Peripheral clock/4"] #[inline(always)] pub fn is_clk_div4(&self) -> bool { *self == PREASELECT_A::CLK_DIV4 } - #[doc = "Checks if the value of the field is `CLK_DIV8`"] + #[doc = "Peripheral clock/8"] #[inline(always)] pub fn is_clk_div8(&self) -> bool { *self == PREASELECT_A::CLK_DIV8 } - #[doc = "Checks if the value of the field is `CLK_DIV16`"] + #[doc = "Peripheral clock/16"] #[inline(always)] pub fn is_clk_div16(&self) -> bool { *self == PREASELECT_A::CLK_DIV16 } - #[doc = "Checks if the value of the field is `CLK_DIV32`"] + #[doc = "Peripheral clock/32"] #[inline(always)] pub fn is_clk_div32(&self) -> bool { *self == PREASELECT_A::CLK_DIV32 } - #[doc = "Checks if the value of the field is `CLK_DIV64`"] + #[doc = "Peripheral clock/64"] #[inline(always)] pub fn is_clk_div64(&self) -> bool { *self == PREASELECT_A::CLK_DIV64 } - #[doc = "Checks if the value of the field is `CLK_DIV128`"] + #[doc = "Peripheral clock/128"] #[inline(always)] pub fn is_clk_div128(&self) -> bool { *self == PREASELECT_A::CLK_DIV128 } - #[doc = "Checks if the value of the field is `CLK_DIV256`"] + #[doc = "Peripheral clock/256"] #[inline(always)] pub fn is_clk_div256(&self) -> bool { *self == PREASELECT_A::CLK_DIV256 } - #[doc = "Checks if the value of the field is `CLK_DIV512`"] + #[doc = "Peripheral clock/512"] #[inline(always)] pub fn is_clk_div512(&self) -> bool { *self == PREASELECT_A::CLK_DIV512 } - #[doc = "Checks if the value of the field is `CLK_DIV1024`"] + #[doc = "Peripheral clock/1024"] #[inline(always)] pub fn is_clk_div1024(&self) -> bool { *self == PREASELECT_A::CLK_DIV1024 } } #[doc = "Field `PREA` writer - CLKA Source Clock Selection"] -pub type PREA_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SPEC, 4, O, PREASELECT_A>; -impl<'a, const O: u8> PREA_W<'a, O> { +pub type PREA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, PREASELECT_A>; +impl<'a, REG, const O: u8> PREA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Peripheral clock"] #[inline(always)] - pub fn clk(self) -> &'a mut W { + pub fn clk(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK) } #[doc = "Peripheral clock/2"] #[inline(always)] - pub fn clk_div2(self) -> &'a mut W { + pub fn clk_div2(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV2) } #[doc = "Peripheral clock/4"] #[inline(always)] - pub fn clk_div4(self) -> &'a mut W { + pub fn clk_div4(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV4) } #[doc = "Peripheral clock/8"] #[inline(always)] - pub fn clk_div8(self) -> &'a mut W { + pub fn clk_div8(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV8) } #[doc = "Peripheral clock/16"] #[inline(always)] - pub fn clk_div16(self) -> &'a mut W { + pub fn clk_div16(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV16) } #[doc = "Peripheral clock/32"] #[inline(always)] - pub fn clk_div32(self) -> &'a mut W { + pub fn clk_div32(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV32) } #[doc = "Peripheral clock/64"] #[inline(always)] - pub fn clk_div64(self) -> &'a mut W { + pub fn clk_div64(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV64) } #[doc = "Peripheral clock/128"] #[inline(always)] - pub fn clk_div128(self) -> &'a mut W { + pub fn clk_div128(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV128) } #[doc = "Peripheral clock/256"] #[inline(always)] - pub fn clk_div256(self) -> &'a mut W { + pub fn clk_div256(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV256) } #[doc = "Peripheral clock/512"] #[inline(always)] - pub fn clk_div512(self) -> &'a mut W { + pub fn clk_div512(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV512) } #[doc = "Peripheral clock/1024"] #[inline(always)] - pub fn clk_div1024(self) -> &'a mut W { + pub fn clk_div1024(self) -> &'a mut crate::W { self.variant(PREASELECT_A::CLK_DIV1024) } } @@ -291,28 +267,32 @@ impl DIVB_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLKB_POFF`"] + #[doc = "CLKB clock is turned off"] #[inline(always)] pub fn is_clkb_poff(&self) -> bool { *self == DIVBSELECT_A::CLKB_POFF } - #[doc = "Checks if the value of the field is `PREB`"] + #[doc = "CLKB clock is clock selected by PREB"] #[inline(always)] pub fn is_preb(&self) -> bool { *self == DIVBSELECT_A::PREB } } #[doc = "Field `DIVB` writer - CLKB Divide Factor"] -pub type DIVB_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SPEC, 8, O, DIVBSELECT_A>; -impl<'a, const O: u8> DIVB_W<'a, O> { +pub type DIVB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, DIVBSELECT_A>; +impl<'a, REG, const O: u8> DIVB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "CLKB clock is turned off"] #[inline(always)] - pub fn clkb_poff(self) -> &'a mut W { + pub fn clkb_poff(self) -> &'a mut crate::W { self.variant(DIVBSELECT_A::CLKB_POFF) } #[doc = "CLKB clock is clock selected by PREB"] #[inline(always)] - pub fn preb(self) -> &'a mut W { + pub fn preb(self) -> &'a mut crate::W { self.variant(DIVBSELECT_A::PREB) } } @@ -373,118 +353,122 @@ impl PREB_R { _ => None, } } - #[doc = "Checks if the value of the field is `CLK`"] + #[doc = "Peripheral clock"] #[inline(always)] pub fn is_clk(&self) -> bool { *self == PREBSELECT_A::CLK } - #[doc = "Checks if the value of the field is `CLK_DIV2`"] + #[doc = "Peripheral clock/2"] #[inline(always)] pub fn is_clk_div2(&self) -> bool { *self == PREBSELECT_A::CLK_DIV2 } - #[doc = "Checks if the value of the field is `CLK_DIV4`"] + #[doc = "Peripheral clock/4"] #[inline(always)] pub fn is_clk_div4(&self) -> bool { *self == PREBSELECT_A::CLK_DIV4 } - #[doc = "Checks if the value of the field is `CLK_DIV8`"] + #[doc = "Peripheral clock/8"] #[inline(always)] pub fn is_clk_div8(&self) -> bool { *self == PREBSELECT_A::CLK_DIV8 } - #[doc = "Checks if the value of the field is `CLK_DIV16`"] + #[doc = "Peripheral clock/16"] #[inline(always)] pub fn is_clk_div16(&self) -> bool { *self == PREBSELECT_A::CLK_DIV16 } - #[doc = "Checks if the value of the field is `CLK_DIV32`"] + #[doc = "Peripheral clock/32"] #[inline(always)] pub fn is_clk_div32(&self) -> bool { *self == PREBSELECT_A::CLK_DIV32 } - #[doc = "Checks if the value of the field is `CLK_DIV64`"] + #[doc = "Peripheral clock/64"] #[inline(always)] pub fn is_clk_div64(&self) -> bool { *self == PREBSELECT_A::CLK_DIV64 } - #[doc = "Checks if the value of the field is `CLK_DIV128`"] + #[doc = "Peripheral clock/128"] #[inline(always)] pub fn is_clk_div128(&self) -> bool { *self == PREBSELECT_A::CLK_DIV128 } - #[doc = "Checks if the value of the field is `CLK_DIV256`"] + #[doc = "Peripheral clock/256"] #[inline(always)] pub fn is_clk_div256(&self) -> bool { *self == PREBSELECT_A::CLK_DIV256 } - #[doc = "Checks if the value of the field is `CLK_DIV512`"] + #[doc = "Peripheral clock/512"] #[inline(always)] pub fn is_clk_div512(&self) -> bool { *self == PREBSELECT_A::CLK_DIV512 } - #[doc = "Checks if the value of the field is `CLK_DIV1024`"] + #[doc = "Peripheral clock/1024"] #[inline(always)] pub fn is_clk_div1024(&self) -> bool { *self == PREBSELECT_A::CLK_DIV1024 } } #[doc = "Field `PREB` writer - CLKB Source Clock Selection"] -pub type PREB_W<'a, const O: u8> = crate::FieldWriter<'a, CLK_SPEC, 4, O, PREBSELECT_A>; -impl<'a, const O: u8> PREB_W<'a, O> { +pub type PREB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, PREBSELECT_A>; +impl<'a, REG, const O: u8> PREB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Peripheral clock"] #[inline(always)] - pub fn clk(self) -> &'a mut W { + pub fn clk(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK) } #[doc = "Peripheral clock/2"] #[inline(always)] - pub fn clk_div2(self) -> &'a mut W { + pub fn clk_div2(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV2) } #[doc = "Peripheral clock/4"] #[inline(always)] - pub fn clk_div4(self) -> &'a mut W { + pub fn clk_div4(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV4) } #[doc = "Peripheral clock/8"] #[inline(always)] - pub fn clk_div8(self) -> &'a mut W { + pub fn clk_div8(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV8) } #[doc = "Peripheral clock/16"] #[inline(always)] - pub fn clk_div16(self) -> &'a mut W { + pub fn clk_div16(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV16) } #[doc = "Peripheral clock/32"] #[inline(always)] - pub fn clk_div32(self) -> &'a mut W { + pub fn clk_div32(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV32) } #[doc = "Peripheral clock/64"] #[inline(always)] - pub fn clk_div64(self) -> &'a mut W { + pub fn clk_div64(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV64) } #[doc = "Peripheral clock/128"] #[inline(always)] - pub fn clk_div128(self) -> &'a mut W { + pub fn clk_div128(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV128) } #[doc = "Peripheral clock/256"] #[inline(always)] - pub fn clk_div256(self) -> &'a mut W { + pub fn clk_div256(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV256) } #[doc = "Peripheral clock/512"] #[inline(always)] - pub fn clk_div512(self) -> &'a mut W { + pub fn clk_div512(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV512) } #[doc = "Peripheral clock/1024"] #[inline(always)] - pub fn clk_div1024(self) -> &'a mut W { + pub fn clk_div1024(self) -> &'a mut crate::W { self.variant(PREBSELECT_A::CLK_DIV1024) } } @@ -514,46 +498,43 @@ impl W { #[doc = "Bits 0:7 - CLKA Divide Factor"] #[inline(always)] #[must_use] - pub fn diva(&mut self) -> DIVA_W<0> { + pub fn diva(&mut self) -> DIVA_W { DIVA_W::new(self) } #[doc = "Bits 8:11 - CLKA Source Clock Selection"] #[inline(always)] #[must_use] - pub fn prea(&mut self) -> PREA_W<8> { + pub fn prea(&mut self) -> PREA_W { PREA_W::new(self) } #[doc = "Bits 16:23 - CLKB Divide Factor"] #[inline(always)] #[must_use] - pub fn divb(&mut self) -> DIVB_W<16> { + pub fn divb(&mut self) -> DIVB_W { DIVB_W::new(self) } #[doc = "Bits 24:27 - CLKB Source Clock Selection"] #[inline(always)] #[must_use] - pub fn preb(&mut self) -> PREB_W<24> { + pub fn preb(&mut self) -> PREB_W { PREB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk](index.html) module"] +#[doc = "PWM Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CLK_SPEC; impl crate::RegisterSpec for CLK_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [clk::R](R) reader structure"] -impl crate::Readable for CLK_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [clk::W](W) writer structure"] +#[doc = "`read()` method returns [`clk::R`](R) reader structure"] +impl crate::Readable for CLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk::W`](W) writer structure"] impl crate::Writable for CLK_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd0.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd0.rs index 60a85332..977cecb9 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd0.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd0.rs @@ -1,56 +1,36 @@ #[doc = "Register `CMUPD0` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPOLUP` writer - Channel Polarity Update"] -pub type CPOLUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD0_SPEC, O>; +pub type CPOLUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOLINVUP` writer - Channel Polarity Inversion Update"] -pub type CPOLINVUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD0_SPEC, O>; +pub type CPOLINVUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 9 - Channel Polarity Update"] #[inline(always)] #[must_use] - pub fn cpolup(&mut self) -> CPOLUP_W<9> { + pub fn cpolup(&mut self) -> CPOLUP_W { CPOLUP_W::new(self) } #[doc = "Bit 13 - Channel Polarity Inversion Update"] #[inline(always)] #[must_use] - pub fn cpolinvup(&mut self) -> CPOLINVUP_W<13> { + pub fn cpolinvup(&mut self) -> CPOLINVUP_W { CPOLINVUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Mode Update Register (ch_num = 0)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmupd0](index.html) module"] +#[doc = "PWM Channel Mode Update Register (ch_num = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMUPD0_SPEC; impl crate::RegisterSpec for CMUPD0_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmupd0::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmupd0::W`](W) writer structure"] impl crate::Writable for CMUPD0_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd1.rs index 6fb9ad0d..24842cb1 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd1.rs @@ -1,56 +1,36 @@ #[doc = "Register `CMUPD1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPOLUP` writer - Channel Polarity Update"] -pub type CPOLUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD1_SPEC, O>; +pub type CPOLUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOLINVUP` writer - Channel Polarity Inversion Update"] -pub type CPOLINVUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD1_SPEC, O>; +pub type CPOLINVUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 9 - Channel Polarity Update"] #[inline(always)] #[must_use] - pub fn cpolup(&mut self) -> CPOLUP_W<9> { + pub fn cpolup(&mut self) -> CPOLUP_W { CPOLUP_W::new(self) } #[doc = "Bit 13 - Channel Polarity Inversion Update"] #[inline(always)] #[must_use] - pub fn cpolinvup(&mut self) -> CPOLINVUP_W<13> { + pub fn cpolinvup(&mut self) -> CPOLINVUP_W { CPOLINVUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Mode Update Register (ch_num = 1)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmupd1](index.html) module"] +#[doc = "PWM Channel Mode Update Register (ch_num = 1)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMUPD1_SPEC; impl crate::RegisterSpec for CMUPD1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmupd1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmupd1::W`](W) writer structure"] impl crate::Writable for CMUPD1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd2.rs index fd1f633f..6eea7c9a 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd2.rs @@ -1,56 +1,36 @@ #[doc = "Register `CMUPD2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPOLUP` writer - Channel Polarity Update"] -pub type CPOLUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD2_SPEC, O>; +pub type CPOLUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOLINVUP` writer - Channel Polarity Inversion Update"] -pub type CPOLINVUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD2_SPEC, O>; +pub type CPOLINVUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 9 - Channel Polarity Update"] #[inline(always)] #[must_use] - pub fn cpolup(&mut self) -> CPOLUP_W<9> { + pub fn cpolup(&mut self) -> CPOLUP_W { CPOLUP_W::new(self) } #[doc = "Bit 13 - Channel Polarity Inversion Update"] #[inline(always)] #[must_use] - pub fn cpolinvup(&mut self) -> CPOLINVUP_W<13> { + pub fn cpolinvup(&mut self) -> CPOLINVUP_W { CPOLINVUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Mode Update Register (ch_num = 2)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmupd2](index.html) module"] +#[doc = "PWM Channel Mode Update Register (ch_num = 2)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMUPD2_SPEC; impl crate::RegisterSpec for CMUPD2_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmupd2::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmupd2::W`](W) writer structure"] impl crate::Writable for CMUPD2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd3.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd3.rs index bc22ec16..5de5ac27 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd3.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/cmupd3.rs @@ -1,56 +1,36 @@ #[doc = "Register `CMUPD3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPOLUP` writer - Channel Polarity Update"] -pub type CPOLUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD3_SPEC, O>; +pub type CPOLUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOLINVUP` writer - Channel Polarity Inversion Update"] -pub type CPOLINVUP_W<'a, const O: u8> = crate::BitWriter<'a, CMUPD3_SPEC, O>; +pub type CPOLINVUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 9 - Channel Polarity Update"] #[inline(always)] #[must_use] - pub fn cpolup(&mut self) -> CPOLUP_W<9> { + pub fn cpolup(&mut self) -> CPOLUP_W { CPOLUP_W::new(self) } #[doc = "Bit 13 - Channel Polarity Inversion Update"] #[inline(always)] #[must_use] - pub fn cpolinvup(&mut self) -> CPOLINVUP_W<13> { + pub fn cpolinvup(&mut self) -> CPOLINVUP_W { CPOLINVUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Mode Update Register (ch_num = 3)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmupd3](index.html) module"] +#[doc = "PWM Channel Mode Update Register (ch_num = 3)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmupd3::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMUPD3_SPEC; impl crate::RegisterSpec for CMUPD3_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmupd3::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmupd3::W`](W) writer structure"] impl crate::Writable for CMUPD3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/dis.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/dis.rs index 233f73f7..5d2ce0f3 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/dis.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/dis.rs @@ -1,72 +1,52 @@ #[doc = "Register `DIS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHID0` writer - Channel ID"] -pub type CHID0_W<'a, const O: u8> = crate::BitWriter<'a, DIS_SPEC, O>; +pub type CHID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID1` writer - Channel ID"] -pub type CHID1_W<'a, const O: u8> = crate::BitWriter<'a, DIS_SPEC, O>; +pub type CHID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID2` writer - Channel ID"] -pub type CHID2_W<'a, const O: u8> = crate::BitWriter<'a, DIS_SPEC, O>; +pub type CHID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID3` writer - Channel ID"] -pub type CHID3_W<'a, const O: u8> = crate::BitWriter<'a, DIS_SPEC, O>; +pub type CHID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid0(&mut self) -> CHID0_W<0> { + pub fn chid0(&mut self) -> CHID0_W { CHID0_W::new(self) } #[doc = "Bit 1 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid1(&mut self) -> CHID1_W<1> { + pub fn chid1(&mut self) -> CHID1_W { CHID1_W::new(self) } #[doc = "Bit 2 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid2(&mut self) -> CHID2_W<2> { + pub fn chid2(&mut self) -> CHID2_W { CHID2_W::new(self) } #[doc = "Bit 3 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid3(&mut self) -> CHID3_W<3> { + pub fn chid3(&mut self) -> CHID3_W { CHID3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dis](index.html) module"] +#[doc = "PWM Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dis::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DIS_SPEC; impl crate::RegisterSpec for DIS_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [dis::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`dis::W`](W) writer structure"] impl crate::Writable for DIS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/dmar.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/dmar.rs index 4410008f..597a1ab8 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/dmar.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/dmar.rs @@ -1,48 +1,28 @@ #[doc = "Register `DMAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DMADUTY` writer - Duty-Cycle Holding Register for DMA Access"] -pub type DMADUTY_W<'a, const O: u8> = crate::FieldWriter<'a, DMAR_SPEC, 24, O, u32>; +pub type DMADUTY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl W { #[doc = "Bits 0:23 - Duty-Cycle Holding Register for DMA Access"] #[inline(always)] #[must_use] - pub fn dmaduty(&mut self) -> DMADUTY_W<0> { + pub fn dmaduty(&mut self) -> DMADUTY_W { DMADUTY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM DMA Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmar](index.html) module"] +#[doc = "PWM DMA Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmar::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DMAR_SPEC; impl crate::RegisterSpec for DMAR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [dmar::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`dmar::W`](W) writer structure"] impl crate::Writable for DMAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/elmr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/elmr.rs index 94226b63..c6da2879 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/elmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/elmr.rs @@ -1,71 +1,39 @@ #[doc = "Register `ELMR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ELMR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CSEL0` reader - Comparison 0 Selection"] pub type CSEL0_R = crate::BitReader; #[doc = "Field `CSEL0` writer - Comparison 0 Selection"] -pub type CSEL0_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL1` reader - Comparison 1 Selection"] pub type CSEL1_R = crate::BitReader; #[doc = "Field `CSEL1` writer - Comparison 1 Selection"] -pub type CSEL1_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL2` reader - Comparison 2 Selection"] pub type CSEL2_R = crate::BitReader; #[doc = "Field `CSEL2` writer - Comparison 2 Selection"] -pub type CSEL2_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL3` reader - Comparison 3 Selection"] pub type CSEL3_R = crate::BitReader; #[doc = "Field `CSEL3` writer - Comparison 3 Selection"] -pub type CSEL3_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL4` reader - Comparison 4 Selection"] pub type CSEL4_R = crate::BitReader; #[doc = "Field `CSEL4` writer - Comparison 4 Selection"] -pub type CSEL4_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL5` reader - Comparison 5 Selection"] pub type CSEL5_R = crate::BitReader; #[doc = "Field `CSEL5` writer - Comparison 5 Selection"] -pub type CSEL5_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL6` reader - Comparison 6 Selection"] pub type CSEL6_R = crate::BitReader; #[doc = "Field `CSEL6` writer - Comparison 6 Selection"] -pub type CSEL6_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSEL7` reader - Comparison 7 Selection"] pub type CSEL7_R = crate::BitReader; #[doc = "Field `CSEL7` writer - Comparison 7 Selection"] -pub type CSEL7_W<'a, const O: u8> = crate::BitWriter<'a, ELMR_SPEC, O>; +pub type CSEL7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Comparison 0 Selection"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bit 0 - Comparison 0 Selection"] #[inline(always)] #[must_use] - pub fn csel0(&mut self) -> CSEL0_W<0> { + pub fn csel0(&mut self) -> CSEL0_W { CSEL0_W::new(self) } #[doc = "Bit 1 - Comparison 1 Selection"] #[inline(always)] #[must_use] - pub fn csel1(&mut self) -> CSEL1_W<1> { + pub fn csel1(&mut self) -> CSEL1_W { CSEL1_W::new(self) } #[doc = "Bit 2 - Comparison 2 Selection"] #[inline(always)] #[must_use] - pub fn csel2(&mut self) -> CSEL2_W<2> { + pub fn csel2(&mut self) -> CSEL2_W { CSEL2_W::new(self) } #[doc = "Bit 3 - Comparison 3 Selection"] #[inline(always)] #[must_use] - pub fn csel3(&mut self) -> CSEL3_W<3> { + pub fn csel3(&mut self) -> CSEL3_W { CSEL3_W::new(self) } #[doc = "Bit 4 - Comparison 4 Selection"] #[inline(always)] #[must_use] - pub fn csel4(&mut self) -> CSEL4_W<4> { + pub fn csel4(&mut self) -> CSEL4_W { CSEL4_W::new(self) } #[doc = "Bit 5 - Comparison 5 Selection"] #[inline(always)] #[must_use] - pub fn csel5(&mut self) -> CSEL5_W<5> { + pub fn csel5(&mut self) -> CSEL5_W { CSEL5_W::new(self) } #[doc = "Bit 6 - Comparison 6 Selection"] #[inline(always)] #[must_use] - pub fn csel6(&mut self) -> CSEL6_W<6> { + pub fn csel6(&mut self) -> CSEL6_W { CSEL6_W::new(self) } #[doc = "Bit 7 - Comparison 7 Selection"] #[inline(always)] #[must_use] - pub fn csel7(&mut self) -> CSEL7_W<7> { + pub fn csel7(&mut self) -> CSEL7_W { CSEL7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Event Line 0 Mode Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [elmr](index.html) module"] +#[doc = "PWM Event Line 0 Mode Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`elmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`elmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ELMR_SPEC; impl crate::RegisterSpec for ELMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [elmr::R](R) reader structure"] -impl crate::Readable for ELMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [elmr::W](W) writer structure"] +#[doc = "`read()` method returns [`elmr::R`](R) reader structure"] +impl crate::Readable for ELMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`elmr::W`](W) writer structure"] impl crate::Writable for ELMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/ena.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/ena.rs index 1b077713..ce2cb2f0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/ena.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/ena.rs @@ -1,72 +1,52 @@ #[doc = "Register `ENA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHID0` writer - Channel ID"] -pub type CHID0_W<'a, const O: u8> = crate::BitWriter<'a, ENA_SPEC, O>; +pub type CHID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID1` writer - Channel ID"] -pub type CHID1_W<'a, const O: u8> = crate::BitWriter<'a, ENA_SPEC, O>; +pub type CHID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID2` writer - Channel ID"] -pub type CHID2_W<'a, const O: u8> = crate::BitWriter<'a, ENA_SPEC, O>; +pub type CHID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID3` writer - Channel ID"] -pub type CHID3_W<'a, const O: u8> = crate::BitWriter<'a, ENA_SPEC, O>; +pub type CHID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid0(&mut self) -> CHID0_W<0> { + pub fn chid0(&mut self) -> CHID0_W { CHID0_W::new(self) } #[doc = "Bit 1 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid1(&mut self) -> CHID1_W<1> { + pub fn chid1(&mut self) -> CHID1_W { CHID1_W::new(self) } #[doc = "Bit 2 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid2(&mut self) -> CHID2_W<2> { + pub fn chid2(&mut self) -> CHID2_W { CHID2_W::new(self) } #[doc = "Bit 3 - Channel ID"] #[inline(always)] #[must_use] - pub fn chid3(&mut self) -> CHID3_W<3> { + pub fn chid3(&mut self) -> CHID3_W { CHID3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ena](index.html) module"] +#[doc = "PWM Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ena::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ENA_SPEC; impl crate::RegisterSpec for ENA_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ena::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ena::W`](W) writer structure"] impl crate::Writable for ENA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/etrg1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/etrg1.rs index 0d51ea96..c487c7b3 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/etrg1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/etrg1.rs @@ -1,43 +1,11 @@ #[doc = "Register `ETRG1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ETRG1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MAXCNT` reader - Maximum Counter value"] pub type MAXCNT_R = crate::FieldReader; #[doc = "Field `MAXCNT` writer - Maximum Counter value"] -pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, ETRG1_SPEC, 24, O, u32>; +pub type MAXCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; #[doc = "Field `TRGMODE` reader - External Trigger Mode"] pub type TRGMODE_R = crate::FieldReader; #[doc = "External Trigger Mode\n\nValue on reset: 0"] @@ -74,48 +42,52 @@ impl TRGMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `OFF`"] + #[doc = "External trigger is not enabled."] #[inline(always)] pub fn is_off(&self) -> bool { *self == TRGMODESELECT_A::OFF } - #[doc = "Checks if the value of the field is `MODE1`"] + #[doc = "External PWM Reset Mode"] #[inline(always)] pub fn is_mode1(&self) -> bool { *self == TRGMODESELECT_A::MODE1 } - #[doc = "Checks if the value of the field is `MODE2`"] + #[doc = "External PWM Start Mode"] #[inline(always)] pub fn is_mode2(&self) -> bool { *self == TRGMODESELECT_A::MODE2 } - #[doc = "Checks if the value of the field is `MODE3`"] + #[doc = "Cycle-by-cycle Duty Mode"] #[inline(always)] pub fn is_mode3(&self) -> bool { *self == TRGMODESELECT_A::MODE3 } } #[doc = "Field `TRGMODE` writer - External Trigger Mode"] -pub type TRGMODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, ETRG1_SPEC, 2, O, TRGMODESELECT_A>; -impl<'a, const O: u8> TRGMODE_W<'a, O> { +pub type TRGMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TRGMODESELECT_A>; +impl<'a, REG, const O: u8> TRGMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "External trigger is not enabled."] #[inline(always)] - pub fn off(self) -> &'a mut W { + pub fn off(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::OFF) } #[doc = "External PWM Reset Mode"] #[inline(always)] - pub fn mode1(self) -> &'a mut W { + pub fn mode1(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::MODE1) } #[doc = "External PWM Start Mode"] #[inline(always)] - pub fn mode2(self) -> &'a mut W { + pub fn mode2(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::MODE2) } #[doc = "Cycle-by-cycle Duty Mode"] #[inline(always)] - pub fn mode3(self) -> &'a mut W { + pub fn mode3(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::MODE3) } } @@ -144,43 +116,46 @@ impl TRGEDGE_R { true => TRGEDGESELECT_A::RISING_ONE, } } - #[doc = "Checks if the value of the field is `FALLING_ZERO`"] + #[doc = "TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0"] #[inline(always)] pub fn is_falling_zero(&self) -> bool { *self == TRGEDGESELECT_A::FALLING_ZERO } - #[doc = "Checks if the value of the field is `RISING_ONE`"] + #[doc = "TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1"] #[inline(always)] pub fn is_rising_one(&self) -> bool { *self == TRGEDGESELECT_A::RISING_ONE } } #[doc = "Field `TRGEDGE` writer - Edge Selection"] -pub type TRGEDGE_W<'a, const O: u8> = crate::BitWriter<'a, ETRG1_SPEC, O, TRGEDGESELECT_A>; -impl<'a, const O: u8> TRGEDGE_W<'a, O> { +pub type TRGEDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRGEDGESELECT_A>; +impl<'a, REG, const O: u8> TRGEDGE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0"] #[inline(always)] - pub fn falling_zero(self) -> &'a mut W { + pub fn falling_zero(self) -> &'a mut crate::W { self.variant(TRGEDGESELECT_A::FALLING_ZERO) } #[doc = "TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1"] #[inline(always)] - pub fn rising_one(self) -> &'a mut W { + pub fn rising_one(self) -> &'a mut crate::W { self.variant(TRGEDGESELECT_A::RISING_ONE) } } #[doc = "Field `TRGFILT` reader - Filtered input"] pub type TRGFILT_R = crate::BitReader; #[doc = "Field `TRGFILT` writer - Filtered input"] -pub type TRGFILT_W<'a, const O: u8> = crate::BitWriter<'a, ETRG1_SPEC, O>; +pub type TRGFILT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRGSRC` reader - Trigger Source"] pub type TRGSRC_R = crate::BitReader; #[doc = "Field `TRGSRC` writer - Trigger Source"] -pub type TRGSRC_W<'a, const O: u8> = crate::BitWriter<'a, ETRG1_SPEC, O>; +pub type TRGSRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RFEN` reader - Recoverable Fault Enable"] pub type RFEN_R = crate::BitReader; #[doc = "Field `RFEN` writer - Recoverable Fault Enable"] -pub type RFEN_W<'a, const O: u8> = crate::BitWriter<'a, ETRG1_SPEC, O>; +pub type RFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:23 - Maximum Counter value"] #[inline(always)] @@ -217,58 +192,55 @@ impl W { #[doc = "Bits 0:23 - Maximum Counter value"] #[inline(always)] #[must_use] - pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + pub fn maxcnt(&mut self) -> MAXCNT_W { MAXCNT_W::new(self) } #[doc = "Bits 24:25 - External Trigger Mode"] #[inline(always)] #[must_use] - pub fn trgmode(&mut self) -> TRGMODE_W<24> { + pub fn trgmode(&mut self) -> TRGMODE_W { TRGMODE_W::new(self) } #[doc = "Bit 28 - Edge Selection"] #[inline(always)] #[must_use] - pub fn trgedge(&mut self) -> TRGEDGE_W<28> { + pub fn trgedge(&mut self) -> TRGEDGE_W { TRGEDGE_W::new(self) } #[doc = "Bit 29 - Filtered input"] #[inline(always)] #[must_use] - pub fn trgfilt(&mut self) -> TRGFILT_W<29> { + pub fn trgfilt(&mut self) -> TRGFILT_W { TRGFILT_W::new(self) } #[doc = "Bit 30 - Trigger Source"] #[inline(always)] #[must_use] - pub fn trgsrc(&mut self) -> TRGSRC_W<30> { + pub fn trgsrc(&mut self) -> TRGSRC_W { TRGSRC_W::new(self) } #[doc = "Bit 31 - Recoverable Fault Enable"] #[inline(always)] #[must_use] - pub fn rfen(&mut self) -> RFEN_W<31> { + pub fn rfen(&mut self) -> RFEN_W { RFEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM External Trigger Register (trg_num = 1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [etrg1](index.html) module"] +#[doc = "PWM External Trigger Register (trg_num = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etrg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etrg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ETRG1_SPEC; impl crate::RegisterSpec for ETRG1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [etrg1::R](R) reader structure"] -impl crate::Readable for ETRG1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [etrg1::W](W) writer structure"] +#[doc = "`read()` method returns [`etrg1::R`](R) reader structure"] +impl crate::Readable for ETRG1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etrg1::W`](W) writer structure"] impl crate::Writable for ETRG1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/etrg2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/etrg2.rs index 5c59c5bd..ee0fcec4 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/etrg2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/etrg2.rs @@ -1,43 +1,11 @@ #[doc = "Register `ETRG2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ETRG2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MAXCNT` reader - Maximum Counter value"] pub type MAXCNT_R = crate::FieldReader; #[doc = "Field `MAXCNT` writer - Maximum Counter value"] -pub type MAXCNT_W<'a, const O: u8> = crate::FieldWriter<'a, ETRG2_SPEC, 24, O, u32>; +pub type MAXCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; #[doc = "Field `TRGMODE` reader - External Trigger Mode"] pub type TRGMODE_R = crate::FieldReader; #[doc = "External Trigger Mode\n\nValue on reset: 0"] @@ -74,48 +42,52 @@ impl TRGMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `OFF`"] + #[doc = "External trigger is not enabled."] #[inline(always)] pub fn is_off(&self) -> bool { *self == TRGMODESELECT_A::OFF } - #[doc = "Checks if the value of the field is `MODE1`"] + #[doc = "External PWM Reset Mode"] #[inline(always)] pub fn is_mode1(&self) -> bool { *self == TRGMODESELECT_A::MODE1 } - #[doc = "Checks if the value of the field is `MODE2`"] + #[doc = "External PWM Start Mode"] #[inline(always)] pub fn is_mode2(&self) -> bool { *self == TRGMODESELECT_A::MODE2 } - #[doc = "Checks if the value of the field is `MODE3`"] + #[doc = "Cycle-by-cycle Duty Mode"] #[inline(always)] pub fn is_mode3(&self) -> bool { *self == TRGMODESELECT_A::MODE3 } } #[doc = "Field `TRGMODE` writer - External Trigger Mode"] -pub type TRGMODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, ETRG2_SPEC, 2, O, TRGMODESELECT_A>; -impl<'a, const O: u8> TRGMODE_W<'a, O> { +pub type TRGMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TRGMODESELECT_A>; +impl<'a, REG, const O: u8> TRGMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "External trigger is not enabled."] #[inline(always)] - pub fn off(self) -> &'a mut W { + pub fn off(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::OFF) } #[doc = "External PWM Reset Mode"] #[inline(always)] - pub fn mode1(self) -> &'a mut W { + pub fn mode1(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::MODE1) } #[doc = "External PWM Start Mode"] #[inline(always)] - pub fn mode2(self) -> &'a mut W { + pub fn mode2(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::MODE2) } #[doc = "Cycle-by-cycle Duty Mode"] #[inline(always)] - pub fn mode3(self) -> &'a mut W { + pub fn mode3(self) -> &'a mut crate::W { self.variant(TRGMODESELECT_A::MODE3) } } @@ -144,43 +116,46 @@ impl TRGEDGE_R { true => TRGEDGESELECT_A::RISING_ONE, } } - #[doc = "Checks if the value of the field is `FALLING_ZERO`"] + #[doc = "TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0"] #[inline(always)] pub fn is_falling_zero(&self) -> bool { *self == TRGEDGESELECT_A::FALLING_ZERO } - #[doc = "Checks if the value of the field is `RISING_ONE`"] + #[doc = "TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1"] #[inline(always)] pub fn is_rising_one(&self) -> bool { *self == TRGEDGESELECT_A::RISING_ONE } } #[doc = "Field `TRGEDGE` writer - Edge Selection"] -pub type TRGEDGE_W<'a, const O: u8> = crate::BitWriter<'a, ETRG2_SPEC, O, TRGEDGESELECT_A>; -impl<'a, const O: u8> TRGEDGE_W<'a, O> { +pub type TRGEDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TRGEDGESELECT_A>; +impl<'a, REG, const O: u8> TRGEDGE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0"] #[inline(always)] - pub fn falling_zero(self) -> &'a mut W { + pub fn falling_zero(self) -> &'a mut crate::W { self.variant(TRGEDGESELECT_A::FALLING_ZERO) } #[doc = "TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1"] #[inline(always)] - pub fn rising_one(self) -> &'a mut W { + pub fn rising_one(self) -> &'a mut crate::W { self.variant(TRGEDGESELECT_A::RISING_ONE) } } #[doc = "Field `TRGFILT` reader - Filtered input"] pub type TRGFILT_R = crate::BitReader; #[doc = "Field `TRGFILT` writer - Filtered input"] -pub type TRGFILT_W<'a, const O: u8> = crate::BitWriter<'a, ETRG2_SPEC, O>; +pub type TRGFILT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TRGSRC` reader - Trigger Source"] pub type TRGSRC_R = crate::BitReader; #[doc = "Field `TRGSRC` writer - Trigger Source"] -pub type TRGSRC_W<'a, const O: u8> = crate::BitWriter<'a, ETRG2_SPEC, O>; +pub type TRGSRC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RFEN` reader - Recoverable Fault Enable"] pub type RFEN_R = crate::BitReader; #[doc = "Field `RFEN` writer - Recoverable Fault Enable"] -pub type RFEN_W<'a, const O: u8> = crate::BitWriter<'a, ETRG2_SPEC, O>; +pub type RFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:23 - Maximum Counter value"] #[inline(always)] @@ -217,58 +192,55 @@ impl W { #[doc = "Bits 0:23 - Maximum Counter value"] #[inline(always)] #[must_use] - pub fn maxcnt(&mut self) -> MAXCNT_W<0> { + pub fn maxcnt(&mut self) -> MAXCNT_W { MAXCNT_W::new(self) } #[doc = "Bits 24:25 - External Trigger Mode"] #[inline(always)] #[must_use] - pub fn trgmode(&mut self) -> TRGMODE_W<24> { + pub fn trgmode(&mut self) -> TRGMODE_W { TRGMODE_W::new(self) } #[doc = "Bit 28 - Edge Selection"] #[inline(always)] #[must_use] - pub fn trgedge(&mut self) -> TRGEDGE_W<28> { + pub fn trgedge(&mut self) -> TRGEDGE_W { TRGEDGE_W::new(self) } #[doc = "Bit 29 - Filtered input"] #[inline(always)] #[must_use] - pub fn trgfilt(&mut self) -> TRGFILT_W<29> { + pub fn trgfilt(&mut self) -> TRGFILT_W { TRGFILT_W::new(self) } #[doc = "Bit 30 - Trigger Source"] #[inline(always)] #[must_use] - pub fn trgsrc(&mut self) -> TRGSRC_W<30> { + pub fn trgsrc(&mut self) -> TRGSRC_W { TRGSRC_W::new(self) } #[doc = "Bit 31 - Recoverable Fault Enable"] #[inline(always)] #[must_use] - pub fn rfen(&mut self) -> RFEN_W<31> { + pub fn rfen(&mut self) -> RFEN_W { RFEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM External Trigger Register (trg_num = 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [etrg2](index.html) module"] +#[doc = "PWM External Trigger Register (trg_num = 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`etrg2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`etrg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ETRG2_SPEC; impl crate::RegisterSpec for ETRG2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [etrg2::R](R) reader structure"] -impl crate::Readable for ETRG2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [etrg2::W](W) writer structure"] +#[doc = "`read()` method returns [`etrg2::R`](R) reader structure"] +impl crate::Readable for ETRG2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`etrg2::W`](W) writer structure"] impl crate::Writable for ETRG2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/fcr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/fcr.rs index d7152841..58e80bf5 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/fcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/fcr.rs @@ -1,48 +1,28 @@ #[doc = "Register `FCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FCLR` writer - Fault Clear"] -pub type FCLR_W<'a, const O: u8> = crate::FieldWriter<'a, FCR_SPEC, 8, O>; +pub type FCLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl W { #[doc = "Bits 0:7 - Fault Clear"] #[inline(always)] #[must_use] - pub fn fclr(&mut self) -> FCLR_W<0> { + pub fn fclr(&mut self) -> FCLR_W { FCLR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Fault Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fcr](index.html) module"] +#[doc = "PWM Fault Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FCR_SPEC; impl crate::RegisterSpec for FCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [fcr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"] impl crate::Writable for FCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/fmr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/fmr.rs index 71d16359..17cc2f75 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/fmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/fmr.rs @@ -1,51 +1,19 @@ #[doc = "Register `FMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FPOL` reader - Fault Polarity"] pub type FPOL_R = crate::FieldReader; #[doc = "Field `FPOL` writer - Fault Polarity"] -pub type FPOL_W<'a, const O: u8> = crate::FieldWriter<'a, FMR_SPEC, 8, O>; +pub type FPOL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FMOD` reader - Fault Activation Mode"] pub type FMOD_R = crate::FieldReader; #[doc = "Field `FMOD` writer - Fault Activation Mode"] -pub type FMOD_W<'a, const O: u8> = crate::FieldWriter<'a, FMR_SPEC, 8, O>; +pub type FMOD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FFIL` reader - Fault Filtering"] pub type FFIL_R = crate::FieldReader; #[doc = "Field `FFIL` writer - Fault Filtering"] -pub type FFIL_W<'a, const O: u8> = crate::FieldWriter<'a, FMR_SPEC, 8, O>; +pub type FFIL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Fault Polarity"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bits 0:7 - Fault Polarity"] #[inline(always)] #[must_use] - pub fn fpol(&mut self) -> FPOL_W<0> { + pub fn fpol(&mut self) -> FPOL_W { FPOL_W::new(self) } #[doc = "Bits 8:15 - Fault Activation Mode"] #[inline(always)] #[must_use] - pub fn fmod(&mut self) -> FMOD_W<8> { + pub fn fmod(&mut self) -> FMOD_W { FMOD_W::new(self) } #[doc = "Bits 16:23 - Fault Filtering"] #[inline(always)] #[must_use] - pub fn ffil(&mut self) -> FFIL_W<16> { + pub fn ffil(&mut self) -> FFIL_W { FFIL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Fault Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fmr](index.html) module"] +#[doc = "PWM Fault Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FMR_SPEC; impl crate::RegisterSpec for FMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fmr::R](R) reader structure"] -impl crate::Readable for FMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fmr::W](W) writer structure"] +#[doc = "`read()` method returns [`fmr::R`](R) reader structure"] +impl crate::Readable for FMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmr::W`](W) writer structure"] impl crate::Writable for FMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/fpe.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/fpe.rs index a9dcc27a..8c5ca257 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/fpe.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/fpe.rs @@ -1,55 +1,23 @@ #[doc = "Register `FPE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FPE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FPE0` reader - Fault Protection Enable for channel 0"] pub type FPE0_R = crate::FieldReader; #[doc = "Field `FPE0` writer - Fault Protection Enable for channel 0"] -pub type FPE0_W<'a, const O: u8> = crate::FieldWriter<'a, FPE_SPEC, 8, O>; +pub type FPE0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FPE1` reader - Fault Protection Enable for channel 1"] pub type FPE1_R = crate::FieldReader; #[doc = "Field `FPE1` writer - Fault Protection Enable for channel 1"] -pub type FPE1_W<'a, const O: u8> = crate::FieldWriter<'a, FPE_SPEC, 8, O>; +pub type FPE1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FPE2` reader - Fault Protection Enable for channel 2"] pub type FPE2_R = crate::FieldReader; #[doc = "Field `FPE2` writer - Fault Protection Enable for channel 2"] -pub type FPE2_W<'a, const O: u8> = crate::FieldWriter<'a, FPE_SPEC, 8, O>; +pub type FPE2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `FPE3` reader - Fault Protection Enable for channel 3"] pub type FPE3_R = crate::FieldReader; #[doc = "Field `FPE3` writer - Fault Protection Enable for channel 3"] -pub type FPE3_W<'a, const O: u8> = crate::FieldWriter<'a, FPE_SPEC, 8, O>; +pub type FPE3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Fault Protection Enable for channel 0"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:7 - Fault Protection Enable for channel 0"] #[inline(always)] #[must_use] - pub fn fpe0(&mut self) -> FPE0_W<0> { + pub fn fpe0(&mut self) -> FPE0_W { FPE0_W::new(self) } #[doc = "Bits 8:15 - Fault Protection Enable for channel 1"] #[inline(always)] #[must_use] - pub fn fpe1(&mut self) -> FPE1_W<8> { + pub fn fpe1(&mut self) -> FPE1_W { FPE1_W::new(self) } #[doc = "Bits 16:23 - Fault Protection Enable for channel 2"] #[inline(always)] #[must_use] - pub fn fpe2(&mut self) -> FPE2_W<16> { + pub fn fpe2(&mut self) -> FPE2_W { FPE2_W::new(self) } #[doc = "Bits 24:31 - Fault Protection Enable for channel 3"] #[inline(always)] #[must_use] - pub fn fpe3(&mut self) -> FPE3_W<24> { + pub fn fpe3(&mut self) -> FPE3_W { FPE3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Fault Protection Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fpe](index.html) module"] +#[doc = "PWM Fault Protection Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPE_SPEC; impl crate::RegisterSpec for FPE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fpe::R](R) reader structure"] -impl crate::Readable for FPE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fpe::W](W) writer structure"] +#[doc = "`read()` method returns [`fpe::R`](R) reader structure"] +impl crate::Readable for FPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpe::W`](W) writer structure"] impl crate::Writable for FPE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/fpv1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/fpv1.rs index f0796c50..eee8b3ca 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/fpv1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/fpv1.rs @@ -1,71 +1,39 @@ #[doc = "Register `FPV1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FPV1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FPVH0` reader - Fault Protection Value for PWMH output on channel 0"] pub type FPVH0_R = crate::BitReader; #[doc = "Field `FPVH0` writer - Fault Protection Value for PWMH output on channel 0"] -pub type FPVH0_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVH1` reader - Fault Protection Value for PWMH output on channel 1"] pub type FPVH1_R = crate::BitReader; #[doc = "Field `FPVH1` writer - Fault Protection Value for PWMH output on channel 1"] -pub type FPVH1_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVH2` reader - Fault Protection Value for PWMH output on channel 2"] pub type FPVH2_R = crate::BitReader; #[doc = "Field `FPVH2` writer - Fault Protection Value for PWMH output on channel 2"] -pub type FPVH2_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVH3` reader - Fault Protection Value for PWMH output on channel 3"] pub type FPVH3_R = crate::BitReader; #[doc = "Field `FPVH3` writer - Fault Protection Value for PWMH output on channel 3"] -pub type FPVH3_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVL0` reader - Fault Protection Value for PWML output on channel 0"] pub type FPVL0_R = crate::BitReader; #[doc = "Field `FPVL0` writer - Fault Protection Value for PWML output on channel 0"] -pub type FPVL0_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVL1` reader - Fault Protection Value for PWML output on channel 1"] pub type FPVL1_R = crate::BitReader; #[doc = "Field `FPVL1` writer - Fault Protection Value for PWML output on channel 1"] -pub type FPVL1_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVL2` reader - Fault Protection Value for PWML output on channel 2"] pub type FPVL2_R = crate::BitReader; #[doc = "Field `FPVL2` writer - Fault Protection Value for PWML output on channel 2"] -pub type FPVL2_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPVL3` reader - Fault Protection Value for PWML output on channel 3"] pub type FPVL3_R = crate::BitReader; #[doc = "Field `FPVL3` writer - Fault Protection Value for PWML output on channel 3"] -pub type FPVL3_W<'a, const O: u8> = crate::BitWriter<'a, FPV1_SPEC, O>; +pub type FPVL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Fault Protection Value for PWMH output on channel 0"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bit 0 - Fault Protection Value for PWMH output on channel 0"] #[inline(always)] #[must_use] - pub fn fpvh0(&mut self) -> FPVH0_W<0> { + pub fn fpvh0(&mut self) -> FPVH0_W { FPVH0_W::new(self) } #[doc = "Bit 1 - Fault Protection Value for PWMH output on channel 1"] #[inline(always)] #[must_use] - pub fn fpvh1(&mut self) -> FPVH1_W<1> { + pub fn fpvh1(&mut self) -> FPVH1_W { FPVH1_W::new(self) } #[doc = "Bit 2 - Fault Protection Value for PWMH output on channel 2"] #[inline(always)] #[must_use] - pub fn fpvh2(&mut self) -> FPVH2_W<2> { + pub fn fpvh2(&mut self) -> FPVH2_W { FPVH2_W::new(self) } #[doc = "Bit 3 - Fault Protection Value for PWMH output on channel 3"] #[inline(always)] #[must_use] - pub fn fpvh3(&mut self) -> FPVH3_W<3> { + pub fn fpvh3(&mut self) -> FPVH3_W { FPVH3_W::new(self) } #[doc = "Bit 16 - Fault Protection Value for PWML output on channel 0"] #[inline(always)] #[must_use] - pub fn fpvl0(&mut self) -> FPVL0_W<16> { + pub fn fpvl0(&mut self) -> FPVL0_W { FPVL0_W::new(self) } #[doc = "Bit 17 - Fault Protection Value for PWML output on channel 1"] #[inline(always)] #[must_use] - pub fn fpvl1(&mut self) -> FPVL1_W<17> { + pub fn fpvl1(&mut self) -> FPVL1_W { FPVL1_W::new(self) } #[doc = "Bit 18 - Fault Protection Value for PWML output on channel 2"] #[inline(always)] #[must_use] - pub fn fpvl2(&mut self) -> FPVL2_W<18> { + pub fn fpvl2(&mut self) -> FPVL2_W { FPVL2_W::new(self) } #[doc = "Bit 19 - Fault Protection Value for PWML output on channel 3"] #[inline(always)] #[must_use] - pub fn fpvl3(&mut self) -> FPVL3_W<19> { + pub fn fpvl3(&mut self) -> FPVL3_W { FPVL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Fault Protection Value Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fpv1](index.html) module"] +#[doc = "PWM Fault Protection Value Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpv1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpv1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPV1_SPEC; impl crate::RegisterSpec for FPV1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fpv1::R](R) reader structure"] -impl crate::Readable for FPV1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fpv1::W](W) writer structure"] +#[doc = "`read()` method returns [`fpv1::R`](R) reader structure"] +impl crate::Readable for FPV1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpv1::W`](W) writer structure"] impl crate::Writable for FPV1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/fpv2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/fpv2.rs index d189ee0c..0269e9ed 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/fpv2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/fpv2.rs @@ -1,71 +1,39 @@ #[doc = "Register `FPV2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FPV2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FPZH0` reader - Fault Protection to Hi-Z for PWMH output on channel 0"] pub type FPZH0_R = crate::BitReader; #[doc = "Field `FPZH0` writer - Fault Protection to Hi-Z for PWMH output on channel 0"] -pub type FPZH0_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZH1` reader - Fault Protection to Hi-Z for PWMH output on channel 1"] pub type FPZH1_R = crate::BitReader; #[doc = "Field `FPZH1` writer - Fault Protection to Hi-Z for PWMH output on channel 1"] -pub type FPZH1_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZH2` reader - Fault Protection to Hi-Z for PWMH output on channel 2"] pub type FPZH2_R = crate::BitReader; #[doc = "Field `FPZH2` writer - Fault Protection to Hi-Z for PWMH output on channel 2"] -pub type FPZH2_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZH3` reader - Fault Protection to Hi-Z for PWMH output on channel 3"] pub type FPZH3_R = crate::BitReader; #[doc = "Field `FPZH3` writer - Fault Protection to Hi-Z for PWMH output on channel 3"] -pub type FPZH3_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZL0` reader - Fault Protection to Hi-Z for PWML output on channel 0"] pub type FPZL0_R = crate::BitReader; #[doc = "Field `FPZL0` writer - Fault Protection to Hi-Z for PWML output on channel 0"] -pub type FPZL0_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZL1` reader - Fault Protection to Hi-Z for PWML output on channel 1"] pub type FPZL1_R = crate::BitReader; #[doc = "Field `FPZL1` writer - Fault Protection to Hi-Z for PWML output on channel 1"] -pub type FPZL1_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZL2` reader - Fault Protection to Hi-Z for PWML output on channel 2"] pub type FPZL2_R = crate::BitReader; #[doc = "Field `FPZL2` writer - Fault Protection to Hi-Z for PWML output on channel 2"] -pub type FPZL2_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPZL3` reader - Fault Protection to Hi-Z for PWML output on channel 3"] pub type FPZL3_R = crate::BitReader; #[doc = "Field `FPZL3` writer - Fault Protection to Hi-Z for PWML output on channel 3"] -pub type FPZL3_W<'a, const O: u8> = crate::BitWriter<'a, FPV2_SPEC, O>; +pub type FPZL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Fault Protection to Hi-Z for PWMH output on channel 0"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bit 0 - Fault Protection to Hi-Z for PWMH output on channel 0"] #[inline(always)] #[must_use] - pub fn fpzh0(&mut self) -> FPZH0_W<0> { + pub fn fpzh0(&mut self) -> FPZH0_W { FPZH0_W::new(self) } #[doc = "Bit 1 - Fault Protection to Hi-Z for PWMH output on channel 1"] #[inline(always)] #[must_use] - pub fn fpzh1(&mut self) -> FPZH1_W<1> { + pub fn fpzh1(&mut self) -> FPZH1_W { FPZH1_W::new(self) } #[doc = "Bit 2 - Fault Protection to Hi-Z for PWMH output on channel 2"] #[inline(always)] #[must_use] - pub fn fpzh2(&mut self) -> FPZH2_W<2> { + pub fn fpzh2(&mut self) -> FPZH2_W { FPZH2_W::new(self) } #[doc = "Bit 3 - Fault Protection to Hi-Z for PWMH output on channel 3"] #[inline(always)] #[must_use] - pub fn fpzh3(&mut self) -> FPZH3_W<3> { + pub fn fpzh3(&mut self) -> FPZH3_W { FPZH3_W::new(self) } #[doc = "Bit 16 - Fault Protection to Hi-Z for PWML output on channel 0"] #[inline(always)] #[must_use] - pub fn fpzl0(&mut self) -> FPZL0_W<16> { + pub fn fpzl0(&mut self) -> FPZL0_W { FPZL0_W::new(self) } #[doc = "Bit 17 - Fault Protection to Hi-Z for PWML output on channel 1"] #[inline(always)] #[must_use] - pub fn fpzl1(&mut self) -> FPZL1_W<17> { + pub fn fpzl1(&mut self) -> FPZL1_W { FPZL1_W::new(self) } #[doc = "Bit 18 - Fault Protection to Hi-Z for PWML output on channel 2"] #[inline(always)] #[must_use] - pub fn fpzl2(&mut self) -> FPZL2_W<18> { + pub fn fpzl2(&mut self) -> FPZL2_W { FPZL2_W::new(self) } #[doc = "Bit 19 - Fault Protection to Hi-Z for PWML output on channel 3"] #[inline(always)] #[must_use] - pub fn fpzl3(&mut self) -> FPZL3_W<19> { + pub fn fpzl3(&mut self) -> FPZL3_W { FPZL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Fault Protection Value 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fpv2](index.html) module"] +#[doc = "PWM Fault Protection Value 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpv2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpv2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FPV2_SPEC; impl crate::RegisterSpec for FPV2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fpv2::R](R) reader structure"] -impl crate::Readable for FPV2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fpv2::W](W) writer structure"] +#[doc = "`read()` method returns [`fpv2::R`](R) reader structure"] +impl crate::Readable for FPV2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpv2::W`](W) writer structure"] impl crate::Writable for FPV2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/fsr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/fsr.rs index e90a9836..95c1b1e8 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/fsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/fsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `FSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `FIV` reader - Fault Input Value"] pub type FIV_R = crate::FieldReader; #[doc = "Field `FS` reader - Fault Status"] @@ -29,15 +16,13 @@ impl R { FS_R::new(((self.bits >> 8) & 0xff) as u8) } } -#[doc = "PWM Fault Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsr](index.html) module"] +#[doc = "PWM Fault Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FSR_SPEC; impl crate::RegisterSpec for FSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fsr::R](R) reader structure"] -impl crate::Readable for FSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`fsr::R`](R) reader structure"] +impl crate::Readable for FSR_SPEC {} #[doc = "`reset()` method sets FSR to value 0"] impl crate::Resettable for FSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/idr1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/idr1.rs index 513ec6ab..ff36d827 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/idr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/idr1.rs @@ -1,104 +1,84 @@ #[doc = "Register `IDR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHID0` writer - Counter Event on Channel 0 Interrupt Disable"] -pub type CHID0_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type CHID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID1` writer - Counter Event on Channel 1 Interrupt Disable"] -pub type CHID1_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type CHID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID2` writer - Counter Event on Channel 2 Interrupt Disable"] -pub type CHID2_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type CHID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID3` writer - Counter Event on Channel 3 Interrupt Disable"] -pub type CHID3_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type CHID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID0` writer - Fault Protection Trigger on Channel 0 Interrupt Disable"] -pub type FCHID0_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type FCHID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID1` writer - Fault Protection Trigger on Channel 1 Interrupt Disable"] -pub type FCHID1_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type FCHID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID2` writer - Fault Protection Trigger on Channel 2 Interrupt Disable"] -pub type FCHID2_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type FCHID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID3` writer - Fault Protection Trigger on Channel 3 Interrupt Disable"] -pub type FCHID3_W<'a, const O: u8> = crate::BitWriter<'a, IDR1_SPEC, O>; +pub type FCHID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Counter Event on Channel 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn chid0(&mut self) -> CHID0_W<0> { + pub fn chid0(&mut self) -> CHID0_W { CHID0_W::new(self) } #[doc = "Bit 1 - Counter Event on Channel 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn chid1(&mut self) -> CHID1_W<1> { + pub fn chid1(&mut self) -> CHID1_W { CHID1_W::new(self) } #[doc = "Bit 2 - Counter Event on Channel 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn chid2(&mut self) -> CHID2_W<2> { + pub fn chid2(&mut self) -> CHID2_W { CHID2_W::new(self) } #[doc = "Bit 3 - Counter Event on Channel 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn chid3(&mut self) -> CHID3_W<3> { + pub fn chid3(&mut self) -> CHID3_W { CHID3_W::new(self) } #[doc = "Bit 16 - Fault Protection Trigger on Channel 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn fchid0(&mut self) -> FCHID0_W<16> { + pub fn fchid0(&mut self) -> FCHID0_W { FCHID0_W::new(self) } #[doc = "Bit 17 - Fault Protection Trigger on Channel 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn fchid1(&mut self) -> FCHID1_W<17> { + pub fn fchid1(&mut self) -> FCHID1_W { FCHID1_W::new(self) } #[doc = "Bit 18 - Fault Protection Trigger on Channel 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn fchid2(&mut self) -> FCHID2_W<18> { + pub fn fchid2(&mut self) -> FCHID2_W { FCHID2_W::new(self) } #[doc = "Bit 19 - Fault Protection Trigger on Channel 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn fchid3(&mut self) -> FCHID3_W<19> { + pub fn fchid3(&mut self) -> FCHID3_W { FCHID3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Interrupt Disable Register 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr1](index.html) module"] +#[doc = "PWM Interrupt Disable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR1_SPEC; impl crate::RegisterSpec for IDR1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr1::W`](W) writer structure"] impl crate::Writable for IDR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/idr2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/idr2.rs index d954a376..9cb35b1d 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/idr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/idr2.rs @@ -1,184 +1,164 @@ #[doc = "Register `IDR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WRDY` writer - Write Ready for Synchronous Channels Update Interrupt Disable"] -pub type WRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type WRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Synchronous Channels Update Underrun Error Interrupt Disable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM0` writer - Comparison 0 Match Interrupt Disable"] -pub type CMPM0_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM1` writer - Comparison 1 Match Interrupt Disable"] -pub type CMPM1_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM2` writer - Comparison 2 Match Interrupt Disable"] -pub type CMPM2_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM3` writer - Comparison 3 Match Interrupt Disable"] -pub type CMPM3_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM4` writer - Comparison 4 Match Interrupt Disable"] -pub type CMPM4_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM5` writer - Comparison 5 Match Interrupt Disable"] -pub type CMPM5_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM6` writer - Comparison 6 Match Interrupt Disable"] -pub type CMPM6_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM7` writer - Comparison 7 Match Interrupt Disable"] -pub type CMPM7_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPM7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU0` writer - Comparison 0 Update Interrupt Disable"] -pub type CMPU0_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU1` writer - Comparison 1 Update Interrupt Disable"] -pub type CMPU1_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU2` writer - Comparison 2 Update Interrupt Disable"] -pub type CMPU2_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU3` writer - Comparison 3 Update Interrupt Disable"] -pub type CMPU3_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU4` writer - Comparison 4 Update Interrupt Disable"] -pub type CMPU4_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU5` writer - Comparison 5 Update Interrupt Disable"] -pub type CMPU5_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU6` writer - Comparison 6 Update Interrupt Disable"] -pub type CMPU6_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU7` writer - Comparison 7 Update Interrupt Disable"] -pub type CMPU7_W<'a, const O: u8> = crate::BitWriter<'a, IDR2_SPEC, O>; +pub type CMPU7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Write Ready for Synchronous Channels Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn wrdy(&mut self) -> WRDY_W<0> { + pub fn wrdy(&mut self) -> WRDY_W { WRDY_W::new(self) } #[doc = "Bit 3 - Synchronous Channels Update Underrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<3> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 8 - Comparison 0 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm0(&mut self) -> CMPM0_W<8> { + pub fn cmpm0(&mut self) -> CMPM0_W { CMPM0_W::new(self) } #[doc = "Bit 9 - Comparison 1 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm1(&mut self) -> CMPM1_W<9> { + pub fn cmpm1(&mut self) -> CMPM1_W { CMPM1_W::new(self) } #[doc = "Bit 10 - Comparison 2 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm2(&mut self) -> CMPM2_W<10> { + pub fn cmpm2(&mut self) -> CMPM2_W { CMPM2_W::new(self) } #[doc = "Bit 11 - Comparison 3 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm3(&mut self) -> CMPM3_W<11> { + pub fn cmpm3(&mut self) -> CMPM3_W { CMPM3_W::new(self) } #[doc = "Bit 12 - Comparison 4 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm4(&mut self) -> CMPM4_W<12> { + pub fn cmpm4(&mut self) -> CMPM4_W { CMPM4_W::new(self) } #[doc = "Bit 13 - Comparison 5 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm5(&mut self) -> CMPM5_W<13> { + pub fn cmpm5(&mut self) -> CMPM5_W { CMPM5_W::new(self) } #[doc = "Bit 14 - Comparison 6 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm6(&mut self) -> CMPM6_W<14> { + pub fn cmpm6(&mut self) -> CMPM6_W { CMPM6_W::new(self) } #[doc = "Bit 15 - Comparison 7 Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpm7(&mut self) -> CMPM7_W<15> { + pub fn cmpm7(&mut self) -> CMPM7_W { CMPM7_W::new(self) } #[doc = "Bit 16 - Comparison 0 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu0(&mut self) -> CMPU0_W<16> { + pub fn cmpu0(&mut self) -> CMPU0_W { CMPU0_W::new(self) } #[doc = "Bit 17 - Comparison 1 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu1(&mut self) -> CMPU1_W<17> { + pub fn cmpu1(&mut self) -> CMPU1_W { CMPU1_W::new(self) } #[doc = "Bit 18 - Comparison 2 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu2(&mut self) -> CMPU2_W<18> { + pub fn cmpu2(&mut self) -> CMPU2_W { CMPU2_W::new(self) } #[doc = "Bit 19 - Comparison 3 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu3(&mut self) -> CMPU3_W<19> { + pub fn cmpu3(&mut self) -> CMPU3_W { CMPU3_W::new(self) } #[doc = "Bit 20 - Comparison 4 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu4(&mut self) -> CMPU4_W<20> { + pub fn cmpu4(&mut self) -> CMPU4_W { CMPU4_W::new(self) } #[doc = "Bit 21 - Comparison 5 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu5(&mut self) -> CMPU5_W<21> { + pub fn cmpu5(&mut self) -> CMPU5_W { CMPU5_W::new(self) } #[doc = "Bit 22 - Comparison 6 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu6(&mut self) -> CMPU6_W<22> { + pub fn cmpu6(&mut self) -> CMPU6_W { CMPU6_W::new(self) } #[doc = "Bit 23 - Comparison 7 Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cmpu7(&mut self) -> CMPU7_W<23> { + pub fn cmpu7(&mut self) -> CMPU7_W { CMPU7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Interrupt Disable Register 2\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr2](index.html) module"] +#[doc = "PWM Interrupt Disable Register 2\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR2_SPEC; impl crate::RegisterSpec for IDR2_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr2::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr2::W`](W) writer structure"] impl crate::Writable for IDR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/ier1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/ier1.rs index 19496ad6..badee22c 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/ier1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/ier1.rs @@ -1,104 +1,84 @@ #[doc = "Register `IER1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHID0` writer - Counter Event on Channel 0 Interrupt Enable"] -pub type CHID0_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type CHID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID1` writer - Counter Event on Channel 1 Interrupt Enable"] -pub type CHID1_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type CHID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID2` writer - Counter Event on Channel 2 Interrupt Enable"] -pub type CHID2_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type CHID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHID3` writer - Counter Event on Channel 3 Interrupt Enable"] -pub type CHID3_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type CHID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID0` writer - Fault Protection Trigger on Channel 0 Interrupt Enable"] -pub type FCHID0_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type FCHID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID1` writer - Fault Protection Trigger on Channel 1 Interrupt Enable"] -pub type FCHID1_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type FCHID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID2` writer - Fault Protection Trigger on Channel 2 Interrupt Enable"] -pub type FCHID2_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type FCHID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCHID3` writer - Fault Protection Trigger on Channel 3 Interrupt Enable"] -pub type FCHID3_W<'a, const O: u8> = crate::BitWriter<'a, IER1_SPEC, O>; +pub type FCHID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Counter Event on Channel 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn chid0(&mut self) -> CHID0_W<0> { + pub fn chid0(&mut self) -> CHID0_W { CHID0_W::new(self) } #[doc = "Bit 1 - Counter Event on Channel 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn chid1(&mut self) -> CHID1_W<1> { + pub fn chid1(&mut self) -> CHID1_W { CHID1_W::new(self) } #[doc = "Bit 2 - Counter Event on Channel 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn chid2(&mut self) -> CHID2_W<2> { + pub fn chid2(&mut self) -> CHID2_W { CHID2_W::new(self) } #[doc = "Bit 3 - Counter Event on Channel 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn chid3(&mut self) -> CHID3_W<3> { + pub fn chid3(&mut self) -> CHID3_W { CHID3_W::new(self) } #[doc = "Bit 16 - Fault Protection Trigger on Channel 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn fchid0(&mut self) -> FCHID0_W<16> { + pub fn fchid0(&mut self) -> FCHID0_W { FCHID0_W::new(self) } #[doc = "Bit 17 - Fault Protection Trigger on Channel 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn fchid1(&mut self) -> FCHID1_W<17> { + pub fn fchid1(&mut self) -> FCHID1_W { FCHID1_W::new(self) } #[doc = "Bit 18 - Fault Protection Trigger on Channel 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn fchid2(&mut self) -> FCHID2_W<18> { + pub fn fchid2(&mut self) -> FCHID2_W { FCHID2_W::new(self) } #[doc = "Bit 19 - Fault Protection Trigger on Channel 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn fchid3(&mut self) -> FCHID3_W<19> { + pub fn fchid3(&mut self) -> FCHID3_W { FCHID3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Interrupt Enable Register 1\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier1](index.html) module"] +#[doc = "PWM Interrupt Enable Register 1\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER1_SPEC; impl crate::RegisterSpec for IER1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier1::W`](W) writer structure"] impl crate::Writable for IER1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/ier2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/ier2.rs index 71870733..5da343d0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/ier2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/ier2.rs @@ -1,184 +1,164 @@ #[doc = "Register `IER2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WRDY` writer - Write Ready for Synchronous Channels Update Interrupt Enable"] -pub type WRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type WRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Synchronous Channels Update Underrun Error Interrupt Enable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM0` writer - Comparison 0 Match Interrupt Enable"] -pub type CMPM0_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM1` writer - Comparison 1 Match Interrupt Enable"] -pub type CMPM1_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM2` writer - Comparison 2 Match Interrupt Enable"] -pub type CMPM2_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM3` writer - Comparison 3 Match Interrupt Enable"] -pub type CMPM3_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM4` writer - Comparison 4 Match Interrupt Enable"] -pub type CMPM4_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM5` writer - Comparison 5 Match Interrupt Enable"] -pub type CMPM5_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM6` writer - Comparison 6 Match Interrupt Enable"] -pub type CMPM6_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPM7` writer - Comparison 7 Match Interrupt Enable"] -pub type CMPM7_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPM7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU0` writer - Comparison 0 Update Interrupt Enable"] -pub type CMPU0_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU1` writer - Comparison 1 Update Interrupt Enable"] -pub type CMPU1_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU2` writer - Comparison 2 Update Interrupt Enable"] -pub type CMPU2_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU3` writer - Comparison 3 Update Interrupt Enable"] -pub type CMPU3_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU4` writer - Comparison 4 Update Interrupt Enable"] -pub type CMPU4_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU5` writer - Comparison 5 Update Interrupt Enable"] -pub type CMPU5_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU6` writer - Comparison 6 Update Interrupt Enable"] -pub type CMPU6_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMPU7` writer - Comparison 7 Update Interrupt Enable"] -pub type CMPU7_W<'a, const O: u8> = crate::BitWriter<'a, IER2_SPEC, O>; +pub type CMPU7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Write Ready for Synchronous Channels Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn wrdy(&mut self) -> WRDY_W<0> { + pub fn wrdy(&mut self) -> WRDY_W { WRDY_W::new(self) } #[doc = "Bit 3 - Synchronous Channels Update Underrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<3> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 8 - Comparison 0 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm0(&mut self) -> CMPM0_W<8> { + pub fn cmpm0(&mut self) -> CMPM0_W { CMPM0_W::new(self) } #[doc = "Bit 9 - Comparison 1 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm1(&mut self) -> CMPM1_W<9> { + pub fn cmpm1(&mut self) -> CMPM1_W { CMPM1_W::new(self) } #[doc = "Bit 10 - Comparison 2 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm2(&mut self) -> CMPM2_W<10> { + pub fn cmpm2(&mut self) -> CMPM2_W { CMPM2_W::new(self) } #[doc = "Bit 11 - Comparison 3 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm3(&mut self) -> CMPM3_W<11> { + pub fn cmpm3(&mut self) -> CMPM3_W { CMPM3_W::new(self) } #[doc = "Bit 12 - Comparison 4 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm4(&mut self) -> CMPM4_W<12> { + pub fn cmpm4(&mut self) -> CMPM4_W { CMPM4_W::new(self) } #[doc = "Bit 13 - Comparison 5 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm5(&mut self) -> CMPM5_W<13> { + pub fn cmpm5(&mut self) -> CMPM5_W { CMPM5_W::new(self) } #[doc = "Bit 14 - Comparison 6 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm6(&mut self) -> CMPM6_W<14> { + pub fn cmpm6(&mut self) -> CMPM6_W { CMPM6_W::new(self) } #[doc = "Bit 15 - Comparison 7 Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpm7(&mut self) -> CMPM7_W<15> { + pub fn cmpm7(&mut self) -> CMPM7_W { CMPM7_W::new(self) } #[doc = "Bit 16 - Comparison 0 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu0(&mut self) -> CMPU0_W<16> { + pub fn cmpu0(&mut self) -> CMPU0_W { CMPU0_W::new(self) } #[doc = "Bit 17 - Comparison 1 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu1(&mut self) -> CMPU1_W<17> { + pub fn cmpu1(&mut self) -> CMPU1_W { CMPU1_W::new(self) } #[doc = "Bit 18 - Comparison 2 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu2(&mut self) -> CMPU2_W<18> { + pub fn cmpu2(&mut self) -> CMPU2_W { CMPU2_W::new(self) } #[doc = "Bit 19 - Comparison 3 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu3(&mut self) -> CMPU3_W<19> { + pub fn cmpu3(&mut self) -> CMPU3_W { CMPU3_W::new(self) } #[doc = "Bit 20 - Comparison 4 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu4(&mut self) -> CMPU4_W<20> { + pub fn cmpu4(&mut self) -> CMPU4_W { CMPU4_W::new(self) } #[doc = "Bit 21 - Comparison 5 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu5(&mut self) -> CMPU5_W<21> { + pub fn cmpu5(&mut self) -> CMPU5_W { CMPU5_W::new(self) } #[doc = "Bit 22 - Comparison 6 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu6(&mut self) -> CMPU6_W<22> { + pub fn cmpu6(&mut self) -> CMPU6_W { CMPU6_W::new(self) } #[doc = "Bit 23 - Comparison 7 Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cmpu7(&mut self) -> CMPU7_W<23> { + pub fn cmpu7(&mut self) -> CMPU7_W { CMPU7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Interrupt Enable Register 2\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier2](index.html) module"] +#[doc = "PWM Interrupt Enable Register 2\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER2_SPEC; impl crate::RegisterSpec for IER2_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier2::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier2::W`](W) writer structure"] impl crate::Writable for IER2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/imr1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/imr1.rs index f20c5192..6abd5ec2 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/imr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/imr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHID0` reader - Counter Event on Channel 0 Interrupt Mask"] pub type CHID0_R = crate::BitReader; #[doc = "Field `CHID1` reader - Counter Event on Channel 1 Interrupt Mask"] @@ -71,15 +58,13 @@ impl R { FCHID3_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "PWM Interrupt Mask Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr1](index.html) module"] +#[doc = "PWM Interrupt Mask Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR1_SPEC; impl crate::RegisterSpec for IMR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr1::R](R) reader structure"] -impl crate::Readable for IMR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr1::R`](R) reader structure"] +impl crate::Readable for IMR1_SPEC {} #[doc = "`reset()` method sets IMR1 to value 0"] impl crate::Resettable for IMR1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/imr2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/imr2.rs index 71c0ef77..8db50f5a 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/imr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/imr2.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WRDY` reader - Write Ready for Synchronous Channels Update Interrupt Mask"] pub type WRDY_R = crate::BitReader; #[doc = "Field `UNRE` reader - Synchronous Channels Update Underrun Error Interrupt Mask"] @@ -141,15 +128,13 @@ impl R { CMPU7_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "PWM Interrupt Mask Register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr2](index.html) module"] +#[doc = "PWM Interrupt Mask Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR2_SPEC; impl crate::RegisterSpec for IMR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr2::R](R) reader structure"] -impl crate::Readable for IMR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr2::R`](R) reader structure"] +impl crate::Readable for IMR2_SPEC {} #[doc = "`reset()` method sets IMR2 to value 0"] impl crate::Resettable for IMR2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/isr1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/isr1.rs index 20b0c6c5..7cd15670 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/isr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/isr1.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHID0` reader - Counter Event on Channel 0"] pub type CHID0_R = crate::BitReader; #[doc = "Field `CHID1` reader - Counter Event on Channel 1"] @@ -71,15 +58,13 @@ impl R { FCHID3_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "PWM Interrupt Status Register 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr1](index.html) module"] +#[doc = "PWM Interrupt Status Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR1_SPEC; impl crate::RegisterSpec for ISR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr1::R](R) reader structure"] -impl crate::Readable for ISR1_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr1::R`](R) reader structure"] +impl crate::Readable for ISR1_SPEC {} #[doc = "`reset()` method sets ISR1 to value 0"] impl crate::Resettable for ISR1_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/isr2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/isr2.rs index ad695407..1a70595e 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/isr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/isr2.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WRDY` reader - Write Ready for Synchronous Channels Update"] pub type WRDY_R = crate::BitReader; #[doc = "Field `UNRE` reader - Synchronous Channels Update Underrun Error"] @@ -141,15 +128,13 @@ impl R { CMPU7_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "PWM Interrupt Status Register 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr2](index.html) module"] +#[doc = "PWM Interrupt Status Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR2_SPEC; impl crate::RegisterSpec for ISR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr2::R](R) reader structure"] -impl crate::Readable for ISR2_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr2::R`](R) reader structure"] +impl crate::Readable for ISR2_SPEC {} #[doc = "`reset()` method sets ISR2 to value 0"] impl crate::Resettable for ISR2_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/lebr1.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/lebr1.rs index 0214e4ba..1892a227 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/lebr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/lebr1.rs @@ -1,59 +1,27 @@ #[doc = "Register `LEBR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LEBR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEBDELAY` reader - Leading-Edge Blanking Delay for TRGINx"] pub type LEBDELAY_R = crate::FieldReader; #[doc = "Field `LEBDELAY` writer - Leading-Edge Blanking Delay for TRGINx"] -pub type LEBDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, LEBR1_SPEC, 7, O>; +pub type LEBDELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PWMLFEN` reader - PWML Falling Edge Enable"] pub type PWMLFEN_R = crate::BitReader; #[doc = "Field `PWMLFEN` writer - PWML Falling Edge Enable"] -pub type PWMLFEN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR1_SPEC, O>; +pub type PWMLFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWMLREN` reader - PWML Rising Edge Enable"] pub type PWMLREN_R = crate::BitReader; #[doc = "Field `PWMLREN` writer - PWML Rising Edge Enable"] -pub type PWMLREN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR1_SPEC, O>; +pub type PWMLREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWMHFEN` reader - PWMH Falling Edge Enable"] pub type PWMHFEN_R = crate::BitReader; #[doc = "Field `PWMHFEN` writer - PWMH Falling Edge Enable"] -pub type PWMHFEN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR1_SPEC, O>; +pub type PWMHFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWMHREN` reader - PWMH Rising Edge Enable"] pub type PWMHREN_R = crate::BitReader; #[doc = "Field `PWMHREN` writer - PWMH Rising Edge Enable"] -pub type PWMHREN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR1_SPEC, O>; +pub type PWMHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Leading-Edge Blanking Delay for TRGINx"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bits 0:6 - Leading-Edge Blanking Delay for TRGINx"] #[inline(always)] #[must_use] - pub fn lebdelay(&mut self) -> LEBDELAY_W<0> { + pub fn lebdelay(&mut self) -> LEBDELAY_W { LEBDELAY_W::new(self) } #[doc = "Bit 16 - PWML Falling Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmlfen(&mut self) -> PWMLFEN_W<16> { + pub fn pwmlfen(&mut self) -> PWMLFEN_W { PWMLFEN_W::new(self) } #[doc = "Bit 17 - PWML Rising Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmlren(&mut self) -> PWMLREN_W<17> { + pub fn pwmlren(&mut self) -> PWMLREN_W { PWMLREN_W::new(self) } #[doc = "Bit 18 - PWMH Falling Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmhfen(&mut self) -> PWMHFEN_W<18> { + pub fn pwmhfen(&mut self) -> PWMHFEN_W { PWMHFEN_W::new(self) } #[doc = "Bit 19 - PWMH Rising Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmhren(&mut self) -> PWMHREN_W<19> { + pub fn pwmhren(&mut self) -> PWMHREN_W { PWMHREN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Leading-Edge Blanking Register (trg_num = 1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lebr1](index.html) module"] +#[doc = "PWM Leading-Edge Blanking Register (trg_num = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lebr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lebr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LEBR1_SPEC; impl crate::RegisterSpec for LEBR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lebr1::R](R) reader structure"] -impl crate::Readable for LEBR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lebr1::W](W) writer structure"] +#[doc = "`read()` method returns [`lebr1::R`](R) reader structure"] +impl crate::Readable for LEBR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lebr1::W`](W) writer structure"] impl crate::Writable for LEBR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/lebr2.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/lebr2.rs index 8fe51447..d5b455df 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/lebr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/lebr2.rs @@ -1,59 +1,27 @@ #[doc = "Register `LEBR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `LEBR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LEBDELAY` reader - Leading-Edge Blanking Delay for TRGINx"] pub type LEBDELAY_R = crate::FieldReader; #[doc = "Field `LEBDELAY` writer - Leading-Edge Blanking Delay for TRGINx"] -pub type LEBDELAY_W<'a, const O: u8> = crate::FieldWriter<'a, LEBR2_SPEC, 7, O>; +pub type LEBDELAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `PWMLFEN` reader - PWML Falling Edge Enable"] pub type PWMLFEN_R = crate::BitReader; #[doc = "Field `PWMLFEN` writer - PWML Falling Edge Enable"] -pub type PWMLFEN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR2_SPEC, O>; +pub type PWMLFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWMLREN` reader - PWML Rising Edge Enable"] pub type PWMLREN_R = crate::BitReader; #[doc = "Field `PWMLREN` writer - PWML Rising Edge Enable"] -pub type PWMLREN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR2_SPEC, O>; +pub type PWMLREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWMHFEN` reader - PWMH Falling Edge Enable"] pub type PWMHFEN_R = crate::BitReader; #[doc = "Field `PWMHFEN` writer - PWMH Falling Edge Enable"] -pub type PWMHFEN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR2_SPEC, O>; +pub type PWMHFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PWMHREN` reader - PWMH Rising Edge Enable"] pub type PWMHREN_R = crate::BitReader; #[doc = "Field `PWMHREN` writer - PWMH Rising Edge Enable"] -pub type PWMHREN_W<'a, const O: u8> = crate::BitWriter<'a, LEBR2_SPEC, O>; +pub type PWMHREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Leading-Edge Blanking Delay for TRGINx"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bits 0:6 - Leading-Edge Blanking Delay for TRGINx"] #[inline(always)] #[must_use] - pub fn lebdelay(&mut self) -> LEBDELAY_W<0> { + pub fn lebdelay(&mut self) -> LEBDELAY_W { LEBDELAY_W::new(self) } #[doc = "Bit 16 - PWML Falling Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmlfen(&mut self) -> PWMLFEN_W<16> { + pub fn pwmlfen(&mut self) -> PWMLFEN_W { PWMLFEN_W::new(self) } #[doc = "Bit 17 - PWML Rising Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmlren(&mut self) -> PWMLREN_W<17> { + pub fn pwmlren(&mut self) -> PWMLREN_W { PWMLREN_W::new(self) } #[doc = "Bit 18 - PWMH Falling Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmhfen(&mut self) -> PWMHFEN_W<18> { + pub fn pwmhfen(&mut self) -> PWMHFEN_W { PWMHFEN_W::new(self) } #[doc = "Bit 19 - PWMH Rising Edge Enable"] #[inline(always)] #[must_use] - pub fn pwmhren(&mut self) -> PWMHREN_W<19> { + pub fn pwmhren(&mut self) -> PWMHREN_W { PWMHREN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Leading-Edge Blanking Register (trg_num = 2)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lebr2](index.html) module"] +#[doc = "PWM Leading-Edge Blanking Register (trg_num = 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lebr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lebr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct LEBR2_SPEC; impl crate::RegisterSpec for LEBR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [lebr2::R](R) reader structure"] -impl crate::Readable for LEBR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [lebr2::W](W) writer structure"] +#[doc = "`read()` method returns [`lebr2::R`](R) reader structure"] +impl crate::Readable for LEBR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lebr2::W`](W) writer structure"] impl crate::Writable for LEBR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/oov.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/oov.rs index c0653d11..de0ff1e9 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/oov.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/oov.rs @@ -1,71 +1,39 @@ #[doc = "Register `OOV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `OOV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OOVH0` reader - Output Override Value for PWMH output of the channel 0"] pub type OOVH0_R = crate::BitReader; #[doc = "Field `OOVH0` writer - Output Override Value for PWMH output of the channel 0"] -pub type OOVH0_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVH1` reader - Output Override Value for PWMH output of the channel 1"] pub type OOVH1_R = crate::BitReader; #[doc = "Field `OOVH1` writer - Output Override Value for PWMH output of the channel 1"] -pub type OOVH1_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVH2` reader - Output Override Value for PWMH output of the channel 2"] pub type OOVH2_R = crate::BitReader; #[doc = "Field `OOVH2` writer - Output Override Value for PWMH output of the channel 2"] -pub type OOVH2_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVH3` reader - Output Override Value for PWMH output of the channel 3"] pub type OOVH3_R = crate::BitReader; #[doc = "Field `OOVH3` writer - Output Override Value for PWMH output of the channel 3"] -pub type OOVH3_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVL0` reader - Output Override Value for PWML output of the channel 0"] pub type OOVL0_R = crate::BitReader; #[doc = "Field `OOVL0` writer - Output Override Value for PWML output of the channel 0"] -pub type OOVL0_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVL1` reader - Output Override Value for PWML output of the channel 1"] pub type OOVL1_R = crate::BitReader; #[doc = "Field `OOVL1` writer - Output Override Value for PWML output of the channel 1"] -pub type OOVL1_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVL2` reader - Output Override Value for PWML output of the channel 2"] pub type OOVL2_R = crate::BitReader; #[doc = "Field `OOVL2` writer - Output Override Value for PWML output of the channel 2"] -pub type OOVL2_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OOVL3` reader - Output Override Value for PWML output of the channel 3"] pub type OOVL3_R = crate::BitReader; #[doc = "Field `OOVL3` writer - Output Override Value for PWML output of the channel 3"] -pub type OOVL3_W<'a, const O: u8> = crate::BitWriter<'a, OOV_SPEC, O>; +pub type OOVL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Output Override Value for PWMH output of the channel 0"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bit 0 - Output Override Value for PWMH output of the channel 0"] #[inline(always)] #[must_use] - pub fn oovh0(&mut self) -> OOVH0_W<0> { + pub fn oovh0(&mut self) -> OOVH0_W { OOVH0_W::new(self) } #[doc = "Bit 1 - Output Override Value for PWMH output of the channel 1"] #[inline(always)] #[must_use] - pub fn oovh1(&mut self) -> OOVH1_W<1> { + pub fn oovh1(&mut self) -> OOVH1_W { OOVH1_W::new(self) } #[doc = "Bit 2 - Output Override Value for PWMH output of the channel 2"] #[inline(always)] #[must_use] - pub fn oovh2(&mut self) -> OOVH2_W<2> { + pub fn oovh2(&mut self) -> OOVH2_W { OOVH2_W::new(self) } #[doc = "Bit 3 - Output Override Value for PWMH output of the channel 3"] #[inline(always)] #[must_use] - pub fn oovh3(&mut self) -> OOVH3_W<3> { + pub fn oovh3(&mut self) -> OOVH3_W { OOVH3_W::new(self) } #[doc = "Bit 16 - Output Override Value for PWML output of the channel 0"] #[inline(always)] #[must_use] - pub fn oovl0(&mut self) -> OOVL0_W<16> { + pub fn oovl0(&mut self) -> OOVL0_W { OOVL0_W::new(self) } #[doc = "Bit 17 - Output Override Value for PWML output of the channel 1"] #[inline(always)] #[must_use] - pub fn oovl1(&mut self) -> OOVL1_W<17> { + pub fn oovl1(&mut self) -> OOVL1_W { OOVL1_W::new(self) } #[doc = "Bit 18 - Output Override Value for PWML output of the channel 2"] #[inline(always)] #[must_use] - pub fn oovl2(&mut self) -> OOVL2_W<18> { + pub fn oovl2(&mut self) -> OOVL2_W { OOVL2_W::new(self) } #[doc = "Bit 19 - Output Override Value for PWML output of the channel 3"] #[inline(always)] #[must_use] - pub fn oovl3(&mut self) -> OOVL3_W<19> { + pub fn oovl3(&mut self) -> OOVL3_W { OOVL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Output Override Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oov](index.html) module"] +#[doc = "PWM Output Override Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oov::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oov::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OOV_SPEC; impl crate::RegisterSpec for OOV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [oov::R](R) reader structure"] -impl crate::Readable for OOV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [oov::W](W) writer structure"] +#[doc = "`read()` method returns [`oov::R`](R) reader structure"] +impl crate::Readable for OOV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`oov::W`](W) writer structure"] impl crate::Writable for OOV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/os.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/os.rs index 7301e3d2..340c3356 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/os.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/os.rs @@ -1,71 +1,39 @@ #[doc = "Register `OS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `OS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OSH0` reader - Output Selection for PWMH output of the channel 0"] pub type OSH0_R = crate::BitReader; #[doc = "Field `OSH0` writer - Output Selection for PWMH output of the channel 0"] -pub type OSH0_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSH1` reader - Output Selection for PWMH output of the channel 1"] pub type OSH1_R = crate::BitReader; #[doc = "Field `OSH1` writer - Output Selection for PWMH output of the channel 1"] -pub type OSH1_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSH2` reader - Output Selection for PWMH output of the channel 2"] pub type OSH2_R = crate::BitReader; #[doc = "Field `OSH2` writer - Output Selection for PWMH output of the channel 2"] -pub type OSH2_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSH3` reader - Output Selection for PWMH output of the channel 3"] pub type OSH3_R = crate::BitReader; #[doc = "Field `OSH3` writer - Output Selection for PWMH output of the channel 3"] -pub type OSH3_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSL0` reader - Output Selection for PWML output of the channel 0"] pub type OSL0_R = crate::BitReader; #[doc = "Field `OSL0` writer - Output Selection for PWML output of the channel 0"] -pub type OSL0_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSL1` reader - Output Selection for PWML output of the channel 1"] pub type OSL1_R = crate::BitReader; #[doc = "Field `OSL1` writer - Output Selection for PWML output of the channel 1"] -pub type OSL1_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSL2` reader - Output Selection for PWML output of the channel 2"] pub type OSL2_R = crate::BitReader; #[doc = "Field `OSL2` writer - Output Selection for PWML output of the channel 2"] -pub type OSL2_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSL3` reader - Output Selection for PWML output of the channel 3"] pub type OSL3_R = crate::BitReader; #[doc = "Field `OSL3` writer - Output Selection for PWML output of the channel 3"] -pub type OSL3_W<'a, const O: u8> = crate::BitWriter<'a, OS_SPEC, O>; +pub type OSL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Output Selection for PWMH output of the channel 0"] #[inline(always)] @@ -112,70 +80,67 @@ impl W { #[doc = "Bit 0 - Output Selection for PWMH output of the channel 0"] #[inline(always)] #[must_use] - pub fn osh0(&mut self) -> OSH0_W<0> { + pub fn osh0(&mut self) -> OSH0_W { OSH0_W::new(self) } #[doc = "Bit 1 - Output Selection for PWMH output of the channel 1"] #[inline(always)] #[must_use] - pub fn osh1(&mut self) -> OSH1_W<1> { + pub fn osh1(&mut self) -> OSH1_W { OSH1_W::new(self) } #[doc = "Bit 2 - Output Selection for PWMH output of the channel 2"] #[inline(always)] #[must_use] - pub fn osh2(&mut self) -> OSH2_W<2> { + pub fn osh2(&mut self) -> OSH2_W { OSH2_W::new(self) } #[doc = "Bit 3 - Output Selection for PWMH output of the channel 3"] #[inline(always)] #[must_use] - pub fn osh3(&mut self) -> OSH3_W<3> { + pub fn osh3(&mut self) -> OSH3_W { OSH3_W::new(self) } #[doc = "Bit 16 - Output Selection for PWML output of the channel 0"] #[inline(always)] #[must_use] - pub fn osl0(&mut self) -> OSL0_W<16> { + pub fn osl0(&mut self) -> OSL0_W { OSL0_W::new(self) } #[doc = "Bit 17 - Output Selection for PWML output of the channel 1"] #[inline(always)] #[must_use] - pub fn osl1(&mut self) -> OSL1_W<17> { + pub fn osl1(&mut self) -> OSL1_W { OSL1_W::new(self) } #[doc = "Bit 18 - Output Selection for PWML output of the channel 2"] #[inline(always)] #[must_use] - pub fn osl2(&mut self) -> OSL2_W<18> { + pub fn osl2(&mut self) -> OSL2_W { OSL2_W::new(self) } #[doc = "Bit 19 - Output Selection for PWML output of the channel 3"] #[inline(always)] #[must_use] - pub fn osl3(&mut self) -> OSL3_W<19> { + pub fn osl3(&mut self) -> OSL3_W { OSL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Output Selection Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [os](index.html) module"] +#[doc = "PWM Output Selection Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`os::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`os::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OS_SPEC; impl crate::RegisterSpec for OS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [os::R](R) reader structure"] -impl crate::Readable for OS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [os::W](W) writer structure"] +#[doc = "`read()` method returns [`os::R`](R) reader structure"] +impl crate::Readable for OS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`os::W`](W) writer structure"] impl crate::Writable for OS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/osc.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/osc.rs index e5dfe4ff..dfd03d05 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/osc.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/osc.rs @@ -1,104 +1,84 @@ #[doc = "Register `OSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OSCH0` writer - Output Selection Clear for PWMH output of the channel 0"] -pub type OSCH0_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCH1` writer - Output Selection Clear for PWMH output of the channel 1"] -pub type OSCH1_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCH2` writer - Output Selection Clear for PWMH output of the channel 2"] -pub type OSCH2_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCH3` writer - Output Selection Clear for PWMH output of the channel 3"] -pub type OSCH3_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCL0` writer - Output Selection Clear for PWML output of the channel 0"] -pub type OSCL0_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCL1` writer - Output Selection Clear for PWML output of the channel 1"] -pub type OSCL1_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCL2` writer - Output Selection Clear for PWML output of the channel 2"] -pub type OSCL2_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCL3` writer - Output Selection Clear for PWML output of the channel 3"] -pub type OSCL3_W<'a, const O: u8> = crate::BitWriter<'a, OSC_SPEC, O>; +pub type OSCL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Selection Clear for PWMH output of the channel 0"] #[inline(always)] #[must_use] - pub fn osch0(&mut self) -> OSCH0_W<0> { + pub fn osch0(&mut self) -> OSCH0_W { OSCH0_W::new(self) } #[doc = "Bit 1 - Output Selection Clear for PWMH output of the channel 1"] #[inline(always)] #[must_use] - pub fn osch1(&mut self) -> OSCH1_W<1> { + pub fn osch1(&mut self) -> OSCH1_W { OSCH1_W::new(self) } #[doc = "Bit 2 - Output Selection Clear for PWMH output of the channel 2"] #[inline(always)] #[must_use] - pub fn osch2(&mut self) -> OSCH2_W<2> { + pub fn osch2(&mut self) -> OSCH2_W { OSCH2_W::new(self) } #[doc = "Bit 3 - Output Selection Clear for PWMH output of the channel 3"] #[inline(always)] #[must_use] - pub fn osch3(&mut self) -> OSCH3_W<3> { + pub fn osch3(&mut self) -> OSCH3_W { OSCH3_W::new(self) } #[doc = "Bit 16 - Output Selection Clear for PWML output of the channel 0"] #[inline(always)] #[must_use] - pub fn oscl0(&mut self) -> OSCL0_W<16> { + pub fn oscl0(&mut self) -> OSCL0_W { OSCL0_W::new(self) } #[doc = "Bit 17 - Output Selection Clear for PWML output of the channel 1"] #[inline(always)] #[must_use] - pub fn oscl1(&mut self) -> OSCL1_W<17> { + pub fn oscl1(&mut self) -> OSCL1_W { OSCL1_W::new(self) } #[doc = "Bit 18 - Output Selection Clear for PWML output of the channel 2"] #[inline(always)] #[must_use] - pub fn oscl2(&mut self) -> OSCL2_W<18> { + pub fn oscl2(&mut self) -> OSCL2_W { OSCL2_W::new(self) } #[doc = "Bit 19 - Output Selection Clear for PWML output of the channel 3"] #[inline(always)] #[must_use] - pub fn oscl3(&mut self) -> OSCL3_W<19> { + pub fn oscl3(&mut self) -> OSCL3_W { OSCL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Output Selection Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc](index.html) module"] +#[doc = "PWM Output Selection Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`osc::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OSC_SPEC; impl crate::RegisterSpec for OSC_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [osc::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`osc::W`](W) writer structure"] impl crate::Writable for OSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/oscupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/oscupd.rs index 8053a5ac..3f9eb95e 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/oscupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/oscupd.rs @@ -1,104 +1,84 @@ #[doc = "Register `OSCUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OSCUPH0` writer - Output Selection Clear for PWMH output of the channel 0"] -pub type OSCUPH0_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPH1` writer - Output Selection Clear for PWMH output of the channel 1"] -pub type OSCUPH1_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPH2` writer - Output Selection Clear for PWMH output of the channel 2"] -pub type OSCUPH2_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPH3` writer - Output Selection Clear for PWMH output of the channel 3"] -pub type OSCUPH3_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPL0` writer - Output Selection Clear for PWML output of the channel 0"] -pub type OSCUPL0_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPL1` writer - Output Selection Clear for PWML output of the channel 1"] -pub type OSCUPL1_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPL2` writer - Output Selection Clear for PWML output of the channel 2"] -pub type OSCUPL2_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCUPL3` writer - Output Selection Clear for PWML output of the channel 3"] -pub type OSCUPL3_W<'a, const O: u8> = crate::BitWriter<'a, OSCUPD_SPEC, O>; +pub type OSCUPL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Selection Clear for PWMH output of the channel 0"] #[inline(always)] #[must_use] - pub fn oscuph0(&mut self) -> OSCUPH0_W<0> { + pub fn oscuph0(&mut self) -> OSCUPH0_W { OSCUPH0_W::new(self) } #[doc = "Bit 1 - Output Selection Clear for PWMH output of the channel 1"] #[inline(always)] #[must_use] - pub fn oscuph1(&mut self) -> OSCUPH1_W<1> { + pub fn oscuph1(&mut self) -> OSCUPH1_W { OSCUPH1_W::new(self) } #[doc = "Bit 2 - Output Selection Clear for PWMH output of the channel 2"] #[inline(always)] #[must_use] - pub fn oscuph2(&mut self) -> OSCUPH2_W<2> { + pub fn oscuph2(&mut self) -> OSCUPH2_W { OSCUPH2_W::new(self) } #[doc = "Bit 3 - Output Selection Clear for PWMH output of the channel 3"] #[inline(always)] #[must_use] - pub fn oscuph3(&mut self) -> OSCUPH3_W<3> { + pub fn oscuph3(&mut self) -> OSCUPH3_W { OSCUPH3_W::new(self) } #[doc = "Bit 16 - Output Selection Clear for PWML output of the channel 0"] #[inline(always)] #[must_use] - pub fn oscupl0(&mut self) -> OSCUPL0_W<16> { + pub fn oscupl0(&mut self) -> OSCUPL0_W { OSCUPL0_W::new(self) } #[doc = "Bit 17 - Output Selection Clear for PWML output of the channel 1"] #[inline(always)] #[must_use] - pub fn oscupl1(&mut self) -> OSCUPL1_W<17> { + pub fn oscupl1(&mut self) -> OSCUPL1_W { OSCUPL1_W::new(self) } #[doc = "Bit 18 - Output Selection Clear for PWML output of the channel 2"] #[inline(always)] #[must_use] - pub fn oscupl2(&mut self) -> OSCUPL2_W<18> { + pub fn oscupl2(&mut self) -> OSCUPL2_W { OSCUPL2_W::new(self) } #[doc = "Bit 19 - Output Selection Clear for PWML output of the channel 3"] #[inline(always)] #[must_use] - pub fn oscupl3(&mut self) -> OSCUPL3_W<19> { + pub fn oscupl3(&mut self) -> OSCUPL3_W { OSCUPL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Output Selection Clear Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oscupd](index.html) module"] +#[doc = "PWM Output Selection Clear Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oscupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OSCUPD_SPEC; impl crate::RegisterSpec for OSCUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [oscupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`oscupd::W`](W) writer structure"] impl crate::Writable for OSCUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/oss.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/oss.rs index bcb89f80..653f364c 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/oss.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/oss.rs @@ -1,104 +1,84 @@ #[doc = "Register `OSS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OSSH0` writer - Output Selection Set for PWMH output of the channel 0"] -pub type OSSH0_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSH1` writer - Output Selection Set for PWMH output of the channel 1"] -pub type OSSH1_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSH2` writer - Output Selection Set for PWMH output of the channel 2"] -pub type OSSH2_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSH3` writer - Output Selection Set for PWMH output of the channel 3"] -pub type OSSH3_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSL0` writer - Output Selection Set for PWML output of the channel 0"] -pub type OSSL0_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSL1` writer - Output Selection Set for PWML output of the channel 1"] -pub type OSSL1_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSL2` writer - Output Selection Set for PWML output of the channel 2"] -pub type OSSL2_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSL3` writer - Output Selection Set for PWML output of the channel 3"] -pub type OSSL3_W<'a, const O: u8> = crate::BitWriter<'a, OSS_SPEC, O>; +pub type OSSL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Selection Set for PWMH output of the channel 0"] #[inline(always)] #[must_use] - pub fn ossh0(&mut self) -> OSSH0_W<0> { + pub fn ossh0(&mut self) -> OSSH0_W { OSSH0_W::new(self) } #[doc = "Bit 1 - Output Selection Set for PWMH output of the channel 1"] #[inline(always)] #[must_use] - pub fn ossh1(&mut self) -> OSSH1_W<1> { + pub fn ossh1(&mut self) -> OSSH1_W { OSSH1_W::new(self) } #[doc = "Bit 2 - Output Selection Set for PWMH output of the channel 2"] #[inline(always)] #[must_use] - pub fn ossh2(&mut self) -> OSSH2_W<2> { + pub fn ossh2(&mut self) -> OSSH2_W { OSSH2_W::new(self) } #[doc = "Bit 3 - Output Selection Set for PWMH output of the channel 3"] #[inline(always)] #[must_use] - pub fn ossh3(&mut self) -> OSSH3_W<3> { + pub fn ossh3(&mut self) -> OSSH3_W { OSSH3_W::new(self) } #[doc = "Bit 16 - Output Selection Set for PWML output of the channel 0"] #[inline(always)] #[must_use] - pub fn ossl0(&mut self) -> OSSL0_W<16> { + pub fn ossl0(&mut self) -> OSSL0_W { OSSL0_W::new(self) } #[doc = "Bit 17 - Output Selection Set for PWML output of the channel 1"] #[inline(always)] #[must_use] - pub fn ossl1(&mut self) -> OSSL1_W<17> { + pub fn ossl1(&mut self) -> OSSL1_W { OSSL1_W::new(self) } #[doc = "Bit 18 - Output Selection Set for PWML output of the channel 2"] #[inline(always)] #[must_use] - pub fn ossl2(&mut self) -> OSSL2_W<18> { + pub fn ossl2(&mut self) -> OSSL2_W { OSSL2_W::new(self) } #[doc = "Bit 19 - Output Selection Set for PWML output of the channel 3"] #[inline(always)] #[must_use] - pub fn ossl3(&mut self) -> OSSL3_W<19> { + pub fn ossl3(&mut self) -> OSSL3_W { OSSL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Output Selection Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [oss](index.html) module"] +#[doc = "PWM Output Selection Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oss::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OSS_SPEC; impl crate::RegisterSpec for OSS_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [oss::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`oss::W`](W) writer structure"] impl crate::Writable for OSS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/ossupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/ossupd.rs index 5a56ab9f..cfadc3e5 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/ossupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/ossupd.rs @@ -1,104 +1,84 @@ #[doc = "Register `OSSUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `OSSUPH0` writer - Output Selection Set for PWMH output of the channel 0"] -pub type OSSUPH0_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPH0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPH1` writer - Output Selection Set for PWMH output of the channel 1"] -pub type OSSUPH1_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPH1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPH2` writer - Output Selection Set for PWMH output of the channel 2"] -pub type OSSUPH2_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPH2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPH3` writer - Output Selection Set for PWMH output of the channel 3"] -pub type OSSUPH3_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPH3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPL0` writer - Output Selection Set for PWML output of the channel 0"] -pub type OSSUPL0_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPL0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPL1` writer - Output Selection Set for PWML output of the channel 1"] -pub type OSSUPL1_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPL1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPL2` writer - Output Selection Set for PWML output of the channel 2"] -pub type OSSUPL2_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPL2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSSUPL3` writer - Output Selection Set for PWML output of the channel 3"] -pub type OSSUPL3_W<'a, const O: u8> = crate::BitWriter<'a, OSSUPD_SPEC, O>; +pub type OSSUPL3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Output Selection Set for PWMH output of the channel 0"] #[inline(always)] #[must_use] - pub fn ossuph0(&mut self) -> OSSUPH0_W<0> { + pub fn ossuph0(&mut self) -> OSSUPH0_W { OSSUPH0_W::new(self) } #[doc = "Bit 1 - Output Selection Set for PWMH output of the channel 1"] #[inline(always)] #[must_use] - pub fn ossuph1(&mut self) -> OSSUPH1_W<1> { + pub fn ossuph1(&mut self) -> OSSUPH1_W { OSSUPH1_W::new(self) } #[doc = "Bit 2 - Output Selection Set for PWMH output of the channel 2"] #[inline(always)] #[must_use] - pub fn ossuph2(&mut self) -> OSSUPH2_W<2> { + pub fn ossuph2(&mut self) -> OSSUPH2_W { OSSUPH2_W::new(self) } #[doc = "Bit 3 - Output Selection Set for PWMH output of the channel 3"] #[inline(always)] #[must_use] - pub fn ossuph3(&mut self) -> OSSUPH3_W<3> { + pub fn ossuph3(&mut self) -> OSSUPH3_W { OSSUPH3_W::new(self) } #[doc = "Bit 16 - Output Selection Set for PWML output of the channel 0"] #[inline(always)] #[must_use] - pub fn ossupl0(&mut self) -> OSSUPL0_W<16> { + pub fn ossupl0(&mut self) -> OSSUPL0_W { OSSUPL0_W::new(self) } #[doc = "Bit 17 - Output Selection Set for PWML output of the channel 1"] #[inline(always)] #[must_use] - pub fn ossupl1(&mut self) -> OSSUPL1_W<17> { + pub fn ossupl1(&mut self) -> OSSUPL1_W { OSSUPL1_W::new(self) } #[doc = "Bit 18 - Output Selection Set for PWML output of the channel 2"] #[inline(always)] #[must_use] - pub fn ossupl2(&mut self) -> OSSUPL2_W<18> { + pub fn ossupl2(&mut self) -> OSSUPL2_W { OSSUPL2_W::new(self) } #[doc = "Bit 19 - Output Selection Set for PWML output of the channel 3"] #[inline(always)] #[must_use] - pub fn ossupl3(&mut self) -> OSSUPL3_W<19> { + pub fn ossupl3(&mut self) -> OSSUPL3_W { OSSUPL3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Output Selection Set Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ossupd](index.html) module"] +#[doc = "PWM Output Selection Set Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ossupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OSSUPD_SPEC; impl crate::RegisterSpec for OSSUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ossupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ossupd::W`](W) writer structure"] impl crate::Writable for OSSUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num.rs index 1297555d..2d0b732a 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num.rs @@ -18,35 +18,43 @@ pub struct PWM_CH_NUM { #[doc = "0x1c - PWM Channel Dead Time Update Register"] pub dtupd: DTUPD, } -#[doc = "CMR (rw) register accessor: an alias for `Reg`"] +#[doc = "CMR (rw) register accessor: PWM Channel Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmr`] +module"] pub type CMR = crate::Reg; #[doc = "PWM Channel Mode Register"] pub mod cmr; -#[doc = "CDTY (rw) register accessor: an alias for `Reg`"] +#[doc = "CDTY (rw) register accessor: PWM Channel Duty Cycle Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdty::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cdty`] +module"] pub type CDTY = crate::Reg; #[doc = "PWM Channel Duty Cycle Register"] pub mod cdty; -#[doc = "CDTYUPD (w) register accessor: an alias for `Reg`"] +#[doc = "CDTYUPD (w) register accessor: PWM Channel Duty Cycle Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdtyupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cdtyupd`] +module"] pub type CDTYUPD = crate::Reg; #[doc = "PWM Channel Duty Cycle Update Register"] pub mod cdtyupd; -#[doc = "CPRD (rw) register accessor: an alias for `Reg`"] +#[doc = "CPRD (rw) register accessor: PWM Channel Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cprd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cprd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cprd`] +module"] pub type CPRD = crate::Reg; #[doc = "PWM Channel Period Register"] pub mod cprd; -#[doc = "CPRDUPD (w) register accessor: an alias for `Reg`"] +#[doc = "CPRDUPD (w) register accessor: PWM Channel Period Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cprdupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cprdupd`] +module"] pub type CPRDUPD = crate::Reg; #[doc = "PWM Channel Period Update Register"] pub mod cprdupd; -#[doc = "CCNT (r) register accessor: an alias for `Reg`"] +#[doc = "CCNT (r) register accessor: PWM Channel Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccnt`] +module"] pub type CCNT = crate::Reg; #[doc = "PWM Channel Counter Register"] pub mod ccnt; -#[doc = "DT (rw) register accessor: an alias for `Reg`"] +#[doc = "DT (rw) register accessor: PWM Channel Dead Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dt`] +module"] pub type DT = crate::Reg; #[doc = "PWM Channel Dead Time Register"] pub mod dt; -#[doc = "DTUPD (w) register accessor: an alias for `Reg`"] +#[doc = "DTUPD (w) register accessor: PWM Channel Dead Time Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`dtupd`] +module"] pub type DTUPD = crate::Reg; #[doc = "PWM Channel Dead Time Update Register"] pub mod dtupd; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/ccnt.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/ccnt.rs index a0fa0f1f..8ea651c5 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/ccnt.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/ccnt.rs @@ -1,18 +1,5 @@ #[doc = "Register `CCNT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CNT` reader - Channel Counter Register"] pub type CNT_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CNT_R::new(self.bits & 0x00ff_ffff) } } -#[doc = "PWM Channel Counter Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccnt](index.html) module"] +#[doc = "PWM Channel Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccnt::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCNT_SPEC; impl crate::RegisterSpec for CCNT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ccnt::R](R) reader structure"] -impl crate::Readable for CCNT_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ccnt::R`](R) reader structure"] +impl crate::Readable for CCNT_SPEC {} #[doc = "`reset()` method sets CCNT to value 0"] impl crate::Resettable for CCNT_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdty.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdty.rs index a5e8361d..fb54e745 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdty.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdty.rs @@ -1,43 +1,11 @@ #[doc = "Register `CDTY` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CDTY` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDTY` reader - Channel Duty-Cycle"] pub type CDTY_R = crate::FieldReader; #[doc = "Field `CDTY` writer - Channel Duty-Cycle"] -pub type CDTY_W<'a, const O: u8> = crate::FieldWriter<'a, CDTY_SPEC, 24, O, u32>; +pub type CDTY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Channel Duty-Cycle"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Channel Duty-Cycle"] #[inline(always)] #[must_use] - pub fn cdty(&mut self) -> CDTY_W<0> { + pub fn cdty(&mut self) -> CDTY_W { CDTY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Duty Cycle Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cdty](index.html) module"] +#[doc = "PWM Channel Duty Cycle Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdty::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdty::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDTY_SPEC; impl crate::RegisterSpec for CDTY_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cdty::R](R) reader structure"] -impl crate::Readable for CDTY_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cdty::W](W) writer structure"] +#[doc = "`read()` method returns [`cdty::R`](R) reader structure"] +impl crate::Readable for CDTY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cdty::W`](W) writer structure"] impl crate::Writable for CDTY_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdtyupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdtyupd.rs index af1d6634..ec25c514 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdtyupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cdtyupd.rs @@ -1,48 +1,28 @@ #[doc = "Register `CDTYUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CDTYUPD` writer - Channel Duty-Cycle Update"] -pub type CDTYUPD_W<'a, const O: u8> = crate::FieldWriter<'a, CDTYUPD_SPEC, 24, O, u32>; +pub type CDTYUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl W { #[doc = "Bits 0:23 - Channel Duty-Cycle Update"] #[inline(always)] #[must_use] - pub fn cdtyupd(&mut self) -> CDTYUPD_W<0> { + pub fn cdtyupd(&mut self) -> CDTYUPD_W { CDTYUPD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Duty Cycle Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cdtyupd](index.html) module"] +#[doc = "PWM Channel Duty Cycle Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdtyupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDTYUPD_SPEC; impl crate::RegisterSpec for CDTYUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cdtyupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cdtyupd::W`](W) writer structure"] impl crate::Writable for CDTYUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cmr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cmr.rs index 46cd580b..4191dbfe 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cmr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPRE` reader - Channel Pre-scaler"] pub type CPRE_R = crate::FieldReader; #[doc = "Channel Pre-scaler\n\nValue on reset: 0"] @@ -97,138 +65,142 @@ impl CPRE_R { _ => None, } } - #[doc = "Checks if the value of the field is `MCK`"] + #[doc = "Peripheral clock"] #[inline(always)] pub fn is_mck(&self) -> bool { *self == CPRESELECT_A::MCK } - #[doc = "Checks if the value of the field is `MCK_DIV_2`"] + #[doc = "Peripheral clock/2"] #[inline(always)] pub fn is_mck_div_2(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_2 } - #[doc = "Checks if the value of the field is `MCK_DIV_4`"] + #[doc = "Peripheral clock/4"] #[inline(always)] pub fn is_mck_div_4(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_4 } - #[doc = "Checks if the value of the field is `MCK_DIV_8`"] + #[doc = "Peripheral clock/8"] #[inline(always)] pub fn is_mck_div_8(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_8 } - #[doc = "Checks if the value of the field is `MCK_DIV_16`"] + #[doc = "Peripheral clock/16"] #[inline(always)] pub fn is_mck_div_16(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_16 } - #[doc = "Checks if the value of the field is `MCK_DIV_32`"] + #[doc = "Peripheral clock/32"] #[inline(always)] pub fn is_mck_div_32(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_32 } - #[doc = "Checks if the value of the field is `MCK_DIV_64`"] + #[doc = "Peripheral clock/64"] #[inline(always)] pub fn is_mck_div_64(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_64 } - #[doc = "Checks if the value of the field is `MCK_DIV_128`"] + #[doc = "Peripheral clock/128"] #[inline(always)] pub fn is_mck_div_128(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_128 } - #[doc = "Checks if the value of the field is `MCK_DIV_256`"] + #[doc = "Peripheral clock/256"] #[inline(always)] pub fn is_mck_div_256(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_256 } - #[doc = "Checks if the value of the field is `MCK_DIV_512`"] + #[doc = "Peripheral clock/512"] #[inline(always)] pub fn is_mck_div_512(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_512 } - #[doc = "Checks if the value of the field is `MCK_DIV_1024`"] + #[doc = "Peripheral clock/1024"] #[inline(always)] pub fn is_mck_div_1024(&self) -> bool { *self == CPRESELECT_A::MCK_DIV_1024 } - #[doc = "Checks if the value of the field is `CLKA`"] + #[doc = "Clock A"] #[inline(always)] pub fn is_clka(&self) -> bool { *self == CPRESELECT_A::CLKA } - #[doc = "Checks if the value of the field is `CLKB`"] + #[doc = "Clock B"] #[inline(always)] pub fn is_clkb(&self) -> bool { *self == CPRESELECT_A::CLKB } } #[doc = "Field `CPRE` writer - Channel Pre-scaler"] -pub type CPRE_W<'a, const O: u8> = crate::FieldWriter<'a, CMR_SPEC, 4, O, CPRESELECT_A>; -impl<'a, const O: u8> CPRE_W<'a, O> { +pub type CPRE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, CPRESELECT_A>; +impl<'a, REG, const O: u8> CPRE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Peripheral clock"] #[inline(always)] - pub fn mck(self) -> &'a mut W { + pub fn mck(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK) } #[doc = "Peripheral clock/2"] #[inline(always)] - pub fn mck_div_2(self) -> &'a mut W { + pub fn mck_div_2(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_2) } #[doc = "Peripheral clock/4"] #[inline(always)] - pub fn mck_div_4(self) -> &'a mut W { + pub fn mck_div_4(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_4) } #[doc = "Peripheral clock/8"] #[inline(always)] - pub fn mck_div_8(self) -> &'a mut W { + pub fn mck_div_8(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_8) } #[doc = "Peripheral clock/16"] #[inline(always)] - pub fn mck_div_16(self) -> &'a mut W { + pub fn mck_div_16(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_16) } #[doc = "Peripheral clock/32"] #[inline(always)] - pub fn mck_div_32(self) -> &'a mut W { + pub fn mck_div_32(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_32) } #[doc = "Peripheral clock/64"] #[inline(always)] - pub fn mck_div_64(self) -> &'a mut W { + pub fn mck_div_64(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_64) } #[doc = "Peripheral clock/128"] #[inline(always)] - pub fn mck_div_128(self) -> &'a mut W { + pub fn mck_div_128(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_128) } #[doc = "Peripheral clock/256"] #[inline(always)] - pub fn mck_div_256(self) -> &'a mut W { + pub fn mck_div_256(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_256) } #[doc = "Peripheral clock/512"] #[inline(always)] - pub fn mck_div_512(self) -> &'a mut W { + pub fn mck_div_512(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_512) } #[doc = "Peripheral clock/1024"] #[inline(always)] - pub fn mck_div_1024(self) -> &'a mut W { + pub fn mck_div_1024(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::MCK_DIV_1024) } #[doc = "Clock A"] #[inline(always)] - pub fn clka(self) -> &'a mut W { + pub fn clka(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::CLKA) } #[doc = "Clock B"] #[inline(always)] - pub fn clkb(self) -> &'a mut W { + pub fn clkb(self) -> &'a mut crate::W { self.variant(CPRESELECT_A::CLKB) } } @@ -257,28 +229,31 @@ impl CALG_R { true => CALGSELECT_A::CENTER_ALIGNED, } } - #[doc = "Checks if the value of the field is `LEFT_ALIGNED`"] + #[doc = "Left aligned"] #[inline(always)] pub fn is_left_aligned(&self) -> bool { *self == CALGSELECT_A::LEFT_ALIGNED } - #[doc = "Checks if the value of the field is `CENTER_ALIGNED`"] + #[doc = "Center aligned"] #[inline(always)] pub fn is_center_aligned(&self) -> bool { *self == CALGSELECT_A::CENTER_ALIGNED } } #[doc = "Field `CALG` writer - Channel Alignment"] -pub type CALG_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O, CALGSELECT_A>; -impl<'a, const O: u8> CALG_W<'a, O> { +pub type CALG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CALGSELECT_A>; +impl<'a, REG, const O: u8> CALG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Left aligned"] #[inline(always)] - pub fn left_aligned(self) -> &'a mut W { + pub fn left_aligned(self) -> &'a mut crate::W { self.variant(CALGSELECT_A::LEFT_ALIGNED) } #[doc = "Center aligned"] #[inline(always)] - pub fn center_aligned(self) -> &'a mut W { + pub fn center_aligned(self) -> &'a mut crate::W { self.variant(CALGSELECT_A::CENTER_ALIGNED) } } @@ -307,28 +282,31 @@ impl CPOL_R { true => CPOLSELECT_A::HIGH_POLARITY, } } - #[doc = "Checks if the value of the field is `LOW_POLARITY`"] + #[doc = "Waveform starts at low level"] #[inline(always)] pub fn is_low_polarity(&self) -> bool { *self == CPOLSELECT_A::LOW_POLARITY } - #[doc = "Checks if the value of the field is `HIGH_POLARITY`"] + #[doc = "Waveform starts at high level"] #[inline(always)] pub fn is_high_polarity(&self) -> bool { *self == CPOLSELECT_A::HIGH_POLARITY } } #[doc = "Field `CPOL` writer - Channel Polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O, CPOLSELECT_A>; -impl<'a, const O: u8> CPOL_W<'a, O> { +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CPOLSELECT_A>; +impl<'a, REG, const O: u8> CPOL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Waveform starts at low level"] #[inline(always)] - pub fn low_polarity(self) -> &'a mut W { + pub fn low_polarity(self) -> &'a mut crate::W { self.variant(CPOLSELECT_A::LOW_POLARITY) } #[doc = "Waveform starts at high level"] #[inline(always)] - pub fn high_polarity(self) -> &'a mut W { + pub fn high_polarity(self) -> &'a mut crate::W { self.variant(CPOLSELECT_A::HIGH_POLARITY) } } @@ -357,28 +335,31 @@ impl CES_R { true => CESSELECT_A::DOUBLE_EVENT, } } - #[doc = "Checks if the value of the field is `SINGLE_EVENT`"] + #[doc = "At the end of PWM period"] #[inline(always)] pub fn is_single_event(&self) -> bool { *self == CESSELECT_A::SINGLE_EVENT } - #[doc = "Checks if the value of the field is `DOUBLE_EVENT`"] + #[doc = "At half of PWM period AND at the end of PWM period"] #[inline(always)] pub fn is_double_event(&self) -> bool { *self == CESSELECT_A::DOUBLE_EVENT } } #[doc = "Field `CES` writer - Counter Event Selection"] -pub type CES_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O, CESSELECT_A>; -impl<'a, const O: u8> CES_W<'a, O> { +pub type CES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CESSELECT_A>; +impl<'a, REG, const O: u8> CES_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "At the end of PWM period"] #[inline(always)] - pub fn single_event(self) -> &'a mut W { + pub fn single_event(self) -> &'a mut crate::W { self.variant(CESSELECT_A::SINGLE_EVENT) } #[doc = "At half of PWM period AND at the end of PWM period"] #[inline(always)] - pub fn double_event(self) -> &'a mut W { + pub fn double_event(self) -> &'a mut crate::W { self.variant(CESSELECT_A::DOUBLE_EVENT) } } @@ -407,55 +388,58 @@ impl UPDS_R { true => UPDSSELECT_A::UPDATE_AT_HALF_PERIOD, } } - #[doc = "Checks if the value of the field is `UPDATE_AT_PERIOD`"] + #[doc = "At the next end of PWM period"] #[inline(always)] pub fn is_update_at_period(&self) -> bool { *self == UPDSSELECT_A::UPDATE_AT_PERIOD } - #[doc = "Checks if the value of the field is `UPDATE_AT_HALF_PERIOD`"] + #[doc = "At the next end of Half PWM period"] #[inline(always)] pub fn is_update_at_half_period(&self) -> bool { *self == UPDSSELECT_A::UPDATE_AT_HALF_PERIOD } } #[doc = "Field `UPDS` writer - Update Selection"] -pub type UPDS_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O, UPDSSELECT_A>; -impl<'a, const O: u8> UPDS_W<'a, O> { +pub type UPDS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, UPDSSELECT_A>; +impl<'a, REG, const O: u8> UPDS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "At the next end of PWM period"] #[inline(always)] - pub fn update_at_period(self) -> &'a mut W { + pub fn update_at_period(self) -> &'a mut crate::W { self.variant(UPDSSELECT_A::UPDATE_AT_PERIOD) } #[doc = "At the next end of Half PWM period"] #[inline(always)] - pub fn update_at_half_period(self) -> &'a mut W { + pub fn update_at_half_period(self) -> &'a mut crate::W { self.variant(UPDSSELECT_A::UPDATE_AT_HALF_PERIOD) } } #[doc = "Field `DPOLI` reader - Disabled Polarity Inverted"] pub type DPOLI_R = crate::BitReader; #[doc = "Field `DPOLI` writer - Disabled Polarity Inverted"] -pub type DPOLI_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O>; +pub type DPOLI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCTS` reader - Timer Counter Trigger Selection"] pub type TCTS_R = crate::BitReader; #[doc = "Field `TCTS` writer - Timer Counter Trigger Selection"] -pub type TCTS_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O>; +pub type TCTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTE` reader - Dead-Time Generator Enable"] pub type DTE_R = crate::BitReader; #[doc = "Field `DTE` writer - Dead-Time Generator Enable"] -pub type DTE_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O>; +pub type DTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTHI` reader - Dead-Time PWMHx Output Inverted"] pub type DTHI_R = crate::BitReader; #[doc = "Field `DTHI` writer - Dead-Time PWMHx Output Inverted"] -pub type DTHI_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O>; +pub type DTHI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTLI` reader - Dead-Time PWMLx Output Inverted"] pub type DTLI_R = crate::BitReader; #[doc = "Field `DTLI` writer - Dead-Time PWMLx Output Inverted"] -pub type DTLI_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O>; +pub type DTLI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PPM` reader - Push-Pull Mode"] pub type PPM_R = crate::BitReader; #[doc = "Field `PPM` writer - Push-Pull Mode"] -pub type PPM_W<'a, const O: u8> = crate::BitWriter<'a, CMR_SPEC, O>; +pub type PPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:3 - Channel Pre-scaler"] #[inline(always)] @@ -517,88 +501,85 @@ impl W { #[doc = "Bits 0:3 - Channel Pre-scaler"] #[inline(always)] #[must_use] - pub fn cpre(&mut self) -> CPRE_W<0> { + pub fn cpre(&mut self) -> CPRE_W { CPRE_W::new(self) } #[doc = "Bit 8 - Channel Alignment"] #[inline(always)] #[must_use] - pub fn calg(&mut self) -> CALG_W<8> { + pub fn calg(&mut self) -> CALG_W { CALG_W::new(self) } #[doc = "Bit 9 - Channel Polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<9> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bit 10 - Counter Event Selection"] #[inline(always)] #[must_use] - pub fn ces(&mut self) -> CES_W<10> { + pub fn ces(&mut self) -> CES_W { CES_W::new(self) } #[doc = "Bit 11 - Update Selection"] #[inline(always)] #[must_use] - pub fn upds(&mut self) -> UPDS_W<11> { + pub fn upds(&mut self) -> UPDS_W { UPDS_W::new(self) } #[doc = "Bit 12 - Disabled Polarity Inverted"] #[inline(always)] #[must_use] - pub fn dpoli(&mut self) -> DPOLI_W<12> { + pub fn dpoli(&mut self) -> DPOLI_W { DPOLI_W::new(self) } #[doc = "Bit 13 - Timer Counter Trigger Selection"] #[inline(always)] #[must_use] - pub fn tcts(&mut self) -> TCTS_W<13> { + pub fn tcts(&mut self) -> TCTS_W { TCTS_W::new(self) } #[doc = "Bit 16 - Dead-Time Generator Enable"] #[inline(always)] #[must_use] - pub fn dte(&mut self) -> DTE_W<16> { + pub fn dte(&mut self) -> DTE_W { DTE_W::new(self) } #[doc = "Bit 17 - Dead-Time PWMHx Output Inverted"] #[inline(always)] #[must_use] - pub fn dthi(&mut self) -> DTHI_W<17> { + pub fn dthi(&mut self) -> DTHI_W { DTHI_W::new(self) } #[doc = "Bit 18 - Dead-Time PWMLx Output Inverted"] #[inline(always)] #[must_use] - pub fn dtli(&mut self) -> DTLI_W<18> { + pub fn dtli(&mut self) -> DTLI_W { DTLI_W::new(self) } #[doc = "Bit 19 - Push-Pull Mode"] #[inline(always)] #[must_use] - pub fn ppm(&mut self) -> PPM_W<19> { + pub fn ppm(&mut self) -> PPM_W { PPM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr](index.html) module"] +#[doc = "PWM Channel Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMR_SPEC; impl crate::RegisterSpec for CMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmr::R](R) reader structure"] -impl crate::Readable for CMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmr::W](W) writer structure"] +#[doc = "`read()` method returns [`cmr::R`](R) reader structure"] +impl crate::Readable for CMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmr::W`](W) writer structure"] impl crate::Writable for CMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprd.rs index 8eb563d7..5dff73d5 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprd.rs @@ -1,43 +1,11 @@ #[doc = "Register `CPRD` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CPRD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPRD` reader - Channel Period"] pub type CPRD_R = crate::FieldReader; #[doc = "Field `CPRD` writer - Channel Period"] -pub type CPRD_W<'a, const O: u8> = crate::FieldWriter<'a, CPRD_SPEC, 24, O, u32>; +pub type CPRD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Channel Period"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Channel Period"] #[inline(always)] #[must_use] - pub fn cprd(&mut self) -> CPRD_W<0> { + pub fn cprd(&mut self) -> CPRD_W { CPRD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Period Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cprd](index.html) module"] +#[doc = "PWM Channel Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cprd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cprd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CPRD_SPEC; impl crate::RegisterSpec for CPRD_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cprd::R](R) reader structure"] -impl crate::Readable for CPRD_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cprd::W](W) writer structure"] +#[doc = "`read()` method returns [`cprd::R`](R) reader structure"] +impl crate::Readable for CPRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cprd::W`](W) writer structure"] impl crate::Writable for CPRD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprdupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprdupd.rs index aabf5f26..673ef4b0 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprdupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/cprdupd.rs @@ -1,48 +1,28 @@ #[doc = "Register `CPRDUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPRDUPD` writer - Channel Period Update"] -pub type CPRDUPD_W<'a, const O: u8> = crate::FieldWriter<'a, CPRDUPD_SPEC, 24, O, u32>; +pub type CPRDUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl W { #[doc = "Bits 0:23 - Channel Period Update"] #[inline(always)] #[must_use] - pub fn cprdupd(&mut self) -> CPRDUPD_W<0> { + pub fn cprdupd(&mut self) -> CPRDUPD_W { CPRDUPD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Period Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cprdupd](index.html) module"] +#[doc = "PWM Channel Period Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cprdupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CPRDUPD_SPEC; impl crate::RegisterSpec for CPRDUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cprdupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cprdupd::W`](W) writer structure"] impl crate::Writable for CPRDUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dt.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dt.rs index de2ff3fd..1a69164f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dt.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dt.rs @@ -1,47 +1,15 @@ #[doc = "Register `DT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DTH` reader - Dead-Time Value for PWMHx Output"] pub type DTH_R = crate::FieldReader; #[doc = "Field `DTH` writer - Dead-Time Value for PWMHx Output"] -pub type DTH_W<'a, const O: u8> = crate::FieldWriter<'a, DT_SPEC, 16, O, u16>; +pub type DTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `DTL` reader - Dead-Time Value for PWMLx Output"] pub type DTL_R = crate::FieldReader; #[doc = "Field `DTL` writer - Dead-Time Value for PWMLx Output"] -pub type DTL_W<'a, const O: u8> = crate::FieldWriter<'a, DT_SPEC, 16, O, u16>; +pub type DTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Dead-Time Value for PWMHx Output"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Dead-Time Value for PWMHx Output"] #[inline(always)] #[must_use] - pub fn dth(&mut self) -> DTH_W<0> { + pub fn dth(&mut self) -> DTH_W { DTH_W::new(self) } #[doc = "Bits 16:31 - Dead-Time Value for PWMLx Output"] #[inline(always)] #[must_use] - pub fn dtl(&mut self) -> DTL_W<16> { + pub fn dtl(&mut self) -> DTL_W { DTL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Dead Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dt](index.html) module"] +#[doc = "PWM Channel Dead Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DT_SPEC; impl crate::RegisterSpec for DT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [dt::R](R) reader structure"] -impl crate::Readable for DT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [dt::W](W) writer structure"] +#[doc = "`read()` method returns [`dt::R`](R) reader structure"] +impl crate::Readable for DT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dt::W`](W) writer structure"] impl crate::Writable for DT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dtupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dtupd.rs index e0e381d7..b44fd441 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dtupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_ch_num/dtupd.rs @@ -1,56 +1,36 @@ #[doc = "Register `DTUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DTHUPD` writer - Dead-Time Value Update for PWMHx Output"] -pub type DTHUPD_W<'a, const O: u8> = crate::FieldWriter<'a, DTUPD_SPEC, 16, O, u16>; +pub type DTHUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `DTLUPD` writer - Dead-Time Value Update for PWMLx Output"] -pub type DTLUPD_W<'a, const O: u8> = crate::FieldWriter<'a, DTUPD_SPEC, 16, O, u16>; +pub type DTLUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl W { #[doc = "Bits 0:15 - Dead-Time Value Update for PWMHx Output"] #[inline(always)] #[must_use] - pub fn dthupd(&mut self) -> DTHUPD_W<0> { + pub fn dthupd(&mut self) -> DTHUPD_W { DTHUPD_W::new(self) } #[doc = "Bits 16:31 - Dead-Time Value Update for PWMLx Output"] #[inline(always)] #[must_use] - pub fn dtlupd(&mut self) -> DTLUPD_W<16> { + pub fn dtlupd(&mut self) -> DTLUPD_W { DTLUPD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Channel Dead Time Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dtupd](index.html) module"] +#[doc = "PWM Channel Dead Time Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dtupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DTUPD_SPEC; impl crate::RegisterSpec for DTUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [dtupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`dtupd::W`](W) writer structure"] impl crate::Writable for DTUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp.rs index 240ec9cb..77bb036f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp.rs @@ -10,19 +10,23 @@ pub struct PWM_CMP { #[doc = "0x0c - PWM Comparison 0 Mode Update Register"] pub cmpmupd: CMPMUPD, } -#[doc = "CMPV (rw) register accessor: an alias for `Reg`"] +#[doc = "CMPV (rw) register accessor: PWM Comparison 0 Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmpv`] +module"] pub type CMPV = crate::Reg; #[doc = "PWM Comparison 0 Value Register"] pub mod cmpv; -#[doc = "CMPVUPD (w) register accessor: an alias for `Reg`"] +#[doc = "CMPVUPD (w) register accessor: PWM Comparison 0 Value Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpvupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmpvupd`] +module"] pub type CMPVUPD = crate::Reg; #[doc = "PWM Comparison 0 Value Update Register"] pub mod cmpvupd; -#[doc = "CMPM (rw) register accessor: an alias for `Reg`"] +#[doc = "CMPM (rw) register accessor: PWM Comparison 0 Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpm::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmpm`] +module"] pub type CMPM = crate::Reg; #[doc = "PWM Comparison 0 Mode Register"] pub mod cmpm; -#[doc = "CMPMUPD (w) register accessor: an alias for `Reg`"] +#[doc = "CMPMUPD (w) register accessor: PWM Comparison 0 Mode Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpmupd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmpmupd`] +module"] pub type CMPMUPD = crate::Reg; #[doc = "PWM Comparison 0 Mode Update Register"] pub mod cmpmupd; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpm.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpm.rs index ffc270ed..464d146f 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpm.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpm.rs @@ -1,63 +1,31 @@ #[doc = "Register `CMPM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMPM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CEN` reader - Comparison x Enable"] pub type CEN_R = crate::BitReader; #[doc = "Field `CEN` writer - Comparison x Enable"] -pub type CEN_W<'a, const O: u8> = crate::BitWriter<'a, CMPM_SPEC, O>; +pub type CEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTR` reader - Comparison x Trigger"] pub type CTR_R = crate::FieldReader; #[doc = "Field `CTR` writer - Comparison x Trigger"] -pub type CTR_W<'a, const O: u8> = crate::FieldWriter<'a, CMPM_SPEC, 4, O>; +pub type CTR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CPR` reader - Comparison x Period"] pub type CPR_R = crate::FieldReader; #[doc = "Field `CPR` writer - Comparison x Period"] -pub type CPR_W<'a, const O: u8> = crate::FieldWriter<'a, CMPM_SPEC, 4, O>; +pub type CPR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CPRCNT` reader - Comparison x Period Counter"] pub type CPRCNT_R = crate::FieldReader; #[doc = "Field `CPRCNT` writer - Comparison x Period Counter"] -pub type CPRCNT_W<'a, const O: u8> = crate::FieldWriter<'a, CMPM_SPEC, 4, O>; +pub type CPRCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CUPR` reader - Comparison x Update Period"] pub type CUPR_R = crate::FieldReader; #[doc = "Field `CUPR` writer - Comparison x Update Period"] -pub type CUPR_W<'a, const O: u8> = crate::FieldWriter<'a, CMPM_SPEC, 4, O>; +pub type CUPR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CUPRCNT` reader - Comparison x Update Period Counter"] pub type CUPRCNT_R = crate::FieldReader; #[doc = "Field `CUPRCNT` writer - Comparison x Update Period Counter"] -pub type CUPRCNT_W<'a, const O: u8> = crate::FieldWriter<'a, CMPM_SPEC, 4, O>; +pub type CUPRCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bit 0 - Comparison x Enable"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bit 0 - Comparison x Enable"] #[inline(always)] #[must_use] - pub fn cen(&mut self) -> CEN_W<0> { + pub fn cen(&mut self) -> CEN_W { CEN_W::new(self) } #[doc = "Bits 4:7 - Comparison x Trigger"] #[inline(always)] #[must_use] - pub fn ctr(&mut self) -> CTR_W<4> { + pub fn ctr(&mut self) -> CTR_W { CTR_W::new(self) } #[doc = "Bits 8:11 - Comparison x Period"] #[inline(always)] #[must_use] - pub fn cpr(&mut self) -> CPR_W<8> { + pub fn cpr(&mut self) -> CPR_W { CPR_W::new(self) } #[doc = "Bits 12:15 - Comparison x Period Counter"] #[inline(always)] #[must_use] - pub fn cprcnt(&mut self) -> CPRCNT_W<12> { + pub fn cprcnt(&mut self) -> CPRCNT_W { CPRCNT_W::new(self) } #[doc = "Bits 16:19 - Comparison x Update Period"] #[inline(always)] #[must_use] - pub fn cupr(&mut self) -> CUPR_W<16> { + pub fn cupr(&mut self) -> CUPR_W { CUPR_W::new(self) } #[doc = "Bits 20:23 - Comparison x Update Period Counter"] #[inline(always)] #[must_use] - pub fn cuprcnt(&mut self) -> CUPRCNT_W<20> { + pub fn cuprcnt(&mut self) -> CUPRCNT_W { CUPRCNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Comparison 0 Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmpm](index.html) module"] +#[doc = "PWM Comparison 0 Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMPM_SPEC; impl crate::RegisterSpec for CMPM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmpm::R](R) reader structure"] -impl crate::Readable for CMPM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmpm::W](W) writer structure"] +#[doc = "`read()` method returns [`cmpm::R`](R) reader structure"] +impl crate::Readable for CMPM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmpm::W`](W) writer structure"] impl crate::Writable for CMPM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpmupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpmupd.rs index 243a113f..7f3ee263 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpmupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpmupd.rs @@ -1,72 +1,52 @@ #[doc = "Register `CMPMUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CENUPD` writer - Comparison x Enable Update"] -pub type CENUPD_W<'a, const O: u8> = crate::BitWriter<'a, CMPMUPD_SPEC, O>; +pub type CENUPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTRUPD` writer - Comparison x Trigger Update"] -pub type CTRUPD_W<'a, const O: u8> = crate::FieldWriter<'a, CMPMUPD_SPEC, 4, O>; +pub type CTRUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CPRUPD` writer - Comparison x Period Update"] -pub type CPRUPD_W<'a, const O: u8> = crate::FieldWriter<'a, CMPMUPD_SPEC, 4, O>; +pub type CPRUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `CUPRUPD` writer - Comparison x Update Period Update"] -pub type CUPRUPD_W<'a, const O: u8> = crate::FieldWriter<'a, CMPMUPD_SPEC, 4, O>; +pub type CUPRUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl W { #[doc = "Bit 0 - Comparison x Enable Update"] #[inline(always)] #[must_use] - pub fn cenupd(&mut self) -> CENUPD_W<0> { + pub fn cenupd(&mut self) -> CENUPD_W { CENUPD_W::new(self) } #[doc = "Bits 4:7 - Comparison x Trigger Update"] #[inline(always)] #[must_use] - pub fn ctrupd(&mut self) -> CTRUPD_W<4> { + pub fn ctrupd(&mut self) -> CTRUPD_W { CTRUPD_W::new(self) } #[doc = "Bits 8:11 - Comparison x Period Update"] #[inline(always)] #[must_use] - pub fn cprupd(&mut self) -> CPRUPD_W<8> { + pub fn cprupd(&mut self) -> CPRUPD_W { CPRUPD_W::new(self) } #[doc = "Bits 16:19 - Comparison x Update Period Update"] #[inline(always)] #[must_use] - pub fn cuprupd(&mut self) -> CUPRUPD_W<16> { + pub fn cuprupd(&mut self) -> CUPRUPD_W { CUPRUPD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Comparison 0 Mode Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmpmupd](index.html) module"] +#[doc = "PWM Comparison 0 Mode Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpmupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMPMUPD_SPEC; impl crate::RegisterSpec for CMPMUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmpmupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmpmupd::W`](W) writer structure"] impl crate::Writable for CMPMUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpv.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpv.rs index 944ca6ff..392a2e76 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpv.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpv.rs @@ -1,43 +1,11 @@ #[doc = "Register `CMPV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMPV` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CV` reader - Comparison x Value"] pub type CV_R = crate::FieldReader; #[doc = "Field `CV` writer - Comparison x Value"] -pub type CV_W<'a, const O: u8> = crate::FieldWriter<'a, CMPV_SPEC, 24, O, u32>; +pub type CV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; #[doc = "Field `CVM` reader - Comparison x Value Mode"] pub type CVM_R = crate::BitReader; #[doc = "Comparison x Value Mode\n\nValue on reset: 0"] @@ -63,28 +31,31 @@ impl CVM_R { true => CVMSELECT_A::COMPARE_AT_DECREMENT, } } - #[doc = "Checks if the value of the field is `COMPARE_AT_INCREMENT`"] + #[doc = "Compare when counter is incrementing"] #[inline(always)] pub fn is_compare_at_increment(&self) -> bool { *self == CVMSELECT_A::COMPARE_AT_INCREMENT } - #[doc = "Checks if the value of the field is `COMPARE_AT_DECREMENT`"] + #[doc = "Compare when counter is decrementing"] #[inline(always)] pub fn is_compare_at_decrement(&self) -> bool { *self == CVMSELECT_A::COMPARE_AT_DECREMENT } } #[doc = "Field `CVM` writer - Comparison x Value Mode"] -pub type CVM_W<'a, const O: u8> = crate::BitWriter<'a, CMPV_SPEC, O, CVMSELECT_A>; -impl<'a, const O: u8> CVM_W<'a, O> { +pub type CVM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CVMSELECT_A>; +impl<'a, REG, const O: u8> CVM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Compare when counter is incrementing"] #[inline(always)] - pub fn compare_at_increment(self) -> &'a mut W { + pub fn compare_at_increment(self) -> &'a mut crate::W { self.variant(CVMSELECT_A::COMPARE_AT_INCREMENT) } #[doc = "Compare when counter is decrementing"] #[inline(always)] - pub fn compare_at_decrement(self) -> &'a mut W { + pub fn compare_at_decrement(self) -> &'a mut crate::W { self.variant(CVMSELECT_A::COMPARE_AT_DECREMENT) } } @@ -104,34 +75,31 @@ impl W { #[doc = "Bits 0:23 - Comparison x Value"] #[inline(always)] #[must_use] - pub fn cv(&mut self) -> CV_W<0> { + pub fn cv(&mut self) -> CV_W { CV_W::new(self) } #[doc = "Bit 24 - Comparison x Value Mode"] #[inline(always)] #[must_use] - pub fn cvm(&mut self) -> CVM_W<24> { + pub fn cvm(&mut self) -> CVM_W { CVM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Comparison 0 Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmpv](index.html) module"] +#[doc = "PWM Comparison 0 Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMPV_SPEC; impl crate::RegisterSpec for CMPV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmpv::R](R) reader structure"] -impl crate::Readable for CMPV_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmpv::W](W) writer structure"] +#[doc = "`read()` method returns [`cmpv::R`](R) reader structure"] +impl crate::Readable for CMPV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmpv::W`](W) writer structure"] impl crate::Writable for CMPV_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpvupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpvupd.rs index 565b5458..e7fd1177 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpvupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/pwm_cmp/cmpvupd.rs @@ -1,56 +1,36 @@ #[doc = "Register `CMPVUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CVUPD` writer - Comparison x Value Update"] -pub type CVUPD_W<'a, const O: u8> = crate::FieldWriter<'a, CMPVUPD_SPEC, 24, O, u32>; +pub type CVUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; #[doc = "Field `CVMUPD` writer - Comparison x Value Mode Update"] -pub type CVMUPD_W<'a, const O: u8> = crate::BitWriter<'a, CMPVUPD_SPEC, O>; +pub type CVMUPD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:23 - Comparison x Value Update"] #[inline(always)] #[must_use] - pub fn cvupd(&mut self) -> CVUPD_W<0> { + pub fn cvupd(&mut self) -> CVUPD_W { CVUPD_W::new(self) } #[doc = "Bit 24 - Comparison x Value Mode Update"] #[inline(always)] #[must_use] - pub fn cvmupd(&mut self) -> CVMUPD_W<24> { + pub fn cvmupd(&mut self) -> CVMUPD_W { CVMUPD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Comparison 0 Value Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmpvupd](index.html) module"] +#[doc = "PWM Comparison 0 Value Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpvupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMPVUPD_SPEC; impl crate::RegisterSpec for CMPVUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cmpvupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cmpvupd::W`](W) writer structure"] impl crate::Writable for CMPVUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/scm.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/scm.rs index 95dcbf09..777abc96 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/scm.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/scm.rs @@ -1,55 +1,23 @@ #[doc = "Register `SCM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SYNC0` reader - Synchronous Channel 0"] pub type SYNC0_R = crate::BitReader; #[doc = "Field `SYNC0` writer - Synchronous Channel 0"] -pub type SYNC0_W<'a, const O: u8> = crate::BitWriter<'a, SCM_SPEC, O>; +pub type SYNC0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYNC1` reader - Synchronous Channel 1"] pub type SYNC1_R = crate::BitReader; #[doc = "Field `SYNC1` writer - Synchronous Channel 1"] -pub type SYNC1_W<'a, const O: u8> = crate::BitWriter<'a, SCM_SPEC, O>; +pub type SYNC1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYNC2` reader - Synchronous Channel 2"] pub type SYNC2_R = crate::BitReader; #[doc = "Field `SYNC2` writer - Synchronous Channel 2"] -pub type SYNC2_W<'a, const O: u8> = crate::BitWriter<'a, SCM_SPEC, O>; +pub type SYNC2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYNC3` reader - Synchronous Channel 3"] pub type SYNC3_R = crate::BitReader; #[doc = "Field `SYNC3` writer - Synchronous Channel 3"] -pub type SYNC3_W<'a, const O: u8> = crate::BitWriter<'a, SCM_SPEC, O>; +pub type SYNC3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPDM` reader - Synchronous Channels Update Mode"] pub type UPDM_R = crate::FieldReader; #[doc = "Synchronous Channels Update Mode\n\nValue on reset: 0"] @@ -83,49 +51,53 @@ impl UPDM_R { _ => None, } } - #[doc = "Checks if the value of the field is `MODE0`"] + #[doc = "Manual write of double buffer registers and manual update of synchronous channels"] #[inline(always)] pub fn is_mode0(&self) -> bool { *self == UPDMSELECT_A::MODE0 } - #[doc = "Checks if the value of the field is `MODE1`"] + #[doc = "Manual write of double buffer registers and automatic update of synchronous channels"] #[inline(always)] pub fn is_mode1(&self) -> bool { *self == UPDMSELECT_A::MODE1 } - #[doc = "Checks if the value of the field is `MODE2`"] + #[doc = "Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels"] #[inline(always)] pub fn is_mode2(&self) -> bool { *self == UPDMSELECT_A::MODE2 } } #[doc = "Field `UPDM` writer - Synchronous Channels Update Mode"] -pub type UPDM_W<'a, const O: u8> = crate::FieldWriter<'a, SCM_SPEC, 2, O, UPDMSELECT_A>; -impl<'a, const O: u8> UPDM_W<'a, O> { +pub type UPDM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, UPDMSELECT_A>; +impl<'a, REG, const O: u8> UPDM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Manual write of double buffer registers and manual update of synchronous channels"] #[inline(always)] - pub fn mode0(self) -> &'a mut W { + pub fn mode0(self) -> &'a mut crate::W { self.variant(UPDMSELECT_A::MODE0) } #[doc = "Manual write of double buffer registers and automatic update of synchronous channels"] #[inline(always)] - pub fn mode1(self) -> &'a mut W { + pub fn mode1(self) -> &'a mut crate::W { self.variant(UPDMSELECT_A::MODE1) } #[doc = "Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels"] #[inline(always)] - pub fn mode2(self) -> &'a mut W { + pub fn mode2(self) -> &'a mut crate::W { self.variant(UPDMSELECT_A::MODE2) } } #[doc = "Field `PTRM` reader - DMA Controller Transfer Request Mode"] pub type PTRM_R = crate::BitReader; #[doc = "Field `PTRM` writer - DMA Controller Transfer Request Mode"] -pub type PTRM_W<'a, const O: u8> = crate::BitWriter<'a, SCM_SPEC, O>; +pub type PTRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTRCS` reader - DMA Controller Transfer Request Comparison Selection"] pub type PTRCS_R = crate::FieldReader; #[doc = "Field `PTRCS` writer - DMA Controller Transfer Request Comparison Selection"] -pub type PTRCS_W<'a, const O: u8> = crate::FieldWriter<'a, SCM_SPEC, 3, O>; +pub type PTRCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bit 0 - Synchronous Channel 0"] #[inline(always)] @@ -167,64 +139,61 @@ impl W { #[doc = "Bit 0 - Synchronous Channel 0"] #[inline(always)] #[must_use] - pub fn sync0(&mut self) -> SYNC0_W<0> { + pub fn sync0(&mut self) -> SYNC0_W { SYNC0_W::new(self) } #[doc = "Bit 1 - Synchronous Channel 1"] #[inline(always)] #[must_use] - pub fn sync1(&mut self) -> SYNC1_W<1> { + pub fn sync1(&mut self) -> SYNC1_W { SYNC1_W::new(self) } #[doc = "Bit 2 - Synchronous Channel 2"] #[inline(always)] #[must_use] - pub fn sync2(&mut self) -> SYNC2_W<2> { + pub fn sync2(&mut self) -> SYNC2_W { SYNC2_W::new(self) } #[doc = "Bit 3 - Synchronous Channel 3"] #[inline(always)] #[must_use] - pub fn sync3(&mut self) -> SYNC3_W<3> { + pub fn sync3(&mut self) -> SYNC3_W { SYNC3_W::new(self) } #[doc = "Bits 16:17 - Synchronous Channels Update Mode"] #[inline(always)] #[must_use] - pub fn updm(&mut self) -> UPDM_W<16> { + pub fn updm(&mut self) -> UPDM_W { UPDM_W::new(self) } #[doc = "Bit 20 - DMA Controller Transfer Request Mode"] #[inline(always)] #[must_use] - pub fn ptrm(&mut self) -> PTRM_W<20> { + pub fn ptrm(&mut self) -> PTRM_W { PTRM_W::new(self) } #[doc = "Bits 21:23 - DMA Controller Transfer Request Comparison Selection"] #[inline(always)] #[must_use] - pub fn ptrcs(&mut self) -> PTRCS_W<21> { + pub fn ptrcs(&mut self) -> PTRCS_W { PTRCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Sync Channels Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scm](index.html) module"] +#[doc = "PWM Sync Channels Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scm::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCM_SPEC; impl crate::RegisterSpec for SCM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scm::R](R) reader structure"] -impl crate::Readable for SCM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scm::W](W) writer structure"] +#[doc = "`read()` method returns [`scm::R`](R) reader structure"] +impl crate::Readable for SCM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scm::W`](W) writer structure"] impl crate::Writable for SCM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/scuc.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/scuc.rs index 7d476af5..11d70f57 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/scuc.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/scuc.rs @@ -1,43 +1,11 @@ #[doc = "Register `SCUC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCUC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UPDULOCK` reader - Synchronous Channels Update Unlock"] pub type UPDULOCK_R = crate::BitReader; #[doc = "Field `UPDULOCK` writer - Synchronous Channels Update Unlock"] -pub type UPDULOCK_W<'a, const O: u8> = crate::BitWriter<'a, SCUC_SPEC, O>; +pub type UPDULOCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Synchronous Channels Update Unlock"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bit 0 - Synchronous Channels Update Unlock"] #[inline(always)] #[must_use] - pub fn updulock(&mut self) -> UPDULOCK_W<0> { + pub fn updulock(&mut self) -> UPDULOCK_W { UPDULOCK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Sync Channels Update Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scuc](index.html) module"] +#[doc = "PWM Sync Channels Update Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scuc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scuc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCUC_SPEC; impl crate::RegisterSpec for SCUC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scuc::R](R) reader structure"] -impl crate::Readable for SCUC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scuc::W](W) writer structure"] +#[doc = "`read()` method returns [`scuc::R`](R) reader structure"] +impl crate::Readable for SCUC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scuc::W`](W) writer structure"] impl crate::Writable for SCUC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/scup.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/scup.rs index fdb7e179..1d9692ab 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/scup.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/scup.rs @@ -1,47 +1,15 @@ #[doc = "Register `SCUP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCUP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UPR` reader - Update Period"] pub type UPR_R = crate::FieldReader; #[doc = "Field `UPR` writer - Update Period"] -pub type UPR_W<'a, const O: u8> = crate::FieldWriter<'a, SCUP_SPEC, 4, O>; +pub type UPR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `UPRCNT` reader - Update Period Counter"] pub type UPRCNT_R = crate::FieldReader; #[doc = "Field `UPRCNT` writer - Update Period Counter"] -pub type UPRCNT_W<'a, const O: u8> = crate::FieldWriter<'a, SCUP_SPEC, 4, O>; +pub type UPRCNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Update Period"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:3 - Update Period"] #[inline(always)] #[must_use] - pub fn upr(&mut self) -> UPR_W<0> { + pub fn upr(&mut self) -> UPR_W { UPR_W::new(self) } #[doc = "Bits 4:7 - Update Period Counter"] #[inline(always)] #[must_use] - pub fn uprcnt(&mut self) -> UPRCNT_W<4> { + pub fn uprcnt(&mut self) -> UPRCNT_W { UPRCNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Sync Channels Update Period Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scup](index.html) module"] +#[doc = "PWM Sync Channels Update Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCUP_SPEC; impl crate::RegisterSpec for SCUP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scup::R](R) reader structure"] -impl crate::Readable for SCUP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scup::W](W) writer structure"] +#[doc = "`read()` method returns [`scup::R`](R) reader structure"] +impl crate::Readable for SCUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scup::W`](W) writer structure"] impl crate::Writable for SCUP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/scupupd.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/scupupd.rs index e6a302f7..270343ae 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/scupupd.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/scupupd.rs @@ -1,48 +1,28 @@ #[doc = "Register `SCUPUPD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UPRUPD` writer - Update Period Update"] -pub type UPRUPD_W<'a, const O: u8> = crate::FieldWriter<'a, SCUPUPD_SPEC, 4, O>; +pub type UPRUPD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl W { #[doc = "Bits 0:3 - Update Period Update"] #[inline(always)] #[must_use] - pub fn uprupd(&mut self) -> UPRUPD_W<0> { + pub fn uprupd(&mut self) -> UPRUPD_W { UPRUPD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Sync Channels Update Period Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scupupd](index.html) module"] +#[doc = "PWM Sync Channels Update Period Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scupupd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCUPUPD_SPEC; impl crate::RegisterSpec for SCUPUPD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [scupupd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`scupupd::W`](W) writer structure"] impl crate::Writable for SCUPUPD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/smmr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/smmr.rs index f68615cb..b30a6678 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/smmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/smmr.rs @@ -1,55 +1,23 @@ #[doc = "Register `SMMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SMMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GCEN0` reader - Gray Count ENable"] pub type GCEN0_R = crate::BitReader; #[doc = "Field `GCEN0` writer - Gray Count ENable"] -pub type GCEN0_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O>; +pub type GCEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GCEN1` reader - Gray Count ENable"] pub type GCEN1_R = crate::BitReader; #[doc = "Field `GCEN1` writer - Gray Count ENable"] -pub type GCEN1_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O>; +pub type GCEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOWN0` reader - DOWN Count"] pub type DOWN0_R = crate::BitReader; #[doc = "Field `DOWN0` writer - DOWN Count"] -pub type DOWN0_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O>; +pub type DOWN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOWN1` reader - DOWN Count"] pub type DOWN1_R = crate::BitReader; #[doc = "Field `DOWN1` writer - DOWN Count"] -pub type DOWN1_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O>; +pub type DOWN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Gray Count ENable"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - Gray Count ENable"] #[inline(always)] #[must_use] - pub fn gcen0(&mut self) -> GCEN0_W<0> { + pub fn gcen0(&mut self) -> GCEN0_W { GCEN0_W::new(self) } #[doc = "Bit 1 - Gray Count ENable"] #[inline(always)] #[must_use] - pub fn gcen1(&mut self) -> GCEN1_W<1> { + pub fn gcen1(&mut self) -> GCEN1_W { GCEN1_W::new(self) } #[doc = "Bit 16 - DOWN Count"] #[inline(always)] #[must_use] - pub fn down0(&mut self) -> DOWN0_W<16> { + pub fn down0(&mut self) -> DOWN0_W { DOWN0_W::new(self) } #[doc = "Bit 17 - DOWN Count"] #[inline(always)] #[must_use] - pub fn down1(&mut self) -> DOWN1_W<17> { + pub fn down1(&mut self) -> DOWN1_W { DOWN1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Stepper Motor Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smmr](index.html) module"] +#[doc = "PWM Stepper Motor Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SMMR_SPEC; impl crate::RegisterSpec for SMMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [smmr::R](R) reader structure"] -impl crate::Readable for SMMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [smmr::W](W) writer structure"] +#[doc = "`read()` method returns [`smmr::R`](R) reader structure"] +impl crate::Readable for SMMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smmr::W`](W) writer structure"] impl crate::Writable for SMMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/sr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/sr.rs index 74b97122..f8fd31ab 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CHID0` reader - Channel ID"] pub type CHID0_R = crate::BitReader; #[doc = "Field `CHID1` reader - Channel ID"] @@ -43,15 +30,13 @@ impl R { CHID3_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "PWM Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "PWM Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/sspr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/sspr.rs index 2f8b4964..ee3ae1e3 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/sspr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/sspr.rs @@ -1,47 +1,15 @@ #[doc = "Register `SSPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SSPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPRD` reader - Spread Spectrum Limit Value"] pub type SPRD_R = crate::FieldReader; #[doc = "Field `SPRD` writer - Spread Spectrum Limit Value"] -pub type SPRD_W<'a, const O: u8> = crate::FieldWriter<'a, SSPR_SPEC, 24, O, u32>; +pub type SPRD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; #[doc = "Field `SPRDM` reader - Spread Spectrum Counter Mode"] pub type SPRDM_R = crate::BitReader; #[doc = "Field `SPRDM` writer - Spread Spectrum Counter Mode"] -pub type SPRDM_W<'a, const O: u8> = crate::BitWriter<'a, SSPR_SPEC, O>; +pub type SPRDM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:23 - Spread Spectrum Limit Value"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:23 - Spread Spectrum Limit Value"] #[inline(always)] #[must_use] - pub fn sprd(&mut self) -> SPRD_W<0> { + pub fn sprd(&mut self) -> SPRD_W { SPRD_W::new(self) } #[doc = "Bit 24 - Spread Spectrum Counter Mode"] #[inline(always)] #[must_use] - pub fn sprdm(&mut self) -> SPRDM_W<24> { + pub fn sprdm(&mut self) -> SPRDM_W { SPRDM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Spread Spectrum Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sspr](index.html) module"] +#[doc = "PWM Spread Spectrum Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sspr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPR_SPEC; impl crate::RegisterSpec for SSPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sspr::R](R) reader structure"] -impl crate::Readable for SSPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sspr::W](W) writer structure"] +#[doc = "`read()` method returns [`sspr::R`](R) reader structure"] +impl crate::Readable for SSPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspr::W`](W) writer structure"] impl crate::Writable for SSPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/sspup.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/sspup.rs index cc1aa016..aadf9990 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/sspup.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/sspup.rs @@ -1,48 +1,28 @@ #[doc = "Register `SSPUP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPRDUP` writer - Spread Spectrum Limit Value Update"] -pub type SPRDUP_W<'a, const O: u8> = crate::FieldWriter<'a, SSPUP_SPEC, 24, O, u32>; +pub type SPRDUP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl W { #[doc = "Bits 0:23 - Spread Spectrum Limit Value Update"] #[inline(always)] #[must_use] - pub fn sprdup(&mut self) -> SPRDUP_W<0> { + pub fn sprdup(&mut self) -> SPRDUP_W { SPRDUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Spread Spectrum Update Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sspup](index.html) module"] +#[doc = "PWM Spread Spectrum Update Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sspup::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SSPUP_SPEC; impl crate::RegisterSpec for SSPUP_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [sspup::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`sspup::W`](W) writer structure"] impl crate::Writable for SSPUP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/wpcr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/wpcr.rs index f2a118db..289d5556 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/wpcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/wpcr.rs @@ -1,24 +1,5 @@ #[doc = "Register `WPCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Write Protection Command\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -40,36 +21,40 @@ impl crate::FieldSpec for WPCMDSELECT_AW { type Ux = u8; } #[doc = "Field `WPCMD` writer - Write Protection Command"] -pub type WPCMD_W<'a, const O: u8> = crate::FieldWriter<'a, WPCR_SPEC, 2, O, WPCMDSELECT_AW>; -impl<'a, const O: u8> WPCMD_W<'a, O> { +pub type WPCMD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, WPCMDSELECT_AW>; +impl<'a, REG, const O: u8> WPCMD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Disables the software write protection of the register groups of which the bit WPRGx is at '1'."] #[inline(always)] - pub fn disable_sw_prot(self) -> &'a mut W { + pub fn disable_sw_prot(self) -> &'a mut crate::W { self.variant(WPCMDSELECT_AW::DISABLE_SW_PROT) } #[doc = "Enables the software write protection of the register groups of which the bit WPRGx is at '1'."] #[inline(always)] - pub fn enable_sw_prot(self) -> &'a mut W { + pub fn enable_sw_prot(self) -> &'a mut crate::W { self.variant(WPCMDSELECT_AW::ENABLE_SW_PROT) } #[doc = "Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface."] #[inline(always)] - pub fn enable_hw_prot(self) -> &'a mut W { + pub fn enable_hw_prot(self) -> &'a mut crate::W { self.variant(WPCMDSELECT_AW::ENABLE_HW_PROT) } } #[doc = "Field `WPRG0` writer - Write Protection Register Group 0"] -pub type WPRG0_W<'a, const O: u8> = crate::BitWriter<'a, WPCR_SPEC, O>; +pub type WPRG0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPRG1` writer - Write Protection Register Group 1"] -pub type WPRG1_W<'a, const O: u8> = crate::BitWriter<'a, WPCR_SPEC, O>; +pub type WPRG1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPRG2` writer - Write Protection Register Group 2"] -pub type WPRG2_W<'a, const O: u8> = crate::BitWriter<'a, WPCR_SPEC, O>; +pub type WPRG2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPRG3` writer - Write Protection Register Group 3"] -pub type WPRG3_W<'a, const O: u8> = crate::BitWriter<'a, WPCR_SPEC, O>; +pub type WPRG3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPRG4` writer - Write Protection Register Group 4"] -pub type WPRG4_W<'a, const O: u8> = crate::BitWriter<'a, WPCR_SPEC, O>; +pub type WPRG4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPRG5` writer - Write Protection Register Group 5"] -pub type WPRG5_W<'a, const O: u8> = crate::BitWriter<'a, WPCR_SPEC, O>; +pub type WPRG5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Write Protection Key\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -87,11 +72,15 @@ impl crate::FieldSpec for WPKEYSELECT_AW { type Ux = u32; } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPCR_SPEC, 24, O, WPKEYSELECT_AW>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_AW>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_AW::PASSWD) } } @@ -99,66 +88,65 @@ impl W { #[doc = "Bits 0:1 - Write Protection Command"] #[inline(always)] #[must_use] - pub fn wpcmd(&mut self) -> WPCMD_W<0> { + pub fn wpcmd(&mut self) -> WPCMD_W { WPCMD_W::new(self) } #[doc = "Bit 2 - Write Protection Register Group 0"] #[inline(always)] #[must_use] - pub fn wprg0(&mut self) -> WPRG0_W<2> { + pub fn wprg0(&mut self) -> WPRG0_W { WPRG0_W::new(self) } #[doc = "Bit 3 - Write Protection Register Group 1"] #[inline(always)] #[must_use] - pub fn wprg1(&mut self) -> WPRG1_W<3> { + pub fn wprg1(&mut self) -> WPRG1_W { WPRG1_W::new(self) } #[doc = "Bit 4 - Write Protection Register Group 2"] #[inline(always)] #[must_use] - pub fn wprg2(&mut self) -> WPRG2_W<4> { + pub fn wprg2(&mut self) -> WPRG2_W { WPRG2_W::new(self) } #[doc = "Bit 5 - Write Protection Register Group 3"] #[inline(always)] #[must_use] - pub fn wprg3(&mut self) -> WPRG3_W<5> { + pub fn wprg3(&mut self) -> WPRG3_W { WPRG3_W::new(self) } #[doc = "Bit 6 - Write Protection Register Group 4"] #[inline(always)] #[must_use] - pub fn wprg4(&mut self) -> WPRG4_W<6> { + pub fn wprg4(&mut self) -> WPRG4_W { WPRG4_W::new(self) } #[doc = "Bit 7 - Write Protection Register Group 5"] #[inline(always)] #[must_use] - pub fn wprg5(&mut self) -> WPRG5_W<7> { + pub fn wprg5(&mut self) -> WPRG5_W { WPRG5_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "PWM Write Protection Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpcr](index.html) module"] +#[doc = "PWM Write Protection Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPCR_SPEC; impl crate::RegisterSpec for WPCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [wpcr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`wpcr::W`](W) writer structure"] impl crate::Writable for WPCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/pwm0/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/pwm0/wpsr.rs index e5681f86..2177531d 100644 --- a/arch/cortex-m/samv71q21-pac/src/pwm0/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/pwm0/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPSWS0` reader - Write Protect SW Status"] pub type WPSWS0_R = crate::BitReader; #[doc = "Field `WPSWS1` reader - Write Protect SW Status"] @@ -113,15 +100,13 @@ impl R { WPVSRC_R::new(((self.bits >> 16) & 0xffff) as u16) } } -#[doc = "PWM Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "PWM Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/qspi.rs b/arch/cortex-m/samv71q21-pac/src/qspi.rs index 2c7fa3ee..5d3aeaef 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi.rs @@ -37,67 +37,83 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "RDR (r) register accessor: an alias for `Reg`"] +#[doc = "RDR (r) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rdr`] +module"] pub type RDR = crate::Reg; #[doc = "Receive Data Register"] pub mod rdr; -#[doc = "TDR (w) register accessor: an alias for `Reg`"] +#[doc = "TDR (w) register accessor: Transmit Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tdr`] +module"] pub type TDR = crate::Reg; #[doc = "Transmit Data Register"] pub mod tdr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "SCR (rw) register accessor: an alias for `Reg`"] +#[doc = "SCR (rw) register accessor: Serial Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +module"] pub type SCR = crate::Reg; #[doc = "Serial Clock Register"] pub mod scr; -#[doc = "IAR (rw) register accessor: an alias for `Reg`"] +#[doc = "IAR (rw) register accessor: Instruction Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iar`] +module"] pub type IAR = crate::Reg; #[doc = "Instruction Address Register"] pub mod iar; -#[doc = "ICR (rw) register accessor: an alias for `Reg`"] +#[doc = "ICR (rw) register accessor: Instruction Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`icr`] +module"] pub type ICR = crate::Reg; #[doc = "Instruction Code Register"] pub mod icr; -#[doc = "IFR (rw) register accessor: an alias for `Reg`"] +#[doc = "IFR (rw) register accessor: Instruction Frame Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ifr`] +module"] pub type IFR = crate::Reg; #[doc = "Instruction Frame Register"] pub mod ifr; -#[doc = "SMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SMR (rw) register accessor: Scrambling Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smr`] +module"] pub type SMR = crate::Reg; #[doc = "Scrambling Mode Register"] pub mod smr; -#[doc = "SKR (w) register accessor: an alias for `Reg`"] +#[doc = "SKR (w) register accessor: Scrambling Key Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`skr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`skr`] +module"] pub type SKR = crate::Reg; #[doc = "Scrambling Key Register"] pub mod skr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/cr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/cr.rs index e0c2cb47..e9b66799 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/cr.rs @@ -1,72 +1,52 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `QSPIEN` writer - QSPI Enable"] -pub type QSPIEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type QSPIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `QSPIDIS` writer - QSPI Disable"] -pub type QSPIDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type QSPIDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - QSPI Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LASTXFER` writer - Last Transfer"] -pub type LASTXFER_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type LASTXFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - QSPI Enable"] #[inline(always)] #[must_use] - pub fn qspien(&mut self) -> QSPIEN_W<0> { + pub fn qspien(&mut self) -> QSPIEN_W { QSPIEN_W::new(self) } #[doc = "Bit 1 - QSPI Disable"] #[inline(always)] #[must_use] - pub fn qspidis(&mut self) -> QSPIDIS_W<1> { + pub fn qspidis(&mut self) -> QSPIDIS_W { QSPIDIS_W::new(self) } #[doc = "Bit 7 - QSPI Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<7> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Bit 24 - Last Transfer"] #[inline(always)] #[must_use] - pub fn lastxfer(&mut self) -> LASTXFER_W<24> { + pub fn lastxfer(&mut self) -> LASTXFER_W { LASTXFER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/iar.rs b/arch/cortex-m/samv71q21-pac/src/qspi/iar.rs index aa94cf72..e961db91 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/iar.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/iar.rs @@ -1,43 +1,11 @@ #[doc = "Register `IAR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IAR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ADDR` reader - Address"] pub type ADDR_R = crate::FieldReader; #[doc = "Field `ADDR` writer - Address"] -pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, IAR_SPEC, 32, O, u32>; +pub type ADDR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Address"] #[inline(always)] #[must_use] - pub fn addr(&mut self) -> ADDR_W<0> { + pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Instruction Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iar](index.html) module"] +#[doc = "Instruction Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IAR_SPEC; impl crate::RegisterSpec for IAR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [iar::R](R) reader structure"] -impl crate::Readable for IAR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [iar::W](W) writer structure"] +#[doc = "`read()` method returns [`iar::R`](R) reader structure"] +impl crate::Readable for IAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iar::W`](W) writer structure"] impl crate::Writable for IAR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/icr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/icr.rs index 0f109877..dfa7914c 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/icr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/icr.rs @@ -1,47 +1,15 @@ #[doc = "Register `ICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INST` reader - Instruction Code"] pub type INST_R = crate::FieldReader; #[doc = "Field `INST` writer - Instruction Code"] -pub type INST_W<'a, const O: u8> = crate::FieldWriter<'a, ICR_SPEC, 8, O>; +pub type INST_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `OPT` reader - Option Code"] pub type OPT_R = crate::FieldReader; #[doc = "Field `OPT` writer - Option Code"] -pub type OPT_W<'a, const O: u8> = crate::FieldWriter<'a, ICR_SPEC, 8, O>; +pub type OPT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Instruction Code"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:7 - Instruction Code"] #[inline(always)] #[must_use] - pub fn inst(&mut self) -> INST_W<0> { + pub fn inst(&mut self) -> INST_W { INST_W::new(self) } #[doc = "Bits 16:23 - Option Code"] #[inline(always)] #[must_use] - pub fn opt(&mut self) -> OPT_W<16> { + pub fn opt(&mut self) -> OPT_W { OPT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Instruction Code Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [icr](index.html) module"] +#[doc = "Instruction Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICR_SPEC; impl crate::RegisterSpec for ICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [icr::R](R) reader structure"] -impl crate::Readable for ICR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [icr::W](W) writer structure"] +#[doc = "`read()` method returns [`icr::R`](R) reader structure"] +impl crate::Readable for ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] impl crate::Writable for ICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/idr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/idr.rs index 8293d9ee..69a92e0b 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/idr.rs @@ -1,96 +1,76 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Disable"] -pub type RDRF_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RDRF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDRE` writer - Transmit Data Register Empty Interrupt Disable"] -pub type TDRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TDRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRES` writer - Overrun Error Interrupt Disable"] -pub type OVRES_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type OVRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSR` writer - Chip Select Rise Interrupt Disable"] -pub type CSR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSS` writer - Chip Select Status Interrupt Disable"] -pub type CSS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CSS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INSTRE` writer - Instruction End Interrupt Disable"] -pub type INSTRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type INSTRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Receive Data Register Full Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rdrf(&mut self) -> RDRF_W<0> { + pub fn rdrf(&mut self) -> RDRF_W { RDRF_W::new(self) } #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Disable"] #[inline(always)] #[must_use] - pub fn tdre(&mut self) -> TDRE_W<1> { + pub fn tdre(&mut self) -> TDRE_W { TDRE_W::new(self) } #[doc = "Bit 2 - Transmission Registers Empty Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<2> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 3 - Overrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ovres(&mut self) -> OVRES_W<3> { + pub fn ovres(&mut self) -> OVRES_W { OVRES_W::new(self) } #[doc = "Bit 8 - Chip Select Rise Interrupt Disable"] #[inline(always)] #[must_use] - pub fn csr(&mut self) -> CSR_W<8> { + pub fn csr(&mut self) -> CSR_W { CSR_W::new(self) } #[doc = "Bit 9 - Chip Select Status Interrupt Disable"] #[inline(always)] #[must_use] - pub fn css(&mut self) -> CSS_W<9> { + pub fn css(&mut self) -> CSS_W { CSS_W::new(self) } #[doc = "Bit 10 - Instruction End Interrupt Disable"] #[inline(always)] #[must_use] - pub fn instre(&mut self) -> INSTRE_W<10> { + pub fn instre(&mut self) -> INSTRE_W { INSTRE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/ier.rs b/arch/cortex-m/samv71q21-pac/src/qspi/ier.rs index 4241d5b6..d36bb39f 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/ier.rs @@ -1,96 +1,76 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Enable"] -pub type RDRF_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RDRF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDRE` writer - Transmit Data Register Empty Interrupt Enable"] -pub type TDRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TDRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRES` writer - Overrun Error Interrupt Enable"] -pub type OVRES_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type OVRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSR` writer - Chip Select Rise Interrupt Enable"] -pub type CSR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSS` writer - Chip Select Status Interrupt Enable"] -pub type CSS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CSS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INSTRE` writer - Instruction End Interrupt Enable"] -pub type INSTRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type INSTRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rdrf(&mut self) -> RDRF_W<0> { + pub fn rdrf(&mut self) -> RDRF_W { RDRF_W::new(self) } #[doc = "Bit 1 - Transmit Data Register Empty Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tdre(&mut self) -> TDRE_W<1> { + pub fn tdre(&mut self) -> TDRE_W { TDRE_W::new(self) } #[doc = "Bit 2 - Transmission Registers Empty Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<2> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 3 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovres(&mut self) -> OVRES_W<3> { + pub fn ovres(&mut self) -> OVRES_W { OVRES_W::new(self) } #[doc = "Bit 8 - Chip Select Rise Interrupt Enable"] #[inline(always)] #[must_use] - pub fn csr(&mut self) -> CSR_W<8> { + pub fn csr(&mut self) -> CSR_W { CSR_W::new(self) } #[doc = "Bit 9 - Chip Select Status Interrupt Enable"] #[inline(always)] #[must_use] - pub fn css(&mut self) -> CSS_W<9> { + pub fn css(&mut self) -> CSS_W { CSS_W::new(self) } #[doc = "Bit 10 - Instruction End Interrupt Enable"] #[inline(always)] #[must_use] - pub fn instre(&mut self) -> INSTRE_W<10> { + pub fn instre(&mut self) -> INSTRE_W { INSTRE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/ifr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/ifr.rs index 8f9b41b8..1ceafcfc 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/ifr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/ifr.rs @@ -1,39 +1,7 @@ #[doc = "Register `IFR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IFR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WIDTH` reader - Width of Instruction Code, Address, Option Code and Data"] pub type WIDTH_R = crate::FieldReader; #[doc = "Width of Instruction Code, Address, Option Code and Data\n\nValue on reset: 0"] @@ -79,97 +47,101 @@ impl WIDTH_R { _ => None, } } - #[doc = "Checks if the value of the field is `SINGLE_BIT_SPI`"] + #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI"] #[inline(always)] pub fn is_single_bit_spi(&self) -> bool { *self == WIDTHSELECT_A::SINGLE_BIT_SPI } - #[doc = "Checks if the value of the field is `DUAL_OUTPUT`"] + #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI"] #[inline(always)] pub fn is_dual_output(&self) -> bool { *self == WIDTHSELECT_A::DUAL_OUTPUT } - #[doc = "Checks if the value of the field is `QUAD_OUTPUT`"] + #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI"] #[inline(always)] pub fn is_quad_output(&self) -> bool { *self == WIDTHSELECT_A::QUAD_OUTPUT } - #[doc = "Checks if the value of the field is `DUAL_IO`"] + #[doc = "Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI"] #[inline(always)] pub fn is_dual_io(&self) -> bool { *self == WIDTHSELECT_A::DUAL_IO } - #[doc = "Checks if the value of the field is `QUAD_IO`"] + #[doc = "Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI"] #[inline(always)] pub fn is_quad_io(&self) -> bool { *self == WIDTHSELECT_A::QUAD_IO } - #[doc = "Checks if the value of the field is `DUAL_CMD`"] + #[doc = "Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI"] #[inline(always)] pub fn is_dual_cmd(&self) -> bool { *self == WIDTHSELECT_A::DUAL_CMD } - #[doc = "Checks if the value of the field is `QUAD_CMD`"] + #[doc = "Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI"] #[inline(always)] pub fn is_quad_cmd(&self) -> bool { *self == WIDTHSELECT_A::QUAD_CMD } } #[doc = "Field `WIDTH` writer - Width of Instruction Code, Address, Option Code and Data"] -pub type WIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, IFR_SPEC, 3, O, WIDTHSELECT_A>; -impl<'a, const O: u8> WIDTH_W<'a, O> { +pub type WIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, WIDTHSELECT_A>; +impl<'a, REG, const O: u8> WIDTH_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI"] #[inline(always)] - pub fn single_bit_spi(self) -> &'a mut W { + pub fn single_bit_spi(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::SINGLE_BIT_SPI) } #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI"] #[inline(always)] - pub fn dual_output(self) -> &'a mut W { + pub fn dual_output(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::DUAL_OUTPUT) } #[doc = "Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI"] #[inline(always)] - pub fn quad_output(self) -> &'a mut W { + pub fn quad_output(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::QUAD_OUTPUT) } #[doc = "Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI"] #[inline(always)] - pub fn dual_io(self) -> &'a mut W { + pub fn dual_io(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::DUAL_IO) } #[doc = "Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI"] #[inline(always)] - pub fn quad_io(self) -> &'a mut W { + pub fn quad_io(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::QUAD_IO) } #[doc = "Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI"] #[inline(always)] - pub fn dual_cmd(self) -> &'a mut W { + pub fn dual_cmd(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::DUAL_CMD) } #[doc = "Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI"] #[inline(always)] - pub fn quad_cmd(self) -> &'a mut W { + pub fn quad_cmd(self) -> &'a mut crate::W { self.variant(WIDTHSELECT_A::QUAD_CMD) } } #[doc = "Field `INSTEN` reader - Instruction Enable"] pub type INSTEN_R = crate::BitReader; #[doc = "Field `INSTEN` writer - Instruction Enable"] -pub type INSTEN_W<'a, const O: u8> = crate::BitWriter<'a, IFR_SPEC, O>; +pub type INSTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ADDREN` reader - Address Enable"] pub type ADDREN_R = crate::BitReader; #[doc = "Field `ADDREN` writer - Address Enable"] -pub type ADDREN_W<'a, const O: u8> = crate::BitWriter<'a, IFR_SPEC, O>; +pub type ADDREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OPTEN` reader - Option Enable"] pub type OPTEN_R = crate::BitReader; #[doc = "Field `OPTEN` writer - Option Enable"] -pub type OPTEN_W<'a, const O: u8> = crate::BitWriter<'a, IFR_SPEC, O>; +pub type OPTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAEN` reader - Data Enable"] pub type DATAEN_R = crate::BitReader; #[doc = "Field `DATAEN` writer - Data Enable"] -pub type DATAEN_W<'a, const O: u8> = crate::BitWriter<'a, IFR_SPEC, O>; +pub type DATAEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OPTL` reader - Option Code Length"] pub type OPTL_R = crate::FieldReader; #[doc = "Option Code Length\n\nValue on reset: 0"] @@ -206,48 +178,52 @@ impl OPTL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `OPTION_1BIT`"] + #[doc = "The option code is 1 bit long."] #[inline(always)] pub fn is_option_1bit(&self) -> bool { *self == OPTLSELECT_A::OPTION_1BIT } - #[doc = "Checks if the value of the field is `OPTION_2BIT`"] + #[doc = "The option code is 2 bits long."] #[inline(always)] pub fn is_option_2bit(&self) -> bool { *self == OPTLSELECT_A::OPTION_2BIT } - #[doc = "Checks if the value of the field is `OPTION_4BIT`"] + #[doc = "The option code is 4 bits long."] #[inline(always)] pub fn is_option_4bit(&self) -> bool { *self == OPTLSELECT_A::OPTION_4BIT } - #[doc = "Checks if the value of the field is `OPTION_8BIT`"] + #[doc = "The option code is 8 bits long."] #[inline(always)] pub fn is_option_8bit(&self) -> bool { *self == OPTLSELECT_A::OPTION_8BIT } } #[doc = "Field `OPTL` writer - Option Code Length"] -pub type OPTL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, IFR_SPEC, 2, O, OPTLSELECT_A>; -impl<'a, const O: u8> OPTL_W<'a, O> { +pub type OPTL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, OPTLSELECT_A>; +impl<'a, REG, const O: u8> OPTL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The option code is 1 bit long."] #[inline(always)] - pub fn option_1bit(self) -> &'a mut W { + pub fn option_1bit(self) -> &'a mut crate::W { self.variant(OPTLSELECT_A::OPTION_1BIT) } #[doc = "The option code is 2 bits long."] #[inline(always)] - pub fn option_2bit(self) -> &'a mut W { + pub fn option_2bit(self) -> &'a mut crate::W { self.variant(OPTLSELECT_A::OPTION_2BIT) } #[doc = "The option code is 4 bits long."] #[inline(always)] - pub fn option_4bit(self) -> &'a mut W { + pub fn option_4bit(self) -> &'a mut crate::W { self.variant(OPTLSELECT_A::OPTION_4BIT) } #[doc = "The option code is 8 bits long."] #[inline(always)] - pub fn option_8bit(self) -> &'a mut W { + pub fn option_8bit(self) -> &'a mut crate::W { self.variant(OPTLSELECT_A::OPTION_8BIT) } } @@ -276,28 +252,31 @@ impl ADDRL_R { true => ADDRLSELECT_A::_32_BIT, } } - #[doc = "Checks if the value of the field is `_24_BIT`"] + #[doc = "The address is 24 bits long."] #[inline(always)] pub fn is_24_bit(&self) -> bool { *self == ADDRLSELECT_A::_24_BIT } - #[doc = "Checks if the value of the field is `_32_BIT`"] + #[doc = "The address is 32 bits long."] #[inline(always)] pub fn is_32_bit(&self) -> bool { *self == ADDRLSELECT_A::_32_BIT } } #[doc = "Field `ADDRL` writer - Address Length"] -pub type ADDRL_W<'a, const O: u8> = crate::BitWriter<'a, IFR_SPEC, O, ADDRLSELECT_A>; -impl<'a, const O: u8> ADDRL_W<'a, O> { +pub type ADDRL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ADDRLSELECT_A>; +impl<'a, REG, const O: u8> ADDRL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The address is 24 bits long."] #[inline(always)] - pub fn _24_bit(self) -> &'a mut W { + pub fn _24_bit(self) -> &'a mut crate::W { self.variant(ADDRLSELECT_A::_24_BIT) } #[doc = "The address is 32 bits long."] #[inline(always)] - pub fn _32_bit(self) -> &'a mut W { + pub fn _32_bit(self) -> &'a mut crate::W { self.variant(ADDRLSELECT_A::_32_BIT) } } @@ -337,48 +316,52 @@ impl TFRTYP_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TRSFR_READ`"] + #[doc = "Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible."] #[inline(always)] pub fn is_trsfr_read(&self) -> bool { *self == TFRTYPSELECT_A::TRSFR_READ } - #[doc = "Checks if the value of the field is `TRSFR_READ_MEMORY`"] + #[doc = "Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible."] #[inline(always)] pub fn is_trsfr_read_memory(&self) -> bool { *self == TFRTYPSELECT_A::TRSFR_READ_MEMORY } - #[doc = "Checks if the value of the field is `TRSFR_WRITE`"] + #[doc = "Write transfer into the serial memory.Scrambling is not performed."] #[inline(always)] pub fn is_trsfr_write(&self) -> bool { *self == TFRTYPSELECT_A::TRSFR_WRITE } - #[doc = "Checks if the value of the field is `TRSFR_WRITE_MEMORY`"] + #[doc = "Write data transfer into the serial memory.If enabled, scrambling is performed."] #[inline(always)] pub fn is_trsfr_write_memory(&self) -> bool { *self == TFRTYPSELECT_A::TRSFR_WRITE_MEMORY } } #[doc = "Field `TFRTYP` writer - Data Transfer Type"] -pub type TFRTYP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, IFR_SPEC, 2, O, TFRTYPSELECT_A>; -impl<'a, const O: u8> TFRTYP_W<'a, O> { +pub type TFRTYP_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TFRTYPSELECT_A>; +impl<'a, REG, const O: u8> TFRTYP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible."] #[inline(always)] - pub fn trsfr_read(self) -> &'a mut W { + pub fn trsfr_read(self) -> &'a mut crate::W { self.variant(TFRTYPSELECT_A::TRSFR_READ) } #[doc = "Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible."] #[inline(always)] - pub fn trsfr_read_memory(self) -> &'a mut W { + pub fn trsfr_read_memory(self) -> &'a mut crate::W { self.variant(TFRTYPSELECT_A::TRSFR_READ_MEMORY) } #[doc = "Write transfer into the serial memory.Scrambling is not performed."] #[inline(always)] - pub fn trsfr_write(self) -> &'a mut W { + pub fn trsfr_write(self) -> &'a mut crate::W { self.variant(TFRTYPSELECT_A::TRSFR_WRITE) } #[doc = "Write data transfer into the serial memory.If enabled, scrambling is performed."] #[inline(always)] - pub fn trsfr_write_memory(self) -> &'a mut W { + pub fn trsfr_write_memory(self) -> &'a mut crate::W { self.variant(TFRTYPSELECT_A::TRSFR_WRITE_MEMORY) } } @@ -407,35 +390,38 @@ impl CRM_R { true => CRMSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "The Continuous Read mode is disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == CRMSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "The Continuous Read mode is enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == CRMSELECT_A::ENABLED } } #[doc = "Field `CRM` writer - Continuous Read Mode"] -pub type CRM_W<'a, const O: u8> = crate::BitWriter<'a, IFR_SPEC, O, CRMSELECT_A>; -impl<'a, const O: u8> CRM_W<'a, O> { +pub type CRM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CRMSELECT_A>; +impl<'a, REG, const O: u8> CRM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The Continuous Read mode is disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(CRMSELECT_A::DISABLED) } #[doc = "The Continuous Read mode is enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(CRMSELECT_A::ENABLED) } } #[doc = "Field `NBDUM` reader - Number Of Dummy Cycles"] pub type NBDUM_R = crate::FieldReader; #[doc = "Field `NBDUM` writer - Number Of Dummy Cycles"] -pub type NBDUM_W<'a, const O: u8> = crate::FieldWriter<'a, IFR_SPEC, 5, O>; +pub type NBDUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; impl R { #[doc = "Bits 0:2 - Width of Instruction Code, Address, Option Code and Data"] #[inline(always)] @@ -492,82 +478,79 @@ impl W { #[doc = "Bits 0:2 - Width of Instruction Code, Address, Option Code and Data"] #[inline(always)] #[must_use] - pub fn width(&mut self) -> WIDTH_W<0> { + pub fn width(&mut self) -> WIDTH_W { WIDTH_W::new(self) } #[doc = "Bit 4 - Instruction Enable"] #[inline(always)] #[must_use] - pub fn insten(&mut self) -> INSTEN_W<4> { + pub fn insten(&mut self) -> INSTEN_W { INSTEN_W::new(self) } #[doc = "Bit 5 - Address Enable"] #[inline(always)] #[must_use] - pub fn addren(&mut self) -> ADDREN_W<5> { + pub fn addren(&mut self) -> ADDREN_W { ADDREN_W::new(self) } #[doc = "Bit 6 - Option Enable"] #[inline(always)] #[must_use] - pub fn opten(&mut self) -> OPTEN_W<6> { + pub fn opten(&mut self) -> OPTEN_W { OPTEN_W::new(self) } #[doc = "Bit 7 - Data Enable"] #[inline(always)] #[must_use] - pub fn dataen(&mut self) -> DATAEN_W<7> { + pub fn dataen(&mut self) -> DATAEN_W { DATAEN_W::new(self) } #[doc = "Bits 8:9 - Option Code Length"] #[inline(always)] #[must_use] - pub fn optl(&mut self) -> OPTL_W<8> { + pub fn optl(&mut self) -> OPTL_W { OPTL_W::new(self) } #[doc = "Bit 10 - Address Length"] #[inline(always)] #[must_use] - pub fn addrl(&mut self) -> ADDRL_W<10> { + pub fn addrl(&mut self) -> ADDRL_W { ADDRL_W::new(self) } #[doc = "Bits 12:13 - Data Transfer Type"] #[inline(always)] #[must_use] - pub fn tfrtyp(&mut self) -> TFRTYP_W<12> { + pub fn tfrtyp(&mut self) -> TFRTYP_W { TFRTYP_W::new(self) } #[doc = "Bit 14 - Continuous Read Mode"] #[inline(always)] #[must_use] - pub fn crm(&mut self) -> CRM_W<14> { + pub fn crm(&mut self) -> CRM_W { CRM_W::new(self) } #[doc = "Bits 16:20 - Number Of Dummy Cycles"] #[inline(always)] #[must_use] - pub fn nbdum(&mut self) -> NBDUM_W<16> { + pub fn nbdum(&mut self) -> NBDUM_W { NBDUM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Instruction Frame Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifr](index.html) module"] +#[doc = "Instruction Frame Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IFR_SPEC; impl crate::RegisterSpec for IFR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ifr::R](R) reader structure"] -impl crate::Readable for IFR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ifr::W](W) writer structure"] +#[doc = "`read()` method returns [`ifr::R`](R) reader structure"] +impl crate::Readable for IFR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ifr::W`](W) writer structure"] impl crate::Writable for IFR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/imr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/imr.rs index a34e9fde..67f3bda7 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDRF` reader - Receive Data Register Full Interrupt Mask"] pub type RDRF_R = crate::BitReader; #[doc = "Field `TDRE` reader - Transmit Data Register Empty Interrupt Mask"] @@ -64,15 +51,13 @@ impl R { INSTRE_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/mr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/mr.rs index b6c1ec26..370f8dc1 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMM` reader - Serial Memory Mode"] pub type SMM_R = crate::BitReader; #[doc = "Serial Memory Mode\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl SMM_R { true => SMMSELECT_A::MEMORY, } } - #[doc = "Checks if the value of the field is `SPI`"] + #[doc = "The QSPI is in SPI mode."] #[inline(always)] pub fn is_spi(&self) -> bool { *self == SMMSELECT_A::SPI } - #[doc = "Checks if the value of the field is `MEMORY`"] + #[doc = "The QSPI is in Serial Memory mode."] #[inline(always)] pub fn is_memory(&self) -> bool { *self == SMMSELECT_A::MEMORY } } #[doc = "Field `SMM` writer - Serial Memory Mode"] -pub type SMM_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, SMMSELECT_A>; -impl<'a, const O: u8> SMM_W<'a, O> { +pub type SMM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SMMSELECT_A>; +impl<'a, REG, const O: u8> SMM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The QSPI is in SPI mode."] #[inline(always)] - pub fn spi(self) -> &'a mut W { + pub fn spi(self) -> &'a mut crate::W { self.variant(SMMSELECT_A::SPI) } #[doc = "The QSPI is in Serial Memory mode."] #[inline(always)] - pub fn memory(self) -> &'a mut W { + pub fn memory(self) -> &'a mut crate::W { self.variant(SMMSELECT_A::MEMORY) } } @@ -109,28 +80,31 @@ impl LLB_R { true => LLBSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Local loopback path disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == LLBSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "Local loopback path enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == LLBSELECT_A::ENABLED } } #[doc = "Field `LLB` writer - Local Loopback Enable"] -pub type LLB_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, LLBSELECT_A>; -impl<'a, const O: u8> LLB_W<'a, O> { +pub type LLB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LLBSELECT_A>; +impl<'a, REG, const O: u8> LLB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Local loopback path disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(LLBSELECT_A::DISABLED) } #[doc = "Local loopback path enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(LLBSELECT_A::ENABLED) } } @@ -159,28 +133,31 @@ impl WDRBT_R { true => WDRBTSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == WDRBTSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == WDRBTSELECT_A::ENABLED } } #[doc = "Field `WDRBT` writer - Wait Data Read Before Transfer"] -pub type WDRBT_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, WDRBTSELECT_A>; -impl<'a, const O: u8> WDRBT_W<'a, O> { +pub type WDRBT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WDRBTSELECT_A>; +impl<'a, REG, const O: u8> WDRBT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(WDRBTSELECT_A::DISABLED) } #[doc = "In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(WDRBTSELECT_A::ENABLED) } } @@ -217,38 +194,42 @@ impl CSMODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `NOT_RELOADED`"] + #[doc = "The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer."] #[inline(always)] pub fn is_not_reloaded(&self) -> bool { *self == CSMODESELECT_A::NOT_RELOADED } - #[doc = "Checks if the value of the field is `LASTXFER`"] + #[doc = "The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred."] #[inline(always)] pub fn is_lastxfer(&self) -> bool { *self == CSMODESELECT_A::LASTXFER } - #[doc = "Checks if the value of the field is `SYSTEMATICALLY`"] + #[doc = "The chip select is deasserted systematically after each transfer."] #[inline(always)] pub fn is_systematically(&self) -> bool { *self == CSMODESELECT_A::SYSTEMATICALLY } } #[doc = "Field `CSMODE` writer - Chip Select Mode"] -pub type CSMODE_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 2, O, CSMODESELECT_A>; -impl<'a, const O: u8> CSMODE_W<'a, O> { +pub type CSMODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CSMODESELECT_A>; +impl<'a, REG, const O: u8> CSMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer."] #[inline(always)] - pub fn not_reloaded(self) -> &'a mut W { + pub fn not_reloaded(self) -> &'a mut crate::W { self.variant(CSMODESELECT_A::NOT_RELOADED) } #[doc = "The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred."] #[inline(always)] - pub fn lastxfer(self) -> &'a mut W { + pub fn lastxfer(self) -> &'a mut crate::W { self.variant(CSMODESELECT_A::LASTXFER) } #[doc = "The chip select is deasserted systematically after each transfer."] #[inline(always)] - pub fn systematically(self) -> &'a mut W { + pub fn systematically(self) -> &'a mut crate::W { self.variant(CSMODESELECT_A::SYSTEMATICALLY) } } @@ -282,39 +263,43 @@ impl NBBITS_R { _ => None, } } - #[doc = "Checks if the value of the field is `_8_BIT`"] + #[doc = "8 bits for transfer"] #[inline(always)] pub fn is_8_bit(&self) -> bool { *self == NBBITSSELECT_A::_8_BIT } - #[doc = "Checks if the value of the field is `_16_BIT`"] + #[doc = "16 bits for transfer"] #[inline(always)] pub fn is_16_bit(&self) -> bool { *self == NBBITSSELECT_A::_16_BIT } } #[doc = "Field `NBBITS` writer - Number Of Bits Per Transfer"] -pub type NBBITS_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O, NBBITSSELECT_A>; -impl<'a, const O: u8> NBBITS_W<'a, O> { +pub type NBBITS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, NBBITSSELECT_A>; +impl<'a, REG, const O: u8> NBBITS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8 bits for transfer"] #[inline(always)] - pub fn _8_bit(self) -> &'a mut W { + pub fn _8_bit(self) -> &'a mut crate::W { self.variant(NBBITSSELECT_A::_8_BIT) } #[doc = "16 bits for transfer"] #[inline(always)] - pub fn _16_bit(self) -> &'a mut W { + pub fn _16_bit(self) -> &'a mut crate::W { self.variant(NBBITSSELECT_A::_16_BIT) } } #[doc = "Field `DLYBCT` reader - Delay Between Consecutive Transfers"] pub type DLYBCT_R = crate::FieldReader; #[doc = "Field `DLYBCT` writer - Delay Between Consecutive Transfers"] -pub type DLYBCT_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O>; +pub type DLYBCT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DLYCS` reader - Minimum Inactive QCS Delay"] pub type DLYCS_R = crate::FieldReader; #[doc = "Field `DLYCS` writer - Minimum Inactive QCS Delay"] -pub type DLYCS_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O>; +pub type DLYCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 0 - Serial Memory Mode"] #[inline(always)] @@ -356,64 +341,61 @@ impl W { #[doc = "Bit 0 - Serial Memory Mode"] #[inline(always)] #[must_use] - pub fn smm(&mut self) -> SMM_W<0> { + pub fn smm(&mut self) -> SMM_W { SMM_W::new(self) } #[doc = "Bit 1 - Local Loopback Enable"] #[inline(always)] #[must_use] - pub fn llb(&mut self) -> LLB_W<1> { + pub fn llb(&mut self) -> LLB_W { LLB_W::new(self) } #[doc = "Bit 2 - Wait Data Read Before Transfer"] #[inline(always)] #[must_use] - pub fn wdrbt(&mut self) -> WDRBT_W<2> { + pub fn wdrbt(&mut self) -> WDRBT_W { WDRBT_W::new(self) } #[doc = "Bits 4:5 - Chip Select Mode"] #[inline(always)] #[must_use] - pub fn csmode(&mut self) -> CSMODE_W<4> { + pub fn csmode(&mut self) -> CSMODE_W { CSMODE_W::new(self) } #[doc = "Bits 8:11 - Number Of Bits Per Transfer"] #[inline(always)] #[must_use] - pub fn nbbits(&mut self) -> NBBITS_W<8> { + pub fn nbbits(&mut self) -> NBBITS_W { NBBITS_W::new(self) } #[doc = "Bits 16:23 - Delay Between Consecutive Transfers"] #[inline(always)] #[must_use] - pub fn dlybct(&mut self) -> DLYBCT_W<16> { + pub fn dlybct(&mut self) -> DLYBCT_W { DLYBCT_W::new(self) } #[doc = "Bits 24:31 - Minimum Inactive QCS Delay"] #[inline(always)] #[must_use] - pub fn dlycs(&mut self) -> DLYCS_W<24> { + pub fn dlycs(&mut self) -> DLYCS_W { DLYCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/rdr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/rdr.rs index ef40e3a7..ec6fdf8e 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/rdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/rdr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RD` reader - Receive Data"] pub type RD_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RD_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Receive Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdr](index.html) module"] +#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RDR_SPEC; impl crate::RegisterSpec for RDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rdr::R](R) reader structure"] -impl crate::Readable for RDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rdr::R`](R) reader structure"] +impl crate::Readable for RDR_SPEC {} #[doc = "`reset()` method sets RDR to value 0"] impl crate::Resettable for RDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/scr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/scr.rs index 3d697be9..ee3df862 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/scr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/scr.rs @@ -1,55 +1,23 @@ #[doc = "Register `SCR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPOL` reader - Clock Polarity"] pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - Clock Polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPHA` reader - Clock Phase"] pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - Clock Phase"] -pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type CPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCBR` reader - Serial Clock Baud Rate"] pub type SCBR_R = crate::FieldReader; #[doc = "Field `SCBR` writer - Serial Clock Baud Rate"] -pub type SCBR_W<'a, const O: u8> = crate::FieldWriter<'a, SCR_SPEC, 8, O>; +pub type SCBR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DLYBS` reader - Delay Before QSCK"] pub type DLYBS_R = crate::FieldReader; #[doc = "Field `DLYBS` writer - Delay Before QSCK"] -pub type DLYBS_W<'a, const O: u8> = crate::FieldWriter<'a, SCR_SPEC, 8, O>; +pub type DLYBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 0 - Clock Polarity"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - Clock Polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<0> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bit 1 - Clock Phase"] #[inline(always)] #[must_use] - pub fn cpha(&mut self) -> CPHA_W<1> { + pub fn cpha(&mut self) -> CPHA_W { CPHA_W::new(self) } #[doc = "Bits 8:15 - Serial Clock Baud Rate"] #[inline(always)] #[must_use] - pub fn scbr(&mut self) -> SCBR_W<8> { + pub fn scbr(&mut self) -> SCBR_W { SCBR_W::new(self) } #[doc = "Bits 16:23 - Delay Before QSCK"] #[inline(always)] #[must_use] - pub fn dlybs(&mut self) -> DLYBS_W<16> { + pub fn dlybs(&mut self) -> DLYBS_W { DLYBS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Serial Clock Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +#[doc = "Serial Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCR_SPEC; impl crate::RegisterSpec for SCR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [scr::R](R) reader structure"] -impl crate::Readable for SCR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +#[doc = "`read()` method returns [`scr::R`](R) reader structure"] +impl crate::Readable for SCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] impl crate::Writable for SCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/skr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/skr.rs index edf2c5a3..56a361ba 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/skr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/skr.rs @@ -1,48 +1,28 @@ #[doc = "Register `SKR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USRK` writer - User Scrambling Key"] -pub type USRK_W<'a, const O: u8> = crate::FieldWriter<'a, SKR_SPEC, 32, O, u32>; +pub type USRK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - User Scrambling Key"] #[inline(always)] #[must_use] - pub fn usrk(&mut self) -> USRK_W<0> { + pub fn usrk(&mut self) -> USRK_W { USRK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Scrambling Key Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [skr](index.html) module"] +#[doc = "Scrambling Key Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`skr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SKR_SPEC; impl crate::RegisterSpec for SKR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [skr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`skr::W`](W) writer structure"] impl crate::Writable for SKR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/smr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/smr.rs index f3d8bf74..ff36ec6c 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/smr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/smr.rs @@ -1,39 +1,7 @@ #[doc = "Register `SMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SCREN` reader - Scrambling/Unscrambling Enable"] pub type SCREN_R = crate::BitReader; #[doc = "Scrambling/Unscrambling Enable\n\nValue on reset: 0"] @@ -59,35 +27,38 @@ impl SCREN_R { true => SCRENSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "The scrambling/unscrambling is disabled."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == SCRENSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "The scrambling/unscrambling is enabled."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == SCRENSELECT_A::ENABLED } } #[doc = "Field `SCREN` writer - Scrambling/Unscrambling Enable"] -pub type SCREN_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O, SCRENSELECT_A>; -impl<'a, const O: u8> SCREN_W<'a, O> { +pub type SCREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SCRENSELECT_A>; +impl<'a, REG, const O: u8> SCREN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The scrambling/unscrambling is disabled."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(SCRENSELECT_A::DISABLED) } #[doc = "The scrambling/unscrambling is enabled."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(SCRENSELECT_A::ENABLED) } } #[doc = "Field `RVDIS` reader - Scrambling/Unscrambling Random Value Disable"] pub type RVDIS_R = crate::BitReader; #[doc = "Field `RVDIS` writer - Scrambling/Unscrambling Random Value Disable"] -pub type RVDIS_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type RVDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Scrambling/Unscrambling Enable"] #[inline(always)] @@ -104,34 +75,31 @@ impl W { #[doc = "Bit 0 - Scrambling/Unscrambling Enable"] #[inline(always)] #[must_use] - pub fn scren(&mut self) -> SCREN_W<0> { + pub fn scren(&mut self) -> SCREN_W { SCREN_W::new(self) } #[doc = "Bit 1 - Scrambling/Unscrambling Random Value Disable"] #[inline(always)] #[must_use] - pub fn rvdis(&mut self) -> RVDIS_W<1> { + pub fn rvdis(&mut self) -> RVDIS_W { RVDIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Scrambling Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smr](index.html) module"] +#[doc = "Scrambling Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SMR_SPEC; impl crate::RegisterSpec for SMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [smr::R](R) reader structure"] -impl crate::Readable for SMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [smr::W](W) writer structure"] +#[doc = "`read()` method returns [`smr::R`](R) reader structure"] +impl crate::Readable for SMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smr::W`](W) writer structure"] impl crate::Writable for SMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/sr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/sr.rs index 76d633a6..f0e99e5b 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDRF` reader - Receive Data Register Full (cleared by reading SPI_RDR)"] pub type RDRF_R = crate::BitReader; #[doc = "Field `TDRE` reader - Transmit Data Register Empty (cleared by writing SPI_TDR)"] @@ -71,15 +58,13 @@ impl R { QSPIENS_R::new(((self.bits >> 24) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/tdr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/tdr.rs index 114ddb0d..4f3b8042 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/tdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/tdr.rs @@ -1,48 +1,28 @@ #[doc = "Register `TDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TD` writer - Transmit Data"] -pub type TD_W<'a, const O: u8> = crate::FieldWriter<'a, TDR_SPEC, 16, O, u16>; +pub type TD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl W { #[doc = "Bits 0:15 - Transmit Data"] #[inline(always)] #[must_use] - pub fn td(&mut self) -> TD_W<0> { + pub fn td(&mut self) -> TD_W { TD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Data Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdr](index.html) module"] +#[doc = "Transmit Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TDR_SPEC; impl crate::RegisterSpec for TDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [tdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"] impl crate::Writable for TDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/wpmr.rs index c4d78f4e..16f83323 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/qspi/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/qspi/wpsr.rs index 07acbfac..23bbcfad 100644 --- a/arch/cortex-m/samv71q21-pac/src/qspi/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/qspi/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xff) as u8) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rstc.rs b/arch/cortex-m/samv71q21-pac/src/rstc.rs index 94399016..3c3fbd95 100644 --- a/arch/cortex-m/samv71q21-pac/src/rstc.rs +++ b/arch/cortex-m/samv71q21-pac/src/rstc.rs @@ -8,15 +8,18 @@ pub struct RegisterBlock { #[doc = "0x08 - Mode Register"] pub mr: MR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; diff --git a/arch/cortex-m/samv71q21-pac/src/rstc/cr.rs b/arch/cortex-m/samv71q21-pac/src/rstc/cr.rs index ca58cd3b..e8443cd0 100644 --- a/arch/cortex-m/samv71q21-pac/src/rstc/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rstc/cr.rs @@ -1,28 +1,9 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PROCRST` writer - Processor Reset"] -pub type PROCRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PROCRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXTRST` writer - External Reset"] -pub type EXTRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type EXTRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "System Reset Key\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -40,11 +21,15 @@ impl crate::FieldSpec for KEYSELECT_AW { type Ux = u8; } #[doc = "Field `KEY` writer - System Reset Key"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 8, O, KEYSELECT_AW>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_AW>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_AW::PASSWD) } } @@ -52,36 +37,35 @@ impl W { #[doc = "Bit 0 - Processor Reset"] #[inline(always)] #[must_use] - pub fn procrst(&mut self) -> PROCRST_W<0> { + pub fn procrst(&mut self) -> PROCRST_W { PROCRST_W::new(self) } #[doc = "Bit 3 - External Reset"] #[inline(always)] #[must_use] - pub fn extrst(&mut self) -> EXTRST_W<3> { + pub fn extrst(&mut self) -> EXTRST_W { EXTRST_W::new(self) } #[doc = "Bits 24:31 - System Reset Key"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<24> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rstc/mr.rs b/arch/cortex-m/samv71q21-pac/src/rstc/mr.rs index de35e696..600b07c3 100644 --- a/arch/cortex-m/samv71q21-pac/src/rstc/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rstc/mr.rs @@ -1,51 +1,19 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `URSTEN` reader - User Reset Enable"] pub type URSTEN_R = crate::BitReader; #[doc = "Field `URSTEN` writer - User Reset Enable"] -pub type URSTEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type URSTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `URSTIEN` reader - User Reset Interrupt Enable"] pub type URSTIEN_R = crate::BitReader; #[doc = "Field `URSTIEN` writer - User Reset Interrupt Enable"] -pub type URSTIEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type URSTIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERSTL` reader - External Reset Length"] pub type ERSTL_R = crate::FieldReader; #[doc = "Field `ERSTL` writer - External Reset Length"] -pub type ERSTL_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O>; +pub type ERSTL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `KEY` reader - Write Access Password"] pub type KEY_R = crate::FieldReader; #[doc = "Write Access Password\n\nValue on reset: 0"] @@ -73,18 +41,22 @@ impl KEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == KEYSELECT_A::PASSWD } } #[doc = "Field `KEY` writer - Write Access Password"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O, KEYSELECT_A>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_A>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_A::PASSWD) } } @@ -114,46 +86,43 @@ impl W { #[doc = "Bit 0 - User Reset Enable"] #[inline(always)] #[must_use] - pub fn ursten(&mut self) -> URSTEN_W<0> { + pub fn ursten(&mut self) -> URSTEN_W { URSTEN_W::new(self) } #[doc = "Bit 4 - User Reset Interrupt Enable"] #[inline(always)] #[must_use] - pub fn urstien(&mut self) -> URSTIEN_W<4> { + pub fn urstien(&mut self) -> URSTIEN_W { URSTIEN_W::new(self) } #[doc = "Bits 8:11 - External Reset Length"] #[inline(always)] #[must_use] - pub fn erstl(&mut self) -> ERSTL_W<8> { + pub fn erstl(&mut self) -> ERSTL_W { ERSTL_W::new(self) } #[doc = "Bits 24:31 - Write Access Password"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<24> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rstc/sr.rs b/arch/cortex-m/samv71q21-pac/src/rstc/sr.rs index 6e912347..31a231ce 100644 --- a/arch/cortex-m/samv71q21-pac/src/rstc/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rstc/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `URSTS` reader - User Reset Status"] pub type URSTS_R = crate::BitReader; #[doc = "Field `RSTTYP` reader - Reset Type"] @@ -54,27 +41,27 @@ impl RSTTYP_R { _ => None, } } - #[doc = "Checks if the value of the field is `GENERAL_RST`"] + #[doc = "First power-up reset"] #[inline(always)] pub fn is_general_rst(&self) -> bool { *self == RSTTYPSELECT_A::GENERAL_RST } - #[doc = "Checks if the value of the field is `BACKUP_RST`"] + #[doc = "Return from Backup Mode"] #[inline(always)] pub fn is_backup_rst(&self) -> bool { *self == RSTTYPSELECT_A::BACKUP_RST } - #[doc = "Checks if the value of the field is `WDT_RST`"] + #[doc = "Watchdog fault occurred"] #[inline(always)] pub fn is_wdt_rst(&self) -> bool { *self == RSTTYPSELECT_A::WDT_RST } - #[doc = "Checks if the value of the field is `SOFT_RST`"] + #[doc = "Processor reset required by the software"] #[inline(always)] pub fn is_soft_rst(&self) -> bool { *self == RSTTYPSELECT_A::SOFT_RST } - #[doc = "Checks if the value of the field is `USER_RST`"] + #[doc = "NRST pin detected low"] #[inline(always)] pub fn is_user_rst(&self) -> bool { *self == RSTTYPSELECT_A::USER_RST @@ -106,15 +93,13 @@ impl R { SRCMP_R::new(((self.bits >> 17) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rswdt.rs b/arch/cortex-m/samv71q21-pac/src/rswdt.rs index 7c245b25..71ec9362 100644 --- a/arch/cortex-m/samv71q21-pac/src/rswdt.rs +++ b/arch/cortex-m/samv71q21-pac/src/rswdt.rs @@ -8,15 +8,18 @@ pub struct RegisterBlock { #[doc = "0x08 - Status Register"] pub sr: SR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; diff --git a/arch/cortex-m/samv71q21-pac/src/rswdt/cr.rs b/arch/cortex-m/samv71q21-pac/src/rswdt/cr.rs index ffd245a3..27d9b0af 100644 --- a/arch/cortex-m/samv71q21-pac/src/rswdt/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rswdt/cr.rs @@ -1,26 +1,7 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WDRSTT` writer - Watchdog Restart"] -pub type WDRSTT_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type WDRSTT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Password\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -38,11 +19,15 @@ impl crate::FieldSpec for KEYSELECT_AW { type Ux = u8; } #[doc = "Field `KEY` writer - Password"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 8, O, KEYSELECT_AW>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_AW>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_AW::PASSWD) } } @@ -50,30 +35,29 @@ impl W { #[doc = "Bit 0 - Watchdog Restart"] #[inline(always)] #[must_use] - pub fn wdrstt(&mut self) -> WDRSTT_W<0> { + pub fn wdrstt(&mut self) -> WDRSTT_W { WDRSTT_W::new(self) } #[doc = "Bits 24:31 - Password"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<24> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rswdt/mr.rs b/arch/cortex-m/samv71q21-pac/src/rswdt/mr.rs index dda6ddac..c14fbba1 100644 --- a/arch/cortex-m/samv71q21-pac/src/rswdt/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rswdt/mr.rs @@ -1,67 +1,35 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WDV` reader - Watchdog Counter Value"] pub type WDV_R = crate::FieldReader; #[doc = "Field `WDV` writer - Watchdog Counter Value"] -pub type WDV_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 12, O, u16>; +pub type WDV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `WDFIEN` reader - Watchdog Fault Interrupt Enable"] pub type WDFIEN_R = crate::BitReader; #[doc = "Field `WDFIEN` writer - Watchdog Fault Interrupt Enable"] -pub type WDFIEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDFIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDRSTEN` reader - Watchdog Reset Enable"] pub type WDRSTEN_R = crate::BitReader; #[doc = "Field `WDRSTEN` writer - Watchdog Reset Enable"] -pub type WDRSTEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDRSTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDDIS` reader - Watchdog Disable"] pub type WDDIS_R = crate::BitReader; #[doc = "Field `WDDIS` writer - Watchdog Disable"] -pub type WDDIS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALLONES` reader - Must Always Be Written with 0xFFF"] pub type ALLONES_R = crate::FieldReader; #[doc = "Field `ALLONES` writer - Must Always Be Written with 0xFFF"] -pub type ALLONES_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 12, O, u16>; +pub type ALLONES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `WDDBGHLT` reader - Watchdog Debug Halt"] pub type WDDBGHLT_R = crate::BitReader; #[doc = "Field `WDDBGHLT` writer - Watchdog Debug Halt"] -pub type WDDBGHLT_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDDBGHLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDIDLEHLT` reader - Watchdog Idle Halt"] pub type WDIDLEHLT_R = crate::BitReader; #[doc = "Field `WDIDLEHLT` writer - Watchdog Idle Halt"] -pub type WDIDLEHLT_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDIDLEHLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:11 - Watchdog Counter Value"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bits 0:11 - Watchdog Counter Value"] #[inline(always)] #[must_use] - pub fn wdv(&mut self) -> WDV_W<0> { + pub fn wdv(&mut self) -> WDV_W { WDV_W::new(self) } #[doc = "Bit 12 - Watchdog Fault Interrupt Enable"] #[inline(always)] #[must_use] - pub fn wdfien(&mut self) -> WDFIEN_W<12> { + pub fn wdfien(&mut self) -> WDFIEN_W { WDFIEN_W::new(self) } #[doc = "Bit 13 - Watchdog Reset Enable"] #[inline(always)] #[must_use] - pub fn wdrsten(&mut self) -> WDRSTEN_W<13> { + pub fn wdrsten(&mut self) -> WDRSTEN_W { WDRSTEN_W::new(self) } #[doc = "Bit 15 - Watchdog Disable"] #[inline(always)] #[must_use] - pub fn wddis(&mut self) -> WDDIS_W<15> { + pub fn wddis(&mut self) -> WDDIS_W { WDDIS_W::new(self) } #[doc = "Bits 16:27 - Must Always Be Written with 0xFFF"] #[inline(always)] #[must_use] - pub fn allones(&mut self) -> ALLONES_W<16> { + pub fn allones(&mut self) -> ALLONES_W { ALLONES_W::new(self) } #[doc = "Bit 28 - Watchdog Debug Halt"] #[inline(always)] #[must_use] - pub fn wddbghlt(&mut self) -> WDDBGHLT_W<28> { + pub fn wddbghlt(&mut self) -> WDDBGHLT_W { WDDBGHLT_W::new(self) } #[doc = "Bit 29 - Watchdog Idle Halt"] #[inline(always)] #[must_use] - pub fn wdidlehlt(&mut self) -> WDIDLEHLT_W<29> { + pub fn wdidlehlt(&mut self) -> WDIDLEHLT_W { WDIDLEHLT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rswdt/sr.rs b/arch/cortex-m/samv71q21-pac/src/rswdt/sr.rs index 8968c695..b3c4474d 100644 --- a/arch/cortex-m/samv71q21-pac/src/rswdt/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rswdt/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WDUNF` reader - Watchdog Underflow"] pub type WDUNF_R = crate::BitReader; impl R { @@ -22,15 +9,13 @@ impl R { WDUNF_R::new((self.bits & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rtc.rs b/arch/cortex-m/samv71q21-pac/src/rtc.rs index 51efcbef..6a3fca6a 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc.rs @@ -26,51 +26,63 @@ pub struct RegisterBlock { #[doc = "0x2c - Valid Entry Register"] pub ver: VER, } -#[doc = "CR (rw) register accessor: an alias for `Reg`"] +#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "TIMR (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMR (rw) register accessor: Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`timr`] +module"] pub type TIMR = crate::Reg; #[doc = "Time Register"] pub mod timr; -#[doc = "CALR (rw) register accessor: an alias for `Reg`"] +#[doc = "CALR (rw) register accessor: Calendar Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`calr`] +module"] pub type CALR = crate::Reg; #[doc = "Calendar Register"] pub mod calr; -#[doc = "TIMALR (rw) register accessor: an alias for `Reg`"] +#[doc = "TIMALR (rw) register accessor: Time Alarm Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timalr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timalr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`timalr`] +module"] pub type TIMALR = crate::Reg; #[doc = "Time Alarm Register"] pub mod timalr; -#[doc = "CALALR (rw) register accessor: an alias for `Reg`"] +#[doc = "CALALR (rw) register accessor: Calendar Alarm Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calalr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calalr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`calalr`] +module"] pub type CALALR = crate::Reg; #[doc = "Calendar Alarm Register"] pub mod calalr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "SCCR (w) register accessor: an alias for `Reg`"] +#[doc = "SCCR (w) register accessor: Status Clear Command Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sccr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sccr`] +module"] pub type SCCR = crate::Reg; #[doc = "Status Clear Command Register"] pub mod sccr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "VER (r) register accessor: an alias for `Reg`"] +#[doc = "VER (r) register accessor: Valid Entry Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ver`] +module"] pub type VER = crate::Reg; #[doc = "Valid Entry Register"] pub mod ver; diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/calalr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/calalr.rs index 860eae1b..6db67513 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/calalr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/calalr.rs @@ -1,55 +1,23 @@ #[doc = "Register `CALALR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CALALR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MONTH` reader - Month Alarm"] pub type MONTH_R = crate::FieldReader; #[doc = "Field `MONTH` writer - Month Alarm"] -pub type MONTH_W<'a, const O: u8> = crate::FieldWriter<'a, CALALR_SPEC, 5, O>; +pub type MONTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `MTHEN` reader - Month Alarm Enable"] pub type MTHEN_R = crate::BitReader; #[doc = "Field `MTHEN` writer - Month Alarm Enable"] -pub type MTHEN_W<'a, const O: u8> = crate::BitWriter<'a, CALALR_SPEC, O>; +pub type MTHEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATE` reader - Date Alarm"] pub type DATE_R = crate::FieldReader; #[doc = "Field `DATE` writer - Date Alarm"] -pub type DATE_W<'a, const O: u8> = crate::FieldWriter<'a, CALALR_SPEC, 6, O>; +pub type DATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `DATEEN` reader - Date Alarm Enable"] pub type DATEEN_R = crate::BitReader; #[doc = "Field `DATEEN` writer - Date Alarm Enable"] -pub type DATEEN_W<'a, const O: u8> = crate::BitWriter<'a, CALALR_SPEC, O>; +pub type DATEEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 16:20 - Month Alarm"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 16:20 - Month Alarm"] #[inline(always)] #[must_use] - pub fn month(&mut self) -> MONTH_W<16> { + pub fn month(&mut self) -> MONTH_W { MONTH_W::new(self) } #[doc = "Bit 23 - Month Alarm Enable"] #[inline(always)] #[must_use] - pub fn mthen(&mut self) -> MTHEN_W<23> { + pub fn mthen(&mut self) -> MTHEN_W { MTHEN_W::new(self) } #[doc = "Bits 24:29 - Date Alarm"] #[inline(always)] #[must_use] - pub fn date(&mut self) -> DATE_W<24> { + pub fn date(&mut self) -> DATE_W { DATE_W::new(self) } #[doc = "Bit 31 - Date Alarm Enable"] #[inline(always)] #[must_use] - pub fn dateen(&mut self) -> DATEEN_W<31> { + pub fn dateen(&mut self) -> DATEEN_W { DATEEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Calendar Alarm Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calalr](index.html) module"] +#[doc = "Calendar Alarm Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calalr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calalr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CALALR_SPEC; impl crate::RegisterSpec for CALALR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [calalr::R](R) reader structure"] -impl crate::Readable for CALALR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [calalr::W](W) writer structure"] +#[doc = "`read()` method returns [`calalr::R`](R) reader structure"] +impl crate::Readable for CALALR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`calalr::W`](W) writer structure"] impl crate::Writable for CALALR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/calr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/calr.rs index fe7bbb5b..26c895aa 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/calr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/calr.rs @@ -1,59 +1,27 @@ #[doc = "Register `CALR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CALR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CENT` reader - Current Century"] pub type CENT_R = crate::FieldReader; #[doc = "Field `CENT` writer - Current Century"] -pub type CENT_W<'a, const O: u8> = crate::FieldWriter<'a, CALR_SPEC, 7, O>; +pub type CENT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `YEAR` reader - Current Year"] pub type YEAR_R = crate::FieldReader; #[doc = "Field `YEAR` writer - Current Year"] -pub type YEAR_W<'a, const O: u8> = crate::FieldWriter<'a, CALR_SPEC, 8, O>; +pub type YEAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `MONTH` reader - Current Month"] pub type MONTH_R = crate::FieldReader; #[doc = "Field `MONTH` writer - Current Month"] -pub type MONTH_W<'a, const O: u8> = crate::FieldWriter<'a, CALR_SPEC, 5, O>; +pub type MONTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DAY` reader - Current Day in Current Week"] pub type DAY_R = crate::FieldReader; #[doc = "Field `DAY` writer - Current Day in Current Week"] -pub type DAY_W<'a, const O: u8> = crate::FieldWriter<'a, CALR_SPEC, 3, O>; +pub type DAY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `DATE` reader - Current Day in Current Month"] pub type DATE_R = crate::FieldReader; #[doc = "Field `DATE` writer - Current Day in Current Month"] -pub type DATE_W<'a, const O: u8> = crate::FieldWriter<'a, CALR_SPEC, 6, O>; +pub type DATE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:6 - Current Century"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bits 0:6 - Current Century"] #[inline(always)] #[must_use] - pub fn cent(&mut self) -> CENT_W<0> { + pub fn cent(&mut self) -> CENT_W { CENT_W::new(self) } #[doc = "Bits 8:15 - Current Year"] #[inline(always)] #[must_use] - pub fn year(&mut self) -> YEAR_W<8> { + pub fn year(&mut self) -> YEAR_W { YEAR_W::new(self) } #[doc = "Bits 16:20 - Current Month"] #[inline(always)] #[must_use] - pub fn month(&mut self) -> MONTH_W<16> { + pub fn month(&mut self) -> MONTH_W { MONTH_W::new(self) } #[doc = "Bits 21:23 - Current Day in Current Week"] #[inline(always)] #[must_use] - pub fn day(&mut self) -> DAY_W<21> { + pub fn day(&mut self) -> DAY_W { DAY_W::new(self) } #[doc = "Bits 24:29 - Current Day in Current Month"] #[inline(always)] #[must_use] - pub fn date(&mut self) -> DATE_W<24> { + pub fn date(&mut self) -> DATE_W { DATE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Calendar Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calr](index.html) module"] +#[doc = "Calendar Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`calr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CALR_SPEC; impl crate::RegisterSpec for CALR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [calr::R](R) reader structure"] -impl crate::Readable for CALR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [calr::W](W) writer structure"] +#[doc = "`read()` method returns [`calr::R`](R) reader structure"] +impl crate::Readable for CALR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`calr::W`](W) writer structure"] impl crate::Writable for CALR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/cr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/cr.rs index 91415a27..c3b746d6 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/cr.rs @@ -1,47 +1,15 @@ #[doc = "Register `CR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UPDTIM` reader - Update Request Time Register"] pub type UPDTIM_R = crate::BitReader; #[doc = "Field `UPDTIM` writer - Update Request Time Register"] -pub type UPDTIM_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type UPDTIM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPDCAL` reader - Update Request Calendar Register"] pub type UPDCAL_R = crate::BitReader; #[doc = "Field `UPDCAL` writer - Update Request Calendar Register"] -pub type UPDCAL_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type UPDCAL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEVSEL` reader - Time Event Selection"] pub type TIMEVSEL_R = crate::FieldReader; #[doc = "Time Event Selection\n\nValue on reset: 0"] @@ -78,48 +46,52 @@ impl TIMEVSEL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `MINUTE`"] + #[doc = "Minute change"] #[inline(always)] pub fn is_minute(&self) -> bool { *self == TIMEVSELSELECT_A::MINUTE } - #[doc = "Checks if the value of the field is `HOUR`"] + #[doc = "Hour change"] #[inline(always)] pub fn is_hour(&self) -> bool { *self == TIMEVSELSELECT_A::HOUR } - #[doc = "Checks if the value of the field is `MIDNIGHT`"] + #[doc = "Every day at midnight"] #[inline(always)] pub fn is_midnight(&self) -> bool { *self == TIMEVSELSELECT_A::MIDNIGHT } - #[doc = "Checks if the value of the field is `NOON`"] + #[doc = "Every day at noon"] #[inline(always)] pub fn is_noon(&self) -> bool { *self == TIMEVSELSELECT_A::NOON } } #[doc = "Field `TIMEVSEL` writer - Time Event Selection"] -pub type TIMEVSEL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CR_SPEC, 2, O, TIMEVSELSELECT_A>; -impl<'a, const O: u8> TIMEVSEL_W<'a, O> { +pub type TIMEVSEL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TIMEVSELSELECT_A>; +impl<'a, REG, const O: u8> TIMEVSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Minute change"] #[inline(always)] - pub fn minute(self) -> &'a mut W { + pub fn minute(self) -> &'a mut crate::W { self.variant(TIMEVSELSELECT_A::MINUTE) } #[doc = "Hour change"] #[inline(always)] - pub fn hour(self) -> &'a mut W { + pub fn hour(self) -> &'a mut crate::W { self.variant(TIMEVSELSELECT_A::HOUR) } #[doc = "Every day at midnight"] #[inline(always)] - pub fn midnight(self) -> &'a mut W { + pub fn midnight(self) -> &'a mut crate::W { self.variant(TIMEVSELSELECT_A::MIDNIGHT) } #[doc = "Every day at noon"] #[inline(always)] - pub fn noon(self) -> &'a mut W { + pub fn noon(self) -> &'a mut crate::W { self.variant(TIMEVSELSELECT_A::NOON) } } @@ -156,38 +128,42 @@ impl CALEVSEL_R { _ => None, } } - #[doc = "Checks if the value of the field is `WEEK`"] + #[doc = "Week change (every Monday at time 00:00:00)"] #[inline(always)] pub fn is_week(&self) -> bool { *self == CALEVSELSELECT_A::WEEK } - #[doc = "Checks if the value of the field is `MONTH`"] + #[doc = "Month change (every 01 of each month at time 00:00:00)"] #[inline(always)] pub fn is_month(&self) -> bool { *self == CALEVSELSELECT_A::MONTH } - #[doc = "Checks if the value of the field is `YEAR`"] + #[doc = "Year change (every January 1 at time 00:00:00)"] #[inline(always)] pub fn is_year(&self) -> bool { *self == CALEVSELSELECT_A::YEAR } } #[doc = "Field `CALEVSEL` writer - Calendar Event Selection"] -pub type CALEVSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 2, O, CALEVSELSELECT_A>; -impl<'a, const O: u8> CALEVSEL_W<'a, O> { +pub type CALEVSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CALEVSELSELECT_A>; +impl<'a, REG, const O: u8> CALEVSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Week change (every Monday at time 00:00:00)"] #[inline(always)] - pub fn week(self) -> &'a mut W { + pub fn week(self) -> &'a mut crate::W { self.variant(CALEVSELSELECT_A::WEEK) } #[doc = "Month change (every 01 of each month at time 00:00:00)"] #[inline(always)] - pub fn month(self) -> &'a mut W { + pub fn month(self) -> &'a mut crate::W { self.variant(CALEVSELSELECT_A::MONTH) } #[doc = "Year change (every January 1 at time 00:00:00)"] #[inline(always)] - pub fn year(self) -> &'a mut W { + pub fn year(self) -> &'a mut crate::W { self.variant(CALEVSELSELECT_A::YEAR) } } @@ -217,46 +193,43 @@ impl W { #[doc = "Bit 0 - Update Request Time Register"] #[inline(always)] #[must_use] - pub fn updtim(&mut self) -> UPDTIM_W<0> { + pub fn updtim(&mut self) -> UPDTIM_W { UPDTIM_W::new(self) } #[doc = "Bit 1 - Update Request Calendar Register"] #[inline(always)] #[must_use] - pub fn updcal(&mut self) -> UPDCAL_W<1> { + pub fn updcal(&mut self) -> UPDCAL_W { UPDCAL_W::new(self) } #[doc = "Bits 8:9 - Time Event Selection"] #[inline(always)] #[must_use] - pub fn timevsel(&mut self) -> TIMEVSEL_W<8> { + pub fn timevsel(&mut self) -> TIMEVSEL_W { TIMEVSEL_W::new(self) } #[doc = "Bits 16:17 - Calendar Event Selection"] #[inline(always)] #[must_use] - pub fn calevsel(&mut self) -> CALEVSEL_W<16> { + pub fn calevsel(&mut self) -> CALEVSEL_W { CALEVSEL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cr::R](R) reader structure"] -impl crate::Readable for CR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`read()` method returns [`cr::R`](R) reader structure"] +impl crate::Readable for CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/idr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/idr.rs index 3097c41f..d8bf1714 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/idr.rs @@ -1,88 +1,68 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACKDIS` writer - Acknowledge Update Interrupt Disable"] -pub type ACKDIS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ACKDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALRDIS` writer - Alarm Interrupt Disable"] -pub type ALRDIS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ALRDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SECDIS` writer - Second Event Interrupt Disable"] -pub type SECDIS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SECDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMDIS` writer - Time Event Interrupt Disable"] -pub type TIMDIS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TIMDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CALDIS` writer - Calendar Event Interrupt Disable"] -pub type CALDIS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CALDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDERRDIS` writer - Time and/or Date Error Interrupt Disable"] -pub type TDERRDIS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TDERRDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Acknowledge Update Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ackdis(&mut self) -> ACKDIS_W<0> { + pub fn ackdis(&mut self) -> ACKDIS_W { ACKDIS_W::new(self) } #[doc = "Bit 1 - Alarm Interrupt Disable"] #[inline(always)] #[must_use] - pub fn alrdis(&mut self) -> ALRDIS_W<1> { + pub fn alrdis(&mut self) -> ALRDIS_W { ALRDIS_W::new(self) } #[doc = "Bit 2 - Second Event Interrupt Disable"] #[inline(always)] #[must_use] - pub fn secdis(&mut self) -> SECDIS_W<2> { + pub fn secdis(&mut self) -> SECDIS_W { SECDIS_W::new(self) } #[doc = "Bit 3 - Time Event Interrupt Disable"] #[inline(always)] #[must_use] - pub fn timdis(&mut self) -> TIMDIS_W<3> { + pub fn timdis(&mut self) -> TIMDIS_W { TIMDIS_W::new(self) } #[doc = "Bit 4 - Calendar Event Interrupt Disable"] #[inline(always)] #[must_use] - pub fn caldis(&mut self) -> CALDIS_W<4> { + pub fn caldis(&mut self) -> CALDIS_W { CALDIS_W::new(self) } #[doc = "Bit 5 - Time and/or Date Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn tderrdis(&mut self) -> TDERRDIS_W<5> { + pub fn tderrdis(&mut self) -> TDERRDIS_W { TDERRDIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/ier.rs b/arch/cortex-m/samv71q21-pac/src/rtc/ier.rs index f7660d53..6f948551 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/ier.rs @@ -1,88 +1,68 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACKEN` writer - Acknowledge Update Interrupt Enable"] -pub type ACKEN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ACKEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALREN` writer - Alarm Interrupt Enable"] -pub type ALREN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ALREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SECEN` writer - Second Event Interrupt Enable"] -pub type SECEN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SECEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEN` writer - Time Event Interrupt Enable"] -pub type TIMEN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TIMEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CALEN` writer - Calendar Event Interrupt Enable"] -pub type CALEN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CALEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDERREN` writer - Time and/or Date Error Interrupt Enable"] -pub type TDERREN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TDERREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Acknowledge Update Interrupt Enable"] #[inline(always)] #[must_use] - pub fn acken(&mut self) -> ACKEN_W<0> { + pub fn acken(&mut self) -> ACKEN_W { ACKEN_W::new(self) } #[doc = "Bit 1 - Alarm Interrupt Enable"] #[inline(always)] #[must_use] - pub fn alren(&mut self) -> ALREN_W<1> { + pub fn alren(&mut self) -> ALREN_W { ALREN_W::new(self) } #[doc = "Bit 2 - Second Event Interrupt Enable"] #[inline(always)] #[must_use] - pub fn secen(&mut self) -> SECEN_W<2> { + pub fn secen(&mut self) -> SECEN_W { SECEN_W::new(self) } #[doc = "Bit 3 - Time Event Interrupt Enable"] #[inline(always)] #[must_use] - pub fn timen(&mut self) -> TIMEN_W<3> { + pub fn timen(&mut self) -> TIMEN_W { TIMEN_W::new(self) } #[doc = "Bit 4 - Calendar Event Interrupt Enable"] #[inline(always)] #[must_use] - pub fn calen(&mut self) -> CALEN_W<4> { + pub fn calen(&mut self) -> CALEN_W { CALEN_W::new(self) } #[doc = "Bit 5 - Time and/or Date Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tderren(&mut self) -> TDERREN_W<5> { + pub fn tderren(&mut self) -> TDERREN_W { TDERREN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/imr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/imr.rs index 523e426a..939877e9 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ACK` reader - Acknowledge Update Interrupt Mask"] pub type ACK_R = crate::BitReader; #[doc = "Field `ALR` reader - Alarm Interrupt Mask"] @@ -57,15 +44,13 @@ impl R { TDERR_R::new(((self.bits >> 5) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/mr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/mr.rs index b77378ac..e90ce0e1 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/mr.rs @@ -1,59 +1,27 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HRMOD` reader - 12-/24-hour Mode"] pub type HRMOD_R = crate::BitReader; #[doc = "Field `HRMOD` writer - 12-/24-hour Mode"] -pub type HRMOD_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type HRMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERSIAN` reader - PERSIAN Calendar"] pub type PERSIAN_R = crate::BitReader; #[doc = "Field `PERSIAN` writer - PERSIAN Calendar"] -pub type PERSIAN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type PERSIAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NEGPPM` reader - NEGative PPM Correction"] pub type NEGPPM_R = crate::BitReader; #[doc = "Field `NEGPPM` writer - NEGative PPM Correction"] -pub type NEGPPM_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type NEGPPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CORRECTION` reader - Slow Clock Correction"] pub type CORRECTION_R = crate::FieldReader; #[doc = "Field `CORRECTION` writer - Slow Clock Correction"] -pub type CORRECTION_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 7, O>; +pub type CORRECTION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HIGHPPM` reader - HIGH PPM Correction"] pub type HIGHPPM_R = crate::BitReader; #[doc = "Field `HIGHPPM` writer - HIGH PPM Correction"] -pub type HIGHPPM_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type HIGHPPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OUT0` reader - RTCOUT0 OutputSource Selection"] pub type OUT0_R = crate::FieldReader; #[doc = "RTCOUT0 OutputSource Selection\n\nValue on reset: 0"] @@ -102,88 +70,92 @@ impl OUT0_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NO_WAVE`"] + #[doc = "No waveform, stuck at '0'"] #[inline(always)] pub fn is_no_wave(&self) -> bool { *self == OUT0SELECT_A::NO_WAVE } - #[doc = "Checks if the value of the field is `FREQ1HZ`"] + #[doc = "1 Hz square wave"] #[inline(always)] pub fn is_freq1hz(&self) -> bool { *self == OUT0SELECT_A::FREQ1HZ } - #[doc = "Checks if the value of the field is `FREQ32HZ`"] + #[doc = "32 Hz square wave"] #[inline(always)] pub fn is_freq32hz(&self) -> bool { *self == OUT0SELECT_A::FREQ32HZ } - #[doc = "Checks if the value of the field is `FREQ64HZ`"] + #[doc = "64 Hz square wave"] #[inline(always)] pub fn is_freq64hz(&self) -> bool { *self == OUT0SELECT_A::FREQ64HZ } - #[doc = "Checks if the value of the field is `FREQ512HZ`"] + #[doc = "512 Hz square wave"] #[inline(always)] pub fn is_freq512hz(&self) -> bool { *self == OUT0SELECT_A::FREQ512HZ } - #[doc = "Checks if the value of the field is `ALARM_TOGGLE`"] + #[doc = "Output toggles when alarm flag rises"] #[inline(always)] pub fn is_alarm_toggle(&self) -> bool { *self == OUT0SELECT_A::ALARM_TOGGLE } - #[doc = "Checks if the value of the field is `ALARM_FLAG`"] + #[doc = "Output is a copy of the alarm flag"] #[inline(always)] pub fn is_alarm_flag(&self) -> bool { *self == OUT0SELECT_A::ALARM_FLAG } - #[doc = "Checks if the value of the field is `PROG_PULSE`"] + #[doc = "Duty cycle programmable pulse"] #[inline(always)] pub fn is_prog_pulse(&self) -> bool { *self == OUT0SELECT_A::PROG_PULSE } } #[doc = "Field `OUT0` writer - RTCOUT0 OutputSource Selection"] -pub type OUT0_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 3, O, OUT0SELECT_A>; -impl<'a, const O: u8> OUT0_W<'a, O> { +pub type OUT0_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, OUT0SELECT_A>; +impl<'a, REG, const O: u8> OUT0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No waveform, stuck at '0'"] #[inline(always)] - pub fn no_wave(self) -> &'a mut W { + pub fn no_wave(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::NO_WAVE) } #[doc = "1 Hz square wave"] #[inline(always)] - pub fn freq1hz(self) -> &'a mut W { + pub fn freq1hz(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::FREQ1HZ) } #[doc = "32 Hz square wave"] #[inline(always)] - pub fn freq32hz(self) -> &'a mut W { + pub fn freq32hz(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::FREQ32HZ) } #[doc = "64 Hz square wave"] #[inline(always)] - pub fn freq64hz(self) -> &'a mut W { + pub fn freq64hz(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::FREQ64HZ) } #[doc = "512 Hz square wave"] #[inline(always)] - pub fn freq512hz(self) -> &'a mut W { + pub fn freq512hz(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::FREQ512HZ) } #[doc = "Output toggles when alarm flag rises"] #[inline(always)] - pub fn alarm_toggle(self) -> &'a mut W { + pub fn alarm_toggle(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::ALARM_TOGGLE) } #[doc = "Output is a copy of the alarm flag"] #[inline(always)] - pub fn alarm_flag(self) -> &'a mut W { + pub fn alarm_flag(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::ALARM_FLAG) } #[doc = "Duty cycle programmable pulse"] #[inline(always)] - pub fn prog_pulse(self) -> &'a mut W { + pub fn prog_pulse(self) -> &'a mut crate::W { self.variant(OUT0SELECT_A::PROG_PULSE) } } @@ -235,88 +207,92 @@ impl OUT1_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NO_WAVE`"] + #[doc = "No waveform, stuck at '0'"] #[inline(always)] pub fn is_no_wave(&self) -> bool { *self == OUT1SELECT_A::NO_WAVE } - #[doc = "Checks if the value of the field is `FREQ1HZ`"] + #[doc = "1 Hz square wave"] #[inline(always)] pub fn is_freq1hz(&self) -> bool { *self == OUT1SELECT_A::FREQ1HZ } - #[doc = "Checks if the value of the field is `FREQ32HZ`"] + #[doc = "32 Hz square wave"] #[inline(always)] pub fn is_freq32hz(&self) -> bool { *self == OUT1SELECT_A::FREQ32HZ } - #[doc = "Checks if the value of the field is `FREQ64HZ`"] + #[doc = "64 Hz square wave"] #[inline(always)] pub fn is_freq64hz(&self) -> bool { *self == OUT1SELECT_A::FREQ64HZ } - #[doc = "Checks if the value of the field is `FREQ512HZ`"] + #[doc = "512 Hz square wave"] #[inline(always)] pub fn is_freq512hz(&self) -> bool { *self == OUT1SELECT_A::FREQ512HZ } - #[doc = "Checks if the value of the field is `ALARM_TOGGLE`"] + #[doc = "Output toggles when alarm flag rises"] #[inline(always)] pub fn is_alarm_toggle(&self) -> bool { *self == OUT1SELECT_A::ALARM_TOGGLE } - #[doc = "Checks if the value of the field is `ALARM_FLAG`"] + #[doc = "Output is a copy of the alarm flag"] #[inline(always)] pub fn is_alarm_flag(&self) -> bool { *self == OUT1SELECT_A::ALARM_FLAG } - #[doc = "Checks if the value of the field is `PROG_PULSE`"] + #[doc = "Duty cycle programmable pulse"] #[inline(always)] pub fn is_prog_pulse(&self) -> bool { *self == OUT1SELECT_A::PROG_PULSE } } #[doc = "Field `OUT1` writer - RTCOUT1 Output Source Selection"] -pub type OUT1_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 3, O, OUT1SELECT_A>; -impl<'a, const O: u8> OUT1_W<'a, O> { +pub type OUT1_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, OUT1SELECT_A>; +impl<'a, REG, const O: u8> OUT1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No waveform, stuck at '0'"] #[inline(always)] - pub fn no_wave(self) -> &'a mut W { + pub fn no_wave(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::NO_WAVE) } #[doc = "1 Hz square wave"] #[inline(always)] - pub fn freq1hz(self) -> &'a mut W { + pub fn freq1hz(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::FREQ1HZ) } #[doc = "32 Hz square wave"] #[inline(always)] - pub fn freq32hz(self) -> &'a mut W { + pub fn freq32hz(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::FREQ32HZ) } #[doc = "64 Hz square wave"] #[inline(always)] - pub fn freq64hz(self) -> &'a mut W { + pub fn freq64hz(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::FREQ64HZ) } #[doc = "512 Hz square wave"] #[inline(always)] - pub fn freq512hz(self) -> &'a mut W { + pub fn freq512hz(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::FREQ512HZ) } #[doc = "Output toggles when alarm flag rises"] #[inline(always)] - pub fn alarm_toggle(self) -> &'a mut W { + pub fn alarm_toggle(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::ALARM_TOGGLE) } #[doc = "Output is a copy of the alarm flag"] #[inline(always)] - pub fn alarm_flag(self) -> &'a mut W { + pub fn alarm_flag(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::ALARM_FLAG) } #[doc = "Duty cycle programmable pulse"] #[inline(always)] - pub fn prog_pulse(self) -> &'a mut W { + pub fn prog_pulse(self) -> &'a mut crate::W { self.variant(OUT1SELECT_A::PROG_PULSE) } } @@ -368,88 +344,92 @@ impl THIGH_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `H_31MS`"] + #[doc = "31.2 ms"] #[inline(always)] pub fn is_h_31ms(&self) -> bool { *self == THIGHSELECT_A::H_31MS } - #[doc = "Checks if the value of the field is `H_16MS`"] + #[doc = "15.6 ms"] #[inline(always)] pub fn is_h_16ms(&self) -> bool { *self == THIGHSELECT_A::H_16MS } - #[doc = "Checks if the value of the field is `H_4MS`"] + #[doc = "3.91 ms"] #[inline(always)] pub fn is_h_4ms(&self) -> bool { *self == THIGHSELECT_A::H_4MS } - #[doc = "Checks if the value of the field is `H_976US`"] + #[doc = "976 us"] #[inline(always)] pub fn is_h_976us(&self) -> bool { *self == THIGHSELECT_A::H_976US } - #[doc = "Checks if the value of the field is `H_488US`"] + #[doc = "488 us"] #[inline(always)] pub fn is_h_488us(&self) -> bool { *self == THIGHSELECT_A::H_488US } - #[doc = "Checks if the value of the field is `H_122US`"] + #[doc = "122 us"] #[inline(always)] pub fn is_h_122us(&self) -> bool { *self == THIGHSELECT_A::H_122US } - #[doc = "Checks if the value of the field is `H_30US`"] + #[doc = "30.5 us"] #[inline(always)] pub fn is_h_30us(&self) -> bool { *self == THIGHSELECT_A::H_30US } - #[doc = "Checks if the value of the field is `H_15US`"] + #[doc = "15.2 us"] #[inline(always)] pub fn is_h_15us(&self) -> bool { *self == THIGHSELECT_A::H_15US } } #[doc = "Field `THIGH` writer - High Duration of the Output Pulse"] -pub type THIGH_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 3, O, THIGHSELECT_A>; -impl<'a, const O: u8> THIGH_W<'a, O> { +pub type THIGH_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, THIGHSELECT_A>; +impl<'a, REG, const O: u8> THIGH_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "31.2 ms"] #[inline(always)] - pub fn h_31ms(self) -> &'a mut W { + pub fn h_31ms(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_31MS) } #[doc = "15.6 ms"] #[inline(always)] - pub fn h_16ms(self) -> &'a mut W { + pub fn h_16ms(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_16MS) } #[doc = "3.91 ms"] #[inline(always)] - pub fn h_4ms(self) -> &'a mut W { + pub fn h_4ms(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_4MS) } #[doc = "976 us"] #[inline(always)] - pub fn h_976us(self) -> &'a mut W { + pub fn h_976us(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_976US) } #[doc = "488 us"] #[inline(always)] - pub fn h_488us(self) -> &'a mut W { + pub fn h_488us(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_488US) } #[doc = "122 us"] #[inline(always)] - pub fn h_122us(self) -> &'a mut W { + pub fn h_122us(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_122US) } #[doc = "30.5 us"] #[inline(always)] - pub fn h_30us(self) -> &'a mut W { + pub fn h_30us(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_30US) } #[doc = "15.2 us"] #[inline(always)] - pub fn h_15us(self) -> &'a mut W { + pub fn h_15us(self) -> &'a mut crate::W { self.variant(THIGHSELECT_A::H_15US) } } @@ -489,48 +469,52 @@ impl TPERIOD_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `P_1S`"] + #[doc = "1 second"] #[inline(always)] pub fn is_p_1s(&self) -> bool { *self == TPERIODSELECT_A::P_1S } - #[doc = "Checks if the value of the field is `P_500MS`"] + #[doc = "500 ms"] #[inline(always)] pub fn is_p_500ms(&self) -> bool { *self == TPERIODSELECT_A::P_500MS } - #[doc = "Checks if the value of the field is `P_250MS`"] + #[doc = "250 ms"] #[inline(always)] pub fn is_p_250ms(&self) -> bool { *self == TPERIODSELECT_A::P_250MS } - #[doc = "Checks if the value of the field is `P_125MS`"] + #[doc = "125 ms"] #[inline(always)] pub fn is_p_125ms(&self) -> bool { *self == TPERIODSELECT_A::P_125MS } } #[doc = "Field `TPERIOD` writer - Period of the Output Pulse"] -pub type TPERIOD_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 2, O, TPERIODSELECT_A>; -impl<'a, const O: u8> TPERIOD_W<'a, O> { +pub type TPERIOD_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TPERIODSELECT_A>; +impl<'a, REG, const O: u8> TPERIOD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "1 second"] #[inline(always)] - pub fn p_1s(self) -> &'a mut W { + pub fn p_1s(self) -> &'a mut crate::W { self.variant(TPERIODSELECT_A::P_1S) } #[doc = "500 ms"] #[inline(always)] - pub fn p_500ms(self) -> &'a mut W { + pub fn p_500ms(self) -> &'a mut crate::W { self.variant(TPERIODSELECT_A::P_500MS) } #[doc = "250 ms"] #[inline(always)] - pub fn p_250ms(self) -> &'a mut W { + pub fn p_250ms(self) -> &'a mut crate::W { self.variant(TPERIODSELECT_A::P_250MS) } #[doc = "125 ms"] #[inline(always)] - pub fn p_125ms(self) -> &'a mut W { + pub fn p_125ms(self) -> &'a mut crate::W { self.variant(TPERIODSELECT_A::P_125MS) } } @@ -585,76 +569,73 @@ impl W { #[doc = "Bit 0 - 12-/24-hour Mode"] #[inline(always)] #[must_use] - pub fn hrmod(&mut self) -> HRMOD_W<0> { + pub fn hrmod(&mut self) -> HRMOD_W { HRMOD_W::new(self) } #[doc = "Bit 1 - PERSIAN Calendar"] #[inline(always)] #[must_use] - pub fn persian(&mut self) -> PERSIAN_W<1> { + pub fn persian(&mut self) -> PERSIAN_W { PERSIAN_W::new(self) } #[doc = "Bit 4 - NEGative PPM Correction"] #[inline(always)] #[must_use] - pub fn negppm(&mut self) -> NEGPPM_W<4> { + pub fn negppm(&mut self) -> NEGPPM_W { NEGPPM_W::new(self) } #[doc = "Bits 8:14 - Slow Clock Correction"] #[inline(always)] #[must_use] - pub fn correction(&mut self) -> CORRECTION_W<8> { + pub fn correction(&mut self) -> CORRECTION_W { CORRECTION_W::new(self) } #[doc = "Bit 15 - HIGH PPM Correction"] #[inline(always)] #[must_use] - pub fn highppm(&mut self) -> HIGHPPM_W<15> { + pub fn highppm(&mut self) -> HIGHPPM_W { HIGHPPM_W::new(self) } #[doc = "Bits 16:18 - RTCOUT0 OutputSource Selection"] #[inline(always)] #[must_use] - pub fn out0(&mut self) -> OUT0_W<16> { + pub fn out0(&mut self) -> OUT0_W { OUT0_W::new(self) } #[doc = "Bits 20:22 - RTCOUT1 Output Source Selection"] #[inline(always)] #[must_use] - pub fn out1(&mut self) -> OUT1_W<20> { + pub fn out1(&mut self) -> OUT1_W { OUT1_W::new(self) } #[doc = "Bits 24:26 - High Duration of the Output Pulse"] #[inline(always)] #[must_use] - pub fn thigh(&mut self) -> THIGH_W<24> { + pub fn thigh(&mut self) -> THIGH_W { THIGH_W::new(self) } #[doc = "Bits 28:29 - Period of the Output Pulse"] #[inline(always)] #[must_use] - pub fn tperiod(&mut self) -> TPERIOD_W<28> { + pub fn tperiod(&mut self) -> TPERIOD_W { TPERIOD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/sccr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/sccr.rs index 4b7be530..37f0eedf 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/sccr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/sccr.rs @@ -1,88 +1,68 @@ #[doc = "Register `SCCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ACKCLR` writer - Acknowledge Clear"] -pub type ACKCLR_W<'a, const O: u8> = crate::BitWriter<'a, SCCR_SPEC, O>; +pub type ACKCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ALRCLR` writer - Alarm Clear"] -pub type ALRCLR_W<'a, const O: u8> = crate::BitWriter<'a, SCCR_SPEC, O>; +pub type ALRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SECCLR` writer - Second Clear"] -pub type SECCLR_W<'a, const O: u8> = crate::BitWriter<'a, SCCR_SPEC, O>; +pub type SECCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMCLR` writer - Time Clear"] -pub type TIMCLR_W<'a, const O: u8> = crate::BitWriter<'a, SCCR_SPEC, O>; +pub type TIMCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CALCLR` writer - Calendar Clear"] -pub type CALCLR_W<'a, const O: u8> = crate::BitWriter<'a, SCCR_SPEC, O>; +pub type CALCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDERRCLR` writer - Time and/or Date Free Running Error Clear"] -pub type TDERRCLR_W<'a, const O: u8> = crate::BitWriter<'a, SCCR_SPEC, O>; +pub type TDERRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Acknowledge Clear"] #[inline(always)] #[must_use] - pub fn ackclr(&mut self) -> ACKCLR_W<0> { + pub fn ackclr(&mut self) -> ACKCLR_W { ACKCLR_W::new(self) } #[doc = "Bit 1 - Alarm Clear"] #[inline(always)] #[must_use] - pub fn alrclr(&mut self) -> ALRCLR_W<1> { + pub fn alrclr(&mut self) -> ALRCLR_W { ALRCLR_W::new(self) } #[doc = "Bit 2 - Second Clear"] #[inline(always)] #[must_use] - pub fn secclr(&mut self) -> SECCLR_W<2> { + pub fn secclr(&mut self) -> SECCLR_W { SECCLR_W::new(self) } #[doc = "Bit 3 - Time Clear"] #[inline(always)] #[must_use] - pub fn timclr(&mut self) -> TIMCLR_W<3> { + pub fn timclr(&mut self) -> TIMCLR_W { TIMCLR_W::new(self) } #[doc = "Bit 4 - Calendar Clear"] #[inline(always)] #[must_use] - pub fn calclr(&mut self) -> CALCLR_W<4> { + pub fn calclr(&mut self) -> CALCLR_W { CALCLR_W::new(self) } #[doc = "Bit 5 - Time and/or Date Free Running Error Clear"] #[inline(always)] #[must_use] - pub fn tderrclr(&mut self) -> TDERRCLR_W<5> { + pub fn tderrclr(&mut self) -> TDERRCLR_W { TDERRCLR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Status Clear Command Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sccr](index.html) module"] +#[doc = "Status Clear Command Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sccr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCCR_SPEC; impl crate::RegisterSpec for SCCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [sccr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`sccr::W`](W) writer structure"] impl crate::Writable for SCCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/sr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/sr.rs index f21aa31d..3804b8af 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ACKUPD` reader - Acknowledge for Update"] pub type ACKUPD_R = crate::BitReader; #[doc = "Acknowledge for Update\n\nValue on reset: 0"] @@ -38,12 +25,12 @@ impl ACKUPD_R { true => ACKUPDSELECT_A::UPDATE, } } - #[doc = "Checks if the value of the field is `FREERUN`"] + #[doc = "Time and calendar registers cannot be updated."] #[inline(always)] pub fn is_freerun(&self) -> bool { *self == ACKUPDSELECT_A::FREERUN } - #[doc = "Checks if the value of the field is `UPDATE`"] + #[doc = "Time and calendar registers can be updated."] #[inline(always)] pub fn is_update(&self) -> bool { *self == ACKUPDSELECT_A::UPDATE @@ -74,12 +61,12 @@ impl ALARM_R { true => ALARMSELECT_A::ALARMEVENT, } } - #[doc = "Checks if the value of the field is `NO_ALARMEVENT`"] + #[doc = "No alarm matching condition occurred."] #[inline(always)] pub fn is_no_alarmevent(&self) -> bool { *self == ALARMSELECT_A::NO_ALARMEVENT } - #[doc = "Checks if the value of the field is `ALARMEVENT`"] + #[doc = "An alarm matching condition has occurred."] #[inline(always)] pub fn is_alarmevent(&self) -> bool { *self == ALARMSELECT_A::ALARMEVENT @@ -110,12 +97,12 @@ impl SEC_R { true => SECSELECT_A::SECEVENT, } } - #[doc = "Checks if the value of the field is `NO_SECEVENT`"] + #[doc = "No second event has occurred since the last clear."] #[inline(always)] pub fn is_no_secevent(&self) -> bool { *self == SECSELECT_A::NO_SECEVENT } - #[doc = "Checks if the value of the field is `SECEVENT`"] + #[doc = "At least one second event has occurred since the last clear."] #[inline(always)] pub fn is_secevent(&self) -> bool { *self == SECSELECT_A::SECEVENT @@ -146,12 +133,12 @@ impl TIMEV_R { true => TIMEVSELECT_A::TIMEVENT, } } - #[doc = "Checks if the value of the field is `NO_TIMEVENT`"] + #[doc = "No time event has occurred since the last clear."] #[inline(always)] pub fn is_no_timevent(&self) -> bool { *self == TIMEVSELECT_A::NO_TIMEVENT } - #[doc = "Checks if the value of the field is `TIMEVENT`"] + #[doc = "At least one time event has occurred since the last clear."] #[inline(always)] pub fn is_timevent(&self) -> bool { *self == TIMEVSELECT_A::TIMEVENT @@ -182,12 +169,12 @@ impl CALEV_R { true => CALEVSELECT_A::CALEVENT, } } - #[doc = "Checks if the value of the field is `NO_CALEVENT`"] + #[doc = "No calendar event has occurred since the last clear."] #[inline(always)] pub fn is_no_calevent(&self) -> bool { *self == CALEVSELECT_A::NO_CALEVENT } - #[doc = "Checks if the value of the field is `CALEVENT`"] + #[doc = "At least one calendar event has occurred since the last clear."] #[inline(always)] pub fn is_calevent(&self) -> bool { *self == CALEVSELECT_A::CALEVENT @@ -218,12 +205,12 @@ impl TDERR_R { true => TDERRSELECT_A::ERR_TIMEDATE, } } - #[doc = "Checks if the value of the field is `CORRECT`"] + #[doc = "The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR)."] #[inline(always)] pub fn is_correct(&self) -> bool { *self == TDERRSELECT_A::CORRECT } - #[doc = "Checks if the value of the field is `ERR_TIMEDATE`"] + #[doc = "The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid."] #[inline(always)] pub fn is_err_timedate(&self) -> bool { *self == TDERRSELECT_A::ERR_TIMEDATE @@ -261,15 +248,13 @@ impl R { TDERR_R::new(((self.bits >> 5) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/timalr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/timalr.rs index a1fb9a95..c0b0cce5 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/timalr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/timalr.rs @@ -1,67 +1,35 @@ #[doc = "Register `TIMALR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIMALR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEC` reader - Second Alarm"] pub type SEC_R = crate::FieldReader; #[doc = "Field `SEC` writer - Second Alarm"] -pub type SEC_W<'a, const O: u8> = crate::FieldWriter<'a, TIMALR_SPEC, 7, O>; +pub type SEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SECEN` reader - Second Alarm Enable"] pub type SECEN_R = crate::BitReader; #[doc = "Field `SECEN` writer - Second Alarm Enable"] -pub type SECEN_W<'a, const O: u8> = crate::BitWriter<'a, TIMALR_SPEC, O>; +pub type SECEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MIN` reader - Minute Alarm"] pub type MIN_R = crate::FieldReader; #[doc = "Field `MIN` writer - Minute Alarm"] -pub type MIN_W<'a, const O: u8> = crate::FieldWriter<'a, TIMALR_SPEC, 7, O>; +pub type MIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `MINEN` reader - Minute Alarm Enable"] pub type MINEN_R = crate::BitReader; #[doc = "Field `MINEN` writer - Minute Alarm Enable"] -pub type MINEN_W<'a, const O: u8> = crate::BitWriter<'a, TIMALR_SPEC, O>; +pub type MINEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOUR` reader - Hour Alarm"] pub type HOUR_R = crate::FieldReader; #[doc = "Field `HOUR` writer - Hour Alarm"] -pub type HOUR_W<'a, const O: u8> = crate::FieldWriter<'a, TIMALR_SPEC, 6, O>; +pub type HOUR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `AMPM` reader - AM/PM Indicator"] pub type AMPM_R = crate::BitReader; #[doc = "Field `AMPM` writer - AM/PM Indicator"] -pub type AMPM_W<'a, const O: u8> = crate::BitWriter<'a, TIMALR_SPEC, O>; +pub type AMPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HOUREN` reader - Hour Alarm Enable"] pub type HOUREN_R = crate::BitReader; #[doc = "Field `HOUREN` writer - Hour Alarm Enable"] -pub type HOUREN_W<'a, const O: u8> = crate::BitWriter<'a, TIMALR_SPEC, O>; +pub type HOUREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Second Alarm"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bits 0:6 - Second Alarm"] #[inline(always)] #[must_use] - pub fn sec(&mut self) -> SEC_W<0> { + pub fn sec(&mut self) -> SEC_W { SEC_W::new(self) } #[doc = "Bit 7 - Second Alarm Enable"] #[inline(always)] #[must_use] - pub fn secen(&mut self) -> SECEN_W<7> { + pub fn secen(&mut self) -> SECEN_W { SECEN_W::new(self) } #[doc = "Bits 8:14 - Minute Alarm"] #[inline(always)] #[must_use] - pub fn min(&mut self) -> MIN_W<8> { + pub fn min(&mut self) -> MIN_W { MIN_W::new(self) } #[doc = "Bit 15 - Minute Alarm Enable"] #[inline(always)] #[must_use] - pub fn minen(&mut self) -> MINEN_W<15> { + pub fn minen(&mut self) -> MINEN_W { MINEN_W::new(self) } #[doc = "Bits 16:21 - Hour Alarm"] #[inline(always)] #[must_use] - pub fn hour(&mut self) -> HOUR_W<16> { + pub fn hour(&mut self) -> HOUR_W { HOUR_W::new(self) } #[doc = "Bit 22 - AM/PM Indicator"] #[inline(always)] #[must_use] - pub fn ampm(&mut self) -> AMPM_W<22> { + pub fn ampm(&mut self) -> AMPM_W { AMPM_W::new(self) } #[doc = "Bit 23 - Hour Alarm Enable"] #[inline(always)] #[must_use] - pub fn houren(&mut self) -> HOUREN_W<23> { + pub fn houren(&mut self) -> HOUREN_W { HOUREN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Time Alarm Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timalr](index.html) module"] +#[doc = "Time Alarm Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timalr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timalr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMALR_SPEC; impl crate::RegisterSpec for TIMALR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timalr::R](R) reader structure"] -impl crate::Readable for TIMALR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [timalr::W](W) writer structure"] +#[doc = "`read()` method returns [`timalr::R`](R) reader structure"] +impl crate::Readable for TIMALR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timalr::W`](W) writer structure"] impl crate::Writable for TIMALR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/timr.rs b/arch/cortex-m/samv71q21-pac/src/rtc/timr.rs index f8d80098..0548d847 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/timr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/timr.rs @@ -1,55 +1,23 @@ #[doc = "Register `TIMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TIMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SEC` reader - Current Second"] pub type SEC_R = crate::FieldReader; #[doc = "Field `SEC` writer - Current Second"] -pub type SEC_W<'a, const O: u8> = crate::FieldWriter<'a, TIMR_SPEC, 7, O>; +pub type SEC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `MIN` reader - Current Minute"] pub type MIN_R = crate::FieldReader; #[doc = "Field `MIN` writer - Current Minute"] -pub type MIN_W<'a, const O: u8> = crate::FieldWriter<'a, TIMR_SPEC, 7, O>; +pub type MIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HOUR` reader - Current Hour"] pub type HOUR_R = crate::FieldReader; #[doc = "Field `HOUR` writer - Current Hour"] -pub type HOUR_W<'a, const O: u8> = crate::FieldWriter<'a, TIMR_SPEC, 6, O>; +pub type HOUR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `AMPM` reader - Ante Meridiem Post Meridiem Indicator"] pub type AMPM_R = crate::BitReader; #[doc = "Field `AMPM` writer - Ante Meridiem Post Meridiem Indicator"] -pub type AMPM_W<'a, const O: u8> = crate::BitWriter<'a, TIMR_SPEC, O>; +pub type AMPM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - Current Second"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - Current Second"] #[inline(always)] #[must_use] - pub fn sec(&mut self) -> SEC_W<0> { + pub fn sec(&mut self) -> SEC_W { SEC_W::new(self) } #[doc = "Bits 8:14 - Current Minute"] #[inline(always)] #[must_use] - pub fn min(&mut self) -> MIN_W<8> { + pub fn min(&mut self) -> MIN_W { MIN_W::new(self) } #[doc = "Bits 16:21 - Current Hour"] #[inline(always)] #[must_use] - pub fn hour(&mut self) -> HOUR_W<16> { + pub fn hour(&mut self) -> HOUR_W { HOUR_W::new(self) } #[doc = "Bit 22 - Ante Meridiem Post Meridiem Indicator"] #[inline(always)] #[must_use] - pub fn ampm(&mut self) -> AMPM_W<22> { + pub fn ampm(&mut self) -> AMPM_W { AMPM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Time Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timr](index.html) module"] +#[doc = "Time Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TIMR_SPEC; impl crate::RegisterSpec for TIMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [timr::R](R) reader structure"] -impl crate::Readable for TIMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [timr::W](W) writer structure"] +#[doc = "`read()` method returns [`timr::R`](R) reader structure"] +impl crate::Readable for TIMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timr::W`](W) writer structure"] impl crate::Writable for TIMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtc/ver.rs b/arch/cortex-m/samv71q21-pac/src/rtc/ver.rs index a84881ab..1b499098 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtc/ver.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtc/ver.rs @@ -1,18 +1,5 @@ #[doc = "Register `VER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NVTIM` reader - Non-valid Time"] pub type NVTIM_R = crate::BitReader; #[doc = "Field `NVCAL` reader - Non-valid Calendar"] @@ -43,15 +30,13 @@ impl R { NVCALALR_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "Valid Entry Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ver](index.html) module"] +#[doc = "Valid Entry Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ver::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VER_SPEC; impl crate::RegisterSpec for VER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ver::R](R) reader structure"] -impl crate::Readable for VER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ver::R`](R) reader structure"] +impl crate::Readable for VER_SPEC {} #[doc = "`reset()` method sets VER to value 0"] impl crate::Resettable for VER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rtt.rs b/arch/cortex-m/samv71q21-pac/src/rtt.rs index a2ad1a9c..3c605a3c 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtt.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtt.rs @@ -10,19 +10,23 @@ pub struct RegisterBlock { #[doc = "0x0c - Status Register"] pub sr: SR, } -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "AR (rw) register accessor: an alias for `Reg`"] +#[doc = "AR (rw) register accessor: Alarm Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ar`] +module"] pub type AR = crate::Reg; #[doc = "Alarm Register"] pub mod ar; -#[doc = "VR (r) register accessor: an alias for `Reg`"] +#[doc = "VR (r) register accessor: Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`vr`] +module"] pub type VR = crate::Reg; #[doc = "Value Register"] pub mod vr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; diff --git a/arch/cortex-m/samv71q21-pac/src/rtt/ar.rs b/arch/cortex-m/samv71q21-pac/src/rtt/ar.rs index 559fc731..3a462ba6 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtt/ar.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtt/ar.rs @@ -1,43 +1,11 @@ #[doc = "Register `AR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `AR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALMV` reader - Alarm Value"] pub type ALMV_R = crate::FieldReader; #[doc = "Field `ALMV` writer - Alarm Value"] -pub type ALMV_W<'a, const O: u8> = crate::FieldWriter<'a, AR_SPEC, 32, O, u32>; +pub type ALMV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Alarm Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Alarm Value"] #[inline(always)] #[must_use] - pub fn almv(&mut self) -> ALMV_W<0> { + pub fn almv(&mut self) -> ALMV_W { ALMV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Alarm Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ar](index.html) module"] +#[doc = "Alarm Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ar::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct AR_SPEC; impl crate::RegisterSpec for AR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ar::R](R) reader structure"] -impl crate::Readable for AR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ar::W](W) writer structure"] +#[doc = "`read()` method returns [`ar::R`](R) reader structure"] +impl crate::Readable for AR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ar::W`](W) writer structure"] impl crate::Writable for AR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtt/mr.rs b/arch/cortex-m/samv71q21-pac/src/rtt/mr.rs index 22facbdb..20404fb2 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtt/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtt/mr.rs @@ -1,63 +1,31 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RTPRES` reader - Real-time Timer Prescaler Value"] pub type RTPRES_R = crate::FieldReader; #[doc = "Field `RTPRES` writer - Real-time Timer Prescaler Value"] -pub type RTPRES_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 16, O, u16>; +pub type RTPRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `ALMIEN` reader - Alarm Interrupt Enable"] pub type ALMIEN_R = crate::BitReader; #[doc = "Field `ALMIEN` writer - Alarm Interrupt Enable"] -pub type ALMIEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type ALMIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTTINCIEN` reader - Real-time Timer Increment Interrupt Enable"] pub type RTTINCIEN_R = crate::BitReader; #[doc = "Field `RTTINCIEN` writer - Real-time Timer Increment Interrupt Enable"] -pub type RTTINCIEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RTTINCIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTTRST` reader - Real-time Timer Restart"] pub type RTTRST_R = crate::BitReader; #[doc = "Field `RTTRST` writer - Real-time Timer Restart"] -pub type RTTRST_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RTTRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTTDIS` reader - Real-time Timer Disable"] pub type RTTDIS_R = crate::BitReader; #[doc = "Field `RTTDIS` writer - Real-time Timer Disable"] -pub type RTTDIS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RTTDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTC1HZ` reader - Real-Time Clock 1Hz Clock Selection"] pub type RTC1HZ_R = crate::BitReader; #[doc = "Field `RTC1HZ` writer - Real-Time Clock 1Hz Clock Selection"] -pub type RTC1HZ_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type RTC1HZ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:15 - Real-time Timer Prescaler Value"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bits 0:15 - Real-time Timer Prescaler Value"] #[inline(always)] #[must_use] - pub fn rtpres(&mut self) -> RTPRES_W<0> { + pub fn rtpres(&mut self) -> RTPRES_W { RTPRES_W::new(self) } #[doc = "Bit 16 - Alarm Interrupt Enable"] #[inline(always)] #[must_use] - pub fn almien(&mut self) -> ALMIEN_W<16> { + pub fn almien(&mut self) -> ALMIEN_W { ALMIEN_W::new(self) } #[doc = "Bit 17 - Real-time Timer Increment Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rttincien(&mut self) -> RTTINCIEN_W<17> { + pub fn rttincien(&mut self) -> RTTINCIEN_W { RTTINCIEN_W::new(self) } #[doc = "Bit 18 - Real-time Timer Restart"] #[inline(always)] #[must_use] - pub fn rttrst(&mut self) -> RTTRST_W<18> { + pub fn rttrst(&mut self) -> RTTRST_W { RTTRST_W::new(self) } #[doc = "Bit 20 - Real-time Timer Disable"] #[inline(always)] #[must_use] - pub fn rttdis(&mut self) -> RTTDIS_W<20> { + pub fn rttdis(&mut self) -> RTTDIS_W { RTTDIS_W::new(self) } #[doc = "Bit 24 - Real-Time Clock 1Hz Clock Selection"] #[inline(always)] #[must_use] - pub fn rtc1hz(&mut self) -> RTC1HZ_W<24> { + pub fn rtc1hz(&mut self) -> RTC1HZ_W { RTC1HZ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/rtt/sr.rs b/arch/cortex-m/samv71q21-pac/src/rtt/sr.rs index 49718c79..6de8e39a 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtt/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtt/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ALMS` reader - Real-time Alarm Status (cleared on read)"] pub type ALMS_R = crate::BitReader; #[doc = "Field `RTTINC` reader - Prescaler Roll-over Status (cleared on read)"] @@ -29,15 +16,13 @@ impl R { RTTINC_R::new(((self.bits >> 1) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/rtt/vr.rs b/arch/cortex-m/samv71q21-pac/src/rtt/vr.rs index 270a1cd7..c1977a5f 100644 --- a/arch/cortex-m/samv71q21-pac/src/rtt/vr.rs +++ b/arch/cortex-m/samv71q21-pac/src/rtt/vr.rs @@ -1,18 +1,5 @@ #[doc = "Register `VR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CRTV` reader - Current Real-time Value"] pub type CRTV_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CRTV_R::new(self.bits) } } -#[doc = "Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vr](index.html) module"] +#[doc = "Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct VR_SPEC; impl crate::RegisterSpec for VR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [vr::R](R) reader structure"] -impl crate::Readable for VR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`vr::R`](R) reader structure"] +impl crate::Readable for VR_SPEC {} #[doc = "`reset()` method sets VR to value 0"] impl crate::Resettable for VR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/scn_scb.rs b/arch/cortex-m/samv71q21-pac/src/scn_scb.rs index 6649e9cd..95df2358 100644 --- a/arch/cortex-m/samv71q21-pac/src/scn_scb.rs +++ b/arch/cortex-m/samv71q21-pac/src/scn_scb.rs @@ -7,11 +7,13 @@ pub struct RegisterBlock { #[doc = "0x08 - Auxiliary Control Register"] pub actlr: ACTLR, } -#[doc = "ICTR (r) register accessor: an alias for `Reg`"] +#[doc = "ICTR (r) register accessor: Interrupt Controller Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ictr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ictr`] +module"] pub type ICTR = crate::Reg; #[doc = "Interrupt Controller Type Register"] pub mod ictr; -#[doc = "ACTLR (rw) register accessor: an alias for `Reg`"] +#[doc = "ACTLR (rw) register accessor: Auxiliary Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`actlr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`actlr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`actlr`] +module"] pub type ACTLR = crate::Reg; #[doc = "Auxiliary Control Register"] pub mod actlr; diff --git a/arch/cortex-m/samv71q21-pac/src/scn_scb/actlr.rs b/arch/cortex-m/samv71q21-pac/src/scn_scb/actlr.rs index 01deab23..53762894 100644 --- a/arch/cortex-m/samv71q21-pac/src/scn_scb/actlr.rs +++ b/arch/cortex-m/samv71q21-pac/src/scn_scb/actlr.rs @@ -1,87 +1,55 @@ #[doc = "Register `ACTLR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `ACTLR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DISFOLD` reader - Disables folding of IT instructions"] pub type DISFOLD_R = crate::BitReader; #[doc = "Field `DISFOLD` writer - Disables folding of IT instructions"] -pub type DISFOLD_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISFOLD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FPEXCODIS` reader - Disables FPU exception outputs"] pub type FPEXCODIS_R = crate::BitReader; #[doc = "Field `FPEXCODIS` writer - Disables FPU exception outputs"] -pub type FPEXCODIS_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type FPEXCODIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISRAMODE` reader - Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions"] pub type DISRAMODE_R = crate::BitReader; #[doc = "Field `DISRAMODE` writer - Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions"] -pub type DISRAMODE_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISRAMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISITMATBFLUSH` reader - Disables ITM and DWT ATB flush"] pub type DISITMATBFLUSH_R = crate::BitReader; #[doc = "Field `DISITMATBFLUSH` writer - Disables ITM and DWT ATB flush"] -pub type DISITMATBFLUSH_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISITMATBFLUSH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISBTACREAD` reader - "] pub type DISBTACREAD_R = crate::BitReader; #[doc = "Field `DISBTACREAD` writer - "] -pub type DISBTACREAD_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISBTACREAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISBTACALLOC` reader - "] pub type DISBTACALLOC_R = crate::BitReader; #[doc = "Field `DISBTACALLOC` writer - "] -pub type DISBTACALLOC_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISBTACALLOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCRITAXIRUR` reader - "] pub type DISCRITAXIRUR_R = crate::BitReader; #[doc = "Field `DISCRITAXIRUR` writer - "] -pub type DISCRITAXIRUR_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISCRITAXIRUR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISDI` reader - "] pub type DISDI_R = crate::FieldReader; #[doc = "Field `DISDI` writer - "] -pub type DISDI_W<'a, const O: u8> = crate::FieldWriter<'a, ACTLR_SPEC, 5, O>; +pub type DISDI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DISISSCH1` reader - "] pub type DISISSCH1_R = crate::FieldReader; #[doc = "Field `DISISSCH1` writer - "] -pub type DISISSCH1_W<'a, const O: u8> = crate::FieldWriter<'a, ACTLR_SPEC, 5, O>; +pub type DISISSCH1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DISDYNADD` reader - Disables dynamic allocation of ADD and SUB instructions"] pub type DISDYNADD_R = crate::BitReader; #[doc = "Field `DISDYNADD` writer - Disables dynamic allocation of ADD and SUB instructions"] -pub type DISDYNADD_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISDYNADD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISCRITAXIRUW` reader - Disable critical AXI read-under-write"] pub type DISCRITAXIRUW_R = crate::BitReader; #[doc = "Field `DISCRITAXIRUW` writer - Disable critical AXI read-under-write"] -pub type DISCRITAXIRUW_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISCRITAXIRUW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DISFPUISSOPT` reader - Disables dynamic allocation of ADD and SUB instructions"] pub type DISFPUISSOPT_R = crate::BitReader; #[doc = "Field `DISFPUISSOPT` writer - Disables dynamic allocation of ADD and SUB instructions"] -pub type DISFPUISSOPT_W<'a, const O: u8> = crate::BitWriter<'a, ACTLR_SPEC, O>; +pub type DISFPUISSOPT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 2 - Disables folding of IT instructions"] #[inline(always)] @@ -148,94 +116,91 @@ impl W { #[doc = "Bit 2 - Disables folding of IT instructions"] #[inline(always)] #[must_use] - pub fn disfold(&mut self) -> DISFOLD_W<2> { + pub fn disfold(&mut self) -> DISFOLD_W { DISFOLD_W::new(self) } #[doc = "Bit 10 - Disables FPU exception outputs"] #[inline(always)] #[must_use] - pub fn fpexcodis(&mut self) -> FPEXCODIS_W<10> { + pub fn fpexcodis(&mut self) -> FPEXCODIS_W { FPEXCODIS_W::new(self) } #[doc = "Bit 11 - Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions"] #[inline(always)] #[must_use] - pub fn disramode(&mut self) -> DISRAMODE_W<11> { + pub fn disramode(&mut self) -> DISRAMODE_W { DISRAMODE_W::new(self) } #[doc = "Bit 12 - Disables ITM and DWT ATB flush"] #[inline(always)] #[must_use] - pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W<12> { + pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W { DISITMATBFLUSH_W::new(self) } #[doc = "Bit 13"] #[inline(always)] #[must_use] - pub fn disbtacread(&mut self) -> DISBTACREAD_W<13> { + pub fn disbtacread(&mut self) -> DISBTACREAD_W { DISBTACREAD_W::new(self) } #[doc = "Bit 14"] #[inline(always)] #[must_use] - pub fn disbtacalloc(&mut self) -> DISBTACALLOC_W<14> { + pub fn disbtacalloc(&mut self) -> DISBTACALLOC_W { DISBTACALLOC_W::new(self) } #[doc = "Bit 15"] #[inline(always)] #[must_use] - pub fn discritaxirur(&mut self) -> DISCRITAXIRUR_W<15> { + pub fn discritaxirur(&mut self) -> DISCRITAXIRUR_W { DISCRITAXIRUR_W::new(self) } #[doc = "Bits 16:20"] #[inline(always)] #[must_use] - pub fn disdi(&mut self) -> DISDI_W<16> { + pub fn disdi(&mut self) -> DISDI_W { DISDI_W::new(self) } #[doc = "Bits 21:25"] #[inline(always)] #[must_use] - pub fn disissch1(&mut self) -> DISISSCH1_W<21> { + pub fn disissch1(&mut self) -> DISISSCH1_W { DISISSCH1_W::new(self) } #[doc = "Bit 26 - Disables dynamic allocation of ADD and SUB instructions"] #[inline(always)] #[must_use] - pub fn disdynadd(&mut self) -> DISDYNADD_W<26> { + pub fn disdynadd(&mut self) -> DISDYNADD_W { DISDYNADD_W::new(self) } #[doc = "Bit 27 - Disable critical AXI read-under-write"] #[inline(always)] #[must_use] - pub fn discritaxiruw(&mut self) -> DISCRITAXIRUW_W<27> { + pub fn discritaxiruw(&mut self) -> DISCRITAXIRUW_W { DISCRITAXIRUW_W::new(self) } #[doc = "Bit 28 - Disables dynamic allocation of ADD and SUB instructions"] #[inline(always)] #[must_use] - pub fn disfpuissopt(&mut self) -> DISFPUISSOPT_W<28> { + pub fn disfpuissopt(&mut self) -> DISFPUISSOPT_W { DISFPUISSOPT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Auxiliary Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [actlr](index.html) module"] +#[doc = "Auxiliary Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`actlr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`actlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ACTLR_SPEC; impl crate::RegisterSpec for ACTLR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [actlr::R](R) reader structure"] -impl crate::Readable for ACTLR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [actlr::W](W) writer structure"] +#[doc = "`read()` method returns [`actlr::R`](R) reader structure"] +impl crate::Readable for ACTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`actlr::W`](W) writer structure"] impl crate::Writable for ACTLR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/scn_scb/ictr.rs b/arch/cortex-m/samv71q21-pac/src/scn_scb/ictr.rs index 7d3d6f6c..94097b52 100644 --- a/arch/cortex-m/samv71q21-pac/src/scn_scb/ictr.rs +++ b/arch/cortex-m/samv71q21-pac/src/scn_scb/ictr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ICTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `INTLINESNUM` reader - Total number of interrupt lines supported by an implementation, defined in groups of 32"] pub type INTLINESNUM_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { INTLINESNUM_R::new((self.bits & 0x0f) as u8) } } -#[doc = "Interrupt Controller Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ictr](index.html) module"] +#[doc = "Interrupt Controller Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ictr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ICTR_SPEC; impl crate::RegisterSpec for ICTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ictr::R](R) reader structure"] -impl crate::Readable for ICTR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`ictr::R`](R) reader structure"] +impl crate::Readable for ICTR_SPEC {} #[doc = "`reset()` method sets ICTR to value 0"] impl crate::Resettable for ICTR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/smc.rs b/arch/cortex-m/samv71q21-pac/src/smc.rs index 107c5ec0..f3f53fa4 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc.rs @@ -21,23 +21,28 @@ pub use self::smc_cs_number::SMC_CS_NUMBER; #[doc = r"Cluster"] #[doc = "SMC Setup Register"] pub mod smc_cs_number; -#[doc = "OCMS (rw) register accessor: an alias for `Reg`"] +#[doc = "OCMS (rw) register accessor: SMC Off-Chip Memory Scrambling Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ocms::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ocms::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ocms`] +module"] pub type OCMS = crate::Reg; #[doc = "SMC Off-Chip Memory Scrambling Register"] pub mod ocms; -#[doc = "KEY1 (w) register accessor: an alias for `Reg`"] +#[doc = "KEY1 (w) register accessor: SMC Off-Chip Memory Scrambling KEY1 Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key1::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`key1`] +module"] pub type KEY1 = crate::Reg; #[doc = "SMC Off-Chip Memory Scrambling KEY1 Register"] pub mod key1; -#[doc = "KEY2 (w) register accessor: an alias for `Reg`"] +#[doc = "KEY2 (w) register accessor: SMC Off-Chip Memory Scrambling KEY2 Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key2::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`key2`] +module"] pub type KEY2 = crate::Reg; #[doc = "SMC Off-Chip Memory Scrambling KEY2 Register"] pub mod key2; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: SMC Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "SMC Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: SMC Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "SMC Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/smc/key1.rs b/arch/cortex-m/samv71q21-pac/src/smc/key1.rs index c764ebb1..6fc23f85 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/key1.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/key1.rs @@ -1,48 +1,28 @@ #[doc = "Register `KEY1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `KEY1` writer - Off-Chip Memory Scrambling (OCMS) Key Part 1"] -pub type KEY1_W<'a, const O: u8> = crate::FieldWriter<'a, KEY1_SPEC, 32, O, u32>; +pub type KEY1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Off-Chip Memory Scrambling (OCMS) Key Part 1"] #[inline(always)] #[must_use] - pub fn key1(&mut self) -> KEY1_W<0> { + pub fn key1(&mut self) -> KEY1_W { KEY1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Off-Chip Memory Scrambling KEY1 Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key1](index.html) module"] +#[doc = "SMC Off-Chip Memory Scrambling KEY1 Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KEY1_SPEC; impl crate::RegisterSpec for KEY1_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [key1::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`key1::W`](W) writer structure"] impl crate::Writable for KEY1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/key2.rs b/arch/cortex-m/samv71q21-pac/src/smc/key2.rs index 1b20d9d3..78aa97db 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/key2.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/key2.rs @@ -1,48 +1,28 @@ #[doc = "Register `KEY2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `KEY2` writer - Off-Chip Memory Scrambling (OCMS) Key Part 2"] -pub type KEY2_W<'a, const O: u8> = crate::FieldWriter<'a, KEY2_SPEC, 32, O, u32>; +pub type KEY2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Off-Chip Memory Scrambling (OCMS) Key Part 2"] #[inline(always)] #[must_use] - pub fn key2(&mut self) -> KEY2_W<0> { + pub fn key2(&mut self) -> KEY2_W { KEY2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Off-Chip Memory Scrambling KEY2 Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [key2](index.html) module"] +#[doc = "SMC Off-Chip Memory Scrambling KEY2 Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`key2::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct KEY2_SPEC; impl crate::RegisterSpec for KEY2_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [key2::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`key2::W`](W) writer structure"] impl crate::Writable for KEY2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/ocms.rs b/arch/cortex-m/samv71q21-pac/src/smc/ocms.rs index c94f0a8f..4f4b4ed4 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/ocms.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/ocms.rs @@ -1,59 +1,27 @@ #[doc = "Register `OCMS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `OCMS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMSE` reader - Static Memory Controller Scrambling Enable"] pub type SMSE_R = crate::BitReader; #[doc = "Field `SMSE` writer - Static Memory Controller Scrambling Enable"] -pub type SMSE_W<'a, const O: u8> = crate::BitWriter<'a, OCMS_SPEC, O>; +pub type SMSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS0SE` reader - Chip Select (x = 0 to 3) Scrambling Enable"] pub type CS0SE_R = crate::BitReader; #[doc = "Field `CS0SE` writer - Chip Select (x = 0 to 3) Scrambling Enable"] -pub type CS0SE_W<'a, const O: u8> = crate::BitWriter<'a, OCMS_SPEC, O>; +pub type CS0SE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS1SE` reader - Chip Select (x = 0 to 3) Scrambling Enable"] pub type CS1SE_R = crate::BitReader; #[doc = "Field `CS1SE` writer - Chip Select (x = 0 to 3) Scrambling Enable"] -pub type CS1SE_W<'a, const O: u8> = crate::BitWriter<'a, OCMS_SPEC, O>; +pub type CS1SE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS2SE` reader - Chip Select (x = 0 to 3) Scrambling Enable"] pub type CS2SE_R = crate::BitReader; #[doc = "Field `CS2SE` writer - Chip Select (x = 0 to 3) Scrambling Enable"] -pub type CS2SE_W<'a, const O: u8> = crate::BitWriter<'a, OCMS_SPEC, O>; +pub type CS2SE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CS3SE` reader - Chip Select (x = 0 to 3) Scrambling Enable"] pub type CS3SE_R = crate::BitReader; #[doc = "Field `CS3SE` writer - Chip Select (x = 0 to 3) Scrambling Enable"] -pub type CS3SE_W<'a, const O: u8> = crate::BitWriter<'a, OCMS_SPEC, O>; +pub type CS3SE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Static Memory Controller Scrambling Enable"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bit 0 - Static Memory Controller Scrambling Enable"] #[inline(always)] #[must_use] - pub fn smse(&mut self) -> SMSE_W<0> { + pub fn smse(&mut self) -> SMSE_W { SMSE_W::new(self) } #[doc = "Bit 8 - Chip Select (x = 0 to 3) Scrambling Enable"] #[inline(always)] #[must_use] - pub fn cs0se(&mut self) -> CS0SE_W<8> { + pub fn cs0se(&mut self) -> CS0SE_W { CS0SE_W::new(self) } #[doc = "Bit 9 - Chip Select (x = 0 to 3) Scrambling Enable"] #[inline(always)] #[must_use] - pub fn cs1se(&mut self) -> CS1SE_W<9> { + pub fn cs1se(&mut self) -> CS1SE_W { CS1SE_W::new(self) } #[doc = "Bit 10 - Chip Select (x = 0 to 3) Scrambling Enable"] #[inline(always)] #[must_use] - pub fn cs2se(&mut self) -> CS2SE_W<10> { + pub fn cs2se(&mut self) -> CS2SE_W { CS2SE_W::new(self) } #[doc = "Bit 11 - Chip Select (x = 0 to 3) Scrambling Enable"] #[inline(always)] #[must_use] - pub fn cs3se(&mut self) -> CS3SE_W<11> { + pub fn cs3se(&mut self) -> CS3SE_W { CS3SE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Off-Chip Memory Scrambling Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ocms](index.html) module"] +#[doc = "SMC Off-Chip Memory Scrambling Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ocms::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ocms::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OCMS_SPEC; impl crate::RegisterSpec for OCMS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ocms::R](R) reader structure"] -impl crate::Readable for OCMS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ocms::W](W) writer structure"] +#[doc = "`read()` method returns [`ocms::R`](R) reader structure"] +impl crate::Readable for OCMS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ocms::W`](W) writer structure"] impl crate::Writable for OCMS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number.rs b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number.rs index 5604e141..88ee2b96 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number.rs @@ -10,19 +10,23 @@ pub struct SMC_CS_NUMBER { #[doc = "0x0c - SMC Mode Register"] pub mode: MODE, } -#[doc = "SETUP (rw) register accessor: an alias for `Reg`"] +#[doc = "SETUP (rw) register accessor: SMC Setup Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`setup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`setup`] +module"] pub type SETUP = crate::Reg; #[doc = "SMC Setup Register"] pub mod setup; -#[doc = "PULSE (rw) register accessor: an alias for `Reg`"] +#[doc = "PULSE (rw) register accessor: SMC Pulse Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`pulse`] +module"] pub type PULSE = crate::Reg; #[doc = "SMC Pulse Register"] pub mod pulse; -#[doc = "CYCLE (rw) register accessor: an alias for `Reg`"] +#[doc = "CYCLE (rw) register accessor: SMC Cycle Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cycle`] +module"] pub type CYCLE = crate::Reg; #[doc = "SMC Cycle Register"] pub mod cycle; -#[doc = "MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "MODE (rw) register accessor: SMC Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mode`] +module"] pub type MODE = crate::Reg; #[doc = "SMC Mode Register"] pub mod mode; diff --git a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/cycle.rs b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/cycle.rs index 839be7be..df994e15 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/cycle.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/cycle.rs @@ -1,47 +1,15 @@ #[doc = "Register `CYCLE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CYCLE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NWE_CYCLE` reader - Total Write Cycle Length"] pub type NWE_CYCLE_R = crate::FieldReader; #[doc = "Field `NWE_CYCLE` writer - Total Write Cycle Length"] -pub type NWE_CYCLE_W<'a, const O: u8> = crate::FieldWriter<'a, CYCLE_SPEC, 9, O, u16>; +pub type NWE_CYCLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `NRD_CYCLE` reader - Total Read Cycle Length"] pub type NRD_CYCLE_R = crate::FieldReader; #[doc = "Field `NRD_CYCLE` writer - Total Read Cycle Length"] -pub type NRD_CYCLE_W<'a, const O: u8> = crate::FieldWriter<'a, CYCLE_SPEC, 9, O, u16>; +pub type NRD_CYCLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; impl R { #[doc = "Bits 0:8 - Total Write Cycle Length"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:8 - Total Write Cycle Length"] #[inline(always)] #[must_use] - pub fn nwe_cycle(&mut self) -> NWE_CYCLE_W<0> { + pub fn nwe_cycle(&mut self) -> NWE_CYCLE_W { NWE_CYCLE_W::new(self) } #[doc = "Bits 16:24 - Total Read Cycle Length"] #[inline(always)] #[must_use] - pub fn nrd_cycle(&mut self) -> NRD_CYCLE_W<16> { + pub fn nrd_cycle(&mut self) -> NRD_CYCLE_W { NRD_CYCLE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Cycle Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cycle](index.html) module"] +#[doc = "SMC Cycle Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CYCLE_SPEC; impl crate::RegisterSpec for CYCLE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cycle::R](R) reader structure"] -impl crate::Readable for CYCLE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cycle::W](W) writer structure"] +#[doc = "`read()` method returns [`cycle::R`](R) reader structure"] +impl crate::Readable for CYCLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cycle::W`](W) writer structure"] impl crate::Writable for CYCLE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/mode.rs b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/mode.rs index 8dcae6fc..1a06a700 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/mode.rs @@ -1,47 +1,15 @@ #[doc = "Register `MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `READ_MODE` reader - Read Mode"] pub type READ_MODE_R = crate::BitReader; #[doc = "Field `READ_MODE` writer - Read Mode"] -pub type READ_MODE_W<'a, const O: u8> = crate::BitWriter<'a, MODE_SPEC, O>; +pub type READ_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRITE_MODE` reader - Write Mode"] pub type WRITE_MODE_R = crate::BitReader; #[doc = "Field `WRITE_MODE` writer - Write Mode"] -pub type WRITE_MODE_W<'a, const O: u8> = crate::BitWriter<'a, MODE_SPEC, O>; +pub type WRITE_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EXNW_MODE` reader - NWAIT Mode"] pub type EXNW_MODE_R = crate::FieldReader; #[doc = "NWAIT Mode\n\nValue on reset: 0"] @@ -75,38 +43,42 @@ impl EXNW_MODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "Disabled-The NWAIT input signal is ignored on the corresponding chip select."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == EXNW_MODESELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `FROZEN`"] + #[doc = "Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped."] #[inline(always)] pub fn is_frozen(&self) -> bool { *self == EXNW_MODESELECT_A::FROZEN } - #[doc = "Checks if the value of the field is `READY`"] + #[doc = "Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high."] #[inline(always)] pub fn is_ready(&self) -> bool { *self == EXNW_MODESELECT_A::READY } } #[doc = "Field `EXNW_MODE` writer - NWAIT Mode"] -pub type EXNW_MODE_W<'a, const O: u8> = crate::FieldWriter<'a, MODE_SPEC, 2, O, EXNW_MODESELECT_A>; -impl<'a, const O: u8> EXNW_MODE_W<'a, O> { +pub type EXNW_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, EXNW_MODESELECT_A>; +impl<'a, REG, const O: u8> EXNW_MODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Disabled-The NWAIT input signal is ignored on the corresponding chip select."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(EXNW_MODESELECT_A::DISABLED) } #[doc = "Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped."] #[inline(always)] - pub fn frozen(self) -> &'a mut W { + pub fn frozen(self) -> &'a mut crate::W { self.variant(EXNW_MODESELECT_A::FROZEN) } #[doc = "Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high."] #[inline(always)] - pub fn ready(self) -> &'a mut W { + pub fn ready(self) -> &'a mut crate::W { self.variant(EXNW_MODESELECT_A::READY) } } @@ -135,28 +107,31 @@ impl BAT_R { true => BATSELECT_A::BYTE_WRITE, } } - #[doc = "Checks if the value of the field is `BYTE_SELECT`"] + #[doc = "Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1."] #[inline(always)] pub fn is_byte_select(&self) -> bool { *self == BATSELECT_A::BYTE_SELECT } - #[doc = "Checks if the value of the field is `BYTE_WRITE`"] + #[doc = "Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD."] #[inline(always)] pub fn is_byte_write(&self) -> bool { *self == BATSELECT_A::BYTE_WRITE } } #[doc = "Field `BAT` writer - Byte Access Type"] -pub type BAT_W<'a, const O: u8> = crate::BitWriter<'a, MODE_SPEC, O, BATSELECT_A>; -impl<'a, const O: u8> BAT_W<'a, O> { +pub type BAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BATSELECT_A>; +impl<'a, REG, const O: u8> BAT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1."] #[inline(always)] - pub fn byte_select(self) -> &'a mut W { + pub fn byte_select(self) -> &'a mut crate::W { self.variant(BATSELECT_A::BYTE_SELECT) } #[doc = "Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD."] #[inline(always)] - pub fn byte_write(self) -> &'a mut W { + pub fn byte_write(self) -> &'a mut crate::W { self.variant(BATSELECT_A::BYTE_WRITE) } } @@ -185,43 +160,46 @@ impl DBW_R { true => DBWSELECT_A::_16_BIT, } } - #[doc = "Checks if the value of the field is `_8_BIT`"] + #[doc = "8-bit Data Bus"] #[inline(always)] pub fn is_8_bit(&self) -> bool { *self == DBWSELECT_A::_8_BIT } - #[doc = "Checks if the value of the field is `_16_BIT`"] + #[doc = "16-bit Data Bus"] #[inline(always)] pub fn is_16_bit(&self) -> bool { *self == DBWSELECT_A::_16_BIT } } #[doc = "Field `DBW` writer - Data Bus Width"] -pub type DBW_W<'a, const O: u8> = crate::BitWriter<'a, MODE_SPEC, O, DBWSELECT_A>; -impl<'a, const O: u8> DBW_W<'a, O> { +pub type DBW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DBWSELECT_A>; +impl<'a, REG, const O: u8> DBW_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "8-bit Data Bus"] #[inline(always)] - pub fn _8_bit(self) -> &'a mut W { + pub fn _8_bit(self) -> &'a mut crate::W { self.variant(DBWSELECT_A::_8_BIT) } #[doc = "16-bit Data Bus"] #[inline(always)] - pub fn _16_bit(self) -> &'a mut W { + pub fn _16_bit(self) -> &'a mut crate::W { self.variant(DBWSELECT_A::_16_BIT) } } #[doc = "Field `TDF_CYCLES` reader - Data Float Time"] pub type TDF_CYCLES_R = crate::FieldReader; #[doc = "Field `TDF_CYCLES` writer - Data Float Time"] -pub type TDF_CYCLES_W<'a, const O: u8> = crate::FieldWriter<'a, MODE_SPEC, 4, O>; +pub type TDF_CYCLES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TDF_MODE` reader - TDF Optimization"] pub type TDF_MODE_R = crate::BitReader; #[doc = "Field `TDF_MODE` writer - TDF Optimization"] -pub type TDF_MODE_W<'a, const O: u8> = crate::BitWriter<'a, MODE_SPEC, O>; +pub type TDF_MODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PMEN` reader - Page Mode Enabled"] pub type PMEN_R = crate::BitReader; #[doc = "Field `PMEN` writer - Page Mode Enabled"] -pub type PMEN_W<'a, const O: u8> = crate::BitWriter<'a, MODE_SPEC, O>; +pub type PMEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PS` reader - Page Size"] pub type PS_R = crate::FieldReader; #[doc = "Page Size\n\nValue on reset: 0"] @@ -258,48 +236,52 @@ impl PS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_4_BYTE`"] + #[doc = "4-byte page"] #[inline(always)] pub fn is_4_byte(&self) -> bool { *self == PSSELECT_A::_4_BYTE } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8-byte page"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == PSSELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16-byte page"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == PSSELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32-byte page"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == PSSELECT_A::_32_BYTE } } #[doc = "Field `PS` writer - Page Size"] -pub type PS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MODE_SPEC, 2, O, PSSELECT_A>; -impl<'a, const O: u8> PS_W<'a, O> { +pub type PS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, PSSELECT_A>; +impl<'a, REG, const O: u8> PS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "4-byte page"] #[inline(always)] - pub fn _4_byte(self) -> &'a mut W { + pub fn _4_byte(self) -> &'a mut crate::W { self.variant(PSSELECT_A::_4_BYTE) } #[doc = "8-byte page"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(PSSELECT_A::_8_BYTE) } #[doc = "16-byte page"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(PSSELECT_A::_16_BYTE) } #[doc = "32-byte page"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(PSSELECT_A::_32_BYTE) } } @@ -354,76 +336,73 @@ impl W { #[doc = "Bit 0 - Read Mode"] #[inline(always)] #[must_use] - pub fn read_mode(&mut self) -> READ_MODE_W<0> { + pub fn read_mode(&mut self) -> READ_MODE_W { READ_MODE_W::new(self) } #[doc = "Bit 1 - Write Mode"] #[inline(always)] #[must_use] - pub fn write_mode(&mut self) -> WRITE_MODE_W<1> { + pub fn write_mode(&mut self) -> WRITE_MODE_W { WRITE_MODE_W::new(self) } #[doc = "Bits 4:5 - NWAIT Mode"] #[inline(always)] #[must_use] - pub fn exnw_mode(&mut self) -> EXNW_MODE_W<4> { + pub fn exnw_mode(&mut self) -> EXNW_MODE_W { EXNW_MODE_W::new(self) } #[doc = "Bit 8 - Byte Access Type"] #[inline(always)] #[must_use] - pub fn bat(&mut self) -> BAT_W<8> { + pub fn bat(&mut self) -> BAT_W { BAT_W::new(self) } #[doc = "Bit 12 - Data Bus Width"] #[inline(always)] #[must_use] - pub fn dbw(&mut self) -> DBW_W<12> { + pub fn dbw(&mut self) -> DBW_W { DBW_W::new(self) } #[doc = "Bits 16:19 - Data Float Time"] #[inline(always)] #[must_use] - pub fn tdf_cycles(&mut self) -> TDF_CYCLES_W<16> { + pub fn tdf_cycles(&mut self) -> TDF_CYCLES_W { TDF_CYCLES_W::new(self) } #[doc = "Bit 20 - TDF Optimization"] #[inline(always)] #[must_use] - pub fn tdf_mode(&mut self) -> TDF_MODE_W<20> { + pub fn tdf_mode(&mut self) -> TDF_MODE_W { TDF_MODE_W::new(self) } #[doc = "Bit 24 - Page Mode Enabled"] #[inline(always)] #[must_use] - pub fn pmen(&mut self) -> PMEN_W<24> { + pub fn pmen(&mut self) -> PMEN_W { PMEN_W::new(self) } #[doc = "Bits 28:29 - Page Size"] #[inline(always)] #[must_use] - pub fn ps(&mut self) -> PS_W<28> { + pub fn ps(&mut self) -> PS_W { PS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mode](index.html) module"] +#[doc = "SMC Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MODE_SPEC; impl crate::RegisterSpec for MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mode::R](R) reader structure"] -impl crate::Readable for MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mode::W](W) writer structure"] +#[doc = "`read()` method returns [`mode::R`](R) reader structure"] +impl crate::Readable for MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"] impl crate::Writable for MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/pulse.rs b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/pulse.rs index 87b2a191..2a12f9f7 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/pulse.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/pulse.rs @@ -1,55 +1,23 @@ #[doc = "Register `PULSE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `PULSE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NWE_PULSE` reader - NWE Pulse Length"] pub type NWE_PULSE_R = crate::FieldReader; #[doc = "Field `NWE_PULSE` writer - NWE Pulse Length"] -pub type NWE_PULSE_W<'a, const O: u8> = crate::FieldWriter<'a, PULSE_SPEC, 7, O>; +pub type NWE_PULSE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `NCS_WR_PULSE` reader - NCS Pulse Length in WRITE Access"] pub type NCS_WR_PULSE_R = crate::FieldReader; #[doc = "Field `NCS_WR_PULSE` writer - NCS Pulse Length in WRITE Access"] -pub type NCS_WR_PULSE_W<'a, const O: u8> = crate::FieldWriter<'a, PULSE_SPEC, 7, O>; +pub type NCS_WR_PULSE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `NRD_PULSE` reader - NRD Pulse Length"] pub type NRD_PULSE_R = crate::FieldReader; #[doc = "Field `NRD_PULSE` writer - NRD Pulse Length"] -pub type NRD_PULSE_W<'a, const O: u8> = crate::FieldWriter<'a, PULSE_SPEC, 7, O>; +pub type NRD_PULSE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `NCS_RD_PULSE` reader - NCS Pulse Length in READ Access"] pub type NCS_RD_PULSE_R = crate::FieldReader; #[doc = "Field `NCS_RD_PULSE` writer - NCS Pulse Length in READ Access"] -pub type NCS_RD_PULSE_W<'a, const O: u8> = crate::FieldWriter<'a, PULSE_SPEC, 7, O>; +pub type NCS_RD_PULSE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - NWE Pulse Length"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - NWE Pulse Length"] #[inline(always)] #[must_use] - pub fn nwe_pulse(&mut self) -> NWE_PULSE_W<0> { + pub fn nwe_pulse(&mut self) -> NWE_PULSE_W { NWE_PULSE_W::new(self) } #[doc = "Bits 8:14 - NCS Pulse Length in WRITE Access"] #[inline(always)] #[must_use] - pub fn ncs_wr_pulse(&mut self) -> NCS_WR_PULSE_W<8> { + pub fn ncs_wr_pulse(&mut self) -> NCS_WR_PULSE_W { NCS_WR_PULSE_W::new(self) } #[doc = "Bits 16:22 - NRD Pulse Length"] #[inline(always)] #[must_use] - pub fn nrd_pulse(&mut self) -> NRD_PULSE_W<16> { + pub fn nrd_pulse(&mut self) -> NRD_PULSE_W { NRD_PULSE_W::new(self) } #[doc = "Bits 24:30 - NCS Pulse Length in READ Access"] #[inline(always)] #[must_use] - pub fn ncs_rd_pulse(&mut self) -> NCS_RD_PULSE_W<24> { + pub fn ncs_rd_pulse(&mut self) -> NCS_RD_PULSE_W { NCS_RD_PULSE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Pulse Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pulse](index.html) module"] +#[doc = "SMC Pulse Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct PULSE_SPEC; impl crate::RegisterSpec for PULSE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [pulse::R](R) reader structure"] -impl crate::Readable for PULSE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [pulse::W](W) writer structure"] +#[doc = "`read()` method returns [`pulse::R`](R) reader structure"] +impl crate::Readable for PULSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pulse::W`](W) writer structure"] impl crate::Writable for PULSE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/setup.rs b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/setup.rs index 9f797436..0683a02e 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/setup.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/smc_cs_number/setup.rs @@ -1,55 +1,23 @@ #[doc = "Register `SETUP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SETUP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NWE_SETUP` reader - NWE Setup Length"] pub type NWE_SETUP_R = crate::FieldReader; #[doc = "Field `NWE_SETUP` writer - NWE Setup Length"] -pub type NWE_SETUP_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_SPEC, 6, O>; +pub type NWE_SETUP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `NCS_WR_SETUP` reader - NCS Setup Length in WRITE Access"] pub type NCS_WR_SETUP_R = crate::FieldReader; #[doc = "Field `NCS_WR_SETUP` writer - NCS Setup Length in WRITE Access"] -pub type NCS_WR_SETUP_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_SPEC, 6, O>; +pub type NCS_WR_SETUP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `NRD_SETUP` reader - NRD Setup Length"] pub type NRD_SETUP_R = crate::FieldReader; #[doc = "Field `NRD_SETUP` writer - NRD Setup Length"] -pub type NRD_SETUP_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_SPEC, 6, O>; +pub type NRD_SETUP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `NCS_RD_SETUP` reader - NCS Setup Length in READ Access"] pub type NCS_RD_SETUP_R = crate::FieldReader; #[doc = "Field `NCS_RD_SETUP` writer - NCS Setup Length in READ Access"] -pub type NCS_RD_SETUP_W<'a, const O: u8> = crate::FieldWriter<'a, SETUP_SPEC, 6, O>; +pub type NCS_RD_SETUP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:5 - NWE Setup Length"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:5 - NWE Setup Length"] #[inline(always)] #[must_use] - pub fn nwe_setup(&mut self) -> NWE_SETUP_W<0> { + pub fn nwe_setup(&mut self) -> NWE_SETUP_W { NWE_SETUP_W::new(self) } #[doc = "Bits 8:13 - NCS Setup Length in WRITE Access"] #[inline(always)] #[must_use] - pub fn ncs_wr_setup(&mut self) -> NCS_WR_SETUP_W<8> { + pub fn ncs_wr_setup(&mut self) -> NCS_WR_SETUP_W { NCS_WR_SETUP_W::new(self) } #[doc = "Bits 16:21 - NRD Setup Length"] #[inline(always)] #[must_use] - pub fn nrd_setup(&mut self) -> NRD_SETUP_W<16> { + pub fn nrd_setup(&mut self) -> NRD_SETUP_W { NRD_SETUP_W::new(self) } #[doc = "Bits 24:29 - NCS Setup Length in READ Access"] #[inline(always)] #[must_use] - pub fn ncs_rd_setup(&mut self) -> NCS_RD_SETUP_W<24> { + pub fn ncs_rd_setup(&mut self) -> NCS_RD_SETUP_W { NCS_RD_SETUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Setup Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [setup](index.html) module"] +#[doc = "SMC Setup Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`setup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SETUP_SPEC; impl crate::RegisterSpec for SETUP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [setup::R](R) reader structure"] -impl crate::Readable for SETUP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [setup::W](W) writer structure"] +#[doc = "`read()` method returns [`setup::R`](R) reader structure"] +impl crate::Readable for SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup::W`](W) writer structure"] impl crate::Writable for SETUP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/smc/wpmr.rs index 0d152f7a..a280cc44 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protect Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protect Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protect Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMC Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "SMC Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/smc/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/smc/wpsr.rs index b207cbb6..2ffe41c2 100644 --- a/arch/cortex-m/samv71q21-pac/src/smc/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/smc/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "SMC Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "SMC Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/spi0.rs b/arch/cortex-m/samv71q21-pac/src/spi0.rs index 6d7f1bff..0001c4f7 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0.rs @@ -26,47 +26,58 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "RDR (r) register accessor: an alias for `Reg`"] +#[doc = "RDR (r) register accessor: Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rdr`] +module"] pub type RDR = crate::Reg; #[doc = "Receive Data Register"] pub mod rdr; -#[doc = "TDR (w) register accessor: an alias for `Reg`"] +#[doc = "TDR (w) register accessor: Transmit Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tdr`] +module"] pub type TDR = crate::Reg; #[doc = "Transmit Data Register"] pub mod tdr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "CSR (rw) register accessor: an alias for `Reg`"] +#[doc = "CSR (rw) register accessor: Chip Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`csr`] +module"] pub type CSR = crate::Reg; #[doc = "Chip Select Register"] pub mod csr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/cr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/cr.rs index c67805e2..0640a826 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/cr.rs @@ -1,80 +1,60 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SPIEN` writer - SPI Enable"] -pub type SPIEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SPIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPIDIS` writer - SPI Disable"] -pub type SPIDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SPIDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - SPI Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REQCLR` writer - Request to Clear the Comparison Trigger"] -pub type REQCLR_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type REQCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LASTXFER` writer - Last Transfer"] -pub type LASTXFER_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type LASTXFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - SPI Enable"] #[inline(always)] #[must_use] - pub fn spien(&mut self) -> SPIEN_W<0> { + pub fn spien(&mut self) -> SPIEN_W { SPIEN_W::new(self) } #[doc = "Bit 1 - SPI Disable"] #[inline(always)] #[must_use] - pub fn spidis(&mut self) -> SPIDIS_W<1> { + pub fn spidis(&mut self) -> SPIDIS_W { SPIDIS_W::new(self) } #[doc = "Bit 7 - SPI Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<7> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Bit 12 - Request to Clear the Comparison Trigger"] #[inline(always)] #[must_use] - pub fn reqclr(&mut self) -> REQCLR_W<12> { + pub fn reqclr(&mut self) -> REQCLR_W { REQCLR_W::new(self) } #[doc = "Bit 24 - Last Transfer"] #[inline(always)] #[must_use] - pub fn lastxfer(&mut self) -> LASTXFER_W<24> { + pub fn lastxfer(&mut self) -> LASTXFER_W { LASTXFER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/csr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/csr.rs index d22d8d20..653fc5f7 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/csr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/csr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CSR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CPOL` reader - Clock Polarity"] pub type CPOL_R = crate::BitReader; #[doc = "Clock Polarity\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl CPOL_R { true => CPOLSELECT_A::IDLE_HIGH, } } - #[doc = "Checks if the value of the field is `IDLE_LOW`"] + #[doc = "Clock is low when inactive (CPOL=0)"] #[inline(always)] pub fn is_idle_low(&self) -> bool { *self == CPOLSELECT_A::IDLE_LOW } - #[doc = "Checks if the value of the field is `IDLE_HIGH`"] + #[doc = "Clock is high when inactive (CPOL=1)"] #[inline(always)] pub fn is_idle_high(&self) -> bool { *self == CPOLSELECT_A::IDLE_HIGH } } #[doc = "Field `CPOL` writer - Clock Polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O, CPOLSELECT_A>; -impl<'a, const O: u8> CPOL_W<'a, O> { +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CPOLSELECT_A>; +impl<'a, REG, const O: u8> CPOL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Clock is low when inactive (CPOL=0)"] #[inline(always)] - pub fn idle_low(self) -> &'a mut W { + pub fn idle_low(self) -> &'a mut crate::W { self.variant(CPOLSELECT_A::IDLE_LOW) } #[doc = "Clock is high when inactive (CPOL=1)"] #[inline(always)] - pub fn idle_high(self) -> &'a mut W { + pub fn idle_high(self) -> &'a mut crate::W { self.variant(CPOLSELECT_A::IDLE_HIGH) } } @@ -109,39 +80,42 @@ impl NCPHA_R { false => NCPHASELECT_A::VALID_TRAILING_EDGE, } } - #[doc = "Checks if the value of the field is `VALID_LEADING_EDGE`"] + #[doc = "Data is valid on clock leading edge (NCPHA=1)"] #[inline(always)] pub fn is_valid_leading_edge(&self) -> bool { *self == NCPHASELECT_A::VALID_LEADING_EDGE } - #[doc = "Checks if the value of the field is `VALID_TRAILING_EDGE`"] + #[doc = "Data is valid on clock trailing edge (NCPHA=0)"] #[inline(always)] pub fn is_valid_trailing_edge(&self) -> bool { *self == NCPHASELECT_A::VALID_TRAILING_EDGE } } #[doc = "Field `NCPHA` writer - Clock Phase"] -pub type NCPHA_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O, NCPHASELECT_A>; -impl<'a, const O: u8> NCPHA_W<'a, O> { +pub type NCPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, NCPHASELECT_A>; +impl<'a, REG, const O: u8> NCPHA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Data is valid on clock leading edge (NCPHA=1)"] #[inline(always)] - pub fn valid_leading_edge(self) -> &'a mut W { + pub fn valid_leading_edge(self) -> &'a mut crate::W { self.variant(NCPHASELECT_A::VALID_LEADING_EDGE) } #[doc = "Data is valid on clock trailing edge (NCPHA=0)"] #[inline(always)] - pub fn valid_trailing_edge(self) -> &'a mut W { + pub fn valid_trailing_edge(self) -> &'a mut crate::W { self.variant(NCPHASELECT_A::VALID_TRAILING_EDGE) } } #[doc = "Field `CSNAAT` reader - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"] pub type CSNAAT_R = crate::BitReader; #[doc = "Field `CSNAAT` writer - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"] -pub type CSNAAT_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type CSNAAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CSAAT` reader - Chip Select Active After Transfer"] pub type CSAAT_R = crate::BitReader; #[doc = "Field `CSAAT` writer - Chip Select Active After Transfer"] -pub type CSAAT_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type CSAAT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BITS` reader - Bits Per Transfer"] pub type BITS_R = crate::FieldReader; #[doc = "Bits Per Transfer\n\nValue on reset: 0"] @@ -193,113 +167,117 @@ impl BITS_R { _ => None, } } - #[doc = "Checks if the value of the field is `_8_BIT`"] + #[doc = "8 bits for transfer"] #[inline(always)] pub fn is_8_bit(&self) -> bool { *self == BITSSELECT_A::_8_BIT } - #[doc = "Checks if the value of the field is `_9_BIT`"] + #[doc = "9 bits for transfer"] #[inline(always)] pub fn is_9_bit(&self) -> bool { *self == BITSSELECT_A::_9_BIT } - #[doc = "Checks if the value of the field is `_10_BIT`"] + #[doc = "10 bits for transfer"] #[inline(always)] pub fn is_10_bit(&self) -> bool { *self == BITSSELECT_A::_10_BIT } - #[doc = "Checks if the value of the field is `_11_BIT`"] + #[doc = "11 bits for transfer"] #[inline(always)] pub fn is_11_bit(&self) -> bool { *self == BITSSELECT_A::_11_BIT } - #[doc = "Checks if the value of the field is `_12_BIT`"] + #[doc = "12 bits for transfer"] #[inline(always)] pub fn is_12_bit(&self) -> bool { *self == BITSSELECT_A::_12_BIT } - #[doc = "Checks if the value of the field is `_13_BIT`"] + #[doc = "13 bits for transfer"] #[inline(always)] pub fn is_13_bit(&self) -> bool { *self == BITSSELECT_A::_13_BIT } - #[doc = "Checks if the value of the field is `_14_BIT`"] + #[doc = "14 bits for transfer"] #[inline(always)] pub fn is_14_bit(&self) -> bool { *self == BITSSELECT_A::_14_BIT } - #[doc = "Checks if the value of the field is `_15_BIT`"] + #[doc = "15 bits for transfer"] #[inline(always)] pub fn is_15_bit(&self) -> bool { *self == BITSSELECT_A::_15_BIT } - #[doc = "Checks if the value of the field is `_16_BIT`"] + #[doc = "16 bits for transfer"] #[inline(always)] pub fn is_16_bit(&self) -> bool { *self == BITSSELECT_A::_16_BIT } } #[doc = "Field `BITS` writer - Bits Per Transfer"] -pub type BITS_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 4, O, BITSSELECT_A>; -impl<'a, const O: u8> BITS_W<'a, O> { +pub type BITS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, BITSSELECT_A>; +impl<'a, REG, const O: u8> BITS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8 bits for transfer"] #[inline(always)] - pub fn _8_bit(self) -> &'a mut W { + pub fn _8_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_8_BIT) } #[doc = "9 bits for transfer"] #[inline(always)] - pub fn _9_bit(self) -> &'a mut W { + pub fn _9_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_9_BIT) } #[doc = "10 bits for transfer"] #[inline(always)] - pub fn _10_bit(self) -> &'a mut W { + pub fn _10_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_10_BIT) } #[doc = "11 bits for transfer"] #[inline(always)] - pub fn _11_bit(self) -> &'a mut W { + pub fn _11_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_11_BIT) } #[doc = "12 bits for transfer"] #[inline(always)] - pub fn _12_bit(self) -> &'a mut W { + pub fn _12_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_12_BIT) } #[doc = "13 bits for transfer"] #[inline(always)] - pub fn _13_bit(self) -> &'a mut W { + pub fn _13_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_13_BIT) } #[doc = "14 bits for transfer"] #[inline(always)] - pub fn _14_bit(self) -> &'a mut W { + pub fn _14_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_14_BIT) } #[doc = "15 bits for transfer"] #[inline(always)] - pub fn _15_bit(self) -> &'a mut W { + pub fn _15_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_15_BIT) } #[doc = "16 bits for transfer"] #[inline(always)] - pub fn _16_bit(self) -> &'a mut W { + pub fn _16_bit(self) -> &'a mut crate::W { self.variant(BITSSELECT_A::_16_BIT) } } #[doc = "Field `SCBR` reader - Serial Clock Bit Rate"] pub type SCBR_R = crate::FieldReader; #[doc = "Field `SCBR` writer - Serial Clock Bit Rate"] -pub type SCBR_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 8, O>; +pub type SCBR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DLYBS` reader - Delay Before SPCK"] pub type DLYBS_R = crate::FieldReader; #[doc = "Field `DLYBS` writer - Delay Before SPCK"] -pub type DLYBS_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 8, O>; +pub type DLYBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `DLYBCT` reader - Delay Between Consecutive Transfers"] pub type DLYBCT_R = crate::FieldReader; #[doc = "Field `DLYBCT` writer - Delay Between Consecutive Transfers"] -pub type DLYBCT_W<'a, const O: u8> = crate::FieldWriter<'a, CSR_SPEC, 8, O>; +pub type DLYBCT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 0 - Clock Polarity"] #[inline(always)] @@ -346,70 +324,67 @@ impl W { #[doc = "Bit 0 - Clock Polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<0> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bit 1 - Clock Phase"] #[inline(always)] #[must_use] - pub fn ncpha(&mut self) -> NCPHA_W<1> { + pub fn ncpha(&mut self) -> NCPHA_W { NCPHA_W::new(self) } #[doc = "Bit 2 - Chip Select Not Active After Transfer (Ignored if CSAAT = 1)"] #[inline(always)] #[must_use] - pub fn csnaat(&mut self) -> CSNAAT_W<2> { + pub fn csnaat(&mut self) -> CSNAAT_W { CSNAAT_W::new(self) } #[doc = "Bit 3 - Chip Select Active After Transfer"] #[inline(always)] #[must_use] - pub fn csaat(&mut self) -> CSAAT_W<3> { + pub fn csaat(&mut self) -> CSAAT_W { CSAAT_W::new(self) } #[doc = "Bits 4:7 - Bits Per Transfer"] #[inline(always)] #[must_use] - pub fn bits_(&mut self) -> BITS_W<4> { + pub fn bits_(&mut self) -> BITS_W { BITS_W::new(self) } #[doc = "Bits 8:15 - Serial Clock Bit Rate"] #[inline(always)] #[must_use] - pub fn scbr(&mut self) -> SCBR_W<8> { + pub fn scbr(&mut self) -> SCBR_W { SCBR_W::new(self) } #[doc = "Bits 16:23 - Delay Before SPCK"] #[inline(always)] #[must_use] - pub fn dlybs(&mut self) -> DLYBS_W<16> { + pub fn dlybs(&mut self) -> DLYBS_W { DLYBS_W::new(self) } #[doc = "Bits 24:31 - Delay Between Consecutive Transfers"] #[inline(always)] #[must_use] - pub fn dlybct(&mut self) -> DLYBCT_W<24> { + pub fn dlybct(&mut self) -> DLYBCT_W { DLYBCT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Chip Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +#[doc = "Chip Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSR_SPEC; impl crate::RegisterSpec for CSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [csr::R](R) reader structure"] -impl crate::Readable for CSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] impl crate::Writable for CSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/idr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/idr.rs index 1ddea1a2..cb91bb1d 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/idr.rs @@ -1,96 +1,76 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Disable"] -pub type RDRF_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RDRF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDRE` writer - SPI Transmit Data Register Empty Interrupt Disable"] -pub type TDRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TDRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODF` writer - Mode Fault Error Interrupt Disable"] -pub type MODF_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MODF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRES` writer - Overrun Error Interrupt Disable"] -pub type OVRES_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type OVRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NSSR` writer - NSS Rising Interrupt Disable"] -pub type NSSR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type NSSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDES` writer - Underrun Error Interrupt Disable"] -pub type UNDES_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type UNDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Receive Data Register Full Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rdrf(&mut self) -> RDRF_W<0> { + pub fn rdrf(&mut self) -> RDRF_W { RDRF_W::new(self) } #[doc = "Bit 1 - SPI Transmit Data Register Empty Interrupt Disable"] #[inline(always)] #[must_use] - pub fn tdre(&mut self) -> TDRE_W<1> { + pub fn tdre(&mut self) -> TDRE_W { TDRE_W::new(self) } #[doc = "Bit 2 - Mode Fault Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn modf(&mut self) -> MODF_W<2> { + pub fn modf(&mut self) -> MODF_W { MODF_W::new(self) } #[doc = "Bit 3 - Overrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ovres(&mut self) -> OVRES_W<3> { + pub fn ovres(&mut self) -> OVRES_W { OVRES_W::new(self) } #[doc = "Bit 8 - NSS Rising Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nssr(&mut self) -> NSSR_W<8> { + pub fn nssr(&mut self) -> NSSR_W { NSSR_W::new(self) } #[doc = "Bit 9 - Transmission Registers Empty Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - Underrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn undes(&mut self) -> UNDES_W<10> { + pub fn undes(&mut self) -> UNDES_W { UNDES_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/ier.rs b/arch/cortex-m/samv71q21-pac/src/spi0/ier.rs index d9d3d5a5..37cc3117 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/ier.rs @@ -1,96 +1,76 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDRF` writer - Receive Data Register Full Interrupt Enable"] -pub type RDRF_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RDRF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TDRE` writer - SPI Transmit Data Register Empty Interrupt Enable"] -pub type TDRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TDRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODF` writer - Mode Fault Error Interrupt Enable"] -pub type MODF_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MODF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRES` writer - Overrun Error Interrupt Enable"] -pub type OVRES_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type OVRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NSSR` writer - NSS Rising Interrupt Enable"] -pub type NSSR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type NSSR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Transmission Registers Empty Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDES` writer - Underrun Error Interrupt Enable"] -pub type UNDES_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type UNDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Receive Data Register Full Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rdrf(&mut self) -> RDRF_W<0> { + pub fn rdrf(&mut self) -> RDRF_W { RDRF_W::new(self) } #[doc = "Bit 1 - SPI Transmit Data Register Empty Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tdre(&mut self) -> TDRE_W<1> { + pub fn tdre(&mut self) -> TDRE_W { TDRE_W::new(self) } #[doc = "Bit 2 - Mode Fault Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn modf(&mut self) -> MODF_W<2> { + pub fn modf(&mut self) -> MODF_W { MODF_W::new(self) } #[doc = "Bit 3 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovres(&mut self) -> OVRES_W<3> { + pub fn ovres(&mut self) -> OVRES_W { OVRES_W::new(self) } #[doc = "Bit 8 - NSS Rising Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nssr(&mut self) -> NSSR_W<8> { + pub fn nssr(&mut self) -> NSSR_W { NSSR_W::new(self) } #[doc = "Bit 9 - Transmission Registers Empty Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - Underrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn undes(&mut self) -> UNDES_W<10> { + pub fn undes(&mut self) -> UNDES_W { UNDES_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/imr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/imr.rs index 0c755157..e7c5bdf4 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDRF` reader - Receive Data Register Full Interrupt Mask"] pub type RDRF_R = crate::BitReader; #[doc = "Field `TDRE` reader - SPI Transmit Data Register Empty Interrupt Mask"] @@ -64,15 +51,13 @@ impl R { UNDES_R::new(((self.bits >> 10) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/mr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/mr.rs index a4115ed7..5d46e4f2 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MSTR` reader - Master/Slave Mode"] pub type MSTR_R = crate::BitReader; #[doc = "Master/Slave Mode\n\nValue on reset: 0"] @@ -59,51 +27,54 @@ impl MSTR_R { false => MSTRSELECT_A::SLAVE, } } - #[doc = "Checks if the value of the field is `MASTER`"] + #[doc = "Master"] #[inline(always)] pub fn is_master(&self) -> bool { *self == MSTRSELECT_A::MASTER } - #[doc = "Checks if the value of the field is `SLAVE`"] + #[doc = "Slave"] #[inline(always)] pub fn is_slave(&self) -> bool { *self == MSTRSELECT_A::SLAVE } } #[doc = "Field `MSTR` writer - Master/Slave Mode"] -pub type MSTR_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, MSTRSELECT_A>; -impl<'a, const O: u8> MSTR_W<'a, O> { +pub type MSTR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MSTRSELECT_A>; +impl<'a, REG, const O: u8> MSTR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Master"] #[inline(always)] - pub fn master(self) -> &'a mut W { + pub fn master(self) -> &'a mut crate::W { self.variant(MSTRSELECT_A::MASTER) } #[doc = "Slave"] #[inline(always)] - pub fn slave(self) -> &'a mut W { + pub fn slave(self) -> &'a mut crate::W { self.variant(MSTRSELECT_A::SLAVE) } } #[doc = "Field `PS` reader - Peripheral Select"] pub type PS_R = crate::BitReader; #[doc = "Field `PS` writer - Peripheral Select"] -pub type PS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type PS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCSDEC` reader - Chip Select Decode"] pub type PCSDEC_R = crate::BitReader; #[doc = "Field `PCSDEC` writer - Chip Select Decode"] -pub type PCSDEC_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type PCSDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODFDIS` reader - Mode Fault Detection"] pub type MODFDIS_R = crate::BitReader; #[doc = "Field `MODFDIS` writer - Mode Fault Detection"] -pub type MODFDIS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type MODFDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDRBT` reader - Wait Data Read Before Transfer"] pub type WDRBT_R = crate::BitReader; #[doc = "Field `WDRBT` writer - Wait Data Read Before Transfer"] -pub type WDRBT_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDRBT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LLB` reader - Local Loopback Enable"] pub type LLB_R = crate::BitReader; #[doc = "Field `LLB` writer - Local Loopback Enable"] -pub type LLB_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type LLB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PCS` reader - Peripheral Chip Select"] pub type PCS_R = crate::FieldReader; #[doc = "Peripheral Chip Select\n\nValue on reset: 0"] @@ -140,55 +111,59 @@ impl PCS_R { _ => None, } } - #[doc = "Checks if the value of the field is `NPCS0`"] + #[doc = "NPCS0 as Chip Select"] #[inline(always)] pub fn is_npcs0(&self) -> bool { *self == PCSSELECT_A::NPCS0 } - #[doc = "Checks if the value of the field is `NPCS1`"] + #[doc = "NPCS1 as Chip Select"] #[inline(always)] pub fn is_npcs1(&self) -> bool { *self == PCSSELECT_A::NPCS1 } - #[doc = "Checks if the value of the field is `NPCS2`"] + #[doc = "NPCS2 as Chip Select"] #[inline(always)] pub fn is_npcs2(&self) -> bool { *self == PCSSELECT_A::NPCS2 } - #[doc = "Checks if the value of the field is `NPCS3`"] + #[doc = "NPCS3 as Chip Select"] #[inline(always)] pub fn is_npcs3(&self) -> bool { *self == PCSSELECT_A::NPCS3 } } #[doc = "Field `PCS` writer - Peripheral Chip Select"] -pub type PCS_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 4, O, PCSSELECT_A>; -impl<'a, const O: u8> PCS_W<'a, O> { +pub type PCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, PCSSELECT_A>; +impl<'a, REG, const O: u8> PCS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NPCS0 as Chip Select"] #[inline(always)] - pub fn npcs0(self) -> &'a mut W { + pub fn npcs0(self) -> &'a mut crate::W { self.variant(PCSSELECT_A::NPCS0) } #[doc = "NPCS1 as Chip Select"] #[inline(always)] - pub fn npcs1(self) -> &'a mut W { + pub fn npcs1(self) -> &'a mut crate::W { self.variant(PCSSELECT_A::NPCS1) } #[doc = "NPCS2 as Chip Select"] #[inline(always)] - pub fn npcs2(self) -> &'a mut W { + pub fn npcs2(self) -> &'a mut crate::W { self.variant(PCSSELECT_A::NPCS2) } #[doc = "NPCS3 as Chip Select"] #[inline(always)] - pub fn npcs3(self) -> &'a mut W { + pub fn npcs3(self) -> &'a mut crate::W { self.variant(PCSSELECT_A::NPCS3) } } #[doc = "Field `DLYBCS` reader - Delay Between Chip Selects"] pub type DLYBCS_R = crate::FieldReader; #[doc = "Field `DLYBCS` writer - Delay Between Chip Selects"] -pub type DLYBCS_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O>; +pub type DLYBCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 0 - Master/Slave Mode"] #[inline(always)] @@ -235,70 +210,67 @@ impl W { #[doc = "Bit 0 - Master/Slave Mode"] #[inline(always)] #[must_use] - pub fn mstr(&mut self) -> MSTR_W<0> { + pub fn mstr(&mut self) -> MSTR_W { MSTR_W::new(self) } #[doc = "Bit 1 - Peripheral Select"] #[inline(always)] #[must_use] - pub fn ps(&mut self) -> PS_W<1> { + pub fn ps(&mut self) -> PS_W { PS_W::new(self) } #[doc = "Bit 2 - Chip Select Decode"] #[inline(always)] #[must_use] - pub fn pcsdec(&mut self) -> PCSDEC_W<2> { + pub fn pcsdec(&mut self) -> PCSDEC_W { PCSDEC_W::new(self) } #[doc = "Bit 4 - Mode Fault Detection"] #[inline(always)] #[must_use] - pub fn modfdis(&mut self) -> MODFDIS_W<4> { + pub fn modfdis(&mut self) -> MODFDIS_W { MODFDIS_W::new(self) } #[doc = "Bit 5 - Wait Data Read Before Transfer"] #[inline(always)] #[must_use] - pub fn wdrbt(&mut self) -> WDRBT_W<5> { + pub fn wdrbt(&mut self) -> WDRBT_W { WDRBT_W::new(self) } #[doc = "Bit 7 - Local Loopback Enable"] #[inline(always)] #[must_use] - pub fn llb(&mut self) -> LLB_W<7> { + pub fn llb(&mut self) -> LLB_W { LLB_W::new(self) } #[doc = "Bits 16:19 - Peripheral Chip Select"] #[inline(always)] #[must_use] - pub fn pcs(&mut self) -> PCS_W<16> { + pub fn pcs(&mut self) -> PCS_W { PCS_W::new(self) } #[doc = "Bits 24:31 - Delay Between Chip Selects"] #[inline(always)] #[must_use] - pub fn dlybcs(&mut self) -> DLYBCS_W<24> { + pub fn dlybcs(&mut self) -> DLYBCS_W { DLYBCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/rdr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/rdr.rs index 427e1f43..e96c6621 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/rdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/rdr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RD` reader - Receive Data"] pub type RD_R = crate::FieldReader; #[doc = "Field `PCS` reader - Peripheral Chip Select"] @@ -29,15 +16,13 @@ impl R { PCS_R::new(((self.bits >> 16) & 0x0f) as u8) } } -#[doc = "Receive Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rdr](index.html) module"] +#[doc = "Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RDR_SPEC; impl crate::RegisterSpec for RDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rdr::R](R) reader structure"] -impl crate::Readable for RDR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rdr::R`](R) reader structure"] +impl crate::Readable for RDR_SPEC {} #[doc = "`reset()` method sets RDR to value 0"] impl crate::Resettable for RDR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/sr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/sr.rs index 2b950880..c3992fa2 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDRF` reader - Receive Data Register Full (cleared by reading SPI_RDR)"] pub type RDRF_R = crate::BitReader; #[doc = "Field `TDRE` reader - Transmit Data Register Empty (cleared by writing SPI_TDR)"] @@ -71,15 +58,13 @@ impl R { SPIENS_R::new(((self.bits >> 16) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/tdr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/tdr.rs index 145f8f1b..2f9b4332 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/tdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/tdr.rs @@ -1,26 +1,7 @@ #[doc = "Register `TDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TD` writer - Transmit Data"] -pub type TD_W<'a, const O: u8> = crate::FieldWriter<'a, TDR_SPEC, 16, O, u16>; +pub type TD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Peripheral Chip Select\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -44,65 +25,68 @@ impl crate::FieldSpec for PCSSELECT_AW { type Ux = u8; } #[doc = "Field `PCS` writer - Peripheral Chip Select"] -pub type PCS_W<'a, const O: u8> = crate::FieldWriter<'a, TDR_SPEC, 4, O, PCSSELECT_AW>; -impl<'a, const O: u8> PCS_W<'a, O> { +pub type PCS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, PCSSELECT_AW>; +impl<'a, REG, const O: u8> PCS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NPCS0 as Chip Select"] #[inline(always)] - pub fn npcs0(self) -> &'a mut W { + pub fn npcs0(self) -> &'a mut crate::W { self.variant(PCSSELECT_AW::NPCS0) } #[doc = "NPCS1 as Chip Select"] #[inline(always)] - pub fn npcs1(self) -> &'a mut W { + pub fn npcs1(self) -> &'a mut crate::W { self.variant(PCSSELECT_AW::NPCS1) } #[doc = "NPCS2 as Chip Select"] #[inline(always)] - pub fn npcs2(self) -> &'a mut W { + pub fn npcs2(self) -> &'a mut crate::W { self.variant(PCSSELECT_AW::NPCS2) } #[doc = "NPCS3 as Chip Select"] #[inline(always)] - pub fn npcs3(self) -> &'a mut W { + pub fn npcs3(self) -> &'a mut crate::W { self.variant(PCSSELECT_AW::NPCS3) } } #[doc = "Field `LASTXFER` writer - Last Transfer"] -pub type LASTXFER_W<'a, const O: u8> = crate::BitWriter<'a, TDR_SPEC, O>; +pub type LASTXFER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:15 - Transmit Data"] #[inline(always)] #[must_use] - pub fn td(&mut self) -> TD_W<0> { + pub fn td(&mut self) -> TD_W { TD_W::new(self) } #[doc = "Bits 16:19 - Peripheral Chip Select"] #[inline(always)] #[must_use] - pub fn pcs(&mut self) -> PCS_W<16> { + pub fn pcs(&mut self) -> PCS_W { PCS_W::new(self) } #[doc = "Bit 24 - Last Transfer"] #[inline(always)] #[must_use] - pub fn lastxfer(&mut self) -> LASTXFER_W<24> { + pub fn lastxfer(&mut self) -> LASTXFER_W { LASTXFER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Data Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdr](index.html) module"] +#[doc = "Transmit Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TDR_SPEC; impl crate::RegisterSpec for TDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [tdr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`tdr::W`](W) writer structure"] impl crate::Writable for TDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/wpmr.rs index 9e02b6c8..00089f88 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/spi0/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/spi0/wpsr.rs index 07acbfac..23bbcfad 100644 --- a/arch/cortex-m/samv71q21-pac/src/spi0/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/spi0/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xff) as u8) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/ssc.rs b/arch/cortex-m/samv71q21-pac/src/ssc.rs index 5e61276d..c86b5b86 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc.rs @@ -41,75 +41,93 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "CMR (rw) register accessor: an alias for `Reg`"] +#[doc = "CMR (rw) register accessor: Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmr`] +module"] pub type CMR = crate::Reg; #[doc = "Clock Mode Register"] pub mod cmr; -#[doc = "RCMR (rw) register accessor: an alias for `Reg`"] +#[doc = "RCMR (rw) register accessor: Receive Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rcmr`] +module"] pub type RCMR = crate::Reg; #[doc = "Receive Clock Mode Register"] pub mod rcmr; -#[doc = "RFMR (rw) register accessor: an alias for `Reg`"] +#[doc = "RFMR (rw) register accessor: Receive Frame Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rfmr`] +module"] pub type RFMR = crate::Reg; #[doc = "Receive Frame Mode Register"] pub mod rfmr; -#[doc = "TCMR (rw) register accessor: an alias for `Reg`"] +#[doc = "TCMR (rw) register accessor: Transmit Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tcmr`] +module"] pub type TCMR = crate::Reg; #[doc = "Transmit Clock Mode Register"] pub mod tcmr; -#[doc = "TFMR (rw) register accessor: an alias for `Reg`"] +#[doc = "TFMR (rw) register accessor: Transmit Frame Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tfmr`] +module"] pub type TFMR = crate::Reg; #[doc = "Transmit Frame Mode Register"] pub mod tfmr; -#[doc = "RHR (r) register accessor: an alias for `Reg`"] +#[doc = "RHR (r) register accessor: Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rhr`] +module"] pub type RHR = crate::Reg; #[doc = "Receive Holding Register"] pub mod rhr; -#[doc = "THR (w) register accessor: an alias for `Reg`"] +#[doc = "THR (w) register accessor: Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "RSHR (r) register accessor: an alias for `Reg`"] +#[doc = "RSHR (r) register accessor: Receive Sync. Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rshr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rshr`] +module"] pub type RSHR = crate::Reg; #[doc = "Receive Sync. Holding Register"] pub mod rshr; -#[doc = "TSHR (rw) register accessor: an alias for `Reg`"] +#[doc = "TSHR (rw) register accessor: Transmit Sync. Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tshr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tshr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`tshr`] +module"] pub type TSHR = crate::Reg; #[doc = "Transmit Sync. Holding Register"] pub mod tshr; -#[doc = "RC0R (rw) register accessor: an alias for `Reg`"] +#[doc = "RC0R (rw) register accessor: Receive Compare 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc0r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc0r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rc0r`] +module"] pub type RC0R = crate::Reg; #[doc = "Receive Compare 0 Register"] pub mod rc0r; -#[doc = "RC1R (rw) register accessor: an alias for `Reg`"] +#[doc = "RC1R (rw) register accessor: Receive Compare 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc1r::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc1r::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rc1r`] +module"] pub type RC1R = crate::Reg; #[doc = "Receive Compare 1 Register"] pub mod rc1r; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/cmr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/cmr.rs index 7eec13a4..65af0b9e 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/cmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/cmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `CMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DIV` reader - Clock Divider"] pub type DIV_R = crate::FieldReader; #[doc = "Field `DIV` writer - Clock Divider"] -pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, CMR_SPEC, 12, O, u16>; +pub type DIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:11 - Clock Divider"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:11 - Clock Divider"] #[inline(always)] #[must_use] - pub fn div(&mut self) -> DIV_W<0> { + pub fn div(&mut self) -> DIV_W { DIV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr](index.html) module"] +#[doc = "Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMR_SPEC; impl crate::RegisterSpec for CMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmr::R](R) reader structure"] -impl crate::Readable for CMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmr::W](W) writer structure"] +#[doc = "`read()` method returns [`cmr::R`](R) reader structure"] +impl crate::Readable for CMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmr::W`](W) writer structure"] impl crate::Writable for CMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/cr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/cr.rs index 36bce559..a1ceed26 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/cr.rs @@ -1,80 +1,60 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXEN` writer - Receive Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDIS` writer - Receive Disable"] -pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` writer - Transmit Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDIS` writer - Transmit Disable"] -pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Receive Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<0> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 1 - Receive Disable"] #[inline(always)] #[must_use] - pub fn rxdis(&mut self) -> RXDIS_W<1> { + pub fn rxdis(&mut self) -> RXDIS_W { RXDIS_W::new(self) } #[doc = "Bit 8 - Transmit Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<8> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 9 - Transmit Disable"] #[inline(always)] #[must_use] - pub fn txdis(&mut self) -> TXDIS_W<9> { + pub fn txdis(&mut self) -> TXDIS_W { TXDIS_W::new(self) } #[doc = "Bit 15 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<15> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/idr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/idr.rs index 1d93c5cc..d86d64e6 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/idr.rs @@ -1,104 +1,84 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Transmit Empty Interrupt Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRDY` writer - Receive Ready Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRUN` writer - Receive Overrun Interrupt Disable"] -pub type OVRUN_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type OVRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CP0` writer - Compare 0 Interrupt Disable"] -pub type CP0_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CP0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CP1` writer - Compare 1 Interrupt Disable"] -pub type CP1_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CP1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSYN` writer - Tx Sync Interrupt Enable"] -pub type TXSYN_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXSYN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSYN` writer - Rx Sync Interrupt Enable"] -pub type RXSYN_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXSYN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmit Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<0> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 1 - Transmit Empty Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<1> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 4 - Receive Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<4> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 5 - Receive Overrun Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ovrun(&mut self) -> OVRUN_W<5> { + pub fn ovrun(&mut self) -> OVRUN_W { OVRUN_W::new(self) } #[doc = "Bit 8 - Compare 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cp0(&mut self) -> CP0_W<8> { + pub fn cp0(&mut self) -> CP0_W { CP0_W::new(self) } #[doc = "Bit 9 - Compare 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn cp1(&mut self) -> CP1_W<9> { + pub fn cp1(&mut self) -> CP1_W { CP1_W::new(self) } #[doc = "Bit 10 - Tx Sync Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txsyn(&mut self) -> TXSYN_W<10> { + pub fn txsyn(&mut self) -> TXSYN_W { TXSYN_W::new(self) } #[doc = "Bit 11 - Rx Sync Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxsyn(&mut self) -> RXSYN_W<11> { + pub fn rxsyn(&mut self) -> RXSYN_W { RXSYN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/ier.rs b/arch/cortex-m/samv71q21-pac/src/ssc/ier.rs index a6b5d9d7..5b5cc137 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/ier.rs @@ -1,104 +1,84 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXRDY` writer - Transmit Ready Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Transmit Empty Interrupt Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRDY` writer - Receive Ready Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRUN` writer - Receive Overrun Interrupt Enable"] -pub type OVRUN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type OVRUN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CP0` writer - Compare 0 Interrupt Enable"] -pub type CP0_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CP0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CP1` writer - Compare 1 Interrupt Enable"] -pub type CP1_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CP1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSYN` writer - Tx Sync Interrupt Enable"] -pub type TXSYN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXSYN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSYN` writer - Rx Sync Interrupt Enable"] -pub type RXSYN_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXSYN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmit Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<0> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 1 - Transmit Empty Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<1> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 4 - Receive Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<4> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 5 - Receive Overrun Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovrun(&mut self) -> OVRUN_W<5> { + pub fn ovrun(&mut self) -> OVRUN_W { OVRUN_W::new(self) } #[doc = "Bit 8 - Compare 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cp0(&mut self) -> CP0_W<8> { + pub fn cp0(&mut self) -> CP0_W { CP0_W::new(self) } #[doc = "Bit 9 - Compare 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn cp1(&mut self) -> CP1_W<9> { + pub fn cp1(&mut self) -> CP1_W { CP1_W::new(self) } #[doc = "Bit 10 - Tx Sync Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txsyn(&mut self) -> TXSYN_W<10> { + pub fn txsyn(&mut self) -> TXSYN_W { TXSYN_W::new(self) } #[doc = "Bit 11 - Rx Sync Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxsyn(&mut self) -> RXSYN_W<11> { + pub fn rxsyn(&mut self) -> RXSYN_W { RXSYN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/imr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/imr.rs index 9a05afe9..cdd946a7 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXRDY` reader - Transmit Ready Interrupt Mask"] pub type TXRDY_R = crate::BitReader; #[doc = "Field `TXEMPTY` reader - Transmit Empty Interrupt Mask"] @@ -71,15 +58,13 @@ impl R { RXSYN_R::new(((self.bits >> 11) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/rc0r.rs b/arch/cortex-m/samv71q21-pac/src/ssc/rc0r.rs index c15ccc81..2bdaa4ad 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/rc0r.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/rc0r.rs @@ -1,43 +1,11 @@ #[doc = "Register `RC0R` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RC0R` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CP0` reader - Receive Compare Data 0"] pub type CP0_R = crate::FieldReader; #[doc = "Field `CP0` writer - Receive Compare Data 0"] -pub type CP0_W<'a, const O: u8> = crate::FieldWriter<'a, RC0R_SPEC, 16, O, u16>; +pub type CP0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Receive Compare Data 0"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Receive Compare Data 0"] #[inline(always)] #[must_use] - pub fn cp0(&mut self) -> CP0_W<0> { + pub fn cp0(&mut self) -> CP0_W { CP0_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Compare 0 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rc0r](index.html) module"] +#[doc = "Receive Compare 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc0r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc0r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RC0R_SPEC; impl crate::RegisterSpec for RC0R_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rc0r::R](R) reader structure"] -impl crate::Readable for RC0R_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rc0r::W](W) writer structure"] +#[doc = "`read()` method returns [`rc0r::R`](R) reader structure"] +impl crate::Readable for RC0R_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rc0r::W`](W) writer structure"] impl crate::Writable for RC0R_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/rc1r.rs b/arch/cortex-m/samv71q21-pac/src/ssc/rc1r.rs index e726c3d1..7e34b3ad 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/rc1r.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/rc1r.rs @@ -1,43 +1,11 @@ #[doc = "Register `RC1R` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RC1R` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CP1` reader - Receive Compare Data 1"] pub type CP1_R = crate::FieldReader; #[doc = "Field `CP1` writer - Receive Compare Data 1"] -pub type CP1_W<'a, const O: u8> = crate::FieldWriter<'a, RC1R_SPEC, 16, O, u16>; +pub type CP1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Receive Compare Data 1"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Receive Compare Data 1"] #[inline(always)] #[must_use] - pub fn cp1(&mut self) -> CP1_W<0> { + pub fn cp1(&mut self) -> CP1_W { CP1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Compare 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rc1r](index.html) module"] +#[doc = "Receive Compare 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc1r::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc1r::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RC1R_SPEC; impl crate::RegisterSpec for RC1R_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rc1r::R](R) reader structure"] -impl crate::Readable for RC1R_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rc1r::W](W) writer structure"] +#[doc = "`read()` method returns [`rc1r::R`](R) reader structure"] +impl crate::Readable for RC1R_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rc1r::W`](W) writer structure"] impl crate::Writable for RC1R_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/rcmr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/rcmr.rs index a64eb6e9..b7f02751 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/rcmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/rcmr.rs @@ -1,39 +1,7 @@ #[doc = "Register `RCMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RCMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CKS` reader - Receive Clock Selection"] pub type CKS_R = crate::FieldReader; #[doc = "Receive Clock Selection\n\nValue on reset: 0"] @@ -67,38 +35,42 @@ impl CKS_R { _ => None, } } - #[doc = "Checks if the value of the field is `MCK`"] + #[doc = "Divided Clock"] #[inline(always)] pub fn is_mck(&self) -> bool { *self == CKSSELECT_A::MCK } - #[doc = "Checks if the value of the field is `TK`"] + #[doc = "TK Clock signal"] #[inline(always)] pub fn is_tk(&self) -> bool { *self == CKSSELECT_A::TK } - #[doc = "Checks if the value of the field is `RK`"] + #[doc = "RK pin"] #[inline(always)] pub fn is_rk(&self) -> bool { *self == CKSSELECT_A::RK } } #[doc = "Field `CKS` writer - Receive Clock Selection"] -pub type CKS_W<'a, const O: u8> = crate::FieldWriter<'a, RCMR_SPEC, 2, O, CKSSELECT_A>; -impl<'a, const O: u8> CKS_W<'a, O> { +pub type CKS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CKSSELECT_A>; +impl<'a, REG, const O: u8> CKS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Divided Clock"] #[inline(always)] - pub fn mck(self) -> &'a mut W { + pub fn mck(self) -> &'a mut crate::W { self.variant(CKSSELECT_A::MCK) } #[doc = "TK Clock signal"] #[inline(always)] - pub fn tk(self) -> &'a mut W { + pub fn tk(self) -> &'a mut crate::W { self.variant(CKSSELECT_A::TK) } #[doc = "RK pin"] #[inline(always)] - pub fn rk(self) -> &'a mut W { + pub fn rk(self) -> &'a mut crate::W { self.variant(CKSSELECT_A::RK) } } @@ -135,45 +107,49 @@ impl CKO_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None, RK pin is an input"] #[inline(always)] pub fn is_none(&self) -> bool { *self == CKOSELECT_A::NONE } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "Continuous Receive Clock, RK pin is an output"] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == CKOSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `TRANSFER`"] + #[doc = "Receive Clock only during data transfers, RK pin is an output"] #[inline(always)] pub fn is_transfer(&self) -> bool { *self == CKOSELECT_A::TRANSFER } } #[doc = "Field `CKO` writer - Receive Clock Output Mode Selection"] -pub type CKO_W<'a, const O: u8> = crate::FieldWriter<'a, RCMR_SPEC, 3, O, CKOSELECT_A>; -impl<'a, const O: u8> CKO_W<'a, O> { +pub type CKO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CKOSELECT_A>; +impl<'a, REG, const O: u8> CKO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None, RK pin is an input"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(CKOSELECT_A::NONE) } #[doc = "Continuous Receive Clock, RK pin is an output"] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(CKOSELECT_A::CONTINUOUS) } #[doc = "Receive Clock only during data transfers, RK pin is an output"] #[inline(always)] - pub fn transfer(self) -> &'a mut W { + pub fn transfer(self) -> &'a mut crate::W { self.variant(CKOSELECT_A::TRANSFER) } } #[doc = "Field `CKI` reader - Receive Clock Inversion"] pub type CKI_R = crate::BitReader; #[doc = "Field `CKI` writer - Receive Clock Inversion"] -pub type CKI_W<'a, const O: u8> = crate::BitWriter<'a, RCMR_SPEC, O>; +pub type CKI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CKG` reader - Receive Clock Gating Selection"] pub type CKG_R = crate::FieldReader; #[doc = "Receive Clock Gating Selection\n\nValue on reset: 0"] @@ -207,38 +183,42 @@ impl CKG_R { _ => None, } } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "None"] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == CKGSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `EN_RF_LOW`"] + #[doc = "Receive Clock enabled only if RF Low"] #[inline(always)] pub fn is_en_rf_low(&self) -> bool { *self == CKGSELECT_A::EN_RF_LOW } - #[doc = "Checks if the value of the field is `EN_RF_HIGH`"] + #[doc = "Receive Clock enabled only if RF High"] #[inline(always)] pub fn is_en_rf_high(&self) -> bool { *self == CKGSELECT_A::EN_RF_HIGH } } #[doc = "Field `CKG` writer - Receive Clock Gating Selection"] -pub type CKG_W<'a, const O: u8> = crate::FieldWriter<'a, RCMR_SPEC, 2, O, CKGSELECT_A>; -impl<'a, const O: u8> CKG_W<'a, O> { +pub type CKG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CKGSELECT_A>; +impl<'a, REG, const O: u8> CKG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None"] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(CKGSELECT_A::CONTINUOUS) } #[doc = "Receive Clock enabled only if RF Low"] #[inline(always)] - pub fn en_rf_low(self) -> &'a mut W { + pub fn en_rf_low(self) -> &'a mut crate::W { self.variant(CKGSELECT_A::EN_RF_LOW) } #[doc = "Receive Clock enabled only if RF High"] #[inline(always)] - pub fn en_rf_high(self) -> &'a mut W { + pub fn en_rf_high(self) -> &'a mut crate::W { self.variant(CKGSELECT_A::EN_RF_HIGH) } } @@ -293,113 +273,117 @@ impl START_R { _ => None, } } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == STARTSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `TRANSMIT`"] + #[doc = "Transmit start"] #[inline(always)] pub fn is_transmit(&self) -> bool { *self == STARTSELECT_A::TRANSMIT } - #[doc = "Checks if the value of the field is `RF_LOW`"] + #[doc = "Detection of a low level on RF signal"] #[inline(always)] pub fn is_rf_low(&self) -> bool { *self == STARTSELECT_A::RF_LOW } - #[doc = "Checks if the value of the field is `RF_HIGH`"] + #[doc = "Detection of a high level on RF signal"] #[inline(always)] pub fn is_rf_high(&self) -> bool { *self == STARTSELECT_A::RF_HIGH } - #[doc = "Checks if the value of the field is `RF_FALLING`"] + #[doc = "Detection of a falling edge on RF signal"] #[inline(always)] pub fn is_rf_falling(&self) -> bool { *self == STARTSELECT_A::RF_FALLING } - #[doc = "Checks if the value of the field is `RF_RISING`"] + #[doc = "Detection of a rising edge on RF signal"] #[inline(always)] pub fn is_rf_rising(&self) -> bool { *self == STARTSELECT_A::RF_RISING } - #[doc = "Checks if the value of the field is `RF_LEVEL`"] + #[doc = "Detection of any level change on RF signal"] #[inline(always)] pub fn is_rf_level(&self) -> bool { *self == STARTSELECT_A::RF_LEVEL } - #[doc = "Checks if the value of the field is `RF_EDGE`"] + #[doc = "Detection of any edge on RF signal"] #[inline(always)] pub fn is_rf_edge(&self) -> bool { *self == STARTSELECT_A::RF_EDGE } - #[doc = "Checks if the value of the field is `CMP_0`"] + #[doc = "Compare 0"] #[inline(always)] pub fn is_cmp_0(&self) -> bool { *self == STARTSELECT_A::CMP_0 } } #[doc = "Field `START` writer - Receive Start Selection"] -pub type START_W<'a, const O: u8> = crate::FieldWriter<'a, RCMR_SPEC, 4, O, STARTSELECT_A>; -impl<'a, const O: u8> START_W<'a, O> { +pub type START_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, STARTSELECT_A>; +impl<'a, REG, const O: u8> START_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data."] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::CONTINUOUS) } #[doc = "Transmit start"] #[inline(always)] - pub fn transmit(self) -> &'a mut W { + pub fn transmit(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TRANSMIT) } #[doc = "Detection of a low level on RF signal"] #[inline(always)] - pub fn rf_low(self) -> &'a mut W { + pub fn rf_low(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RF_LOW) } #[doc = "Detection of a high level on RF signal"] #[inline(always)] - pub fn rf_high(self) -> &'a mut W { + pub fn rf_high(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RF_HIGH) } #[doc = "Detection of a falling edge on RF signal"] #[inline(always)] - pub fn rf_falling(self) -> &'a mut W { + pub fn rf_falling(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RF_FALLING) } #[doc = "Detection of a rising edge on RF signal"] #[inline(always)] - pub fn rf_rising(self) -> &'a mut W { + pub fn rf_rising(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RF_RISING) } #[doc = "Detection of any level change on RF signal"] #[inline(always)] - pub fn rf_level(self) -> &'a mut W { + pub fn rf_level(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RF_LEVEL) } #[doc = "Detection of any edge on RF signal"] #[inline(always)] - pub fn rf_edge(self) -> &'a mut W { + pub fn rf_edge(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RF_EDGE) } #[doc = "Compare 0"] #[inline(always)] - pub fn cmp_0(self) -> &'a mut W { + pub fn cmp_0(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::CMP_0) } } #[doc = "Field `STOP` reader - Receive Stop Selection"] pub type STOP_R = crate::BitReader; #[doc = "Field `STOP` writer - Receive Stop Selection"] -pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, RCMR_SPEC, O>; +pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STTDLY` reader - Receive Start Delay"] pub type STTDLY_R = crate::FieldReader; #[doc = "Field `STTDLY` writer - Receive Start Delay"] -pub type STTDLY_W<'a, const O: u8> = crate::FieldWriter<'a, RCMR_SPEC, 8, O>; +pub type STTDLY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PERIOD` reader - Receive Period Divider Selection"] pub type PERIOD_R = crate::FieldReader; #[doc = "Field `PERIOD` writer - Receive Period Divider Selection"] -pub type PERIOD_W<'a, const O: u8> = crate::FieldWriter<'a, RCMR_SPEC, 8, O>; +pub type PERIOD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:1 - Receive Clock Selection"] #[inline(always)] @@ -446,70 +430,67 @@ impl W { #[doc = "Bits 0:1 - Receive Clock Selection"] #[inline(always)] #[must_use] - pub fn cks(&mut self) -> CKS_W<0> { + pub fn cks(&mut self) -> CKS_W { CKS_W::new(self) } #[doc = "Bits 2:4 - Receive Clock Output Mode Selection"] #[inline(always)] #[must_use] - pub fn cko(&mut self) -> CKO_W<2> { + pub fn cko(&mut self) -> CKO_W { CKO_W::new(self) } #[doc = "Bit 5 - Receive Clock Inversion"] #[inline(always)] #[must_use] - pub fn cki(&mut self) -> CKI_W<5> { + pub fn cki(&mut self) -> CKI_W { CKI_W::new(self) } #[doc = "Bits 6:7 - Receive Clock Gating Selection"] #[inline(always)] #[must_use] - pub fn ckg(&mut self) -> CKG_W<6> { + pub fn ckg(&mut self) -> CKG_W { CKG_W::new(self) } #[doc = "Bits 8:11 - Receive Start Selection"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W<8> { + pub fn start(&mut self) -> START_W { START_W::new(self) } #[doc = "Bit 12 - Receive Stop Selection"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W<12> { + pub fn stop(&mut self) -> STOP_W { STOP_W::new(self) } #[doc = "Bits 16:23 - Receive Start Delay"] #[inline(always)] #[must_use] - pub fn sttdly(&mut self) -> STTDLY_W<16> { + pub fn sttdly(&mut self) -> STTDLY_W { STTDLY_W::new(self) } #[doc = "Bits 24:31 - Receive Period Divider Selection"] #[inline(always)] #[must_use] - pub fn period(&mut self) -> PERIOD_W<24> { + pub fn period(&mut self) -> PERIOD_W { PERIOD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Clock Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcmr](index.html) module"] +#[doc = "Receive Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rcmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rcmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RCMR_SPEC; impl crate::RegisterSpec for RCMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rcmr::R](R) reader structure"] -impl crate::Readable for RCMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rcmr::W](W) writer structure"] +#[doc = "`read()` method returns [`rcmr::R`](R) reader structure"] +impl crate::Readable for RCMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rcmr::W`](W) writer structure"] impl crate::Writable for RCMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/rfmr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/rfmr.rs index a3931ac1..39ab6f7c 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/rfmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/rfmr.rs @@ -1,59 +1,27 @@ #[doc = "Register `RFMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RFMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATLEN` reader - Data Length"] pub type DATLEN_R = crate::FieldReader; #[doc = "Field `DATLEN` writer - Data Length"] -pub type DATLEN_W<'a, const O: u8> = crate::FieldWriter<'a, RFMR_SPEC, 5, O>; +pub type DATLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `LOOP` reader - Loop Mode"] pub type LOOP_R = crate::BitReader; #[doc = "Field `LOOP` writer - Loop Mode"] -pub type LOOP_W<'a, const O: u8> = crate::BitWriter<'a, RFMR_SPEC, O>; +pub type LOOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSBF` reader - Most Significant Bit First"] pub type MSBF_R = crate::BitReader; #[doc = "Field `MSBF` writer - Most Significant Bit First"] -pub type MSBF_W<'a, const O: u8> = crate::BitWriter<'a, RFMR_SPEC, O>; +pub type MSBF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATNB` reader - Data Number per Frame"] pub type DATNB_R = crate::FieldReader; #[doc = "Field `DATNB` writer - Data Number per Frame"] -pub type DATNB_W<'a, const O: u8> = crate::FieldWriter<'a, RFMR_SPEC, 4, O>; +pub type DATNB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `FSLEN` reader - Receive Frame Sync Length"] pub type FSLEN_R = crate::FieldReader; #[doc = "Field `FSLEN` writer - Receive Frame Sync Length"] -pub type FSLEN_W<'a, const O: u8> = crate::FieldWriter<'a, RFMR_SPEC, 4, O>; +pub type FSLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `FSOS` reader - Receive Frame Sync Output Selection"] pub type FSOS_R = crate::FieldReader; #[doc = "Receive Frame Sync Output Selection\n\nValue on reset: 0"] @@ -96,68 +64,72 @@ impl FSOS_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None, RF pin is an input"] #[inline(always)] pub fn is_none(&self) -> bool { *self == FSOSSELECT_A::NONE } - #[doc = "Checks if the value of the field is `NEGATIVE`"] + #[doc = "Negative Pulse, RF pin is an output"] #[inline(always)] pub fn is_negative(&self) -> bool { *self == FSOSSELECT_A::NEGATIVE } - #[doc = "Checks if the value of the field is `POSITIVE`"] + #[doc = "Positive Pulse, RF pin is an output"] #[inline(always)] pub fn is_positive(&self) -> bool { *self == FSOSSELECT_A::POSITIVE } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Driven Low during data transfer, RF pin is an output"] #[inline(always)] pub fn is_low(&self) -> bool { *self == FSOSSELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Driven High during data transfer, RF pin is an output"] #[inline(always)] pub fn is_high(&self) -> bool { *self == FSOSSELECT_A::HIGH } - #[doc = "Checks if the value of the field is `TOGGLING`"] + #[doc = "Toggling at each start of data transfer, RF pin is an output"] #[inline(always)] pub fn is_toggling(&self) -> bool { *self == FSOSSELECT_A::TOGGLING } } #[doc = "Field `FSOS` writer - Receive Frame Sync Output Selection"] -pub type FSOS_W<'a, const O: u8> = crate::FieldWriter<'a, RFMR_SPEC, 3, O, FSOSSELECT_A>; -impl<'a, const O: u8> FSOS_W<'a, O> { +pub type FSOS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, FSOSSELECT_A>; +impl<'a, REG, const O: u8> FSOS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None, RF pin is an input"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::NONE) } #[doc = "Negative Pulse, RF pin is an output"] #[inline(always)] - pub fn negative(self) -> &'a mut W { + pub fn negative(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::NEGATIVE) } #[doc = "Positive Pulse, RF pin is an output"] #[inline(always)] - pub fn positive(self) -> &'a mut W { + pub fn positive(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::POSITIVE) } #[doc = "Driven Low during data transfer, RF pin is an output"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::LOW) } #[doc = "Driven High during data transfer, RF pin is an output"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::HIGH) } #[doc = "Toggling at each start of data transfer, RF pin is an output"] #[inline(always)] - pub fn toggling(self) -> &'a mut W { + pub fn toggling(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::TOGGLING) } } @@ -186,35 +158,38 @@ impl FSEDGE_R { true => FSEDGESELECT_A::NEGATIVE, } } - #[doc = "Checks if the value of the field is `POSITIVE`"] + #[doc = "Positive Edge Detection"] #[inline(always)] pub fn is_positive(&self) -> bool { *self == FSEDGESELECT_A::POSITIVE } - #[doc = "Checks if the value of the field is `NEGATIVE`"] + #[doc = "Negative Edge Detection"] #[inline(always)] pub fn is_negative(&self) -> bool { *self == FSEDGESELECT_A::NEGATIVE } } #[doc = "Field `FSEDGE` writer - Frame Sync Edge Detection"] -pub type FSEDGE_W<'a, const O: u8> = crate::BitWriter<'a, RFMR_SPEC, O, FSEDGESELECT_A>; -impl<'a, const O: u8> FSEDGE_W<'a, O> { +pub type FSEDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FSEDGESELECT_A>; +impl<'a, REG, const O: u8> FSEDGE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Positive Edge Detection"] #[inline(always)] - pub fn positive(self) -> &'a mut W { + pub fn positive(self) -> &'a mut crate::W { self.variant(FSEDGESELECT_A::POSITIVE) } #[doc = "Negative Edge Detection"] #[inline(always)] - pub fn negative(self) -> &'a mut W { + pub fn negative(self) -> &'a mut crate::W { self.variant(FSEDGESELECT_A::NEGATIVE) } } #[doc = "Field `FSLEN_EXT` reader - FSLEN Field Extension"] pub type FSLEN_EXT_R = crate::FieldReader; #[doc = "Field `FSLEN_EXT` writer - FSLEN Field Extension"] -pub type FSLEN_EXT_W<'a, const O: u8> = crate::FieldWriter<'a, RFMR_SPEC, 4, O>; +pub type FSLEN_EXT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:4 - Data Length"] #[inline(always)] @@ -261,70 +236,67 @@ impl W { #[doc = "Bits 0:4 - Data Length"] #[inline(always)] #[must_use] - pub fn datlen(&mut self) -> DATLEN_W<0> { + pub fn datlen(&mut self) -> DATLEN_W { DATLEN_W::new(self) } #[doc = "Bit 5 - Loop Mode"] #[inline(always)] #[must_use] - pub fn loop_(&mut self) -> LOOP_W<5> { + pub fn loop_(&mut self) -> LOOP_W { LOOP_W::new(self) } #[doc = "Bit 7 - Most Significant Bit First"] #[inline(always)] #[must_use] - pub fn msbf(&mut self) -> MSBF_W<7> { + pub fn msbf(&mut self) -> MSBF_W { MSBF_W::new(self) } #[doc = "Bits 8:11 - Data Number per Frame"] #[inline(always)] #[must_use] - pub fn datnb(&mut self) -> DATNB_W<8> { + pub fn datnb(&mut self) -> DATNB_W { DATNB_W::new(self) } #[doc = "Bits 16:19 - Receive Frame Sync Length"] #[inline(always)] #[must_use] - pub fn fslen(&mut self) -> FSLEN_W<16> { + pub fn fslen(&mut self) -> FSLEN_W { FSLEN_W::new(self) } #[doc = "Bits 20:22 - Receive Frame Sync Output Selection"] #[inline(always)] #[must_use] - pub fn fsos(&mut self) -> FSOS_W<20> { + pub fn fsos(&mut self) -> FSOS_W { FSOS_W::new(self) } #[doc = "Bit 24 - Frame Sync Edge Detection"] #[inline(always)] #[must_use] - pub fn fsedge(&mut self) -> FSEDGE_W<24> { + pub fn fsedge(&mut self) -> FSEDGE_W { FSEDGE_W::new(self) } #[doc = "Bits 28:31 - FSLEN Field Extension"] #[inline(always)] #[must_use] - pub fn fslen_ext(&mut self) -> FSLEN_EXT_W<28> { + pub fn fslen_ext(&mut self) -> FSLEN_EXT_W { FSLEN_EXT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receive Frame Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rfmr](index.html) module"] +#[doc = "Receive Frame Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rfmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rfmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RFMR_SPEC; impl crate::RegisterSpec for RFMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rfmr::R](R) reader structure"] -impl crate::Readable for RFMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rfmr::W](W) writer structure"] +#[doc = "`read()` method returns [`rfmr::R`](R) reader structure"] +impl crate::Readable for RFMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rfmr::W`](W) writer structure"] impl crate::Writable for RFMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/rhr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/rhr.rs index 6110c285..2ab22ede 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/rhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/rhr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDAT` reader - Receive Data"] pub type RDAT_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RDAT_R::new(self.bits) } } -#[doc = "Receive Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rhr](index.html) module"] +#[doc = "Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RHR_SPEC; impl crate::RegisterSpec for RHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rhr::R](R) reader structure"] -impl crate::Readable for RHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rhr::R`](R) reader structure"] +impl crate::Readable for RHR_SPEC {} #[doc = "`reset()` method sets RHR to value 0"] impl crate::Resettable for RHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/rshr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/rshr.rs index 596b6501..b9d3ee24 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/rshr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/rshr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RSHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RSDAT` reader - Receive Synchronization Data"] pub type RSDAT_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RSDAT_R::new((self.bits & 0xffff) as u16) } } -#[doc = "Receive Sync. Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rshr](index.html) module"] +#[doc = "Receive Sync. Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rshr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RSHR_SPEC; impl crate::RegisterSpec for RSHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rshr::R](R) reader structure"] -impl crate::Readable for RSHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rshr::R`](R) reader structure"] +impl crate::Readable for RSHR_SPEC {} #[doc = "`reset()` method sets RSHR to value 0"] impl crate::Resettable for RSHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/sr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/sr.rs index 5b312f43..fb64c09f 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXRDY` reader - Transmit Ready"] pub type TXRDY_R = crate::BitReader; #[doc = "Field `TXEMPTY` reader - Transmit Empty"] @@ -85,15 +72,13 @@ impl R { RXEN_R::new(((self.bits >> 17) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/tcmr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/tcmr.rs index f6531b44..bf263d30 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/tcmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/tcmr.rs @@ -1,39 +1,7 @@ #[doc = "Register `TCMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TCMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CKS` reader - Transmit Clock Selection"] pub type CKS_R = crate::FieldReader; #[doc = "Transmit Clock Selection\n\nValue on reset: 0"] @@ -67,38 +35,42 @@ impl CKS_R { _ => None, } } - #[doc = "Checks if the value of the field is `MCK`"] + #[doc = "Divided Clock"] #[inline(always)] pub fn is_mck(&self) -> bool { *self == CKSSELECT_A::MCK } - #[doc = "Checks if the value of the field is `RK`"] + #[doc = "RK Clock signal"] #[inline(always)] pub fn is_rk(&self) -> bool { *self == CKSSELECT_A::RK } - #[doc = "Checks if the value of the field is `TK`"] + #[doc = "TK pin"] #[inline(always)] pub fn is_tk(&self) -> bool { *self == CKSSELECT_A::TK } } #[doc = "Field `CKS` writer - Transmit Clock Selection"] -pub type CKS_W<'a, const O: u8> = crate::FieldWriter<'a, TCMR_SPEC, 2, O, CKSSELECT_A>; -impl<'a, const O: u8> CKS_W<'a, O> { +pub type CKS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CKSSELECT_A>; +impl<'a, REG, const O: u8> CKS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Divided Clock"] #[inline(always)] - pub fn mck(self) -> &'a mut W { + pub fn mck(self) -> &'a mut crate::W { self.variant(CKSSELECT_A::MCK) } #[doc = "RK Clock signal"] #[inline(always)] - pub fn rk(self) -> &'a mut W { + pub fn rk(self) -> &'a mut crate::W { self.variant(CKSSELECT_A::RK) } #[doc = "TK pin"] #[inline(always)] - pub fn tk(self) -> &'a mut W { + pub fn tk(self) -> &'a mut crate::W { self.variant(CKSSELECT_A::TK) } } @@ -135,45 +107,49 @@ impl CKO_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None, TK pin is an input"] #[inline(always)] pub fn is_none(&self) -> bool { *self == CKOSELECT_A::NONE } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "Continuous Transmit Clock, TK pin is an output"] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == CKOSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `TRANSFER`"] + #[doc = "Transmit Clock only during data transfers, TK pin is an output"] #[inline(always)] pub fn is_transfer(&self) -> bool { *self == CKOSELECT_A::TRANSFER } } #[doc = "Field `CKO` writer - Transmit Clock Output Mode Selection"] -pub type CKO_W<'a, const O: u8> = crate::FieldWriter<'a, TCMR_SPEC, 3, O, CKOSELECT_A>; -impl<'a, const O: u8> CKO_W<'a, O> { +pub type CKO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CKOSELECT_A>; +impl<'a, REG, const O: u8> CKO_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None, TK pin is an input"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(CKOSELECT_A::NONE) } #[doc = "Continuous Transmit Clock, TK pin is an output"] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(CKOSELECT_A::CONTINUOUS) } #[doc = "Transmit Clock only during data transfers, TK pin is an output"] #[inline(always)] - pub fn transfer(self) -> &'a mut W { + pub fn transfer(self) -> &'a mut crate::W { self.variant(CKOSELECT_A::TRANSFER) } } #[doc = "Field `CKI` reader - Transmit Clock Inversion"] pub type CKI_R = crate::BitReader; #[doc = "Field `CKI` writer - Transmit Clock Inversion"] -pub type CKI_W<'a, const O: u8> = crate::BitWriter<'a, TCMR_SPEC, O>; +pub type CKI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CKG` reader - Transmit Clock Gating Selection"] pub type CKG_R = crate::FieldReader; #[doc = "Transmit Clock Gating Selection\n\nValue on reset: 0"] @@ -207,38 +183,42 @@ impl CKG_R { _ => None, } } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "None"] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == CKGSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `EN_TF_LOW`"] + #[doc = "Transmit Clock enabled only if TF Low"] #[inline(always)] pub fn is_en_tf_low(&self) -> bool { *self == CKGSELECT_A::EN_TF_LOW } - #[doc = "Checks if the value of the field is `EN_TF_HIGH`"] + #[doc = "Transmit Clock enabled only if TF High"] #[inline(always)] pub fn is_en_tf_high(&self) -> bool { *self == CKGSELECT_A::EN_TF_HIGH } } #[doc = "Field `CKG` writer - Transmit Clock Gating Selection"] -pub type CKG_W<'a, const O: u8> = crate::FieldWriter<'a, TCMR_SPEC, 2, O, CKGSELECT_A>; -impl<'a, const O: u8> CKG_W<'a, O> { +pub type CKG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, CKGSELECT_A>; +impl<'a, REG, const O: u8> CKG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None"] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(CKGSELECT_A::CONTINUOUS) } #[doc = "Transmit Clock enabled only if TF Low"] #[inline(always)] - pub fn en_tf_low(self) -> &'a mut W { + pub fn en_tf_low(self) -> &'a mut crate::W { self.variant(CKGSELECT_A::EN_TF_LOW) } #[doc = "Transmit Clock enabled only if TF High"] #[inline(always)] - pub fn en_tf_high(self) -> &'a mut W { + pub fn en_tf_high(self) -> &'a mut crate::W { self.variant(CKGSELECT_A::EN_TF_HIGH) } } @@ -290,99 +270,103 @@ impl START_R { _ => None, } } - #[doc = "Checks if the value of the field is `CONTINUOUS`"] + #[doc = "Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data"] #[inline(always)] pub fn is_continuous(&self) -> bool { *self == STARTSELECT_A::CONTINUOUS } - #[doc = "Checks if the value of the field is `RECEIVE`"] + #[doc = "Receive start"] #[inline(always)] pub fn is_receive(&self) -> bool { *self == STARTSELECT_A::RECEIVE } - #[doc = "Checks if the value of the field is `TF_LOW`"] + #[doc = "Detection of a low level on TF signal"] #[inline(always)] pub fn is_tf_low(&self) -> bool { *self == STARTSELECT_A::TF_LOW } - #[doc = "Checks if the value of the field is `TF_HIGH`"] + #[doc = "Detection of a high level on TF signal"] #[inline(always)] pub fn is_tf_high(&self) -> bool { *self == STARTSELECT_A::TF_HIGH } - #[doc = "Checks if the value of the field is `TF_FALLING`"] + #[doc = "Detection of a falling edge on TF signal"] #[inline(always)] pub fn is_tf_falling(&self) -> bool { *self == STARTSELECT_A::TF_FALLING } - #[doc = "Checks if the value of the field is `TF_RISING`"] + #[doc = "Detection of a rising edge on TF signal"] #[inline(always)] pub fn is_tf_rising(&self) -> bool { *self == STARTSELECT_A::TF_RISING } - #[doc = "Checks if the value of the field is `TF_LEVEL`"] + #[doc = "Detection of any level change on TF signal"] #[inline(always)] pub fn is_tf_level(&self) -> bool { *self == STARTSELECT_A::TF_LEVEL } - #[doc = "Checks if the value of the field is `TF_EDGE`"] + #[doc = "Detection of any edge on TF signal"] #[inline(always)] pub fn is_tf_edge(&self) -> bool { *self == STARTSELECT_A::TF_EDGE } } #[doc = "Field `START` writer - Transmit Start Selection"] -pub type START_W<'a, const O: u8> = crate::FieldWriter<'a, TCMR_SPEC, 4, O, STARTSELECT_A>; -impl<'a, const O: u8> START_W<'a, O> { +pub type START_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, STARTSELECT_A>; +impl<'a, REG, const O: u8> START_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data"] #[inline(always)] - pub fn continuous(self) -> &'a mut W { + pub fn continuous(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::CONTINUOUS) } #[doc = "Receive start"] #[inline(always)] - pub fn receive(self) -> &'a mut W { + pub fn receive(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::RECEIVE) } #[doc = "Detection of a low level on TF signal"] #[inline(always)] - pub fn tf_low(self) -> &'a mut W { + pub fn tf_low(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TF_LOW) } #[doc = "Detection of a high level on TF signal"] #[inline(always)] - pub fn tf_high(self) -> &'a mut W { + pub fn tf_high(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TF_HIGH) } #[doc = "Detection of a falling edge on TF signal"] #[inline(always)] - pub fn tf_falling(self) -> &'a mut W { + pub fn tf_falling(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TF_FALLING) } #[doc = "Detection of a rising edge on TF signal"] #[inline(always)] - pub fn tf_rising(self) -> &'a mut W { + pub fn tf_rising(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TF_RISING) } #[doc = "Detection of any level change on TF signal"] #[inline(always)] - pub fn tf_level(self) -> &'a mut W { + pub fn tf_level(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TF_LEVEL) } #[doc = "Detection of any edge on TF signal"] #[inline(always)] - pub fn tf_edge(self) -> &'a mut W { + pub fn tf_edge(self) -> &'a mut crate::W { self.variant(STARTSELECT_A::TF_EDGE) } } #[doc = "Field `STTDLY` reader - Transmit Start Delay"] pub type STTDLY_R = crate::FieldReader; #[doc = "Field `STTDLY` writer - Transmit Start Delay"] -pub type STTDLY_W<'a, const O: u8> = crate::FieldWriter<'a, TCMR_SPEC, 8, O>; +pub type STTDLY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PERIOD` reader - Transmit Period Divider Selection"] pub type PERIOD_R = crate::FieldReader; #[doc = "Field `PERIOD` writer - Transmit Period Divider Selection"] -pub type PERIOD_W<'a, const O: u8> = crate::FieldWriter<'a, TCMR_SPEC, 8, O>; +pub type PERIOD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:1 - Transmit Clock Selection"] #[inline(always)] @@ -424,64 +408,61 @@ impl W { #[doc = "Bits 0:1 - Transmit Clock Selection"] #[inline(always)] #[must_use] - pub fn cks(&mut self) -> CKS_W<0> { + pub fn cks(&mut self) -> CKS_W { CKS_W::new(self) } #[doc = "Bits 2:4 - Transmit Clock Output Mode Selection"] #[inline(always)] #[must_use] - pub fn cko(&mut self) -> CKO_W<2> { + pub fn cko(&mut self) -> CKO_W { CKO_W::new(self) } #[doc = "Bit 5 - Transmit Clock Inversion"] #[inline(always)] #[must_use] - pub fn cki(&mut self) -> CKI_W<5> { + pub fn cki(&mut self) -> CKI_W { CKI_W::new(self) } #[doc = "Bits 6:7 - Transmit Clock Gating Selection"] #[inline(always)] #[must_use] - pub fn ckg(&mut self) -> CKG_W<6> { + pub fn ckg(&mut self) -> CKG_W { CKG_W::new(self) } #[doc = "Bits 8:11 - Transmit Start Selection"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W<8> { + pub fn start(&mut self) -> START_W { START_W::new(self) } #[doc = "Bits 16:23 - Transmit Start Delay"] #[inline(always)] #[must_use] - pub fn sttdly(&mut self) -> STTDLY_W<16> { + pub fn sttdly(&mut self) -> STTDLY_W { STTDLY_W::new(self) } #[doc = "Bits 24:31 - Transmit Period Divider Selection"] #[inline(always)] #[must_use] - pub fn period(&mut self) -> PERIOD_W<24> { + pub fn period(&mut self) -> PERIOD_W { PERIOD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Clock Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcmr](index.html) module"] +#[doc = "Transmit Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TCMR_SPEC; impl crate::RegisterSpec for TCMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tcmr::R](R) reader structure"] -impl crate::Readable for TCMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tcmr::W](W) writer structure"] +#[doc = "`read()` method returns [`tcmr::R`](R) reader structure"] +impl crate::Readable for TCMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tcmr::W`](W) writer structure"] impl crate::Writable for TCMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/tfmr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/tfmr.rs index 17239821..d943a856 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/tfmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/tfmr.rs @@ -1,59 +1,27 @@ #[doc = "Register `TFMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TFMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATLEN` reader - Data Length"] pub type DATLEN_R = crate::FieldReader; #[doc = "Field `DATLEN` writer - Data Length"] -pub type DATLEN_W<'a, const O: u8> = crate::FieldWriter<'a, TFMR_SPEC, 5, O>; +pub type DATLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>; #[doc = "Field `DATDEF` reader - Data Default Value"] pub type DATDEF_R = crate::BitReader; #[doc = "Field `DATDEF` writer - Data Default Value"] -pub type DATDEF_W<'a, const O: u8> = crate::BitWriter<'a, TFMR_SPEC, O>; +pub type DATDEF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSBF` reader - Most Significant Bit First"] pub type MSBF_R = crate::BitReader; #[doc = "Field `MSBF` writer - Most Significant Bit First"] -pub type MSBF_W<'a, const O: u8> = crate::BitWriter<'a, TFMR_SPEC, O>; +pub type MSBF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATNB` reader - Data Number per Frame"] pub type DATNB_R = crate::FieldReader; #[doc = "Field `DATNB` writer - Data Number per Frame"] -pub type DATNB_W<'a, const O: u8> = crate::FieldWriter<'a, TFMR_SPEC, 4, O>; +pub type DATNB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `FSLEN` reader - Transmit Frame Sync Length"] pub type FSLEN_R = crate::FieldReader; #[doc = "Field `FSLEN` writer - Transmit Frame Sync Length"] -pub type FSLEN_W<'a, const O: u8> = crate::FieldWriter<'a, TFMR_SPEC, 4, O>; +pub type FSLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `FSOS` reader - Transmit Frame Sync Output Selection"] pub type FSOS_R = crate::FieldReader; #[doc = "Transmit Frame Sync Output Selection\n\nValue on reset: 0"] @@ -96,75 +64,79 @@ impl FSOS_R { _ => None, } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None, TF pin is an input"] #[inline(always)] pub fn is_none(&self) -> bool { *self == FSOSSELECT_A::NONE } - #[doc = "Checks if the value of the field is `NEGATIVE`"] + #[doc = "Negative Pulse, TF pin is an output"] #[inline(always)] pub fn is_negative(&self) -> bool { *self == FSOSSELECT_A::NEGATIVE } - #[doc = "Checks if the value of the field is `POSITIVE`"] + #[doc = "Positive Pulse, TF pin is an output"] #[inline(always)] pub fn is_positive(&self) -> bool { *self == FSOSSELECT_A::POSITIVE } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "Driven Low during data transfer"] #[inline(always)] pub fn is_low(&self) -> bool { *self == FSOSSELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "Driven High during data transfer"] #[inline(always)] pub fn is_high(&self) -> bool { *self == FSOSSELECT_A::HIGH } - #[doc = "Checks if the value of the field is `TOGGLING`"] + #[doc = "Toggling at each start of data transfer"] #[inline(always)] pub fn is_toggling(&self) -> bool { *self == FSOSSELECT_A::TOGGLING } } #[doc = "Field `FSOS` writer - Transmit Frame Sync Output Selection"] -pub type FSOS_W<'a, const O: u8> = crate::FieldWriter<'a, TFMR_SPEC, 3, O, FSOSSELECT_A>; -impl<'a, const O: u8> FSOS_W<'a, O> { +pub type FSOS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, FSOSSELECT_A>; +impl<'a, REG, const O: u8> FSOS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None, TF pin is an input"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::NONE) } #[doc = "Negative Pulse, TF pin is an output"] #[inline(always)] - pub fn negative(self) -> &'a mut W { + pub fn negative(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::NEGATIVE) } #[doc = "Positive Pulse, TF pin is an output"] #[inline(always)] - pub fn positive(self) -> &'a mut W { + pub fn positive(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::POSITIVE) } #[doc = "Driven Low during data transfer"] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::LOW) } #[doc = "Driven High during data transfer"] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::HIGH) } #[doc = "Toggling at each start of data transfer"] #[inline(always)] - pub fn toggling(self) -> &'a mut W { + pub fn toggling(self) -> &'a mut crate::W { self.variant(FSOSSELECT_A::TOGGLING) } } #[doc = "Field `FSDEN` reader - Frame Sync Data Enable"] pub type FSDEN_R = crate::BitReader; #[doc = "Field `FSDEN` writer - Frame Sync Data Enable"] -pub type FSDEN_W<'a, const O: u8> = crate::BitWriter<'a, TFMR_SPEC, O>; +pub type FSDEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSEDGE` reader - Frame Sync Edge Detection"] pub type FSEDGE_R = crate::BitReader; #[doc = "Frame Sync Edge Detection\n\nValue on reset: 0"] @@ -190,35 +162,38 @@ impl FSEDGE_R { true => FSEDGESELECT_A::NEGATIVE, } } - #[doc = "Checks if the value of the field is `POSITIVE`"] + #[doc = "Positive Edge Detection"] #[inline(always)] pub fn is_positive(&self) -> bool { *self == FSEDGESELECT_A::POSITIVE } - #[doc = "Checks if the value of the field is `NEGATIVE`"] + #[doc = "Negative Edge Detection"] #[inline(always)] pub fn is_negative(&self) -> bool { *self == FSEDGESELECT_A::NEGATIVE } } #[doc = "Field `FSEDGE` writer - Frame Sync Edge Detection"] -pub type FSEDGE_W<'a, const O: u8> = crate::BitWriter<'a, TFMR_SPEC, O, FSEDGESELECT_A>; -impl<'a, const O: u8> FSEDGE_W<'a, O> { +pub type FSEDGE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FSEDGESELECT_A>; +impl<'a, REG, const O: u8> FSEDGE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Positive Edge Detection"] #[inline(always)] - pub fn positive(self) -> &'a mut W { + pub fn positive(self) -> &'a mut crate::W { self.variant(FSEDGESELECT_A::POSITIVE) } #[doc = "Negative Edge Detection"] #[inline(always)] - pub fn negative(self) -> &'a mut W { + pub fn negative(self) -> &'a mut crate::W { self.variant(FSEDGESELECT_A::NEGATIVE) } } #[doc = "Field `FSLEN_EXT` reader - FSLEN Field Extension"] pub type FSLEN_EXT_R = crate::FieldReader; #[doc = "Field `FSLEN_EXT` writer - FSLEN Field Extension"] -pub type FSLEN_EXT_W<'a, const O: u8> = crate::FieldWriter<'a, TFMR_SPEC, 4, O>; +pub type FSLEN_EXT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:4 - Data Length"] #[inline(always)] @@ -270,76 +245,73 @@ impl W { #[doc = "Bits 0:4 - Data Length"] #[inline(always)] #[must_use] - pub fn datlen(&mut self) -> DATLEN_W<0> { + pub fn datlen(&mut self) -> DATLEN_W { DATLEN_W::new(self) } #[doc = "Bit 5 - Data Default Value"] #[inline(always)] #[must_use] - pub fn datdef(&mut self) -> DATDEF_W<5> { + pub fn datdef(&mut self) -> DATDEF_W { DATDEF_W::new(self) } #[doc = "Bit 7 - Most Significant Bit First"] #[inline(always)] #[must_use] - pub fn msbf(&mut self) -> MSBF_W<7> { + pub fn msbf(&mut self) -> MSBF_W { MSBF_W::new(self) } #[doc = "Bits 8:11 - Data Number per Frame"] #[inline(always)] #[must_use] - pub fn datnb(&mut self) -> DATNB_W<8> { + pub fn datnb(&mut self) -> DATNB_W { DATNB_W::new(self) } #[doc = "Bits 16:19 - Transmit Frame Sync Length"] #[inline(always)] #[must_use] - pub fn fslen(&mut self) -> FSLEN_W<16> { + pub fn fslen(&mut self) -> FSLEN_W { FSLEN_W::new(self) } #[doc = "Bits 20:22 - Transmit Frame Sync Output Selection"] #[inline(always)] #[must_use] - pub fn fsos(&mut self) -> FSOS_W<20> { + pub fn fsos(&mut self) -> FSOS_W { FSOS_W::new(self) } #[doc = "Bit 23 - Frame Sync Data Enable"] #[inline(always)] #[must_use] - pub fn fsden(&mut self) -> FSDEN_W<23> { + pub fn fsden(&mut self) -> FSDEN_W { FSDEN_W::new(self) } #[doc = "Bit 24 - Frame Sync Edge Detection"] #[inline(always)] #[must_use] - pub fn fsedge(&mut self) -> FSEDGE_W<24> { + pub fn fsedge(&mut self) -> FSEDGE_W { FSEDGE_W::new(self) } #[doc = "Bits 28:31 - FSLEN Field Extension"] #[inline(always)] #[must_use] - pub fn fslen_ext(&mut self) -> FSLEN_EXT_W<28> { + pub fn fslen_ext(&mut self) -> FSLEN_EXT_W { FSLEN_EXT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Frame Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tfmr](index.html) module"] +#[doc = "Transmit Frame Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tfmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tfmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TFMR_SPEC; impl crate::RegisterSpec for TFMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tfmr::R](R) reader structure"] -impl crate::Readable for TFMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tfmr::W](W) writer structure"] +#[doc = "`read()` method returns [`tfmr::R`](R) reader structure"] +impl crate::Readable for TFMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tfmr::W`](W) writer structure"] impl crate::Writable for TFMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/thr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/thr.rs index 1fe1b6bd..6b96a749 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/thr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/thr.rs @@ -1,48 +1,28 @@ #[doc = "Register `THR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TDAT` writer - Transmit Data"] -pub type TDAT_W<'a, const O: u8> = crate::FieldWriter<'a, THR_SPEC, 32, O, u32>; +pub type TDAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl W { #[doc = "Bits 0:31 - Transmit Data"] #[inline(always)] #[must_use] - pub fn tdat(&mut self) -> TDAT_W<0> { + pub fn tdat(&mut self) -> TDAT_W { TDAT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Holding Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [thr](index.html) module"] +#[doc = "Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct THR_SPEC; impl crate::RegisterSpec for THR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [thr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`thr::W`](W) writer structure"] impl crate::Writable for THR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/tshr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/tshr.rs index ae531e45..4d321893 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/tshr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/tshr.rs @@ -1,43 +1,11 @@ #[doc = "Register `TSHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `TSHR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TSDAT` reader - Transmit Synchronization Data"] pub type TSDAT_R = crate::FieldReader; #[doc = "Field `TSDAT` writer - Transmit Synchronization Data"] -pub type TSDAT_W<'a, const O: u8> = crate::FieldWriter<'a, TSHR_SPEC, 16, O, u16>; +pub type TSDAT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Transmit Synchronization Data"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Transmit Synchronization Data"] #[inline(always)] #[must_use] - pub fn tsdat(&mut self) -> TSDAT_W<0> { + pub fn tsdat(&mut self) -> TSDAT_W { TSDAT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Sync. Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tshr](index.html) module"] +#[doc = "Transmit Sync. Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tshr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tshr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct TSHR_SPEC; impl crate::RegisterSpec for TSHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [tshr::R](R) reader structure"] -impl crate::Readable for TSHR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [tshr::W](W) writer structure"] +#[doc = "`read()` method returns [`tshr::R`](R) reader structure"] +impl crate::Readable for TSHR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tshr::W`](W) writer structure"] impl crate::Writable for TSHR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/wpmr.rs index 16627f18..928b7c54 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/ssc/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/ssc/wpsr.rs index e6008ec5..99598c6b 100644 --- a/arch/cortex-m/samv71q21-pac/src/ssc/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/ssc/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protect Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/supc.rs b/arch/cortex-m/samv71q21-pac/src/supc.rs index 6d65613d..9377104c 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc.rs @@ -17,31 +17,38 @@ pub struct RegisterBlock { #[doc = "0xd4 - Write Protection Mode Register"] pub sysc_wpmr: SYSC_WPMR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Supply Controller Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Supply Controller Control Register"] pub mod cr; -#[doc = "SMMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SMMR (rw) register accessor: Supply Controller Supply Monitor Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smmr`] +module"] pub type SMMR = crate::Reg; #[doc = "Supply Controller Supply Monitor Mode Register"] pub mod smmr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Supply Controller Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Supply Controller Mode Register"] pub mod mr; -#[doc = "WUMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WUMR (rw) register accessor: Supply Controller Wake-up Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wumr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wumr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wumr`] +module"] pub type WUMR = crate::Reg; #[doc = "Supply Controller Wake-up Mode Register"] pub mod wumr; -#[doc = "WUIR (rw) register accessor: an alias for `Reg`"] +#[doc = "WUIR (rw) register accessor: Supply Controller Wake-up Inputs Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wuir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wuir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wuir`] +module"] pub type WUIR = crate::Reg; #[doc = "Supply Controller Wake-up Inputs Register"] pub mod wuir; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Supply Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Supply Controller Status Register"] pub mod sr; -#[doc = "SYSC_WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SYSC_WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysc_wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysc_wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sysc_wpmr`] +module"] pub type SYSC_WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod sysc_wpmr; diff --git a/arch/cortex-m/samv71q21-pac/src/supc/cr.rs b/arch/cortex-m/samv71q21-pac/src/supc/cr.rs index baeb6d56..1eb1d78e 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/cr.rs @@ -1,24 +1,5 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Voltage Regulator Off\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] pub enum VROFFSELECT_AW { @@ -34,16 +15,19 @@ impl From for bool { } } #[doc = "Field `VROFF` writer - Voltage Regulator Off"] -pub type VROFF_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O, VROFFSELECT_AW>; -impl<'a, const O: u8> VROFF_W<'a, O> { +pub type VROFF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, VROFFSELECT_AW>; +impl<'a, REG, const O: u8> VROFF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No effect."] #[inline(always)] - pub fn no_effect(self) -> &'a mut W { + pub fn no_effect(self) -> &'a mut crate::W { self.variant(VROFFSELECT_AW::NO_EFFECT) } #[doc = "If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator."] #[inline(always)] - pub fn stop_vreg(self) -> &'a mut W { + pub fn stop_vreg(self) -> &'a mut crate::W { self.variant(VROFFSELECT_AW::STOP_VREG) } } @@ -62,16 +46,19 @@ impl From for bool { } } #[doc = "Field `XTALSEL` writer - Crystal Oscillator Select"] -pub type XTALSEL_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O, XTALSELSELECT_AW>; -impl<'a, const O: u8> XTALSEL_W<'a, O> { +pub type XTALSEL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, XTALSELSELECT_AW>; +impl<'a, REG, const O: u8> XTALSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No effect."] #[inline(always)] - pub fn no_effect(self) -> &'a mut W { + pub fn no_effect(self) -> &'a mut crate::W { self.variant(XTALSELSELECT_AW::NO_EFFECT) } #[doc = "If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output."] #[inline(always)] - pub fn crystal_sel(self) -> &'a mut W { + pub fn crystal_sel(self) -> &'a mut crate::W { self.variant(XTALSELSELECT_AW::CRYSTAL_SEL) } } @@ -92,11 +79,15 @@ impl crate::FieldSpec for KEYSELECT_AW { type Ux = u8; } #[doc = "Field `KEY` writer - Password"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 8, O, KEYSELECT_AW>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_AW>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_AW::PASSWD) } } @@ -104,36 +95,35 @@ impl W { #[doc = "Bit 2 - Voltage Regulator Off"] #[inline(always)] #[must_use] - pub fn vroff(&mut self) -> VROFF_W<2> { + pub fn vroff(&mut self) -> VROFF_W { VROFF_W::new(self) } #[doc = "Bit 3 - Crystal Oscillator Select"] #[inline(always)] #[must_use] - pub fn xtalsel(&mut self) -> XTALSEL_W<3> { + pub fn xtalsel(&mut self) -> XTALSEL_W { XTALSEL_W::new(self) } #[doc = "Bits 24:31 - Password"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<24> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Supply Controller Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Supply Controller Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/supc/mr.rs b/arch/cortex-m/samv71q21-pac/src/supc/mr.rs index a44eba06..63385a98 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BODRSTEN` reader - Brownout Detector Reset Enable"] pub type BODRSTEN_R = crate::BitReader; #[doc = "Brownout Detector Reset Enable\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl BODRSTEN_R { true => BODRSTENSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The core reset signal vddcore_nreset is not affected when a brownout detection occurs."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == BODRSTENSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The core reset signal, vddcore_nreset is asserted when a brownout detection occurs."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == BODRSTENSELECT_A::ENABLE } } #[doc = "Field `BODRSTEN` writer - Brownout Detector Reset Enable"] -pub type BODRSTEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, BODRSTENSELECT_A>; -impl<'a, const O: u8> BODRSTEN_W<'a, O> { +pub type BODRSTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BODRSTENSELECT_A>; +impl<'a, REG, const O: u8> BODRSTEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The core reset signal vddcore_nreset is not affected when a brownout detection occurs."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(BODRSTENSELECT_A::NOT_ENABLE) } #[doc = "The core reset signal, vddcore_nreset is asserted when a brownout detection occurs."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(BODRSTENSELECT_A::ENABLE) } } @@ -109,28 +80,31 @@ impl BODDIS_R { true => BODDISSELECT_A::DISABLE, } } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The core brownout detector is enabled."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == BODDISSELECT_A::ENABLE } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The core brownout detector is disabled."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == BODDISSELECT_A::DISABLE } } #[doc = "Field `BODDIS` writer - Brownout Detector Disable"] -pub type BODDIS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, BODDISSELECT_A>; -impl<'a, const O: u8> BODDIS_W<'a, O> { +pub type BODDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BODDISSELECT_A>; +impl<'a, REG, const O: u8> BODDIS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The core brownout detector is enabled."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(BODDISSELECT_A::ENABLE) } #[doc = "The core brownout detector is disabled."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(BODDISSELECT_A::DISABLE) } } @@ -159,35 +133,38 @@ impl ONREG_R { true => ONREGSELECT_A::ONREG_USED, } } - #[doc = "Checks if the value of the field is `ONREG_UNUSED`"] + #[doc = "Internal voltage regulator is not used (external power supply is used)."] #[inline(always)] pub fn is_onreg_unused(&self) -> bool { *self == ONREGSELECT_A::ONREG_UNUSED } - #[doc = "Checks if the value of the field is `ONREG_USED`"] + #[doc = "Internal voltage regulator is used."] #[inline(always)] pub fn is_onreg_used(&self) -> bool { *self == ONREGSELECT_A::ONREG_USED } } #[doc = "Field `ONREG` writer - Voltage Regulator Enable"] -pub type ONREG_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, ONREGSELECT_A>; -impl<'a, const O: u8> ONREG_W<'a, O> { +pub type ONREG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ONREGSELECT_A>; +impl<'a, REG, const O: u8> ONREG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Internal voltage regulator is not used (external power supply is used)."] #[inline(always)] - pub fn onreg_unused(self) -> &'a mut W { + pub fn onreg_unused(self) -> &'a mut crate::W { self.variant(ONREGSELECT_A::ONREG_UNUSED) } #[doc = "Internal voltage regulator is used."] #[inline(always)] - pub fn onreg_used(self) -> &'a mut W { + pub fn onreg_used(self) -> &'a mut crate::W { self.variant(ONREGSELECT_A::ONREG_USED) } } #[doc = "Field `BKUPRETON` reader - SRAM On In Backup Mode"] pub type BKUPRETON_R = crate::BitReader; #[doc = "Field `BKUPRETON` writer - SRAM On In Backup Mode"] -pub type BKUPRETON_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type BKUPRETON_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OSCBYPASS` reader - Oscillator Bypass"] pub type OSCBYPASS_R = crate::BitReader; #[doc = "Oscillator Bypass\n\nValue on reset: 0"] @@ -213,28 +190,31 @@ impl OSCBYPASS_R { true => OSCBYPASSSELECT_A::BYPASS, } } - #[doc = "Checks if the value of the field is `NO_EFFECT`"] + #[doc = "No effect. Clock selection depends on the value of XTALSEL (SUPC_CR)."] #[inline(always)] pub fn is_no_effect(&self) -> bool { *self == OSCBYPASSSELECT_A::NO_EFFECT } - #[doc = "Checks if the value of the field is `BYPASS`"] + #[doc = "The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL."] #[inline(always)] pub fn is_bypass(&self) -> bool { *self == OSCBYPASSSELECT_A::BYPASS } } #[doc = "Field `OSCBYPASS` writer - Oscillator Bypass"] -pub type OSCBYPASS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, OSCBYPASSSELECT_A>; -impl<'a, const O: u8> OSCBYPASS_W<'a, O> { +pub type OSCBYPASS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, OSCBYPASSSELECT_A>; +impl<'a, REG, const O: u8> OSCBYPASS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No effect. Clock selection depends on the value of XTALSEL (SUPC_CR)."] #[inline(always)] - pub fn no_effect(self) -> &'a mut W { + pub fn no_effect(self) -> &'a mut crate::W { self.variant(OSCBYPASSSELECT_A::NO_EFFECT) } #[doc = "The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL."] #[inline(always)] - pub fn bypass(self) -> &'a mut W { + pub fn bypass(self) -> &'a mut crate::W { self.variant(OSCBYPASSSELECT_A::BYPASS) } } @@ -265,18 +245,22 @@ impl KEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == KEYSELECT_A::PASSWD } } #[doc = "Field `KEY` writer - Password Key"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 8, O, KEYSELECT_A>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_A>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_A::PASSWD) } } @@ -316,58 +300,55 @@ impl W { #[doc = "Bit 12 - Brownout Detector Reset Enable"] #[inline(always)] #[must_use] - pub fn bodrsten(&mut self) -> BODRSTEN_W<12> { + pub fn bodrsten(&mut self) -> BODRSTEN_W { BODRSTEN_W::new(self) } #[doc = "Bit 13 - Brownout Detector Disable"] #[inline(always)] #[must_use] - pub fn boddis(&mut self) -> BODDIS_W<13> { + pub fn boddis(&mut self) -> BODDIS_W { BODDIS_W::new(self) } #[doc = "Bit 14 - Voltage Regulator Enable"] #[inline(always)] #[must_use] - pub fn onreg(&mut self) -> ONREG_W<14> { + pub fn onreg(&mut self) -> ONREG_W { ONREG_W::new(self) } #[doc = "Bit 17 - SRAM On In Backup Mode"] #[inline(always)] #[must_use] - pub fn bkupreton(&mut self) -> BKUPRETON_W<17> { + pub fn bkupreton(&mut self) -> BKUPRETON_W { BKUPRETON_W::new(self) } #[doc = "Bit 20 - Oscillator Bypass"] #[inline(always)] #[must_use] - pub fn oscbypass(&mut self) -> OSCBYPASS_W<20> { + pub fn oscbypass(&mut self) -> OSCBYPASS_W { OSCBYPASS_W::new(self) } #[doc = "Bits 24:31 - Password Key"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<24> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Supply Controller Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Supply Controller Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/supc/smmr.rs b/arch/cortex-m/samv71q21-pac/src/supc/smmr.rs index 7f1837cb..2f30f044 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/smmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/smmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SMMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SMMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMTH` reader - Supply Monitor Threshold"] pub type SMTH_R = crate::FieldReader; #[doc = "Field `SMTH` writer - Supply Monitor Threshold"] -pub type SMTH_W<'a, const O: u8> = crate::FieldWriter<'a, SMMR_SPEC, 4, O>; +pub type SMTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `SMSMPL` reader - Supply Monitor Sampling Period"] pub type SMSMPL_R = crate::FieldReader; #[doc = "Supply Monitor Sampling Period\n\nValue on reset: 0"] @@ -77,58 +45,62 @@ impl SMSMPL_R { _ => None, } } - #[doc = "Checks if the value of the field is `SMD`"] + #[doc = "Supply Monitor disabled"] #[inline(always)] pub fn is_smd(&self) -> bool { *self == SMSMPLSELECT_A::SMD } - #[doc = "Checks if the value of the field is `CSM`"] + #[doc = "Continuous Supply Monitor"] #[inline(always)] pub fn is_csm(&self) -> bool { *self == SMSMPLSELECT_A::CSM } - #[doc = "Checks if the value of the field is `_32SLCK`"] + #[doc = "Supply Monitor enabled one SLCK period every 32 SLCK periods"] #[inline(always)] pub fn is_32slck(&self) -> bool { *self == SMSMPLSELECT_A::_32SLCK } - #[doc = "Checks if the value of the field is `_256SLCK`"] + #[doc = "Supply Monitor enabled one SLCK period every 256 SLCK periods"] #[inline(always)] pub fn is_256slck(&self) -> bool { *self == SMSMPLSELECT_A::_256SLCK } - #[doc = "Checks if the value of the field is `_2048SLCK`"] + #[doc = "Supply Monitor enabled one SLCK period every 2,048 SLCK periods"] #[inline(always)] pub fn is_2048slck(&self) -> bool { *self == SMSMPLSELECT_A::_2048SLCK } } #[doc = "Field `SMSMPL` writer - Supply Monitor Sampling Period"] -pub type SMSMPL_W<'a, const O: u8> = crate::FieldWriter<'a, SMMR_SPEC, 3, O, SMSMPLSELECT_A>; -impl<'a, const O: u8> SMSMPL_W<'a, O> { +pub type SMSMPL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, SMSMPLSELECT_A>; +impl<'a, REG, const O: u8> SMSMPL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Supply Monitor disabled"] #[inline(always)] - pub fn smd(self) -> &'a mut W { + pub fn smd(self) -> &'a mut crate::W { self.variant(SMSMPLSELECT_A::SMD) } #[doc = "Continuous Supply Monitor"] #[inline(always)] - pub fn csm(self) -> &'a mut W { + pub fn csm(self) -> &'a mut crate::W { self.variant(SMSMPLSELECT_A::CSM) } #[doc = "Supply Monitor enabled one SLCK period every 32 SLCK periods"] #[inline(always)] - pub fn _32slck(self) -> &'a mut W { + pub fn _32slck(self) -> &'a mut crate::W { self.variant(SMSMPLSELECT_A::_32SLCK) } #[doc = "Supply Monitor enabled one SLCK period every 256 SLCK periods"] #[inline(always)] - pub fn _256slck(self) -> &'a mut W { + pub fn _256slck(self) -> &'a mut crate::W { self.variant(SMSMPLSELECT_A::_256SLCK) } #[doc = "Supply Monitor enabled one SLCK period every 2,048 SLCK periods"] #[inline(always)] - pub fn _2048slck(self) -> &'a mut W { + pub fn _2048slck(self) -> &'a mut crate::W { self.variant(SMSMPLSELECT_A::_2048SLCK) } } @@ -157,28 +129,31 @@ impl SMRSTEN_R { true => SMRSTENSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == SMRSTENSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == SMRSTENSELECT_A::ENABLE } } #[doc = "Field `SMRSTEN` writer - Supply Monitor Reset Enable"] -pub type SMRSTEN_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O, SMRSTENSELECT_A>; -impl<'a, const O: u8> SMRSTEN_W<'a, O> { +pub type SMRSTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SMRSTENSELECT_A>; +impl<'a, REG, const O: u8> SMRSTEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(SMRSTENSELECT_A::NOT_ENABLE) } #[doc = "The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(SMRSTENSELECT_A::ENABLE) } } @@ -207,28 +182,31 @@ impl SMIEN_R { true => SMIENSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The SUPC interrupt signal is not affected when a supply monitor detection occurs."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == SMIENSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The SUPC interrupt signal is asserted when a supply monitor detection occurs."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == SMIENSELECT_A::ENABLE } } #[doc = "Field `SMIEN` writer - Supply Monitor Interrupt Enable"] -pub type SMIEN_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O, SMIENSELECT_A>; -impl<'a, const O: u8> SMIEN_W<'a, O> { +pub type SMIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SMIENSELECT_A>; +impl<'a, REG, const O: u8> SMIEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The SUPC interrupt signal is not affected when a supply monitor detection occurs."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(SMIENSELECT_A::NOT_ENABLE) } #[doc = "The SUPC interrupt signal is asserted when a supply monitor detection occurs."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(SMIENSELECT_A::ENABLE) } } @@ -258,46 +236,43 @@ impl W { #[doc = "Bits 0:3 - Supply Monitor Threshold"] #[inline(always)] #[must_use] - pub fn smth(&mut self) -> SMTH_W<0> { + pub fn smth(&mut self) -> SMTH_W { SMTH_W::new(self) } #[doc = "Bits 8:10 - Supply Monitor Sampling Period"] #[inline(always)] #[must_use] - pub fn smsmpl(&mut self) -> SMSMPL_W<8> { + pub fn smsmpl(&mut self) -> SMSMPL_W { SMSMPL_W::new(self) } #[doc = "Bit 12 - Supply Monitor Reset Enable"] #[inline(always)] #[must_use] - pub fn smrsten(&mut self) -> SMRSTEN_W<12> { + pub fn smrsten(&mut self) -> SMRSTEN_W { SMRSTEN_W::new(self) } #[doc = "Bit 13 - Supply Monitor Interrupt Enable"] #[inline(always)] #[must_use] - pub fn smien(&mut self) -> SMIEN_W<13> { + pub fn smien(&mut self) -> SMIEN_W { SMIEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Supply Controller Supply Monitor Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smmr](index.html) module"] +#[doc = "Supply Controller Supply Monitor Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SMMR_SPEC; impl crate::RegisterSpec for SMMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [smmr::R](R) reader structure"] -impl crate::Readable for SMMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [smmr::W](W) writer structure"] +#[doc = "`read()` method returns [`smmr::R`](R) reader structure"] +impl crate::Readable for SMMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smmr::W`](W) writer structure"] impl crate::Writable for SMMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/supc/sr.rs b/arch/cortex-m/samv71q21-pac/src/supc/sr.rs index d846638a..3f3ec421 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WKUPS` reader - WKUP Wake-up Status (cleared on read)"] pub type WKUPS_R = crate::BitReader; #[doc = "WKUP Wake-up Status (cleared on read)\n\nValue on reset: 0"] @@ -38,12 +25,12 @@ impl WKUPS_R { true => WKUPSSELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == WKUPSSELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == WKUPSSELECT_A::PRESENT @@ -74,12 +61,12 @@ impl SMWS_R { true => SMWSSELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == SMWSSELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == SMWSSELECT_A::PRESENT @@ -110,12 +97,12 @@ impl BODRSTS_R { true => BODRSTSSELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No core brownout rising edge event has been detected since the last read of the SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == BODRSTSSELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one brownout output rising edge event has been detected since the last read of the SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == BODRSTSSELECT_A::PRESENT @@ -146,12 +133,12 @@ impl SMRSTS_R { true => SMRSTSSELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No supply monitor detection has generated a core reset since the last read of the SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == SMRSTSSELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == SMRSTSSELECT_A::PRESENT @@ -182,12 +169,12 @@ impl SMS_R { true => SMSSELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No supply monitor detection since the last read of SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == SMSSELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one supply monitor detection since the last read of SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == SMSSELECT_A::PRESENT @@ -218,12 +205,12 @@ impl SMOS_R { true => SMOSSELECT_A::LOW, } } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "The supply monitor detected VDDIO higher than its threshold at its last measurement."] #[inline(always)] pub fn is_high(&self) -> bool { *self == SMOSSELECT_A::HIGH } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "The supply monitor detected VDDIO lower than its threshold at its last measurement."] #[inline(always)] pub fn is_low(&self) -> bool { *self == SMOSSELECT_A::LOW @@ -254,12 +241,12 @@ impl OSCSEL_R { true => OSCSELSELECT_A::CRYST, } } - #[doc = "Checks if the value of the field is `RC`"] + #[doc = "The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator."] #[inline(always)] pub fn is_rc(&self) -> bool { *self == OSCSELSELECT_A::RC } - #[doc = "Checks if the value of the field is `CRYST`"] + #[doc = "The slow clock, SLCK, is generated by the 32 kHz crystal oscillator."] #[inline(always)] pub fn is_cryst(&self) -> bool { *self == OSCSELSELECT_A::CRYST @@ -290,12 +277,12 @@ impl LPDBCS0_R { true => LPDBCS0SELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == LPDBCS0SELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == LPDBCS0SELECT_A::PRESENT @@ -326,12 +313,12 @@ impl LPDBCS1_R { true => LPDBCS1SELECT_A::PRESENT, } } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_no(&self) -> bool { *self == LPDBCS1SELECT_A::NO } - #[doc = "Checks if the value of the field is `PRESENT`"] + #[doc = "At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR."] #[inline(always)] pub fn is_present(&self) -> bool { *self == LPDBCS1SELECT_A::PRESENT @@ -362,12 +349,12 @@ impl WKUPIS0_R { true => WKUPIS0SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS0SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS0SELECT_A::EN @@ -398,12 +385,12 @@ impl WKUPIS1_R { true => WKUPIS1SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS1SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS1SELECT_A::EN @@ -434,12 +421,12 @@ impl WKUPIS2_R { true => WKUPIS2SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS2SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS2SELECT_A::EN @@ -470,12 +457,12 @@ impl WKUPIS3_R { true => WKUPIS3SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS3SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS3SELECT_A::EN @@ -506,12 +493,12 @@ impl WKUPIS4_R { true => WKUPIS4SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS4SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS4SELECT_A::EN @@ -542,12 +529,12 @@ impl WKUPIS5_R { true => WKUPIS5SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS5SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS5SELECT_A::EN @@ -578,12 +565,12 @@ impl WKUPIS6_R { true => WKUPIS6SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS6SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS6SELECT_A::EN @@ -614,12 +601,12 @@ impl WKUPIS7_R { true => WKUPIS7SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS7SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS7SELECT_A::EN @@ -650,12 +637,12 @@ impl WKUPIS8_R { true => WKUPIS8SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS8SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS8SELECT_A::EN @@ -686,12 +673,12 @@ impl WKUPIS9_R { true => WKUPIS9SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS9SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS9SELECT_A::EN @@ -722,12 +709,12 @@ impl WKUPIS10_R { true => WKUPIS10SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS10SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS10SELECT_A::EN @@ -758,12 +745,12 @@ impl WKUPIS11_R { true => WKUPIS11SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS11SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS11SELECT_A::EN @@ -794,12 +781,12 @@ impl WKUPIS12_R { true => WKUPIS12SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS12SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS12SELECT_A::EN @@ -830,12 +817,12 @@ impl WKUPIS13_R { true => WKUPIS13SELECT_A::EN, } } - #[doc = "Checks if the value of the field is `DIS`"] + #[doc = "The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event."] #[inline(always)] pub fn is_dis(&self) -> bool { *self == WKUPIS13SELECT_A::DIS } - #[doc = "Checks if the value of the field is `EN`"] + #[doc = "The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR."] #[inline(always)] pub fn is_en(&self) -> bool { *self == WKUPIS13SELECT_A::EN @@ -958,15 +945,13 @@ impl R { WKUPIS13_R::new(((self.bits >> 29) & 1) != 0) } } -#[doc = "Supply Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Supply Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/supc/sysc_wpmr.rs b/arch/cortex-m/samv71q21-pac/src/supc/sysc_wpmr.rs index 60afc9b4..980c42fe 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/sysc_wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/sysc_wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `SYSC_WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SYSC_WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, SYSC_WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, SYSC_WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sysc_wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysc_wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysc_wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SYSC_WPMR_SPEC; impl crate::RegisterSpec for SYSC_WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sysc_wpmr::R](R) reader structure"] -impl crate::Readable for SYSC_WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [sysc_wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`sysc_wpmr::R`](R) reader structure"] +impl crate::Readable for SYSC_WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sysc_wpmr::W`](W) writer structure"] impl crate::Writable for SYSC_WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/supc/wuir.rs b/arch/cortex-m/samv71q21-pac/src/supc/wuir.rs index 1de55c7e..2d6269eb 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/wuir.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/wuir.rs @@ -1,39 +1,7 @@ #[doc = "Register `WUIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WUIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WKUPEN0` reader - Wake-up Input Enable 0 to 0"] pub type WKUPEN0_R = crate::BitReader; #[doc = "Wake-up Input Enable 0 to 0\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl WKUPEN0_R { true => WKUPEN0SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN0SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN0SELECT_A::ENABLE } } #[doc = "Field `WKUPEN0` writer - Wake-up Input Enable 0 to 0"] -pub type WKUPEN0_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN0SELECT_A>; -impl<'a, const O: u8> WKUPEN0_W<'a, O> { +pub type WKUPEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN0SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN0SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN0SELECT_A::ENABLE) } } @@ -109,28 +80,31 @@ impl WKUPEN1_R { true => WKUPEN1SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN1SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN1SELECT_A::ENABLE } } #[doc = "Field `WKUPEN1` writer - Wake-up Input Enable 0 to 1"] -pub type WKUPEN1_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN1SELECT_A>; -impl<'a, const O: u8> WKUPEN1_W<'a, O> { +pub type WKUPEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN1SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN1SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN1SELECT_A::ENABLE) } } @@ -159,28 +133,31 @@ impl WKUPEN2_R { true => WKUPEN2SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN2SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN2SELECT_A::ENABLE } } #[doc = "Field `WKUPEN2` writer - Wake-up Input Enable 0 to 2"] -pub type WKUPEN2_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN2SELECT_A>; -impl<'a, const O: u8> WKUPEN2_W<'a, O> { +pub type WKUPEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN2SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN2SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN2SELECT_A::ENABLE) } } @@ -209,28 +186,31 @@ impl WKUPEN3_R { true => WKUPEN3SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN3SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN3SELECT_A::ENABLE } } #[doc = "Field `WKUPEN3` writer - Wake-up Input Enable 0 to 3"] -pub type WKUPEN3_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN3SELECT_A>; -impl<'a, const O: u8> WKUPEN3_W<'a, O> { +pub type WKUPEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN3SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN3SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN3SELECT_A::ENABLE) } } @@ -259,28 +239,31 @@ impl WKUPEN4_R { true => WKUPEN4SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN4SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN4SELECT_A::ENABLE } } #[doc = "Field `WKUPEN4` writer - Wake-up Input Enable 0 to 4"] -pub type WKUPEN4_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN4SELECT_A>; -impl<'a, const O: u8> WKUPEN4_W<'a, O> { +pub type WKUPEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN4SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN4SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN4SELECT_A::ENABLE) } } @@ -309,28 +292,31 @@ impl WKUPEN5_R { true => WKUPEN5SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN5SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN5SELECT_A::ENABLE } } #[doc = "Field `WKUPEN5` writer - Wake-up Input Enable 0 to 5"] -pub type WKUPEN5_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN5SELECT_A>; -impl<'a, const O: u8> WKUPEN5_W<'a, O> { +pub type WKUPEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN5SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN5SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN5SELECT_A::ENABLE) } } @@ -359,28 +345,31 @@ impl WKUPEN6_R { true => WKUPEN6SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN6SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN6SELECT_A::ENABLE } } #[doc = "Field `WKUPEN6` writer - Wake-up Input Enable 0 to 6"] -pub type WKUPEN6_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN6SELECT_A>; -impl<'a, const O: u8> WKUPEN6_W<'a, O> { +pub type WKUPEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN6SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN6SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN6SELECT_A::ENABLE) } } @@ -409,28 +398,31 @@ impl WKUPEN7_R { true => WKUPEN7SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN7SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN7SELECT_A::ENABLE } } #[doc = "Field `WKUPEN7` writer - Wake-up Input Enable 0 to 7"] -pub type WKUPEN7_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN7SELECT_A>; -impl<'a, const O: u8> WKUPEN7_W<'a, O> { +pub type WKUPEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN7SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN7SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN7SELECT_A::ENABLE) } } @@ -459,28 +451,31 @@ impl WKUPEN8_R { true => WKUPEN8SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN8SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN8SELECT_A::ENABLE } } #[doc = "Field `WKUPEN8` writer - Wake-up Input Enable 0 to 8"] -pub type WKUPEN8_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN8SELECT_A>; -impl<'a, const O: u8> WKUPEN8_W<'a, O> { +pub type WKUPEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN8SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN8SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN8SELECT_A::ENABLE) } } @@ -509,28 +504,31 @@ impl WKUPEN9_R { true => WKUPEN9SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN9SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN9SELECT_A::ENABLE } } #[doc = "Field `WKUPEN9` writer - Wake-up Input Enable 0 to 9"] -pub type WKUPEN9_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN9SELECT_A>; -impl<'a, const O: u8> WKUPEN9_W<'a, O> { +pub type WKUPEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN9SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN9SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN9SELECT_A::ENABLE) } } @@ -559,28 +557,31 @@ impl WKUPEN10_R { true => WKUPEN10SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN10SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN10SELECT_A::ENABLE } } #[doc = "Field `WKUPEN10` writer - Wake-up Input Enable 0 to 10"] -pub type WKUPEN10_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN10SELECT_A>; -impl<'a, const O: u8> WKUPEN10_W<'a, O> { +pub type WKUPEN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN10SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN10SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN10SELECT_A::ENABLE) } } @@ -609,28 +610,31 @@ impl WKUPEN11_R { true => WKUPEN11SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN11SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN11SELECT_A::ENABLE } } #[doc = "Field `WKUPEN11` writer - Wake-up Input Enable 0 to 11"] -pub type WKUPEN11_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN11SELECT_A>; -impl<'a, const O: u8> WKUPEN11_W<'a, O> { +pub type WKUPEN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN11SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN11SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN11SELECT_A::ENABLE) } } @@ -659,28 +663,31 @@ impl WKUPEN12_R { true => WKUPEN12SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN12SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN12SELECT_A::ENABLE } } #[doc = "Field `WKUPEN12` writer - Wake-up Input Enable 0 to 12"] -pub type WKUPEN12_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN12SELECT_A>; -impl<'a, const O: u8> WKUPEN12_W<'a, O> { +pub type WKUPEN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN12SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN12SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN12SELECT_A::ENABLE) } } @@ -709,28 +716,31 @@ impl WKUPEN13_R { true => WKUPEN13SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == WKUPEN13SELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == WKUPEN13SELECT_A::ENABLE } } #[doc = "Field `WKUPEN13` writer - Wake-up Input Enable 0 to 13"] -pub type WKUPEN13_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPEN13SELECT_A>; -impl<'a, const O: u8> WKUPEN13_W<'a, O> { +pub type WKUPEN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPEN13SELECT_A>; +impl<'a, REG, const O: u8> WKUPEN13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The corresponding wake-up input has no wake-up effect."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(WKUPEN13SELECT_A::DISABLE) } #[doc = "The corresponding wake-up input is enabled for a wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(WKUPEN13SELECT_A::ENABLE) } } @@ -759,28 +769,31 @@ impl WKUPT0_R { true => WKUPT0SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT0SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT0SELECT_A::HIGH } } #[doc = "Field `WKUPT0` writer - Wake-up Input Type 0 to 0"] -pub type WKUPT0_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT0SELECT_A>; -impl<'a, const O: u8> WKUPT0_W<'a, O> { +pub type WKUPT0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT0SELECT_A>; +impl<'a, REG, const O: u8> WKUPT0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT0SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT0SELECT_A::HIGH) } } @@ -809,28 +822,31 @@ impl WKUPT1_R { true => WKUPT1SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT1SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT1SELECT_A::HIGH } } #[doc = "Field `WKUPT1` writer - Wake-up Input Type 0 to 1"] -pub type WKUPT1_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT1SELECT_A>; -impl<'a, const O: u8> WKUPT1_W<'a, O> { +pub type WKUPT1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT1SELECT_A>; +impl<'a, REG, const O: u8> WKUPT1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT1SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT1SELECT_A::HIGH) } } @@ -859,28 +875,31 @@ impl WKUPT2_R { true => WKUPT2SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT2SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT2SELECT_A::HIGH } } #[doc = "Field `WKUPT2` writer - Wake-up Input Type 0 to 2"] -pub type WKUPT2_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT2SELECT_A>; -impl<'a, const O: u8> WKUPT2_W<'a, O> { +pub type WKUPT2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT2SELECT_A>; +impl<'a, REG, const O: u8> WKUPT2_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT2SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT2SELECT_A::HIGH) } } @@ -909,28 +928,31 @@ impl WKUPT3_R { true => WKUPT3SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT3SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT3SELECT_A::HIGH } } #[doc = "Field `WKUPT3` writer - Wake-up Input Type 0 to 3"] -pub type WKUPT3_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT3SELECT_A>; -impl<'a, const O: u8> WKUPT3_W<'a, O> { +pub type WKUPT3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT3SELECT_A>; +impl<'a, REG, const O: u8> WKUPT3_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT3SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT3SELECT_A::HIGH) } } @@ -959,28 +981,31 @@ impl WKUPT4_R { true => WKUPT4SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT4SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT4SELECT_A::HIGH } } #[doc = "Field `WKUPT4` writer - Wake-up Input Type 0 to 4"] -pub type WKUPT4_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT4SELECT_A>; -impl<'a, const O: u8> WKUPT4_W<'a, O> { +pub type WKUPT4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT4SELECT_A>; +impl<'a, REG, const O: u8> WKUPT4_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT4SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT4SELECT_A::HIGH) } } @@ -1009,28 +1034,31 @@ impl WKUPT5_R { true => WKUPT5SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT5SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT5SELECT_A::HIGH } } #[doc = "Field `WKUPT5` writer - Wake-up Input Type 0 to 5"] -pub type WKUPT5_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT5SELECT_A>; -impl<'a, const O: u8> WKUPT5_W<'a, O> { +pub type WKUPT5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT5SELECT_A>; +impl<'a, REG, const O: u8> WKUPT5_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT5SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT5SELECT_A::HIGH) } } @@ -1059,28 +1087,31 @@ impl WKUPT6_R { true => WKUPT6SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT6SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT6SELECT_A::HIGH } } #[doc = "Field `WKUPT6` writer - Wake-up Input Type 0 to 6"] -pub type WKUPT6_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT6SELECT_A>; -impl<'a, const O: u8> WKUPT6_W<'a, O> { +pub type WKUPT6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT6SELECT_A>; +impl<'a, REG, const O: u8> WKUPT6_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT6SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT6SELECT_A::HIGH) } } @@ -1109,28 +1140,31 @@ impl WKUPT7_R { true => WKUPT7SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT7SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT7SELECT_A::HIGH } } #[doc = "Field `WKUPT7` writer - Wake-up Input Type 0 to 7"] -pub type WKUPT7_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT7SELECT_A>; -impl<'a, const O: u8> WKUPT7_W<'a, O> { +pub type WKUPT7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT7SELECT_A>; +impl<'a, REG, const O: u8> WKUPT7_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT7SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT7SELECT_A::HIGH) } } @@ -1159,28 +1193,31 @@ impl WKUPT8_R { true => WKUPT8SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT8SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT8SELECT_A::HIGH } } #[doc = "Field `WKUPT8` writer - Wake-up Input Type 0 to 8"] -pub type WKUPT8_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT8SELECT_A>; -impl<'a, const O: u8> WKUPT8_W<'a, O> { +pub type WKUPT8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT8SELECT_A>; +impl<'a, REG, const O: u8> WKUPT8_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT8SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT8SELECT_A::HIGH) } } @@ -1209,28 +1246,31 @@ impl WKUPT9_R { true => WKUPT9SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT9SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT9SELECT_A::HIGH } } #[doc = "Field `WKUPT9` writer - Wake-up Input Type 0 to 9"] -pub type WKUPT9_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT9SELECT_A>; -impl<'a, const O: u8> WKUPT9_W<'a, O> { +pub type WKUPT9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT9SELECT_A>; +impl<'a, REG, const O: u8> WKUPT9_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT9SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT9SELECT_A::HIGH) } } @@ -1259,28 +1299,31 @@ impl WKUPT10_R { true => WKUPT10SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT10SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT10SELECT_A::HIGH } } #[doc = "Field `WKUPT10` writer - Wake-up Input Type 0 to 10"] -pub type WKUPT10_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT10SELECT_A>; -impl<'a, const O: u8> WKUPT10_W<'a, O> { +pub type WKUPT10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT10SELECT_A>; +impl<'a, REG, const O: u8> WKUPT10_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT10SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT10SELECT_A::HIGH) } } @@ -1309,28 +1352,31 @@ impl WKUPT11_R { true => WKUPT11SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT11SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT11SELECT_A::HIGH } } #[doc = "Field `WKUPT11` writer - Wake-up Input Type 0 to 11"] -pub type WKUPT11_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT11SELECT_A>; -impl<'a, const O: u8> WKUPT11_W<'a, O> { +pub type WKUPT11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT11SELECT_A>; +impl<'a, REG, const O: u8> WKUPT11_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT11SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT11SELECT_A::HIGH) } } @@ -1359,28 +1405,31 @@ impl WKUPT12_R { true => WKUPT12SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT12SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT12SELECT_A::HIGH } } #[doc = "Field `WKUPT12` writer - Wake-up Input Type 0 to 12"] -pub type WKUPT12_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT12SELECT_A>; -impl<'a, const O: u8> WKUPT12_W<'a, O> { +pub type WKUPT12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT12SELECT_A>; +impl<'a, REG, const O: u8> WKUPT12_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT12SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT12SELECT_A::HIGH) } } @@ -1409,28 +1458,31 @@ impl WKUPT13_R { true => WKUPT13SELECT_A::HIGH, } } - #[doc = "Checks if the value of the field is `LOW`"] + #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_low(&self) -> bool { *self == WKUPT13SELECT_A::LOW } - #[doc = "Checks if the value of the field is `HIGH`"] + #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] pub fn is_high(&self) -> bool { *self == WKUPT13SELECT_A::HIGH } } #[doc = "Field `WKUPT13` writer - Wake-up Input Type 0 to 13"] -pub type WKUPT13_W<'a, const O: u8> = crate::BitWriter<'a, WUIR_SPEC, O, WKUPT13SELECT_A>; -impl<'a, const O: u8> WKUPT13_W<'a, O> { +pub type WKUPT13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WKUPT13SELECT_A>; +impl<'a, REG, const O: u8> WKUPT13_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn low(self) -> &'a mut W { + pub fn low(self) -> &'a mut crate::W { self.variant(WKUPT13SELECT_A::LOW) } #[doc = "A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply."] #[inline(always)] - pub fn high(self) -> &'a mut W { + pub fn high(self) -> &'a mut crate::W { self.variant(WKUPT13SELECT_A::HIGH) } } @@ -1580,190 +1632,187 @@ impl W { #[doc = "Bit 0 - Wake-up Input Enable 0 to 0"] #[inline(always)] #[must_use] - pub fn wkupen0(&mut self) -> WKUPEN0_W<0> { + pub fn wkupen0(&mut self) -> WKUPEN0_W { WKUPEN0_W::new(self) } #[doc = "Bit 1 - Wake-up Input Enable 0 to 1"] #[inline(always)] #[must_use] - pub fn wkupen1(&mut self) -> WKUPEN1_W<1> { + pub fn wkupen1(&mut self) -> WKUPEN1_W { WKUPEN1_W::new(self) } #[doc = "Bit 2 - Wake-up Input Enable 0 to 2"] #[inline(always)] #[must_use] - pub fn wkupen2(&mut self) -> WKUPEN2_W<2> { + pub fn wkupen2(&mut self) -> WKUPEN2_W { WKUPEN2_W::new(self) } #[doc = "Bit 3 - Wake-up Input Enable 0 to 3"] #[inline(always)] #[must_use] - pub fn wkupen3(&mut self) -> WKUPEN3_W<3> { + pub fn wkupen3(&mut self) -> WKUPEN3_W { WKUPEN3_W::new(self) } #[doc = "Bit 4 - Wake-up Input Enable 0 to 4"] #[inline(always)] #[must_use] - pub fn wkupen4(&mut self) -> WKUPEN4_W<4> { + pub fn wkupen4(&mut self) -> WKUPEN4_W { WKUPEN4_W::new(self) } #[doc = "Bit 5 - Wake-up Input Enable 0 to 5"] #[inline(always)] #[must_use] - pub fn wkupen5(&mut self) -> WKUPEN5_W<5> { + pub fn wkupen5(&mut self) -> WKUPEN5_W { WKUPEN5_W::new(self) } #[doc = "Bit 6 - Wake-up Input Enable 0 to 6"] #[inline(always)] #[must_use] - pub fn wkupen6(&mut self) -> WKUPEN6_W<6> { + pub fn wkupen6(&mut self) -> WKUPEN6_W { WKUPEN6_W::new(self) } #[doc = "Bit 7 - Wake-up Input Enable 0 to 7"] #[inline(always)] #[must_use] - pub fn wkupen7(&mut self) -> WKUPEN7_W<7> { + pub fn wkupen7(&mut self) -> WKUPEN7_W { WKUPEN7_W::new(self) } #[doc = "Bit 8 - Wake-up Input Enable 0 to 8"] #[inline(always)] #[must_use] - pub fn wkupen8(&mut self) -> WKUPEN8_W<8> { + pub fn wkupen8(&mut self) -> WKUPEN8_W { WKUPEN8_W::new(self) } #[doc = "Bit 9 - Wake-up Input Enable 0 to 9"] #[inline(always)] #[must_use] - pub fn wkupen9(&mut self) -> WKUPEN9_W<9> { + pub fn wkupen9(&mut self) -> WKUPEN9_W { WKUPEN9_W::new(self) } #[doc = "Bit 10 - Wake-up Input Enable 0 to 10"] #[inline(always)] #[must_use] - pub fn wkupen10(&mut self) -> WKUPEN10_W<10> { + pub fn wkupen10(&mut self) -> WKUPEN10_W { WKUPEN10_W::new(self) } #[doc = "Bit 11 - Wake-up Input Enable 0 to 11"] #[inline(always)] #[must_use] - pub fn wkupen11(&mut self) -> WKUPEN11_W<11> { + pub fn wkupen11(&mut self) -> WKUPEN11_W { WKUPEN11_W::new(self) } #[doc = "Bit 12 - Wake-up Input Enable 0 to 12"] #[inline(always)] #[must_use] - pub fn wkupen12(&mut self) -> WKUPEN12_W<12> { + pub fn wkupen12(&mut self) -> WKUPEN12_W { WKUPEN12_W::new(self) } #[doc = "Bit 13 - Wake-up Input Enable 0 to 13"] #[inline(always)] #[must_use] - pub fn wkupen13(&mut self) -> WKUPEN13_W<13> { + pub fn wkupen13(&mut self) -> WKUPEN13_W { WKUPEN13_W::new(self) } #[doc = "Bit 16 - Wake-up Input Type 0 to 0"] #[inline(always)] #[must_use] - pub fn wkupt0(&mut self) -> WKUPT0_W<16> { + pub fn wkupt0(&mut self) -> WKUPT0_W { WKUPT0_W::new(self) } #[doc = "Bit 17 - Wake-up Input Type 0 to 1"] #[inline(always)] #[must_use] - pub fn wkupt1(&mut self) -> WKUPT1_W<17> { + pub fn wkupt1(&mut self) -> WKUPT1_W { WKUPT1_W::new(self) } #[doc = "Bit 18 - Wake-up Input Type 0 to 2"] #[inline(always)] #[must_use] - pub fn wkupt2(&mut self) -> WKUPT2_W<18> { + pub fn wkupt2(&mut self) -> WKUPT2_W { WKUPT2_W::new(self) } #[doc = "Bit 19 - Wake-up Input Type 0 to 3"] #[inline(always)] #[must_use] - pub fn wkupt3(&mut self) -> WKUPT3_W<19> { + pub fn wkupt3(&mut self) -> WKUPT3_W { WKUPT3_W::new(self) } #[doc = "Bit 20 - Wake-up Input Type 0 to 4"] #[inline(always)] #[must_use] - pub fn wkupt4(&mut self) -> WKUPT4_W<20> { + pub fn wkupt4(&mut self) -> WKUPT4_W { WKUPT4_W::new(self) } #[doc = "Bit 21 - Wake-up Input Type 0 to 5"] #[inline(always)] #[must_use] - pub fn wkupt5(&mut self) -> WKUPT5_W<21> { + pub fn wkupt5(&mut self) -> WKUPT5_W { WKUPT5_W::new(self) } #[doc = "Bit 22 - Wake-up Input Type 0 to 6"] #[inline(always)] #[must_use] - pub fn wkupt6(&mut self) -> WKUPT6_W<22> { + pub fn wkupt6(&mut self) -> WKUPT6_W { WKUPT6_W::new(self) } #[doc = "Bit 23 - Wake-up Input Type 0 to 7"] #[inline(always)] #[must_use] - pub fn wkupt7(&mut self) -> WKUPT7_W<23> { + pub fn wkupt7(&mut self) -> WKUPT7_W { WKUPT7_W::new(self) } #[doc = "Bit 24 - Wake-up Input Type 0 to 8"] #[inline(always)] #[must_use] - pub fn wkupt8(&mut self) -> WKUPT8_W<24> { + pub fn wkupt8(&mut self) -> WKUPT8_W { WKUPT8_W::new(self) } #[doc = "Bit 25 - Wake-up Input Type 0 to 9"] #[inline(always)] #[must_use] - pub fn wkupt9(&mut self) -> WKUPT9_W<25> { + pub fn wkupt9(&mut self) -> WKUPT9_W { WKUPT9_W::new(self) } #[doc = "Bit 26 - Wake-up Input Type 0 to 10"] #[inline(always)] #[must_use] - pub fn wkupt10(&mut self) -> WKUPT10_W<26> { + pub fn wkupt10(&mut self) -> WKUPT10_W { WKUPT10_W::new(self) } #[doc = "Bit 27 - Wake-up Input Type 0 to 11"] #[inline(always)] #[must_use] - pub fn wkupt11(&mut self) -> WKUPT11_W<27> { + pub fn wkupt11(&mut self) -> WKUPT11_W { WKUPT11_W::new(self) } #[doc = "Bit 28 - Wake-up Input Type 0 to 12"] #[inline(always)] #[must_use] - pub fn wkupt12(&mut self) -> WKUPT12_W<28> { + pub fn wkupt12(&mut self) -> WKUPT12_W { WKUPT12_W::new(self) } #[doc = "Bit 29 - Wake-up Input Type 0 to 13"] #[inline(always)] #[must_use] - pub fn wkupt13(&mut self) -> WKUPT13_W<29> { + pub fn wkupt13(&mut self) -> WKUPT13_W { WKUPT13_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Supply Controller Wake-up Inputs Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wuir](index.html) module"] +#[doc = "Supply Controller Wake-up Inputs Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wuir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wuir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WUIR_SPEC; impl crate::RegisterSpec for WUIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wuir::R](R) reader structure"] -impl crate::Readable for WUIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wuir::W](W) writer structure"] +#[doc = "`read()` method returns [`wuir::R`](R) reader structure"] +impl crate::Readable for WUIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wuir::W`](W) writer structure"] impl crate::Writable for WUIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/supc/wumr.rs b/arch/cortex-m/samv71q21-pac/src/supc/wumr.rs index c7171193..1b0c1b36 100644 --- a/arch/cortex-m/samv71q21-pac/src/supc/wumr.rs +++ b/arch/cortex-m/samv71q21-pac/src/supc/wumr.rs @@ -1,39 +1,7 @@ #[doc = "Register `WUMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WUMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SMEN` reader - Supply Monitor Wake-up Enable"] pub type SMEN_R = crate::BitReader; #[doc = "Supply Monitor Wake-up Enable\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl SMEN_R { true => SMENSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The supply monitor detection has no wake-up effect."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == SMENSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The supply monitor detection forces the wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == SMENSELECT_A::ENABLE } } #[doc = "Field `SMEN` writer - Supply Monitor Wake-up Enable"] -pub type SMEN_W<'a, const O: u8> = crate::BitWriter<'a, WUMR_SPEC, O, SMENSELECT_A>; -impl<'a, const O: u8> SMEN_W<'a, O> { +pub type SMEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SMENSELECT_A>; +impl<'a, REG, const O: u8> SMEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The supply monitor detection has no wake-up effect."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(SMENSELECT_A::NOT_ENABLE) } #[doc = "The supply monitor detection forces the wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(SMENSELECT_A::ENABLE) } } @@ -109,28 +80,31 @@ impl RTTEN_R { true => RTTENSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The RTT alarm signal has no wake-up effect."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == RTTENSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The RTT alarm signal forces the wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == RTTENSELECT_A::ENABLE } } #[doc = "Field `RTTEN` writer - Real-time Timer Wake-up Enable"] -pub type RTTEN_W<'a, const O: u8> = crate::BitWriter<'a, WUMR_SPEC, O, RTTENSELECT_A>; -impl<'a, const O: u8> RTTEN_W<'a, O> { +pub type RTTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RTTENSELECT_A>; +impl<'a, REG, const O: u8> RTTEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The RTT alarm signal has no wake-up effect."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(RTTENSELECT_A::NOT_ENABLE) } #[doc = "The RTT alarm signal forces the wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(RTTENSELECT_A::ENABLE) } } @@ -159,28 +133,31 @@ impl RTCEN_R { true => RTCENSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The RTC alarm signal has no wake-up effect."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == RTCENSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The RTC alarm signal forces the wake-up of the core power supply."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == RTCENSELECT_A::ENABLE } } #[doc = "Field `RTCEN` writer - Real-time Clock Wake-up Enable"] -pub type RTCEN_W<'a, const O: u8> = crate::BitWriter<'a, WUMR_SPEC, O, RTCENSELECT_A>; -impl<'a, const O: u8> RTCEN_W<'a, O> { +pub type RTCEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RTCENSELECT_A>; +impl<'a, REG, const O: u8> RTCEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The RTC alarm signal has no wake-up effect."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(RTCENSELECT_A::NOT_ENABLE) } #[doc = "The RTC alarm signal forces the wake-up of the core power supply."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(RTCENSELECT_A::ENABLE) } } @@ -209,28 +186,31 @@ impl LPDBCEN0_R { true => LPDBCEN0SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The WKUP0 input pin is not connected to the low-power debouncer."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == LPDBCEN0SELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == LPDBCEN0SELECT_A::ENABLE } } #[doc = "Field `LPDBCEN0` writer - Low-power Debouncer Enable WKUP0"] -pub type LPDBCEN0_W<'a, const O: u8> = crate::BitWriter<'a, WUMR_SPEC, O, LPDBCEN0SELECT_A>; -impl<'a, const O: u8> LPDBCEN0_W<'a, O> { +pub type LPDBCEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LPDBCEN0SELECT_A>; +impl<'a, REG, const O: u8> LPDBCEN0_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The WKUP0 input pin is not connected to the low-power debouncer."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(LPDBCEN0SELECT_A::NOT_ENABLE) } #[doc = "The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(LPDBCEN0SELECT_A::ENABLE) } } @@ -259,28 +239,31 @@ impl LPDBCEN1_R { true => LPDBCEN1SELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "The WKUP1 input pin is not connected to the low-power debouncer."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == LPDBCEN1SELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == LPDBCEN1SELECT_A::ENABLE } } #[doc = "Field `LPDBCEN1` writer - Low-power Debouncer Enable WKUP1"] -pub type LPDBCEN1_W<'a, const O: u8> = crate::BitWriter<'a, WUMR_SPEC, O, LPDBCEN1SELECT_A>; -impl<'a, const O: u8> LPDBCEN1_W<'a, O> { +pub type LPDBCEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LPDBCEN1SELECT_A>; +impl<'a, REG, const O: u8> LPDBCEN1_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The WKUP1 input pin is not connected to the low-power debouncer."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(LPDBCEN1SELECT_A::NOT_ENABLE) } #[doc = "The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(LPDBCEN1SELECT_A::ENABLE) } } @@ -309,28 +292,31 @@ impl LPDBCCLR_R { true => LPDBCCLRSELECT_A::ENABLE, } } - #[doc = "Checks if the value of the field is `NOT_ENABLE`"] + #[doc = "A low-power debounce event does not create an immediate clear on the first half of GPBR registers."] #[inline(always)] pub fn is_not_enable(&self) -> bool { *self == LPDBCCLRSELECT_A::NOT_ENABLE } - #[doc = "Checks if the value of the field is `ENABLE`"] + #[doc = "A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers."] #[inline(always)] pub fn is_enable(&self) -> bool { *self == LPDBCCLRSELECT_A::ENABLE } } #[doc = "Field `LPDBCCLR` writer - Low-power Debouncer Clear"] -pub type LPDBCCLR_W<'a, const O: u8> = crate::BitWriter<'a, WUMR_SPEC, O, LPDBCCLRSELECT_A>; -impl<'a, const O: u8> LPDBCCLR_W<'a, O> { +pub type LPDBCCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, LPDBCCLRSELECT_A>; +impl<'a, REG, const O: u8> LPDBCCLR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "A low-power debounce event does not create an immediate clear on the first half of GPBR registers."] #[inline(always)] - pub fn not_enable(self) -> &'a mut W { + pub fn not_enable(self) -> &'a mut crate::W { self.variant(LPDBCCLRSELECT_A::NOT_ENABLE) } #[doc = "A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers."] #[inline(always)] - pub fn enable(self) -> &'a mut W { + pub fn enable(self) -> &'a mut crate::W { self.variant(LPDBCCLRSELECT_A::ENABLE) } } @@ -376,68 +362,72 @@ impl WKUPDBC_R { _ => None, } } - #[doc = "Checks if the value of the field is `IMMEDIATE`"] + #[doc = "Immediate, no debouncing, detected active at least on one Slow Clock edge."] #[inline(always)] pub fn is_immediate(&self) -> bool { *self == WKUPDBCSELECT_A::IMMEDIATE } - #[doc = "Checks if the value of the field is `_3_SLCK`"] + #[doc = "WKUPx shall be in its active state for at least 3 SLCK periods"] #[inline(always)] pub fn is_3_slck(&self) -> bool { *self == WKUPDBCSELECT_A::_3_SLCK } - #[doc = "Checks if the value of the field is `_32_SLCK`"] + #[doc = "WKUPx shall be in its active state for at least 32 SLCK periods"] #[inline(always)] pub fn is_32_slck(&self) -> bool { *self == WKUPDBCSELECT_A::_32_SLCK } - #[doc = "Checks if the value of the field is `_512_SLCK`"] + #[doc = "WKUPx shall be in its active state for at least 512 SLCK periods"] #[inline(always)] pub fn is_512_slck(&self) -> bool { *self == WKUPDBCSELECT_A::_512_SLCK } - #[doc = "Checks if the value of the field is `_4096_SLCK`"] + #[doc = "WKUPx shall be in its active state for at least 4,096 SLCK periods"] #[inline(always)] pub fn is_4096_slck(&self) -> bool { *self == WKUPDBCSELECT_A::_4096_SLCK } - #[doc = "Checks if the value of the field is `_32768_SLCK`"] + #[doc = "WKUPx shall be in its active state for at least 32,768 SLCK periods"] #[inline(always)] pub fn is_32768_slck(&self) -> bool { *self == WKUPDBCSELECT_A::_32768_SLCK } } #[doc = "Field `WKUPDBC` writer - Wake-up Inputs Debouncer Period"] -pub type WKUPDBC_W<'a, const O: u8> = crate::FieldWriter<'a, WUMR_SPEC, 3, O, WKUPDBCSELECT_A>; -impl<'a, const O: u8> WKUPDBC_W<'a, O> { +pub type WKUPDBC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, WKUPDBCSELECT_A>; +impl<'a, REG, const O: u8> WKUPDBC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Immediate, no debouncing, detected active at least on one Slow Clock edge."] #[inline(always)] - pub fn immediate(self) -> &'a mut W { + pub fn immediate(self) -> &'a mut crate::W { self.variant(WKUPDBCSELECT_A::IMMEDIATE) } #[doc = "WKUPx shall be in its active state for at least 3 SLCK periods"] #[inline(always)] - pub fn _3_slck(self) -> &'a mut W { + pub fn _3_slck(self) -> &'a mut crate::W { self.variant(WKUPDBCSELECT_A::_3_SLCK) } #[doc = "WKUPx shall be in its active state for at least 32 SLCK periods"] #[inline(always)] - pub fn _32_slck(self) -> &'a mut W { + pub fn _32_slck(self) -> &'a mut crate::W { self.variant(WKUPDBCSELECT_A::_32_SLCK) } #[doc = "WKUPx shall be in its active state for at least 512 SLCK periods"] #[inline(always)] - pub fn _512_slck(self) -> &'a mut W { + pub fn _512_slck(self) -> &'a mut crate::W { self.variant(WKUPDBCSELECT_A::_512_SLCK) } #[doc = "WKUPx shall be in its active state for at least 4,096 SLCK periods"] #[inline(always)] - pub fn _4096_slck(self) -> &'a mut W { + pub fn _4096_slck(self) -> &'a mut crate::W { self.variant(WKUPDBCSELECT_A::_4096_SLCK) } #[doc = "WKUPx shall be in its active state for at least 32,768 SLCK periods"] #[inline(always)] - pub fn _32768_slck(self) -> &'a mut W { + pub fn _32768_slck(self) -> &'a mut crate::W { self.variant(WKUPDBCSELECT_A::_32768_SLCK) } } @@ -489,88 +479,92 @@ impl LPDBC_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DISABLE`"] + #[doc = "Disable the low-power debouncers."] #[inline(always)] pub fn is_disable(&self) -> bool { *self == LPDBCSELECT_A::DISABLE } - #[doc = "Checks if the value of the field is `_2_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 2 RTCOUTx clock periods"] #[inline(always)] pub fn is_2_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_2_RTCOUT } - #[doc = "Checks if the value of the field is `_3_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 3 RTCOUTx clock periods"] #[inline(always)] pub fn is_3_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_3_RTCOUT } - #[doc = "Checks if the value of the field is `_4_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 4 RTCOUTx clock periods"] #[inline(always)] pub fn is_4_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_4_RTCOUT } - #[doc = "Checks if the value of the field is `_5_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 5 RTCOUTx clock periods"] #[inline(always)] pub fn is_5_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_5_RTCOUT } - #[doc = "Checks if the value of the field is `_6_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 6 RTCOUTx clock periods"] #[inline(always)] pub fn is_6_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_6_RTCOUT } - #[doc = "Checks if the value of the field is `_7_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 7 RTCOUTx clock periods"] #[inline(always)] pub fn is_7_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_7_RTCOUT } - #[doc = "Checks if the value of the field is `_8_RTCOUT`"] + #[doc = "WKUP0/1 in active state for at least 8 RTCOUTx clock periods"] #[inline(always)] pub fn is_8_rtcout(&self) -> bool { *self == LPDBCSELECT_A::_8_RTCOUT } } #[doc = "Field `LPDBC` writer - Low-power Debouncer Period"] -pub type LPDBC_W<'a, const O: u8> = crate::FieldWriterSafe<'a, WUMR_SPEC, 3, O, LPDBCSELECT_A>; -impl<'a, const O: u8> LPDBC_W<'a, O> { +pub type LPDBC_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, LPDBCSELECT_A>; +impl<'a, REG, const O: u8> LPDBC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Disable the low-power debouncers."] #[inline(always)] - pub fn disable(self) -> &'a mut W { + pub fn disable(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::DISABLE) } #[doc = "WKUP0/1 in active state for at least 2 RTCOUTx clock periods"] #[inline(always)] - pub fn _2_rtcout(self) -> &'a mut W { + pub fn _2_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_2_RTCOUT) } #[doc = "WKUP0/1 in active state for at least 3 RTCOUTx clock periods"] #[inline(always)] - pub fn _3_rtcout(self) -> &'a mut W { + pub fn _3_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_3_RTCOUT) } #[doc = "WKUP0/1 in active state for at least 4 RTCOUTx clock periods"] #[inline(always)] - pub fn _4_rtcout(self) -> &'a mut W { + pub fn _4_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_4_RTCOUT) } #[doc = "WKUP0/1 in active state for at least 5 RTCOUTx clock periods"] #[inline(always)] - pub fn _5_rtcout(self) -> &'a mut W { + pub fn _5_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_5_RTCOUT) } #[doc = "WKUP0/1 in active state for at least 6 RTCOUTx clock periods"] #[inline(always)] - pub fn _6_rtcout(self) -> &'a mut W { + pub fn _6_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_6_RTCOUT) } #[doc = "WKUP0/1 in active state for at least 7 RTCOUTx clock periods"] #[inline(always)] - pub fn _7_rtcout(self) -> &'a mut W { + pub fn _7_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_7_RTCOUT) } #[doc = "WKUP0/1 in active state for at least 8 RTCOUTx clock periods"] #[inline(always)] - pub fn _8_rtcout(self) -> &'a mut W { + pub fn _8_rtcout(self) -> &'a mut crate::W { self.variant(LPDBCSELECT_A::_8_RTCOUT) } } @@ -620,70 +614,67 @@ impl W { #[doc = "Bit 1 - Supply Monitor Wake-up Enable"] #[inline(always)] #[must_use] - pub fn smen(&mut self) -> SMEN_W<1> { + pub fn smen(&mut self) -> SMEN_W { SMEN_W::new(self) } #[doc = "Bit 2 - Real-time Timer Wake-up Enable"] #[inline(always)] #[must_use] - pub fn rtten(&mut self) -> RTTEN_W<2> { + pub fn rtten(&mut self) -> RTTEN_W { RTTEN_W::new(self) } #[doc = "Bit 3 - Real-time Clock Wake-up Enable"] #[inline(always)] #[must_use] - pub fn rtcen(&mut self) -> RTCEN_W<3> { + pub fn rtcen(&mut self) -> RTCEN_W { RTCEN_W::new(self) } #[doc = "Bit 5 - Low-power Debouncer Enable WKUP0"] #[inline(always)] #[must_use] - pub fn lpdbcen0(&mut self) -> LPDBCEN0_W<5> { + pub fn lpdbcen0(&mut self) -> LPDBCEN0_W { LPDBCEN0_W::new(self) } #[doc = "Bit 6 - Low-power Debouncer Enable WKUP1"] #[inline(always)] #[must_use] - pub fn lpdbcen1(&mut self) -> LPDBCEN1_W<6> { + pub fn lpdbcen1(&mut self) -> LPDBCEN1_W { LPDBCEN1_W::new(self) } #[doc = "Bit 7 - Low-power Debouncer Clear"] #[inline(always)] #[must_use] - pub fn lpdbcclr(&mut self) -> LPDBCCLR_W<7> { + pub fn lpdbcclr(&mut self) -> LPDBCCLR_W { LPDBCCLR_W::new(self) } #[doc = "Bits 12:14 - Wake-up Inputs Debouncer Period"] #[inline(always)] #[must_use] - pub fn wkupdbc(&mut self) -> WKUPDBC_W<12> { + pub fn wkupdbc(&mut self) -> WKUPDBC_W { WKUPDBC_W::new(self) } #[doc = "Bits 16:18 - Low-power Debouncer Period"] #[inline(always)] #[must_use] - pub fn lpdbc(&mut self) -> LPDBC_W<16> { + pub fn lpdbc(&mut self) -> LPDBC_W { LPDBC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Supply Controller Wake-up Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wumr](index.html) module"] +#[doc = "Supply Controller Wake-up Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wumr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wumr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WUMR_SPEC; impl crate::RegisterSpec for WUMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wumr::R](R) reader structure"] -impl crate::Readable for WUMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wumr::W](W) writer structure"] +#[doc = "`read()` method returns [`wumr::R`](R) reader structure"] +impl crate::Readable for WUMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wumr::W`](W) writer structure"] impl crate::Writable for WUMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/sys_tick.rs b/arch/cortex-m/samv71q21-pac/src/sys_tick.rs index b18ab42f..0309d4e0 100644 --- a/arch/cortex-m/samv71q21-pac/src/sys_tick.rs +++ b/arch/cortex-m/samv71q21-pac/src/sys_tick.rs @@ -10,19 +10,23 @@ pub struct RegisterBlock { #[doc = "0x0c - Calibration Value Register"] pub calib: CALIB, } -#[doc = "CSR (rw) register accessor: an alias for `Reg`"] +#[doc = "CSR (rw) register accessor: Control and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`csr`] +module"] pub type CSR = crate::Reg; #[doc = "Control and Status Register"] pub mod csr; -#[doc = "RVR (rw) register accessor: an alias for `Reg`"] +#[doc = "RVR (rw) register accessor: Reload Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rvr`] +module"] pub type RVR = crate::Reg; #[doc = "Reload Value Register"] pub mod rvr; -#[doc = "CVR (rw) register accessor: an alias for `Reg`"] +#[doc = "CVR (rw) register accessor: Current Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cvr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cvr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cvr`] +module"] pub type CVR = crate::Reg; #[doc = "Current Value Register"] pub mod cvr; -#[doc = "CALIB (r) register accessor: an alias for `Reg`"] +#[doc = "CALIB (r) register accessor: Calibration Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calib::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`calib`] +module"] pub type CALIB = crate::Reg; #[doc = "Calibration Value Register"] pub mod calib; diff --git a/arch/cortex-m/samv71q21-pac/src/sys_tick/calib.rs b/arch/cortex-m/samv71q21-pac/src/sys_tick/calib.rs index aa11f28d..9d657f7d 100644 --- a/arch/cortex-m/samv71q21-pac/src/sys_tick/calib.rs +++ b/arch/cortex-m/samv71q21-pac/src/sys_tick/calib.rs @@ -1,18 +1,5 @@ #[doc = "Register `CALIB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TENMS` reader - Reload value to use for 10ms timing"] pub type TENMS_R = crate::FieldReader; #[doc = "Field `SKEW` reader - Indicates whether the TENMS value is exact"] @@ -40,12 +27,12 @@ impl SKEW_R { true => SKEWSELECT_A::VALUE_1, } } - #[doc = "Checks if the value of the field is `VALUE_0`"] + #[doc = "10ms calibration value is exact"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == SKEWSELECT_A::VALUE_0 } - #[doc = "Checks if the value of the field is `VALUE_1`"] + #[doc = "10ms calibration value is inexact, because of the clock frequency"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == SKEWSELECT_A::VALUE_1 @@ -76,12 +63,12 @@ impl NOREF_R { true => NOREFSELECT_A::VALUE_1, } } - #[doc = "Checks if the value of the field is `VALUE_0`"] + #[doc = "The reference clock is provided"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == NOREFSELECT_A::VALUE_0 } - #[doc = "Checks if the value of the field is `VALUE_1`"] + #[doc = "The reference clock is not provided"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == NOREFSELECT_A::VALUE_1 @@ -104,15 +91,13 @@ impl R { NOREF_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Calibration Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +#[doc = "Calibration Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`calib::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CALIB_SPEC; impl crate::RegisterSpec for CALIB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [calib::R](R) reader structure"] -impl crate::Readable for CALIB_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`calib::R`](R) reader structure"] +impl crate::Readable for CALIB_SPEC {} #[doc = "`reset()` method sets CALIB to value 0"] impl crate::Resettable for CALIB_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/sys_tick/csr.rs b/arch/cortex-m/samv71q21-pac/src/sys_tick/csr.rs index 3690c35d..05983dc6 100644 --- a/arch/cortex-m/samv71q21-pac/src/sys_tick/csr.rs +++ b/arch/cortex-m/samv71q21-pac/src/sys_tick/csr.rs @@ -1,39 +1,7 @@ #[doc = "Register `CSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` reader - Enables the counter"] pub type ENABLE_R = crate::BitReader; #[doc = "Enables the counter\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl ENABLE_R { true => ENABLESELECT_A::VALUE_1, } } - #[doc = "Checks if the value of the field is `VALUE_0`"] + #[doc = "counter disabled"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == ENABLESELECT_A::VALUE_0 } - #[doc = "Checks if the value of the field is `VALUE_1`"] + #[doc = "counter enabled"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == ENABLESELECT_A::VALUE_1 } } #[doc = "Field `ENABLE` writer - Enables the counter"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O, ENABLESELECT_A>; -impl<'a, const O: u8> ENABLE_W<'a, O> { +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, ENABLESELECT_A>; +impl<'a, REG, const O: u8> ENABLE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "counter disabled"] #[inline(always)] - pub fn value_0(self) -> &'a mut W { + pub fn value_0(self) -> &'a mut crate::W { self.variant(ENABLESELECT_A::VALUE_0) } #[doc = "counter enabled"] #[inline(always)] - pub fn value_1(self) -> &'a mut W { + pub fn value_1(self) -> &'a mut crate::W { self.variant(ENABLESELECT_A::VALUE_1) } } @@ -109,28 +80,31 @@ impl TICKINT_R { true => TICKINTSELECT_A::VALUE_1, } } - #[doc = "Checks if the value of the field is `VALUE_0`"] + #[doc = "counting down to 0 does not assert the SysTick exception request"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == TICKINTSELECT_A::VALUE_0 } - #[doc = "Checks if the value of the field is `VALUE_1`"] + #[doc = "counting down to 0 asserts the SysTick exception request"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == TICKINTSELECT_A::VALUE_1 } } #[doc = "Field `TICKINT` writer - Enables SysTick exception request"] -pub type TICKINT_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O, TICKINTSELECT_A>; -impl<'a, const O: u8> TICKINT_W<'a, O> { +pub type TICKINT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TICKINTSELECT_A>; +impl<'a, REG, const O: u8> TICKINT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "counting down to 0 does not assert the SysTick exception request"] #[inline(always)] - pub fn value_0(self) -> &'a mut W { + pub fn value_0(self) -> &'a mut crate::W { self.variant(TICKINTSELECT_A::VALUE_0) } #[doc = "counting down to 0 asserts the SysTick exception request"] #[inline(always)] - pub fn value_1(self) -> &'a mut W { + pub fn value_1(self) -> &'a mut crate::W { self.variant(TICKINTSELECT_A::VALUE_1) } } @@ -159,35 +133,38 @@ impl CLKSOURCE_R { true => CLKSOURCESELECT_A::VALUE_1, } } - #[doc = "Checks if the value of the field is `VALUE_0`"] + #[doc = "external clock"] #[inline(always)] pub fn is_value_0(&self) -> bool { *self == CLKSOURCESELECT_A::VALUE_0 } - #[doc = "Checks if the value of the field is `VALUE_1`"] + #[doc = "processor clock"] #[inline(always)] pub fn is_value_1(&self) -> bool { *self == CLKSOURCESELECT_A::VALUE_1 } } #[doc = "Field `CLKSOURCE` writer - Indicates the clock source"] -pub type CLKSOURCE_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O, CLKSOURCESELECT_A>; -impl<'a, const O: u8> CLKSOURCE_W<'a, O> { +pub type CLKSOURCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CLKSOURCESELECT_A>; +impl<'a, REG, const O: u8> CLKSOURCE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "external clock"] #[inline(always)] - pub fn value_0(self) -> &'a mut W { + pub fn value_0(self) -> &'a mut crate::W { self.variant(CLKSOURCESELECT_A::VALUE_0) } #[doc = "processor clock"] #[inline(always)] - pub fn value_1(self) -> &'a mut W { + pub fn value_1(self) -> &'a mut crate::W { self.variant(CLKSOURCESELECT_A::VALUE_1) } } #[doc = "Field `COUNTFLAG` reader - Returns 1 if timer counted to 0 since last time this was read"] pub type COUNTFLAG_R = crate::BitReader; #[doc = "Field `COUNTFLAG` writer - Returns 1 if timer counted to 0 since last time this was read"] -pub type COUNTFLAG_W<'a, const O: u8> = crate::BitWriter<'a, CSR_SPEC, O>; +pub type COUNTFLAG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enables the counter"] #[inline(always)] @@ -214,46 +191,43 @@ impl W { #[doc = "Bit 0 - Enables the counter"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bit 1 - Enables SysTick exception request"] #[inline(always)] #[must_use] - pub fn tickint(&mut self) -> TICKINT_W<1> { + pub fn tickint(&mut self) -> TICKINT_W { TICKINT_W::new(self) } #[doc = "Bit 2 - Indicates the clock source"] #[inline(always)] #[must_use] - pub fn clksource(&mut self) -> CLKSOURCE_W<2> { + pub fn clksource(&mut self) -> CLKSOURCE_W { CLKSOURCE_W::new(self) } #[doc = "Bit 16 - Returns 1 if timer counted to 0 since last time this was read"] #[inline(always)] #[must_use] - pub fn countflag(&mut self) -> COUNTFLAG_W<16> { + pub fn countflag(&mut self) -> COUNTFLAG_W { COUNTFLAG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csr](index.html) module"] +#[doc = "Control and Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSR_SPEC; impl crate::RegisterSpec for CSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [csr::R](R) reader structure"] -impl crate::Readable for CSR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [csr::W](W) writer structure"] +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] impl crate::Writable for CSR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/sys_tick/cvr.rs b/arch/cortex-m/samv71q21-pac/src/sys_tick/cvr.rs index baaf0b0e..0c14e5bd 100644 --- a/arch/cortex-m/samv71q21-pac/src/sys_tick/cvr.rs +++ b/arch/cortex-m/samv71q21-pac/src/sys_tick/cvr.rs @@ -1,43 +1,11 @@ #[doc = "Register `CVR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CVR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CURRENT` reader - Current value at the time the register is accessed"] pub type CURRENT_R = crate::FieldReader; #[doc = "Field `CURRENT` writer - Current value at the time the register is accessed"] -pub type CURRENT_W<'a, const O: u8> = crate::FieldWriter<'a, CVR_SPEC, 24, O, u32>; +pub type CURRENT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Current value at the time the register is accessed"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Current value at the time the register is accessed"] #[inline(always)] #[must_use] - pub fn current(&mut self) -> CURRENT_W<0> { + pub fn current(&mut self) -> CURRENT_W { CURRENT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Current Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cvr](index.html) module"] +#[doc = "Current Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cvr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CVR_SPEC; impl crate::RegisterSpec for CVR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cvr::R](R) reader structure"] -impl crate::Readable for CVR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cvr::W](W) writer structure"] +#[doc = "`read()` method returns [`cvr::R`](R) reader structure"] +impl crate::Readable for CVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cvr::W`](W) writer structure"] impl crate::Writable for CVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/sys_tick/rvr.rs b/arch/cortex-m/samv71q21-pac/src/sys_tick/rvr.rs index c2e198f0..ca31a7f7 100644 --- a/arch/cortex-m/samv71q21-pac/src/sys_tick/rvr.rs +++ b/arch/cortex-m/samv71q21-pac/src/sys_tick/rvr.rs @@ -1,43 +1,11 @@ #[doc = "Register `RVR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RVR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0"] pub type RELOAD_R = crate::FieldReader; #[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0"] -pub type RELOAD_W<'a, const O: u8> = crate::FieldWriter<'a, RVR_SPEC, 24, O, u32>; +pub type RELOAD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0"] #[inline(always)] #[must_use] - pub fn reload(&mut self) -> RELOAD_W<0> { + pub fn reload(&mut self) -> RELOAD_W { RELOAD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Reload Value Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rvr](index.html) module"] +#[doc = "Reload Value Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rvr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rvr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RVR_SPEC; impl crate::RegisterSpec for RVR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rvr::R](R) reader structure"] -impl crate::Readable for RVR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rvr::W](W) writer structure"] +#[doc = "`read()` method returns [`rvr::R`](R) reader structure"] +impl crate::Readable for RVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rvr::W`](W) writer structure"] impl crate::Writable for RVR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0.rs b/arch/cortex-m/samv71q21-pac/src/tc0.rs index c4c68e52..b2169849 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0.rs @@ -33,35 +33,43 @@ pub use self::tc_channel::TC_CHANNEL; #[doc = r"Cluster"] #[doc = "Channel Control Register (channel = 0)"] pub mod tc_channel; -#[doc = "BCR (w) register accessor: an alias for `Reg`"] +#[doc = "BCR (w) register accessor: Block Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bcr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`bcr`] +module"] pub type BCR = crate::Reg; #[doc = "Block Control Register"] pub mod bcr; -#[doc = "BMR (rw) register accessor: an alias for `Reg`"] +#[doc = "BMR (rw) register accessor: Block Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`bmr`] +module"] pub type BMR = crate::Reg; #[doc = "Block Mode Register"] pub mod bmr; -#[doc = "QIER (w) register accessor: an alias for `Reg`"] +#[doc = "QIER (w) register accessor: QDEC Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`qier`] +module"] pub type QIER = crate::Reg; #[doc = "QDEC Interrupt Enable Register"] pub mod qier; -#[doc = "QIDR (w) register accessor: an alias for `Reg`"] +#[doc = "QIDR (w) register accessor: QDEC Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qidr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`qidr`] +module"] pub type QIDR = crate::Reg; #[doc = "QDEC Interrupt Disable Register"] pub mod qidr; -#[doc = "QIMR (r) register accessor: an alias for `Reg`"] +#[doc = "QIMR (r) register accessor: QDEC Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`qimr`] +module"] pub type QIMR = crate::Reg; #[doc = "QDEC Interrupt Mask Register"] pub mod qimr; -#[doc = "QISR (r) register accessor: an alias for `Reg`"] +#[doc = "QISR (r) register accessor: QDEC Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`qisr`] +module"] pub type QISR = crate::Reg; #[doc = "QDEC Interrupt Status Register"] pub mod qisr; -#[doc = "FMR (rw) register accessor: an alias for `Reg`"] +#[doc = "FMR (rw) register accessor: Fault Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`fmr`] +module"] pub type FMR = crate::Reg; #[doc = "Fault Mode Register"] pub mod fmr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/bcr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/bcr.rs index 643d6651..a47bc9cb 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/bcr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/bcr.rs @@ -1,48 +1,28 @@ #[doc = "Register `BCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SYNC` writer - Synchro Command"] -pub type SYNC_W<'a, const O: u8> = crate::BitWriter<'a, BCR_SPEC, O>; +pub type SYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Synchro Command"] #[inline(always)] #[must_use] - pub fn sync(&mut self) -> SYNC_W<0> { + pub fn sync(&mut self) -> SYNC_W { SYNC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Block Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bcr](index.html) module"] +#[doc = "Block Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bcr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BCR_SPEC; impl crate::RegisterSpec for BCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [bcr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`bcr::W`](W) writer structure"] impl crate::Writable for BCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/bmr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/bmr.rs index f8ce1362..c1518281 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/bmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/bmr.rs @@ -1,39 +1,7 @@ #[doc = "Register `BMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TC0XC0S` reader - External Clock Signal 0 Selection"] pub type TC0XC0S_R = crate::FieldReader; #[doc = "External Clock Signal 0 Selection\n\nValue on reset: 0"] @@ -67,38 +35,42 @@ impl TC0XC0S_R { _ => None, } } - #[doc = "Checks if the value of the field is `TCLK0`"] + #[doc = "Signal connected to XC0: TCLK0"] #[inline(always)] pub fn is_tclk0(&self) -> bool { *self == TC0XC0SSELECT_A::TCLK0 } - #[doc = "Checks if the value of the field is `TIOA1`"] + #[doc = "Signal connected to XC0: TIOA1"] #[inline(always)] pub fn is_tioa1(&self) -> bool { *self == TC0XC0SSELECT_A::TIOA1 } - #[doc = "Checks if the value of the field is `TIOA2`"] + #[doc = "Signal connected to XC0: TIOA2"] #[inline(always)] pub fn is_tioa2(&self) -> bool { *self == TC0XC0SSELECT_A::TIOA2 } } #[doc = "Field `TC0XC0S` writer - External Clock Signal 0 Selection"] -pub type TC0XC0S_W<'a, const O: u8> = crate::FieldWriter<'a, BMR_SPEC, 2, O, TC0XC0SSELECT_A>; -impl<'a, const O: u8> TC0XC0S_W<'a, O> { +pub type TC0XC0S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TC0XC0SSELECT_A>; +impl<'a, REG, const O: u8> TC0XC0S_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Signal connected to XC0: TCLK0"] #[inline(always)] - pub fn tclk0(self) -> &'a mut W { + pub fn tclk0(self) -> &'a mut crate::W { self.variant(TC0XC0SSELECT_A::TCLK0) } #[doc = "Signal connected to XC0: TIOA1"] #[inline(always)] - pub fn tioa1(self) -> &'a mut W { + pub fn tioa1(self) -> &'a mut crate::W { self.variant(TC0XC0SSELECT_A::TIOA1) } #[doc = "Signal connected to XC0: TIOA2"] #[inline(always)] - pub fn tioa2(self) -> &'a mut W { + pub fn tioa2(self) -> &'a mut crate::W { self.variant(TC0XC0SSELECT_A::TIOA2) } } @@ -135,38 +107,42 @@ impl TC1XC1S_R { _ => None, } } - #[doc = "Checks if the value of the field is `TCLK1`"] + #[doc = "Signal connected to XC1: TCLK1"] #[inline(always)] pub fn is_tclk1(&self) -> bool { *self == TC1XC1SSELECT_A::TCLK1 } - #[doc = "Checks if the value of the field is `TIOA0`"] + #[doc = "Signal connected to XC1: TIOA0"] #[inline(always)] pub fn is_tioa0(&self) -> bool { *self == TC1XC1SSELECT_A::TIOA0 } - #[doc = "Checks if the value of the field is `TIOA2`"] + #[doc = "Signal connected to XC1: TIOA2"] #[inline(always)] pub fn is_tioa2(&self) -> bool { *self == TC1XC1SSELECT_A::TIOA2 } } #[doc = "Field `TC1XC1S` writer - External Clock Signal 1 Selection"] -pub type TC1XC1S_W<'a, const O: u8> = crate::FieldWriter<'a, BMR_SPEC, 2, O, TC1XC1SSELECT_A>; -impl<'a, const O: u8> TC1XC1S_W<'a, O> { +pub type TC1XC1S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TC1XC1SSELECT_A>; +impl<'a, REG, const O: u8> TC1XC1S_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Signal connected to XC1: TCLK1"] #[inline(always)] - pub fn tclk1(self) -> &'a mut W { + pub fn tclk1(self) -> &'a mut crate::W { self.variant(TC1XC1SSELECT_A::TCLK1) } #[doc = "Signal connected to XC1: TIOA0"] #[inline(always)] - pub fn tioa0(self) -> &'a mut W { + pub fn tioa0(self) -> &'a mut crate::W { self.variant(TC1XC1SSELECT_A::TIOA0) } #[doc = "Signal connected to XC1: TIOA2"] #[inline(always)] - pub fn tioa2(self) -> &'a mut W { + pub fn tioa2(self) -> &'a mut crate::W { self.variant(TC1XC1SSELECT_A::TIOA2) } } @@ -203,93 +179,97 @@ impl TC2XC2S_R { _ => None, } } - #[doc = "Checks if the value of the field is `TCLK2`"] + #[doc = "Signal connected to XC2: TCLK2"] #[inline(always)] pub fn is_tclk2(&self) -> bool { *self == TC2XC2SSELECT_A::TCLK2 } - #[doc = "Checks if the value of the field is `TIOA0`"] + #[doc = "Signal connected to XC2: TIOA0"] #[inline(always)] pub fn is_tioa0(&self) -> bool { *self == TC2XC2SSELECT_A::TIOA0 } - #[doc = "Checks if the value of the field is `TIOA1`"] + #[doc = "Signal connected to XC2: TIOA1"] #[inline(always)] pub fn is_tioa1(&self) -> bool { *self == TC2XC2SSELECT_A::TIOA1 } } #[doc = "Field `TC2XC2S` writer - External Clock Signal 2 Selection"] -pub type TC2XC2S_W<'a, const O: u8> = crate::FieldWriter<'a, BMR_SPEC, 2, O, TC2XC2SSELECT_A>; -impl<'a, const O: u8> TC2XC2S_W<'a, O> { +pub type TC2XC2S_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TC2XC2SSELECT_A>; +impl<'a, REG, const O: u8> TC2XC2S_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Signal connected to XC2: TCLK2"] #[inline(always)] - pub fn tclk2(self) -> &'a mut W { + pub fn tclk2(self) -> &'a mut crate::W { self.variant(TC2XC2SSELECT_A::TCLK2) } #[doc = "Signal connected to XC2: TIOA0"] #[inline(always)] - pub fn tioa0(self) -> &'a mut W { + pub fn tioa0(self) -> &'a mut crate::W { self.variant(TC2XC2SSELECT_A::TIOA0) } #[doc = "Signal connected to XC2: TIOA1"] #[inline(always)] - pub fn tioa1(self) -> &'a mut W { + pub fn tioa1(self) -> &'a mut crate::W { self.variant(TC2XC2SSELECT_A::TIOA1) } } #[doc = "Field `QDEN` reader - Quadrature Decoder Enabled"] pub type QDEN_R = crate::BitReader; #[doc = "Field `QDEN` writer - Quadrature Decoder Enabled"] -pub type QDEN_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type QDEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `POSEN` reader - Position Enabled"] pub type POSEN_R = crate::BitReader; #[doc = "Field `POSEN` writer - Position Enabled"] -pub type POSEN_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type POSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPEEDEN` reader - Speed Enabled"] pub type SPEEDEN_R = crate::BitReader; #[doc = "Field `SPEEDEN` writer - Speed Enabled"] -pub type SPEEDEN_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type SPEEDEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `QDTRANS` reader - Quadrature Decoding Transparent"] pub type QDTRANS_R = crate::BitReader; #[doc = "Field `QDTRANS` writer - Quadrature Decoding Transparent"] -pub type QDTRANS_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type QDTRANS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EDGPHA` reader - Edge on PHA Count Mode"] pub type EDGPHA_R = crate::BitReader; #[doc = "Field `EDGPHA` writer - Edge on PHA Count Mode"] -pub type EDGPHA_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type EDGPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVA` reader - Inverted PHA"] pub type INVA_R = crate::BitReader; #[doc = "Field `INVA` writer - Inverted PHA"] -pub type INVA_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type INVA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVB` reader - Inverted PHB"] pub type INVB_R = crate::BitReader; #[doc = "Field `INVB` writer - Inverted PHB"] -pub type INVB_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type INVB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVIDX` reader - Inverted Index"] pub type INVIDX_R = crate::BitReader; #[doc = "Field `INVIDX` writer - Inverted Index"] -pub type INVIDX_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type INVIDX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWAP` reader - Swap PHA and PHB"] pub type SWAP_R = crate::BitReader; #[doc = "Field `SWAP` writer - Swap PHA and PHB"] -pub type SWAP_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type SWAP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IDXPHB` reader - Index Pin is PHB Pin"] pub type IDXPHB_R = crate::BitReader; #[doc = "Field `IDXPHB` writer - Index Pin is PHB Pin"] -pub type IDXPHB_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type IDXPHB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `AUTOC` reader - AutoCorrection of missing pulses"] pub type AUTOC_R = crate::BitReader; #[doc = "Field `AUTOC` writer - AutoCorrection of missing pulses"] -pub type AUTOC_W<'a, const O: u8> = crate::BitWriter<'a, BMR_SPEC, O>; +pub type AUTOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MAXFILT` reader - Maximum Filter"] pub type MAXFILT_R = crate::FieldReader; #[doc = "Field `MAXFILT` writer - Maximum Filter"] -pub type MAXFILT_W<'a, const O: u8> = crate::FieldWriter<'a, BMR_SPEC, 6, O>; +pub type MAXFILT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `MAXCMP` reader - Maximum Consecutive Missing Pulses"] pub type MAXCMP_R = crate::FieldReader; #[doc = "Field `MAXCMP` writer - Maximum Consecutive Missing Pulses"] -pub type MAXCMP_W<'a, const O: u8> = crate::FieldWriter<'a, BMR_SPEC, 4, O>; +pub type MAXCMP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:1 - External Clock Signal 0 Selection"] #[inline(always)] @@ -376,118 +356,115 @@ impl W { #[doc = "Bits 0:1 - External Clock Signal 0 Selection"] #[inline(always)] #[must_use] - pub fn tc0xc0s(&mut self) -> TC0XC0S_W<0> { + pub fn tc0xc0s(&mut self) -> TC0XC0S_W { TC0XC0S_W::new(self) } #[doc = "Bits 2:3 - External Clock Signal 1 Selection"] #[inline(always)] #[must_use] - pub fn tc1xc1s(&mut self) -> TC1XC1S_W<2> { + pub fn tc1xc1s(&mut self) -> TC1XC1S_W { TC1XC1S_W::new(self) } #[doc = "Bits 4:5 - External Clock Signal 2 Selection"] #[inline(always)] #[must_use] - pub fn tc2xc2s(&mut self) -> TC2XC2S_W<4> { + pub fn tc2xc2s(&mut self) -> TC2XC2S_W { TC2XC2S_W::new(self) } #[doc = "Bit 8 - Quadrature Decoder Enabled"] #[inline(always)] #[must_use] - pub fn qden(&mut self) -> QDEN_W<8> { + pub fn qden(&mut self) -> QDEN_W { QDEN_W::new(self) } #[doc = "Bit 9 - Position Enabled"] #[inline(always)] #[must_use] - pub fn posen(&mut self) -> POSEN_W<9> { + pub fn posen(&mut self) -> POSEN_W { POSEN_W::new(self) } #[doc = "Bit 10 - Speed Enabled"] #[inline(always)] #[must_use] - pub fn speeden(&mut self) -> SPEEDEN_W<10> { + pub fn speeden(&mut self) -> SPEEDEN_W { SPEEDEN_W::new(self) } #[doc = "Bit 11 - Quadrature Decoding Transparent"] #[inline(always)] #[must_use] - pub fn qdtrans(&mut self) -> QDTRANS_W<11> { + pub fn qdtrans(&mut self) -> QDTRANS_W { QDTRANS_W::new(self) } #[doc = "Bit 12 - Edge on PHA Count Mode"] #[inline(always)] #[must_use] - pub fn edgpha(&mut self) -> EDGPHA_W<12> { + pub fn edgpha(&mut self) -> EDGPHA_W { EDGPHA_W::new(self) } #[doc = "Bit 13 - Inverted PHA"] #[inline(always)] #[must_use] - pub fn inva(&mut self) -> INVA_W<13> { + pub fn inva(&mut self) -> INVA_W { INVA_W::new(self) } #[doc = "Bit 14 - Inverted PHB"] #[inline(always)] #[must_use] - pub fn invb(&mut self) -> INVB_W<14> { + pub fn invb(&mut self) -> INVB_W { INVB_W::new(self) } #[doc = "Bit 15 - Inverted Index"] #[inline(always)] #[must_use] - pub fn invidx(&mut self) -> INVIDX_W<15> { + pub fn invidx(&mut self) -> INVIDX_W { INVIDX_W::new(self) } #[doc = "Bit 16 - Swap PHA and PHB"] #[inline(always)] #[must_use] - pub fn swap(&mut self) -> SWAP_W<16> { + pub fn swap(&mut self) -> SWAP_W { SWAP_W::new(self) } #[doc = "Bit 17 - Index Pin is PHB Pin"] #[inline(always)] #[must_use] - pub fn idxphb(&mut self) -> IDXPHB_W<17> { + pub fn idxphb(&mut self) -> IDXPHB_W { IDXPHB_W::new(self) } #[doc = "Bit 18 - AutoCorrection of missing pulses"] #[inline(always)] #[must_use] - pub fn autoc(&mut self) -> AUTOC_W<18> { + pub fn autoc(&mut self) -> AUTOC_W { AUTOC_W::new(self) } #[doc = "Bits 20:25 - Maximum Filter"] #[inline(always)] #[must_use] - pub fn maxfilt(&mut self) -> MAXFILT_W<20> { + pub fn maxfilt(&mut self) -> MAXFILT_W { MAXFILT_W::new(self) } #[doc = "Bits 26:29 - Maximum Consecutive Missing Pulses"] #[inline(always)] #[must_use] - pub fn maxcmp(&mut self) -> MAXCMP_W<26> { + pub fn maxcmp(&mut self) -> MAXCMP_W { MAXCMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Block Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bmr](index.html) module"] +#[doc = "Block Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BMR_SPEC; impl crate::RegisterSpec for BMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [bmr::R](R) reader structure"] -impl crate::Readable for BMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [bmr::W](W) writer structure"] +#[doc = "`read()` method returns [`bmr::R`](R) reader structure"] +impl crate::Readable for BMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bmr::W`](W) writer structure"] impl crate::Writable for BMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/fmr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/fmr.rs index 4e290765..49e4cb6f 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/fmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/fmr.rs @@ -1,47 +1,15 @@ #[doc = "Register `FMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENCF0` reader - Enable Compare Fault Channel 0"] pub type ENCF0_R = crate::BitReader; #[doc = "Field `ENCF0` writer - Enable Compare Fault Channel 0"] -pub type ENCF0_W<'a, const O: u8> = crate::BitWriter<'a, FMR_SPEC, O>; +pub type ENCF0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ENCF1` reader - Enable Compare Fault Channel 1"] pub type ENCF1_R = crate::BitReader; #[doc = "Field `ENCF1` writer - Enable Compare Fault Channel 1"] -pub type ENCF1_W<'a, const O: u8> = crate::BitWriter<'a, FMR_SPEC, O>; +pub type ENCF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Enable Compare Fault Channel 0"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 0 - Enable Compare Fault Channel 0"] #[inline(always)] #[must_use] - pub fn encf0(&mut self) -> ENCF0_W<0> { + pub fn encf0(&mut self) -> ENCF0_W { ENCF0_W::new(self) } #[doc = "Bit 1 - Enable Compare Fault Channel 1"] #[inline(always)] #[must_use] - pub fn encf1(&mut self) -> ENCF1_W<1> { + pub fn encf1(&mut self) -> ENCF1_W { ENCF1_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Fault Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fmr](index.html) module"] +#[doc = "Fault Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FMR_SPEC; impl crate::RegisterSpec for FMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [fmr::R](R) reader structure"] -impl crate::Readable for FMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [fmr::W](W) writer structure"] +#[doc = "`read()` method returns [`fmr::R`](R) reader structure"] +impl crate::Readable for FMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fmr::W`](W) writer structure"] impl crate::Writable for FMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/qidr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/qidr.rs index b89207bf..778885a6 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/qidr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/qidr.rs @@ -1,72 +1,52 @@ #[doc = "Register `QIDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IDX` writer - Index"] -pub type IDX_W<'a, const O: u8> = crate::BitWriter<'a, QIDR_SPEC, O>; +pub type IDX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIRCHG` writer - Direction Change"] -pub type DIRCHG_W<'a, const O: u8> = crate::BitWriter<'a, QIDR_SPEC, O>; +pub type DIRCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `QERR` writer - Quadrature Error"] -pub type QERR_W<'a, const O: u8> = crate::BitWriter<'a, QIDR_SPEC, O>; +pub type QERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MPE` writer - Consecutive Missing Pulse Error"] -pub type MPE_W<'a, const O: u8> = crate::BitWriter<'a, QIDR_SPEC, O>; +pub type MPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Index"] #[inline(always)] #[must_use] - pub fn idx(&mut self) -> IDX_W<0> { + pub fn idx(&mut self) -> IDX_W { IDX_W::new(self) } #[doc = "Bit 1 - Direction Change"] #[inline(always)] #[must_use] - pub fn dirchg(&mut self) -> DIRCHG_W<1> { + pub fn dirchg(&mut self) -> DIRCHG_W { DIRCHG_W::new(self) } #[doc = "Bit 2 - Quadrature Error"] #[inline(always)] #[must_use] - pub fn qerr(&mut self) -> QERR_W<2> { + pub fn qerr(&mut self) -> QERR_W { QERR_W::new(self) } #[doc = "Bit 3 - Consecutive Missing Pulse Error"] #[inline(always)] #[must_use] - pub fn mpe(&mut self) -> MPE_W<3> { + pub fn mpe(&mut self) -> MPE_W { MPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "QDEC Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qidr](index.html) module"] +#[doc = "QDEC Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qidr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct QIDR_SPEC; impl crate::RegisterSpec for QIDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [qidr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`qidr::W`](W) writer structure"] impl crate::Writable for QIDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/qier.rs b/arch/cortex-m/samv71q21-pac/src/tc0/qier.rs index 005ba829..56836c79 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/qier.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/qier.rs @@ -1,72 +1,52 @@ #[doc = "Register `QIER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IDX` writer - Index"] -pub type IDX_W<'a, const O: u8> = crate::BitWriter<'a, QIER_SPEC, O>; +pub type IDX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIRCHG` writer - Direction Change"] -pub type DIRCHG_W<'a, const O: u8> = crate::BitWriter<'a, QIER_SPEC, O>; +pub type DIRCHG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `QERR` writer - Quadrature Error"] -pub type QERR_W<'a, const O: u8> = crate::BitWriter<'a, QIER_SPEC, O>; +pub type QERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MPE` writer - Consecutive Missing Pulse Error"] -pub type MPE_W<'a, const O: u8> = crate::BitWriter<'a, QIER_SPEC, O>; +pub type MPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Index"] #[inline(always)] #[must_use] - pub fn idx(&mut self) -> IDX_W<0> { + pub fn idx(&mut self) -> IDX_W { IDX_W::new(self) } #[doc = "Bit 1 - Direction Change"] #[inline(always)] #[must_use] - pub fn dirchg(&mut self) -> DIRCHG_W<1> { + pub fn dirchg(&mut self) -> DIRCHG_W { DIRCHG_W::new(self) } #[doc = "Bit 2 - Quadrature Error"] #[inline(always)] #[must_use] - pub fn qerr(&mut self) -> QERR_W<2> { + pub fn qerr(&mut self) -> QERR_W { QERR_W::new(self) } #[doc = "Bit 3 - Consecutive Missing Pulse Error"] #[inline(always)] #[must_use] - pub fn mpe(&mut self) -> MPE_W<3> { + pub fn mpe(&mut self) -> MPE_W { MPE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "QDEC Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qier](index.html) module"] +#[doc = "QDEC Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct QIER_SPEC; impl crate::RegisterSpec for QIER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [qier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`qier::W`](W) writer structure"] impl crate::Writable for QIER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/qimr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/qimr.rs index de7163c2..18e2fa5e 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/qimr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/qimr.rs @@ -1,18 +1,5 @@ #[doc = "Register `QIMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IDX` reader - Index"] pub type IDX_R = crate::BitReader; #[doc = "Field `DIRCHG` reader - Direction Change"] @@ -43,15 +30,13 @@ impl R { MPE_R::new(((self.bits >> 3) & 1) != 0) } } -#[doc = "QDEC Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qimr](index.html) module"] +#[doc = "QDEC Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qimr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct QIMR_SPEC; impl crate::RegisterSpec for QIMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [qimr::R](R) reader structure"] -impl crate::Readable for QIMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`qimr::R`](R) reader structure"] +impl crate::Readable for QIMR_SPEC {} #[doc = "`reset()` method sets QIMR to value 0"] impl crate::Resettable for QIMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/qisr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/qisr.rs index 935b0d2c..486e5a86 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/qisr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/qisr.rs @@ -1,18 +1,5 @@ #[doc = "Register `QISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IDX` reader - Index"] pub type IDX_R = crate::BitReader; #[doc = "Field `DIRCHG` reader - Direction Change"] @@ -50,15 +37,13 @@ impl R { DIR_R::new(((self.bits >> 8) & 1) != 0) } } -#[doc = "QDEC Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qisr](index.html) module"] +#[doc = "QDEC Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct QISR_SPEC; impl crate::RegisterSpec for QISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [qisr::R](R) reader structure"] -impl crate::Readable for QISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`qisr::R`](R) reader structure"] +impl crate::Readable for QISR_SPEC {} #[doc = "`reset()` method sets QISR to value 0"] impl crate::Resettable for QISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel.rs index c0a1318e..b75bbf26 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel.rs @@ -39,59 +39,73 @@ impl TC_CHANNEL { unsafe { &*(self as *const Self).cast::().add(4usize).cast() } } } -#[doc = "CCR (w) register accessor: an alias for `Reg`"] +#[doc = "CCR (w) register accessor: Channel Control Register (channel = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ccr`] +module"] pub type CCR = crate::Reg; #[doc = "Channel Control Register (channel = 0)"] pub mod ccr; -#[doc = "CMR_CAPTURE_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "CMR_CAPTURE_MODE (rw) register accessor: Channel Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr_capture_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr_capture_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmr_capture_mode`] +module"] pub type CMR_CAPTURE_MODE = crate::Reg; #[doc = "Channel Mode Register (channel = 0)"] pub mod cmr_capture_mode; -#[doc = "CMR_WAVEFORM_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "CMR_WAVEFORM_MODE (rw) register accessor: Channel Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr_waveform_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr_waveform_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmr_waveform_mode`] +module"] pub type CMR_WAVEFORM_MODE = crate::Reg; #[doc = "Channel Mode Register (channel = 0)"] pub mod cmr_waveform_mode; -#[doc = "SMMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SMMR (rw) register accessor: Stepper Motor Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smmr`] +module"] pub type SMMR = crate::Reg; #[doc = "Stepper Motor Mode Register (channel = 0)"] pub mod smmr; -#[doc = "RAB (r) register accessor: an alias for `Reg`"] +#[doc = "RAB (r) register accessor: Register AB (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rab::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rab`] +module"] pub type RAB = crate::Reg; #[doc = "Register AB (channel = 0)"] pub mod rab; -#[doc = "CV (r) register accessor: an alias for `Reg`"] +#[doc = "CV (r) register accessor: Counter Value (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cv::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cv`] +module"] pub type CV = crate::Reg; #[doc = "Counter Value (channel = 0)"] pub mod cv; -#[doc = "RA (rw) register accessor: an alias for `Reg`"] +#[doc = "RA (rw) register accessor: Register A (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ra::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ra::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ra`] +module"] pub type RA = crate::Reg; #[doc = "Register A (channel = 0)"] pub mod ra; -#[doc = "RB (rw) register accessor: an alias for `Reg`"] +#[doc = "RB (rw) register accessor: Register B (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rb`] +module"] pub type RB = crate::Reg; #[doc = "Register B (channel = 0)"] pub mod rb; -#[doc = "RC (rw) register accessor: an alias for `Reg`"] +#[doc = "RC (rw) register accessor: Register C (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rc`] +module"] pub type RC = crate::Reg; #[doc = "Register C (channel = 0)"] pub mod rc; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register (channel = 0)"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register (channel = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register (channel = 0)"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register (channel = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register (channel = 0)"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register (channel = 0)"] pub mod imr; -#[doc = "EMR (rw) register accessor: an alias for `Reg`"] +#[doc = "EMR (rw) register accessor: Extended Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`emr`] +module"] pub type EMR = crate::Reg; #[doc = "Extended Mode Register (channel = 0)"] pub mod emr; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ccr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ccr.rs index 2abb7afa..34493624 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ccr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ccr.rs @@ -1,64 +1,44 @@ #[doc = "Register `CCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLKEN` writer - Counter Clock Enable Command"] -pub type CLKEN_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; +pub type CLKEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLKDIS` writer - Counter Clock Disable Command"] -pub type CLKDIS_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; +pub type CLKDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWTRG` writer - Software Trigger Command"] -pub type SWTRG_W<'a, const O: u8> = crate::BitWriter<'a, CCR_SPEC, O>; +pub type SWTRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Counter Clock Enable Command"] #[inline(always)] #[must_use] - pub fn clken(&mut self) -> CLKEN_W<0> { + pub fn clken(&mut self) -> CLKEN_W { CLKEN_W::new(self) } #[doc = "Bit 1 - Counter Clock Disable Command"] #[inline(always)] #[must_use] - pub fn clkdis(&mut self) -> CLKDIS_W<1> { + pub fn clkdis(&mut self) -> CLKDIS_W { CLKDIS_W::new(self) } #[doc = "Bit 2 - Software Trigger Command"] #[inline(always)] #[must_use] - pub fn swtrg(&mut self) -> SWTRG_W<2> { + pub fn swtrg(&mut self) -> SWTRG_W { SWTRG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Control Register (channel = 0)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccr](index.html) module"] +#[doc = "Channel Control Register (channel = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CCR_SPEC; impl crate::RegisterSpec for CCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ccr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] impl crate::Writable for CCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_capture_mode.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_capture_mode.rs index 016921e0..9dc87c64 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_capture_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_capture_mode.rs @@ -1,39 +1,7 @@ #[doc = "Register `CMR_CAPTURE_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMR_CAPTURE_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TCCLKS` reader - Clock Selection"] pub type TCCLKS_R = crate::FieldReader; #[doc = "Clock Selection\n\nValue on reset: 0"] @@ -82,96 +50,99 @@ impl TCCLKS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TIMER_CLOCK1`"] + #[doc = "Clock selected: internal PCK6 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock1(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK1 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK2`"] + #[doc = "Clock selected: internal MCK/8 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock2(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK2 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK3`"] + #[doc = "Clock selected: internal MCK/32 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock3(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK3 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK4`"] + #[doc = "Clock selected: internal MCK/128 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock4(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK4 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK5`"] + #[doc = "Clock selected: internal SLCK clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock5(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK5 } - #[doc = "Checks if the value of the field is `XC0`"] + #[doc = "Clock selected: XC0"] #[inline(always)] pub fn is_xc0(&self) -> bool { *self == TCCLKSSELECT_A::XC0 } - #[doc = "Checks if the value of the field is `XC1`"] + #[doc = "Clock selected: XC1"] #[inline(always)] pub fn is_xc1(&self) -> bool { *self == TCCLKSSELECT_A::XC1 } - #[doc = "Checks if the value of the field is `XC2`"] + #[doc = "Clock selected: XC2"] #[inline(always)] pub fn is_xc2(&self) -> bool { *self == TCCLKSSELECT_A::XC2 } } #[doc = "Field `TCCLKS` writer - Clock Selection"] -pub type TCCLKS_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_CAPTURE_MODE_SPEC, 3, O, TCCLKSSELECT_A>; -impl<'a, const O: u8> TCCLKS_W<'a, O> { +pub type TCCLKS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, TCCLKSSELECT_A>; +impl<'a, REG, const O: u8> TCCLKS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Clock selected: internal PCK6 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock1(self) -> &'a mut W { + pub fn timer_clock1(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK1) } #[doc = "Clock selected: internal MCK/8 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock2(self) -> &'a mut W { + pub fn timer_clock2(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK2) } #[doc = "Clock selected: internal MCK/32 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock3(self) -> &'a mut W { + pub fn timer_clock3(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK3) } #[doc = "Clock selected: internal MCK/128 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock4(self) -> &'a mut W { + pub fn timer_clock4(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK4) } #[doc = "Clock selected: internal SLCK clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock5(self) -> &'a mut W { + pub fn timer_clock5(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK5) } #[doc = "Clock selected: XC0"] #[inline(always)] - pub fn xc0(self) -> &'a mut W { + pub fn xc0(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::XC0) } #[doc = "Clock selected: XC1"] #[inline(always)] - pub fn xc1(self) -> &'a mut W { + pub fn xc1(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::XC1) } #[doc = "Clock selected: XC2"] #[inline(always)] - pub fn xc2(self) -> &'a mut W { + pub fn xc2(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::XC2) } } #[doc = "Field `CLKI` reader - Clock Invert"] pub type CLKI_R = crate::BitReader; #[doc = "Field `CLKI` writer - Clock Invert"] -pub type CLKI_W<'a, const O: u8> = crate::BitWriter<'a, CMR_CAPTURE_MODE_SPEC, O>; +pub type CLKI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BURST` reader - Burst Signal Selection"] pub type BURST_R = crate::FieldReader; #[doc = "Burst Signal Selection\n\nValue on reset: 0"] @@ -208,60 +179,63 @@ impl BURST_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "The clock is not gated by an external signal."] #[inline(always)] pub fn is_none(&self) -> bool { *self == BURSTSELECT_A::NONE } - #[doc = "Checks if the value of the field is `XC0`"] + #[doc = "XC0 is ANDed with the selected clock."] #[inline(always)] pub fn is_xc0(&self) -> bool { *self == BURSTSELECT_A::XC0 } - #[doc = "Checks if the value of the field is `XC1`"] + #[doc = "XC1 is ANDed with the selected clock."] #[inline(always)] pub fn is_xc1(&self) -> bool { *self == BURSTSELECT_A::XC1 } - #[doc = "Checks if the value of the field is `XC2`"] + #[doc = "XC2 is ANDed with the selected clock."] #[inline(always)] pub fn is_xc2(&self) -> bool { *self == BURSTSELECT_A::XC2 } } #[doc = "Field `BURST` writer - Burst Signal Selection"] -pub type BURST_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_CAPTURE_MODE_SPEC, 2, O, BURSTSELECT_A>; -impl<'a, const O: u8> BURST_W<'a, O> { +pub type BURST_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BURSTSELECT_A>; +impl<'a, REG, const O: u8> BURST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The clock is not gated by an external signal."] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::NONE) } #[doc = "XC0 is ANDed with the selected clock."] #[inline(always)] - pub fn xc0(self) -> &'a mut W { + pub fn xc0(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::XC0) } #[doc = "XC1 is ANDed with the selected clock."] #[inline(always)] - pub fn xc1(self) -> &'a mut W { + pub fn xc1(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::XC1) } #[doc = "XC2 is ANDed with the selected clock."] #[inline(always)] - pub fn xc2(self) -> &'a mut W { + pub fn xc2(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::XC2) } } #[doc = "Field `LDBSTOP` reader - Counter Clock Stopped with RB Loading"] pub type LDBSTOP_R = crate::BitReader; #[doc = "Field `LDBSTOP` writer - Counter Clock Stopped with RB Loading"] -pub type LDBSTOP_W<'a, const O: u8> = crate::BitWriter<'a, CMR_CAPTURE_MODE_SPEC, O>; +pub type LDBSTOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDBDIS` reader - Counter Clock Disable with RB Loading"] pub type LDBDIS_R = crate::BitReader; #[doc = "Field `LDBDIS` writer - Counter Clock Disable with RB Loading"] -pub type LDBDIS_W<'a, const O: u8> = crate::BitWriter<'a, CMR_CAPTURE_MODE_SPEC, O>; +pub type LDBDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETRGEDG` reader - External Trigger Edge Selection"] pub type ETRGEDG_R = crate::FieldReader; #[doc = "External Trigger Edge Selection\n\nValue on reset: 0"] @@ -298,64 +272,67 @@ impl ETRGEDG_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "The clock is not gated by an external signal."] #[inline(always)] pub fn is_none(&self) -> bool { *self == ETRGEDGSELECT_A::NONE } - #[doc = "Checks if the value of the field is `RISING`"] + #[doc = "Rising edge"] #[inline(always)] pub fn is_rising(&self) -> bool { *self == ETRGEDGSELECT_A::RISING } - #[doc = "Checks if the value of the field is `FALLING`"] + #[doc = "Falling edge"] #[inline(always)] pub fn is_falling(&self) -> bool { *self == ETRGEDGSELECT_A::FALLING } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Each edge"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == ETRGEDGSELECT_A::EDGE } } #[doc = "Field `ETRGEDG` writer - External Trigger Edge Selection"] -pub type ETRGEDG_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_CAPTURE_MODE_SPEC, 2, O, ETRGEDGSELECT_A>; -impl<'a, const O: u8> ETRGEDG_W<'a, O> { +pub type ETRGEDG_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, ETRGEDGSELECT_A>; +impl<'a, REG, const O: u8> ETRGEDG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The clock is not gated by an external signal."] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(ETRGEDGSELECT_A::NONE) } #[doc = "Rising edge"] #[inline(always)] - pub fn rising(self) -> &'a mut W { + pub fn rising(self) -> &'a mut crate::W { self.variant(ETRGEDGSELECT_A::RISING) } #[doc = "Falling edge"] #[inline(always)] - pub fn falling(self) -> &'a mut W { + pub fn falling(self) -> &'a mut crate::W { self.variant(ETRGEDGSELECT_A::FALLING) } #[doc = "Each edge"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(ETRGEDGSELECT_A::EDGE) } } #[doc = "Field `ABETRG` reader - TIOAx or TIOBx External Trigger Selection"] pub type ABETRG_R = crate::BitReader; #[doc = "Field `ABETRG` writer - TIOAx or TIOBx External Trigger Selection"] -pub type ABETRG_W<'a, const O: u8> = crate::BitWriter<'a, CMR_CAPTURE_MODE_SPEC, O>; +pub type ABETRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPCTRG` reader - RC Compare Trigger Enable"] pub type CPCTRG_R = crate::BitReader; #[doc = "Field `CPCTRG` writer - RC Compare Trigger Enable"] -pub type CPCTRG_W<'a, const O: u8> = crate::BitWriter<'a, CMR_CAPTURE_MODE_SPEC, O>; +pub type CPCTRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAVE` reader - Waveform Mode"] pub type WAVE_R = crate::BitReader; #[doc = "Field `WAVE` writer - Waveform Mode"] -pub type WAVE_W<'a, const O: u8> = crate::BitWriter<'a, CMR_CAPTURE_MODE_SPEC, O>; +pub type WAVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDRA` reader - RA Loading Edge Selection"] pub type LDRA_R = crate::FieldReader; #[doc = "RA Loading Edge Selection\n\nValue on reset: 0"] @@ -392,49 +369,52 @@ impl LDRA_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None"] #[inline(always)] pub fn is_none(&self) -> bool { *self == LDRASELECT_A::NONE } - #[doc = "Checks if the value of the field is `RISING`"] + #[doc = "Rising edge of TIOAx"] #[inline(always)] pub fn is_rising(&self) -> bool { *self == LDRASELECT_A::RISING } - #[doc = "Checks if the value of the field is `FALLING`"] + #[doc = "Falling edge of TIOAx"] #[inline(always)] pub fn is_falling(&self) -> bool { *self == LDRASELECT_A::FALLING } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Each edge of TIOAx"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == LDRASELECT_A::EDGE } } #[doc = "Field `LDRA` writer - RA Loading Edge Selection"] -pub type LDRA_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_CAPTURE_MODE_SPEC, 2, O, LDRASELECT_A>; -impl<'a, const O: u8> LDRA_W<'a, O> { +pub type LDRA_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, LDRASELECT_A>; +impl<'a, REG, const O: u8> LDRA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(LDRASELECT_A::NONE) } #[doc = "Rising edge of TIOAx"] #[inline(always)] - pub fn rising(self) -> &'a mut W { + pub fn rising(self) -> &'a mut crate::W { self.variant(LDRASELECT_A::RISING) } #[doc = "Falling edge of TIOAx"] #[inline(always)] - pub fn falling(self) -> &'a mut W { + pub fn falling(self) -> &'a mut crate::W { self.variant(LDRASELECT_A::FALLING) } #[doc = "Each edge of TIOAx"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(LDRASELECT_A::EDGE) } } @@ -474,49 +454,52 @@ impl LDRB_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None"] #[inline(always)] pub fn is_none(&self) -> bool { *self == LDRBSELECT_A::NONE } - #[doc = "Checks if the value of the field is `RISING`"] + #[doc = "Rising edge of TIOAx"] #[inline(always)] pub fn is_rising(&self) -> bool { *self == LDRBSELECT_A::RISING } - #[doc = "Checks if the value of the field is `FALLING`"] + #[doc = "Falling edge of TIOAx"] #[inline(always)] pub fn is_falling(&self) -> bool { *self == LDRBSELECT_A::FALLING } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Each edge of TIOAx"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == LDRBSELECT_A::EDGE } } #[doc = "Field `LDRB` writer - RB Loading Edge Selection"] -pub type LDRB_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_CAPTURE_MODE_SPEC, 2, O, LDRBSELECT_A>; -impl<'a, const O: u8> LDRB_W<'a, O> { +pub type LDRB_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, LDRBSELECT_A>; +impl<'a, REG, const O: u8> LDRB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(LDRBSELECT_A::NONE) } #[doc = "Rising edge of TIOAx"] #[inline(always)] - pub fn rising(self) -> &'a mut W { + pub fn rising(self) -> &'a mut crate::W { self.variant(LDRBSELECT_A::RISING) } #[doc = "Falling edge of TIOAx"] #[inline(always)] - pub fn falling(self) -> &'a mut W { + pub fn falling(self) -> &'a mut crate::W { self.variant(LDRBSELECT_A::FALLING) } #[doc = "Each edge of TIOAx"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(LDRBSELECT_A::EDGE) } } @@ -559,59 +542,62 @@ impl SBSMPLR_R { _ => None, } } - #[doc = "Checks if the value of the field is `ONE`"] + #[doc = "Load a Capture Register each selected edge"] #[inline(always)] pub fn is_one(&self) -> bool { *self == SBSMPLRSELECT_A::ONE } - #[doc = "Checks if the value of the field is `HALF`"] + #[doc = "Load a Capture Register every 2 selected edges"] #[inline(always)] pub fn is_half(&self) -> bool { *self == SBSMPLRSELECT_A::HALF } - #[doc = "Checks if the value of the field is `FOURTH`"] + #[doc = "Load a Capture Register every 4 selected edges"] #[inline(always)] pub fn is_fourth(&self) -> bool { *self == SBSMPLRSELECT_A::FOURTH } - #[doc = "Checks if the value of the field is `EIGHTH`"] + #[doc = "Load a Capture Register every 8 selected edges"] #[inline(always)] pub fn is_eighth(&self) -> bool { *self == SBSMPLRSELECT_A::EIGHTH } - #[doc = "Checks if the value of the field is `SIXTEENTH`"] + #[doc = "Load a Capture Register every 16 selected edges"] #[inline(always)] pub fn is_sixteenth(&self) -> bool { *self == SBSMPLRSELECT_A::SIXTEENTH } } #[doc = "Field `SBSMPLR` writer - Loading Edge Subsampling Ratio"] -pub type SBSMPLR_W<'a, const O: u8> = - crate::FieldWriter<'a, CMR_CAPTURE_MODE_SPEC, 3, O, SBSMPLRSELECT_A>; -impl<'a, const O: u8> SBSMPLR_W<'a, O> { +pub type SBSMPLR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, SBSMPLRSELECT_A>; +impl<'a, REG, const O: u8> SBSMPLR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Load a Capture Register each selected edge"] #[inline(always)] - pub fn one(self) -> &'a mut W { + pub fn one(self) -> &'a mut crate::W { self.variant(SBSMPLRSELECT_A::ONE) } #[doc = "Load a Capture Register every 2 selected edges"] #[inline(always)] - pub fn half(self) -> &'a mut W { + pub fn half(self) -> &'a mut crate::W { self.variant(SBSMPLRSELECT_A::HALF) } #[doc = "Load a Capture Register every 4 selected edges"] #[inline(always)] - pub fn fourth(self) -> &'a mut W { + pub fn fourth(self) -> &'a mut crate::W { self.variant(SBSMPLRSELECT_A::FOURTH) } #[doc = "Load a Capture Register every 8 selected edges"] #[inline(always)] - pub fn eighth(self) -> &'a mut W { + pub fn eighth(self) -> &'a mut crate::W { self.variant(SBSMPLRSELECT_A::EIGHTH) } #[doc = "Load a Capture Register every 16 selected edges"] #[inline(always)] - pub fn sixteenth(self) -> &'a mut W { + pub fn sixteenth(self) -> &'a mut crate::W { self.variant(SBSMPLRSELECT_A::SIXTEENTH) } } @@ -681,94 +667,91 @@ impl W { #[doc = "Bits 0:2 - Clock Selection"] #[inline(always)] #[must_use] - pub fn tcclks(&mut self) -> TCCLKS_W<0> { + pub fn tcclks(&mut self) -> TCCLKS_W { TCCLKS_W::new(self) } #[doc = "Bit 3 - Clock Invert"] #[inline(always)] #[must_use] - pub fn clki(&mut self) -> CLKI_W<3> { + pub fn clki(&mut self) -> CLKI_W { CLKI_W::new(self) } #[doc = "Bits 4:5 - Burst Signal Selection"] #[inline(always)] #[must_use] - pub fn burst(&mut self) -> BURST_W<4> { + pub fn burst(&mut self) -> BURST_W { BURST_W::new(self) } #[doc = "Bit 6 - Counter Clock Stopped with RB Loading"] #[inline(always)] #[must_use] - pub fn ldbstop(&mut self) -> LDBSTOP_W<6> { + pub fn ldbstop(&mut self) -> LDBSTOP_W { LDBSTOP_W::new(self) } #[doc = "Bit 7 - Counter Clock Disable with RB Loading"] #[inline(always)] #[must_use] - pub fn ldbdis(&mut self) -> LDBDIS_W<7> { + pub fn ldbdis(&mut self) -> LDBDIS_W { LDBDIS_W::new(self) } #[doc = "Bits 8:9 - External Trigger Edge Selection"] #[inline(always)] #[must_use] - pub fn etrgedg(&mut self) -> ETRGEDG_W<8> { + pub fn etrgedg(&mut self) -> ETRGEDG_W { ETRGEDG_W::new(self) } #[doc = "Bit 10 - TIOAx or TIOBx External Trigger Selection"] #[inline(always)] #[must_use] - pub fn abetrg(&mut self) -> ABETRG_W<10> { + pub fn abetrg(&mut self) -> ABETRG_W { ABETRG_W::new(self) } #[doc = "Bit 14 - RC Compare Trigger Enable"] #[inline(always)] #[must_use] - pub fn cpctrg(&mut self) -> CPCTRG_W<14> { + pub fn cpctrg(&mut self) -> CPCTRG_W { CPCTRG_W::new(self) } #[doc = "Bit 15 - Waveform Mode"] #[inline(always)] #[must_use] - pub fn wave(&mut self) -> WAVE_W<15> { + pub fn wave(&mut self) -> WAVE_W { WAVE_W::new(self) } #[doc = "Bits 16:17 - RA Loading Edge Selection"] #[inline(always)] #[must_use] - pub fn ldra(&mut self) -> LDRA_W<16> { + pub fn ldra(&mut self) -> LDRA_W { LDRA_W::new(self) } #[doc = "Bits 18:19 - RB Loading Edge Selection"] #[inline(always)] #[must_use] - pub fn ldrb(&mut self) -> LDRB_W<18> { + pub fn ldrb(&mut self) -> LDRB_W { LDRB_W::new(self) } #[doc = "Bits 20:22 - Loading Edge Subsampling Ratio"] #[inline(always)] #[must_use] - pub fn sbsmplr(&mut self) -> SBSMPLR_W<20> { + pub fn sbsmplr(&mut self) -> SBSMPLR_W { SBSMPLR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Mode Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr_capture_mode](index.html) module"] +#[doc = "Channel Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr_capture_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr_capture_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMR_CAPTURE_MODE_SPEC; impl crate::RegisterSpec for CMR_CAPTURE_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmr_capture_mode::R](R) reader structure"] -impl crate::Readable for CMR_CAPTURE_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmr_capture_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`cmr_capture_mode::R`](R) reader structure"] +impl crate::Readable for CMR_CAPTURE_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmr_capture_mode::W`](W) writer structure"] impl crate::Writable for CMR_CAPTURE_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_waveform_mode.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_waveform_mode.rs index ff9081ee..fc9b2835 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_waveform_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cmr_waveform_mode.rs @@ -1,39 +1,7 @@ #[doc = "Register `CMR_WAVEFORM_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMR_WAVEFORM_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TCCLKS` reader - Clock Selection"] pub type TCCLKS_R = crate::FieldReader; #[doc = "Clock Selection\n\nValue on reset: 0"] @@ -82,96 +50,99 @@ impl TCCLKS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TIMER_CLOCK1`"] + #[doc = "Clock selected: internal PCK6 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock1(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK1 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK2`"] + #[doc = "Clock selected: internal MCK/8 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock2(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK2 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK3`"] + #[doc = "Clock selected: internal MCK/32 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock3(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK3 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK4`"] + #[doc = "Clock selected: internal MCK/128 clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock4(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK4 } - #[doc = "Checks if the value of the field is `TIMER_CLOCK5`"] + #[doc = "Clock selected: internal SLCK clock signal (from PMC)"] #[inline(always)] pub fn is_timer_clock5(&self) -> bool { *self == TCCLKSSELECT_A::TIMER_CLOCK5 } - #[doc = "Checks if the value of the field is `XC0`"] + #[doc = "Clock selected: XC0"] #[inline(always)] pub fn is_xc0(&self) -> bool { *self == TCCLKSSELECT_A::XC0 } - #[doc = "Checks if the value of the field is `XC1`"] + #[doc = "Clock selected: XC1"] #[inline(always)] pub fn is_xc1(&self) -> bool { *self == TCCLKSSELECT_A::XC1 } - #[doc = "Checks if the value of the field is `XC2`"] + #[doc = "Clock selected: XC2"] #[inline(always)] pub fn is_xc2(&self) -> bool { *self == TCCLKSSELECT_A::XC2 } } #[doc = "Field `TCCLKS` writer - Clock Selection"] -pub type TCCLKS_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 3, O, TCCLKSSELECT_A>; -impl<'a, const O: u8> TCCLKS_W<'a, O> { +pub type TCCLKS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, TCCLKSSELECT_A>; +impl<'a, REG, const O: u8> TCCLKS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Clock selected: internal PCK6 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock1(self) -> &'a mut W { + pub fn timer_clock1(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK1) } #[doc = "Clock selected: internal MCK/8 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock2(self) -> &'a mut W { + pub fn timer_clock2(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK2) } #[doc = "Clock selected: internal MCK/32 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock3(self) -> &'a mut W { + pub fn timer_clock3(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK3) } #[doc = "Clock selected: internal MCK/128 clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock4(self) -> &'a mut W { + pub fn timer_clock4(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK4) } #[doc = "Clock selected: internal SLCK clock signal (from PMC)"] #[inline(always)] - pub fn timer_clock5(self) -> &'a mut W { + pub fn timer_clock5(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::TIMER_CLOCK5) } #[doc = "Clock selected: XC0"] #[inline(always)] - pub fn xc0(self) -> &'a mut W { + pub fn xc0(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::XC0) } #[doc = "Clock selected: XC1"] #[inline(always)] - pub fn xc1(self) -> &'a mut W { + pub fn xc1(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::XC1) } #[doc = "Clock selected: XC2"] #[inline(always)] - pub fn xc2(self) -> &'a mut W { + pub fn xc2(self) -> &'a mut crate::W { self.variant(TCCLKSSELECT_A::XC2) } } #[doc = "Field `CLKI` reader - Clock Invert"] pub type CLKI_R = crate::BitReader; #[doc = "Field `CLKI` writer - Clock Invert"] -pub type CLKI_W<'a, const O: u8> = crate::BitWriter<'a, CMR_WAVEFORM_MODE_SPEC, O>; +pub type CLKI_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BURST` reader - Burst Signal Selection"] pub type BURST_R = crate::FieldReader; #[doc = "Burst Signal Selection\n\nValue on reset: 0"] @@ -208,60 +179,63 @@ impl BURST_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "The clock is not gated by an external signal."] #[inline(always)] pub fn is_none(&self) -> bool { *self == BURSTSELECT_A::NONE } - #[doc = "Checks if the value of the field is `XC0`"] + #[doc = "XC0 is ANDed with the selected clock."] #[inline(always)] pub fn is_xc0(&self) -> bool { *self == BURSTSELECT_A::XC0 } - #[doc = "Checks if the value of the field is `XC1`"] + #[doc = "XC1 is ANDed with the selected clock."] #[inline(always)] pub fn is_xc1(&self) -> bool { *self == BURSTSELECT_A::XC1 } - #[doc = "Checks if the value of the field is `XC2`"] + #[doc = "XC2 is ANDed with the selected clock."] #[inline(always)] pub fn is_xc2(&self) -> bool { *self == BURSTSELECT_A::XC2 } } #[doc = "Field `BURST` writer - Burst Signal Selection"] -pub type BURST_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, BURSTSELECT_A>; -impl<'a, const O: u8> BURST_W<'a, O> { +pub type BURST_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BURSTSELECT_A>; +impl<'a, REG, const O: u8> BURST_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The clock is not gated by an external signal."] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::NONE) } #[doc = "XC0 is ANDed with the selected clock."] #[inline(always)] - pub fn xc0(self) -> &'a mut W { + pub fn xc0(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::XC0) } #[doc = "XC1 is ANDed with the selected clock."] #[inline(always)] - pub fn xc1(self) -> &'a mut W { + pub fn xc1(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::XC1) } #[doc = "XC2 is ANDed with the selected clock."] #[inline(always)] - pub fn xc2(self) -> &'a mut W { + pub fn xc2(self) -> &'a mut crate::W { self.variant(BURSTSELECT_A::XC2) } } #[doc = "Field `CPCSTOP` reader - Counter Clock Stopped with RC Compare"] pub type CPCSTOP_R = crate::BitReader; #[doc = "Field `CPCSTOP` writer - Counter Clock Stopped with RC Compare"] -pub type CPCSTOP_W<'a, const O: u8> = crate::BitWriter<'a, CMR_WAVEFORM_MODE_SPEC, O>; +pub type CPCSTOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPCDIS` reader - Counter Clock Disable with RC Loading"] pub type CPCDIS_R = crate::BitReader; #[doc = "Field `CPCDIS` writer - Counter Clock Disable with RC Loading"] -pub type CPCDIS_W<'a, const O: u8> = crate::BitWriter<'a, CMR_WAVEFORM_MODE_SPEC, O>; +pub type CPCDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EEVTEDG` reader - External Event Edge Selection"] pub type EEVTEDG_R = crate::FieldReader; #[doc = "External Event Edge Selection\n\nValue on reset: 0"] @@ -298,49 +272,52 @@ impl EEVTEDG_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "None"] #[inline(always)] pub fn is_none(&self) -> bool { *self == EEVTEDGSELECT_A::NONE } - #[doc = "Checks if the value of the field is `RISING`"] + #[doc = "Rising edge"] #[inline(always)] pub fn is_rising(&self) -> bool { *self == EEVTEDGSELECT_A::RISING } - #[doc = "Checks if the value of the field is `FALLING`"] + #[doc = "Falling edge"] #[inline(always)] pub fn is_falling(&self) -> bool { *self == EEVTEDGSELECT_A::FALLING } - #[doc = "Checks if the value of the field is `EDGE`"] + #[doc = "Each edges"] #[inline(always)] pub fn is_edge(&self) -> bool { *self == EEVTEDGSELECT_A::EDGE } } #[doc = "Field `EEVTEDG` writer - External Event Edge Selection"] -pub type EEVTEDG_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, EEVTEDGSELECT_A>; -impl<'a, const O: u8> EEVTEDG_W<'a, O> { +pub type EEVTEDG_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, EEVTEDGSELECT_A>; +impl<'a, REG, const O: u8> EEVTEDG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "None"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(EEVTEDGSELECT_A::NONE) } #[doc = "Rising edge"] #[inline(always)] - pub fn rising(self) -> &'a mut W { + pub fn rising(self) -> &'a mut crate::W { self.variant(EEVTEDGSELECT_A::RISING) } #[doc = "Falling edge"] #[inline(always)] - pub fn falling(self) -> &'a mut W { + pub fn falling(self) -> &'a mut crate::W { self.variant(EEVTEDGSELECT_A::FALLING) } #[doc = "Each edges"] #[inline(always)] - pub fn edge(self) -> &'a mut W { + pub fn edge(self) -> &'a mut crate::W { self.variant(EEVTEDGSELECT_A::EDGE) } } @@ -380,56 +357,59 @@ impl EEVT_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `TIOB`"] + #[doc = "TIOB"] #[inline(always)] pub fn is_tiob(&self) -> bool { *self == EEVTSELECT_A::TIOB } - #[doc = "Checks if the value of the field is `XC0`"] + #[doc = "XC0"] #[inline(always)] pub fn is_xc0(&self) -> bool { *self == EEVTSELECT_A::XC0 } - #[doc = "Checks if the value of the field is `XC1`"] + #[doc = "XC1"] #[inline(always)] pub fn is_xc1(&self) -> bool { *self == EEVTSELECT_A::XC1 } - #[doc = "Checks if the value of the field is `XC2`"] + #[doc = "XC2"] #[inline(always)] pub fn is_xc2(&self) -> bool { *self == EEVTSELECT_A::XC2 } } #[doc = "Field `EEVT` writer - External Event Selection"] -pub type EEVT_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, EEVTSELECT_A>; -impl<'a, const O: u8> EEVT_W<'a, O> { +pub type EEVT_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, EEVTSELECT_A>; +impl<'a, REG, const O: u8> EEVT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "TIOB"] #[inline(always)] - pub fn tiob(self) -> &'a mut W { + pub fn tiob(self) -> &'a mut crate::W { self.variant(EEVTSELECT_A::TIOB) } #[doc = "XC0"] #[inline(always)] - pub fn xc0(self) -> &'a mut W { + pub fn xc0(self) -> &'a mut crate::W { self.variant(EEVTSELECT_A::XC0) } #[doc = "XC1"] #[inline(always)] - pub fn xc1(self) -> &'a mut W { + pub fn xc1(self) -> &'a mut crate::W { self.variant(EEVTSELECT_A::XC1) } #[doc = "XC2"] #[inline(always)] - pub fn xc2(self) -> &'a mut W { + pub fn xc2(self) -> &'a mut crate::W { self.variant(EEVTSELECT_A::XC2) } } #[doc = "Field `ENETRG` reader - External Event Trigger Enable"] pub type ENETRG_R = crate::BitReader; #[doc = "Field `ENETRG` writer - External Event Trigger Enable"] -pub type ENETRG_W<'a, const O: u8> = crate::BitWriter<'a, CMR_WAVEFORM_MODE_SPEC, O>; +pub type ENETRG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAVSEL` reader - Waveform Selection"] pub type WAVSEL_R = crate::FieldReader; #[doc = "Waveform Selection\n\nValue on reset: 0"] @@ -466,56 +446,59 @@ impl WAVSEL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `UP`"] + #[doc = "UP mode without automatic trigger on RC Compare"] #[inline(always)] pub fn is_up(&self) -> bool { *self == WAVSELSELECT_A::UP } - #[doc = "Checks if the value of the field is `UPDOWN`"] + #[doc = "UPDOWN mode without automatic trigger on RC Compare"] #[inline(always)] pub fn is_updown(&self) -> bool { *self == WAVSELSELECT_A::UPDOWN } - #[doc = "Checks if the value of the field is `UP_RC`"] + #[doc = "UP mode with automatic trigger on RC Compare"] #[inline(always)] pub fn is_up_rc(&self) -> bool { *self == WAVSELSELECT_A::UP_RC } - #[doc = "Checks if the value of the field is `UPDOWN_RC`"] + #[doc = "UPDOWN mode with automatic trigger on RC Compare"] #[inline(always)] pub fn is_updown_rc(&self) -> bool { *self == WAVSELSELECT_A::UPDOWN_RC } } #[doc = "Field `WAVSEL` writer - Waveform Selection"] -pub type WAVSEL_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, WAVSELSELECT_A>; -impl<'a, const O: u8> WAVSEL_W<'a, O> { +pub type WAVSEL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, WAVSELSELECT_A>; +impl<'a, REG, const O: u8> WAVSEL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "UP mode without automatic trigger on RC Compare"] #[inline(always)] - pub fn up(self) -> &'a mut W { + pub fn up(self) -> &'a mut crate::W { self.variant(WAVSELSELECT_A::UP) } #[doc = "UPDOWN mode without automatic trigger on RC Compare"] #[inline(always)] - pub fn updown(self) -> &'a mut W { + pub fn updown(self) -> &'a mut crate::W { self.variant(WAVSELSELECT_A::UPDOWN) } #[doc = "UP mode with automatic trigger on RC Compare"] #[inline(always)] - pub fn up_rc(self) -> &'a mut W { + pub fn up_rc(self) -> &'a mut crate::W { self.variant(WAVSELSELECT_A::UP_RC) } #[doc = "UPDOWN mode with automatic trigger on RC Compare"] #[inline(always)] - pub fn updown_rc(self) -> &'a mut W { + pub fn updown_rc(self) -> &'a mut crate::W { self.variant(WAVSELSELECT_A::UPDOWN_RC) } } #[doc = "Field `WAVE` reader - Waveform Mode"] pub type WAVE_R = crate::BitReader; #[doc = "Field `WAVE` writer - Waveform Mode"] -pub type WAVE_W<'a, const O: u8> = crate::BitWriter<'a, CMR_WAVEFORM_MODE_SPEC, O>; +pub type WAVE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACPA` reader - RA Compare Effect on TIOAx"] pub type ACPA_R = crate::FieldReader; #[doc = "RA Compare Effect on TIOAx\n\nValue on reset: 0"] @@ -552,49 +535,52 @@ impl ACPA_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == ACPASELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == ACPASELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == ACPASELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == ACPASELECT_A::TOGGLE } } #[doc = "Field `ACPA` writer - RA Compare Effect on TIOAx"] -pub type ACPA_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, ACPASELECT_A>; -impl<'a, const O: u8> ACPA_W<'a, O> { +pub type ACPA_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, ACPASELECT_A>; +impl<'a, REG, const O: u8> ACPA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(ACPASELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(ACPASELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(ACPASELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(ACPASELECT_A::TOGGLE) } } @@ -634,49 +620,52 @@ impl ACPC_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == ACPCSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == ACPCSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == ACPCSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == ACPCSELECT_A::TOGGLE } } #[doc = "Field `ACPC` writer - RC Compare Effect on TIOAx"] -pub type ACPC_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, ACPCSELECT_A>; -impl<'a, const O: u8> ACPC_W<'a, O> { +pub type ACPC_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, ACPCSELECT_A>; +impl<'a, REG, const O: u8> ACPC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(ACPCSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(ACPCSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(ACPCSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(ACPCSELECT_A::TOGGLE) } } @@ -716,49 +705,52 @@ impl AEEVT_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == AEEVTSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == AEEVTSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == AEEVTSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == AEEVTSELECT_A::TOGGLE } } #[doc = "Field `AEEVT` writer - External Event Effect on TIOAx"] -pub type AEEVT_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, AEEVTSELECT_A>; -impl<'a, const O: u8> AEEVT_W<'a, O> { +pub type AEEVT_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, AEEVTSELECT_A>; +impl<'a, REG, const O: u8> AEEVT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(AEEVTSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(AEEVTSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(AEEVTSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(AEEVTSELECT_A::TOGGLE) } } @@ -798,49 +790,52 @@ impl ASWTRG_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == ASWTRGSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == ASWTRGSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == ASWTRGSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == ASWTRGSELECT_A::TOGGLE } } #[doc = "Field `ASWTRG` writer - Software Trigger Effect on TIOAx"] -pub type ASWTRG_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, ASWTRGSELECT_A>; -impl<'a, const O: u8> ASWTRG_W<'a, O> { +pub type ASWTRG_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, ASWTRGSELECT_A>; +impl<'a, REG, const O: u8> ASWTRG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(ASWTRGSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(ASWTRGSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(ASWTRGSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(ASWTRGSELECT_A::TOGGLE) } } @@ -880,49 +875,52 @@ impl BCPB_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BCPBSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == BCPBSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == BCPBSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == BCPBSELECT_A::TOGGLE } } #[doc = "Field `BCPB` writer - RB Compare Effect on TIOBx"] -pub type BCPB_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, BCPBSELECT_A>; -impl<'a, const O: u8> BCPB_W<'a, O> { +pub type BCPB_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BCPBSELECT_A>; +impl<'a, REG, const O: u8> BCPB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BCPBSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(BCPBSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(BCPBSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(BCPBSELECT_A::TOGGLE) } } @@ -962,49 +960,52 @@ impl BCPC_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BCPCSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == BCPCSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == BCPCSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == BCPCSELECT_A::TOGGLE } } #[doc = "Field `BCPC` writer - RC Compare Effect on TIOBx"] -pub type BCPC_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, BCPCSELECT_A>; -impl<'a, const O: u8> BCPC_W<'a, O> { +pub type BCPC_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BCPCSELECT_A>; +impl<'a, REG, const O: u8> BCPC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BCPCSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(BCPCSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(BCPCSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(BCPCSELECT_A::TOGGLE) } } @@ -1044,49 +1045,52 @@ impl BEEVT_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BEEVTSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == BEEVTSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == BEEVTSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == BEEVTSELECT_A::TOGGLE } } #[doc = "Field `BEEVT` writer - External Event Effect on TIOBx"] -pub type BEEVT_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, BEEVTSELECT_A>; -impl<'a, const O: u8> BEEVT_W<'a, O> { +pub type BEEVT_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BEEVTSELECT_A>; +impl<'a, REG, const O: u8> BEEVT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BEEVTSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(BEEVTSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(BEEVTSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(BEEVTSELECT_A::TOGGLE) } } @@ -1126,49 +1130,52 @@ impl BSWTRG_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "NONE"] #[inline(always)] pub fn is_none(&self) -> bool { *self == BSWTRGSELECT_A::NONE } - #[doc = "Checks if the value of the field is `SET`"] + #[doc = "SET"] #[inline(always)] pub fn is_set(&self) -> bool { *self == BSWTRGSELECT_A::SET } - #[doc = "Checks if the value of the field is `CLEAR`"] + #[doc = "CLEAR"] #[inline(always)] pub fn is_clear(&self) -> bool { *self == BSWTRGSELECT_A::CLEAR } - #[doc = "Checks if the value of the field is `TOGGLE`"] + #[doc = "TOGGLE"] #[inline(always)] pub fn is_toggle(&self) -> bool { *self == BSWTRGSELECT_A::TOGGLE } } #[doc = "Field `BSWTRG` writer - Software Trigger Effect on TIOBx"] -pub type BSWTRG_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, CMR_WAVEFORM_MODE_SPEC, 2, O, BSWTRGSELECT_A>; -impl<'a, const O: u8> BSWTRG_W<'a, O> { +pub type BSWTRG_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, BSWTRGSELECT_A>; +impl<'a, REG, const O: u8> BSWTRG_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "NONE"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(BSWTRGSELECT_A::NONE) } #[doc = "SET"] #[inline(always)] - pub fn set(self) -> &'a mut W { + pub fn set(self) -> &'a mut crate::W { self.variant(BSWTRGSELECT_A::SET) } #[doc = "CLEAR"] #[inline(always)] - pub fn clear(self) -> &'a mut W { + pub fn clear(self) -> &'a mut crate::W { self.variant(BSWTRGSELECT_A::CLEAR) } #[doc = "TOGGLE"] #[inline(always)] - pub fn toggle(self) -> &'a mut W { + pub fn toggle(self) -> &'a mut crate::W { self.variant(BSWTRGSELECT_A::TOGGLE) } } @@ -1268,130 +1275,127 @@ impl W { #[doc = "Bits 0:2 - Clock Selection"] #[inline(always)] #[must_use] - pub fn tcclks(&mut self) -> TCCLKS_W<0> { + pub fn tcclks(&mut self) -> TCCLKS_W { TCCLKS_W::new(self) } #[doc = "Bit 3 - Clock Invert"] #[inline(always)] #[must_use] - pub fn clki(&mut self) -> CLKI_W<3> { + pub fn clki(&mut self) -> CLKI_W { CLKI_W::new(self) } #[doc = "Bits 4:5 - Burst Signal Selection"] #[inline(always)] #[must_use] - pub fn burst(&mut self) -> BURST_W<4> { + pub fn burst(&mut self) -> BURST_W { BURST_W::new(self) } #[doc = "Bit 6 - Counter Clock Stopped with RC Compare"] #[inline(always)] #[must_use] - pub fn cpcstop(&mut self) -> CPCSTOP_W<6> { + pub fn cpcstop(&mut self) -> CPCSTOP_W { CPCSTOP_W::new(self) } #[doc = "Bit 7 - Counter Clock Disable with RC Loading"] #[inline(always)] #[must_use] - pub fn cpcdis(&mut self) -> CPCDIS_W<7> { + pub fn cpcdis(&mut self) -> CPCDIS_W { CPCDIS_W::new(self) } #[doc = "Bits 8:9 - External Event Edge Selection"] #[inline(always)] #[must_use] - pub fn eevtedg(&mut self) -> EEVTEDG_W<8> { + pub fn eevtedg(&mut self) -> EEVTEDG_W { EEVTEDG_W::new(self) } #[doc = "Bits 10:11 - External Event Selection"] #[inline(always)] #[must_use] - pub fn eevt(&mut self) -> EEVT_W<10> { + pub fn eevt(&mut self) -> EEVT_W { EEVT_W::new(self) } #[doc = "Bit 12 - External Event Trigger Enable"] #[inline(always)] #[must_use] - pub fn enetrg(&mut self) -> ENETRG_W<12> { + pub fn enetrg(&mut self) -> ENETRG_W { ENETRG_W::new(self) } #[doc = "Bits 13:14 - Waveform Selection"] #[inline(always)] #[must_use] - pub fn wavsel(&mut self) -> WAVSEL_W<13> { + pub fn wavsel(&mut self) -> WAVSEL_W { WAVSEL_W::new(self) } #[doc = "Bit 15 - Waveform Mode"] #[inline(always)] #[must_use] - pub fn wave(&mut self) -> WAVE_W<15> { + pub fn wave(&mut self) -> WAVE_W { WAVE_W::new(self) } #[doc = "Bits 16:17 - RA Compare Effect on TIOAx"] #[inline(always)] #[must_use] - pub fn acpa(&mut self) -> ACPA_W<16> { + pub fn acpa(&mut self) -> ACPA_W { ACPA_W::new(self) } #[doc = "Bits 18:19 - RC Compare Effect on TIOAx"] #[inline(always)] #[must_use] - pub fn acpc(&mut self) -> ACPC_W<18> { + pub fn acpc(&mut self) -> ACPC_W { ACPC_W::new(self) } #[doc = "Bits 20:21 - External Event Effect on TIOAx"] #[inline(always)] #[must_use] - pub fn aeevt(&mut self) -> AEEVT_W<20> { + pub fn aeevt(&mut self) -> AEEVT_W { AEEVT_W::new(self) } #[doc = "Bits 22:23 - Software Trigger Effect on TIOAx"] #[inline(always)] #[must_use] - pub fn aswtrg(&mut self) -> ASWTRG_W<22> { + pub fn aswtrg(&mut self) -> ASWTRG_W { ASWTRG_W::new(self) } #[doc = "Bits 24:25 - RB Compare Effect on TIOBx"] #[inline(always)] #[must_use] - pub fn bcpb(&mut self) -> BCPB_W<24> { + pub fn bcpb(&mut self) -> BCPB_W { BCPB_W::new(self) } #[doc = "Bits 26:27 - RC Compare Effect on TIOBx"] #[inline(always)] #[must_use] - pub fn bcpc(&mut self) -> BCPC_W<26> { + pub fn bcpc(&mut self) -> BCPC_W { BCPC_W::new(self) } #[doc = "Bits 28:29 - External Event Effect on TIOBx"] #[inline(always)] #[must_use] - pub fn beevt(&mut self) -> BEEVT_W<28> { + pub fn beevt(&mut self) -> BEEVT_W { BEEVT_W::new(self) } #[doc = "Bits 30:31 - Software Trigger Effect on TIOBx"] #[inline(always)] #[must_use] - pub fn bswtrg(&mut self) -> BSWTRG_W<30> { + pub fn bswtrg(&mut self) -> BSWTRG_W { BSWTRG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Mode Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmr_waveform_mode](index.html) module"] +#[doc = "Channel Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmr_waveform_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmr_waveform_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMR_WAVEFORM_MODE_SPEC; impl crate::RegisterSpec for CMR_WAVEFORM_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmr_waveform_mode::R](R) reader structure"] -impl crate::Readable for CMR_WAVEFORM_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmr_waveform_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`cmr_waveform_mode::R`](R) reader structure"] +impl crate::Readable for CMR_WAVEFORM_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmr_waveform_mode::W`](W) writer structure"] impl crate::Writable for CMR_WAVEFORM_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cv.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cv.rs index 0361918e..60c4af69 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cv.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/cv.rs @@ -1,18 +1,5 @@ #[doc = "Register `CV` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `CV` reader - Counter Value"] pub type CV_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { CV_R::new(self.bits) } } -#[doc = "Counter Value (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cv](index.html) module"] +#[doc = "Counter Value (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cv::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CV_SPEC; impl crate::RegisterSpec for CV_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cv::R](R) reader structure"] -impl crate::Readable for CV_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cv::R`](R) reader structure"] +impl crate::Readable for CV_SPEC {} #[doc = "`reset()` method sets CV to value 0"] impl crate::Resettable for CV_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/emr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/emr.rs index d820892b..86d75e6d 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/emr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/emr.rs @@ -1,39 +1,7 @@ #[doc = "Register `EMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `EMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TRIGSRCA` reader - Trigger Source for Input A"] pub type TRIGSRCA_R = crate::FieldReader; #[doc = "Trigger Source for Input A\n\nValue on reset: 0"] @@ -64,28 +32,32 @@ impl TRIGSRCA_R { _ => None, } } - #[doc = "Checks if the value of the field is `EXTERNAL_TIOAX`"] + #[doc = "The trigger/capture input A is driven by external pin TIOAx"] #[inline(always)] pub fn is_external_tioax(&self) -> bool { *self == TRIGSRCASELECT_A::EXTERNAL_TIOAX } - #[doc = "Checks if the value of the field is `PWMX`"] + #[doc = "The trigger/capture input A is driven internally by PWMx"] #[inline(always)] pub fn is_pwmx(&self) -> bool { *self == TRIGSRCASELECT_A::PWMX } } #[doc = "Field `TRIGSRCA` writer - Trigger Source for Input A"] -pub type TRIGSRCA_W<'a, const O: u8> = crate::FieldWriter<'a, EMR_SPEC, 2, O, TRIGSRCASELECT_A>; -impl<'a, const O: u8> TRIGSRCA_W<'a, O> { +pub type TRIGSRCA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TRIGSRCASELECT_A>; +impl<'a, REG, const O: u8> TRIGSRCA_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The trigger/capture input A is driven by external pin TIOAx"] #[inline(always)] - pub fn external_tioax(self) -> &'a mut W { + pub fn external_tioax(self) -> &'a mut crate::W { self.variant(TRIGSRCASELECT_A::EXTERNAL_TIOAX) } #[doc = "The trigger/capture input A is driven internally by PWMx"] #[inline(always)] - pub fn pwmx(self) -> &'a mut W { + pub fn pwmx(self) -> &'a mut crate::W { self.variant(TRIGSRCASELECT_A::PWMX) } } @@ -119,35 +91,39 @@ impl TRIGSRCB_R { _ => None, } } - #[doc = "Checks if the value of the field is `EXTERNAL_TIOBX`"] + #[doc = "The trigger/capture input B is driven by external pin TIOBx"] #[inline(always)] pub fn is_external_tiobx(&self) -> bool { *self == TRIGSRCBSELECT_A::EXTERNAL_TIOBX } - #[doc = "Checks if the value of the field is `PWMX`"] + #[doc = "For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC)."] #[inline(always)] pub fn is_pwmx(&self) -> bool { *self == TRIGSRCBSELECT_A::PWMX } } #[doc = "Field `TRIGSRCB` writer - Trigger Source for Input B"] -pub type TRIGSRCB_W<'a, const O: u8> = crate::FieldWriter<'a, EMR_SPEC, 2, O, TRIGSRCBSELECT_A>; -impl<'a, const O: u8> TRIGSRCB_W<'a, O> { +pub type TRIGSRCB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, TRIGSRCBSELECT_A>; +impl<'a, REG, const O: u8> TRIGSRCB_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The trigger/capture input B is driven by external pin TIOBx"] #[inline(always)] - pub fn external_tiobx(self) -> &'a mut W { + pub fn external_tiobx(self) -> &'a mut crate::W { self.variant(TRIGSRCBSELECT_A::EXTERNAL_TIOBX) } #[doc = "For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC)."] #[inline(always)] - pub fn pwmx(self) -> &'a mut W { + pub fn pwmx(self) -> &'a mut crate::W { self.variant(TRIGSRCBSELECT_A::PWMX) } } #[doc = "Field `NODIVCLK` reader - No Divided Clock"] pub type NODIVCLK_R = crate::BitReader; #[doc = "Field `NODIVCLK` writer - No Divided Clock"] -pub type NODIVCLK_W<'a, const O: u8> = crate::BitWriter<'a, EMR_SPEC, O>; +pub type NODIVCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - Trigger Source for Input A"] #[inline(always)] @@ -169,40 +145,37 @@ impl W { #[doc = "Bits 0:1 - Trigger Source for Input A"] #[inline(always)] #[must_use] - pub fn trigsrca(&mut self) -> TRIGSRCA_W<0> { + pub fn trigsrca(&mut self) -> TRIGSRCA_W { TRIGSRCA_W::new(self) } #[doc = "Bits 4:5 - Trigger Source for Input B"] #[inline(always)] #[must_use] - pub fn trigsrcb(&mut self) -> TRIGSRCB_W<4> { + pub fn trigsrcb(&mut self) -> TRIGSRCB_W { TRIGSRCB_W::new(self) } #[doc = "Bit 8 - No Divided Clock"] #[inline(always)] #[must_use] - pub fn nodivclk(&mut self) -> NODIVCLK_W<8> { + pub fn nodivclk(&mut self) -> NODIVCLK_W { NODIVCLK_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Extended Mode Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [emr](index.html) module"] +#[doc = "Extended Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct EMR_SPEC; impl crate::RegisterSpec for EMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [emr::R](R) reader structure"] -impl crate::Readable for EMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [emr::W](W) writer structure"] +#[doc = "`read()` method returns [`emr::R`](R) reader structure"] +impl crate::Readable for EMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`emr::W`](W) writer structure"] impl crate::Writable for EMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/idr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/idr.rs index fc5dbb7a..2a465128 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/idr.rs @@ -1,104 +1,84 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `COVFS` writer - Counter Overflow"] -pub type COVFS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type COVFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOVRS` writer - Load Overrun"] -pub type LOVRS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type LOVRS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPAS` writer - RA Compare"] -pub type CPAS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CPAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPBS` writer - RB Compare"] -pub type CPBS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CPBS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPCS` writer - RC Compare"] -pub type CPCS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CPCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDRAS` writer - RA Loading"] -pub type LDRAS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type LDRAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDRBS` writer - RB Loading"] -pub type LDRBS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type LDRBS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETRGS` writer - External Trigger"] -pub type ETRGS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ETRGS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Counter Overflow"] #[inline(always)] #[must_use] - pub fn covfs(&mut self) -> COVFS_W<0> { + pub fn covfs(&mut self) -> COVFS_W { COVFS_W::new(self) } #[doc = "Bit 1 - Load Overrun"] #[inline(always)] #[must_use] - pub fn lovrs(&mut self) -> LOVRS_W<1> { + pub fn lovrs(&mut self) -> LOVRS_W { LOVRS_W::new(self) } #[doc = "Bit 2 - RA Compare"] #[inline(always)] #[must_use] - pub fn cpas(&mut self) -> CPAS_W<2> { + pub fn cpas(&mut self) -> CPAS_W { CPAS_W::new(self) } #[doc = "Bit 3 - RB Compare"] #[inline(always)] #[must_use] - pub fn cpbs(&mut self) -> CPBS_W<3> { + pub fn cpbs(&mut self) -> CPBS_W { CPBS_W::new(self) } #[doc = "Bit 4 - RC Compare"] #[inline(always)] #[must_use] - pub fn cpcs(&mut self) -> CPCS_W<4> { + pub fn cpcs(&mut self) -> CPCS_W { CPCS_W::new(self) } #[doc = "Bit 5 - RA Loading"] #[inline(always)] #[must_use] - pub fn ldras(&mut self) -> LDRAS_W<5> { + pub fn ldras(&mut self) -> LDRAS_W { LDRAS_W::new(self) } #[doc = "Bit 6 - RB Loading"] #[inline(always)] #[must_use] - pub fn ldrbs(&mut self) -> LDRBS_W<6> { + pub fn ldrbs(&mut self) -> LDRBS_W { LDRBS_W::new(self) } #[doc = "Bit 7 - External Trigger"] #[inline(always)] #[must_use] - pub fn etrgs(&mut self) -> ETRGS_W<7> { + pub fn etrgs(&mut self) -> ETRGS_W { ETRGS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register (channel = 0)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register (channel = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ier.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ier.rs index e09c4da9..e80950f5 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ier.rs @@ -1,104 +1,84 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `COVFS` writer - Counter Overflow"] -pub type COVFS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type COVFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOVRS` writer - Load Overrun"] -pub type LOVRS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type LOVRS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPAS` writer - RA Compare"] -pub type CPAS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CPAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPBS` writer - RB Compare"] -pub type CPBS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CPBS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPCS` writer - RC Compare"] -pub type CPCS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CPCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDRAS` writer - RA Loading"] -pub type LDRAS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type LDRAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDRBS` writer - RB Loading"] -pub type LDRBS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type LDRBS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ETRGS` writer - External Trigger"] -pub type ETRGS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ETRGS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Counter Overflow"] #[inline(always)] #[must_use] - pub fn covfs(&mut self) -> COVFS_W<0> { + pub fn covfs(&mut self) -> COVFS_W { COVFS_W::new(self) } #[doc = "Bit 1 - Load Overrun"] #[inline(always)] #[must_use] - pub fn lovrs(&mut self) -> LOVRS_W<1> { + pub fn lovrs(&mut self) -> LOVRS_W { LOVRS_W::new(self) } #[doc = "Bit 2 - RA Compare"] #[inline(always)] #[must_use] - pub fn cpas(&mut self) -> CPAS_W<2> { + pub fn cpas(&mut self) -> CPAS_W { CPAS_W::new(self) } #[doc = "Bit 3 - RB Compare"] #[inline(always)] #[must_use] - pub fn cpbs(&mut self) -> CPBS_W<3> { + pub fn cpbs(&mut self) -> CPBS_W { CPBS_W::new(self) } #[doc = "Bit 4 - RC Compare"] #[inline(always)] #[must_use] - pub fn cpcs(&mut self) -> CPCS_W<4> { + pub fn cpcs(&mut self) -> CPCS_W { CPCS_W::new(self) } #[doc = "Bit 5 - RA Loading"] #[inline(always)] #[must_use] - pub fn ldras(&mut self) -> LDRAS_W<5> { + pub fn ldras(&mut self) -> LDRAS_W { LDRAS_W::new(self) } #[doc = "Bit 6 - RB Loading"] #[inline(always)] #[must_use] - pub fn ldrbs(&mut self) -> LDRBS_W<6> { + pub fn ldrbs(&mut self) -> LDRBS_W { LDRBS_W::new(self) } #[doc = "Bit 7 - External Trigger"] #[inline(always)] #[must_use] - pub fn etrgs(&mut self) -> ETRGS_W<7> { + pub fn etrgs(&mut self) -> ETRGS_W { ETRGS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register (channel = 0)\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register (channel = 0)\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/imr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/imr.rs index 6b87abfb..7314736c 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `COVFS` reader - Counter Overflow"] pub type COVFS_R = crate::BitReader; #[doc = "Field `LOVRS` reader - Load Overrun"] @@ -71,15 +58,13 @@ impl R { ETRGS_R::new(((self.bits >> 7) & 1) != 0) } } -#[doc = "Interrupt Mask Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ra.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ra.rs index 57cbd5d1..9250b3c8 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ra.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/ra.rs @@ -1,43 +1,11 @@ #[doc = "Register `RA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RA` reader - Register A"] pub type RA_R = crate::FieldReader; #[doc = "Field `RA` writer - Register A"] -pub type RA_W<'a, const O: u8> = crate::FieldWriter<'a, RA_SPEC, 32, O, u32>; +pub type RA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Register A"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Register A"] #[inline(always)] #[must_use] - pub fn ra(&mut self) -> RA_W<0> { + pub fn ra(&mut self) -> RA_W { RA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Register A (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ra](index.html) module"] +#[doc = "Register A (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ra::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ra::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RA_SPEC; impl crate::RegisterSpec for RA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ra::R](R) reader structure"] -impl crate::Readable for RA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ra::W](W) writer structure"] +#[doc = "`read()` method returns [`ra::R`](R) reader structure"] +impl crate::Readable for RA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ra::W`](W) writer structure"] impl crate::Writable for RA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rab.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rab.rs index cda5a864..c057fa91 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rab.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rab.rs @@ -1,18 +1,5 @@ #[doc = "Register `RAB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RAB` reader - Register A or Register B"] pub type RAB_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RAB_R::new(self.bits) } } -#[doc = "Register AB (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rab](index.html) module"] +#[doc = "Register AB (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rab::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RAB_SPEC; impl crate::RegisterSpec for RAB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rab::R](R) reader structure"] -impl crate::Readable for RAB_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rab::R`](R) reader structure"] +impl crate::Readable for RAB_SPEC {} #[doc = "`reset()` method sets RAB to value 0"] impl crate::Resettable for RAB_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rb.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rb.rs index e9b01768..05b1afaf 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rb.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rb.rs @@ -1,43 +1,11 @@ #[doc = "Register `RB` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RB` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RB` reader - Register B"] pub type RB_R = crate::FieldReader; #[doc = "Field `RB` writer - Register B"] -pub type RB_W<'a, const O: u8> = crate::FieldWriter<'a, RB_SPEC, 32, O, u32>; +pub type RB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Register B"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Register B"] #[inline(always)] #[must_use] - pub fn rb(&mut self) -> RB_W<0> { + pub fn rb(&mut self) -> RB_W { RB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Register B (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rb](index.html) module"] +#[doc = "Register B (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RB_SPEC; impl crate::RegisterSpec for RB_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rb::R](R) reader structure"] -impl crate::Readable for RB_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rb::W](W) writer structure"] +#[doc = "`read()` method returns [`rb::R`](R) reader structure"] +impl crate::Readable for RB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rb::W`](W) writer structure"] impl crate::Writable for RB_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rc.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rc.rs index cd8f69f8..d89500b6 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rc.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/rc.rs @@ -1,43 +1,11 @@ #[doc = "Register `RC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `RC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RC` reader - Register C"] pub type RC_R = crate::FieldReader; #[doc = "Field `RC` writer - Register C"] -pub type RC_W<'a, const O: u8> = crate::FieldWriter<'a, RC_SPEC, 32, O, u32>; +pub type RC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Register C"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Register C"] #[inline(always)] #[must_use] - pub fn rc(&mut self) -> RC_W<0> { + pub fn rc(&mut self) -> RC_W { RC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Register C (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rc](index.html) module"] +#[doc = "Register C (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RC_SPEC; impl crate::RegisterSpec for RC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rc::R](R) reader structure"] -impl crate::Readable for RC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [rc::W](W) writer structure"] +#[doc = "`read()` method returns [`rc::R`](R) reader structure"] +impl crate::Readable for RC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rc::W`](W) writer structure"] impl crate::Writable for RC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/smmr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/smmr.rs index cb8a2c11..a27dc2bc 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/smmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/smmr.rs @@ -1,47 +1,15 @@ #[doc = "Register `SMMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SMMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `GCEN` reader - Gray Count Enable"] pub type GCEN_R = crate::BitReader; #[doc = "Field `GCEN` writer - Gray Count Enable"] -pub type GCEN_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O>; +pub type GCEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DOWN` reader - Down Count"] pub type DOWN_R = crate::BitReader; #[doc = "Field `DOWN` writer - Down Count"] -pub type DOWN_W<'a, const O: u8> = crate::BitWriter<'a, SMMR_SPEC, O>; +pub type DOWN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Gray Count Enable"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 0 - Gray Count Enable"] #[inline(always)] #[must_use] - pub fn gcen(&mut self) -> GCEN_W<0> { + pub fn gcen(&mut self) -> GCEN_W { GCEN_W::new(self) } #[doc = "Bit 1 - Down Count"] #[inline(always)] #[must_use] - pub fn down(&mut self) -> DOWN_W<1> { + pub fn down(&mut self) -> DOWN_W { DOWN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Stepper Motor Mode Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smmr](index.html) module"] +#[doc = "Stepper Motor Mode Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SMMR_SPEC; impl crate::RegisterSpec for SMMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [smmr::R](R) reader structure"] -impl crate::Readable for SMMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [smmr::W](W) writer structure"] +#[doc = "`read()` method returns [`smmr::R`](R) reader structure"] +impl crate::Readable for SMMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smmr::W`](W) writer structure"] impl crate::Writable for SMMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/sr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/sr.rs index ef6ebdca..c85a6418 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/tc_channel/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `COVFS` reader - Counter Overflow Status (cleared on read)"] pub type COVFS_R = crate::BitReader; #[doc = "Field `LOVRS` reader - Load Overrun Status (cleared on read)"] @@ -92,15 +79,13 @@ impl R { MTIOB_R::new(((self.bits >> 18) & 1) != 0) } } -#[doc = "Status Register (channel = 0)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register (channel = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/tc0/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/tc0/wpmr.rs index 29f2adac..81772480 100644 --- a/arch/cortex-m/samv71q21-pac/src/tc0/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/tc0/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/trng.rs b/arch/cortex-m/samv71q21-pac/src/trng.rs index 20cb6da4..f0aaf24d 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng.rs @@ -16,27 +16,33 @@ pub struct RegisterBlock { #[doc = "0x50 - Output Data Register"] pub odata: ODATA, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "ISR (r) register accessor: an alias for `Reg`"] +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`isr`] +module"] pub type ISR = crate::Reg; #[doc = "Interrupt Status Register"] pub mod isr; -#[doc = "ODATA (r) register accessor: an alias for `Reg`"] +#[doc = "ODATA (r) register accessor: Output Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odata::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`odata`] +module"] pub type ODATA = crate::Reg; #[doc = "Output Data Register"] pub mod odata; diff --git a/arch/cortex-m/samv71q21-pac/src/trng/cr.rs b/arch/cortex-m/samv71q21-pac/src/trng/cr.rs index 77932398..76ba9549 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng/cr.rs @@ -1,26 +1,7 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ENABLE` writer - Enables the TRNG to Provide Random Values"] -pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ENABLE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Security Key\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u32)] @@ -38,11 +19,15 @@ impl crate::FieldSpec for KEYSELECT_AW { type Ux = u32; } #[doc = "Field `KEY` writer - Security Key"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 24, O, KEYSELECT_AW>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, KEYSELECT_AW>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_AW::PASSWD) } } @@ -50,30 +35,29 @@ impl W { #[doc = "Bit 0 - Enables the TRNG to Provide Random Values"] #[inline(always)] #[must_use] - pub fn enable(&mut self) -> ENABLE_W<0> { + pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self) } #[doc = "Bits 8:31 - Security Key"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<8> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/trng/idr.rs b/arch/cortex-m/samv71q21-pac/src/trng/idr.rs index 408bead1..b061cd0f 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng/idr.rs @@ -1,48 +1,28 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATRDY` writer - Data Ready Interrupt Disable"] -pub type DATRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type DATRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Data Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn datrdy(&mut self) -> DATRDY_W<0> { + pub fn datrdy(&mut self) -> DATRDY_W { DATRDY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/trng/ier.rs b/arch/cortex-m/samv71q21-pac/src/trng/ier.rs index bc0e1375..cd2e292d 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng/ier.rs @@ -1,48 +1,28 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATRDY` writer - Data Ready Interrupt Enable"] -pub type DATRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type DATRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Data Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn datrdy(&mut self) -> DATRDY_W<0> { + pub fn datrdy(&mut self) -> DATRDY_W { DATRDY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/trng/imr.rs b/arch/cortex-m/samv71q21-pac/src/trng/imr.rs index a835dc0b..79cd2f7c 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATRDY` reader - Data Ready Interrupt Mask"] pub type DATRDY_R = crate::BitReader; impl R { @@ -22,15 +9,13 @@ impl R { DATRDY_R::new((self.bits & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/trng/isr.rs b/arch/cortex-m/samv71q21-pac/src/trng/isr.rs index e1a7328d..d09b757c 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng/isr.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng/isr.rs @@ -1,18 +1,5 @@ #[doc = "Register `ISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DATRDY` reader - Data Ready"] pub type DATRDY_R = crate::BitReader; impl R { @@ -22,15 +9,13 @@ impl R { DATRDY_R::new((self.bits & 1) != 0) } } -#[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isr](index.html) module"] +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ISR_SPEC; impl crate::RegisterSpec for ISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [isr::R](R) reader structure"] -impl crate::Readable for ISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for ISR_SPEC {} #[doc = "`reset()` method sets ISR to value 0"] impl crate::Resettable for ISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/trng/odata.rs b/arch/cortex-m/samv71q21-pac/src/trng/odata.rs index 6bc6252a..2d423e1c 100644 --- a/arch/cortex-m/samv71q21-pac/src/trng/odata.rs +++ b/arch/cortex-m/samv71q21-pac/src/trng/odata.rs @@ -1,18 +1,5 @@ #[doc = "Register `ODATA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ODATA` reader - Output Data"] pub type ODATA_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { ODATA_R::new(self.bits) } } -#[doc = "Output Data Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [odata](index.html) module"] +#[doc = "Output Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odata::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct ODATA_SPEC; impl crate::RegisterSpec for ODATA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [odata::R](R) reader structure"] -impl crate::Readable for ODATA_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`odata::R`](R) reader structure"] +impl crate::Readable for ODATA_SPEC {} #[doc = "`reset()` method sets ODATA to value 0"] impl crate::Resettable for ODATA_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0.rs b/arch/cortex-m/samv71q21-pac/src/twihs0.rs index 8eb6e474..b3cfddc9 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0.rs @@ -38,67 +38,83 @@ pub struct RegisterBlock { #[doc = "0xe8 - Write Protection Status Register"] pub wpsr: WPSR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MMR (rw) register accessor: an alias for `Reg`"] +#[doc = "MMR (rw) register accessor: Master Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mmr`] +module"] pub type MMR = crate::Reg; #[doc = "Master Mode Register"] pub mod mmr; -#[doc = "SMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SMR (rw) register accessor: Slave Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smr`] +module"] pub type SMR = crate::Reg; #[doc = "Slave Mode Register"] pub mod smr; -#[doc = "IADR (rw) register accessor: an alias for `Reg`"] +#[doc = "IADR (rw) register accessor: Internal Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iadr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iadr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`iadr`] +module"] pub type IADR = crate::Reg; #[doc = "Internal Address Register"] pub mod iadr; -#[doc = "CWGR (rw) register accessor: an alias for `Reg`"] +#[doc = "CWGR (rw) register accessor: Clock Waveform Generator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cwgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cwgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cwgr`] +module"] pub type CWGR = crate::Reg; #[doc = "Clock Waveform Generator Register"] pub mod cwgr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "RHR (r) register accessor: an alias for `Reg`"] +#[doc = "RHR (r) register accessor: Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rhr`] +module"] pub type RHR = crate::Reg; #[doc = "Receive Holding Register"] pub mod rhr; -#[doc = "THR (w) register accessor: an alias for `Reg`"] +#[doc = "THR (w) register accessor: Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "SMBTR (rw) register accessor: an alias for `Reg`"] +#[doc = "SMBTR (rw) register accessor: SMBus Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smbtr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smbtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`smbtr`] +module"] pub type SMBTR = crate::Reg; #[doc = "SMBus Timing Register"] pub mod smbtr; -#[doc = "FILTR (rw) register accessor: an alias for `Reg`"] +#[doc = "FILTR (rw) register accessor: Filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filtr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filtr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`filtr`] +module"] pub type FILTR = crate::Reg; #[doc = "Filter Register"] pub mod filtr; -#[doc = "SWMR (rw) register accessor: an alias for `Reg`"] +#[doc = "SWMR (rw) register accessor: SleepWalking Matching Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`swmr`] +module"] pub type SWMR = crate::Reg; #[doc = "SleepWalking Matching Register"] pub mod swmr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; -#[doc = "WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpsr`] +module"] pub type WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/cr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/cr.rs index ba118a30..58b4e3e8 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/cr.rs @@ -1,216 +1,196 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `START` writer - Send a START Condition"] -pub type START_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type START_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STOP` writer - Send a STOP Condition"] -pub type STOP_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type STOP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSEN` writer - TWIHS Master Mode Enabled"] -pub type MSEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type MSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSDIS` writer - TWIHS Master Mode Disabled"] -pub type MSDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type MSDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SVEN` writer - TWIHS Slave Mode Enabled"] -pub type SVEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SVEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SVDIS` writer - TWIHS Slave Mode Disabled"] -pub type SVDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SVDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `QUICK` writer - SMBus Quick Command"] -pub type QUICK_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type QUICK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWRST` writer - Software Reset"] -pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SWRST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSEN` writer - TWIHS High-Speed Mode Enabled"] -pub type HSEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type HSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSDIS` writer - TWIHS High-Speed Mode Disabled"] -pub type HSDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type HSDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMBEN` writer - SMBus Mode Enabled"] -pub type SMBEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SMBEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMBDIS` writer - SMBus Mode Disabled"] -pub type SMBDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type SMBDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PECEN` writer - Packet Error Checking Enable"] -pub type PECEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PECEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PECDIS` writer - Packet Error Checking Disable"] -pub type PECDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PECDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PECRQ` writer - PEC Request"] -pub type PECRQ_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type PECRQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLEAR` writer - Bus CLEAR Command"] -pub type CLEAR_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type CLEAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMEN` writer - Alternative Command Mode Enable"] -pub type ACMEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ACMEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ACMDIS` writer - Alternative Command Mode Disable"] -pub type ACMDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type ACMDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `THRCLR` writer - Transmit Holding Register Clear"] -pub type THRCLR_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type THRCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LOCKCLR` writer - Lock Clear"] -pub type LOCKCLR_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type LOCKCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOEN` writer - FIFO Enable"] -pub type FIFOEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type FIFOEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFODIS` writer - FIFO Disable"] -pub type FIFODIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type FIFODIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Send a START Condition"] #[inline(always)] #[must_use] - pub fn start(&mut self) -> START_W<0> { + pub fn start(&mut self) -> START_W { START_W::new(self) } #[doc = "Bit 1 - Send a STOP Condition"] #[inline(always)] #[must_use] - pub fn stop(&mut self) -> STOP_W<1> { + pub fn stop(&mut self) -> STOP_W { STOP_W::new(self) } #[doc = "Bit 2 - TWIHS Master Mode Enabled"] #[inline(always)] #[must_use] - pub fn msen(&mut self) -> MSEN_W<2> { + pub fn msen(&mut self) -> MSEN_W { MSEN_W::new(self) } #[doc = "Bit 3 - TWIHS Master Mode Disabled"] #[inline(always)] #[must_use] - pub fn msdis(&mut self) -> MSDIS_W<3> { + pub fn msdis(&mut self) -> MSDIS_W { MSDIS_W::new(self) } #[doc = "Bit 4 - TWIHS Slave Mode Enabled"] #[inline(always)] #[must_use] - pub fn sven(&mut self) -> SVEN_W<4> { + pub fn sven(&mut self) -> SVEN_W { SVEN_W::new(self) } #[doc = "Bit 5 - TWIHS Slave Mode Disabled"] #[inline(always)] #[must_use] - pub fn svdis(&mut self) -> SVDIS_W<5> { + pub fn svdis(&mut self) -> SVDIS_W { SVDIS_W::new(self) } #[doc = "Bit 6 - SMBus Quick Command"] #[inline(always)] #[must_use] - pub fn quick(&mut self) -> QUICK_W<6> { + pub fn quick(&mut self) -> QUICK_W { QUICK_W::new(self) } #[doc = "Bit 7 - Software Reset"] #[inline(always)] #[must_use] - pub fn swrst(&mut self) -> SWRST_W<7> { + pub fn swrst(&mut self) -> SWRST_W { SWRST_W::new(self) } #[doc = "Bit 8 - TWIHS High-Speed Mode Enabled"] #[inline(always)] #[must_use] - pub fn hsen(&mut self) -> HSEN_W<8> { + pub fn hsen(&mut self) -> HSEN_W { HSEN_W::new(self) } #[doc = "Bit 9 - TWIHS High-Speed Mode Disabled"] #[inline(always)] #[must_use] - pub fn hsdis(&mut self) -> HSDIS_W<9> { + pub fn hsdis(&mut self) -> HSDIS_W { HSDIS_W::new(self) } #[doc = "Bit 10 - SMBus Mode Enabled"] #[inline(always)] #[must_use] - pub fn smben(&mut self) -> SMBEN_W<10> { + pub fn smben(&mut self) -> SMBEN_W { SMBEN_W::new(self) } #[doc = "Bit 11 - SMBus Mode Disabled"] #[inline(always)] #[must_use] - pub fn smbdis(&mut self) -> SMBDIS_W<11> { + pub fn smbdis(&mut self) -> SMBDIS_W { SMBDIS_W::new(self) } #[doc = "Bit 12 - Packet Error Checking Enable"] #[inline(always)] #[must_use] - pub fn pecen(&mut self) -> PECEN_W<12> { + pub fn pecen(&mut self) -> PECEN_W { PECEN_W::new(self) } #[doc = "Bit 13 - Packet Error Checking Disable"] #[inline(always)] #[must_use] - pub fn pecdis(&mut self) -> PECDIS_W<13> { + pub fn pecdis(&mut self) -> PECDIS_W { PECDIS_W::new(self) } #[doc = "Bit 14 - PEC Request"] #[inline(always)] #[must_use] - pub fn pecrq(&mut self) -> PECRQ_W<14> { + pub fn pecrq(&mut self) -> PECRQ_W { PECRQ_W::new(self) } #[doc = "Bit 15 - Bus CLEAR Command"] #[inline(always)] #[must_use] - pub fn clear(&mut self) -> CLEAR_W<15> { + pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self) } #[doc = "Bit 16 - Alternative Command Mode Enable"] #[inline(always)] #[must_use] - pub fn acmen(&mut self) -> ACMEN_W<16> { + pub fn acmen(&mut self) -> ACMEN_W { ACMEN_W::new(self) } #[doc = "Bit 17 - Alternative Command Mode Disable"] #[inline(always)] #[must_use] - pub fn acmdis(&mut self) -> ACMDIS_W<17> { + pub fn acmdis(&mut self) -> ACMDIS_W { ACMDIS_W::new(self) } #[doc = "Bit 24 - Transmit Holding Register Clear"] #[inline(always)] #[must_use] - pub fn thrclr(&mut self) -> THRCLR_W<24> { + pub fn thrclr(&mut self) -> THRCLR_W { THRCLR_W::new(self) } #[doc = "Bit 26 - Lock Clear"] #[inline(always)] #[must_use] - pub fn lockclr(&mut self) -> LOCKCLR_W<26> { + pub fn lockclr(&mut self) -> LOCKCLR_W { LOCKCLR_W::new(self) } #[doc = "Bit 28 - FIFO Enable"] #[inline(always)] #[must_use] - pub fn fifoen(&mut self) -> FIFOEN_W<28> { + pub fn fifoen(&mut self) -> FIFOEN_W { FIFOEN_W::new(self) } #[doc = "Bit 29 - FIFO Disable"] #[inline(always)] #[must_use] - pub fn fifodis(&mut self) -> FIFODIS_W<29> { + pub fn fifodis(&mut self) -> FIFODIS_W { FIFODIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/cwgr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/cwgr.rs index e5ed7d05..0b78b6e7 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/cwgr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/cwgr.rs @@ -1,55 +1,23 @@ #[doc = "Register `CWGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CWGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CLDIV` reader - Clock Low Divider"] pub type CLDIV_R = crate::FieldReader; #[doc = "Field `CLDIV` writer - Clock Low Divider"] -pub type CLDIV_W<'a, const O: u8> = crate::FieldWriter<'a, CWGR_SPEC, 8, O>; +pub type CLDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CHDIV` reader - Clock High Divider"] pub type CHDIV_R = crate::FieldReader; #[doc = "Field `CHDIV` writer - Clock High Divider"] -pub type CHDIV_W<'a, const O: u8> = crate::FieldWriter<'a, CWGR_SPEC, 8, O>; +pub type CHDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CKDIV` reader - Clock Divider"] pub type CKDIV_R = crate::FieldReader; #[doc = "Field `CKDIV` writer - Clock Divider"] -pub type CKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, CWGR_SPEC, 3, O>; +pub type CKDIV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `HOLD` reader - TWD Hold Time Versus TWCK Falling"] pub type HOLD_R = crate::FieldReader; #[doc = "Field `HOLD` writer - TWD Hold Time Versus TWCK Falling"] -pub type HOLD_W<'a, const O: u8> = crate::FieldWriter<'a, CWGR_SPEC, 6, O>; +pub type HOLD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; impl R { #[doc = "Bits 0:7 - Clock Low Divider"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:7 - Clock Low Divider"] #[inline(always)] #[must_use] - pub fn cldiv(&mut self) -> CLDIV_W<0> { + pub fn cldiv(&mut self) -> CLDIV_W { CLDIV_W::new(self) } #[doc = "Bits 8:15 - Clock High Divider"] #[inline(always)] #[must_use] - pub fn chdiv(&mut self) -> CHDIV_W<8> { + pub fn chdiv(&mut self) -> CHDIV_W { CHDIV_W::new(self) } #[doc = "Bits 16:18 - Clock Divider"] #[inline(always)] #[must_use] - pub fn ckdiv(&mut self) -> CKDIV_W<16> { + pub fn ckdiv(&mut self) -> CKDIV_W { CKDIV_W::new(self) } #[doc = "Bits 24:29 - TWD Hold Time Versus TWCK Falling"] #[inline(always)] #[must_use] - pub fn hold(&mut self) -> HOLD_W<24> { + pub fn hold(&mut self) -> HOLD_W { HOLD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Clock Waveform Generator Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cwgr](index.html) module"] +#[doc = "Clock Waveform Generator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cwgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cwgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CWGR_SPEC; impl crate::RegisterSpec for CWGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cwgr::R](R) reader structure"] -impl crate::Readable for CWGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cwgr::W](W) writer structure"] +#[doc = "`read()` method returns [`cwgr::R`](R) reader structure"] +impl crate::Readable for CWGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cwgr::W`](W) writer structure"] impl crate::Writable for CWGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/filtr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/filtr.rs index 0d8ef419..675a58c2 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/filtr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/filtr.rs @@ -1,55 +1,23 @@ #[doc = "Register `FILTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `FILTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FILT` reader - RX Digital Filter"] pub type FILT_R = crate::BitReader; #[doc = "Field `FILT` writer - RX Digital Filter"] -pub type FILT_W<'a, const O: u8> = crate::BitWriter<'a, FILTR_SPEC, O>; +pub type FILT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PADFEN` reader - PAD Filter Enable"] pub type PADFEN_R = crate::BitReader; #[doc = "Field `PADFEN` writer - PAD Filter Enable"] -pub type PADFEN_W<'a, const O: u8> = crate::BitWriter<'a, FILTR_SPEC, O>; +pub type PADFEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PADFCFG` reader - PAD Filter Config"] pub type PADFCFG_R = crate::BitReader; #[doc = "Field `PADFCFG` writer - PAD Filter Config"] -pub type PADFCFG_W<'a, const O: u8> = crate::BitWriter<'a, FILTR_SPEC, O>; +pub type PADFCFG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `THRES` reader - Digital Filter Threshold"] pub type THRES_R = crate::FieldReader; #[doc = "Field `THRES` writer - Digital Filter Threshold"] -pub type THRES_W<'a, const O: u8> = crate::FieldWriter<'a, FILTR_SPEC, 3, O>; +pub type THRES_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bit 0 - RX Digital Filter"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - RX Digital Filter"] #[inline(always)] #[must_use] - pub fn filt(&mut self) -> FILT_W<0> { + pub fn filt(&mut self) -> FILT_W { FILT_W::new(self) } #[doc = "Bit 1 - PAD Filter Enable"] #[inline(always)] #[must_use] - pub fn padfen(&mut self) -> PADFEN_W<1> { + pub fn padfen(&mut self) -> PADFEN_W { PADFEN_W::new(self) } #[doc = "Bit 2 - PAD Filter Config"] #[inline(always)] #[must_use] - pub fn padfcfg(&mut self) -> PADFCFG_W<2> { + pub fn padfcfg(&mut self) -> PADFCFG_W { PADFCFG_W::new(self) } #[doc = "Bits 8:10 - Digital Filter Threshold"] #[inline(always)] #[must_use] - pub fn thres(&mut self) -> THRES_W<8> { + pub fn thres(&mut self) -> THRES_W { THRES_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Filter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [filtr](index.html) module"] +#[doc = "Filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filtr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct FILTR_SPEC; impl crate::RegisterSpec for FILTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [filtr::R](R) reader structure"] -impl crate::Readable for FILTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [filtr::W](W) writer structure"] +#[doc = "`read()` method returns [`filtr::R`](R) reader structure"] +impl crate::Readable for FILTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`filtr::W`](W) writer structure"] impl crate::Writable for FILTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/iadr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/iadr.rs index 41ac0ed5..d4b52946 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/iadr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/iadr.rs @@ -1,43 +1,11 @@ #[doc = "Register `IADR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `IADR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IADR` reader - Internal Address"] pub type IADR_R = crate::FieldReader; #[doc = "Field `IADR` writer - Internal Address"] -pub type IADR_W<'a, const O: u8> = crate::FieldWriter<'a, IADR_SPEC, 24, O, u32>; +pub type IADR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Internal Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Internal Address"] #[inline(always)] #[must_use] - pub fn iadr(&mut self) -> IADR_W<0> { + pub fn iadr(&mut self) -> IADR_W { IADR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Internal Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iadr](index.html) module"] +#[doc = "Internal Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iadr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iadr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IADR_SPEC; impl crate::RegisterSpec for IADR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [iadr::R](R) reader structure"] -impl crate::Readable for IADR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [iadr::W](W) writer structure"] +#[doc = "`read()` method returns [`iadr::R`](R) reader structure"] +impl crate::Readable for IADR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`iadr::W`](W) writer structure"] impl crate::Writable for IADR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/idr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/idr.rs index 87c01470..f1beb72f 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/idr.rs @@ -1,168 +1,148 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXCOMP` writer - Transmission Completed Interrupt Disable"] -pub type TXCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRDY` writer - Receive Holding Register Ready Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Transmit Holding Register Ready Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SVACC` writer - Slave Access Interrupt Disable"] -pub type SVACC_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SVACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GACC` writer - General Call Access Interrupt Disable"] -pub type GACC_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type GACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Disable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Underrun Error Interrupt Disable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NACK` writer - Not Acknowledge Interrupt Disable"] -pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type NACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARBLST` writer - Arbitration Lost Interrupt Disable"] -pub type ARBLST_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type ARBLST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCL_WS` writer - Clock Wait State Interrupt Disable"] -pub type SCL_WS_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SCL_WS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOSACC` writer - End Of Slave Access Interrupt Disable"] -pub type EOSACC_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type EOSACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MCACK` writer - Master Code Acknowledge Interrupt Disable"] -pub type MCACK_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type MCACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOUT` writer - Timeout Error Interrupt Disable"] -pub type TOUT_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PECERR` writer - PEC Error Interrupt Disable"] -pub type PECERR_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PECERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMBDAM` writer - SMBus Default Address Match Interrupt Disable"] -pub type SMBDAM_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SMBDAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMBHHM` writer - SMBus Host Header Address Match Interrupt Disable"] -pub type SMBHHM_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type SMBHHM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmission Completed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txcomp(&mut self) -> TXCOMP_W<0> { + pub fn txcomp(&mut self) -> TXCOMP_W { TXCOMP_W::new(self) } #[doc = "Bit 1 - Receive Holding Register Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<1> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<2> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 4 - Slave Access Interrupt Disable"] #[inline(always)] #[must_use] - pub fn svacc(&mut self) -> SVACC_W<4> { + pub fn svacc(&mut self) -> SVACC_W { SVACC_W::new(self) } #[doc = "Bit 5 - General Call Access Interrupt Disable"] #[inline(always)] #[must_use] - pub fn gacc(&mut self) -> GACC_W<5> { + pub fn gacc(&mut self) -> GACC_W { GACC_W::new(self) } #[doc = "Bit 6 - Overrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<6> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 7 - Underrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<7> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 8 - Not Acknowledge Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nack(&mut self) -> NACK_W<8> { + pub fn nack(&mut self) -> NACK_W { NACK_W::new(self) } #[doc = "Bit 9 - Arbitration Lost Interrupt Disable"] #[inline(always)] #[must_use] - pub fn arblst(&mut self) -> ARBLST_W<9> { + pub fn arblst(&mut self) -> ARBLST_W { ARBLST_W::new(self) } #[doc = "Bit 10 - Clock Wait State Interrupt Disable"] #[inline(always)] #[must_use] - pub fn scl_ws(&mut self) -> SCL_WS_W<10> { + pub fn scl_ws(&mut self) -> SCL_WS_W { SCL_WS_W::new(self) } #[doc = "Bit 11 - End Of Slave Access Interrupt Disable"] #[inline(always)] #[must_use] - pub fn eosacc(&mut self) -> EOSACC_W<11> { + pub fn eosacc(&mut self) -> EOSACC_W { EOSACC_W::new(self) } #[doc = "Bit 16 - Master Code Acknowledge Interrupt Disable"] #[inline(always)] #[must_use] - pub fn mcack(&mut self) -> MCACK_W<16> { + pub fn mcack(&mut self) -> MCACK_W { MCACK_W::new(self) } #[doc = "Bit 18 - Timeout Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn tout(&mut self) -> TOUT_W<18> { + pub fn tout(&mut self) -> TOUT_W { TOUT_W::new(self) } #[doc = "Bit 19 - PEC Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pecerr(&mut self) -> PECERR_W<19> { + pub fn pecerr(&mut self) -> PECERR_W { PECERR_W::new(self) } #[doc = "Bit 20 - SMBus Default Address Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn smbdam(&mut self) -> SMBDAM_W<20> { + pub fn smbdam(&mut self) -> SMBDAM_W { SMBDAM_W::new(self) } #[doc = "Bit 21 - SMBus Host Header Address Match Interrupt Disable"] #[inline(always)] #[must_use] - pub fn smbhhm(&mut self) -> SMBHHM_W<21> { + pub fn smbhhm(&mut self) -> SMBHHM_W { SMBHHM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/ier.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/ier.rs index fe57ad8f..d6ce4a15 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/ier.rs @@ -1,168 +1,148 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXCOMP` writer - Transmission Completed Interrupt Enable"] -pub type TXCOMP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXCOMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRDY` writer - Receive Holding Register Ready Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Transmit Holding Register Ready Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SVACC` writer - Slave Access Interrupt Enable"] -pub type SVACC_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SVACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `GACC` writer - General Call Access Interrupt Enable"] -pub type GACC_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type GACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Underrun Error Interrupt Enable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NACK` writer - Not Acknowledge Interrupt Enable"] -pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type NACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARBLST` writer - Arbitration Lost Interrupt Enable"] -pub type ARBLST_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type ARBLST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCL_WS` writer - Clock Wait State Interrupt Enable"] -pub type SCL_WS_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SCL_WS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOSACC` writer - End Of Slave Access Interrupt Enable"] -pub type EOSACC_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type EOSACC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MCACK` writer - Master Code Acknowledge Interrupt Enable"] -pub type MCACK_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type MCACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TOUT` writer - Timeout Error Interrupt Enable"] -pub type TOUT_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PECERR` writer - PEC Error Interrupt Enable"] -pub type PECERR_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PECERR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMBDAM` writer - SMBus Default Address Match Interrupt Enable"] -pub type SMBDAM_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SMBDAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMBHHM` writer - SMBus Host Header Address Match Interrupt Enable"] -pub type SMBHHM_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type SMBHHM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmission Completed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txcomp(&mut self) -> TXCOMP_W<0> { + pub fn txcomp(&mut self) -> TXCOMP_W { TXCOMP_W::new(self) } #[doc = "Bit 1 - Receive Holding Register Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<1> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 2 - Transmit Holding Register Ready Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<2> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 4 - Slave Access Interrupt Enable"] #[inline(always)] #[must_use] - pub fn svacc(&mut self) -> SVACC_W<4> { + pub fn svacc(&mut self) -> SVACC_W { SVACC_W::new(self) } #[doc = "Bit 5 - General Call Access Interrupt Enable"] #[inline(always)] #[must_use] - pub fn gacc(&mut self) -> GACC_W<5> { + pub fn gacc(&mut self) -> GACC_W { GACC_W::new(self) } #[doc = "Bit 6 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<6> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 7 - Underrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<7> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 8 - Not Acknowledge Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nack(&mut self) -> NACK_W<8> { + pub fn nack(&mut self) -> NACK_W { NACK_W::new(self) } #[doc = "Bit 9 - Arbitration Lost Interrupt Enable"] #[inline(always)] #[must_use] - pub fn arblst(&mut self) -> ARBLST_W<9> { + pub fn arblst(&mut self) -> ARBLST_W { ARBLST_W::new(self) } #[doc = "Bit 10 - Clock Wait State Interrupt Enable"] #[inline(always)] #[must_use] - pub fn scl_ws(&mut self) -> SCL_WS_W<10> { + pub fn scl_ws(&mut self) -> SCL_WS_W { SCL_WS_W::new(self) } #[doc = "Bit 11 - End Of Slave Access Interrupt Enable"] #[inline(always)] #[must_use] - pub fn eosacc(&mut self) -> EOSACC_W<11> { + pub fn eosacc(&mut self) -> EOSACC_W { EOSACC_W::new(self) } #[doc = "Bit 16 - Master Code Acknowledge Interrupt Enable"] #[inline(always)] #[must_use] - pub fn mcack(&mut self) -> MCACK_W<16> { + pub fn mcack(&mut self) -> MCACK_W { MCACK_W::new(self) } #[doc = "Bit 18 - Timeout Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn tout(&mut self) -> TOUT_W<18> { + pub fn tout(&mut self) -> TOUT_W { TOUT_W::new(self) } #[doc = "Bit 19 - PEC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pecerr(&mut self) -> PECERR_W<19> { + pub fn pecerr(&mut self) -> PECERR_W { PECERR_W::new(self) } #[doc = "Bit 20 - SMBus Default Address Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn smbdam(&mut self) -> SMBDAM_W<20> { + pub fn smbdam(&mut self) -> SMBDAM_W { SMBDAM_W::new(self) } #[doc = "Bit 21 - SMBus Host Header Address Match Interrupt Enable"] #[inline(always)] #[must_use] - pub fn smbhhm(&mut self) -> SMBHHM_W<21> { + pub fn smbhhm(&mut self) -> SMBHHM_W { SMBHHM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/imr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/imr.rs index 5dcd34c4..44dc4987 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXCOMP` reader - Transmission Completed Interrupt Mask"] pub type TXCOMP_R = crate::BitReader; #[doc = "Field `RXRDY` reader - Receive Holding Register Ready Interrupt Mask"] @@ -127,15 +114,13 @@ impl R { SMBHHM_R::new(((self.bits >> 21) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/mmr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/mmr.rs index e3d32d8c..4668bbd8 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/mmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/mmr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IADRSZ` reader - Internal Device Address Size"] pub type IADRSZ_R = crate::FieldReader; #[doc = "Internal Device Address Size\n\nValue on reset: 0"] @@ -70,59 +38,63 @@ impl IADRSZ_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NONE`"] + #[doc = "No internal device address"] #[inline(always)] pub fn is_none(&self) -> bool { *self == IADRSZSELECT_A::NONE } - #[doc = "Checks if the value of the field is `_1_BYTE`"] + #[doc = "One-byte internal device address"] #[inline(always)] pub fn is_1_byte(&self) -> bool { *self == IADRSZSELECT_A::_1_BYTE } - #[doc = "Checks if the value of the field is `_2_BYTE`"] + #[doc = "Two-byte internal device address"] #[inline(always)] pub fn is_2_byte(&self) -> bool { *self == IADRSZSELECT_A::_2_BYTE } - #[doc = "Checks if the value of the field is `_3_BYTE`"] + #[doc = "Three-byte internal device address"] #[inline(always)] pub fn is_3_byte(&self) -> bool { *self == IADRSZSELECT_A::_3_BYTE } } #[doc = "Field `IADRSZ` writer - Internal Device Address Size"] -pub type IADRSZ_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MMR_SPEC, 2, O, IADRSZSELECT_A>; -impl<'a, const O: u8> IADRSZ_W<'a, O> { +pub type IADRSZ_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, IADRSZSELECT_A>; +impl<'a, REG, const O: u8> IADRSZ_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "No internal device address"] #[inline(always)] - pub fn none(self) -> &'a mut W { + pub fn none(self) -> &'a mut crate::W { self.variant(IADRSZSELECT_A::NONE) } #[doc = "One-byte internal device address"] #[inline(always)] - pub fn _1_byte(self) -> &'a mut W { + pub fn _1_byte(self) -> &'a mut crate::W { self.variant(IADRSZSELECT_A::_1_BYTE) } #[doc = "Two-byte internal device address"] #[inline(always)] - pub fn _2_byte(self) -> &'a mut W { + pub fn _2_byte(self) -> &'a mut crate::W { self.variant(IADRSZSELECT_A::_2_BYTE) } #[doc = "Three-byte internal device address"] #[inline(always)] - pub fn _3_byte(self) -> &'a mut W { + pub fn _3_byte(self) -> &'a mut crate::W { self.variant(IADRSZSELECT_A::_3_BYTE) } } #[doc = "Field `MREAD` reader - Master Read Direction"] pub type MREAD_R = crate::BitReader; #[doc = "Field `MREAD` writer - Master Read Direction"] -pub type MREAD_W<'a, const O: u8> = crate::BitWriter<'a, MMR_SPEC, O>; +pub type MREAD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DADR` reader - Device Address"] pub type DADR_R = crate::FieldReader; #[doc = "Field `DADR` writer - Device Address"] -pub type DADR_W<'a, const O: u8> = crate::FieldWriter<'a, MMR_SPEC, 7, O>; +pub type DADR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 8:9 - Internal Device Address Size"] #[inline(always)] @@ -144,40 +116,37 @@ impl W { #[doc = "Bits 8:9 - Internal Device Address Size"] #[inline(always)] #[must_use] - pub fn iadrsz(&mut self) -> IADRSZ_W<8> { + pub fn iadrsz(&mut self) -> IADRSZ_W { IADRSZ_W::new(self) } #[doc = "Bit 12 - Master Read Direction"] #[inline(always)] #[must_use] - pub fn mread(&mut self) -> MREAD_W<12> { + pub fn mread(&mut self) -> MREAD_W { MREAD_W::new(self) } #[doc = "Bits 16:22 - Device Address"] #[inline(always)] #[must_use] - pub fn dadr(&mut self) -> DADR_W<16> { + pub fn dadr(&mut self) -> DADR_W { DADR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Master Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mmr](index.html) module"] +#[doc = "Master Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MMR_SPEC; impl crate::RegisterSpec for MMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mmr::R](R) reader structure"] -impl crate::Readable for MMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mmr::W](W) writer structure"] +#[doc = "`read()` method returns [`mmr::R`](R) reader structure"] +impl crate::Readable for MMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mmr::W`](W) writer structure"] impl crate::Writable for MMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/rhr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/rhr.rs index 022b632e..937d3b04 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/rhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/rhr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXDATA` reader - Master or Slave Receive Holding Data"] pub type RXDATA_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXDATA_R::new((self.bits & 0xff) as u8) } } -#[doc = "Receive Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rhr](index.html) module"] +#[doc = "Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RHR_SPEC; impl crate::RegisterSpec for RHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rhr::R](R) reader structure"] -impl crate::Readable for RHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rhr::R`](R) reader structure"] +impl crate::Readable for RHR_SPEC {} #[doc = "`reset()` method sets RHR to value 0"] impl crate::Resettable for RHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/smbtr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/smbtr.rs index db386552..3bcf747b 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/smbtr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/smbtr.rs @@ -1,55 +1,23 @@ #[doc = "Register `SMBTR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SMBTR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PRESC` reader - SMBus Clock Prescaler"] pub type PRESC_R = crate::FieldReader; #[doc = "Field `PRESC` writer - SMBus Clock Prescaler"] -pub type PRESC_W<'a, const O: u8> = crate::FieldWriter<'a, SMBTR_SPEC, 4, O>; +pub type PRESC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TLOWS` reader - Slave Clock Stretch Maximum Cycles"] pub type TLOWS_R = crate::FieldReader; #[doc = "Field `TLOWS` writer - Slave Clock Stretch Maximum Cycles"] -pub type TLOWS_W<'a, const O: u8> = crate::FieldWriter<'a, SMBTR_SPEC, 8, O>; +pub type TLOWS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `TLOWM` reader - Master Clock Stretch Maximum Cycles"] pub type TLOWM_R = crate::FieldReader; #[doc = "Field `TLOWM` writer - Master Clock Stretch Maximum Cycles"] -pub type TLOWM_W<'a, const O: u8> = crate::FieldWriter<'a, SMBTR_SPEC, 8, O>; +pub type TLOWM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `THMAX` reader - Clock High Maximum Cycles"] pub type THMAX_R = crate::FieldReader; #[doc = "Field `THMAX` writer - Clock High Maximum Cycles"] -pub type THMAX_W<'a, const O: u8> = crate::FieldWriter<'a, SMBTR_SPEC, 8, O>; +pub type THMAX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:3 - SMBus Clock Prescaler"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:3 - SMBus Clock Prescaler"] #[inline(always)] #[must_use] - pub fn presc(&mut self) -> PRESC_W<0> { + pub fn presc(&mut self) -> PRESC_W { PRESC_W::new(self) } #[doc = "Bits 8:15 - Slave Clock Stretch Maximum Cycles"] #[inline(always)] #[must_use] - pub fn tlows(&mut self) -> TLOWS_W<8> { + pub fn tlows(&mut self) -> TLOWS_W { TLOWS_W::new(self) } #[doc = "Bits 16:23 - Master Clock Stretch Maximum Cycles"] #[inline(always)] #[must_use] - pub fn tlowm(&mut self) -> TLOWM_W<16> { + pub fn tlowm(&mut self) -> TLOWM_W { TLOWM_W::new(self) } #[doc = "Bits 24:31 - Clock High Maximum Cycles"] #[inline(always)] #[must_use] - pub fn thmax(&mut self) -> THMAX_W<24> { + pub fn thmax(&mut self) -> THMAX_W { THMAX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SMBus Timing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smbtr](index.html) module"] +#[doc = "SMBus Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smbtr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smbtr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SMBTR_SPEC; impl crate::RegisterSpec for SMBTR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [smbtr::R](R) reader structure"] -impl crate::Readable for SMBTR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [smbtr::W](W) writer structure"] +#[doc = "`read()` method returns [`smbtr::R`](R) reader structure"] +impl crate::Readable for SMBTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smbtr::W`](W) writer structure"] impl crate::Writable for SMBTR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/smr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/smr.rs index 9cc6647a..ffc8d4ed 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/smr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/smr.rs @@ -1,79 +1,47 @@ #[doc = "Register `SMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NACKEN` reader - Slave Receiver Data Phase NACK enable"] pub type NACKEN_R = crate::BitReader; #[doc = "Field `NACKEN` writer - Slave Receiver Data Phase NACK enable"] -pub type NACKEN_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type NACKEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMDA` reader - SMBus Default Address"] pub type SMDA_R = crate::BitReader; #[doc = "Field `SMDA` writer - SMBus Default Address"] -pub type SMDA_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type SMDA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SMHH` reader - SMBus Host Header"] pub type SMHH_R = crate::BitReader; #[doc = "Field `SMHH` writer - SMBus Host Header"] -pub type SMHH_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type SMHH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SCLWSDIS` reader - Clock Wait State Disable"] pub type SCLWSDIS_R = crate::BitReader; #[doc = "Field `SCLWSDIS` writer - Clock Wait State Disable"] -pub type SCLWSDIS_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type SCLWSDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MASK` reader - Slave Address Mask"] pub type MASK_R = crate::FieldReader; #[doc = "Field `MASK` writer - Slave Address Mask"] -pub type MASK_W<'a, const O: u8> = crate::FieldWriter<'a, SMR_SPEC, 7, O>; +pub type MASK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SADR` reader - Slave Address"] pub type SADR_R = crate::FieldReader; #[doc = "Field `SADR` writer - Slave Address"] -pub type SADR_W<'a, const O: u8> = crate::FieldWriter<'a, SMR_SPEC, 7, O>; +pub type SADR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SADR1EN` reader - Slave Address 1 Enable"] pub type SADR1EN_R = crate::BitReader; #[doc = "Field `SADR1EN` writer - Slave Address 1 Enable"] -pub type SADR1EN_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type SADR1EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SADR2EN` reader - Slave Address 2 Enable"] pub type SADR2EN_R = crate::BitReader; #[doc = "Field `SADR2EN` writer - Slave Address 2 Enable"] -pub type SADR2EN_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type SADR2EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SADR3EN` reader - Slave Address 3 Enable"] pub type SADR3EN_R = crate::BitReader; #[doc = "Field `SADR3EN` writer - Slave Address 3 Enable"] -pub type SADR3EN_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type SADR3EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAMEN` reader - Data Matching Enable"] pub type DATAMEN_R = crate::BitReader; #[doc = "Field `DATAMEN` writer - Data Matching Enable"] -pub type DATAMEN_W<'a, const O: u8> = crate::BitWriter<'a, SMR_SPEC, O>; +pub type DATAMEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Slave Receiver Data Phase NACK enable"] #[inline(always)] @@ -130,82 +98,79 @@ impl W { #[doc = "Bit 0 - Slave Receiver Data Phase NACK enable"] #[inline(always)] #[must_use] - pub fn nacken(&mut self) -> NACKEN_W<0> { + pub fn nacken(&mut self) -> NACKEN_W { NACKEN_W::new(self) } #[doc = "Bit 2 - SMBus Default Address"] #[inline(always)] #[must_use] - pub fn smda(&mut self) -> SMDA_W<2> { + pub fn smda(&mut self) -> SMDA_W { SMDA_W::new(self) } #[doc = "Bit 3 - SMBus Host Header"] #[inline(always)] #[must_use] - pub fn smhh(&mut self) -> SMHH_W<3> { + pub fn smhh(&mut self) -> SMHH_W { SMHH_W::new(self) } #[doc = "Bit 6 - Clock Wait State Disable"] #[inline(always)] #[must_use] - pub fn sclwsdis(&mut self) -> SCLWSDIS_W<6> { + pub fn sclwsdis(&mut self) -> SCLWSDIS_W { SCLWSDIS_W::new(self) } #[doc = "Bits 8:14 - Slave Address Mask"] #[inline(always)] #[must_use] - pub fn mask(&mut self) -> MASK_W<8> { + pub fn mask(&mut self) -> MASK_W { MASK_W::new(self) } #[doc = "Bits 16:22 - Slave Address"] #[inline(always)] #[must_use] - pub fn sadr(&mut self) -> SADR_W<16> { + pub fn sadr(&mut self) -> SADR_W { SADR_W::new(self) } #[doc = "Bit 28 - Slave Address 1 Enable"] #[inline(always)] #[must_use] - pub fn sadr1en(&mut self) -> SADR1EN_W<28> { + pub fn sadr1en(&mut self) -> SADR1EN_W { SADR1EN_W::new(self) } #[doc = "Bit 29 - Slave Address 2 Enable"] #[inline(always)] #[must_use] - pub fn sadr2en(&mut self) -> SADR2EN_W<29> { + pub fn sadr2en(&mut self) -> SADR2EN_W { SADR2EN_W::new(self) } #[doc = "Bit 30 - Slave Address 3 Enable"] #[inline(always)] #[must_use] - pub fn sadr3en(&mut self) -> SADR3EN_W<30> { + pub fn sadr3en(&mut self) -> SADR3EN_W { SADR3EN_W::new(self) } #[doc = "Bit 31 - Data Matching Enable"] #[inline(always)] #[must_use] - pub fn datamen(&mut self) -> DATAMEN_W<31> { + pub fn datamen(&mut self) -> DATAMEN_W { DATAMEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Slave Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smr](index.html) module"] +#[doc = "Slave Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SMR_SPEC; impl crate::RegisterSpec for SMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [smr::R](R) reader structure"] -impl crate::Readable for SMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [smr::W](W) writer structure"] +#[doc = "`read()` method returns [`smr::R`](R) reader structure"] +impl crate::Readable for SMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`smr::W`](W) writer structure"] impl crate::Writable for SMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/sr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/sr.rs index 9e9fe907..faf50e71 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXCOMP` reader - Transmission Completed (cleared by writing TWIHS_THR)"] pub type TXCOMP_R = crate::BitReader; #[doc = "Field `RXRDY` reader - Receive Holding Register Ready (cleared by reading TWIHS_RHR)"] @@ -148,15 +135,13 @@ impl R { SDA_R::new(((self.bits >> 25) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/swmr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/swmr.rs index 62e99e1b..17678a7d 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/swmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/swmr.rs @@ -1,55 +1,23 @@ #[doc = "Register `SWMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `SWMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SADR1` reader - Slave Address 1"] pub type SADR1_R = crate::FieldReader; #[doc = "Field `SADR1` writer - Slave Address 1"] -pub type SADR1_W<'a, const O: u8> = crate::FieldWriter<'a, SWMR_SPEC, 7, O>; +pub type SADR1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SADR2` reader - Slave Address 2"] pub type SADR2_R = crate::FieldReader; #[doc = "Field `SADR2` writer - Slave Address 2"] -pub type SADR2_W<'a, const O: u8> = crate::FieldWriter<'a, SWMR_SPEC, 7, O>; +pub type SADR2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `SADR3` reader - Slave Address 3"] pub type SADR3_R = crate::FieldReader; #[doc = "Field `SADR3` writer - Slave Address 3"] -pub type SADR3_W<'a, const O: u8> = crate::FieldWriter<'a, SWMR_SPEC, 7, O>; +pub type SADR3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `DATAM` reader - Data Match"] pub type DATAM_R = crate::FieldReader; #[doc = "Field `DATAM` writer - Data Match"] -pub type DATAM_W<'a, const O: u8> = crate::FieldWriter<'a, SWMR_SPEC, 8, O>; +pub type DATAM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:6 - Slave Address 1"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - Slave Address 1"] #[inline(always)] #[must_use] - pub fn sadr1(&mut self) -> SADR1_W<0> { + pub fn sadr1(&mut self) -> SADR1_W { SADR1_W::new(self) } #[doc = "Bits 8:14 - Slave Address 2"] #[inline(always)] #[must_use] - pub fn sadr2(&mut self) -> SADR2_W<8> { + pub fn sadr2(&mut self) -> SADR2_W { SADR2_W::new(self) } #[doc = "Bits 16:22 - Slave Address 3"] #[inline(always)] #[must_use] - pub fn sadr3(&mut self) -> SADR3_W<16> { + pub fn sadr3(&mut self) -> SADR3_W { SADR3_W::new(self) } #[doc = "Bits 24:31 - Data Match"] #[inline(always)] #[must_use] - pub fn datam(&mut self) -> DATAM_W<24> { + pub fn datam(&mut self) -> DATAM_W { DATAM_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "SleepWalking Matching Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swmr](index.html) module"] +#[doc = "SleepWalking Matching Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`swmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SWMR_SPEC; impl crate::RegisterSpec for SWMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [swmr::R](R) reader structure"] -impl crate::Readable for SWMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [swmr::W](W) writer structure"] +#[doc = "`read()` method returns [`swmr::R`](R) reader structure"] +impl crate::Readable for SWMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swmr::W`](W) writer structure"] impl crate::Writable for SWMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/thr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/thr.rs index 2c7107f8..2e71be85 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/thr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/thr.rs @@ -1,48 +1,28 @@ #[doc = "Register `THR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXDATA` writer - Master or Slave Transmit Holding Data"] -pub type TXDATA_W<'a, const O: u8> = crate::FieldWriter<'a, THR_SPEC, 8, O>; +pub type TXDATA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl W { #[doc = "Bits 0:7 - Master or Slave Transmit Holding Data"] #[inline(always)] #[must_use] - pub fn txdata(&mut self) -> TXDATA_W<0> { + pub fn txdata(&mut self) -> TXDATA_W { TXDATA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Holding Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [thr](index.html) module"] +#[doc = "Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct THR_SPEC; impl crate::RegisterSpec for THR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [thr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`thr::W`](W) writer structure"] impl crate::Writable for THR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/wpmr.rs index eb5c545d..3d35c736 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0"] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0"] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/twihs0/wpsr.rs b/arch/cortex-m/samv71q21-pac/src/twihs0/wpsr.rs index f744ff35..e1f49a1c 100644 --- a/arch/cortex-m/samv71q21-pac/src/twihs0/wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/twihs0/wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new((self.bits >> 8) & 0x00ff_ffff) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPSR_SPEC; impl crate::RegisterSpec for WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpsr::R](R) reader structure"] -impl crate::Readable for WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`wpsr::R`](R) reader structure"] +impl crate::Readable for WPSR_SPEC {} #[doc = "`reset()` method sets WPSR to value 0"] impl crate::Resettable for WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/uart0.rs b/arch/cortex-m/samv71q21-pac/src/uart0.rs index 87391345..de2892eb 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0.rs @@ -25,47 +25,58 @@ pub struct RegisterBlock { #[doc = "0xe4 - Write Protection Mode Register"] pub wpmr: WPMR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "IER (w) register accessor: an alias for `Reg`"] +#[doc = "IER (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ier`] +module"] pub type IER = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod ier; -#[doc = "IDR (w) register accessor: an alias for `Reg`"] +#[doc = "IDR (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`idr`] +module"] pub type IDR = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod idr; -#[doc = "IMR (r) register accessor: an alias for `Reg`"] +#[doc = "IMR (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`imr`] +module"] pub type IMR = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod imr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; -#[doc = "RHR (r) register accessor: an alias for `Reg`"] +#[doc = "RHR (r) register accessor: Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`rhr`] +module"] pub type RHR = crate::Reg; #[doc = "Receive Holding Register"] pub mod rhr; -#[doc = "THR (w) register accessor: an alias for `Reg`"] +#[doc = "THR (w) register accessor: Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`thr`] +module"] pub type THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod thr; -#[doc = "BRGR (rw) register accessor: an alias for `Reg`"] +#[doc = "BRGR (rw) register accessor: Baud Rate Generator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`brgr`] +module"] pub type BRGR = crate::Reg; #[doc = "Baud Rate Generator Register"] pub mod brgr; -#[doc = "CMPR (rw) register accessor: an alias for `Reg`"] +#[doc = "CMPR (rw) register accessor: Comparison Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cmpr`] +module"] pub type CMPR = crate::Reg; #[doc = "Comparison Register"] pub mod cmpr; -#[doc = "WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`wpmr`] +module"] pub type WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod wpmr; diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/brgr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/brgr.rs index 5f2e5f31..7b1d291c 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/brgr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/brgr.rs @@ -1,43 +1,11 @@ #[doc = "Register `BRGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `BRGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CD` reader - Clock Divisor"] pub type CD_R = crate::FieldReader; #[doc = "Field `CD` writer - Clock Divisor"] -pub type CD_W<'a, const O: u8> = crate::FieldWriter<'a, BRGR_SPEC, 16, O, u16>; +pub type CD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Clock Divisor"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - Clock Divisor"] #[inline(always)] #[must_use] - pub fn cd(&mut self) -> CD_W<0> { + pub fn cd(&mut self) -> CD_W { CD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Baud Rate Generator Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [brgr](index.html) module"] +#[doc = "Baud Rate Generator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`brgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`brgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct BRGR_SPEC; impl crate::RegisterSpec for BRGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [brgr::R](R) reader structure"] -impl crate::Readable for BRGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [brgr::W](W) writer structure"] +#[doc = "`read()` method returns [`brgr::R`](R) reader structure"] +impl crate::Readable for BRGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`brgr::W`](W) writer structure"] impl crate::Writable for BRGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/cmpr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/cmpr.rs index 9b315dc1..d8381fa3 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/cmpr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/cmpr.rs @@ -1,43 +1,11 @@ #[doc = "Register `CMPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CMPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `VAL1` reader - First Comparison Value for Received Character"] pub type VAL1_R = crate::FieldReader; #[doc = "Field `VAL1` writer - First Comparison Value for Received Character"] -pub type VAL1_W<'a, const O: u8> = crate::FieldWriter<'a, CMPR_SPEC, 8, O>; +pub type VAL1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `CMPMODE` reader - Comparison Mode"] pub type CMPMODE_R = crate::BitReader; #[doc = "Comparison Mode\n\nValue on reset: 0"] @@ -63,39 +31,42 @@ impl CMPMODE_R { true => CMPMODESELECT_A::START_CONDITION, } } - #[doc = "Checks if the value of the field is `FLAG_ONLY`"] + #[doc = "Any character is received and comparison function drives CMP flag."] #[inline(always)] pub fn is_flag_only(&self) -> bool { *self == CMPMODESELECT_A::FLAG_ONLY } - #[doc = "Checks if the value of the field is `START_CONDITION`"] + #[doc = "Comparison condition must be met to start reception."] #[inline(always)] pub fn is_start_condition(&self) -> bool { *self == CMPMODESELECT_A::START_CONDITION } } #[doc = "Field `CMPMODE` writer - Comparison Mode"] -pub type CMPMODE_W<'a, const O: u8> = crate::BitWriter<'a, CMPR_SPEC, O, CMPMODESELECT_A>; -impl<'a, const O: u8> CMPMODE_W<'a, O> { +pub type CMPMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, CMPMODESELECT_A>; +impl<'a, REG, const O: u8> CMPMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Any character is received and comparison function drives CMP flag."] #[inline(always)] - pub fn flag_only(self) -> &'a mut W { + pub fn flag_only(self) -> &'a mut crate::W { self.variant(CMPMODESELECT_A::FLAG_ONLY) } #[doc = "Comparison condition must be met to start reception."] #[inline(always)] - pub fn start_condition(self) -> &'a mut W { + pub fn start_condition(self) -> &'a mut crate::W { self.variant(CMPMODESELECT_A::START_CONDITION) } } #[doc = "Field `CMPPAR` reader - Compare Parity"] pub type CMPPAR_R = crate::BitReader; #[doc = "Field `CMPPAR` writer - Compare Parity"] -pub type CMPPAR_W<'a, const O: u8> = crate::BitWriter<'a, CMPR_SPEC, O>; +pub type CMPPAR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VAL2` reader - Second Comparison Value for Received Character"] pub type VAL2_R = crate::FieldReader; #[doc = "Field `VAL2` writer - Second Comparison Value for Received Character"] -pub type VAL2_W<'a, const O: u8> = crate::FieldWriter<'a, CMPR_SPEC, 8, O>; +pub type VAL2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - First Comparison Value for Received Character"] #[inline(always)] @@ -122,46 +93,43 @@ impl W { #[doc = "Bits 0:7 - First Comparison Value for Received Character"] #[inline(always)] #[must_use] - pub fn val1(&mut self) -> VAL1_W<0> { + pub fn val1(&mut self) -> VAL1_W { VAL1_W::new(self) } #[doc = "Bit 12 - Comparison Mode"] #[inline(always)] #[must_use] - pub fn cmpmode(&mut self) -> CMPMODE_W<12> { + pub fn cmpmode(&mut self) -> CMPMODE_W { CMPMODE_W::new(self) } #[doc = "Bit 14 - Compare Parity"] #[inline(always)] #[must_use] - pub fn cmppar(&mut self) -> CMPPAR_W<14> { + pub fn cmppar(&mut self) -> CMPPAR_W { CMPPAR_W::new(self) } #[doc = "Bits 16:23 - Second Comparison Value for Received Character"] #[inline(always)] #[must_use] - pub fn val2(&mut self) -> VAL2_W<16> { + pub fn val2(&mut self) -> VAL2_W { VAL2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Comparison Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmpr](index.html) module"] +#[doc = "Comparison Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CMPR_SPEC; impl crate::RegisterSpec for CMPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cmpr::R](R) reader structure"] -impl crate::Readable for CMPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cmpr::W](W) writer structure"] +#[doc = "`read()` method returns [`cmpr::R`](R) reader structure"] +impl crate::Readable for CMPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cmpr::W`](W) writer structure"] impl crate::Writable for CMPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/cr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/cr.rs index 65638ada..df39b28f 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/cr.rs @@ -1,104 +1,84 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RSTRX` writer - Reset Receiver"] -pub type RSTRX_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RSTRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTTX` writer - Reset Transmitter"] -pub type RSTTX_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RSTTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXEN` writer - Receiver Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDIS` writer - Receiver Disable"] -pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` writer - Transmitter Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDIS` writer - Transmitter Disable"] -pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type TXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTSTA` writer - Reset Status"] -pub type RSTSTA_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type RSTSTA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `REQCLR` writer - Request Clear"] -pub type REQCLR_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type REQCLR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 2 - Reset Receiver"] #[inline(always)] #[must_use] - pub fn rstrx(&mut self) -> RSTRX_W<2> { + pub fn rstrx(&mut self) -> RSTRX_W { RSTRX_W::new(self) } #[doc = "Bit 3 - Reset Transmitter"] #[inline(always)] #[must_use] - pub fn rsttx(&mut self) -> RSTTX_W<3> { + pub fn rsttx(&mut self) -> RSTTX_W { RSTTX_W::new(self) } #[doc = "Bit 4 - Receiver Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<4> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 5 - Receiver Disable"] #[inline(always)] #[must_use] - pub fn rxdis(&mut self) -> RXDIS_W<5> { + pub fn rxdis(&mut self) -> RXDIS_W { RXDIS_W::new(self) } #[doc = "Bit 6 - Transmitter Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<6> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 7 - Transmitter Disable"] #[inline(always)] #[must_use] - pub fn txdis(&mut self) -> TXDIS_W<7> { + pub fn txdis(&mut self) -> TXDIS_W { TXDIS_W::new(self) } #[doc = "Bit 8 - Reset Status"] #[inline(always)] #[must_use] - pub fn rststa(&mut self) -> RSTSTA_W<8> { + pub fn rststa(&mut self) -> RSTSTA_W { RSTSTA_W::new(self) } #[doc = "Bit 12 - Request Clear"] #[inline(always)] #[must_use] - pub fn reqclr(&mut self) -> REQCLR_W<12> { + pub fn reqclr(&mut self) -> REQCLR_W { REQCLR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/idr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/idr.rs index a89fb44d..5668be4d 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/idr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/idr.rs @@ -1,96 +1,76 @@ #[doc = "Register `IDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - Disable RXRDY Interrupt"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Disable TXRDY Interrupt"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Disable Overrun Error Interrupt"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRAME` writer - Disable Framing Error Interrupt"] -pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PARE` writer - Disable Parity Error Interrupt"] -pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type PARE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Disable TXEMPTY Interrupt"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMP` writer - Disable Comparison Interrupt"] -pub type CMP_W<'a, const O: u8> = crate::BitWriter<'a, IDR_SPEC, O>; +pub type CMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Disable RXRDY Interrupt"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - Disable TXRDY Interrupt"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Disable Overrun Error Interrupt"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - Disable Framing Error Interrupt"] #[inline(always)] #[must_use] - pub fn frame(&mut self) -> FRAME_W<6> { + pub fn frame(&mut self) -> FRAME_W { FRAME_W::new(self) } #[doc = "Bit 7 - Disable Parity Error Interrupt"] #[inline(always)] #[must_use] - pub fn pare(&mut self) -> PARE_W<7> { + pub fn pare(&mut self) -> PARE_W { PARE_W::new(self) } #[doc = "Bit 9 - Disable TXEMPTY Interrupt"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 15 - Disable Comparison Interrupt"] #[inline(always)] #[must_use] - pub fn cmp(&mut self) -> CMP_W<15> { + pub fn cmp(&mut self) -> CMP_W { CMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [idr](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IDR_SPEC; impl crate::RegisterSpec for IDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [idr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`idr::W`](W) writer structure"] impl crate::Writable for IDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/ier.rs b/arch/cortex-m/samv71q21-pac/src/uart0/ier.rs index 023258ea..ac44f709 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/ier.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/ier.rs @@ -1,96 +1,76 @@ #[doc = "Register `IER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - Enable RXRDY Interrupt"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - Enable TXRDY Interrupt"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Enable Overrun Error Interrupt"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRAME` writer - Enable Framing Error Interrupt"] -pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PARE` writer - Enable Parity Error Interrupt"] -pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type PARE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - Enable TXEMPTY Interrupt"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CMP` writer - Enable Comparison Interrupt"] -pub type CMP_W<'a, const O: u8> = crate::BitWriter<'a, IER_SPEC, O>; +pub type CMP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Enable RXRDY Interrupt"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - Enable TXRDY Interrupt"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Enable Overrun Error Interrupt"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - Enable Framing Error Interrupt"] #[inline(always)] #[must_use] - pub fn frame(&mut self) -> FRAME_W<6> { + pub fn frame(&mut self) -> FRAME_W { FRAME_W::new(self) } #[doc = "Bit 7 - Enable Parity Error Interrupt"] #[inline(always)] #[must_use] - pub fn pare(&mut self) -> PARE_W<7> { + pub fn pare(&mut self) -> PARE_W { PARE_W::new(self) } #[doc = "Bit 9 - Enable TXEMPTY Interrupt"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 15 - Enable Comparison Interrupt"] #[inline(always)] #[must_use] - pub fn cmp(&mut self) -> CMP_W<15> { + pub fn cmp(&mut self) -> CMP_W { CMP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ier](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IER_SPEC; impl crate::RegisterSpec for IER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"] impl crate::Writable for IER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/imr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/imr.rs index a47c3f2d..4f32a284 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/imr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/imr.rs @@ -1,18 +1,5 @@ #[doc = "Register `IMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Mask RXRDY Interrupt"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - Disable TXRDY Interrupt"] @@ -64,15 +51,13 @@ impl R { CMP_R::new(((self.bits >> 15) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imr](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct IMR_SPEC; impl crate::RegisterSpec for IMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [imr::R](R) reader structure"] -impl crate::Readable for IMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for IMR_SPEC {} #[doc = "`reset()` method sets IMR to value 0"] impl crate::Resettable for IMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/mr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/mr.rs index b1bb771e..80387abf 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/mr.rs @@ -1,39 +1,7 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FILTER` reader - Receiver Digital Filter"] pub type FILTER_R = crate::BitReader; #[doc = "Receiver Digital Filter\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl FILTER_R { true => FILTERSELECT_A::ENABLED, } } - #[doc = "Checks if the value of the field is `DISABLED`"] + #[doc = "UART does not filter the receive line."] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == FILTERSELECT_A::DISABLED } - #[doc = "Checks if the value of the field is `ENABLED`"] + #[doc = "UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority)."] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == FILTERSELECT_A::ENABLED } } #[doc = "Field `FILTER` writer - Receiver Digital Filter"] -pub type FILTER_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, FILTERSELECT_A>; -impl<'a, const O: u8> FILTER_W<'a, O> { +pub type FILTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, FILTERSELECT_A>; +impl<'a, REG, const O: u8> FILTER_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "UART does not filter the receive line."] #[inline(always)] - pub fn disabled(self) -> &'a mut W { + pub fn disabled(self) -> &'a mut crate::W { self.variant(FILTERSELECT_A::DISABLED) } #[doc = "UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority)."] #[inline(always)] - pub fn enabled(self) -> &'a mut W { + pub fn enabled(self) -> &'a mut crate::W { self.variant(FILTERSELECT_A::ENABLED) } } @@ -123,58 +94,62 @@ impl PAR_R { _ => None, } } - #[doc = "Checks if the value of the field is `EVEN`"] + #[doc = "Even Parity"] #[inline(always)] pub fn is_even(&self) -> bool { *self == PARSELECT_A::EVEN } - #[doc = "Checks if the value of the field is `ODD`"] + #[doc = "Odd Parity"] #[inline(always)] pub fn is_odd(&self) -> bool { *self == PARSELECT_A::ODD } - #[doc = "Checks if the value of the field is `SPACE`"] + #[doc = "Space: parity forced to 0"] #[inline(always)] pub fn is_space(&self) -> bool { *self == PARSELECT_A::SPACE } - #[doc = "Checks if the value of the field is `MARK`"] + #[doc = "Mark: parity forced to 1"] #[inline(always)] pub fn is_mark(&self) -> bool { *self == PARSELECT_A::MARK } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No parity"] #[inline(always)] pub fn is_no(&self) -> bool { *self == PARSELECT_A::NO } } #[doc = "Field `PAR` writer - Parity Type"] -pub type PAR_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 3, O, PARSELECT_A>; -impl<'a, const O: u8> PAR_W<'a, O> { +pub type PAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, PARSELECT_A>; +impl<'a, REG, const O: u8> PAR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Even Parity"] #[inline(always)] - pub fn even(self) -> &'a mut W { + pub fn even(self) -> &'a mut crate::W { self.variant(PARSELECT_A::EVEN) } #[doc = "Odd Parity"] #[inline(always)] - pub fn odd(self) -> &'a mut W { + pub fn odd(self) -> &'a mut crate::W { self.variant(PARSELECT_A::ODD) } #[doc = "Space: parity forced to 0"] #[inline(always)] - pub fn space(self) -> &'a mut W { + pub fn space(self) -> &'a mut crate::W { self.variant(PARSELECT_A::SPACE) } #[doc = "Mark: parity forced to 1"] #[inline(always)] - pub fn mark(self) -> &'a mut W { + pub fn mark(self) -> &'a mut crate::W { self.variant(PARSELECT_A::MARK) } #[doc = "No parity"] #[inline(always)] - pub fn no(self) -> &'a mut W { + pub fn no(self) -> &'a mut crate::W { self.variant(PARSELECT_A::NO) } } @@ -203,28 +178,31 @@ impl BRSRCCK_R { true => BRSRCCKSELECT_A::PMC_PCK, } } - #[doc = "Checks if the value of the field is `PERIPH_CLK`"] + #[doc = "The baud rate is driven by the peripheral clock"] #[inline(always)] pub fn is_periph_clk(&self) -> bool { *self == BRSRCCKSELECT_A::PERIPH_CLK } - #[doc = "Checks if the value of the field is `PMC_PCK`"] + #[doc = "The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC))."] #[inline(always)] pub fn is_pmc_pck(&self) -> bool { *self == BRSRCCKSELECT_A::PMC_PCK } } #[doc = "Field `BRSRCCK` writer - Baud Rate Source Clock"] -pub type BRSRCCK_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O, BRSRCCKSELECT_A>; -impl<'a, const O: u8> BRSRCCK_W<'a, O> { +pub type BRSRCCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, BRSRCCKSELECT_A>; +impl<'a, REG, const O: u8> BRSRCCK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The baud rate is driven by the peripheral clock"] #[inline(always)] - pub fn periph_clk(self) -> &'a mut W { + pub fn periph_clk(self) -> &'a mut crate::W { self.variant(BRSRCCKSELECT_A::PERIPH_CLK) } #[doc = "The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC))."] #[inline(always)] - pub fn pmc_pck(self) -> &'a mut W { + pub fn pmc_pck(self) -> &'a mut crate::W { self.variant(BRSRCCKSELECT_A::PMC_PCK) } } @@ -264,48 +242,52 @@ impl CHMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "Normal mode"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == CHMODESELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `AUTOMATIC`"] + #[doc = "Automatic echo"] #[inline(always)] pub fn is_automatic(&self) -> bool { *self == CHMODESELECT_A::AUTOMATIC } - #[doc = "Checks if the value of the field is `LOCAL_LOOPBACK`"] + #[doc = "Local loopback"] #[inline(always)] pub fn is_local_loopback(&self) -> bool { *self == CHMODESELECT_A::LOCAL_LOOPBACK } - #[doc = "Checks if the value of the field is `REMOTE_LOOPBACK`"] + #[doc = "Remote loopback"] #[inline(always)] pub fn is_remote_loopback(&self) -> bool { *self == CHMODESELECT_A::REMOTE_LOOPBACK } } #[doc = "Field `CHMODE` writer - Channel Mode"] -pub type CHMODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, MR_SPEC, 2, O, CHMODESELECT_A>; -impl<'a, const O: u8> CHMODE_W<'a, O> { +pub type CHMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CHMODESELECT_A>; +impl<'a, REG, const O: u8> CHMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Normal mode"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::NORMAL) } #[doc = "Automatic echo"] #[inline(always)] - pub fn automatic(self) -> &'a mut W { + pub fn automatic(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::AUTOMATIC) } #[doc = "Local loopback"] #[inline(always)] - pub fn local_loopback(self) -> &'a mut W { + pub fn local_loopback(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::LOCAL_LOOPBACK) } #[doc = "Remote loopback"] #[inline(always)] - pub fn remote_loopback(self) -> &'a mut W { + pub fn remote_loopback(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::REMOTE_LOOPBACK) } } @@ -335,46 +317,43 @@ impl W { #[doc = "Bit 4 - Receiver Digital Filter"] #[inline(always)] #[must_use] - pub fn filter(&mut self) -> FILTER_W<4> { + pub fn filter(&mut self) -> FILTER_W { FILTER_W::new(self) } #[doc = "Bits 9:11 - Parity Type"] #[inline(always)] #[must_use] - pub fn par(&mut self) -> PAR_W<9> { + pub fn par(&mut self) -> PAR_W { PAR_W::new(self) } #[doc = "Bit 12 - Baud Rate Source Clock"] #[inline(always)] #[must_use] - pub fn brsrcck(&mut self) -> BRSRCCK_W<12> { + pub fn brsrcck(&mut self) -> BRSRCCK_W { BRSRCCK_W::new(self) } #[doc = "Bits 14:15 - Channel Mode"] #[inline(always)] #[must_use] - pub fn chmode(&mut self) -> CHMODE_W<14> { + pub fn chmode(&mut self) -> CHMODE_W { CHMODE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/rhr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/rhr.rs index f77aab59..8198a63a 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/rhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/rhr.rs @@ -1,18 +1,5 @@ #[doc = "Register `RHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXCHR` reader - Received Character"] pub type RXCHR_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { RXCHR_R::new((self.bits & 0xff) as u8) } } -#[doc = "Receive Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rhr](index.html) module"] +#[doc = "Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rhr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct RHR_SPEC; impl crate::RegisterSpec for RHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [rhr::R](R) reader structure"] -impl crate::Readable for RHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`rhr::R`](R) reader structure"] +impl crate::Readable for RHR_SPEC {} #[doc = "`reset()` method sets RHR to value 0"] impl crate::Resettable for RHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/sr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/sr.rs index cf1efff9..2bd14e0c 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Receiver Ready"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - Transmitter Ready"] @@ -64,15 +51,13 @@ impl R { CMP_R::new(((self.bits >> 15) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/thr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/thr.rs index 51f1c0a9..6fcedc02 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/thr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/thr.rs @@ -1,48 +1,28 @@ #[doc = "Register `THR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXCHR` writer - Character to be Transmitted"] -pub type TXCHR_W<'a, const O: u8> = crate::FieldWriter<'a, THR_SPEC, 8, O>; +pub type TXCHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl W { #[doc = "Bits 0:7 - Character to be Transmitted"] #[inline(always)] #[must_use] - pub fn txchr(&mut self) -> TXCHR_W<0> { + pub fn txchr(&mut self) -> TXCHR_W { TXCHR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Holding Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [thr](index.html) module"] +#[doc = "Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct THR_SPEC; impl crate::RegisterSpec for THR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [thr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`thr::W`](W) writer structure"] impl crate::Writable for THR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/uart0/wpmr.rs b/arch/cortex-m/samv71q21-pac/src/uart0/wpmr.rs index 6996fcf1..8dc26db3 100644 --- a/arch/cortex-m/samv71q21-pac/src/uart0/wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/uart0/wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation.Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct WPMR_SPEC; impl crate::RegisterSpec for WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [wpmr::R](R) reader structure"] -impl crate::Readable for WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`wpmr::R`](R) reader structure"] +impl crate::Readable for WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wpmr::W`](W) writer structure"] impl crate::Writable for WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0.rs b/arch/cortex-m/samv71q21-pac/src/usart0.rs index 273fdcd5..e3d19056 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0.rs @@ -186,195 +186,243 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(64usize).cast() } } } -#[doc = "US_CR_USART_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_CR_USART_MODE (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_cr_usart_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_cr_usart_mode`] +module"] pub type US_CR_USART_MODE = crate::Reg; #[doc = "Control Register"] pub mod us_cr_usart_mode; -#[doc = "US_CR_SPI_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_CR_SPI_MODE (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_cr_spi_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_cr_spi_mode`] +module"] pub type US_CR_SPI_MODE = crate::Reg; #[doc = "Control Register"] pub mod us_cr_spi_mode; -#[doc = "US_CR_LIN_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_CR_LIN_MODE (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_cr_lin_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_cr_lin_mode`] +module"] pub type US_CR_LIN_MODE = crate::Reg; #[doc = "Control Register"] pub mod us_cr_lin_mode; -#[doc = "US_MR_USART_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "US_MR_USART_MODE (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_mr_usart_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_mr_usart_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_mr_usart_mode`] +module"] pub type US_MR_USART_MODE = crate::Reg; #[doc = "Mode Register"] pub mod us_mr_usart_mode; -#[doc = "US_MR_SPI_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "US_MR_SPI_MODE (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_mr_spi_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_mr_spi_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_mr_spi_mode`] +module"] pub type US_MR_SPI_MODE = crate::Reg; #[doc = "Mode Register"] pub mod us_mr_spi_mode; -#[doc = "US_IER_USART_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IER_USART_MODE (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_usart_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ier_usart_mode`] +module"] pub type US_IER_USART_MODE = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod us_ier_usart_mode; -#[doc = "US_IER_SPI_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IER_SPI_MODE (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_spi_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ier_spi_mode`] +module"] pub type US_IER_SPI_MODE = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod us_ier_spi_mode; -#[doc = "US_IER_LIN_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IER_LIN_MODE (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_lin_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ier_lin_mode`] +module"] pub type US_IER_LIN_MODE = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod us_ier_lin_mode; -#[doc = "US_IER_LON_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IER_LON_MODE (w) register accessor: Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_lon_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ier_lon_mode`] +module"] pub type US_IER_LON_MODE = crate::Reg; #[doc = "Interrupt Enable Register"] pub mod us_ier_lon_mode; -#[doc = "US_IDR_USART_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IDR_USART_MODE (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_usart_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_idr_usart_mode`] +module"] pub type US_IDR_USART_MODE = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod us_idr_usart_mode; -#[doc = "US_IDR_SPI_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IDR_SPI_MODE (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_spi_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_idr_spi_mode`] +module"] pub type US_IDR_SPI_MODE = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod us_idr_spi_mode; -#[doc = "US_IDR_LIN_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IDR_LIN_MODE (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_lin_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_idr_lin_mode`] +module"] pub type US_IDR_LIN_MODE = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod us_idr_lin_mode; -#[doc = "US_IDR_LON_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "US_IDR_LON_MODE (w) register accessor: Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_lon_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_idr_lon_mode`] +module"] pub type US_IDR_LON_MODE = crate::Reg; #[doc = "Interrupt Disable Register"] pub mod us_idr_lon_mode; -#[doc = "US_IMR_USART_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_IMR_USART_MODE (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_usart_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_imr_usart_mode`] +module"] pub type US_IMR_USART_MODE = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod us_imr_usart_mode; -#[doc = "US_IMR_SPI_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_IMR_SPI_MODE (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_spi_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_imr_spi_mode`] +module"] pub type US_IMR_SPI_MODE = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod us_imr_spi_mode; -#[doc = "US_IMR_LIN_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_IMR_LIN_MODE (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_lin_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_imr_lin_mode`] +module"] pub type US_IMR_LIN_MODE = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod us_imr_lin_mode; -#[doc = "US_IMR_LON_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_IMR_LON_MODE (r) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_lon_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_imr_lon_mode`] +module"] pub type US_IMR_LON_MODE = crate::Reg; #[doc = "Interrupt Mask Register"] pub mod us_imr_lon_mode; -#[doc = "US_CSR_USART_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_CSR_USART_MODE (r) register accessor: Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_usart_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_csr_usart_mode`] +module"] pub type US_CSR_USART_MODE = crate::Reg; #[doc = "Channel Status Register"] pub mod us_csr_usart_mode; -#[doc = "US_CSR_SPI_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_CSR_SPI_MODE (r) register accessor: Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_spi_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_csr_spi_mode`] +module"] pub type US_CSR_SPI_MODE = crate::Reg; #[doc = "Channel Status Register"] pub mod us_csr_spi_mode; -#[doc = "US_CSR_LIN_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_CSR_LIN_MODE (r) register accessor: Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_lin_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_csr_lin_mode`] +module"] pub type US_CSR_LIN_MODE = crate::Reg; #[doc = "Channel Status Register"] pub mod us_csr_lin_mode; -#[doc = "US_CSR_LON_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "US_CSR_LON_MODE (r) register accessor: Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_lon_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_csr_lon_mode`] +module"] pub type US_CSR_LON_MODE = crate::Reg; #[doc = "Channel Status Register"] pub mod us_csr_lon_mode; -#[doc = "US_RHR (r) register accessor: an alias for `Reg`"] +#[doc = "US_RHR (r) register accessor: Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_rhr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_rhr`] +module"] pub type US_RHR = crate::Reg; #[doc = "Receive Holding Register"] pub mod us_rhr; -#[doc = "US_THR (w) register accessor: an alias for `Reg`"] +#[doc = "US_THR (w) register accessor: Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_thr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_thr`] +module"] pub type US_THR = crate::Reg; #[doc = "Transmit Holding Register"] pub mod us_thr; -#[doc = "US_BRGR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_BRGR (rw) register accessor: Baud Rate Generator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_brgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_brgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_brgr`] +module"] pub type US_BRGR = crate::Reg; #[doc = "Baud Rate Generator Register"] pub mod us_brgr; -#[doc = "US_RTOR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_RTOR (rw) register accessor: Receiver Timeout Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_rtor::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_rtor::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_rtor`] +module"] pub type US_RTOR = crate::Reg; #[doc = "Receiver Timeout Register"] pub mod us_rtor; -#[doc = "US_TTGR_USART_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "US_TTGR_USART_MODE (rw) register accessor: Transmitter Timeguard Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_ttgr_usart_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ttgr_usart_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ttgr_usart_mode`] +module"] pub type US_TTGR_USART_MODE = crate::Reg; #[doc = "Transmitter Timeguard Register"] pub mod us_ttgr_usart_mode; -#[doc = "US_TTGR_LON_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "US_TTGR_LON_MODE (rw) register accessor: Transmitter Timeguard Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_ttgr_lon_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ttgr_lon_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ttgr_lon_mode`] +module"] pub type US_TTGR_LON_MODE = crate::Reg; #[doc = "Transmitter Timeguard Register"] pub mod us_ttgr_lon_mode; -#[doc = "US_FIDI_USART_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "US_FIDI_USART_MODE (rw) register accessor: FI DI Ratio Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_fidi_usart_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_fidi_usart_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_fidi_usart_mode`] +module"] pub type US_FIDI_USART_MODE = crate::Reg; #[doc = "FI DI Ratio Register"] pub mod us_fidi_usart_mode; -#[doc = "US_FIDI_LON_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "US_FIDI_LON_MODE (rw) register accessor: FI DI Ratio Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_fidi_lon_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_fidi_lon_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_fidi_lon_mode`] +module"] pub type US_FIDI_LON_MODE = crate::Reg; #[doc = "FI DI Ratio Register"] pub mod us_fidi_lon_mode; -#[doc = "US_NER (r) register accessor: an alias for `Reg`"] +#[doc = "US_NER (r) register accessor: Number of Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_ner::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_ner`] +module"] pub type US_NER = crate::Reg; #[doc = "Number of Errors Register"] pub mod us_ner; -#[doc = "US_IF (rw) register accessor: an alias for `Reg`"] +#[doc = "US_IF (rw) register accessor: IrDA Filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_if::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_if::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_if`] +module"] pub type US_IF = crate::Reg; #[doc = "IrDA Filter Register"] pub mod us_if; -#[doc = "US_MAN (rw) register accessor: an alias for `Reg`"] +#[doc = "US_MAN (rw) register accessor: Manchester Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_man::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_man::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_man`] +module"] pub type US_MAN = crate::Reg; #[doc = "Manchester Configuration Register"] pub mod us_man; -#[doc = "US_LINMR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LINMR (rw) register accessor: LIN Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_linmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_linmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_linmr`] +module"] pub type US_LINMR = crate::Reg; #[doc = "LIN Mode Register"] pub mod us_linmr; -#[doc = "US_LINIR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LINIR (rw) register accessor: LIN Identifier Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_linir::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_linir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_linir`] +module"] pub type US_LINIR = crate::Reg; #[doc = "LIN Identifier Register"] pub mod us_linir; -#[doc = "US_LINBRR (r) register accessor: an alias for `Reg`"] +#[doc = "US_LINBRR (r) register accessor: LIN Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_linbrr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_linbrr`] +module"] pub type US_LINBRR = crate::Reg; #[doc = "LIN Baud Rate Register"] pub mod us_linbrr; -#[doc = "US_LONMR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONMR (rw) register accessor: LON Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonmr`] +module"] pub type US_LONMR = crate::Reg; #[doc = "LON Mode Register"] pub mod us_lonmr; -#[doc = "US_LONPR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONPR (rw) register accessor: LON Preamble Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonpr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonpr`] +module"] pub type US_LONPR = crate::Reg; #[doc = "LON Preamble Register"] pub mod us_lonpr; -#[doc = "US_LONDL (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONDL (rw) register accessor: LON Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_londl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_londl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_londl`] +module"] pub type US_LONDL = crate::Reg; #[doc = "LON Data Length Register"] pub mod us_londl; -#[doc = "US_LONL2HDR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONL2HDR (rw) register accessor: LON L2HDR Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonl2hdr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonl2hdr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonl2hdr`] +module"] pub type US_LONL2HDR = crate::Reg; #[doc = "LON L2HDR Register"] pub mod us_lonl2hdr; -#[doc = "US_LONBL (r) register accessor: an alias for `Reg`"] +#[doc = "US_LONBL (r) register accessor: LON Backlog Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonbl::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonbl`] +module"] pub type US_LONBL = crate::Reg; #[doc = "LON Backlog Register"] pub mod us_lonbl; -#[doc = "US_LONB1TX (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONB1TX (rw) register accessor: LON Beta1 Tx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonb1tx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonb1tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonb1tx`] +module"] pub type US_LONB1TX = crate::Reg; #[doc = "LON Beta1 Tx Register"] pub mod us_lonb1tx; -#[doc = "US_LONB1RX (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONB1RX (rw) register accessor: LON Beta1 Rx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonb1rx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonb1rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonb1rx`] +module"] pub type US_LONB1RX = crate::Reg; #[doc = "LON Beta1 Rx Register"] pub mod us_lonb1rx; -#[doc = "US_LONPRIO (rw) register accessor: an alias for `Reg`"] +#[doc = "US_LONPRIO (rw) register accessor: LON Priority Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonprio::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonprio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_lonprio`] +module"] pub type US_LONPRIO = crate::Reg; #[doc = "LON Priority Register"] pub mod us_lonprio; -#[doc = "US_IDTTX (rw) register accessor: an alias for `Reg`"] +#[doc = "US_IDTTX (rw) register accessor: LON IDT Tx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_idttx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idttx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_idttx`] +module"] pub type US_IDTTX = crate::Reg; #[doc = "LON IDT Tx Register"] pub mod us_idttx; -#[doc = "US_IDTRX (rw) register accessor: an alias for `Reg`"] +#[doc = "US_IDTRX (rw) register accessor: LON IDT Rx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_idtrx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idtrx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_idtrx`] +module"] pub type US_IDTRX = crate::Reg; #[doc = "LON IDT Rx Register"] pub mod us_idtrx; -#[doc = "US_ICDIFF (rw) register accessor: an alias for `Reg`"] +#[doc = "US_ICDIFF (rw) register accessor: IC DIFF Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_icdiff::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_icdiff::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_icdiff`] +module"] pub type US_ICDIFF = crate::Reg; #[doc = "IC DIFF Register"] pub mod us_icdiff; -#[doc = "US_WPMR (rw) register accessor: an alias for `Reg`"] +#[doc = "US_WPMR (rw) register accessor: Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_wpmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_wpmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_wpmr`] +module"] pub type US_WPMR = crate::Reg; #[doc = "Write Protection Mode Register"] pub mod us_wpmr; -#[doc = "US_WPSR (r) register accessor: an alias for `Reg`"] +#[doc = "US_WPSR (r) register accessor: Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_wpsr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`us_wpsr`] +module"] pub type US_WPSR = crate::Reg; #[doc = "Write Protection Status Register"] pub mod us_wpsr; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_brgr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_brgr.rs index c9a1759f..80902db9 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_brgr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_brgr.rs @@ -1,47 +1,15 @@ #[doc = "Register `US_BRGR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_BRGR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CD` reader - Clock Divider"] pub type CD_R = crate::FieldReader; #[doc = "Field `CD` writer - Clock Divider"] -pub type CD_W<'a, const O: u8> = crate::FieldWriter<'a, US_BRGR_SPEC, 16, O, u16>; +pub type CD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `FP` reader - Fractional Part"] pub type FP_R = crate::FieldReader; #[doc = "Field `FP` writer - Fractional Part"] -pub type FP_W<'a, const O: u8> = crate::FieldWriter<'a, US_BRGR_SPEC, 3, O>; +pub type FP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; impl R { #[doc = "Bits 0:15 - Clock Divider"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Clock Divider"] #[inline(always)] #[must_use] - pub fn cd(&mut self) -> CD_W<0> { + pub fn cd(&mut self) -> CD_W { CD_W::new(self) } #[doc = "Bits 16:18 - Fractional Part"] #[inline(always)] #[must_use] - pub fn fp(&mut self) -> FP_W<16> { + pub fn fp(&mut self) -> FP_W { FP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Baud Rate Generator Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_brgr](index.html) module"] +#[doc = "Baud Rate Generator Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_brgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_brgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_BRGR_SPEC; impl crate::RegisterSpec for US_BRGR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_brgr::R](R) reader structure"] -impl crate::Readable for US_BRGR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_brgr::W](W) writer structure"] +#[doc = "`read()` method returns [`us_brgr::R`](R) reader structure"] +impl crate::Readable for US_BRGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_brgr::W`](W) writer structure"] impl crate::Writable for US_BRGR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_lin_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_lin_mode.rs index 4183b520..6096d66f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_lin_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_lin_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `US_CR_LIN_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RSTRX` writer - Reset Receiver"] -pub type RSTRX_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type RSTRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTTX` writer - Reset Transmitter"] -pub type RSTTX_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type RSTTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXEN` writer - Receiver Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDIS` writer - Receiver Disable"] -pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type RXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` writer - Transmitter Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDIS` writer - Transmitter Disable"] -pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type TXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTSTA` writer - Reset Status Bits"] -pub type RSTSTA_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type RSTSTA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINABT` writer - Abort LIN Transmission"] -pub type LINABT_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type LINABT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINWKUP` writer - Send LIN Wakeup Signal"] -pub type LINWKUP_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_LIN_MODE_SPEC, O>; +pub type LINWKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 2 - Reset Receiver"] #[inline(always)] #[must_use] - pub fn rstrx(&mut self) -> RSTRX_W<2> { + pub fn rstrx(&mut self) -> RSTRX_W { RSTRX_W::new(self) } #[doc = "Bit 3 - Reset Transmitter"] #[inline(always)] #[must_use] - pub fn rsttx(&mut self) -> RSTTX_W<3> { + pub fn rsttx(&mut self) -> RSTTX_W { RSTTX_W::new(self) } #[doc = "Bit 4 - Receiver Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<4> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 5 - Receiver Disable"] #[inline(always)] #[must_use] - pub fn rxdis(&mut self) -> RXDIS_W<5> { + pub fn rxdis(&mut self) -> RXDIS_W { RXDIS_W::new(self) } #[doc = "Bit 6 - Transmitter Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<6> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 7 - Transmitter Disable"] #[inline(always)] #[must_use] - pub fn txdis(&mut self) -> TXDIS_W<7> { + pub fn txdis(&mut self) -> TXDIS_W { TXDIS_W::new(self) } #[doc = "Bit 8 - Reset Status Bits"] #[inline(always)] #[must_use] - pub fn rststa(&mut self) -> RSTSTA_W<8> { + pub fn rststa(&mut self) -> RSTSTA_W { RSTSTA_W::new(self) } #[doc = "Bit 20 - Abort LIN Transmission"] #[inline(always)] #[must_use] - pub fn linabt(&mut self) -> LINABT_W<20> { + pub fn linabt(&mut self) -> LINABT_W { LINABT_W::new(self) } #[doc = "Bit 21 - Send LIN Wakeup Signal"] #[inline(always)] #[must_use] - pub fn linwkup(&mut self) -> LINWKUP_W<21> { + pub fn linwkup(&mut self) -> LINWKUP_W { LINWKUP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_cr_lin_mode](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_cr_lin_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CR_LIN_MODE_SPEC; impl crate::RegisterSpec for US_CR_LIN_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_cr_lin_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_cr_lin_mode::W`](W) writer structure"] impl crate::Writable for US_CR_LIN_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_spi_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_spi_mode.rs index c3dbf9a5..5a6bf67b 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_spi_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_spi_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `US_CR_SPI_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RSTRX` writer - Reset Receiver"] -pub type RSTRX_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type RSTRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTTX` writer - Reset Transmitter"] -pub type RSTTX_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type RSTTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXEN` writer - Receiver Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDIS` writer - Receiver Disable"] -pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type RXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` writer - Transmitter Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDIS` writer - Transmitter Disable"] -pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type TXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTSTA` writer - Reset Status Bits"] -pub type RSTSTA_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type RSTSTA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FCS` writer - Force SPI Chip Select"] -pub type FCS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type FCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RCS` writer - Release SPI Chip Select"] -pub type RCS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_SPI_MODE_SPEC, O>; +pub type RCS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 2 - Reset Receiver"] #[inline(always)] #[must_use] - pub fn rstrx(&mut self) -> RSTRX_W<2> { + pub fn rstrx(&mut self) -> RSTRX_W { RSTRX_W::new(self) } #[doc = "Bit 3 - Reset Transmitter"] #[inline(always)] #[must_use] - pub fn rsttx(&mut self) -> RSTTX_W<3> { + pub fn rsttx(&mut self) -> RSTTX_W { RSTTX_W::new(self) } #[doc = "Bit 4 - Receiver Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<4> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 5 - Receiver Disable"] #[inline(always)] #[must_use] - pub fn rxdis(&mut self) -> RXDIS_W<5> { + pub fn rxdis(&mut self) -> RXDIS_W { RXDIS_W::new(self) } #[doc = "Bit 6 - Transmitter Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<6> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 7 - Transmitter Disable"] #[inline(always)] #[must_use] - pub fn txdis(&mut self) -> TXDIS_W<7> { + pub fn txdis(&mut self) -> TXDIS_W { TXDIS_W::new(self) } #[doc = "Bit 8 - Reset Status Bits"] #[inline(always)] #[must_use] - pub fn rststa(&mut self) -> RSTSTA_W<8> { + pub fn rststa(&mut self) -> RSTSTA_W { RSTSTA_W::new(self) } #[doc = "Bit 18 - Force SPI Chip Select"] #[inline(always)] #[must_use] - pub fn fcs(&mut self) -> FCS_W<18> { + pub fn fcs(&mut self) -> FCS_W { FCS_W::new(self) } #[doc = "Bit 19 - Release SPI Chip Select"] #[inline(always)] #[must_use] - pub fn rcs(&mut self) -> RCS_W<19> { + pub fn rcs(&mut self) -> RCS_W { RCS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_cr_spi_mode](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_cr_spi_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CR_SPI_MODE_SPEC; impl crate::RegisterSpec for US_CR_SPI_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_cr_spi_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_cr_spi_mode::W`](W) writer structure"] impl crate::Writable for US_CR_SPI_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_usart_mode.rs index 53cf4527..4984a4c4 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_cr_usart_mode.rs @@ -1,184 +1,164 @@ #[doc = "Register `US_CR_USART_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RSTRX` writer - Reset Receiver"] -pub type RSTRX_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RSTRX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTTX` writer - Reset Transmitter"] -pub type RSTTX_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RSTTX_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXEN` writer - Receiver Enable"] -pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXDIS` writer - Receiver Disable"] -pub type RXDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEN` writer - Transmitter Enable"] -pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type TXEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXDIS` writer - Transmitter Disable"] -pub type TXDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type TXDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTSTA` writer - Reset Status Bits"] -pub type RSTSTA_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RSTSTA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STTBRK` writer - Start Break"] -pub type STTBRK_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type STTBRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STPBRK` writer - Stop Break"] -pub type STPBRK_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type STPBRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STTTO` writer - Clear TIMEOUT Flag and Start Timeout After Next Character Received"] -pub type STTTO_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type STTTO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SENDA` writer - Send Address"] -pub type SENDA_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type SENDA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTIT` writer - Reset Iterations"] -pub type RSTIT_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RSTIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTNACK` writer - Reset Non Acknowledge"] -pub type RSTNACK_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RSTNACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RETTO` writer - Start Timeout Immediately"] -pub type RETTO_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RETTO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTREN` writer - Data Terminal Ready Enable"] -pub type DTREN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type DTREN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DTRDIS` writer - Data Terminal Ready Disable"] -pub type DTRDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type DTRDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTSEN` writer - Request to Send Enable"] -pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RTSEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RTSDIS` writer - Request to Send Disable"] -pub type RTSDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_CR_USART_MODE_SPEC, O>; +pub type RTSDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 2 - Reset Receiver"] #[inline(always)] #[must_use] - pub fn rstrx(&mut self) -> RSTRX_W<2> { + pub fn rstrx(&mut self) -> RSTRX_W { RSTRX_W::new(self) } #[doc = "Bit 3 - Reset Transmitter"] #[inline(always)] #[must_use] - pub fn rsttx(&mut self) -> RSTTX_W<3> { + pub fn rsttx(&mut self) -> RSTTX_W { RSTTX_W::new(self) } #[doc = "Bit 4 - Receiver Enable"] #[inline(always)] #[must_use] - pub fn rxen(&mut self) -> RXEN_W<4> { + pub fn rxen(&mut self) -> RXEN_W { RXEN_W::new(self) } #[doc = "Bit 5 - Receiver Disable"] #[inline(always)] #[must_use] - pub fn rxdis(&mut self) -> RXDIS_W<5> { + pub fn rxdis(&mut self) -> RXDIS_W { RXDIS_W::new(self) } #[doc = "Bit 6 - Transmitter Enable"] #[inline(always)] #[must_use] - pub fn txen(&mut self) -> TXEN_W<6> { + pub fn txen(&mut self) -> TXEN_W { TXEN_W::new(self) } #[doc = "Bit 7 - Transmitter Disable"] #[inline(always)] #[must_use] - pub fn txdis(&mut self) -> TXDIS_W<7> { + pub fn txdis(&mut self) -> TXDIS_W { TXDIS_W::new(self) } #[doc = "Bit 8 - Reset Status Bits"] #[inline(always)] #[must_use] - pub fn rststa(&mut self) -> RSTSTA_W<8> { + pub fn rststa(&mut self) -> RSTSTA_W { RSTSTA_W::new(self) } #[doc = "Bit 9 - Start Break"] #[inline(always)] #[must_use] - pub fn sttbrk(&mut self) -> STTBRK_W<9> { + pub fn sttbrk(&mut self) -> STTBRK_W { STTBRK_W::new(self) } #[doc = "Bit 10 - Stop Break"] #[inline(always)] #[must_use] - pub fn stpbrk(&mut self) -> STPBRK_W<10> { + pub fn stpbrk(&mut self) -> STPBRK_W { STPBRK_W::new(self) } #[doc = "Bit 11 - Clear TIMEOUT Flag and Start Timeout After Next Character Received"] #[inline(always)] #[must_use] - pub fn sttto(&mut self) -> STTTO_W<11> { + pub fn sttto(&mut self) -> STTTO_W { STTTO_W::new(self) } #[doc = "Bit 12 - Send Address"] #[inline(always)] #[must_use] - pub fn senda(&mut self) -> SENDA_W<12> { + pub fn senda(&mut self) -> SENDA_W { SENDA_W::new(self) } #[doc = "Bit 13 - Reset Iterations"] #[inline(always)] #[must_use] - pub fn rstit(&mut self) -> RSTIT_W<13> { + pub fn rstit(&mut self) -> RSTIT_W { RSTIT_W::new(self) } #[doc = "Bit 14 - Reset Non Acknowledge"] #[inline(always)] #[must_use] - pub fn rstnack(&mut self) -> RSTNACK_W<14> { + pub fn rstnack(&mut self) -> RSTNACK_W { RSTNACK_W::new(self) } #[doc = "Bit 15 - Start Timeout Immediately"] #[inline(always)] #[must_use] - pub fn retto(&mut self) -> RETTO_W<15> { + pub fn retto(&mut self) -> RETTO_W { RETTO_W::new(self) } #[doc = "Bit 16 - Data Terminal Ready Enable"] #[inline(always)] #[must_use] - pub fn dtren(&mut self) -> DTREN_W<16> { + pub fn dtren(&mut self) -> DTREN_W { DTREN_W::new(self) } #[doc = "Bit 17 - Data Terminal Ready Disable"] #[inline(always)] #[must_use] - pub fn dtrdis(&mut self) -> DTRDIS_W<17> { + pub fn dtrdis(&mut self) -> DTRDIS_W { DTRDIS_W::new(self) } #[doc = "Bit 18 - Request to Send Enable"] #[inline(always)] #[must_use] - pub fn rtsen(&mut self) -> RTSEN_W<18> { + pub fn rtsen(&mut self) -> RTSEN_W { RTSEN_W::new(self) } #[doc = "Bit 19 - Request to Send Disable"] #[inline(always)] #[must_use] - pub fn rtsdis(&mut self) -> RTSDIS_W<19> { + pub fn rtsdis(&mut self) -> RTSDIS_W { RTSDIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_cr_usart_mode](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_cr_usart_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CR_USART_MODE_SPEC; impl crate::RegisterSpec for US_CR_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_cr_usart_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_cr_usart_mode::W`](W) writer structure"] impl crate::Writable for US_CR_USART_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lin_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lin_mode.rs index 3c0f063d..190d4368 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lin_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lin_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_CSR_LIN_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Receiver Ready (cleared by reading US_RHR)"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - Transmitter Ready (cleared by writing US_THR)"] @@ -141,15 +128,13 @@ impl R { LINHTE_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_csr_lin_mode](index.html) module"] +#[doc = "Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_lin_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CSR_LIN_MODE_SPEC; impl crate::RegisterSpec for US_CSR_LIN_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_csr_lin_mode::R](R) reader structure"] -impl crate::Readable for US_CSR_LIN_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_csr_lin_mode::R`](R) reader structure"] +impl crate::Readable for US_CSR_LIN_MODE_SPEC {} #[doc = "`reset()` method sets US_CSR_LIN_MODE to value 0"] impl crate::Resettable for US_CSR_LIN_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lon_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lon_mode.rs index a2bb4786..400d3756 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lon_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_lon_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_CSR_LON_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Receiver Ready (cleared by reading US_RHR)"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - Transmitter Ready (cleared by writing US_THR)"] @@ -99,15 +86,13 @@ impl R { LBLOVFE_R::new(((self.bits >> 28) & 1) != 0) } } -#[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_csr_lon_mode](index.html) module"] +#[doc = "Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_lon_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CSR_LON_MODE_SPEC; impl crate::RegisterSpec for US_CSR_LON_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_csr_lon_mode::R](R) reader structure"] -impl crate::Readable for US_CSR_LON_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_csr_lon_mode::R`](R) reader structure"] +impl crate::Readable for US_CSR_LON_MODE_SPEC {} #[doc = "`reset()` method sets US_CSR_LON_MODE to value 0"] impl crate::Resettable for US_CSR_LON_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_spi_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_spi_mode.rs index e11c1372..0d29d3a4 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_spi_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_spi_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_CSR_SPI_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Receiver Ready (cleared by reading US_RHR)"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - Transmitter Ready (cleared by writing US_THR)"] @@ -64,15 +51,13 @@ impl R { NSS_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_csr_spi_mode](index.html) module"] +#[doc = "Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_spi_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CSR_SPI_MODE_SPEC; impl crate::RegisterSpec for US_CSR_SPI_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_csr_spi_mode::R](R) reader structure"] -impl crate::Readable for US_CSR_SPI_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_csr_spi_mode::R`](R) reader structure"] +impl crate::Readable for US_CSR_SPI_MODE_SPEC {} #[doc = "`reset()` method sets US_CSR_SPI_MODE to value 0"] impl crate::Resettable for US_CSR_SPI_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_usart_mode.rs index 61400372..a5b315fd 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_csr_usart_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_CSR_USART_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - Receiver Ready (cleared by reading US_RHR)"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - Transmitter Ready (cleared by writing US_THR)"] @@ -148,15 +135,13 @@ impl R { MANERR_R::new(((self.bits >> 24) & 1) != 0) } } -#[doc = "Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_csr_usart_mode](index.html) module"] +#[doc = "Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_csr_usart_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_CSR_USART_MODE_SPEC; impl crate::RegisterSpec for US_CSR_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_csr_usart_mode::R](R) reader structure"] -impl crate::Readable for US_CSR_USART_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_csr_usart_mode::R`](R) reader structure"] +impl crate::Readable for US_CSR_USART_MODE_SPEC {} #[doc = "`reset()` method sets US_CSR_USART_MODE to value 0"] impl crate::Resettable for US_CSR_USART_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_lon_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_lon_mode.rs index b111c080..ccea23a0 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_lon_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_lon_mode.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_FIDI_LON_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_FIDI_LON_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BETA2` reader - LON BETA2 Length"] pub type BETA2_R = crate::FieldReader; #[doc = "Field `BETA2` writer - LON BETA2 Length"] -pub type BETA2_W<'a, const O: u8> = crate::FieldWriter<'a, US_FIDI_LON_MODE_SPEC, 24, O, u32>; +pub type BETA2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - LON BETA2 Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - LON BETA2 Length"] #[inline(always)] #[must_use] - pub fn beta2(&mut self) -> BETA2_W<0> { + pub fn beta2(&mut self) -> BETA2_W { BETA2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FI DI Ratio Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_fidi_lon_mode](index.html) module"] +#[doc = "FI DI Ratio Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_fidi_lon_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_fidi_lon_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_FIDI_LON_MODE_SPEC; impl crate::RegisterSpec for US_FIDI_LON_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_fidi_lon_mode::R](R) reader structure"] -impl crate::Readable for US_FIDI_LON_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_fidi_lon_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`us_fidi_lon_mode::R`](R) reader structure"] +impl crate::Readable for US_FIDI_LON_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_fidi_lon_mode::W`](W) writer structure"] impl crate::Writable for US_FIDI_LON_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_usart_mode.rs index 3c9299e6..f55b8692 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_fidi_usart_mode.rs @@ -1,44 +1,11 @@ #[doc = "Register `US_FIDI_USART_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_FIDI_USART_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FI_DI_RATIO` reader - FI Over DI Ratio Value"] pub type FI_DI_RATIO_R = crate::FieldReader; #[doc = "Field `FI_DI_RATIO` writer - FI Over DI Ratio Value"] -pub type FI_DI_RATIO_W<'a, const O: u8> = - crate::FieldWriter<'a, US_FIDI_USART_MODE_SPEC, 16, O, u16>; +pub type FI_DI_RATIO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - FI Over DI Ratio Value"] #[inline(always)] @@ -50,28 +17,25 @@ impl W { #[doc = "Bits 0:15 - FI Over DI Ratio Value"] #[inline(always)] #[must_use] - pub fn fi_di_ratio(&mut self) -> FI_DI_RATIO_W<0> { + pub fn fi_di_ratio(&mut self) -> FI_DI_RATIO_W { FI_DI_RATIO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "FI DI Ratio Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_fidi_usart_mode](index.html) module"] +#[doc = "FI DI Ratio Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_fidi_usart_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_fidi_usart_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_FIDI_USART_MODE_SPEC; impl crate::RegisterSpec for US_FIDI_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_fidi_usart_mode::R](R) reader structure"] -impl crate::Readable for US_FIDI_USART_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_fidi_usart_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`us_fidi_usart_mode::R`](R) reader structure"] +impl crate::Readable for US_FIDI_USART_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_fidi_usart_mode::W`](W) writer structure"] impl crate::Writable for US_FIDI_USART_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_icdiff.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_icdiff.rs index 0d5ea152..1ea822a5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_icdiff.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_icdiff.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_ICDIFF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_ICDIFF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ICDIFF` reader - IC Differentiator Number"] pub type ICDIFF_R = crate::FieldReader; #[doc = "Field `ICDIFF` writer - IC Differentiator Number"] -pub type ICDIFF_W<'a, const O: u8> = crate::FieldWriter<'a, US_ICDIFF_SPEC, 4, O>; +pub type ICDIFF_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - IC Differentiator Number"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:3 - IC Differentiator Number"] #[inline(always)] #[must_use] - pub fn icdiff(&mut self) -> ICDIFF_W<0> { + pub fn icdiff(&mut self) -> ICDIFF_W { ICDIFF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "IC DIFF Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_icdiff](index.html) module"] +#[doc = "IC DIFF Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_icdiff::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_icdiff::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_ICDIFF_SPEC; impl crate::RegisterSpec for US_ICDIFF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_icdiff::R](R) reader structure"] -impl crate::Readable for US_ICDIFF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_icdiff::W](W) writer structure"] +#[doc = "`read()` method returns [`us_icdiff::R`](R) reader structure"] +impl crate::Readable for US_ICDIFF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_icdiff::W`](W) writer structure"] impl crate::Writable for US_ICDIFF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lin_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lin_mode.rs index 18a1603d..0d7e2c4e 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lin_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lin_mode.rs @@ -1,176 +1,156 @@ #[doc = "Register `US_IDR_LIN_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRAME` writer - Framing Error Interrupt Disable"] -pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PARE` writer - Parity Error Interrupt Disable"] -pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type PARE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEOUT` writer - Timeout Interrupt Disable"] -pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINBK` writer - LIN Break Sent or LIN Break Received Interrupt Disable"] -pub type LINBK_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINBK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINID` writer - LIN Identifier Sent or LIN Identifier Received Interrupt Disable"] -pub type LINID_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINTC` writer - LIN Transfer Completed Interrupt Disable"] -pub type LINTC_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINBE` writer - LIN Bus Error Interrupt Disable"] -pub type LINBE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINBE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINISFE` writer - LIN Inconsistent Synch Field Error Interrupt Disable"] -pub type LINISFE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINISFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINIPE` writer - LIN Identifier Parity Interrupt Disable"] -pub type LINIPE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINIPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINCE` writer - LIN Checksum Error Interrupt Disable"] -pub type LINCE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINSNRE` writer - LIN Slave Not Responding Error Interrupt Disable"] -pub type LINSNRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINSNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINSTE` writer - LIN Synch Tolerance Error Interrupt Disable"] -pub type LINSTE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINSTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINHTE` writer - LIN Header Timeout Error Interrupt Disable"] -pub type LINHTE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LIN_MODE_SPEC, O>; +pub type LINHTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - Framing Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn frame(&mut self) -> FRAME_W<6> { + pub fn frame(&mut self) -> FRAME_W { FRAME_W::new(self) } #[doc = "Bit 7 - Parity Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pare(&mut self) -> PARE_W<7> { + pub fn pare(&mut self) -> PARE_W { PARE_W::new(self) } #[doc = "Bit 8 - Timeout Interrupt Disable"] #[inline(always)] #[must_use] - pub fn timeout(&mut self) -> TIMEOUT_W<8> { + pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 13 - LIN Break Sent or LIN Break Received Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linbk(&mut self) -> LINBK_W<13> { + pub fn linbk(&mut self) -> LINBK_W { LINBK_W::new(self) } #[doc = "Bit 14 - LIN Identifier Sent or LIN Identifier Received Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linid(&mut self) -> LINID_W<14> { + pub fn linid(&mut self) -> LINID_W { LINID_W::new(self) } #[doc = "Bit 15 - LIN Transfer Completed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lintc(&mut self) -> LINTC_W<15> { + pub fn lintc(&mut self) -> LINTC_W { LINTC_W::new(self) } #[doc = "Bit 25 - LIN Bus Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linbe(&mut self) -> LINBE_W<25> { + pub fn linbe(&mut self) -> LINBE_W { LINBE_W::new(self) } #[doc = "Bit 26 - LIN Inconsistent Synch Field Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linisfe(&mut self) -> LINISFE_W<26> { + pub fn linisfe(&mut self) -> LINISFE_W { LINISFE_W::new(self) } #[doc = "Bit 27 - LIN Identifier Parity Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linipe(&mut self) -> LINIPE_W<27> { + pub fn linipe(&mut self) -> LINIPE_W { LINIPE_W::new(self) } #[doc = "Bit 28 - LIN Checksum Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lince(&mut self) -> LINCE_W<28> { + pub fn lince(&mut self) -> LINCE_W { LINCE_W::new(self) } #[doc = "Bit 29 - LIN Slave Not Responding Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linsnre(&mut self) -> LINSNRE_W<29> { + pub fn linsnre(&mut self) -> LINSNRE_W { LINSNRE_W::new(self) } #[doc = "Bit 30 - LIN Synch Tolerance Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linste(&mut self) -> LINSTE_W<30> { + pub fn linste(&mut self) -> LINSTE_W { LINSTE_W::new(self) } #[doc = "Bit 31 - LIN Header Timeout Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn linhte(&mut self) -> LINHTE_W<31> { + pub fn linhte(&mut self) -> LINHTE_W { LINHTE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_idr_lin_mode](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_lin_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IDR_LIN_MODE_SPEC; impl crate::RegisterSpec for US_IDR_LIN_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_idr_lin_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_idr_lin_mode::W`](W) writer structure"] impl crate::Writable for US_IDR_LIN_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lon_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lon_mode.rs index dcd1fdb2..131c7414 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lon_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_lon_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `US_IDR_LON_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LSFE` writer - LON Short Frame Error Interrupt Disable"] -pub type LSFE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LSFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LCRCE` writer - LON CRC Error Interrupt Disable"] -pub type LCRCE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LCRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - SPI Underrun Error Interrupt Disable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LTXD` writer - LON Transmission Done Interrupt Disable"] -pub type LTXD_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LTXD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LCOL` writer - LON Collision Interrupt Disable"] -pub type LCOL_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LCOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LFET` writer - LON Frame Early Termination Interrupt Disable"] -pub type LFET_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LFET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LRXD` writer - LON Reception Done Interrupt Disable"] -pub type LRXD_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LRXD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LBLOVFE` writer - LON Backlog Overflow Error Interrupt Disable"] -pub type LBLOVFE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_LON_MODE_SPEC, O>; +pub type LBLOVFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - LON Short Frame Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lsfe(&mut self) -> LSFE_W<6> { + pub fn lsfe(&mut self) -> LSFE_W { LSFE_W::new(self) } #[doc = "Bit 7 - LON CRC Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lcrce(&mut self) -> LCRCE_W<7> { + pub fn lcrce(&mut self) -> LCRCE_W { LCRCE_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - SPI Underrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<10> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 24 - LON Transmission Done Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ltxd(&mut self) -> LTXD_W<24> { + pub fn ltxd(&mut self) -> LTXD_W { LTXD_W::new(self) } #[doc = "Bit 25 - LON Collision Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lcol(&mut self) -> LCOL_W<25> { + pub fn lcol(&mut self) -> LCOL_W { LCOL_W::new(self) } #[doc = "Bit 26 - LON Frame Early Termination Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lfet(&mut self) -> LFET_W<26> { + pub fn lfet(&mut self) -> LFET_W { LFET_W::new(self) } #[doc = "Bit 27 - LON Reception Done Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lrxd(&mut self) -> LRXD_W<27> { + pub fn lrxd(&mut self) -> LRXD_W { LRXD_W::new(self) } #[doc = "Bit 28 - LON Backlog Overflow Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn lblovfe(&mut self) -> LBLOVFE_W<28> { + pub fn lblovfe(&mut self) -> LBLOVFE_W { LBLOVFE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_idr_lon_mode](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_lon_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IDR_LON_MODE_SPEC; impl crate::RegisterSpec for US_IDR_LON_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_idr_lon_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_idr_lon_mode::W`](W) writer structure"] impl crate::Writable for US_IDR_LON_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_spi_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_spi_mode.rs index 8f74e4cc..164a9fa5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_spi_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_spi_mode.rs @@ -1,88 +1,68 @@ #[doc = "Register `US_IDR_SPI_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_SPI_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_SPI_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_SPI_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_SPI_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - SPI Underrun Error Interrupt Disable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_SPI_MODE_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NSSE` writer - NSS Line (Driving CTS Pin) Rising or Falling Edge Event"] -pub type NSSE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_SPI_MODE_SPEC, O>; +pub type NSSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - SPI Underrun Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<10> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 19 - NSS Line (Driving CTS Pin) Rising or Falling Edge Event"] #[inline(always)] #[must_use] - pub fn nsse(&mut self) -> NSSE_W<19> { + pub fn nsse(&mut self) -> NSSE_W { NSSE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_idr_spi_mode](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_spi_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IDR_SPI_MODE_SPEC; impl crate::RegisterSpec for US_IDR_SPI_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_idr_spi_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_idr_spi_mode::W`](W) writer structure"] impl crate::Writable for US_IDR_SPI_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_usart_mode.rs index 81da2d7c..ee217e93 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_idr_usart_mode.rs @@ -1,160 +1,140 @@ #[doc = "Register `US_IDR_USART_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Disable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Disable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBRK` writer - Receiver Break Interrupt Disable"] -pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type RXBRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRAME` writer - Framing Error Interrupt Disable"] -pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PARE` writer - Parity Error Interrupt Disable"] -pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type PARE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEOUT` writer - Timeout Interrupt Disable"] -pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Disable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITER` writer - Max Number of Repetitions Reached Interrupt Disable"] -pub type ITER_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type ITER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NACK` writer - Non Acknowledge Interrupt Disable"] -pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type NACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RIIC` writer - Ring Indicator Input Change Disable"] -pub type RIIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type RIIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRIC` writer - Data Set Ready Input Change Disable"] -pub type DSRIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type DSRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDIC` writer - Data Carrier Detect Input Change Interrupt Disable"] -pub type DCDIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type DCDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSIC` writer - Clear to Send Input Change Interrupt Disable"] -pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type CTSIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MANE` writer - Manchester Error Interrupt Disable"] -pub type MANE_W<'a, const O: u8> = crate::BitWriter<'a, US_IDR_USART_MODE_SPEC, O>; +pub type MANE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 2 - Receiver Break Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxbrk(&mut self) -> RXBRK_W<2> { + pub fn rxbrk(&mut self) -> RXBRK_W { RXBRK_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - Framing Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn frame(&mut self) -> FRAME_W<6> { + pub fn frame(&mut self) -> FRAME_W { FRAME_W::new(self) } #[doc = "Bit 7 - Parity Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pare(&mut self) -> PARE_W<7> { + pub fn pare(&mut self) -> PARE_W { PARE_W::new(self) } #[doc = "Bit 8 - Timeout Interrupt Disable"] #[inline(always)] #[must_use] - pub fn timeout(&mut self) -> TIMEOUT_W<8> { + pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - Max Number of Repetitions Reached Interrupt Disable"] #[inline(always)] #[must_use] - pub fn iter(&mut self) -> ITER_W<10> { + pub fn iter(&mut self) -> ITER_W { ITER_W::new(self) } #[doc = "Bit 13 - Non Acknowledge Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nack(&mut self) -> NACK_W<13> { + pub fn nack(&mut self) -> NACK_W { NACK_W::new(self) } #[doc = "Bit 16 - Ring Indicator Input Change Disable"] #[inline(always)] #[must_use] - pub fn riic(&mut self) -> RIIC_W<16> { + pub fn riic(&mut self) -> RIIC_W { RIIC_W::new(self) } #[doc = "Bit 17 - Data Set Ready Input Change Disable"] #[inline(always)] #[must_use] - pub fn dsric(&mut self) -> DSRIC_W<17> { + pub fn dsric(&mut self) -> DSRIC_W { DSRIC_W::new(self) } #[doc = "Bit 18 - Data Carrier Detect Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dcdic(&mut self) -> DCDIC_W<18> { + pub fn dcdic(&mut self) -> DCDIC_W { DCDIC_W::new(self) } #[doc = "Bit 19 - Clear to Send Input Change Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ctsic(&mut self) -> CTSIC_W<19> { + pub fn ctsic(&mut self) -> CTSIC_W { CTSIC_W::new(self) } #[doc = "Bit 24 - Manchester Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn mane(&mut self) -> MANE_W<24> { + pub fn mane(&mut self) -> MANE_W { MANE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_idr_usart_mode](index.html) module"] +#[doc = "Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idr_usart_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IDR_USART_MODE_SPEC; impl crate::RegisterSpec for US_IDR_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_idr_usart_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_idr_usart_mode::W`](W) writer structure"] impl crate::Writable for US_IDR_USART_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_idtrx.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_idtrx.rs index 45b997f8..4af24e58 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_idtrx.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_idtrx.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_IDTRX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_IDTRX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IDTRX` reader - LON Indeterminate Time after Reception (comm_type = 1 mode only)"] pub type IDTRX_R = crate::FieldReader; #[doc = "Field `IDTRX` writer - LON Indeterminate Time after Reception (comm_type = 1 mode only)"] -pub type IDTRX_W<'a, const O: u8> = crate::FieldWriter<'a, US_IDTRX_SPEC, 24, O, u32>; +pub type IDTRX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - LON Indeterminate Time after Reception (comm_type = 1 mode only)"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - LON Indeterminate Time after Reception (comm_type = 1 mode only)"] #[inline(always)] #[must_use] - pub fn idtrx(&mut self) -> IDTRX_W<0> { + pub fn idtrx(&mut self) -> IDTRX_W { IDTRX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON IDT Rx Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_idtrx](index.html) module"] +#[doc = "LON IDT Rx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_idtrx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idtrx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IDTRX_SPEC; impl crate::RegisterSpec for US_IDTRX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_idtrx::R](R) reader structure"] -impl crate::Readable for US_IDTRX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_idtrx::W](W) writer structure"] +#[doc = "`read()` method returns [`us_idtrx::R`](R) reader structure"] +impl crate::Readable for US_IDTRX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_idtrx::W`](W) writer structure"] impl crate::Writable for US_IDTRX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_idttx.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_idttx.rs index c6117c89..894bbe01 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_idttx.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_idttx.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_IDTTX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_IDTTX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IDTTX` reader - LON Indeterminate Time after Transmission (comm_type = 1 mode only)"] pub type IDTTX_R = crate::FieldReader; #[doc = "Field `IDTTX` writer - LON Indeterminate Time after Transmission (comm_type = 1 mode only)"] -pub type IDTTX_W<'a, const O: u8> = crate::FieldWriter<'a, US_IDTTX_SPEC, 24, O, u32>; +pub type IDTTX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - LON Indeterminate Time after Transmission (comm_type = 1 mode only)"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - LON Indeterminate Time after Transmission (comm_type = 1 mode only)"] #[inline(always)] #[must_use] - pub fn idttx(&mut self) -> IDTTX_W<0> { + pub fn idttx(&mut self) -> IDTTX_W { IDTTX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON IDT Tx Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_idttx](index.html) module"] +#[doc = "LON IDT Tx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_idttx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_idttx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IDTTX_SPEC; impl crate::RegisterSpec for US_IDTTX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_idttx::R](R) reader structure"] -impl crate::Readable for US_IDTTX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_idttx::W](W) writer structure"] +#[doc = "`read()` method returns [`us_idttx::R`](R) reader structure"] +impl crate::Readable for US_IDTTX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_idttx::W`](W) writer structure"] impl crate::Writable for US_IDTTX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lin_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lin_mode.rs index 9197d079..35358778 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lin_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lin_mode.rs @@ -1,176 +1,156 @@ #[doc = "Register `US_IER_LIN_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRAME` writer - Framing Error Interrupt Enable"] -pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PARE` writer - Parity Error Interrupt Enable"] -pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type PARE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEOUT` writer - Timeout Interrupt Enable"] -pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINBK` writer - LIN Break Sent or LIN Break Received Interrupt Enable"] -pub type LINBK_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINBK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINID` writer - LIN Identifier Sent or LIN Identifier Received Interrupt Enable"] -pub type LINID_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINTC` writer - LIN Transfer Completed Interrupt Enable"] -pub type LINTC_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINBE` writer - LIN Bus Error Interrupt Enable"] -pub type LINBE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINBE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINISFE` writer - LIN Inconsistent Synch Field Error Interrupt Enable"] -pub type LINISFE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINISFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINIPE` writer - LIN Identifier Parity Interrupt Enable"] -pub type LINIPE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINIPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINCE` writer - LIN Checksum Error Interrupt Enable"] -pub type LINCE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINSNRE` writer - LIN Slave Not Responding Error Interrupt Enable"] -pub type LINSNRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINSNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINSTE` writer - LIN Synch Tolerance Error Interrupt Enable"] -pub type LINSTE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINSTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LINHTE` writer - LIN Header Timeout Error Interrupt Enable"] -pub type LINHTE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LIN_MODE_SPEC, O>; +pub type LINHTE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - Framing Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn frame(&mut self) -> FRAME_W<6> { + pub fn frame(&mut self) -> FRAME_W { FRAME_W::new(self) } #[doc = "Bit 7 - Parity Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pare(&mut self) -> PARE_W<7> { + pub fn pare(&mut self) -> PARE_W { PARE_W::new(self) } #[doc = "Bit 8 - Timeout Interrupt Enable"] #[inline(always)] #[must_use] - pub fn timeout(&mut self) -> TIMEOUT_W<8> { + pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 13 - LIN Break Sent or LIN Break Received Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linbk(&mut self) -> LINBK_W<13> { + pub fn linbk(&mut self) -> LINBK_W { LINBK_W::new(self) } #[doc = "Bit 14 - LIN Identifier Sent or LIN Identifier Received Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linid(&mut self) -> LINID_W<14> { + pub fn linid(&mut self) -> LINID_W { LINID_W::new(self) } #[doc = "Bit 15 - LIN Transfer Completed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lintc(&mut self) -> LINTC_W<15> { + pub fn lintc(&mut self) -> LINTC_W { LINTC_W::new(self) } #[doc = "Bit 25 - LIN Bus Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linbe(&mut self) -> LINBE_W<25> { + pub fn linbe(&mut self) -> LINBE_W { LINBE_W::new(self) } #[doc = "Bit 26 - LIN Inconsistent Synch Field Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linisfe(&mut self) -> LINISFE_W<26> { + pub fn linisfe(&mut self) -> LINISFE_W { LINISFE_W::new(self) } #[doc = "Bit 27 - LIN Identifier Parity Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linipe(&mut self) -> LINIPE_W<27> { + pub fn linipe(&mut self) -> LINIPE_W { LINIPE_W::new(self) } #[doc = "Bit 28 - LIN Checksum Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lince(&mut self) -> LINCE_W<28> { + pub fn lince(&mut self) -> LINCE_W { LINCE_W::new(self) } #[doc = "Bit 29 - LIN Slave Not Responding Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linsnre(&mut self) -> LINSNRE_W<29> { + pub fn linsnre(&mut self) -> LINSNRE_W { LINSNRE_W::new(self) } #[doc = "Bit 30 - LIN Synch Tolerance Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linste(&mut self) -> LINSTE_W<30> { + pub fn linste(&mut self) -> LINSTE_W { LINSTE_W::new(self) } #[doc = "Bit 31 - LIN Header Timeout Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn linhte(&mut self) -> LINHTE_W<31> { + pub fn linhte(&mut self) -> LINHTE_W { LINHTE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ier_lin_mode](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_lin_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IER_LIN_MODE_SPEC; impl crate::RegisterSpec for US_IER_LIN_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_ier_lin_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_ier_lin_mode::W`](W) writer structure"] impl crate::Writable for US_IER_LIN_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lon_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lon_mode.rs index c6126560..a73180cc 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lon_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_lon_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `US_IER_LON_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LSFE` writer - LON Short Frame Error Interrupt Enable"] -pub type LSFE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LSFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LCRCE` writer - LON CRC Error Interrupt Enable"] -pub type LCRCE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LCRCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Underrun Error Interrupt Enable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LTXD` writer - LON Transmission Done Interrupt Enable"] -pub type LTXD_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LTXD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LCOL` writer - LON Collision Interrupt Enable"] -pub type LCOL_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LCOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LFET` writer - LON Frame Early Termination Interrupt Enable"] -pub type LFET_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LFET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LRXD` writer - LON Reception Done Interrupt Enable"] -pub type LRXD_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LRXD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LBLOVFE` writer - LON Backlog Overflow Error Interrupt Enable"] -pub type LBLOVFE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_LON_MODE_SPEC, O>; +pub type LBLOVFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - LON Short Frame Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lsfe(&mut self) -> LSFE_W<6> { + pub fn lsfe(&mut self) -> LSFE_W { LSFE_W::new(self) } #[doc = "Bit 7 - LON CRC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lcrce(&mut self) -> LCRCE_W<7> { + pub fn lcrce(&mut self) -> LCRCE_W { LCRCE_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - Underrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<10> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 24 - LON Transmission Done Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ltxd(&mut self) -> LTXD_W<24> { + pub fn ltxd(&mut self) -> LTXD_W { LTXD_W::new(self) } #[doc = "Bit 25 - LON Collision Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lcol(&mut self) -> LCOL_W<25> { + pub fn lcol(&mut self) -> LCOL_W { LCOL_W::new(self) } #[doc = "Bit 26 - LON Frame Early Termination Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lfet(&mut self) -> LFET_W<26> { + pub fn lfet(&mut self) -> LFET_W { LFET_W::new(self) } #[doc = "Bit 27 - LON Reception Done Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lrxd(&mut self) -> LRXD_W<27> { + pub fn lrxd(&mut self) -> LRXD_W { LRXD_W::new(self) } #[doc = "Bit 28 - LON Backlog Overflow Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn lblovfe(&mut self) -> LBLOVFE_W<28> { + pub fn lblovfe(&mut self) -> LBLOVFE_W { LBLOVFE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ier_lon_mode](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_lon_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IER_LON_MODE_SPEC; impl crate::RegisterSpec for US_IER_LON_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_ier_lon_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_ier_lon_mode::W`](W) writer structure"] impl crate::Writable for US_IER_LON_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_spi_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_spi_mode.rs index 11850061..3a3993d0 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_spi_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_spi_mode.rs @@ -1,88 +1,68 @@ #[doc = "Register `US_IER_SPI_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_SPI_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_SPI_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_SPI_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_SPI_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNRE` writer - Underrun Error Interrupt Enable"] -pub type UNRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_SPI_MODE_SPEC, O>; +pub type UNRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NSSE` writer - NSS Line (Driving CTS Pin) Rising or Falling Edge Event"] -pub type NSSE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_SPI_MODE_SPEC, O>; +pub type NSSE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - Underrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn unre(&mut self) -> UNRE_W<10> { + pub fn unre(&mut self) -> UNRE_W { UNRE_W::new(self) } #[doc = "Bit 19 - NSS Line (Driving CTS Pin) Rising or Falling Edge Event"] #[inline(always)] #[must_use] - pub fn nsse(&mut self) -> NSSE_W<19> { + pub fn nsse(&mut self) -> NSSE_W { NSSE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ier_spi_mode](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_spi_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IER_SPI_MODE_SPEC; impl crate::RegisterSpec for US_IER_SPI_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_ier_spi_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_ier_spi_mode::W`](W) writer structure"] impl crate::Writable for US_IER_SPI_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_usart_mode.rs index b9565d19..066551e0 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ier_usart_mode.rs @@ -1,160 +1,140 @@ #[doc = "Register `US_IER_USART_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXRDY` writer - RXRDY Interrupt Enable"] -pub type RXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type RXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXRDY` writer - TXRDY Interrupt Enable"] -pub type TXRDY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type TXRDY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXBRK` writer - Receiver Break Interrupt Enable"] -pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type RXBRK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVRE` writer - Overrun Error Interrupt Enable"] -pub type OVRE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type OVRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRAME` writer - Framing Error Interrupt Enable"] -pub type FRAME_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type FRAME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PARE` writer - Parity Error Interrupt Enable"] -pub type PARE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type PARE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEOUT` writer - Timeout Interrupt Enable"] -pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXEMPTY` writer - TXEMPTY Interrupt Enable"] -pub type TXEMPTY_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type TXEMPTY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ITER` writer - Max number of Repetitions Reached Interrupt Enable"] -pub type ITER_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type ITER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NACK` writer - Non Acknowledge Interrupt Enable"] -pub type NACK_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type NACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RIIC` writer - Ring Indicator Input Change Enable"] -pub type RIIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type RIIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSRIC` writer - Data Set Ready Input Change Enable"] -pub type DSRIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type DSRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DCDIC` writer - Data Carrier Detect Input Change Interrupt Enable"] -pub type DCDIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type DCDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CTSIC` writer - Clear to Send Input Change Interrupt Enable"] -pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type CTSIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MANE` writer - Manchester Error Interrupt Enable"] -pub type MANE_W<'a, const O: u8> = crate::BitWriter<'a, US_IER_USART_MODE_SPEC, O>; +pub type MANE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - RXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrdy(&mut self) -> RXRDY_W<0> { + pub fn rxrdy(&mut self) -> RXRDY_W { RXRDY_W::new(self) } #[doc = "Bit 1 - TXRDY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txrdy(&mut self) -> TXRDY_W<1> { + pub fn txrdy(&mut self) -> TXRDY_W { TXRDY_W::new(self) } #[doc = "Bit 2 - Receiver Break Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxbrk(&mut self) -> RXBRK_W<2> { + pub fn rxbrk(&mut self) -> RXBRK_W { RXBRK_W::new(self) } #[doc = "Bit 5 - Overrun Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ovre(&mut self) -> OVRE_W<5> { + pub fn ovre(&mut self) -> OVRE_W { OVRE_W::new(self) } #[doc = "Bit 6 - Framing Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn frame(&mut self) -> FRAME_W<6> { + pub fn frame(&mut self) -> FRAME_W { FRAME_W::new(self) } #[doc = "Bit 7 - Parity Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pare(&mut self) -> PARE_W<7> { + pub fn pare(&mut self) -> PARE_W { PARE_W::new(self) } #[doc = "Bit 8 - Timeout Interrupt Enable"] #[inline(always)] #[must_use] - pub fn timeout(&mut self) -> TIMEOUT_W<8> { + pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W::new(self) } #[doc = "Bit 9 - TXEMPTY Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txempty(&mut self) -> TXEMPTY_W<9> { + pub fn txempty(&mut self) -> TXEMPTY_W { TXEMPTY_W::new(self) } #[doc = "Bit 10 - Max number of Repetitions Reached Interrupt Enable"] #[inline(always)] #[must_use] - pub fn iter(&mut self) -> ITER_W<10> { + pub fn iter(&mut self) -> ITER_W { ITER_W::new(self) } #[doc = "Bit 13 - Non Acknowledge Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nack(&mut self) -> NACK_W<13> { + pub fn nack(&mut self) -> NACK_W { NACK_W::new(self) } #[doc = "Bit 16 - Ring Indicator Input Change Enable"] #[inline(always)] #[must_use] - pub fn riic(&mut self) -> RIIC_W<16> { + pub fn riic(&mut self) -> RIIC_W { RIIC_W::new(self) } #[doc = "Bit 17 - Data Set Ready Input Change Enable"] #[inline(always)] #[must_use] - pub fn dsric(&mut self) -> DSRIC_W<17> { + pub fn dsric(&mut self) -> DSRIC_W { DSRIC_W::new(self) } #[doc = "Bit 18 - Data Carrier Detect Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dcdic(&mut self) -> DCDIC_W<18> { + pub fn dcdic(&mut self) -> DCDIC_W { DCDIC_W::new(self) } #[doc = "Bit 19 - Clear to Send Input Change Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ctsic(&mut self) -> CTSIC_W<19> { + pub fn ctsic(&mut self) -> CTSIC_W { CTSIC_W::new(self) } #[doc = "Bit 24 - Manchester Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn mane(&mut self) -> MANE_W<24> { + pub fn mane(&mut self) -> MANE_W { MANE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ier_usart_mode](index.html) module"] +#[doc = "Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ier_usart_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IER_USART_MODE_SPEC; impl crate::RegisterSpec for US_IER_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_ier_usart_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_ier_usart_mode::W`](W) writer structure"] impl crate::Writable for US_IER_USART_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_if.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_if.rs index a4fe09f1..8a1b7161 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_if.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_if.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_IF` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_IF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IRDA_FILTER` reader - IrDA Filter"] pub type IRDA_FILTER_R = crate::FieldReader; #[doc = "Field `IRDA_FILTER` writer - IrDA Filter"] -pub type IRDA_FILTER_W<'a, const O: u8> = crate::FieldWriter<'a, US_IF_SPEC, 8, O>; +pub type IRDA_FILTER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - IrDA Filter"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:7 - IrDA Filter"] #[inline(always)] #[must_use] - pub fn irda_filter(&mut self) -> IRDA_FILTER_W<0> { + pub fn irda_filter(&mut self) -> IRDA_FILTER_W { IRDA_FILTER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "IrDA Filter Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_if](index.html) module"] +#[doc = "IrDA Filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_if::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_if::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IF_SPEC; impl crate::RegisterSpec for US_IF_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_if::R](R) reader structure"] -impl crate::Readable for US_IF_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_if::W](W) writer structure"] +#[doc = "`read()` method returns [`us_if::R`](R) reader structure"] +impl crate::Readable for US_IF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_if::W`](W) writer structure"] impl crate::Writable for US_IF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lin_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lin_mode.rs index a003c44c..cf782085 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lin_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lin_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_IMR_LIN_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - RXRDY Interrupt Mask"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - TXRDY Interrupt Mask"] @@ -134,15 +121,13 @@ impl R { LINHTE_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_imr_lin_mode](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_lin_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IMR_LIN_MODE_SPEC; impl crate::RegisterSpec for US_IMR_LIN_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_imr_lin_mode::R](R) reader structure"] -impl crate::Readable for US_IMR_LIN_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_imr_lin_mode::R`](R) reader structure"] +impl crate::Readable for US_IMR_LIN_MODE_SPEC {} #[doc = "`reset()` method sets US_IMR_LIN_MODE to value 0"] impl crate::Resettable for US_IMR_LIN_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lon_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lon_mode.rs index 53e7fe78..1697a9b1 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lon_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_lon_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_IMR_LON_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - RXRDY Interrupt Mask"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - TXRDY Interrupt Mask"] @@ -99,15 +86,13 @@ impl R { LBLOVFE_R::new(((self.bits >> 28) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_imr_lon_mode](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_lon_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IMR_LON_MODE_SPEC; impl crate::RegisterSpec for US_IMR_LON_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_imr_lon_mode::R](R) reader structure"] -impl crate::Readable for US_IMR_LON_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_imr_lon_mode::R`](R) reader structure"] +impl crate::Readable for US_IMR_LON_MODE_SPEC {} #[doc = "`reset()` method sets US_IMR_LON_MODE to value 0"] impl crate::Resettable for US_IMR_LON_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_spi_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_spi_mode.rs index 15ea353d..69f65dcc 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_spi_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_spi_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_IMR_SPI_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - RXRDY Interrupt Mask"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - TXRDY Interrupt Mask"] @@ -57,15 +44,13 @@ impl R { NSSE_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_imr_spi_mode](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_spi_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IMR_SPI_MODE_SPEC; impl crate::RegisterSpec for US_IMR_SPI_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_imr_spi_mode::R](R) reader structure"] -impl crate::Readable for US_IMR_SPI_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_imr_spi_mode::R`](R) reader structure"] +impl crate::Readable for US_IMR_SPI_MODE_SPEC {} #[doc = "`reset()` method sets US_IMR_SPI_MODE to value 0"] impl crate::Resettable for US_IMR_SPI_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_usart_mode.rs index cf17da05..5d04335f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_imr_usart_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_IMR_USART_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXRDY` reader - RXRDY Interrupt Mask"] pub type RXRDY_R = crate::BitReader; #[doc = "Field `TXRDY` reader - TXRDY Interrupt Mask"] @@ -120,15 +107,13 @@ impl R { MANE_R::new(((self.bits >> 24) & 1) != 0) } } -#[doc = "Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_imr_usart_mode](index.html) module"] +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_imr_usart_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_IMR_USART_MODE_SPEC; impl crate::RegisterSpec for US_IMR_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_imr_usart_mode::R](R) reader structure"] -impl crate::Readable for US_IMR_USART_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_imr_usart_mode::R`](R) reader structure"] +impl crate::Readable for US_IMR_USART_MODE_SPEC {} #[doc = "`reset()` method sets US_IMR_USART_MODE to value 0"] impl crate::Resettable for US_IMR_USART_MODE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_linbrr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_linbrr.rs index 62de0701..800d5188 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_linbrr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_linbrr.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_LINBRR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LINCD` reader - Clock Divider after Synchronization"] pub type LINCD_R = crate::FieldReader; #[doc = "Field `LINFP` reader - Fractional Part after Synchronization"] @@ -29,15 +16,13 @@ impl R { LINFP_R::new(((self.bits >> 16) & 7) as u8) } } -#[doc = "LIN Baud Rate Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_linbrr](index.html) module"] +#[doc = "LIN Baud Rate Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_linbrr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LINBRR_SPEC; impl crate::RegisterSpec for US_LINBRR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_linbrr::R](R) reader structure"] -impl crate::Readable for US_LINBRR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_linbrr::R`](R) reader structure"] +impl crate::Readable for US_LINBRR_SPEC {} #[doc = "`reset()` method sets US_LINBRR to value 0"] impl crate::Resettable for US_LINBRR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_linir.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_linir.rs index c458d2da..6a5fc7c3 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_linir.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_linir.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_LINIR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LINIR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IDCHR` reader - Identifier Character"] pub type IDCHR_R = crate::FieldReader; #[doc = "Field `IDCHR` writer - Identifier Character"] -pub type IDCHR_W<'a, const O: u8> = crate::FieldWriter<'a, US_LINIR_SPEC, 8, O>; +pub type IDCHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Identifier Character"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:7 - Identifier Character"] #[inline(always)] #[must_use] - pub fn idchr(&mut self) -> IDCHR_W<0> { + pub fn idchr(&mut self) -> IDCHR_W { IDCHR_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LIN Identifier Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_linir](index.html) module"] +#[doc = "LIN Identifier Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_linir::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_linir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LINIR_SPEC; impl crate::RegisterSpec for US_LINIR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_linir::R](R) reader structure"] -impl crate::Readable for US_LINIR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_linir::W](W) writer structure"] +#[doc = "`read()` method returns [`us_linir::R`](R) reader structure"] +impl crate::Readable for US_LINIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_linir::W`](W) writer structure"] impl crate::Writable for US_LINIR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_linmr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_linmr.rs index e0fedb17..5ecf629f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_linmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_linmr.rs @@ -1,39 +1,7 @@ #[doc = "Register `US_LINMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LINMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NACT` reader - LIN Node Action"] pub type NACT_R = crate::FieldReader; #[doc = "LIN Node Action\n\nValue on reset: 0"] @@ -67,77 +35,81 @@ impl NACT_R { _ => None, } } - #[doc = "Checks if the value of the field is `PUBLISH`"] + #[doc = "The USART transmits the response."] #[inline(always)] pub fn is_publish(&self) -> bool { *self == NACTSELECT_A::PUBLISH } - #[doc = "Checks if the value of the field is `SUBSCRIBE`"] + #[doc = "The USART receives the response."] #[inline(always)] pub fn is_subscribe(&self) -> bool { *self == NACTSELECT_A::SUBSCRIBE } - #[doc = "Checks if the value of the field is `IGNORE`"] + #[doc = "The USART does not transmit and does not receive the response."] #[inline(always)] pub fn is_ignore(&self) -> bool { *self == NACTSELECT_A::IGNORE } } #[doc = "Field `NACT` writer - LIN Node Action"] -pub type NACT_W<'a, const O: u8> = crate::FieldWriter<'a, US_LINMR_SPEC, 2, O, NACTSELECT_A>; -impl<'a, const O: u8> NACT_W<'a, O> { +pub type NACT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, NACTSELECT_A>; +impl<'a, REG, const O: u8> NACT_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The USART transmits the response."] #[inline(always)] - pub fn publish(self) -> &'a mut W { + pub fn publish(self) -> &'a mut crate::W { self.variant(NACTSELECT_A::PUBLISH) } #[doc = "The USART receives the response."] #[inline(always)] - pub fn subscribe(self) -> &'a mut W { + pub fn subscribe(self) -> &'a mut crate::W { self.variant(NACTSELECT_A::SUBSCRIBE) } #[doc = "The USART does not transmit and does not receive the response."] #[inline(always)] - pub fn ignore(self) -> &'a mut W { + pub fn ignore(self) -> &'a mut crate::W { self.variant(NACTSELECT_A::IGNORE) } } #[doc = "Field `PARDIS` reader - Parity Disable"] pub type PARDIS_R = crate::BitReader; #[doc = "Field `PARDIS` writer - Parity Disable"] -pub type PARDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type PARDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHKDIS` reader - Checksum Disable"] pub type CHKDIS_R = crate::BitReader; #[doc = "Field `CHKDIS` writer - Checksum Disable"] -pub type CHKDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type CHKDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHKTYP` reader - Checksum Type"] pub type CHKTYP_R = crate::BitReader; #[doc = "Field `CHKTYP` writer - Checksum Type"] -pub type CHKTYP_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type CHKTYP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DLM` reader - Data Length Mode"] pub type DLM_R = crate::BitReader; #[doc = "Field `DLM` writer - Data Length Mode"] -pub type DLM_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type DLM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FSDIS` reader - Frame Slot Mode Disable"] pub type FSDIS_R = crate::BitReader; #[doc = "Field `FSDIS` writer - Frame Slot Mode Disable"] -pub type FSDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type FSDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WKUPTYP` reader - Wakeup Signal Type"] pub type WKUPTYP_R = crate::BitReader; #[doc = "Field `WKUPTYP` writer - Wakeup Signal Type"] -pub type WKUPTYP_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type WKUPTYP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DLC` reader - Data Length Control"] pub type DLC_R = crate::FieldReader; #[doc = "Field `DLC` writer - Data Length Control"] -pub type DLC_W<'a, const O: u8> = crate::FieldWriter<'a, US_LINMR_SPEC, 8, O>; +pub type DLC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `PDCM` reader - DMAC Mode"] pub type PDCM_R = crate::BitReader; #[doc = "Field `PDCM` writer - DMAC Mode"] -pub type PDCM_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type PDCM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SYNCDIS` reader - Synchronization Disable"] pub type SYNCDIS_R = crate::BitReader; #[doc = "Field `SYNCDIS` writer - Synchronization Disable"] -pub type SYNCDIS_W<'a, const O: u8> = crate::BitWriter<'a, US_LINMR_SPEC, O>; +pub type SYNCDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:1 - LIN Node Action"] #[inline(always)] @@ -194,82 +166,79 @@ impl W { #[doc = "Bits 0:1 - LIN Node Action"] #[inline(always)] #[must_use] - pub fn nact(&mut self) -> NACT_W<0> { + pub fn nact(&mut self) -> NACT_W { NACT_W::new(self) } #[doc = "Bit 2 - Parity Disable"] #[inline(always)] #[must_use] - pub fn pardis(&mut self) -> PARDIS_W<2> { + pub fn pardis(&mut self) -> PARDIS_W { PARDIS_W::new(self) } #[doc = "Bit 3 - Checksum Disable"] #[inline(always)] #[must_use] - pub fn chkdis(&mut self) -> CHKDIS_W<3> { + pub fn chkdis(&mut self) -> CHKDIS_W { CHKDIS_W::new(self) } #[doc = "Bit 4 - Checksum Type"] #[inline(always)] #[must_use] - pub fn chktyp(&mut self) -> CHKTYP_W<4> { + pub fn chktyp(&mut self) -> CHKTYP_W { CHKTYP_W::new(self) } #[doc = "Bit 5 - Data Length Mode"] #[inline(always)] #[must_use] - pub fn dlm(&mut self) -> DLM_W<5> { + pub fn dlm(&mut self) -> DLM_W { DLM_W::new(self) } #[doc = "Bit 6 - Frame Slot Mode Disable"] #[inline(always)] #[must_use] - pub fn fsdis(&mut self) -> FSDIS_W<6> { + pub fn fsdis(&mut self) -> FSDIS_W { FSDIS_W::new(self) } #[doc = "Bit 7 - Wakeup Signal Type"] #[inline(always)] #[must_use] - pub fn wkuptyp(&mut self) -> WKUPTYP_W<7> { + pub fn wkuptyp(&mut self) -> WKUPTYP_W { WKUPTYP_W::new(self) } #[doc = "Bits 8:15 - Data Length Control"] #[inline(always)] #[must_use] - pub fn dlc(&mut self) -> DLC_W<8> { + pub fn dlc(&mut self) -> DLC_W { DLC_W::new(self) } #[doc = "Bit 16 - DMAC Mode"] #[inline(always)] #[must_use] - pub fn pdcm(&mut self) -> PDCM_W<16> { + pub fn pdcm(&mut self) -> PDCM_W { PDCM_W::new(self) } #[doc = "Bit 17 - Synchronization Disable"] #[inline(always)] #[must_use] - pub fn syncdis(&mut self) -> SYNCDIS_W<17> { + pub fn syncdis(&mut self) -> SYNCDIS_W { SYNCDIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LIN Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_linmr](index.html) module"] +#[doc = "LIN Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_linmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_linmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LINMR_SPEC; impl crate::RegisterSpec for US_LINMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_linmr::R](R) reader structure"] -impl crate::Readable for US_LINMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_linmr::W](W) writer structure"] +#[doc = "`read()` method returns [`us_linmr::R`](R) reader structure"] +impl crate::Readable for US_LINMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_linmr::W`](W) writer structure"] impl crate::Writable for US_LINMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1rx.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1rx.rs index a40b8e9f..ff58efa7 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1rx.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1rx.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_LONB1RX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONB1RX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BETA1RX` reader - LON Beta1 Length after Reception"] pub type BETA1RX_R = crate::FieldReader; #[doc = "Field `BETA1RX` writer - LON Beta1 Length after Reception"] -pub type BETA1RX_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONB1RX_SPEC, 24, O, u32>; +pub type BETA1RX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - LON Beta1 Length after Reception"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - LON Beta1 Length after Reception"] #[inline(always)] #[must_use] - pub fn beta1rx(&mut self) -> BETA1RX_W<0> { + pub fn beta1rx(&mut self) -> BETA1RX_W { BETA1RX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON Beta1 Rx Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonb1rx](index.html) module"] +#[doc = "LON Beta1 Rx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonb1rx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonb1rx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONB1RX_SPEC; impl crate::RegisterSpec for US_LONB1RX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonb1rx::R](R) reader structure"] -impl crate::Readable for US_LONB1RX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_lonb1rx::W](W) writer structure"] +#[doc = "`read()` method returns [`us_lonb1rx::R`](R) reader structure"] +impl crate::Readable for US_LONB1RX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_lonb1rx::W`](W) writer structure"] impl crate::Writable for US_LONB1RX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1tx.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1tx.rs index 7db4bfac..e147c491 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1tx.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonb1tx.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_LONB1TX` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONB1TX` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BETA1TX` reader - LON Beta1 Length after Transmission"] pub type BETA1TX_R = crate::FieldReader; #[doc = "Field `BETA1TX` writer - LON Beta1 Length after Transmission"] -pub type BETA1TX_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONB1TX_SPEC, 24, O, u32>; +pub type BETA1TX_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - LON Beta1 Length after Transmission"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - LON Beta1 Length after Transmission"] #[inline(always)] #[must_use] - pub fn beta1tx(&mut self) -> BETA1TX_W<0> { + pub fn beta1tx(&mut self) -> BETA1TX_W { BETA1TX_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON Beta1 Tx Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonb1tx](index.html) module"] +#[doc = "LON Beta1 Tx Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonb1tx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonb1tx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONB1TX_SPEC; impl crate::RegisterSpec for US_LONB1TX_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonb1tx::R](R) reader structure"] -impl crate::Readable for US_LONB1TX_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_lonb1tx::W](W) writer structure"] +#[doc = "`read()` method returns [`us_lonb1tx::R`](R) reader structure"] +impl crate::Readable for US_LONB1TX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_lonb1tx::W`](W) writer structure"] impl crate::Writable for US_LONB1TX_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonbl.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonbl.rs index 29b96d51..994d1505 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonbl.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonbl.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_LONBL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `LONBL` reader - LON Node Backlog Value"] pub type LONBL_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { LONBL_R::new((self.bits & 0x3f) as u8) } } -#[doc = "LON Backlog Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonbl](index.html) module"] +#[doc = "LON Backlog Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonbl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONBL_SPEC; impl crate::RegisterSpec for US_LONBL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonbl::R](R) reader structure"] -impl crate::Readable for US_LONBL_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_lonbl::R`](R) reader structure"] +impl crate::Readable for US_LONBL_SPEC {} #[doc = "`reset()` method sets US_LONBL to value 0"] impl crate::Resettable for US_LONBL_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_londl.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_londl.rs index c604f22e..39de0b95 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_londl.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_londl.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_LONDL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONDL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LONDL` reader - LON Data Length"] pub type LONDL_R = crate::FieldReader; #[doc = "Field `LONDL` writer - LON Data Length"] -pub type LONDL_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONDL_SPEC, 8, O>; +pub type LONDL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - LON Data Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:7 - LON Data Length"] #[inline(always)] #[must_use] - pub fn londl(&mut self) -> LONDL_W<0> { + pub fn londl(&mut self) -> LONDL_W { LONDL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON Data Length Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_londl](index.html) module"] +#[doc = "LON Data Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_londl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_londl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONDL_SPEC; impl crate::RegisterSpec for US_LONDL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_londl::R](R) reader structure"] -impl crate::Readable for US_LONDL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_londl::W](W) writer structure"] +#[doc = "`read()` method returns [`us_londl::R`](R) reader structure"] +impl crate::Readable for US_LONDL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_londl::W`](W) writer structure"] impl crate::Writable for US_LONDL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonl2hdr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonl2hdr.rs index 1805c186..ca56e4dc 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonl2hdr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonl2hdr.rs @@ -1,51 +1,19 @@ #[doc = "Register `US_LONL2HDR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONL2HDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BLI` reader - LON Backlog Increment"] pub type BLI_R = crate::FieldReader; #[doc = "Field `BLI` writer - LON Backlog Increment"] -pub type BLI_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONL2HDR_SPEC, 6, O>; +pub type BLI_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 6, O>; #[doc = "Field `ALTP` reader - LON Alternate Path Bit"] pub type ALTP_R = crate::BitReader; #[doc = "Field `ALTP` writer - LON Alternate Path Bit"] -pub type ALTP_W<'a, const O: u8> = crate::BitWriter<'a, US_LONL2HDR_SPEC, O>; +pub type ALTP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PB` reader - LON Priority Bit"] pub type PB_R = crate::BitReader; #[doc = "Field `PB` writer - LON Priority Bit"] -pub type PB_W<'a, const O: u8> = crate::BitWriter<'a, US_LONL2HDR_SPEC, O>; +pub type PB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:5 - LON Backlog Increment"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bits 0:5 - LON Backlog Increment"] #[inline(always)] #[must_use] - pub fn bli(&mut self) -> BLI_W<0> { + pub fn bli(&mut self) -> BLI_W { BLI_W::new(self) } #[doc = "Bit 6 - LON Alternate Path Bit"] #[inline(always)] #[must_use] - pub fn altp(&mut self) -> ALTP_W<6> { + pub fn altp(&mut self) -> ALTP_W { ALTP_W::new(self) } #[doc = "Bit 7 - LON Priority Bit"] #[inline(always)] #[must_use] - pub fn pb(&mut self) -> PB_W<7> { + pub fn pb(&mut self) -> PB_W { PB_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON L2HDR Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonl2hdr](index.html) module"] +#[doc = "LON L2HDR Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonl2hdr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonl2hdr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONL2HDR_SPEC; impl crate::RegisterSpec for US_LONL2HDR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonl2hdr::R](R) reader structure"] -impl crate::Readable for US_LONL2HDR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_lonl2hdr::W](W) writer structure"] +#[doc = "`read()` method returns [`us_lonl2hdr::R`](R) reader structure"] +impl crate::Readable for US_LONL2HDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_lonl2hdr::W`](W) writer structure"] impl crate::Writable for US_LONL2HDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonmr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonmr.rs index 28c1e157..317e1724 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonmr.rs @@ -1,67 +1,35 @@ #[doc = "Register `US_LONMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `COMMT` reader - LON comm_type Parameter Value"] pub type COMMT_R = crate::BitReader; #[doc = "Field `COMMT` writer - LON comm_type Parameter Value"] -pub type COMMT_W<'a, const O: u8> = crate::BitWriter<'a, US_LONMR_SPEC, O>; +pub type COMMT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COLDET` reader - LON Collision Detection Feature"] pub type COLDET_R = crate::BitReader; #[doc = "Field `COLDET` writer - LON Collision Detection Feature"] -pub type COLDET_W<'a, const O: u8> = crate::BitWriter<'a, US_LONMR_SPEC, O>; +pub type COLDET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TCOL` reader - Terminate Frame upon Collision Notification"] pub type TCOL_R = crate::BitReader; #[doc = "Field `TCOL` writer - Terminate Frame upon Collision Notification"] -pub type TCOL_W<'a, const O: u8> = crate::BitWriter<'a, US_LONMR_SPEC, O>; +pub type TCOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CDTAIL` reader - LON Collision Detection on Frame Tail"] pub type CDTAIL_R = crate::BitReader; #[doc = "Field `CDTAIL` writer - LON Collision Detection on Frame Tail"] -pub type CDTAIL_W<'a, const O: u8> = crate::BitWriter<'a, US_LONMR_SPEC, O>; +pub type CDTAIL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMAM` reader - LON DMA Mode"] pub type DMAM_R = crate::BitReader; #[doc = "Field `DMAM` writer - LON DMA Mode"] -pub type DMAM_W<'a, const O: u8> = crate::BitWriter<'a, US_LONMR_SPEC, O>; +pub type DMAM_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LCDS` reader - LON Collision Detection Source"] pub type LCDS_R = crate::BitReader; #[doc = "Field `LCDS` writer - LON Collision Detection Source"] -pub type LCDS_W<'a, const O: u8> = crate::BitWriter<'a, US_LONMR_SPEC, O>; +pub type LCDS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EOFS` reader - End of Frame Condition Size"] pub type EOFS_R = crate::FieldReader; #[doc = "Field `EOFS` writer - End of Frame Condition Size"] -pub type EOFS_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONMR_SPEC, 8, O>; +pub type EOFS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 0 - LON comm_type Parameter Value"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bit 0 - LON comm_type Parameter Value"] #[inline(always)] #[must_use] - pub fn commt(&mut self) -> COMMT_W<0> { + pub fn commt(&mut self) -> COMMT_W { COMMT_W::new(self) } #[doc = "Bit 1 - LON Collision Detection Feature"] #[inline(always)] #[must_use] - pub fn coldet(&mut self) -> COLDET_W<1> { + pub fn coldet(&mut self) -> COLDET_W { COLDET_W::new(self) } #[doc = "Bit 2 - Terminate Frame upon Collision Notification"] #[inline(always)] #[must_use] - pub fn tcol(&mut self) -> TCOL_W<2> { + pub fn tcol(&mut self) -> TCOL_W { TCOL_W::new(self) } #[doc = "Bit 3 - LON Collision Detection on Frame Tail"] #[inline(always)] #[must_use] - pub fn cdtail(&mut self) -> CDTAIL_W<3> { + pub fn cdtail(&mut self) -> CDTAIL_W { CDTAIL_W::new(self) } #[doc = "Bit 4 - LON DMA Mode"] #[inline(always)] #[must_use] - pub fn dmam(&mut self) -> DMAM_W<4> { + pub fn dmam(&mut self) -> DMAM_W { DMAM_W::new(self) } #[doc = "Bit 5 - LON Collision Detection Source"] #[inline(always)] #[must_use] - pub fn lcds(&mut self) -> LCDS_W<5> { + pub fn lcds(&mut self) -> LCDS_W { LCDS_W::new(self) } #[doc = "Bits 16:23 - End of Frame Condition Size"] #[inline(always)] #[must_use] - pub fn eofs(&mut self) -> EOFS_W<16> { + pub fn eofs(&mut self) -> EOFS_W { EOFS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonmr](index.html) module"] +#[doc = "LON Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONMR_SPEC; impl crate::RegisterSpec for US_LONMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonmr::R](R) reader structure"] -impl crate::Readable for US_LONMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_lonmr::W](W) writer structure"] +#[doc = "`read()` method returns [`us_lonmr::R`](R) reader structure"] +impl crate::Readable for US_LONMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_lonmr::W`](W) writer structure"] impl crate::Writable for US_LONMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonpr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonpr.rs index 01fe790a..1ab8ebb5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonpr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonpr.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_LONPR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONPR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `LONPL` reader - LON Preamble Length"] pub type LONPL_R = crate::FieldReader; #[doc = "Field `LONPL` writer - LON Preamble Length"] -pub type LONPL_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONPR_SPEC, 14, O, u16>; +pub type LONPL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 14, O, u16>; impl R { #[doc = "Bits 0:13 - LON Preamble Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:13 - LON Preamble Length"] #[inline(always)] #[must_use] - pub fn lonpl(&mut self) -> LONPL_W<0> { + pub fn lonpl(&mut self) -> LONPL_W { LONPL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON Preamble Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonpr](index.html) module"] +#[doc = "LON Preamble Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonpr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONPR_SPEC; impl crate::RegisterSpec for US_LONPR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonpr::R](R) reader structure"] -impl crate::Readable for US_LONPR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_lonpr::W](W) writer structure"] +#[doc = "`read()` method returns [`us_lonpr::R`](R) reader structure"] +impl crate::Readable for US_LONPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_lonpr::W`](W) writer structure"] impl crate::Writable for US_LONPR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonprio.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonprio.rs index bedc96c9..832f9b00 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_lonprio.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_lonprio.rs @@ -1,47 +1,15 @@ #[doc = "Register `US_LONPRIO` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_LONPRIO` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PSNB` reader - LON Priority Slot Number"] pub type PSNB_R = crate::FieldReader; #[doc = "Field `PSNB` writer - LON Priority Slot Number"] -pub type PSNB_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONPRIO_SPEC, 7, O>; +pub type PSNB_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `NPS` reader - LON Node Priority Slot"] pub type NPS_R = crate::FieldReader; #[doc = "Field `NPS` writer - LON Node Priority Slot"] -pub type NPS_W<'a, const O: u8> = crate::FieldWriter<'a, US_LONPRIO_SPEC, 7, O>; +pub type NPS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - LON Priority Slot Number"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:6 - LON Priority Slot Number"] #[inline(always)] #[must_use] - pub fn psnb(&mut self) -> PSNB_W<0> { + pub fn psnb(&mut self) -> PSNB_W { PSNB_W::new(self) } #[doc = "Bits 8:14 - LON Node Priority Slot"] #[inline(always)] #[must_use] - pub fn nps(&mut self) -> NPS_W<8> { + pub fn nps(&mut self) -> NPS_W { NPS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "LON Priority Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_lonprio](index.html) module"] +#[doc = "LON Priority Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_lonprio::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_lonprio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_LONPRIO_SPEC; impl crate::RegisterSpec for US_LONPRIO_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_lonprio::R](R) reader structure"] -impl crate::Readable for US_LONPRIO_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_lonprio::W](W) writer structure"] +#[doc = "`read()` method returns [`us_lonprio::R`](R) reader structure"] +impl crate::Readable for US_LONPRIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_lonprio::W`](W) writer structure"] impl crate::Writable for US_LONPRIO_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_man.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_man.rs index 81ba4b86..7d428d84 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_man.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_man.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_MAN` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_MAN` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TX_PL` reader - Transmitter Preamble Length"] pub type TX_PL_R = crate::FieldReader; #[doc = "Field `TX_PL` writer - Transmitter Preamble Length"] -pub type TX_PL_W<'a, const O: u8> = crate::FieldWriter<'a, US_MAN_SPEC, 4, O>; +pub type TX_PL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `TX_PP` reader - Transmitter Preamble Pattern"] pub type TX_PP_R = crate::FieldReader; #[doc = "Transmitter Preamble Pattern\n\nValue on reset: 0"] @@ -74,59 +42,63 @@ impl TX_PP_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `ALL_ONE`"] + #[doc = "The preamble is composed of '1's"] #[inline(always)] pub fn is_all_one(&self) -> bool { *self == TX_PPSELECT_A::ALL_ONE } - #[doc = "Checks if the value of the field is `ALL_ZERO`"] + #[doc = "The preamble is composed of '0's"] #[inline(always)] pub fn is_all_zero(&self) -> bool { *self == TX_PPSELECT_A::ALL_ZERO } - #[doc = "Checks if the value of the field is `ZERO_ONE`"] + #[doc = "The preamble is composed of '01's"] #[inline(always)] pub fn is_zero_one(&self) -> bool { *self == TX_PPSELECT_A::ZERO_ONE } - #[doc = "Checks if the value of the field is `ONE_ZERO`"] + #[doc = "The preamble is composed of '10's"] #[inline(always)] pub fn is_one_zero(&self) -> bool { *self == TX_PPSELECT_A::ONE_ZERO } } #[doc = "Field `TX_PP` writer - Transmitter Preamble Pattern"] -pub type TX_PP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, US_MAN_SPEC, 2, O, TX_PPSELECT_A>; -impl<'a, const O: u8> TX_PP_W<'a, O> { +pub type TX_PP_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, TX_PPSELECT_A>; +impl<'a, REG, const O: u8> TX_PP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The preamble is composed of '1's"] #[inline(always)] - pub fn all_one(self) -> &'a mut W { + pub fn all_one(self) -> &'a mut crate::W { self.variant(TX_PPSELECT_A::ALL_ONE) } #[doc = "The preamble is composed of '0's"] #[inline(always)] - pub fn all_zero(self) -> &'a mut W { + pub fn all_zero(self) -> &'a mut crate::W { self.variant(TX_PPSELECT_A::ALL_ZERO) } #[doc = "The preamble is composed of '01's"] #[inline(always)] - pub fn zero_one(self) -> &'a mut W { + pub fn zero_one(self) -> &'a mut crate::W { self.variant(TX_PPSELECT_A::ZERO_ONE) } #[doc = "The preamble is composed of '10's"] #[inline(always)] - pub fn one_zero(self) -> &'a mut W { + pub fn one_zero(self) -> &'a mut crate::W { self.variant(TX_PPSELECT_A::ONE_ZERO) } } #[doc = "Field `TX_MPOL` reader - Transmitter Manchester Polarity"] pub type TX_MPOL_R = crate::BitReader; #[doc = "Field `TX_MPOL` writer - Transmitter Manchester Polarity"] -pub type TX_MPOL_W<'a, const O: u8> = crate::BitWriter<'a, US_MAN_SPEC, O>; +pub type TX_MPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RX_PL` reader - Receiver Preamble Length"] pub type RX_PL_R = crate::FieldReader; #[doc = "Field `RX_PL` writer - Receiver Preamble Length"] -pub type RX_PL_W<'a, const O: u8> = crate::FieldWriter<'a, US_MAN_SPEC, 4, O>; +pub type RX_PL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `RX_PP` reader - Receiver Preamble Pattern detected"] pub type RX_PP_R = crate::FieldReader; #[doc = "Receiver Preamble Pattern detected\n\nValue on reset: 0"] @@ -163,67 +135,71 @@ impl RX_PP_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `ALL_ONE`"] + #[doc = "The preamble is composed of '1's"] #[inline(always)] pub fn is_all_one(&self) -> bool { *self == RX_PPSELECT_A::ALL_ONE } - #[doc = "Checks if the value of the field is `ALL_ZERO`"] + #[doc = "The preamble is composed of '0's"] #[inline(always)] pub fn is_all_zero(&self) -> bool { *self == RX_PPSELECT_A::ALL_ZERO } - #[doc = "Checks if the value of the field is `ZERO_ONE`"] + #[doc = "The preamble is composed of '01's"] #[inline(always)] pub fn is_zero_one(&self) -> bool { *self == RX_PPSELECT_A::ZERO_ONE } - #[doc = "Checks if the value of the field is `ONE_ZERO`"] + #[doc = "The preamble is composed of '10's"] #[inline(always)] pub fn is_one_zero(&self) -> bool { *self == RX_PPSELECT_A::ONE_ZERO } } #[doc = "Field `RX_PP` writer - Receiver Preamble Pattern detected"] -pub type RX_PP_W<'a, const O: u8> = crate::FieldWriterSafe<'a, US_MAN_SPEC, 2, O, RX_PPSELECT_A>; -impl<'a, const O: u8> RX_PP_W<'a, O> { +pub type RX_PP_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, RX_PPSELECT_A>; +impl<'a, REG, const O: u8> RX_PP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The preamble is composed of '1's"] #[inline(always)] - pub fn all_one(self) -> &'a mut W { + pub fn all_one(self) -> &'a mut crate::W { self.variant(RX_PPSELECT_A::ALL_ONE) } #[doc = "The preamble is composed of '0's"] #[inline(always)] - pub fn all_zero(self) -> &'a mut W { + pub fn all_zero(self) -> &'a mut crate::W { self.variant(RX_PPSELECT_A::ALL_ZERO) } #[doc = "The preamble is composed of '01's"] #[inline(always)] - pub fn zero_one(self) -> &'a mut W { + pub fn zero_one(self) -> &'a mut crate::W { self.variant(RX_PPSELECT_A::ZERO_ONE) } #[doc = "The preamble is composed of '10's"] #[inline(always)] - pub fn one_zero(self) -> &'a mut W { + pub fn one_zero(self) -> &'a mut crate::W { self.variant(RX_PPSELECT_A::ONE_ZERO) } } #[doc = "Field `RX_MPOL` reader - Receiver Manchester Polarity"] pub type RX_MPOL_R = crate::BitReader; #[doc = "Field `RX_MPOL` writer - Receiver Manchester Polarity"] -pub type RX_MPOL_W<'a, const O: u8> = crate::BitWriter<'a, US_MAN_SPEC, O>; +pub type RX_MPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ONE` reader - Must Be Set to 1"] pub type ONE_R = crate::BitReader; #[doc = "Field `ONE` writer - Must Be Set to 1"] -pub type ONE_W<'a, const O: u8> = crate::BitWriter<'a, US_MAN_SPEC, O>; +pub type ONE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DRIFT` reader - Drift Compensation"] pub type DRIFT_R = crate::BitReader; #[doc = "Field `DRIFT` writer - Drift Compensation"] -pub type DRIFT_W<'a, const O: u8> = crate::BitWriter<'a, US_MAN_SPEC, O>; +pub type DRIFT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXIDLEV` reader - Receiver Idle Value"] pub type RXIDLEV_R = crate::BitReader; #[doc = "Field `RXIDLEV` writer - Receiver Idle Value"] -pub type RXIDLEV_W<'a, const O: u8> = crate::BitWriter<'a, US_MAN_SPEC, O>; +pub type RXIDLEV_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:3 - Transmitter Preamble Length"] #[inline(always)] @@ -275,76 +251,73 @@ impl W { #[doc = "Bits 0:3 - Transmitter Preamble Length"] #[inline(always)] #[must_use] - pub fn tx_pl(&mut self) -> TX_PL_W<0> { + pub fn tx_pl(&mut self) -> TX_PL_W { TX_PL_W::new(self) } #[doc = "Bits 8:9 - Transmitter Preamble Pattern"] #[inline(always)] #[must_use] - pub fn tx_pp(&mut self) -> TX_PP_W<8> { + pub fn tx_pp(&mut self) -> TX_PP_W { TX_PP_W::new(self) } #[doc = "Bit 12 - Transmitter Manchester Polarity"] #[inline(always)] #[must_use] - pub fn tx_mpol(&mut self) -> TX_MPOL_W<12> { + pub fn tx_mpol(&mut self) -> TX_MPOL_W { TX_MPOL_W::new(self) } #[doc = "Bits 16:19 - Receiver Preamble Length"] #[inline(always)] #[must_use] - pub fn rx_pl(&mut self) -> RX_PL_W<16> { + pub fn rx_pl(&mut self) -> RX_PL_W { RX_PL_W::new(self) } #[doc = "Bits 24:25 - Receiver Preamble Pattern detected"] #[inline(always)] #[must_use] - pub fn rx_pp(&mut self) -> RX_PP_W<24> { + pub fn rx_pp(&mut self) -> RX_PP_W { RX_PP_W::new(self) } #[doc = "Bit 28 - Receiver Manchester Polarity"] #[inline(always)] #[must_use] - pub fn rx_mpol(&mut self) -> RX_MPOL_W<28> { + pub fn rx_mpol(&mut self) -> RX_MPOL_W { RX_MPOL_W::new(self) } #[doc = "Bit 29 - Must Be Set to 1"] #[inline(always)] #[must_use] - pub fn one(&mut self) -> ONE_W<29> { + pub fn one(&mut self) -> ONE_W { ONE_W::new(self) } #[doc = "Bit 30 - Drift Compensation"] #[inline(always)] #[must_use] - pub fn drift(&mut self) -> DRIFT_W<30> { + pub fn drift(&mut self) -> DRIFT_W { DRIFT_W::new(self) } #[doc = "Bit 31 - Receiver Idle Value"] #[inline(always)] #[must_use] - pub fn rxidlev(&mut self) -> RXIDLEV_W<31> { + pub fn rxidlev(&mut self) -> RXIDLEV_W { RXIDLEV_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Manchester Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_man](index.html) module"] +#[doc = "Manchester Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_man::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_man::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_MAN_SPEC; impl crate::RegisterSpec for US_MAN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_man::R](R) reader structure"] -impl crate::Readable for US_MAN_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_man::W](W) writer structure"] +#[doc = "`read()` method returns [`us_man::R`](R) reader structure"] +impl crate::Readable for US_MAN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_man::W`](W) writer structure"] impl crate::Writable for US_MAN_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_spi_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_spi_mode.rs index 3e60f3fa..3f2850f8 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_spi_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_spi_mode.rs @@ -1,39 +1,7 @@ #[doc = "Register `US_MR_SPI_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_MR_SPI_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USART_MODE` reader - USART Mode of Operation"] pub type USART_MODE_R = crate::FieldReader; #[doc = "USART Mode of Operation\n\nValue on reset: 0"] @@ -94,129 +62,132 @@ impl USART_MODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "Normal mode"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == USART_MODESELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `RS485`"] + #[doc = "RS485"] #[inline(always)] pub fn is_rs485(&self) -> bool { *self == USART_MODESELECT_A::RS485 } - #[doc = "Checks if the value of the field is `HW_HANDSHAKING`"] + #[doc = "Hardware handshaking"] #[inline(always)] pub fn is_hw_handshaking(&self) -> bool { *self == USART_MODESELECT_A::HW_HANDSHAKING } - #[doc = "Checks if the value of the field is `MODEM`"] + #[doc = "Modem"] #[inline(always)] pub fn is_modem(&self) -> bool { *self == USART_MODESELECT_A::MODEM } - #[doc = "Checks if the value of the field is `IS07816_T_0`"] + #[doc = "IS07816 Protocol: T = 0"] #[inline(always)] pub fn is_is07816_t_0(&self) -> bool { *self == USART_MODESELECT_A::IS07816_T_0 } - #[doc = "Checks if the value of the field is `IS07816_T_1`"] + #[doc = "IS07816 Protocol: T = 1"] #[inline(always)] pub fn is_is07816_t_1(&self) -> bool { *self == USART_MODESELECT_A::IS07816_T_1 } - #[doc = "Checks if the value of the field is `IRDA`"] + #[doc = "IrDA"] #[inline(always)] pub fn is_irda(&self) -> bool { *self == USART_MODESELECT_A::IRDA } - #[doc = "Checks if the value of the field is `LON`"] + #[doc = "LON"] #[inline(always)] pub fn is_lon(&self) -> bool { *self == USART_MODESELECT_A::LON } - #[doc = "Checks if the value of the field is `LIN_MASTER`"] + #[doc = "LIN Master mode"] #[inline(always)] pub fn is_lin_master(&self) -> bool { *self == USART_MODESELECT_A::LIN_MASTER } - #[doc = "Checks if the value of the field is `LIN_SLAVE`"] + #[doc = "LIN Slave mode"] #[inline(always)] pub fn is_lin_slave(&self) -> bool { *self == USART_MODESELECT_A::LIN_SLAVE } - #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[doc = "SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)"] #[inline(always)] pub fn is_spi_master(&self) -> bool { *self == USART_MODESELECT_A::SPI_MASTER } - #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[doc = "SPI Slave mode"] #[inline(always)] pub fn is_spi_slave(&self) -> bool { *self == USART_MODESELECT_A::SPI_SLAVE } } #[doc = "Field `USART_MODE` writer - USART Mode of Operation"] -pub type USART_MODE_W<'a, const O: u8> = - crate::FieldWriter<'a, US_MR_SPI_MODE_SPEC, 4, O, USART_MODESELECT_A>; -impl<'a, const O: u8> USART_MODE_W<'a, O> { +pub type USART_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, USART_MODESELECT_A>; +impl<'a, REG, const O: u8> USART_MODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Normal mode"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::NORMAL) } #[doc = "RS485"] #[inline(always)] - pub fn rs485(self) -> &'a mut W { + pub fn rs485(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::RS485) } #[doc = "Hardware handshaking"] #[inline(always)] - pub fn hw_handshaking(self) -> &'a mut W { + pub fn hw_handshaking(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::HW_HANDSHAKING) } #[doc = "Modem"] #[inline(always)] - pub fn modem(self) -> &'a mut W { + pub fn modem(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::MODEM) } #[doc = "IS07816 Protocol: T = 0"] #[inline(always)] - pub fn is07816_t_0(self) -> &'a mut W { + pub fn is07816_t_0(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::IS07816_T_0) } #[doc = "IS07816 Protocol: T = 1"] #[inline(always)] - pub fn is07816_t_1(self) -> &'a mut W { + pub fn is07816_t_1(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::IS07816_T_1) } #[doc = "IrDA"] #[inline(always)] - pub fn irda(self) -> &'a mut W { + pub fn irda(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::IRDA) } #[doc = "LON"] #[inline(always)] - pub fn lon(self) -> &'a mut W { + pub fn lon(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::LON) } #[doc = "LIN Master mode"] #[inline(always)] - pub fn lin_master(self) -> &'a mut W { + pub fn lin_master(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::LIN_MASTER) } #[doc = "LIN Slave mode"] #[inline(always)] - pub fn lin_slave(self) -> &'a mut W { + pub fn lin_slave(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::LIN_SLAVE) } #[doc = "SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)"] #[inline(always)] - pub fn spi_master(self) -> &'a mut W { + pub fn spi_master(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::SPI_MASTER) } #[doc = "SPI Slave mode"] #[inline(always)] - pub fn spi_slave(self) -> &'a mut W { + pub fn spi_slave(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::SPI_SLAVE) } } @@ -256,49 +227,52 @@ impl USCLKS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `MCK`"] + #[doc = "Peripheral clock is selected"] #[inline(always)] pub fn is_mck(&self) -> bool { *self == USCLKSSELECT_A::MCK } - #[doc = "Checks if the value of the field is `DIV`"] + #[doc = "Peripheral clock divided (DIV = 8) is selected"] #[inline(always)] pub fn is_div(&self) -> bool { *self == USCLKSSELECT_A::DIV } - #[doc = "Checks if the value of the field is `PCK`"] + #[doc = "PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1."] #[inline(always)] pub fn is_pck(&self) -> bool { *self == USCLKSSELECT_A::PCK } - #[doc = "Checks if the value of the field is `SCK`"] + #[doc = "Serial clock (SCK) is selected"] #[inline(always)] pub fn is_sck(&self) -> bool { *self == USCLKSSELECT_A::SCK } } #[doc = "Field `USCLKS` writer - Clock Selection"] -pub type USCLKS_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, US_MR_SPI_MODE_SPEC, 2, O, USCLKSSELECT_A>; -impl<'a, const O: u8> USCLKS_W<'a, O> { +pub type USCLKS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, USCLKSSELECT_A>; +impl<'a, REG, const O: u8> USCLKS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Peripheral clock is selected"] #[inline(always)] - pub fn mck(self) -> &'a mut W { + pub fn mck(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::MCK) } #[doc = "Peripheral clock divided (DIV = 8) is selected"] #[inline(always)] - pub fn div(self) -> &'a mut W { + pub fn div(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::DIV) } #[doc = "PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1."] #[inline(always)] - pub fn pck(self) -> &'a mut W { + pub fn pck(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::PCK) } #[doc = "Serial clock (SCK) is selected"] #[inline(always)] - pub fn sck(self) -> &'a mut W { + pub fn sck(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::SCK) } } @@ -338,68 +312,71 @@ impl CHRL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_5_BIT`"] + #[doc = "Character length is 5 bits"] #[inline(always)] pub fn is_5_bit(&self) -> bool { *self == CHRLSELECT_A::_5_BIT } - #[doc = "Checks if the value of the field is `_6_BIT`"] + #[doc = "Character length is 6 bits"] #[inline(always)] pub fn is_6_bit(&self) -> bool { *self == CHRLSELECT_A::_6_BIT } - #[doc = "Checks if the value of the field is `_7_BIT`"] + #[doc = "Character length is 7 bits"] #[inline(always)] pub fn is_7_bit(&self) -> bool { *self == CHRLSELECT_A::_7_BIT } - #[doc = "Checks if the value of the field is `_8_BIT`"] + #[doc = "Character length is 8 bits"] #[inline(always)] pub fn is_8_bit(&self) -> bool { *self == CHRLSELECT_A::_8_BIT } } #[doc = "Field `CHRL` writer - Character Length"] -pub type CHRL_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, US_MR_SPI_MODE_SPEC, 2, O, CHRLSELECT_A>; -impl<'a, const O: u8> CHRL_W<'a, O> { +pub type CHRL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CHRLSELECT_A>; +impl<'a, REG, const O: u8> CHRL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Character length is 5 bits"] #[inline(always)] - pub fn _5_bit(self) -> &'a mut W { + pub fn _5_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_5_BIT) } #[doc = "Character length is 6 bits"] #[inline(always)] - pub fn _6_bit(self) -> &'a mut W { + pub fn _6_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_6_BIT) } #[doc = "Character length is 7 bits"] #[inline(always)] - pub fn _7_bit(self) -> &'a mut W { + pub fn _7_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_7_BIT) } #[doc = "Character length is 8 bits"] #[inline(always)] - pub fn _8_bit(self) -> &'a mut W { + pub fn _8_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_8_BIT) } } #[doc = "Field `CPHA` reader - SPI Clock Phase"] pub type CPHA_R = crate::BitReader; #[doc = "Field `CPHA` writer - SPI Clock Phase"] -pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_SPI_MODE_SPEC, O>; +pub type CPHA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CPOL` reader - SPI Clock Polarity"] pub type CPOL_R = crate::BitReader; #[doc = "Field `CPOL` writer - SPI Clock Polarity"] -pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_SPI_MODE_SPEC, O>; +pub type CPOL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLKO` reader - Clock Output Select"] pub type CLKO_R = crate::BitReader; #[doc = "Field `CLKO` writer - Clock Output Select"] -pub type CLKO_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_SPI_MODE_SPEC, O>; +pub type CLKO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WRDBT` reader - Wait Read Data Before Transfer"] pub type WRDBT_R = crate::BitReader; #[doc = "Field `WRDBT` writer - Wait Read Data Before Transfer"] -pub type WRDBT_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_SPI_MODE_SPEC, O>; +pub type WRDBT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:3 - USART Mode of Operation"] #[inline(always)] @@ -441,64 +418,61 @@ impl W { #[doc = "Bits 0:3 - USART Mode of Operation"] #[inline(always)] #[must_use] - pub fn usart_mode(&mut self) -> USART_MODE_W<0> { + pub fn usart_mode(&mut self) -> USART_MODE_W { USART_MODE_W::new(self) } #[doc = "Bits 4:5 - Clock Selection"] #[inline(always)] #[must_use] - pub fn usclks(&mut self) -> USCLKS_W<4> { + pub fn usclks(&mut self) -> USCLKS_W { USCLKS_W::new(self) } #[doc = "Bits 6:7 - Character Length"] #[inline(always)] #[must_use] - pub fn chrl(&mut self) -> CHRL_W<6> { + pub fn chrl(&mut self) -> CHRL_W { CHRL_W::new(self) } #[doc = "Bit 8 - SPI Clock Phase"] #[inline(always)] #[must_use] - pub fn cpha(&mut self) -> CPHA_W<8> { + pub fn cpha(&mut self) -> CPHA_W { CPHA_W::new(self) } #[doc = "Bit 16 - SPI Clock Polarity"] #[inline(always)] #[must_use] - pub fn cpol(&mut self) -> CPOL_W<16> { + pub fn cpol(&mut self) -> CPOL_W { CPOL_W::new(self) } #[doc = "Bit 18 - Clock Output Select"] #[inline(always)] #[must_use] - pub fn clko(&mut self) -> CLKO_W<18> { + pub fn clko(&mut self) -> CLKO_W { CLKO_W::new(self) } #[doc = "Bit 20 - Wait Read Data Before Transfer"] #[inline(always)] #[must_use] - pub fn wrdbt(&mut self) -> WRDBT_W<20> { + pub fn wrdbt(&mut self) -> WRDBT_W { WRDBT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_mr_spi_mode](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_mr_spi_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_mr_spi_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_MR_SPI_MODE_SPEC; impl crate::RegisterSpec for US_MR_SPI_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_mr_spi_mode::R](R) reader structure"] -impl crate::Readable for US_MR_SPI_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_mr_spi_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`us_mr_spi_mode::R`](R) reader structure"] +impl crate::Readable for US_MR_SPI_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_mr_spi_mode::W`](W) writer structure"] impl crate::Writable for US_MR_SPI_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_usart_mode.rs index 7c7c7ba5..c5a8e193 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_mr_usart_mode.rs @@ -1,39 +1,7 @@ #[doc = "Register `US_MR_USART_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_MR_USART_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `USART_MODE` reader - USART Mode of Operation"] pub type USART_MODE_R = crate::FieldReader; #[doc = "USART Mode of Operation\n\nValue on reset: 0"] @@ -94,129 +62,132 @@ impl USART_MODE_R { _ => None, } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "Normal mode"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == USART_MODESELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `RS485`"] + #[doc = "RS485"] #[inline(always)] pub fn is_rs485(&self) -> bool { *self == USART_MODESELECT_A::RS485 } - #[doc = "Checks if the value of the field is `HW_HANDSHAKING`"] + #[doc = "Hardware handshaking"] #[inline(always)] pub fn is_hw_handshaking(&self) -> bool { *self == USART_MODESELECT_A::HW_HANDSHAKING } - #[doc = "Checks if the value of the field is `MODEM`"] + #[doc = "Modem"] #[inline(always)] pub fn is_modem(&self) -> bool { *self == USART_MODESELECT_A::MODEM } - #[doc = "Checks if the value of the field is `IS07816_T_0`"] + #[doc = "IS07816 Protocol: T = 0"] #[inline(always)] pub fn is_is07816_t_0(&self) -> bool { *self == USART_MODESELECT_A::IS07816_T_0 } - #[doc = "Checks if the value of the field is `IS07816_T_1`"] + #[doc = "IS07816 Protocol: T = 1"] #[inline(always)] pub fn is_is07816_t_1(&self) -> bool { *self == USART_MODESELECT_A::IS07816_T_1 } - #[doc = "Checks if the value of the field is `IRDA`"] + #[doc = "IrDA"] #[inline(always)] pub fn is_irda(&self) -> bool { *self == USART_MODESELECT_A::IRDA } - #[doc = "Checks if the value of the field is `LON`"] + #[doc = "LON"] #[inline(always)] pub fn is_lon(&self) -> bool { *self == USART_MODESELECT_A::LON } - #[doc = "Checks if the value of the field is `LIN_MASTER`"] + #[doc = "LIN Master mode"] #[inline(always)] pub fn is_lin_master(&self) -> bool { *self == USART_MODESELECT_A::LIN_MASTER } - #[doc = "Checks if the value of the field is `LIN_SLAVE`"] + #[doc = "LIN Slave mode"] #[inline(always)] pub fn is_lin_slave(&self) -> bool { *self == USART_MODESELECT_A::LIN_SLAVE } - #[doc = "Checks if the value of the field is `SPI_MASTER`"] + #[doc = "SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)"] #[inline(always)] pub fn is_spi_master(&self) -> bool { *self == USART_MODESELECT_A::SPI_MASTER } - #[doc = "Checks if the value of the field is `SPI_SLAVE`"] + #[doc = "SPI Slave mode"] #[inline(always)] pub fn is_spi_slave(&self) -> bool { *self == USART_MODESELECT_A::SPI_SLAVE } } #[doc = "Field `USART_MODE` writer - USART Mode of Operation"] -pub type USART_MODE_W<'a, const O: u8> = - crate::FieldWriter<'a, US_MR_USART_MODE_SPEC, 4, O, USART_MODESELECT_A>; -impl<'a, const O: u8> USART_MODE_W<'a, O> { +pub type USART_MODE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O, USART_MODESELECT_A>; +impl<'a, REG, const O: u8> USART_MODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Normal mode"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::NORMAL) } #[doc = "RS485"] #[inline(always)] - pub fn rs485(self) -> &'a mut W { + pub fn rs485(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::RS485) } #[doc = "Hardware handshaking"] #[inline(always)] - pub fn hw_handshaking(self) -> &'a mut W { + pub fn hw_handshaking(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::HW_HANDSHAKING) } #[doc = "Modem"] #[inline(always)] - pub fn modem(self) -> &'a mut W { + pub fn modem(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::MODEM) } #[doc = "IS07816 Protocol: T = 0"] #[inline(always)] - pub fn is07816_t_0(self) -> &'a mut W { + pub fn is07816_t_0(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::IS07816_T_0) } #[doc = "IS07816 Protocol: T = 1"] #[inline(always)] - pub fn is07816_t_1(self) -> &'a mut W { + pub fn is07816_t_1(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::IS07816_T_1) } #[doc = "IrDA"] #[inline(always)] - pub fn irda(self) -> &'a mut W { + pub fn irda(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::IRDA) } #[doc = "LON"] #[inline(always)] - pub fn lon(self) -> &'a mut W { + pub fn lon(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::LON) } #[doc = "LIN Master mode"] #[inline(always)] - pub fn lin_master(self) -> &'a mut W { + pub fn lin_master(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::LIN_MASTER) } #[doc = "LIN Slave mode"] #[inline(always)] - pub fn lin_slave(self) -> &'a mut W { + pub fn lin_slave(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::LIN_SLAVE) } #[doc = "SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2)"] #[inline(always)] - pub fn spi_master(self) -> &'a mut W { + pub fn spi_master(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::SPI_MASTER) } #[doc = "SPI Slave mode"] #[inline(always)] - pub fn spi_slave(self) -> &'a mut W { + pub fn spi_slave(self) -> &'a mut crate::W { self.variant(USART_MODESELECT_A::SPI_SLAVE) } } @@ -256,49 +227,52 @@ impl USCLKS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `MCK`"] + #[doc = "Peripheral clock is selected"] #[inline(always)] pub fn is_mck(&self) -> bool { *self == USCLKSSELECT_A::MCK } - #[doc = "Checks if the value of the field is `DIV`"] + #[doc = "Peripheral clock divided (DIV = 8) is selected"] #[inline(always)] pub fn is_div(&self) -> bool { *self == USCLKSSELECT_A::DIV } - #[doc = "Checks if the value of the field is `PCK`"] + #[doc = "PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1."] #[inline(always)] pub fn is_pck(&self) -> bool { *self == USCLKSSELECT_A::PCK } - #[doc = "Checks if the value of the field is `SCK`"] + #[doc = "Serial clock (SCK) is selected"] #[inline(always)] pub fn is_sck(&self) -> bool { *self == USCLKSSELECT_A::SCK } } #[doc = "Field `USCLKS` writer - Clock Selection"] -pub type USCLKS_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, US_MR_USART_MODE_SPEC, 2, O, USCLKSSELECT_A>; -impl<'a, const O: u8> USCLKS_W<'a, O> { +pub type USCLKS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, USCLKSSELECT_A>; +impl<'a, REG, const O: u8> USCLKS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Peripheral clock is selected"] #[inline(always)] - pub fn mck(self) -> &'a mut W { + pub fn mck(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::MCK) } #[doc = "Peripheral clock divided (DIV = 8) is selected"] #[inline(always)] - pub fn div(self) -> &'a mut W { + pub fn div(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::DIV) } #[doc = "PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1."] #[inline(always)] - pub fn pck(self) -> &'a mut W { + pub fn pck(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::PCK) } #[doc = "Serial clock (SCK) is selected"] #[inline(always)] - pub fn sck(self) -> &'a mut W { + pub fn sck(self) -> &'a mut crate::W { self.variant(USCLKSSELECT_A::SCK) } } @@ -338,56 +312,59 @@ impl CHRL_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_5_BIT`"] + #[doc = "Character length is 5 bits"] #[inline(always)] pub fn is_5_bit(&self) -> bool { *self == CHRLSELECT_A::_5_BIT } - #[doc = "Checks if the value of the field is `_6_BIT`"] + #[doc = "Character length is 6 bits"] #[inline(always)] pub fn is_6_bit(&self) -> bool { *self == CHRLSELECT_A::_6_BIT } - #[doc = "Checks if the value of the field is `_7_BIT`"] + #[doc = "Character length is 7 bits"] #[inline(always)] pub fn is_7_bit(&self) -> bool { *self == CHRLSELECT_A::_7_BIT } - #[doc = "Checks if the value of the field is `_8_BIT`"] + #[doc = "Character length is 8 bits"] #[inline(always)] pub fn is_8_bit(&self) -> bool { *self == CHRLSELECT_A::_8_BIT } } #[doc = "Field `CHRL` writer - Character Length"] -pub type CHRL_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, US_MR_USART_MODE_SPEC, 2, O, CHRLSELECT_A>; -impl<'a, const O: u8> CHRL_W<'a, O> { +pub type CHRL_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CHRLSELECT_A>; +impl<'a, REG, const O: u8> CHRL_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Character length is 5 bits"] #[inline(always)] - pub fn _5_bit(self) -> &'a mut W { + pub fn _5_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_5_BIT) } #[doc = "Character length is 6 bits"] #[inline(always)] - pub fn _6_bit(self) -> &'a mut W { + pub fn _6_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_6_BIT) } #[doc = "Character length is 7 bits"] #[inline(always)] - pub fn _7_bit(self) -> &'a mut W { + pub fn _7_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_7_BIT) } #[doc = "Character length is 8 bits"] #[inline(always)] - pub fn _8_bit(self) -> &'a mut W { + pub fn _8_bit(self) -> &'a mut crate::W { self.variant(CHRLSELECT_A::_8_BIT) } } #[doc = "Field `SYNC` reader - Synchronous Mode Select"] pub type SYNC_R = crate::BitReader; #[doc = "Field `SYNC` writer - Synchronous Mode Select"] -pub type SYNC_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type SYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PAR` reader - Parity Type"] pub type PAR_R = crate::FieldReader; #[doc = "Parity Type\n\nValue on reset: 0"] @@ -430,68 +407,72 @@ impl PAR_R { _ => None, } } - #[doc = "Checks if the value of the field is `EVEN`"] + #[doc = "Even parity"] #[inline(always)] pub fn is_even(&self) -> bool { *self == PARSELECT_A::EVEN } - #[doc = "Checks if the value of the field is `ODD`"] + #[doc = "Odd parity"] #[inline(always)] pub fn is_odd(&self) -> bool { *self == PARSELECT_A::ODD } - #[doc = "Checks if the value of the field is `SPACE`"] + #[doc = "Parity forced to 0 (Space)"] #[inline(always)] pub fn is_space(&self) -> bool { *self == PARSELECT_A::SPACE } - #[doc = "Checks if the value of the field is `MARK`"] + #[doc = "Parity forced to 1 (Mark)"] #[inline(always)] pub fn is_mark(&self) -> bool { *self == PARSELECT_A::MARK } - #[doc = "Checks if the value of the field is `NO`"] + #[doc = "No parity"] #[inline(always)] pub fn is_no(&self) -> bool { *self == PARSELECT_A::NO } - #[doc = "Checks if the value of the field is `MULTIDROP`"] + #[doc = "Multidrop mode"] #[inline(always)] pub fn is_multidrop(&self) -> bool { *self == PARSELECT_A::MULTIDROP } } #[doc = "Field `PAR` writer - Parity Type"] -pub type PAR_W<'a, const O: u8> = crate::FieldWriter<'a, US_MR_USART_MODE_SPEC, 3, O, PARSELECT_A>; -impl<'a, const O: u8> PAR_W<'a, O> { +pub type PAR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, PARSELECT_A>; +impl<'a, REG, const O: u8> PAR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Even parity"] #[inline(always)] - pub fn even(self) -> &'a mut W { + pub fn even(self) -> &'a mut crate::W { self.variant(PARSELECT_A::EVEN) } #[doc = "Odd parity"] #[inline(always)] - pub fn odd(self) -> &'a mut W { + pub fn odd(self) -> &'a mut crate::W { self.variant(PARSELECT_A::ODD) } #[doc = "Parity forced to 0 (Space)"] #[inline(always)] - pub fn space(self) -> &'a mut W { + pub fn space(self) -> &'a mut crate::W { self.variant(PARSELECT_A::SPACE) } #[doc = "Parity forced to 1 (Mark)"] #[inline(always)] - pub fn mark(self) -> &'a mut W { + pub fn mark(self) -> &'a mut crate::W { self.variant(PARSELECT_A::MARK) } #[doc = "No parity"] #[inline(always)] - pub fn no(self) -> &'a mut W { + pub fn no(self) -> &'a mut crate::W { self.variant(PARSELECT_A::NO) } #[doc = "Multidrop mode"] #[inline(always)] - pub fn multidrop(self) -> &'a mut W { + pub fn multidrop(self) -> &'a mut crate::W { self.variant(PARSELECT_A::MULTIDROP) } } @@ -528,39 +509,42 @@ impl NBSTOP_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1_BIT`"] + #[doc = "1 stop bit"] #[inline(always)] pub fn is_1_bit(&self) -> bool { *self == NBSTOPSELECT_A::_1_BIT } - #[doc = "Checks if the value of the field is `_1_5_BIT`"] + #[doc = "1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)"] #[inline(always)] pub fn is_1_5_bit(&self) -> bool { *self == NBSTOPSELECT_A::_1_5_BIT } - #[doc = "Checks if the value of the field is `_2_BIT`"] + #[doc = "2 stop bits"] #[inline(always)] pub fn is_2_bit(&self) -> bool { *self == NBSTOPSELECT_A::_2_BIT } } #[doc = "Field `NBSTOP` writer - Number of Stop Bits"] -pub type NBSTOP_W<'a, const O: u8> = - crate::FieldWriter<'a, US_MR_USART_MODE_SPEC, 2, O, NBSTOPSELECT_A>; -impl<'a, const O: u8> NBSTOP_W<'a, O> { +pub type NBSTOP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, NBSTOPSELECT_A>; +impl<'a, REG, const O: u8> NBSTOP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "1 stop bit"] #[inline(always)] - pub fn _1_bit(self) -> &'a mut W { + pub fn _1_bit(self) -> &'a mut crate::W { self.variant(NBSTOPSELECT_A::_1_BIT) } #[doc = "1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)"] #[inline(always)] - pub fn _1_5_bit(self) -> &'a mut W { + pub fn _1_5_bit(self) -> &'a mut crate::W { self.variant(NBSTOPSELECT_A::_1_5_BIT) } #[doc = "2 stop bits"] #[inline(always)] - pub fn _2_bit(self) -> &'a mut W { + pub fn _2_bit(self) -> &'a mut crate::W { self.variant(NBSTOPSELECT_A::_2_BIT) } } @@ -600,104 +584,107 @@ impl CHMODE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "Normal mode"] #[inline(always)] pub fn is_normal(&self) -> bool { *self == CHMODESELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `AUTOMATIC`"] + #[doc = "Automatic Echo. Receiver input is connected to the TXD pin."] #[inline(always)] pub fn is_automatic(&self) -> bool { *self == CHMODESELECT_A::AUTOMATIC } - #[doc = "Checks if the value of the field is `LOCAL_LOOPBACK`"] + #[doc = "Local Loopback. Transmitter output is connected to the Receiver Input."] #[inline(always)] pub fn is_local_loopback(&self) -> bool { *self == CHMODESELECT_A::LOCAL_LOOPBACK } - #[doc = "Checks if the value of the field is `REMOTE_LOOPBACK`"] + #[doc = "Remote Loopback. RXD pin is internally connected to the TXD pin."] #[inline(always)] pub fn is_remote_loopback(&self) -> bool { *self == CHMODESELECT_A::REMOTE_LOOPBACK } } #[doc = "Field `CHMODE` writer - Channel Mode"] -pub type CHMODE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, US_MR_USART_MODE_SPEC, 2, O, CHMODESELECT_A>; -impl<'a, const O: u8> CHMODE_W<'a, O> { +pub type CHMODE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, CHMODESELECT_A>; +impl<'a, REG, const O: u8> CHMODE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Normal mode"] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::NORMAL) } #[doc = "Automatic Echo. Receiver input is connected to the TXD pin."] #[inline(always)] - pub fn automatic(self) -> &'a mut W { + pub fn automatic(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::AUTOMATIC) } #[doc = "Local Loopback. Transmitter output is connected to the Receiver Input."] #[inline(always)] - pub fn local_loopback(self) -> &'a mut W { + pub fn local_loopback(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::LOCAL_LOOPBACK) } #[doc = "Remote Loopback. RXD pin is internally connected to the TXD pin."] #[inline(always)] - pub fn remote_loopback(self) -> &'a mut W { + pub fn remote_loopback(self) -> &'a mut crate::W { self.variant(CHMODESELECT_A::REMOTE_LOOPBACK) } } #[doc = "Field `MSBF` reader - Bit Order"] pub type MSBF_R = crate::BitReader; #[doc = "Field `MSBF` writer - Bit Order"] -pub type MSBF_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type MSBF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODE9` reader - 9-bit Character Length"] pub type MODE9_R = crate::BitReader; #[doc = "Field `MODE9` writer - 9-bit Character Length"] -pub type MODE9_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type MODE9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CLKO` reader - Clock Output Select"] pub type CLKO_R = crate::BitReader; #[doc = "Field `CLKO` writer - Clock Output Select"] -pub type CLKO_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type CLKO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVER` reader - Oversampling Mode"] pub type OVER_R = crate::BitReader; #[doc = "Field `OVER` writer - Oversampling Mode"] -pub type OVER_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type OVER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INACK` reader - Inhibit Non Acknowledge"] pub type INACK_R = crate::BitReader; #[doc = "Field `INACK` writer - Inhibit Non Acknowledge"] -pub type INACK_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type INACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DSNACK` reader - Disable Successive NACK"] pub type DSNACK_R = crate::BitReader; #[doc = "Field `DSNACK` writer - Disable Successive NACK"] -pub type DSNACK_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type DSNACK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VAR_SYNC` reader - Variable Synchronization of Command/Data Sync Start Frame Delimiter"] pub type VAR_SYNC_R = crate::BitReader; #[doc = "Field `VAR_SYNC` writer - Variable Synchronization of Command/Data Sync Start Frame Delimiter"] -pub type VAR_SYNC_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type VAR_SYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `INVDATA` reader - Inverted Data"] pub type INVDATA_R = crate::BitReader; #[doc = "Field `INVDATA` writer - Inverted Data"] -pub type INVDATA_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type INVDATA_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MAX_ITERATION` reader - Maximum Number of Automatic Iteration"] pub type MAX_ITERATION_R = crate::FieldReader; #[doc = "Field `MAX_ITERATION` writer - Maximum Number of Automatic Iteration"] -pub type MAX_ITERATION_W<'a, const O: u8> = crate::FieldWriter<'a, US_MR_USART_MODE_SPEC, 3, O>; +pub type MAX_ITERATION_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `FILTER` reader - Receive Line Filter"] pub type FILTER_R = crate::BitReader; #[doc = "Field `FILTER` writer - Receive Line Filter"] -pub type FILTER_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type FILTER_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MAN` reader - Manchester Encoder/Decoder Enable"] pub type MAN_R = crate::BitReader; #[doc = "Field `MAN` writer - Manchester Encoder/Decoder Enable"] -pub type MAN_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type MAN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MODSYNC` reader - Manchester Synchronization Mode"] pub type MODSYNC_R = crate::BitReader; #[doc = "Field `MODSYNC` writer - Manchester Synchronization Mode"] -pub type MODSYNC_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type MODSYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ONEBIT` reader - Start Frame Delimiter Selector"] pub type ONEBIT_R = crate::BitReader; #[doc = "Field `ONEBIT` writer - Start Frame Delimiter Selector"] -pub type ONEBIT_W<'a, const O: u8> = crate::BitWriter<'a, US_MR_USART_MODE_SPEC, O>; +pub type ONEBIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:3 - USART Mode of Operation"] #[inline(always)] @@ -804,142 +791,139 @@ impl W { #[doc = "Bits 0:3 - USART Mode of Operation"] #[inline(always)] #[must_use] - pub fn usart_mode(&mut self) -> USART_MODE_W<0> { + pub fn usart_mode(&mut self) -> USART_MODE_W { USART_MODE_W::new(self) } #[doc = "Bits 4:5 - Clock Selection"] #[inline(always)] #[must_use] - pub fn usclks(&mut self) -> USCLKS_W<4> { + pub fn usclks(&mut self) -> USCLKS_W { USCLKS_W::new(self) } #[doc = "Bits 6:7 - Character Length"] #[inline(always)] #[must_use] - pub fn chrl(&mut self) -> CHRL_W<6> { + pub fn chrl(&mut self) -> CHRL_W { CHRL_W::new(self) } #[doc = "Bit 8 - Synchronous Mode Select"] #[inline(always)] #[must_use] - pub fn sync(&mut self) -> SYNC_W<8> { + pub fn sync(&mut self) -> SYNC_W { SYNC_W::new(self) } #[doc = "Bits 9:11 - Parity Type"] #[inline(always)] #[must_use] - pub fn par(&mut self) -> PAR_W<9> { + pub fn par(&mut self) -> PAR_W { PAR_W::new(self) } #[doc = "Bits 12:13 - Number of Stop Bits"] #[inline(always)] #[must_use] - pub fn nbstop(&mut self) -> NBSTOP_W<12> { + pub fn nbstop(&mut self) -> NBSTOP_W { NBSTOP_W::new(self) } #[doc = "Bits 14:15 - Channel Mode"] #[inline(always)] #[must_use] - pub fn chmode(&mut self) -> CHMODE_W<14> { + pub fn chmode(&mut self) -> CHMODE_W { CHMODE_W::new(self) } #[doc = "Bit 16 - Bit Order"] #[inline(always)] #[must_use] - pub fn msbf(&mut self) -> MSBF_W<16> { + pub fn msbf(&mut self) -> MSBF_W { MSBF_W::new(self) } #[doc = "Bit 17 - 9-bit Character Length"] #[inline(always)] #[must_use] - pub fn mode9(&mut self) -> MODE9_W<17> { + pub fn mode9(&mut self) -> MODE9_W { MODE9_W::new(self) } #[doc = "Bit 18 - Clock Output Select"] #[inline(always)] #[must_use] - pub fn clko(&mut self) -> CLKO_W<18> { + pub fn clko(&mut self) -> CLKO_W { CLKO_W::new(self) } #[doc = "Bit 19 - Oversampling Mode"] #[inline(always)] #[must_use] - pub fn over(&mut self) -> OVER_W<19> { + pub fn over(&mut self) -> OVER_W { OVER_W::new(self) } #[doc = "Bit 20 - Inhibit Non Acknowledge"] #[inline(always)] #[must_use] - pub fn inack(&mut self) -> INACK_W<20> { + pub fn inack(&mut self) -> INACK_W { INACK_W::new(self) } #[doc = "Bit 21 - Disable Successive NACK"] #[inline(always)] #[must_use] - pub fn dsnack(&mut self) -> DSNACK_W<21> { + pub fn dsnack(&mut self) -> DSNACK_W { DSNACK_W::new(self) } #[doc = "Bit 22 - Variable Synchronization of Command/Data Sync Start Frame Delimiter"] #[inline(always)] #[must_use] - pub fn var_sync(&mut self) -> VAR_SYNC_W<22> { + pub fn var_sync(&mut self) -> VAR_SYNC_W { VAR_SYNC_W::new(self) } #[doc = "Bit 23 - Inverted Data"] #[inline(always)] #[must_use] - pub fn invdata(&mut self) -> INVDATA_W<23> { + pub fn invdata(&mut self) -> INVDATA_W { INVDATA_W::new(self) } #[doc = "Bits 24:26 - Maximum Number of Automatic Iteration"] #[inline(always)] #[must_use] - pub fn max_iteration(&mut self) -> MAX_ITERATION_W<24> { + pub fn max_iteration(&mut self) -> MAX_ITERATION_W { MAX_ITERATION_W::new(self) } #[doc = "Bit 28 - Receive Line Filter"] #[inline(always)] #[must_use] - pub fn filter(&mut self) -> FILTER_W<28> { + pub fn filter(&mut self) -> FILTER_W { FILTER_W::new(self) } #[doc = "Bit 29 - Manchester Encoder/Decoder Enable"] #[inline(always)] #[must_use] - pub fn man(&mut self) -> MAN_W<29> { + pub fn man(&mut self) -> MAN_W { MAN_W::new(self) } #[doc = "Bit 30 - Manchester Synchronization Mode"] #[inline(always)] #[must_use] - pub fn modsync(&mut self) -> MODSYNC_W<30> { + pub fn modsync(&mut self) -> MODSYNC_W { MODSYNC_W::new(self) } #[doc = "Bit 31 - Start Frame Delimiter Selector"] #[inline(always)] #[must_use] - pub fn onebit(&mut self) -> ONEBIT_W<31> { + pub fn onebit(&mut self) -> ONEBIT_W { ONEBIT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_mr_usart_mode](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_mr_usart_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_mr_usart_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_MR_USART_MODE_SPEC; impl crate::RegisterSpec for US_MR_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_mr_usart_mode::R](R) reader structure"] -impl crate::Readable for US_MR_USART_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_mr_usart_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`us_mr_usart_mode::R`](R) reader structure"] +impl crate::Readable for US_MR_USART_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_mr_usart_mode::W`](W) writer structure"] impl crate::Writable for US_MR_USART_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ner.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ner.rs index 5491fc75..70c9f5b9 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ner.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ner.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_NER` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NB_ERRORS` reader - Number of Errors"] pub type NB_ERRORS_R = crate::FieldReader; impl R { @@ -22,15 +9,13 @@ impl R { NB_ERRORS_R::new((self.bits & 0xff) as u8) } } -#[doc = "Number of Errors Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ner](index.html) module"] +#[doc = "Number of Errors Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_ner::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_NER_SPEC; impl crate::RegisterSpec for US_NER_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_ner::R](R) reader structure"] -impl crate::Readable for US_NER_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_ner::R`](R) reader structure"] +impl crate::Readable for US_NER_SPEC {} #[doc = "`reset()` method sets US_NER to value 0"] impl crate::Resettable for US_NER_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_rhr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_rhr.rs index 9ca9c4fe..8764d73a 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_rhr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_rhr.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_RHR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXCHR` reader - Received Character"] pub type RXCHR_R = crate::FieldReader; #[doc = "Field `RXSYNH` reader - Received Sync"] @@ -29,15 +16,13 @@ impl R { RXSYNH_R::new(((self.bits >> 15) & 1) != 0) } } -#[doc = "Receive Holding Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_rhr](index.html) module"] +#[doc = "Receive Holding Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_rhr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_RHR_SPEC; impl crate::RegisterSpec for US_RHR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_rhr::R](R) reader structure"] -impl crate::Readable for US_RHR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_rhr::R`](R) reader structure"] +impl crate::Readable for US_RHR_SPEC {} #[doc = "`reset()` method sets US_RHR to value 0"] impl crate::Resettable for US_RHR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_rtor.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_rtor.rs index 7dedb432..02f3fd2f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_rtor.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_rtor.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_RTOR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_RTOR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TO` reader - Timeout Value"] pub type TO_R = crate::FieldReader; #[doc = "Field `TO` writer - Timeout Value"] -pub type TO_W<'a, const O: u8> = crate::FieldWriter<'a, US_RTOR_SPEC, 17, O, u32>; +pub type TO_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 17, O, u32>; impl R { #[doc = "Bits 0:16 - Timeout Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:16 - Timeout Value"] #[inline(always)] #[must_use] - pub fn to(&mut self) -> TO_W<0> { + pub fn to(&mut self) -> TO_W { TO_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Receiver Timeout Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_rtor](index.html) module"] +#[doc = "Receiver Timeout Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_rtor::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_rtor::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_RTOR_SPEC; impl crate::RegisterSpec for US_RTOR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_rtor::R](R) reader structure"] -impl crate::Readable for US_RTOR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_rtor::W](W) writer structure"] +#[doc = "`read()` method returns [`us_rtor::R`](R) reader structure"] +impl crate::Readable for US_RTOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_rtor::W`](W) writer structure"] impl crate::Writable for US_RTOR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_thr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_thr.rs index dc59f3d1..3f9cceb5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_thr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_thr.rs @@ -1,56 +1,36 @@ #[doc = "Register `US_THR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXCHR` writer - Character to be Transmitted"] -pub type TXCHR_W<'a, const O: u8> = crate::FieldWriter<'a, US_THR_SPEC, 9, O, u16>; +pub type TXCHR_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 9, O, u16>; #[doc = "Field `TXSYNH` writer - Sync Field to be Transmitted"] -pub type TXSYNH_W<'a, const O: u8> = crate::BitWriter<'a, US_THR_SPEC, O>; +pub type TXSYNH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bits 0:8 - Character to be Transmitted"] #[inline(always)] #[must_use] - pub fn txchr(&mut self) -> TXCHR_W<0> { + pub fn txchr(&mut self) -> TXCHR_W { TXCHR_W::new(self) } #[doc = "Bit 15 - Sync Field to be Transmitted"] #[inline(always)] #[must_use] - pub fn txsynh(&mut self) -> TXSYNH_W<15> { + pub fn txsynh(&mut self) -> TXSYNH_W { TXSYNH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmit Holding Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_thr](index.html) module"] +#[doc = "Transmit Holding Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_thr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_THR_SPEC; impl crate::RegisterSpec for US_THR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [us_thr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`us_thr::W`](W) writer structure"] impl crate::Writable for US_THR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_lon_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_lon_mode.rs index 07064e72..b2f7a5c2 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_lon_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_lon_mode.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_TTGR_LON_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_TTGR_LON_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PCYCLE` reader - LON PCYCLE Length"] pub type PCYCLE_R = crate::FieldReader; #[doc = "Field `PCYCLE` writer - LON PCYCLE Length"] -pub type PCYCLE_W<'a, const O: u8> = crate::FieldWriter<'a, US_TTGR_LON_MODE_SPEC, 24, O, u32>; +pub type PCYCLE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - LON PCYCLE Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - LON PCYCLE Length"] #[inline(always)] #[must_use] - pub fn pcycle(&mut self) -> PCYCLE_W<0> { + pub fn pcycle(&mut self) -> PCYCLE_W { PCYCLE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmitter Timeguard Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ttgr_lon_mode](index.html) module"] +#[doc = "Transmitter Timeguard Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_ttgr_lon_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ttgr_lon_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_TTGR_LON_MODE_SPEC; impl crate::RegisterSpec for US_TTGR_LON_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_ttgr_lon_mode::R](R) reader structure"] -impl crate::Readable for US_TTGR_LON_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_ttgr_lon_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`us_ttgr_lon_mode::R`](R) reader structure"] +impl crate::Readable for US_TTGR_LON_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_ttgr_lon_mode::W`](W) writer structure"] impl crate::Writable for US_TTGR_LON_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_usart_mode.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_usart_mode.rs index e73c1c12..d2eda812 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_usart_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_ttgr_usart_mode.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_TTGR_USART_MODE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_TTGR_USART_MODE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TG` reader - Timeguard Value"] pub type TG_R = crate::FieldReader; #[doc = "Field `TG` writer - Timeguard Value"] -pub type TG_W<'a, const O: u8> = crate::FieldWriter<'a, US_TTGR_USART_MODE_SPEC, 8, O>; +pub type TG_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:7 - Timeguard Value"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:7 - Timeguard Value"] #[inline(always)] #[must_use] - pub fn tg(&mut self) -> TG_W<0> { + pub fn tg(&mut self) -> TG_W { TG_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Transmitter Timeguard Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_ttgr_usart_mode](index.html) module"] +#[doc = "Transmitter Timeguard Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_ttgr_usart_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_ttgr_usart_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_TTGR_USART_MODE_SPEC; impl crate::RegisterSpec for US_TTGR_USART_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_ttgr_usart_mode::R](R) reader structure"] -impl crate::Readable for US_TTGR_USART_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_ttgr_usart_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`us_ttgr_usart_mode::R`](R) reader structure"] +impl crate::Readable for US_TTGR_USART_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_ttgr_usart_mode::W`](W) writer structure"] impl crate::Writable for US_TTGR_USART_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_wpmr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_wpmr.rs index b42c54b4..025524d5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_wpmr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_wpmr.rs @@ -1,43 +1,11 @@ #[doc = "Register `US_WPMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `US_WPMR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WPEN` reader - Write Protection Enable"] pub type WPEN_R = crate::BitReader; #[doc = "Field `WPEN` writer - Write Protection Enable"] -pub type WPEN_W<'a, const O: u8> = crate::BitWriter<'a, US_WPMR_SPEC, O>; +pub type WPEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WPKEY` reader - Write Protection Key"] pub type WPKEY_R = crate::FieldReader; #[doc = "Write Protection Key\n\nValue on reset: 0"] @@ -65,18 +33,22 @@ impl WPKEY_R { _ => None, } } - #[doc = "Checks if the value of the field is `PASSWD`"] + #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] pub fn is_passwd(&self) -> bool { *self == WPKEYSELECT_A::PASSWD } } #[doc = "Field `WPKEY` writer - Write Protection Key"] -pub type WPKEY_W<'a, const O: u8> = crate::FieldWriter<'a, US_WPMR_SPEC, 24, O, WPKEYSELECT_A>; -impl<'a, const O: u8> WPKEY_W<'a, O> { +pub type WPKEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, WPKEYSELECT_A>; +impl<'a, REG, const O: u8> WPKEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(WPKEYSELECT_A::PASSWD) } } @@ -96,34 +68,31 @@ impl W { #[doc = "Bit 0 - Write Protection Enable"] #[inline(always)] #[must_use] - pub fn wpen(&mut self) -> WPEN_W<0> { + pub fn wpen(&mut self) -> WPEN_W { WPEN_W::new(self) } #[doc = "Bits 8:31 - Write Protection Key"] #[inline(always)] #[must_use] - pub fn wpkey(&mut self) -> WPKEY_W<8> { + pub fn wpkey(&mut self) -> WPKEY_W { WPKEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Write Protection Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_wpmr](index.html) module"] +#[doc = "Write Protection Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_wpmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`us_wpmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_WPMR_SPEC; impl crate::RegisterSpec for US_WPMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_wpmr::R](R) reader structure"] -impl crate::Readable for US_WPMR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [us_wpmr::W](W) writer structure"] +#[doc = "`read()` method returns [`us_wpmr::R`](R) reader structure"] +impl crate::Readable for US_WPMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`us_wpmr::W`](W) writer structure"] impl crate::Writable for US_WPMR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usart0/us_wpsr.rs b/arch/cortex-m/samv71q21-pac/src/usart0/us_wpsr.rs index e54aa110..1baa759d 100644 --- a/arch/cortex-m/samv71q21-pac/src/usart0/us_wpsr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usart0/us_wpsr.rs @@ -1,18 +1,5 @@ #[doc = "Register `US_WPSR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WPVS` reader - Write Protection Violation Status"] pub type WPVS_R = crate::BitReader; #[doc = "Field `WPVSRC` reader - Write Protection Violation Source"] @@ -29,15 +16,13 @@ impl R { WPVSRC_R::new(((self.bits >> 8) & 0xffff) as u16) } } -#[doc = "Write Protection Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [us_wpsr](index.html) module"] +#[doc = "Write Protection Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`us_wpsr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct US_WPSR_SPEC; impl crate::RegisterSpec for US_WPSR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [us_wpsr::R](R) reader structure"] -impl crate::Readable for US_WPSR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`us_wpsr::R`](R) reader structure"] +impl crate::Readable for US_WPSR_SPEC {} #[doc = "`reset()` method sets US_WPSR to value 0"] impl crate::Resettable for US_WPSR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs.rs b/arch/cortex-m/samv71q21-pac/src/usbhs.rs index b34e7b82..1f9bbdbb 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs.rs @@ -347,139 +347,173 @@ impl RegisterBlock { unsafe { &*(self as *const Self).cast::().add(1568usize).cast() } } } -#[doc = "DEVCTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVCTRL (rw) register accessor: Device General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devctrl`] +module"] pub type DEVCTRL = crate::Reg; #[doc = "Device General Control Register"] pub mod devctrl; -#[doc = "DEVISR (r) register accessor: an alias for `Reg`"] +#[doc = "DEVISR (r) register accessor: Device Global Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devisr`] +module"] pub type DEVISR = crate::Reg; #[doc = "Device Global Interrupt Status Register"] pub mod devisr; -#[doc = "DEVICR (w) register accessor: an alias for `Reg`"] +#[doc = "DEVICR (w) register accessor: Device Global Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devicr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devicr`] +module"] pub type DEVICR = crate::Reg; #[doc = "Device Global Interrupt Clear Register"] pub mod devicr; -#[doc = "DEVIFR (w) register accessor: an alias for `Reg`"] +#[doc = "DEVIFR (w) register accessor: Device Global Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devifr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devifr`] +module"] pub type DEVIFR = crate::Reg; #[doc = "Device Global Interrupt Set Register"] pub mod devifr; -#[doc = "DEVIMR (r) register accessor: an alias for `Reg`"] +#[doc = "DEVIMR (r) register accessor: Device Global Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devimr`] +module"] pub type DEVIMR = crate::Reg; #[doc = "Device Global Interrupt Mask Register"] pub mod devimr; -#[doc = "DEVIDR (w) register accessor: an alias for `Reg`"] +#[doc = "DEVIDR (w) register accessor: Device Global Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devidr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devidr`] +module"] pub type DEVIDR = crate::Reg; #[doc = "Device Global Interrupt Disable Register"] pub mod devidr; -#[doc = "DEVIER (w) register accessor: an alias for `Reg`"] +#[doc = "DEVIER (w) register accessor: Device Global Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devier`] +module"] pub type DEVIER = crate::Reg; #[doc = "Device Global Interrupt Enable Register"] pub mod devier; -#[doc = "DEVEPT (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVEPT (rw) register accessor: Device Endpoint Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devept::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devept::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devept`] +module"] pub type DEVEPT = crate::Reg; #[doc = "Device Endpoint Register"] pub mod devept; -#[doc = "DEVFNUM (r) register accessor: an alias for `Reg`"] +#[doc = "DEVFNUM (r) register accessor: Device Frame Number Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devfnum::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devfnum`] +module"] pub type DEVFNUM = crate::Reg; #[doc = "Device Frame Number Register"] pub mod devfnum; -#[doc = "DEVEPTCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTCFG (rw) register accessor: Device Endpoint Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptcfg`] +module"] pub type DEVEPTCFG = crate::Reg; #[doc = "Device Endpoint Configuration Register"] pub mod deveptcfg; -#[doc = "DEVEPTISR_CTRL_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTISR_CTRL_MODE (r) register accessor: Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_ctrl_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptisr_ctrl_mode`] +module"] pub type DEVEPTISR_CTRL_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Status Register"] pub mod deveptisr_ctrl_mode; -#[doc = "DEVEPTISR_ISO_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTISR_ISO_MODE (r) register accessor: Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_iso_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptisr_iso_mode`] +module"] pub type DEVEPTISR_ISO_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Status Register"] pub mod deveptisr_iso_mode; -#[doc = "DEVEPTISR_BLK_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTISR_BLK_MODE (r) register accessor: Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_blk_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptisr_blk_mode`] +module"] pub type DEVEPTISR_BLK_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Status Register"] pub mod deveptisr_blk_mode; -#[doc = "DEVEPTISR_INTRPT_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTISR_INTRPT_MODE (r) register accessor: Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_intrpt_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptisr_intrpt_mode`] +module"] pub type DEVEPTISR_INTRPT_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Status Register"] pub mod deveptisr_intrpt_mode; -#[doc = "DEVEPTICR_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTICR_CTRL_MODE (w) register accessor: Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devepticr_ctrl_mode`] +module"] pub type DEVEPTICR_CTRL_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Clear Register"] pub mod devepticr_ctrl_mode; -#[doc = "DEVEPTICR_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTICR_ISO_MODE (w) register accessor: Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devepticr_iso_mode`] +module"] pub type DEVEPTICR_ISO_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Clear Register"] pub mod devepticr_iso_mode; -#[doc = "DEVEPTICR_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTICR_BLK_MODE (w) register accessor: Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devepticr_blk_mode`] +module"] pub type DEVEPTICR_BLK_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Clear Register"] pub mod devepticr_blk_mode; -#[doc = "DEVEPTICR_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTICR_INTRPT_MODE (w) register accessor: Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devepticr_intrpt_mode`] +module"] pub type DEVEPTICR_INTRPT_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Clear Register"] pub mod devepticr_intrpt_mode; -#[doc = "DEVEPTIFR_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIFR_CTRL_MODE (w) register accessor: Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptifr_ctrl_mode`] +module"] pub type DEVEPTIFR_CTRL_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Set Register"] pub mod deveptifr_ctrl_mode; -#[doc = "DEVEPTIFR_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIFR_ISO_MODE (w) register accessor: Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptifr_iso_mode`] +module"] pub type DEVEPTIFR_ISO_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Set Register"] pub mod deveptifr_iso_mode; -#[doc = "DEVEPTIFR_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIFR_BLK_MODE (w) register accessor: Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptifr_blk_mode`] +module"] pub type DEVEPTIFR_BLK_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Set Register"] pub mod deveptifr_blk_mode; -#[doc = "DEVEPTIFR_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIFR_INTRPT_MODE (w) register accessor: Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptifr_intrpt_mode`] +module"] pub type DEVEPTIFR_INTRPT_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Set Register"] pub mod deveptifr_intrpt_mode; -#[doc = "DEVEPTIMR_CTRL_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIMR_CTRL_MODE (r) register accessor: Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_ctrl_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptimr_ctrl_mode`] +module"] pub type DEVEPTIMR_CTRL_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Mask Register"] pub mod deveptimr_ctrl_mode; -#[doc = "DEVEPTIMR_ISO_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIMR_ISO_MODE (r) register accessor: Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_iso_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptimr_iso_mode`] +module"] pub type DEVEPTIMR_ISO_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Mask Register"] pub mod deveptimr_iso_mode; -#[doc = "DEVEPTIMR_BLK_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIMR_BLK_MODE (r) register accessor: Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_blk_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptimr_blk_mode`] +module"] pub type DEVEPTIMR_BLK_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Mask Register"] pub mod deveptimr_blk_mode; -#[doc = "DEVEPTIMR_INTRPT_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIMR_INTRPT_MODE (r) register accessor: Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_intrpt_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptimr_intrpt_mode`] +module"] pub type DEVEPTIMR_INTRPT_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Mask Register"] pub mod deveptimr_intrpt_mode; -#[doc = "DEVEPTIER_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIER_CTRL_MODE (w) register accessor: Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptier_ctrl_mode`] +module"] pub type DEVEPTIER_CTRL_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Enable Register"] pub mod deveptier_ctrl_mode; -#[doc = "DEVEPTIER_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIER_ISO_MODE (w) register accessor: Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptier_iso_mode`] +module"] pub type DEVEPTIER_ISO_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Enable Register"] pub mod deveptier_iso_mode; -#[doc = "DEVEPTIER_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIER_BLK_MODE (w) register accessor: Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptier_blk_mode`] +module"] pub type DEVEPTIER_BLK_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Enable Register"] pub mod deveptier_blk_mode; -#[doc = "DEVEPTIER_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIER_INTRPT_MODE (w) register accessor: Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptier_intrpt_mode`] +module"] pub type DEVEPTIER_INTRPT_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Enable Register"] pub mod deveptier_intrpt_mode; -#[doc = "DEVEPTIDR_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIDR_CTRL_MODE (w) register accessor: Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptidr_ctrl_mode`] +module"] pub type DEVEPTIDR_CTRL_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Disable Register"] pub mod deveptidr_ctrl_mode; -#[doc = "DEVEPTIDR_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIDR_ISO_MODE (w) register accessor: Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptidr_iso_mode`] +module"] pub type DEVEPTIDR_ISO_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Disable Register"] pub mod deveptidr_iso_mode; -#[doc = "DEVEPTIDR_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIDR_BLK_MODE (w) register accessor: Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptidr_blk_mode`] +module"] pub type DEVEPTIDR_BLK_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Disable Register"] pub mod deveptidr_blk_mode; -#[doc = "DEVEPTIDR_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "DEVEPTIDR_INTRPT_MODE (w) register accessor: Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`deveptidr_intrpt_mode`] +module"] pub type DEVEPTIDR_INTRPT_MODE = crate::Reg; #[doc = "Device Endpoint Interrupt Disable Register"] pub mod deveptidr_intrpt_mode; @@ -488,164 +522,204 @@ pub use self::usbhs_devdma::USBHS_DEVDMA; #[doc = r"Cluster"] #[doc = "Device DMA Channel Next Descriptor Address Register"] pub mod usbhs_devdma; -#[doc = "HSTCTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTCTRL (rw) register accessor: Host General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstctrl`] +module"] pub type HSTCTRL = crate::Reg; #[doc = "Host General Control Register"] pub mod hstctrl; -#[doc = "HSTISR (r) register accessor: an alias for `Reg`"] +#[doc = "HSTISR (r) register accessor: Host Global Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstisr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstisr`] +module"] pub type HSTISR = crate::Reg; #[doc = "Host Global Interrupt Status Register"] pub mod hstisr; -#[doc = "HSTICR (w) register accessor: an alias for `Reg`"] +#[doc = "HSTICR (w) register accessor: Host Global Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hsticr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hsticr`] +module"] pub type HSTICR = crate::Reg; #[doc = "Host Global Interrupt Clear Register"] pub mod hsticr; -#[doc = "HSTIFR (w) register accessor: an alias for `Reg`"] +#[doc = "HSTIFR (w) register accessor: Host Global Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstifr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstifr`] +module"] pub type HSTIFR = crate::Reg; #[doc = "Host Global Interrupt Set Register"] pub mod hstifr; -#[doc = "HSTIMR (r) register accessor: an alias for `Reg`"] +#[doc = "HSTIMR (r) register accessor: Host Global Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstimr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstimr`] +module"] pub type HSTIMR = crate::Reg; #[doc = "Host Global Interrupt Mask Register"] pub mod hstimr; -#[doc = "HSTIDR (w) register accessor: an alias for `Reg`"] +#[doc = "HSTIDR (w) register accessor: Host Global Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstidr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstidr`] +module"] pub type HSTIDR = crate::Reg; #[doc = "Host Global Interrupt Disable Register"] pub mod hstidr; -#[doc = "HSTIER (w) register accessor: an alias for `Reg`"] +#[doc = "HSTIER (w) register accessor: Host Global Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstier::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstier`] +module"] pub type HSTIER = crate::Reg; #[doc = "Host Global Interrupt Enable Register"] pub mod hstier; -#[doc = "HSTPIP (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTPIP (rw) register accessor: Host Pipe Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpip::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpip::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpip`] +module"] pub type HSTPIP = crate::Reg; #[doc = "Host Pipe Register"] pub mod hstpip; -#[doc = "HSTFNUM (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTFNUM (rw) register accessor: Host Frame Number Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstfnum::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstfnum::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstfnum`] +module"] pub type HSTFNUM = crate::Reg; #[doc = "Host Frame Number Register"] pub mod hstfnum; -#[doc = "HSTADDR1 (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTADDR1 (rw) register accessor: Host Address 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstaddr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstaddr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstaddr1`] +module"] pub type HSTADDR1 = crate::Reg; #[doc = "Host Address 1 Register"] pub mod hstaddr1; -#[doc = "HSTADDR2 (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTADDR2 (rw) register accessor: Host Address 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstaddr2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstaddr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstaddr2`] +module"] pub type HSTADDR2 = crate::Reg; #[doc = "Host Address 2 Register"] pub mod hstaddr2; -#[doc = "HSTADDR3 (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTADDR3 (rw) register accessor: Host Address 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstaddr3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstaddr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstaddr3`] +module"] pub type HSTADDR3 = crate::Reg; #[doc = "Host Address 3 Register"] pub mod hstaddr3; -#[doc = "HSTPIPCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPCFG (rw) register accessor: Host Pipe Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipcfg`] +module"] pub type HSTPIPCFG = crate::Reg; #[doc = "Host Pipe Configuration Register"] pub mod hstpipcfg; -#[doc = "HSTPIPCFG_CTRL_BULK_MODE (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPCFG_CTRL_BULK_MODE (rw) register accessor: Host Pipe Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipcfg_ctrl_bulk_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipcfg_ctrl_bulk_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipcfg_ctrl_bulk_mode`] +module"] pub type HSTPIPCFG_CTRL_BULK_MODE = crate::Reg; #[doc = "Host Pipe Configuration Register"] pub mod hstpipcfg_ctrl_bulk_mode; -#[doc = "HSTPIPISR_CTRL_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPISR_CTRL_MODE (r) register accessor: Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_ctrl_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipisr_ctrl_mode`] +module"] pub type HSTPIPISR_CTRL_MODE = crate::Reg; #[doc = "Host Pipe Status Register"] pub mod hstpipisr_ctrl_mode; -#[doc = "HSTPIPISR_ISO_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPISR_ISO_MODE (r) register accessor: Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_iso_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipisr_iso_mode`] +module"] pub type HSTPIPISR_ISO_MODE = crate::Reg; #[doc = "Host Pipe Status Register"] pub mod hstpipisr_iso_mode; -#[doc = "HSTPIPISR_BLK_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPISR_BLK_MODE (r) register accessor: Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_blk_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipisr_blk_mode`] +module"] pub type HSTPIPISR_BLK_MODE = crate::Reg; #[doc = "Host Pipe Status Register"] pub mod hstpipisr_blk_mode; -#[doc = "HSTPIPISR_INTRPT_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPISR_INTRPT_MODE (r) register accessor: Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_intrpt_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipisr_intrpt_mode`] +module"] pub type HSTPIPISR_INTRPT_MODE = crate::Reg; #[doc = "Host Pipe Status Register"] pub mod hstpipisr_intrpt_mode; -#[doc = "HSTPIPICR_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPICR_CTRL_MODE (w) register accessor: Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipicr_ctrl_mode`] +module"] pub type HSTPIPICR_CTRL_MODE = crate::Reg; #[doc = "Host Pipe Clear Register"] pub mod hstpipicr_ctrl_mode; -#[doc = "HSTPIPICR_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPICR_ISO_MODE (w) register accessor: Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipicr_iso_mode`] +module"] pub type HSTPIPICR_ISO_MODE = crate::Reg; #[doc = "Host Pipe Clear Register"] pub mod hstpipicr_iso_mode; -#[doc = "HSTPIPICR_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPICR_BLK_MODE (w) register accessor: Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipicr_blk_mode`] +module"] pub type HSTPIPICR_BLK_MODE = crate::Reg; #[doc = "Host Pipe Clear Register"] pub mod hstpipicr_blk_mode; -#[doc = "HSTPIPICR_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPICR_INTRPT_MODE (w) register accessor: Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipicr_intrpt_mode`] +module"] pub type HSTPIPICR_INTRPT_MODE = crate::Reg; #[doc = "Host Pipe Clear Register"] pub mod hstpipicr_intrpt_mode; -#[doc = "HSTPIPIFR_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIFR_CTRL_MODE (w) register accessor: Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipifr_ctrl_mode`] +module"] pub type HSTPIPIFR_CTRL_MODE = crate::Reg; #[doc = "Host Pipe Set Register"] pub mod hstpipifr_ctrl_mode; -#[doc = "HSTPIPIFR_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIFR_ISO_MODE (w) register accessor: Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipifr_iso_mode`] +module"] pub type HSTPIPIFR_ISO_MODE = crate::Reg; #[doc = "Host Pipe Set Register"] pub mod hstpipifr_iso_mode; -#[doc = "HSTPIPIFR_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIFR_BLK_MODE (w) register accessor: Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipifr_blk_mode`] +module"] pub type HSTPIPIFR_BLK_MODE = crate::Reg; #[doc = "Host Pipe Set Register"] pub mod hstpipifr_blk_mode; -#[doc = "HSTPIPIFR_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIFR_INTRPT_MODE (w) register accessor: Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipifr_intrpt_mode`] +module"] pub type HSTPIPIFR_INTRPT_MODE = crate::Reg; #[doc = "Host Pipe Set Register"] pub mod hstpipifr_intrpt_mode; -#[doc = "HSTPIPIMR_CTRL_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIMR_CTRL_MODE (r) register accessor: Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_ctrl_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipimr_ctrl_mode`] +module"] pub type HSTPIPIMR_CTRL_MODE = crate::Reg; #[doc = "Host Pipe Mask Register"] pub mod hstpipimr_ctrl_mode; -#[doc = "HSTPIPIMR_ISO_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIMR_ISO_MODE (r) register accessor: Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_iso_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipimr_iso_mode`] +module"] pub type HSTPIPIMR_ISO_MODE = crate::Reg; #[doc = "Host Pipe Mask Register"] pub mod hstpipimr_iso_mode; -#[doc = "HSTPIPIMR_BLK_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIMR_BLK_MODE (r) register accessor: Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_blk_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipimr_blk_mode`] +module"] pub type HSTPIPIMR_BLK_MODE = crate::Reg; #[doc = "Host Pipe Mask Register"] pub mod hstpipimr_blk_mode; -#[doc = "HSTPIPIMR_INTRPT_MODE (r) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIMR_INTRPT_MODE (r) register accessor: Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_intrpt_mode::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipimr_intrpt_mode`] +module"] pub type HSTPIPIMR_INTRPT_MODE = crate::Reg; #[doc = "Host Pipe Mask Register"] pub mod hstpipimr_intrpt_mode; -#[doc = "HSTPIPIER_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIER_CTRL_MODE (w) register accessor: Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipier_ctrl_mode`] +module"] pub type HSTPIPIER_CTRL_MODE = crate::Reg; #[doc = "Host Pipe Enable Register"] pub mod hstpipier_ctrl_mode; -#[doc = "HSTPIPIER_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIER_ISO_MODE (w) register accessor: Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipier_iso_mode`] +module"] pub type HSTPIPIER_ISO_MODE = crate::Reg; #[doc = "Host Pipe Enable Register"] pub mod hstpipier_iso_mode; -#[doc = "HSTPIPIER_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIER_BLK_MODE (w) register accessor: Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipier_blk_mode`] +module"] pub type HSTPIPIER_BLK_MODE = crate::Reg; #[doc = "Host Pipe Enable Register"] pub mod hstpipier_blk_mode; -#[doc = "HSTPIPIER_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIER_INTRPT_MODE (w) register accessor: Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipier_intrpt_mode`] +module"] pub type HSTPIPIER_INTRPT_MODE = crate::Reg; #[doc = "Host Pipe Enable Register"] pub mod hstpipier_intrpt_mode; -#[doc = "HSTPIPIDR_CTRL_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIDR_CTRL_MODE (w) register accessor: Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_ctrl_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipidr_ctrl_mode`] +module"] pub type HSTPIPIDR_CTRL_MODE = crate::Reg; #[doc = "Host Pipe Disable Register"] pub mod hstpipidr_ctrl_mode; -#[doc = "HSTPIPIDR_ISO_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIDR_ISO_MODE (w) register accessor: Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_iso_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipidr_iso_mode`] +module"] pub type HSTPIPIDR_ISO_MODE = crate::Reg; #[doc = "Host Pipe Disable Register"] pub mod hstpipidr_iso_mode; -#[doc = "HSTPIPIDR_BLK_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIDR_BLK_MODE (w) register accessor: Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_blk_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipidr_blk_mode`] +module"] pub type HSTPIPIDR_BLK_MODE = crate::Reg; #[doc = "Host Pipe Disable Register"] pub mod hstpipidr_blk_mode; -#[doc = "HSTPIPIDR_INTRPT_MODE (w) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPIDR_INTRPT_MODE (w) register accessor: Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_intrpt_mode::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipidr_intrpt_mode`] +module"] pub type HSTPIPIDR_INTRPT_MODE = crate::Reg; #[doc = "Host Pipe Disable Register"] pub mod hstpipidr_intrpt_mode; -#[doc = "HSTPIPINRQ (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPINRQ (rw) register accessor: Host Pipe IN Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipinrq::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipinrq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpipinrq`] +module"] pub type HSTPIPINRQ = crate::Reg; #[doc = "Host Pipe IN Request Register"] pub mod hstpipinrq; -#[doc = "HSTPIPERR (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTPIPERR (rw) register accessor: Host Pipe Error Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpiperr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpiperr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstpiperr`] +module"] pub type HSTPIPERR = crate::Reg; #[doc = "Host Pipe Error Register"] pub mod hstpiperr; @@ -654,19 +728,23 @@ pub use self::usbhs_hstdma::USBHS_HSTDMA; #[doc = r"Cluster"] #[doc = "Host DMA Channel Next Descriptor Address Register"] pub mod usbhs_hstdma; -#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +#[doc = "CTRL (rw) register accessor: General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ctrl`] +module"] pub type CTRL = crate::Reg; #[doc = "General Control Register"] pub mod ctrl; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: General Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "General Status Register"] pub mod sr; -#[doc = "SCR (w) register accessor: an alias for `Reg`"] +#[doc = "SCR (w) register accessor: General Status Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`scr`] +module"] pub type SCR = crate::Reg; #[doc = "General Status Clear Register"] pub mod scr; -#[doc = "SFR (w) register accessor: an alias for `Reg`"] +#[doc = "SFR (w) register accessor: General Status Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sfr`] +module"] pub type SFR = crate::Reg; #[doc = "General Status Set Register"] pub mod sfr; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/ctrl.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/ctrl.rs index 1e740285..887b08b5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/ctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/ctrl.rs @@ -1,59 +1,27 @@ #[doc = "Register `CTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDERRE` reader - Remote Device Connection Error Interrupt Enable"] pub type RDERRE_R = crate::BitReader; #[doc = "Field `RDERRE` writer - Remote Device Connection Error Interrupt Enable"] -pub type RDERRE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type RDERRE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSHWC` reader - VBUS Hardware Control"] pub type VBUSHWC_R = crate::BitReader; #[doc = "Field `VBUSHWC` writer - VBUS Hardware Control"] -pub type VBUSHWC_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type VBUSHWC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FRZCLK` reader - Freeze USB Clock"] pub type FRZCLK_R = crate::BitReader; #[doc = "Field `FRZCLK` writer - Freeze USB Clock"] -pub type FRZCLK_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type FRZCLK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `USBE` reader - USBHS Enable"] pub type USBE_R = crate::BitReader; #[doc = "Field `USBE` writer - USBHS Enable"] -pub type USBE_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type USBE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UID` reader - UID Pin Enable"] pub type UID_R = crate::BitReader; #[doc = "Field `UID` writer - UID Pin Enable"] -pub type UID_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O>; +pub type UID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UIMOD` reader - USBHS Mode"] pub type UIMOD_R = crate::BitReader; #[doc = "USBHS Mode\n\nValue on reset: 0"] @@ -79,28 +47,31 @@ impl UIMOD_R { true => UIMODSELECT_A::DEVICE, } } - #[doc = "Checks if the value of the field is `HOST`"] + #[doc = "The module is in USB Host mode."] #[inline(always)] pub fn is_host(&self) -> bool { *self == UIMODSELECT_A::HOST } - #[doc = "Checks if the value of the field is `DEVICE`"] + #[doc = "The module is in USB Device mode."] #[inline(always)] pub fn is_device(&self) -> bool { *self == UIMODSELECT_A::DEVICE } } #[doc = "Field `UIMOD` writer - USBHS Mode"] -pub type UIMOD_W<'a, const O: u8> = crate::BitWriter<'a, CTRL_SPEC, O, UIMODSELECT_A>; -impl<'a, const O: u8> UIMOD_W<'a, O> { +pub type UIMOD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, UIMODSELECT_A>; +impl<'a, REG, const O: u8> UIMOD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The module is in USB Host mode."] #[inline(always)] - pub fn host(self) -> &'a mut W { + pub fn host(self) -> &'a mut crate::W { self.variant(UIMODSELECT_A::HOST) } #[doc = "The module is in USB Device mode."] #[inline(always)] - pub fn device(self) -> &'a mut W { + pub fn device(self) -> &'a mut crate::W { self.variant(UIMODSELECT_A::DEVICE) } } @@ -140,58 +111,55 @@ impl W { #[doc = "Bit 4 - Remote Device Connection Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rderre(&mut self) -> RDERRE_W<4> { + pub fn rderre(&mut self) -> RDERRE_W { RDERRE_W::new(self) } #[doc = "Bit 8 - VBUS Hardware Control"] #[inline(always)] #[must_use] - pub fn vbushwc(&mut self) -> VBUSHWC_W<8> { + pub fn vbushwc(&mut self) -> VBUSHWC_W { VBUSHWC_W::new(self) } #[doc = "Bit 14 - Freeze USB Clock"] #[inline(always)] #[must_use] - pub fn frzclk(&mut self) -> FRZCLK_W<14> { + pub fn frzclk(&mut self) -> FRZCLK_W { FRZCLK_W::new(self) } #[doc = "Bit 15 - USBHS Enable"] #[inline(always)] #[must_use] - pub fn usbe(&mut self) -> USBE_W<15> { + pub fn usbe(&mut self) -> USBE_W { USBE_W::new(self) } #[doc = "Bit 24 - UID Pin Enable"] #[inline(always)] #[must_use] - pub fn uid(&mut self) -> UID_W<24> { + pub fn uid(&mut self) -> UID_W { UID_W::new(self) } #[doc = "Bit 25 - USBHS Mode"] #[inline(always)] #[must_use] - pub fn uimod(&mut self) -> UIMOD_W<25> { + pub fn uimod(&mut self) -> UIMOD_W { UIMOD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "General Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +#[doc = "General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CTRL_SPEC; impl crate::RegisterSpec for CTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ctrl::R](R) reader structure"] -impl crate::Readable for CTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devctrl.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devctrl.rs index b9afa1ec..8594e581 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devctrl.rs @@ -1,55 +1,23 @@ #[doc = "Register `DEVCTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVCTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UADD` reader - USB Address"] pub type UADD_R = crate::FieldReader; #[doc = "Field `UADD` writer - USB Address"] -pub type UADD_W<'a, const O: u8> = crate::FieldWriter<'a, DEVCTRL_SPEC, 7, O>; +pub type UADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `ADDEN` reader - Address Enable"] pub type ADDEN_R = crate::BitReader; #[doc = "Field `ADDEN` writer - Address Enable"] -pub type ADDEN_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type ADDEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DETACH` reader - Detach"] pub type DETACH_R = crate::BitReader; #[doc = "Field `DETACH` writer - Detach"] -pub type DETACH_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type DETACH_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RMWKUP` reader - Remote Wake-Up"] pub type RMWKUP_R = crate::BitReader; #[doc = "Field `RMWKUP` writer - Remote Wake-Up"] -pub type RMWKUP_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type RMWKUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPDCONF` reader - Mode Configuration"] pub type SPDCONF_R = crate::FieldReader; #[doc = "Mode Configuration\n\nValue on reset: 0"] @@ -86,72 +54,75 @@ impl SPDCONF_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable."] #[inline(always)] pub fn is_normal(&self) -> bool { *self == SPDCONFSELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[doc = "For a better consumption, if high speed is not needed."] #[inline(always)] pub fn is_low_power(&self) -> bool { *self == SPDCONFSELECT_A::LOW_POWER } - #[doc = "Checks if the value of the field is `HIGH_SPEED`"] + #[doc = "Forced high speed."] #[inline(always)] pub fn is_high_speed(&self) -> bool { *self == SPDCONFSELECT_A::HIGH_SPEED } - #[doc = "Checks if the value of the field is `FORCED_FS`"] + #[doc = "The peripheral remains in Full-speed mode whatever the host speed capability."] #[inline(always)] pub fn is_forced_fs(&self) -> bool { *self == SPDCONFSELECT_A::FORCED_FS } } #[doc = "Field `SPDCONF` writer - Mode Configuration"] -pub type SPDCONF_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, DEVCTRL_SPEC, 2, O, SPDCONFSELECT_A>; -impl<'a, const O: u8> SPDCONF_W<'a, O> { +pub type SPDCONF_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, SPDCONFSELECT_A>; +impl<'a, REG, const O: u8> SPDCONF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable."] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::NORMAL) } #[doc = "For a better consumption, if high speed is not needed."] #[inline(always)] - pub fn low_power(self) -> &'a mut W { + pub fn low_power(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::LOW_POWER) } #[doc = "Forced high speed."] #[inline(always)] - pub fn high_speed(self) -> &'a mut W { + pub fn high_speed(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::HIGH_SPEED) } #[doc = "The peripheral remains in Full-speed mode whatever the host speed capability."] #[inline(always)] - pub fn forced_fs(self) -> &'a mut W { + pub fn forced_fs(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::FORCED_FS) } } #[doc = "Field `LS` reader - Low-Speed Mode Force"] pub type LS_R = crate::BitReader; #[doc = "Field `LS` writer - Low-Speed Mode Force"] -pub type LS_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type LS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSTJ` reader - Test mode J"] pub type TSTJ_R = crate::BitReader; #[doc = "Field `TSTJ` writer - Test mode J"] -pub type TSTJ_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type TSTJ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSTK` reader - Test mode K"] pub type TSTK_R = crate::BitReader; #[doc = "Field `TSTK` writer - Test mode K"] -pub type TSTK_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type TSTK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TSTPCKT` reader - Test packet mode"] pub type TSTPCKT_R = crate::BitReader; #[doc = "Field `TSTPCKT` writer - Test packet mode"] -pub type TSTPCKT_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type TSTPCKT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OPMODE2` reader - Specific Operational mode"] pub type OPMODE2_R = crate::BitReader; #[doc = "Field `OPMODE2` writer - Specific Operational mode"] -pub type OPMODE2_W<'a, const O: u8> = crate::BitWriter<'a, DEVCTRL_SPEC, O>; +pub type OPMODE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:6 - USB Address"] #[inline(always)] @@ -208,82 +179,79 @@ impl W { #[doc = "Bits 0:6 - USB Address"] #[inline(always)] #[must_use] - pub fn uadd(&mut self) -> UADD_W<0> { + pub fn uadd(&mut self) -> UADD_W { UADD_W::new(self) } #[doc = "Bit 7 - Address Enable"] #[inline(always)] #[must_use] - pub fn adden(&mut self) -> ADDEN_W<7> { + pub fn adden(&mut self) -> ADDEN_W { ADDEN_W::new(self) } #[doc = "Bit 8 - Detach"] #[inline(always)] #[must_use] - pub fn detach(&mut self) -> DETACH_W<8> { + pub fn detach(&mut self) -> DETACH_W { DETACH_W::new(self) } #[doc = "Bit 9 - Remote Wake-Up"] #[inline(always)] #[must_use] - pub fn rmwkup(&mut self) -> RMWKUP_W<9> { + pub fn rmwkup(&mut self) -> RMWKUP_W { RMWKUP_W::new(self) } #[doc = "Bits 10:11 - Mode Configuration"] #[inline(always)] #[must_use] - pub fn spdconf(&mut self) -> SPDCONF_W<10> { + pub fn spdconf(&mut self) -> SPDCONF_W { SPDCONF_W::new(self) } #[doc = "Bit 12 - Low-Speed Mode Force"] #[inline(always)] #[must_use] - pub fn ls(&mut self) -> LS_W<12> { + pub fn ls(&mut self) -> LS_W { LS_W::new(self) } #[doc = "Bit 13 - Test mode J"] #[inline(always)] #[must_use] - pub fn tstj(&mut self) -> TSTJ_W<13> { + pub fn tstj(&mut self) -> TSTJ_W { TSTJ_W::new(self) } #[doc = "Bit 14 - Test mode K"] #[inline(always)] #[must_use] - pub fn tstk(&mut self) -> TSTK_W<14> { + pub fn tstk(&mut self) -> TSTK_W { TSTK_W::new(self) } #[doc = "Bit 15 - Test packet mode"] #[inline(always)] #[must_use] - pub fn tstpckt(&mut self) -> TSTPCKT_W<15> { + pub fn tstpckt(&mut self) -> TSTPCKT_W { TSTPCKT_W::new(self) } #[doc = "Bit 16 - Specific Operational mode"] #[inline(always)] #[must_use] - pub fn opmode2(&mut self) -> OPMODE2_W<16> { + pub fn opmode2(&mut self) -> OPMODE2_W { OPMODE2_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device General Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devctrl](index.html) module"] +#[doc = "Device General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVCTRL_SPEC; impl crate::RegisterSpec for DEVCTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devctrl::R](R) reader structure"] -impl crate::Readable for DEVCTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [devctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`devctrl::R`](R) reader structure"] +impl crate::Readable for DEVCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devctrl::W`](W) writer structure"] impl crate::Writable for DEVCTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devept.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devept.rs index 15bf858e..ddcb218f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devept.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devept.rs @@ -1,119 +1,87 @@ #[doc = "Register `DEVEPT` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVEPT` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EPEN0` reader - Endpoint 0 Enable"] pub type EPEN0_R = crate::BitReader; #[doc = "Field `EPEN0` writer - Endpoint 0 Enable"] -pub type EPEN0_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN1` reader - Endpoint 1 Enable"] pub type EPEN1_R = crate::BitReader; #[doc = "Field `EPEN1` writer - Endpoint 1 Enable"] -pub type EPEN1_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN2` reader - Endpoint 2 Enable"] pub type EPEN2_R = crate::BitReader; #[doc = "Field `EPEN2` writer - Endpoint 2 Enable"] -pub type EPEN2_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN3` reader - Endpoint 3 Enable"] pub type EPEN3_R = crate::BitReader; #[doc = "Field `EPEN3` writer - Endpoint 3 Enable"] -pub type EPEN3_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN4` reader - Endpoint 4 Enable"] pub type EPEN4_R = crate::BitReader; #[doc = "Field `EPEN4` writer - Endpoint 4 Enable"] -pub type EPEN4_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN5` reader - Endpoint 5 Enable"] pub type EPEN5_R = crate::BitReader; #[doc = "Field `EPEN5` writer - Endpoint 5 Enable"] -pub type EPEN5_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN6` reader - Endpoint 6 Enable"] pub type EPEN6_R = crate::BitReader; #[doc = "Field `EPEN6` writer - Endpoint 6 Enable"] -pub type EPEN6_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN7` reader - Endpoint 7 Enable"] pub type EPEN7_R = crate::BitReader; #[doc = "Field `EPEN7` writer - Endpoint 7 Enable"] -pub type EPEN7_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN8` reader - Endpoint 8 Enable"] pub type EPEN8_R = crate::BitReader; #[doc = "Field `EPEN8` writer - Endpoint 8 Enable"] -pub type EPEN8_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPEN9` reader - Endpoint 9 Enable"] pub type EPEN9_R = crate::BitReader; #[doc = "Field `EPEN9` writer - Endpoint 9 Enable"] -pub type EPEN9_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPEN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST0` reader - Endpoint 0 Reset"] pub type EPRST0_R = crate::BitReader; #[doc = "Field `EPRST0` writer - Endpoint 0 Reset"] -pub type EPRST0_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST1` reader - Endpoint 1 Reset"] pub type EPRST1_R = crate::BitReader; #[doc = "Field `EPRST1` writer - Endpoint 1 Reset"] -pub type EPRST1_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST2` reader - Endpoint 2 Reset"] pub type EPRST2_R = crate::BitReader; #[doc = "Field `EPRST2` writer - Endpoint 2 Reset"] -pub type EPRST2_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST3` reader - Endpoint 3 Reset"] pub type EPRST3_R = crate::BitReader; #[doc = "Field `EPRST3` writer - Endpoint 3 Reset"] -pub type EPRST3_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST4` reader - Endpoint 4 Reset"] pub type EPRST4_R = crate::BitReader; #[doc = "Field `EPRST4` writer - Endpoint 4 Reset"] -pub type EPRST4_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST5` reader - Endpoint 5 Reset"] pub type EPRST5_R = crate::BitReader; #[doc = "Field `EPRST5` writer - Endpoint 5 Reset"] -pub type EPRST5_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST6` reader - Endpoint 6 Reset"] pub type EPRST6_R = crate::BitReader; #[doc = "Field `EPRST6` writer - Endpoint 6 Reset"] -pub type EPRST6_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST7` reader - Endpoint 7 Reset"] pub type EPRST7_R = crate::BitReader; #[doc = "Field `EPRST7` writer - Endpoint 7 Reset"] -pub type EPRST7_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST8` reader - Endpoint 8 Reset"] pub type EPRST8_R = crate::BitReader; #[doc = "Field `EPRST8` writer - Endpoint 8 Reset"] -pub type EPRST8_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPRST9` reader - Endpoint 9 Reset"] pub type EPRST9_R = crate::BitReader; #[doc = "Field `EPRST9` writer - Endpoint 9 Reset"] -pub type EPRST9_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPT_SPEC, O>; +pub type EPRST9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Endpoint 0 Enable"] #[inline(always)] @@ -220,142 +188,139 @@ impl W { #[doc = "Bit 0 - Endpoint 0 Enable"] #[inline(always)] #[must_use] - pub fn epen0(&mut self) -> EPEN0_W<0> { + pub fn epen0(&mut self) -> EPEN0_W { EPEN0_W::new(self) } #[doc = "Bit 1 - Endpoint 1 Enable"] #[inline(always)] #[must_use] - pub fn epen1(&mut self) -> EPEN1_W<1> { + pub fn epen1(&mut self) -> EPEN1_W { EPEN1_W::new(self) } #[doc = "Bit 2 - Endpoint 2 Enable"] #[inline(always)] #[must_use] - pub fn epen2(&mut self) -> EPEN2_W<2> { + pub fn epen2(&mut self) -> EPEN2_W { EPEN2_W::new(self) } #[doc = "Bit 3 - Endpoint 3 Enable"] #[inline(always)] #[must_use] - pub fn epen3(&mut self) -> EPEN3_W<3> { + pub fn epen3(&mut self) -> EPEN3_W { EPEN3_W::new(self) } #[doc = "Bit 4 - Endpoint 4 Enable"] #[inline(always)] #[must_use] - pub fn epen4(&mut self) -> EPEN4_W<4> { + pub fn epen4(&mut self) -> EPEN4_W { EPEN4_W::new(self) } #[doc = "Bit 5 - Endpoint 5 Enable"] #[inline(always)] #[must_use] - pub fn epen5(&mut self) -> EPEN5_W<5> { + pub fn epen5(&mut self) -> EPEN5_W { EPEN5_W::new(self) } #[doc = "Bit 6 - Endpoint 6 Enable"] #[inline(always)] #[must_use] - pub fn epen6(&mut self) -> EPEN6_W<6> { + pub fn epen6(&mut self) -> EPEN6_W { EPEN6_W::new(self) } #[doc = "Bit 7 - Endpoint 7 Enable"] #[inline(always)] #[must_use] - pub fn epen7(&mut self) -> EPEN7_W<7> { + pub fn epen7(&mut self) -> EPEN7_W { EPEN7_W::new(self) } #[doc = "Bit 8 - Endpoint 8 Enable"] #[inline(always)] #[must_use] - pub fn epen8(&mut self) -> EPEN8_W<8> { + pub fn epen8(&mut self) -> EPEN8_W { EPEN8_W::new(self) } #[doc = "Bit 9 - Endpoint 9 Enable"] #[inline(always)] #[must_use] - pub fn epen9(&mut self) -> EPEN9_W<9> { + pub fn epen9(&mut self) -> EPEN9_W { EPEN9_W::new(self) } #[doc = "Bit 16 - Endpoint 0 Reset"] #[inline(always)] #[must_use] - pub fn eprst0(&mut self) -> EPRST0_W<16> { + pub fn eprst0(&mut self) -> EPRST0_W { EPRST0_W::new(self) } #[doc = "Bit 17 - Endpoint 1 Reset"] #[inline(always)] #[must_use] - pub fn eprst1(&mut self) -> EPRST1_W<17> { + pub fn eprst1(&mut self) -> EPRST1_W { EPRST1_W::new(self) } #[doc = "Bit 18 - Endpoint 2 Reset"] #[inline(always)] #[must_use] - pub fn eprst2(&mut self) -> EPRST2_W<18> { + pub fn eprst2(&mut self) -> EPRST2_W { EPRST2_W::new(self) } #[doc = "Bit 19 - Endpoint 3 Reset"] #[inline(always)] #[must_use] - pub fn eprst3(&mut self) -> EPRST3_W<19> { + pub fn eprst3(&mut self) -> EPRST3_W { EPRST3_W::new(self) } #[doc = "Bit 20 - Endpoint 4 Reset"] #[inline(always)] #[must_use] - pub fn eprst4(&mut self) -> EPRST4_W<20> { + pub fn eprst4(&mut self) -> EPRST4_W { EPRST4_W::new(self) } #[doc = "Bit 21 - Endpoint 5 Reset"] #[inline(always)] #[must_use] - pub fn eprst5(&mut self) -> EPRST5_W<21> { + pub fn eprst5(&mut self) -> EPRST5_W { EPRST5_W::new(self) } #[doc = "Bit 22 - Endpoint 6 Reset"] #[inline(always)] #[must_use] - pub fn eprst6(&mut self) -> EPRST6_W<22> { + pub fn eprst6(&mut self) -> EPRST6_W { EPRST6_W::new(self) } #[doc = "Bit 23 - Endpoint 7 Reset"] #[inline(always)] #[must_use] - pub fn eprst7(&mut self) -> EPRST7_W<23> { + pub fn eprst7(&mut self) -> EPRST7_W { EPRST7_W::new(self) } #[doc = "Bit 24 - Endpoint 8 Reset"] #[inline(always)] #[must_use] - pub fn eprst8(&mut self) -> EPRST8_W<24> { + pub fn eprst8(&mut self) -> EPRST8_W { EPRST8_W::new(self) } #[doc = "Bit 25 - Endpoint 9 Reset"] #[inline(always)] #[must_use] - pub fn eprst9(&mut self) -> EPRST9_W<25> { + pub fn eprst9(&mut self) -> EPRST9_W { EPRST9_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devept](index.html) module"] +#[doc = "Device Endpoint Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devept::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devept::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPT_SPEC; impl crate::RegisterSpec for DEVEPT_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devept::R](R) reader structure"] -impl crate::Readable for DEVEPT_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [devept::W](W) writer structure"] +#[doc = "`read()` method returns [`devept::R`](R) reader structure"] +impl crate::Readable for DEVEPT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devept::W`](W) writer structure"] impl crate::Writable for DEVEPT_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptcfg.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptcfg.rs index ccee5c36..becaf7b2 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptcfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptcfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `DEVEPTCFG[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVEPTCFG[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALLOC` reader - Endpoint Memory Allocate"] pub type ALLOC_R = crate::BitReader; #[doc = "Field `ALLOC` writer - Endpoint Memory Allocate"] -pub type ALLOC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTCFG_SPEC, O>; +pub type ALLOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPBK` reader - Endpoint Banks"] pub type EPBK_R = crate::FieldReader; #[doc = "Endpoint Banks\n\nValue on reset: 0"] @@ -71,38 +39,42 @@ impl EPBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1_BANK`"] + #[doc = "Single-bank endpoint"] #[inline(always)] pub fn is_1_bank(&self) -> bool { *self == EPBKSELECT_A::_1_BANK } - #[doc = "Checks if the value of the field is `_2_BANK`"] + #[doc = "Double-bank endpoint"] #[inline(always)] pub fn is_2_bank(&self) -> bool { *self == EPBKSELECT_A::_2_BANK } - #[doc = "Checks if the value of the field is `_3_BANK`"] + #[doc = "Triple-bank endpoint"] #[inline(always)] pub fn is_3_bank(&self) -> bool { *self == EPBKSELECT_A::_3_BANK } } #[doc = "Field `EPBK` writer - Endpoint Banks"] -pub type EPBK_W<'a, const O: u8> = crate::FieldWriter<'a, DEVEPTCFG_SPEC, 2, O, EPBKSELECT_A>; -impl<'a, const O: u8> EPBK_W<'a, O> { +pub type EPBK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, EPBKSELECT_A>; +impl<'a, REG, const O: u8> EPBK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Single-bank endpoint"] #[inline(always)] - pub fn _1_bank(self) -> &'a mut W { + pub fn _1_bank(self) -> &'a mut crate::W { self.variant(EPBKSELECT_A::_1_BANK) } #[doc = "Double-bank endpoint"] #[inline(always)] - pub fn _2_bank(self) -> &'a mut W { + pub fn _2_bank(self) -> &'a mut crate::W { self.variant(EPBKSELECT_A::_2_BANK) } #[doc = "Triple-bank endpoint"] #[inline(always)] - pub fn _3_bank(self) -> &'a mut W { + pub fn _3_bank(self) -> &'a mut crate::W { self.variant(EPBKSELECT_A::_3_BANK) } } @@ -154,89 +126,92 @@ impl EPSIZE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8 bytes"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == EPSIZESELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16 bytes"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == EPSIZESELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32 bytes"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == EPSIZESELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64 bytes"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == EPSIZESELECT_A::_64_BYTE } - #[doc = "Checks if the value of the field is `_128_BYTE`"] + #[doc = "128 bytes"] #[inline(always)] pub fn is_128_byte(&self) -> bool { *self == EPSIZESELECT_A::_128_BYTE } - #[doc = "Checks if the value of the field is `_256_BYTE`"] + #[doc = "256 bytes"] #[inline(always)] pub fn is_256_byte(&self) -> bool { *self == EPSIZESELECT_A::_256_BYTE } - #[doc = "Checks if the value of the field is `_512_BYTE`"] + #[doc = "512 bytes"] #[inline(always)] pub fn is_512_byte(&self) -> bool { *self == EPSIZESELECT_A::_512_BYTE } - #[doc = "Checks if the value of the field is `_1024_BYTE`"] + #[doc = "1024 bytes"] #[inline(always)] pub fn is_1024_byte(&self) -> bool { *self == EPSIZESELECT_A::_1024_BYTE } } #[doc = "Field `EPSIZE` writer - Endpoint Size"] -pub type EPSIZE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, DEVEPTCFG_SPEC, 3, O, EPSIZESELECT_A>; -impl<'a, const O: u8> EPSIZE_W<'a, O> { +pub type EPSIZE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, EPSIZESELECT_A>; +impl<'a, REG, const O: u8> EPSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8 bytes"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_8_BYTE) } #[doc = "16 bytes"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_16_BYTE) } #[doc = "32 bytes"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_32_BYTE) } #[doc = "64 bytes"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_64_BYTE) } #[doc = "128 bytes"] #[inline(always)] - pub fn _128_byte(self) -> &'a mut W { + pub fn _128_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_128_BYTE) } #[doc = "256 bytes"] #[inline(always)] - pub fn _256_byte(self) -> &'a mut W { + pub fn _256_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_256_BYTE) } #[doc = "512 bytes"] #[inline(always)] - pub fn _512_byte(self) -> &'a mut W { + pub fn _512_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_512_BYTE) } #[doc = "1024 bytes"] #[inline(always)] - pub fn _1024_byte(self) -> &'a mut W { + pub fn _1024_byte(self) -> &'a mut crate::W { self.variant(EPSIZESELECT_A::_1024_BYTE) } } @@ -265,35 +240,38 @@ impl EPDIR_R { true => EPDIRSELECT_A::IN, } } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "The endpoint direction is OUT."] #[inline(always)] pub fn is_out(&self) -> bool { *self == EPDIRSELECT_A::OUT } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "The endpoint direction is IN (nor for control endpoints)."] #[inline(always)] pub fn is_in(&self) -> bool { *self == EPDIRSELECT_A::IN } } #[doc = "Field `EPDIR` writer - Endpoint Direction"] -pub type EPDIR_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTCFG_SPEC, O, EPDIRSELECT_A>; -impl<'a, const O: u8> EPDIR_W<'a, O> { +pub type EPDIR_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, EPDIRSELECT_A>; +impl<'a, REG, const O: u8> EPDIR_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The endpoint direction is OUT."] #[inline(always)] - pub fn out(self) -> &'a mut W { + pub fn out(self) -> &'a mut crate::W { self.variant(EPDIRSELECT_A::OUT) } #[doc = "The endpoint direction is IN (nor for control endpoints)."] #[inline(always)] - pub fn in_(self) -> &'a mut W { + pub fn in_(self) -> &'a mut crate::W { self.variant(EPDIRSELECT_A::IN) } } #[doc = "Field `AUTOSW` reader - Automatic Switch"] pub type AUTOSW_R = crate::BitReader; #[doc = "Field `AUTOSW` writer - Automatic Switch"] -pub type AUTOSW_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTCFG_SPEC, O>; +pub type AUTOSW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPTYPE` reader - Endpoint Type"] pub type EPTYPE_R = crate::FieldReader; #[doc = "Endpoint Type\n\nValue on reset: 0"] @@ -330,49 +308,52 @@ impl EPTYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CTRL`"] + #[doc = "Control"] #[inline(always)] pub fn is_ctrl(&self) -> bool { *self == EPTYPESELECT_A::CTRL } - #[doc = "Checks if the value of the field is `ISO`"] + #[doc = "Isochronous"] #[inline(always)] pub fn is_iso(&self) -> bool { *self == EPTYPESELECT_A::ISO } - #[doc = "Checks if the value of the field is `BLK`"] + #[doc = "Bulk"] #[inline(always)] pub fn is_blk(&self) -> bool { *self == EPTYPESELECT_A::BLK } - #[doc = "Checks if the value of the field is `INTRPT`"] + #[doc = "Interrupt"] #[inline(always)] pub fn is_intrpt(&self) -> bool { *self == EPTYPESELECT_A::INTRPT } } #[doc = "Field `EPTYPE` writer - Endpoint Type"] -pub type EPTYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, DEVEPTCFG_SPEC, 2, O, EPTYPESELECT_A>; -impl<'a, const O: u8> EPTYPE_W<'a, O> { +pub type EPTYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, EPTYPESELECT_A>; +impl<'a, REG, const O: u8> EPTYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Control"] #[inline(always)] - pub fn ctrl(self) -> &'a mut W { + pub fn ctrl(self) -> &'a mut crate::W { self.variant(EPTYPESELECT_A::CTRL) } #[doc = "Isochronous"] #[inline(always)] - pub fn iso(self) -> &'a mut W { + pub fn iso(self) -> &'a mut crate::W { self.variant(EPTYPESELECT_A::ISO) } #[doc = "Bulk"] #[inline(always)] - pub fn blk(self) -> &'a mut W { + pub fn blk(self) -> &'a mut crate::W { self.variant(EPTYPESELECT_A::BLK) } #[doc = "Interrupt"] #[inline(always)] - pub fn intrpt(self) -> &'a mut W { + pub fn intrpt(self) -> &'a mut crate::W { self.variant(EPTYPESELECT_A::INTRPT) } } @@ -412,49 +393,52 @@ impl NBTRANS_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_TRANS`"] + #[doc = "Reserved to endpoint that does not have the high-bandwidth isochronous capability."] #[inline(always)] pub fn is_0_trans(&self) -> bool { *self == NBTRANSSELECT_A::_0_TRANS } - #[doc = "Checks if the value of the field is `_1_TRANS`"] + #[doc = "Default value: one transaction per microframe."] #[inline(always)] pub fn is_1_trans(&self) -> bool { *self == NBTRANSSELECT_A::_1_TRANS } - #[doc = "Checks if the value of the field is `_2_TRANS`"] + #[doc = "Two transactions per microframe. This endpoint should be configured as double-bank."] #[inline(always)] pub fn is_2_trans(&self) -> bool { *self == NBTRANSSELECT_A::_2_TRANS } - #[doc = "Checks if the value of the field is `_3_TRANS`"] + #[doc = "Three transactions per microframe. This endpoint should be configured as triple-bank."] #[inline(always)] pub fn is_3_trans(&self) -> bool { *self == NBTRANSSELECT_A::_3_TRANS } } #[doc = "Field `NBTRANS` writer - Number of transactions per microframe for isochronous endpoint"] -pub type NBTRANS_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, DEVEPTCFG_SPEC, 2, O, NBTRANSSELECT_A>; -impl<'a, const O: u8> NBTRANS_W<'a, O> { +pub type NBTRANS_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, NBTRANSSELECT_A>; +impl<'a, REG, const O: u8> NBTRANS_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Reserved to endpoint that does not have the high-bandwidth isochronous capability."] #[inline(always)] - pub fn _0_trans(self) -> &'a mut W { + pub fn _0_trans(self) -> &'a mut crate::W { self.variant(NBTRANSSELECT_A::_0_TRANS) } #[doc = "Default value: one transaction per microframe."] #[inline(always)] - pub fn _1_trans(self) -> &'a mut W { + pub fn _1_trans(self) -> &'a mut crate::W { self.variant(NBTRANSSELECT_A::_1_TRANS) } #[doc = "Two transactions per microframe. This endpoint should be configured as double-bank."] #[inline(always)] - pub fn _2_trans(self) -> &'a mut W { + pub fn _2_trans(self) -> &'a mut crate::W { self.variant(NBTRANSSELECT_A::_2_TRANS) } #[doc = "Three transactions per microframe. This endpoint should be configured as triple-bank."] #[inline(always)] - pub fn _3_trans(self) -> &'a mut W { + pub fn _3_trans(self) -> &'a mut crate::W { self.variant(NBTRANSSELECT_A::_3_TRANS) } } @@ -499,64 +483,61 @@ impl W { #[doc = "Bit 1 - Endpoint Memory Allocate"] #[inline(always)] #[must_use] - pub fn alloc(&mut self) -> ALLOC_W<1> { + pub fn alloc(&mut self) -> ALLOC_W { ALLOC_W::new(self) } #[doc = "Bits 2:3 - Endpoint Banks"] #[inline(always)] #[must_use] - pub fn epbk(&mut self) -> EPBK_W<2> { + pub fn epbk(&mut self) -> EPBK_W { EPBK_W::new(self) } #[doc = "Bits 4:6 - Endpoint Size"] #[inline(always)] #[must_use] - pub fn epsize(&mut self) -> EPSIZE_W<4> { + pub fn epsize(&mut self) -> EPSIZE_W { EPSIZE_W::new(self) } #[doc = "Bit 8 - Endpoint Direction"] #[inline(always)] #[must_use] - pub fn epdir(&mut self) -> EPDIR_W<8> { + pub fn epdir(&mut self) -> EPDIR_W { EPDIR_W::new(self) } #[doc = "Bit 9 - Automatic Switch"] #[inline(always)] #[must_use] - pub fn autosw(&mut self) -> AUTOSW_W<9> { + pub fn autosw(&mut self) -> AUTOSW_W { AUTOSW_W::new(self) } #[doc = "Bits 11:12 - Endpoint Type"] #[inline(always)] #[must_use] - pub fn eptype(&mut self) -> EPTYPE_W<11> { + pub fn eptype(&mut self) -> EPTYPE_W { EPTYPE_W::new(self) } #[doc = "Bits 13:14 - Number of transactions per microframe for isochronous endpoint"] #[inline(always)] #[must_use] - pub fn nbtrans(&mut self) -> NBTRANS_W<13> { + pub fn nbtrans(&mut self) -> NBTRANS_W { NBTRANS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptcfg](index.html) module"] +#[doc = "Device Endpoint Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTCFG_SPEC; impl crate::RegisterSpec for DEVEPTCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptcfg::R](R) reader structure"] -impl crate::Readable for DEVEPTCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [deveptcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`deveptcfg::R`](R) reader structure"] +impl crate::Readable for DEVEPTCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`deveptcfg::W`](W) writer structure"] impl crate::Writable for DEVEPTCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_blk_mode.rs index eec48557..d9ebcf9e 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_blk_mode.rs @@ -1,104 +1,84 @@ #[doc = "Register `DEVEPTICR_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIC` writer - Transmitted IN Data Interrupt Clear"] -pub type TXINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type TXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type RXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPIC` writer - Received SETUP Interrupt Clear"] -pub type RXSTPIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type RXSTPIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTIC` writer - NAKed OUT Interrupt Clear"] -pub type NAKOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type NAKOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINIC` writer - NAKed IN Interrupt Clear"] -pub type NAKINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type NAKINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDIC` writer - STALLed Interrupt Clear"] -pub type STALLEDIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type STALLEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_BLK_MODE_SPEC, O>; +pub type SHORTPACKETC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinic(&mut self) -> TXINIC_W<0> { + pub fn txinic(&mut self) -> TXINIC_W { TXINIC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutic(&mut self) -> RXOUTIC_W<1> { + pub fn rxoutic(&mut self) -> RXOUTIC_W { RXOUTIC_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstpic(&mut self) -> RXSTPIC_W<2> { + pub fn rxstpic(&mut self) -> RXSTPIC_W { RXSTPIC_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakoutic(&mut self) -> NAKOUTIC_W<3> { + pub fn nakoutic(&mut self) -> NAKOUTIC_W { NAKOUTIC_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakinic(&mut self) -> NAKINIC_W<4> { + pub fn nakinic(&mut self) -> NAKINIC_W { NAKINIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn stalledic(&mut self) -> STALLEDIC_W<6> { + pub fn stalledic(&mut self) -> STALLEDIC_W { STALLEDIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketc(&mut self) -> SHORTPACKETC_W<7> { + pub fn shortpacketc(&mut self) -> SHORTPACKETC_W { SHORTPACKETC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devepticr_blk_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTICR_BLK_MODE_SPEC; impl crate::RegisterSpec for DEVEPTICR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devepticr_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devepticr_blk_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTICR_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_ctrl_mode.rs index 327136cc..a0fdbb4b 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_ctrl_mode.rs @@ -1,104 +1,84 @@ #[doc = "Register `DEVEPTICR_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIC` writer - Transmitted IN Data Interrupt Clear"] -pub type TXINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type TXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type RXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPIC` writer - Received SETUP Interrupt Clear"] -pub type RXSTPIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type RXSTPIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTIC` writer - NAKed OUT Interrupt Clear"] -pub type NAKOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type NAKOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINIC` writer - NAKed IN Interrupt Clear"] -pub type NAKINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type NAKINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDIC` writer - STALLed Interrupt Clear"] -pub type STALLEDIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type STALLEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinic(&mut self) -> TXINIC_W<0> { + pub fn txinic(&mut self) -> TXINIC_W { TXINIC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutic(&mut self) -> RXOUTIC_W<1> { + pub fn rxoutic(&mut self) -> RXOUTIC_W { RXOUTIC_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstpic(&mut self) -> RXSTPIC_W<2> { + pub fn rxstpic(&mut self) -> RXSTPIC_W { RXSTPIC_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakoutic(&mut self) -> NAKOUTIC_W<3> { + pub fn nakoutic(&mut self) -> NAKOUTIC_W { NAKOUTIC_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakinic(&mut self) -> NAKINIC_W<4> { + pub fn nakinic(&mut self) -> NAKINIC_W { NAKINIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn stalledic(&mut self) -> STALLEDIC_W<6> { + pub fn stalledic(&mut self) -> STALLEDIC_W { STALLEDIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketc(&mut self) -> SHORTPACKETC_W<7> { + pub fn shortpacketc(&mut self) -> SHORTPACKETC_W { SHORTPACKETC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devepticr_ctrl_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTICR_CTRL_MODE_SPEC; impl crate::RegisterSpec for DEVEPTICR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devepticr_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devepticr_ctrl_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTICR_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_intrpt_mode.rs index 90e57eda..205dbe03 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_intrpt_mode.rs @@ -1,104 +1,84 @@ #[doc = "Register `DEVEPTICR_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIC` writer - Transmitted IN Data Interrupt Clear"] -pub type TXINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type TXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type RXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPIC` writer - Received SETUP Interrupt Clear"] -pub type RXSTPIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type RXSTPIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTIC` writer - NAKed OUT Interrupt Clear"] -pub type NAKOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type NAKOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINIC` writer - NAKed IN Interrupt Clear"] -pub type NAKINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type NAKINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDIC` writer - STALLed Interrupt Clear"] -pub type STALLEDIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type STALLEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinic(&mut self) -> TXINIC_W<0> { + pub fn txinic(&mut self) -> TXINIC_W { TXINIC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutic(&mut self) -> RXOUTIC_W<1> { + pub fn rxoutic(&mut self) -> RXOUTIC_W { RXOUTIC_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstpic(&mut self) -> RXSTPIC_W<2> { + pub fn rxstpic(&mut self) -> RXSTPIC_W { RXSTPIC_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakoutic(&mut self) -> NAKOUTIC_W<3> { + pub fn nakoutic(&mut self) -> NAKOUTIC_W { NAKOUTIC_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakinic(&mut self) -> NAKINIC_W<4> { + pub fn nakinic(&mut self) -> NAKINIC_W { NAKINIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn stalledic(&mut self) -> STALLEDIC_W<6> { + pub fn stalledic(&mut self) -> STALLEDIC_W { STALLEDIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketc(&mut self) -> SHORTPACKETC_W<7> { + pub fn shortpacketc(&mut self) -> SHORTPACKETC_W { SHORTPACKETC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devepticr_intrpt_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTICR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for DEVEPTICR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devepticr_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devepticr_intrpt_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTICR_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_iso_mode.rs index 4581e2c2..7a55285c 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devepticr_iso_mode.rs @@ -1,104 +1,84 @@ #[doc = "Register `DEVEPTICR_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIC` writer - Transmitted IN Data Interrupt Clear"] -pub type TXINIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type TXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type RXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIC` writer - Underflow Interrupt Clear"] -pub type UNDERFIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type UNDERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOINERRIC` writer - High Bandwidth Isochronous IN Underflow Error Interrupt Clear"] -pub type HBISOINERRIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type HBISOINERRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOFLUSHIC` writer - High Bandwidth Isochronous IN Flush Interrupt Clear"] -pub type HBISOFLUSHIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type HBISOFLUSHIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERRIC` writer - CRC Error Interrupt Clear"] -pub type CRCERRIC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type CRCERRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTICR_ISO_MODE_SPEC, O>; +pub type SHORTPACKETC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinic(&mut self) -> TXINIC_W<0> { + pub fn txinic(&mut self) -> TXINIC_W { TXINIC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutic(&mut self) -> RXOUTIC_W<1> { + pub fn rxoutic(&mut self) -> RXOUTIC_W { RXOUTIC_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn underfic(&mut self) -> UNDERFIC_W<2> { + pub fn underfic(&mut self) -> UNDERFIC_W { UNDERFIC_W::new(self) } #[doc = "Bit 3 - High Bandwidth Isochronous IN Underflow Error Interrupt Clear"] #[inline(always)] #[must_use] - pub fn hbisoinerric(&mut self) -> HBISOINERRIC_W<3> { + pub fn hbisoinerric(&mut self) -> HBISOINERRIC_W { HBISOINERRIC_W::new(self) } #[doc = "Bit 4 - High Bandwidth Isochronous IN Flush Interrupt Clear"] #[inline(always)] #[must_use] - pub fn hbisoflushic(&mut self) -> HBISOFLUSHIC_W<4> { + pub fn hbisoflushic(&mut self) -> HBISOFLUSHIC_W { HBISOFLUSHIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Clear"] #[inline(always)] #[must_use] - pub fn crcerric(&mut self) -> CRCERRIC_W<6> { + pub fn crcerric(&mut self) -> CRCERRIC_W { CRCERRIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketc(&mut self) -> SHORTPACKETC_W<7> { + pub fn shortpacketc(&mut self) -> SHORTPACKETC_W { SHORTPACKETC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devepticr_iso_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devepticr_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTICR_ISO_MODE_SPEC; impl crate::RegisterSpec for DEVEPTICR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devepticr_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devepticr_iso_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTICR_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_blk_mode.rs index 70d4f847..98bf6c9c 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_blk_mode.rs @@ -1,144 +1,124 @@ #[doc = "Register `DEVEPTIDR_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINEC` writer - Transmitted IN Interrupt Clear"] -pub type TXINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type TXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTEC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type RXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPEC` writer - Received SETUP Interrupt Clear"] -pub type RXSTPEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type RXSTPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTEC` writer - NAKed OUT Interrupt Clear"] -pub type NAKOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type NAKOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINEC` writer - NAKed IN Interrupt Clear"] -pub type NAKINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type NAKINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFEC` writer - Overflow Interrupt Clear"] -pub type OVERFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type OVERFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDEC` writer - STALLed Interrupt Clear"] -pub type STALLEDEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type STALLEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETEC` writer - Shortpacket Interrupt Clear"] -pub type SHORTPACKETEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type SHORTPACKETEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Interrupt Clear"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Clear"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAC` writer - Endpoint Interrupts Disable HDMA Request Clear"] -pub type EPDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type EPDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETDISC` writer - NYET Token Disable Clear"] -pub type NYETDISC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type NYETDISC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLRQC` writer - STALL Request Clear"] -pub type STALLRQC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_BLK_MODE_SPEC, O>; +pub type STALLRQC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinec(&mut self) -> TXINEC_W<0> { + pub fn txinec(&mut self) -> TXINEC_W { TXINEC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutec(&mut self) -> RXOUTEC_W<1> { + pub fn rxoutec(&mut self) -> RXOUTEC_W { RXOUTEC_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstpec(&mut self) -> RXSTPEC_W<2> { + pub fn rxstpec(&mut self) -> RXSTPEC_W { RXSTPEC_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakoutec(&mut self) -> NAKOUTEC_W<3> { + pub fn nakoutec(&mut self) -> NAKOUTEC_W { NAKOUTEC_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakinec(&mut self) -> NAKINEC_W<4> { + pub fn nakinec(&mut self) -> NAKINEC_W { NAKINEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfec(&mut self) -> OVERFEC_W<5> { + pub fn overfec(&mut self) -> OVERFEC_W { OVERFEC_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn stalledec(&mut self) -> STALLEDEC_W<6> { + pub fn stalledec(&mut self) -> STALLEDEC_W { STALLEDEC_W::new(self) } #[doc = "Bit 7 - Shortpacket Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W<7> { + pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W { SHORTPACKETEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Clear"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Clear"] #[inline(always)] #[must_use] - pub fn epdishdmac(&mut self) -> EPDISHDMAC_W<16> { + pub fn epdishdmac(&mut self) -> EPDISHDMAC_W { EPDISHDMAC_W::new(self) } #[doc = "Bit 17 - NYET Token Disable Clear"] #[inline(always)] #[must_use] - pub fn nyetdisc(&mut self) -> NYETDISC_W<17> { + pub fn nyetdisc(&mut self) -> NYETDISC_W { NYETDISC_W::new(self) } #[doc = "Bit 19 - STALL Request Clear"] #[inline(always)] #[must_use] - pub fn stallrqc(&mut self) -> STALLRQC_W<19> { + pub fn stallrqc(&mut self) -> STALLRQC_W { STALLRQC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptidr_blk_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIDR_BLK_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIDR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptidr_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptidr_blk_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIDR_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_ctrl_mode.rs index d8ea5b9f..300e74ae 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_ctrl_mode.rs @@ -1,144 +1,124 @@ #[doc = "Register `DEVEPTIDR_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINEC` writer - Transmitted IN Interrupt Clear"] -pub type TXINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type TXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTEC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type RXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPEC` writer - Received SETUP Interrupt Clear"] -pub type RXSTPEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type RXSTPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTEC` writer - NAKed OUT Interrupt Clear"] -pub type NAKOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type NAKOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINEC` writer - NAKed IN Interrupt Clear"] -pub type NAKINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type NAKINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFEC` writer - Overflow Interrupt Clear"] -pub type OVERFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type OVERFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDEC` writer - STALLed Interrupt Clear"] -pub type STALLEDEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type STALLEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETEC` writer - Shortpacket Interrupt Clear"] -pub type SHORTPACKETEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Interrupt Clear"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Clear"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAC` writer - Endpoint Interrupts Disable HDMA Request Clear"] -pub type EPDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type EPDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETDISC` writer - NYET Token Disable Clear"] -pub type NYETDISC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type NYETDISC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLRQC` writer - STALL Request Clear"] -pub type STALLRQC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_CTRL_MODE_SPEC, O>; +pub type STALLRQC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinec(&mut self) -> TXINEC_W<0> { + pub fn txinec(&mut self) -> TXINEC_W { TXINEC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutec(&mut self) -> RXOUTEC_W<1> { + pub fn rxoutec(&mut self) -> RXOUTEC_W { RXOUTEC_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstpec(&mut self) -> RXSTPEC_W<2> { + pub fn rxstpec(&mut self) -> RXSTPEC_W { RXSTPEC_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakoutec(&mut self) -> NAKOUTEC_W<3> { + pub fn nakoutec(&mut self) -> NAKOUTEC_W { NAKOUTEC_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakinec(&mut self) -> NAKINEC_W<4> { + pub fn nakinec(&mut self) -> NAKINEC_W { NAKINEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfec(&mut self) -> OVERFEC_W<5> { + pub fn overfec(&mut self) -> OVERFEC_W { OVERFEC_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn stalledec(&mut self) -> STALLEDEC_W<6> { + pub fn stalledec(&mut self) -> STALLEDEC_W { STALLEDEC_W::new(self) } #[doc = "Bit 7 - Shortpacket Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W<7> { + pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W { SHORTPACKETEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Clear"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Clear"] #[inline(always)] #[must_use] - pub fn epdishdmac(&mut self) -> EPDISHDMAC_W<16> { + pub fn epdishdmac(&mut self) -> EPDISHDMAC_W { EPDISHDMAC_W::new(self) } #[doc = "Bit 17 - NYET Token Disable Clear"] #[inline(always)] #[must_use] - pub fn nyetdisc(&mut self) -> NYETDISC_W<17> { + pub fn nyetdisc(&mut self) -> NYETDISC_W { NYETDISC_W::new(self) } #[doc = "Bit 19 - STALL Request Clear"] #[inline(always)] #[must_use] - pub fn stallrqc(&mut self) -> STALLRQC_W<19> { + pub fn stallrqc(&mut self) -> STALLRQC_W { STALLRQC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptidr_ctrl_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIDR_CTRL_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIDR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptidr_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptidr_ctrl_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIDR_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_intrpt_mode.rs index 9b9bc9cc..b5e1c4fa 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_intrpt_mode.rs @@ -1,144 +1,124 @@ #[doc = "Register `DEVEPTIDR_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINEC` writer - Transmitted IN Interrupt Clear"] -pub type TXINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type TXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTEC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type RXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPEC` writer - Received SETUP Interrupt Clear"] -pub type RXSTPEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type RXSTPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTEC` writer - NAKed OUT Interrupt Clear"] -pub type NAKOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type NAKOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINEC` writer - NAKed IN Interrupt Clear"] -pub type NAKINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type NAKINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFEC` writer - Overflow Interrupt Clear"] -pub type OVERFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type OVERFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDEC` writer - STALLed Interrupt Clear"] -pub type STALLEDEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type STALLEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETEC` writer - Shortpacket Interrupt Clear"] -pub type SHORTPACKETEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Interrupt Clear"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Clear"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAC` writer - Endpoint Interrupts Disable HDMA Request Clear"] -pub type EPDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type EPDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETDISC` writer - NYET Token Disable Clear"] -pub type NYETDISC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type NYETDISC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLRQC` writer - STALL Request Clear"] -pub type STALLRQC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_INTRPT_MODE_SPEC, O>; +pub type STALLRQC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinec(&mut self) -> TXINEC_W<0> { + pub fn txinec(&mut self) -> TXINEC_W { TXINEC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutec(&mut self) -> RXOUTEC_W<1> { + pub fn rxoutec(&mut self) -> RXOUTEC_W { RXOUTEC_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstpec(&mut self) -> RXSTPEC_W<2> { + pub fn rxstpec(&mut self) -> RXSTPEC_W { RXSTPEC_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakoutec(&mut self) -> NAKOUTEC_W<3> { + pub fn nakoutec(&mut self) -> NAKOUTEC_W { NAKOUTEC_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakinec(&mut self) -> NAKINEC_W<4> { + pub fn nakinec(&mut self) -> NAKINEC_W { NAKINEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfec(&mut self) -> OVERFEC_W<5> { + pub fn overfec(&mut self) -> OVERFEC_W { OVERFEC_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn stalledec(&mut self) -> STALLEDEC_W<6> { + pub fn stalledec(&mut self) -> STALLEDEC_W { STALLEDEC_W::new(self) } #[doc = "Bit 7 - Shortpacket Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W<7> { + pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W { SHORTPACKETEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Clear"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Clear"] #[inline(always)] #[must_use] - pub fn epdishdmac(&mut self) -> EPDISHDMAC_W<16> { + pub fn epdishdmac(&mut self) -> EPDISHDMAC_W { EPDISHDMAC_W::new(self) } #[doc = "Bit 17 - NYET Token Disable Clear"] #[inline(always)] #[must_use] - pub fn nyetdisc(&mut self) -> NYETDISC_W<17> { + pub fn nyetdisc(&mut self) -> NYETDISC_W { NYETDISC_W::new(self) } #[doc = "Bit 19 - STALL Request Clear"] #[inline(always)] #[must_use] - pub fn stallrqc(&mut self) -> STALLRQC_W<19> { + pub fn stallrqc(&mut self) -> STALLRQC_W { STALLRQC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptidr_intrpt_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIDR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIDR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptidr_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptidr_intrpt_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIDR_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_iso_mode.rs index 67b506ba..3421d295 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptidr_iso_mode.rs @@ -1,144 +1,124 @@ #[doc = "Register `DEVEPTIDR_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINEC` writer - Transmitted IN Interrupt Clear"] -pub type TXINEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type TXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTEC` writer - Received OUT Data Interrupt Clear"] -pub type RXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type RXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFEC` writer - Underflow Interrupt Clear"] -pub type UNDERFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type UNDERFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOINERREC` writer - High Bandwidth Isochronous IN Underflow Error Interrupt Clear"] -pub type HBISOINERREC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type HBISOINERREC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOFLUSHEC` writer - High Bandwidth Isochronous IN Flush Interrupt Clear"] -pub type HBISOFLUSHEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type HBISOFLUSHEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFEC` writer - Overflow Interrupt Clear"] -pub type OVERFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type OVERFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETEC` writer - Shortpacket Interrupt Clear"] -pub type SHORTPACKETEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type SHORTPACKETEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MDATAEC` writer - MData Interrupt Clear"] -pub type MDATAEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type MDATAEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAXEC` writer - DataX Interrupt Clear"] -pub type DATAXEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type DATAXEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERRORTRANSEC` writer - Transaction Error Interrupt Clear"] -pub type ERRORTRANSEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type ERRORTRANSEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Interrupt Clear"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Clear"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAC` writer - Endpoint Interrupts Disable HDMA Request Clear"] -pub type EPDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIDR_ISO_MODE_SPEC, O>; +pub type EPDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txinec(&mut self) -> TXINEC_W<0> { + pub fn txinec(&mut self) -> TXINEC_W { TXINEC_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxoutec(&mut self) -> RXOUTEC_W<1> { + pub fn rxoutec(&mut self) -> RXOUTEC_W { RXOUTEC_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn underfec(&mut self) -> UNDERFEC_W<2> { + pub fn underfec(&mut self) -> UNDERFEC_W { UNDERFEC_W::new(self) } #[doc = "Bit 3 - High Bandwidth Isochronous IN Underflow Error Interrupt Clear"] #[inline(always)] #[must_use] - pub fn hbisoinerrec(&mut self) -> HBISOINERREC_W<3> { + pub fn hbisoinerrec(&mut self) -> HBISOINERREC_W { HBISOINERREC_W::new(self) } #[doc = "Bit 4 - High Bandwidth Isochronous IN Flush Interrupt Clear"] #[inline(always)] #[must_use] - pub fn hbisoflushec(&mut self) -> HBISOFLUSHEC_W<4> { + pub fn hbisoflushec(&mut self) -> HBISOFLUSHEC_W { HBISOFLUSHEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfec(&mut self) -> OVERFEC_W<5> { + pub fn overfec(&mut self) -> OVERFEC_W { OVERFEC_W::new(self) } #[doc = "Bit 7 - Shortpacket Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W<7> { + pub fn shortpacketec(&mut self) -> SHORTPACKETEC_W { SHORTPACKETEC_W::new(self) } #[doc = "Bit 8 - MData Interrupt Clear"] #[inline(always)] #[must_use] - pub fn mdataec(&mut self) -> MDATAEC_W<8> { + pub fn mdataec(&mut self) -> MDATAEC_W { MDATAEC_W::new(self) } #[doc = "Bit 9 - DataX Interrupt Clear"] #[inline(always)] #[must_use] - pub fn dataxec(&mut self) -> DATAXEC_W<9> { + pub fn dataxec(&mut self) -> DATAXEC_W { DATAXEC_W::new(self) } #[doc = "Bit 10 - Transaction Error Interrupt Clear"] #[inline(always)] #[must_use] - pub fn errortransec(&mut self) -> ERRORTRANSEC_W<10> { + pub fn errortransec(&mut self) -> ERRORTRANSEC_W { ERRORTRANSEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Clear"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Clear"] #[inline(always)] #[must_use] - pub fn epdishdmac(&mut self) -> EPDISHDMAC_W<16> { + pub fn epdishdmac(&mut self) -> EPDISHDMAC_W { EPDISHDMAC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptidr_iso_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptidr_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIDR_ISO_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIDR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptidr_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptidr_iso_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIDR_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_blk_mode.rs index 1aa6d5a1..ae3565e7 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_blk_mode.rs @@ -1,160 +1,140 @@ #[doc = "Register `DEVEPTIER_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINES` writer - Transmitted IN Data Interrupt Enable"] -pub type TXINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type TXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTES` writer - Received OUT Data Interrupt Enable"] -pub type RXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type RXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPES` writer - Received SETUP Interrupt Enable"] -pub type RXSTPES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type RXSTPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTES` writer - NAKed OUT Interrupt Enable"] -pub type NAKOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type NAKOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINES` writer - NAKed IN Interrupt Enable"] -pub type NAKINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type NAKINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFES` writer - Overflow Interrupt Enable"] -pub type OVERFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type OVERFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDES` writer - STALLed Interrupt Enable"] -pub type STALLEDES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type STALLEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type SHORTPACKETES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Interrupt Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILLBKS` writer - Kill IN Bank"] -pub type KILLBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type KILLBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONS` writer - FIFO Control"] -pub type FIFOCONS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type FIFOCONS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAS` writer - Endpoint Interrupts Disable HDMA Request Enable"] -pub type EPDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type EPDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETDISS` writer - NYET Token Disable Enable"] -pub type NYETDISS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type NYETDISS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLRQS` writer - STALL Request Enable"] -pub type STALLRQS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_BLK_MODE_SPEC, O>; +pub type STALLRQS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txines(&mut self) -> TXINES_W<0> { + pub fn txines(&mut self) -> TXINES_W { TXINES_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxoutes(&mut self) -> RXOUTES_W<1> { + pub fn rxoutes(&mut self) -> RXOUTES_W { RXOUTES_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxstpes(&mut self) -> RXSTPES_W<2> { + pub fn rxstpes(&mut self) -> RXSTPES_W { RXSTPES_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakoutes(&mut self) -> NAKOUTES_W<3> { + pub fn nakoutes(&mut self) -> NAKOUTES_W { NAKOUTES_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakines(&mut self) -> NAKINES_W<4> { + pub fn nakines(&mut self) -> NAKINES_W { NAKINES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfes(&mut self) -> OVERFES_W<5> { + pub fn overfes(&mut self) -> OVERFES_W { OVERFES_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn stalledes(&mut self) -> STALLEDES_W<6> { + pub fn stalledes(&mut self) -> STALLEDES_W { STALLEDES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketes(&mut self) -> SHORTPACKETES_W<7> { + pub fn shortpacketes(&mut self) -> SHORTPACKETES_W { SHORTPACKETES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 13 - Kill IN Bank"] #[inline(always)] #[must_use] - pub fn killbks(&mut self) -> KILLBKS_W<13> { + pub fn killbks(&mut self) -> KILLBKS_W { KILLBKS_W::new(self) } #[doc = "Bit 14 - FIFO Control"] #[inline(always)] #[must_use] - pub fn fifocons(&mut self) -> FIFOCONS_W<14> { + pub fn fifocons(&mut self) -> FIFOCONS_W { FIFOCONS_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn epdishdmas(&mut self) -> EPDISHDMAS_W<16> { + pub fn epdishdmas(&mut self) -> EPDISHDMAS_W { EPDISHDMAS_W::new(self) } #[doc = "Bit 17 - NYET Token Disable Enable"] #[inline(always)] #[must_use] - pub fn nyetdiss(&mut self) -> NYETDISS_W<17> { + pub fn nyetdiss(&mut self) -> NYETDISS_W { NYETDISS_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Bit 19 - STALL Request Enable"] #[inline(always)] #[must_use] - pub fn stallrqs(&mut self) -> STALLRQS_W<19> { + pub fn stallrqs(&mut self) -> STALLRQS_W { STALLRQS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptier_blk_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIER_BLK_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIER_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptier_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptier_blk_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIER_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_ctrl_mode.rs index 87f63c02..51ab6261 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_ctrl_mode.rs @@ -1,160 +1,140 @@ #[doc = "Register `DEVEPTIER_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINES` writer - Transmitted IN Data Interrupt Enable"] -pub type TXINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type TXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTES` writer - Received OUT Data Interrupt Enable"] -pub type RXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type RXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPES` writer - Received SETUP Interrupt Enable"] -pub type RXSTPES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type RXSTPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTES` writer - NAKed OUT Interrupt Enable"] -pub type NAKOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type NAKOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINES` writer - NAKed IN Interrupt Enable"] -pub type NAKINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type NAKINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFES` writer - Overflow Interrupt Enable"] -pub type OVERFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type OVERFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDES` writer - STALLed Interrupt Enable"] -pub type STALLEDES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type STALLEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Interrupt Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILLBKS` writer - Kill IN Bank"] -pub type KILLBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type KILLBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONS` writer - FIFO Control"] -pub type FIFOCONS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type FIFOCONS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAS` writer - Endpoint Interrupts Disable HDMA Request Enable"] -pub type EPDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type EPDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETDISS` writer - NYET Token Disable Enable"] -pub type NYETDISS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type NYETDISS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLRQS` writer - STALL Request Enable"] -pub type STALLRQS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_CTRL_MODE_SPEC, O>; +pub type STALLRQS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txines(&mut self) -> TXINES_W<0> { + pub fn txines(&mut self) -> TXINES_W { TXINES_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxoutes(&mut self) -> RXOUTES_W<1> { + pub fn rxoutes(&mut self) -> RXOUTES_W { RXOUTES_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxstpes(&mut self) -> RXSTPES_W<2> { + pub fn rxstpes(&mut self) -> RXSTPES_W { RXSTPES_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakoutes(&mut self) -> NAKOUTES_W<3> { + pub fn nakoutes(&mut self) -> NAKOUTES_W { NAKOUTES_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakines(&mut self) -> NAKINES_W<4> { + pub fn nakines(&mut self) -> NAKINES_W { NAKINES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfes(&mut self) -> OVERFES_W<5> { + pub fn overfes(&mut self) -> OVERFES_W { OVERFES_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn stalledes(&mut self) -> STALLEDES_W<6> { + pub fn stalledes(&mut self) -> STALLEDES_W { STALLEDES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketes(&mut self) -> SHORTPACKETES_W<7> { + pub fn shortpacketes(&mut self) -> SHORTPACKETES_W { SHORTPACKETES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 13 - Kill IN Bank"] #[inline(always)] #[must_use] - pub fn killbks(&mut self) -> KILLBKS_W<13> { + pub fn killbks(&mut self) -> KILLBKS_W { KILLBKS_W::new(self) } #[doc = "Bit 14 - FIFO Control"] #[inline(always)] #[must_use] - pub fn fifocons(&mut self) -> FIFOCONS_W<14> { + pub fn fifocons(&mut self) -> FIFOCONS_W { FIFOCONS_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn epdishdmas(&mut self) -> EPDISHDMAS_W<16> { + pub fn epdishdmas(&mut self) -> EPDISHDMAS_W { EPDISHDMAS_W::new(self) } #[doc = "Bit 17 - NYET Token Disable Enable"] #[inline(always)] #[must_use] - pub fn nyetdiss(&mut self) -> NYETDISS_W<17> { + pub fn nyetdiss(&mut self) -> NYETDISS_W { NYETDISS_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Bit 19 - STALL Request Enable"] #[inline(always)] #[must_use] - pub fn stallrqs(&mut self) -> STALLRQS_W<19> { + pub fn stallrqs(&mut self) -> STALLRQS_W { STALLRQS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptier_ctrl_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIER_CTRL_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIER_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptier_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptier_ctrl_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIER_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_intrpt_mode.rs index 4d21468b..2f75fe00 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_intrpt_mode.rs @@ -1,160 +1,140 @@ #[doc = "Register `DEVEPTIER_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINES` writer - Transmitted IN Data Interrupt Enable"] -pub type TXINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type TXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTES` writer - Received OUT Data Interrupt Enable"] -pub type RXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type RXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPES` writer - Received SETUP Interrupt Enable"] -pub type RXSTPES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type RXSTPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTES` writer - NAKed OUT Interrupt Enable"] -pub type NAKOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type NAKOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINES` writer - NAKed IN Interrupt Enable"] -pub type NAKINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type NAKINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFES` writer - Overflow Interrupt Enable"] -pub type OVERFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type OVERFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDES` writer - STALLed Interrupt Enable"] -pub type STALLEDES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type STALLEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Interrupt Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILLBKS` writer - Kill IN Bank"] -pub type KILLBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type KILLBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONS` writer - FIFO Control"] -pub type FIFOCONS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type FIFOCONS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAS` writer - Endpoint Interrupts Disable HDMA Request Enable"] -pub type EPDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type EPDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NYETDISS` writer - NYET Token Disable Enable"] -pub type NYETDISS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type NYETDISS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLRQS` writer - STALL Request Enable"] -pub type STALLRQS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_INTRPT_MODE_SPEC, O>; +pub type STALLRQS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txines(&mut self) -> TXINES_W<0> { + pub fn txines(&mut self) -> TXINES_W { TXINES_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxoutes(&mut self) -> RXOUTES_W<1> { + pub fn rxoutes(&mut self) -> RXOUTES_W { RXOUTES_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxstpes(&mut self) -> RXSTPES_W<2> { + pub fn rxstpes(&mut self) -> RXSTPES_W { RXSTPES_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakoutes(&mut self) -> NAKOUTES_W<3> { + pub fn nakoutes(&mut self) -> NAKOUTES_W { NAKOUTES_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakines(&mut self) -> NAKINES_W<4> { + pub fn nakines(&mut self) -> NAKINES_W { NAKINES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfes(&mut self) -> OVERFES_W<5> { + pub fn overfes(&mut self) -> OVERFES_W { OVERFES_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn stalledes(&mut self) -> STALLEDES_W<6> { + pub fn stalledes(&mut self) -> STALLEDES_W { STALLEDES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketes(&mut self) -> SHORTPACKETES_W<7> { + pub fn shortpacketes(&mut self) -> SHORTPACKETES_W { SHORTPACKETES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 13 - Kill IN Bank"] #[inline(always)] #[must_use] - pub fn killbks(&mut self) -> KILLBKS_W<13> { + pub fn killbks(&mut self) -> KILLBKS_W { KILLBKS_W::new(self) } #[doc = "Bit 14 - FIFO Control"] #[inline(always)] #[must_use] - pub fn fifocons(&mut self) -> FIFOCONS_W<14> { + pub fn fifocons(&mut self) -> FIFOCONS_W { FIFOCONS_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn epdishdmas(&mut self) -> EPDISHDMAS_W<16> { + pub fn epdishdmas(&mut self) -> EPDISHDMAS_W { EPDISHDMAS_W::new(self) } #[doc = "Bit 17 - NYET Token Disable Enable"] #[inline(always)] #[must_use] - pub fn nyetdiss(&mut self) -> NYETDISS_W<17> { + pub fn nyetdiss(&mut self) -> NYETDISS_W { NYETDISS_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Bit 19 - STALL Request Enable"] #[inline(always)] #[must_use] - pub fn stallrqs(&mut self) -> STALLRQS_W<19> { + pub fn stallrqs(&mut self) -> STALLRQS_W { STALLRQS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptier_intrpt_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIER_INTRPT_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIER_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptier_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptier_intrpt_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIER_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_iso_mode.rs index a4f97edc..77ed93b2 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptier_iso_mode.rs @@ -1,168 +1,148 @@ #[doc = "Register `DEVEPTIER_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINES` writer - Transmitted IN Data Interrupt Enable"] -pub type TXINES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type TXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTES` writer - Received OUT Data Interrupt Enable"] -pub type RXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type RXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFES` writer - Underflow Interrupt Enable"] -pub type UNDERFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type UNDERFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOINERRES` writer - High Bandwidth Isochronous IN Underflow Error Interrupt Enable"] -pub type HBISOINERRES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type HBISOINERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOFLUSHES` writer - High Bandwidth Isochronous IN Flush Interrupt Enable"] -pub type HBISOFLUSHES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type HBISOFLUSHES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFES` writer - Overflow Interrupt Enable"] -pub type OVERFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type OVERFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERRES` writer - CRC Error Interrupt Enable"] -pub type CRCERRES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type CRCERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type SHORTPACKETES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MDATAES` writer - MData Interrupt Enable"] -pub type MDATAES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type MDATAES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAXES` writer - DataX Interrupt Enable"] -pub type DATAXES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type DATAXES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ERRORTRANSES` writer - Transaction Error Interrupt Enable"] -pub type ERRORTRANSES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type ERRORTRANSES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Interrupt Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `KILLBKS` writer - Kill IN Bank"] -pub type KILLBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type KILLBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONS` writer - FIFO Control"] -pub type FIFOCONS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type FIFOCONS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EPDISHDMAS` writer - Endpoint Interrupts Disable HDMA Request Enable"] -pub type EPDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type EPDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIER_ISO_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txines(&mut self) -> TXINES_W<0> { + pub fn txines(&mut self) -> TXINES_W { TXINES_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxoutes(&mut self) -> RXOUTES_W<1> { + pub fn rxoutes(&mut self) -> RXOUTES_W { RXOUTES_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn underfes(&mut self) -> UNDERFES_W<2> { + pub fn underfes(&mut self) -> UNDERFES_W { UNDERFES_W::new(self) } #[doc = "Bit 3 - High Bandwidth Isochronous IN Underflow Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn hbisoinerres(&mut self) -> HBISOINERRES_W<3> { + pub fn hbisoinerres(&mut self) -> HBISOINERRES_W { HBISOINERRES_W::new(self) } #[doc = "Bit 4 - High Bandwidth Isochronous IN Flush Interrupt Enable"] #[inline(always)] #[must_use] - pub fn hbisoflushes(&mut self) -> HBISOFLUSHES_W<4> { + pub fn hbisoflushes(&mut self) -> HBISOFLUSHES_W { HBISOFLUSHES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfes(&mut self) -> OVERFES_W<5> { + pub fn overfes(&mut self) -> OVERFES_W { OVERFES_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn crcerres(&mut self) -> CRCERRES_W<6> { + pub fn crcerres(&mut self) -> CRCERRES_W { CRCERRES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketes(&mut self) -> SHORTPACKETES_W<7> { + pub fn shortpacketes(&mut self) -> SHORTPACKETES_W { SHORTPACKETES_W::new(self) } #[doc = "Bit 8 - MData Interrupt Enable"] #[inline(always)] #[must_use] - pub fn mdataes(&mut self) -> MDATAES_W<8> { + pub fn mdataes(&mut self) -> MDATAES_W { MDATAES_W::new(self) } #[doc = "Bit 9 - DataX Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dataxes(&mut self) -> DATAXES_W<9> { + pub fn dataxes(&mut self) -> DATAXES_W { DATAXES_W::new(self) } #[doc = "Bit 10 - Transaction Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn errortranses(&mut self) -> ERRORTRANSES_W<10> { + pub fn errortranses(&mut self) -> ERRORTRANSES_W { ERRORTRANSES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 13 - Kill IN Bank"] #[inline(always)] #[must_use] - pub fn killbks(&mut self) -> KILLBKS_W<13> { + pub fn killbks(&mut self) -> KILLBKS_W { KILLBKS_W::new(self) } #[doc = "Bit 14 - FIFO Control"] #[inline(always)] #[must_use] - pub fn fifocons(&mut self) -> FIFOCONS_W<14> { + pub fn fifocons(&mut self) -> FIFOCONS_W { FIFOCONS_W::new(self) } #[doc = "Bit 16 - Endpoint Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn epdishdmas(&mut self) -> EPDISHDMAS_W<16> { + pub fn epdishdmas(&mut self) -> EPDISHDMAS_W { EPDISHDMAS_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptier_iso_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptier_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIER_ISO_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIER_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptier_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptier_iso_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIER_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_blk_mode.rs index 1ef9a551..6185feb7 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_blk_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `DEVEPTIFR_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIS` writer - Transmitted IN Data Interrupt Set"] -pub type TXINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type TXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIS` writer - Received OUT Data Interrupt Set"] -pub type RXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type RXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPIS` writer - Received SETUP Interrupt Set"] -pub type RXSTPIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type RXSTPIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTIS` writer - NAKed OUT Interrupt Set"] -pub type NAKOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type NAKOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINIS` writer - NAKed IN Interrupt Set"] -pub type NAKINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type NAKINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDIS` writer - STALLed Interrupt Set"] -pub type STALLEDIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type STALLEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type SHORTPACKETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Interrupt Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_BLK_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txinis(&mut self) -> TXINIS_W<0> { + pub fn txinis(&mut self) -> TXINIS_W { TXINIS_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxoutis(&mut self) -> RXOUTIS_W<1> { + pub fn rxoutis(&mut self) -> RXOUTIS_W { RXOUTIS_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxstpis(&mut self) -> RXSTPIS_W<2> { + pub fn rxstpis(&mut self) -> RXSTPIS_W { RXSTPIS_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakoutis(&mut self) -> NAKOUTIS_W<3> { + pub fn nakoutis(&mut self) -> NAKOUTIS_W { NAKOUTIS_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakinis(&mut self) -> NAKINIS_W<4> { + pub fn nakinis(&mut self) -> NAKINIS_W { NAKINIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Set"] #[inline(always)] #[must_use] - pub fn stalledis(&mut self) -> STALLEDIS_W<6> { + pub fn stalledis(&mut self) -> STALLEDIS_W { STALLEDIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpackets(&mut self) -> SHORTPACKETS_W<7> { + pub fn shortpackets(&mut self) -> SHORTPACKETS_W { SHORTPACKETS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptifr_blk_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIFR_BLK_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIFR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptifr_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptifr_blk_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIFR_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_ctrl_mode.rs index 6f994664..77402dc5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_ctrl_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `DEVEPTIFR_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIS` writer - Transmitted IN Data Interrupt Set"] -pub type TXINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type TXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIS` writer - Received OUT Data Interrupt Set"] -pub type RXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type RXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPIS` writer - Received SETUP Interrupt Set"] -pub type RXSTPIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type RXSTPIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTIS` writer - NAKed OUT Interrupt Set"] -pub type NAKOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type NAKOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINIS` writer - NAKed IN Interrupt Set"] -pub type NAKINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type NAKINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDIS` writer - STALLed Interrupt Set"] -pub type STALLEDIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type STALLEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Interrupt Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_CTRL_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txinis(&mut self) -> TXINIS_W<0> { + pub fn txinis(&mut self) -> TXINIS_W { TXINIS_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxoutis(&mut self) -> RXOUTIS_W<1> { + pub fn rxoutis(&mut self) -> RXOUTIS_W { RXOUTIS_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxstpis(&mut self) -> RXSTPIS_W<2> { + pub fn rxstpis(&mut self) -> RXSTPIS_W { RXSTPIS_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakoutis(&mut self) -> NAKOUTIS_W<3> { + pub fn nakoutis(&mut self) -> NAKOUTIS_W { NAKOUTIS_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakinis(&mut self) -> NAKINIS_W<4> { + pub fn nakinis(&mut self) -> NAKINIS_W { NAKINIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Set"] #[inline(always)] #[must_use] - pub fn stalledis(&mut self) -> STALLEDIS_W<6> { + pub fn stalledis(&mut self) -> STALLEDIS_W { STALLEDIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpackets(&mut self) -> SHORTPACKETS_W<7> { + pub fn shortpackets(&mut self) -> SHORTPACKETS_W { SHORTPACKETS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptifr_ctrl_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIFR_CTRL_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIFR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptifr_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptifr_ctrl_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIFR_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_intrpt_mode.rs index 8a6b9c52..ff72979b 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_intrpt_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `DEVEPTIFR_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIS` writer - Transmitted IN Data Interrupt Set"] -pub type TXINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type TXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIS` writer - Received OUT Data Interrupt Set"] -pub type RXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type RXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTPIS` writer - Received SETUP Interrupt Set"] -pub type RXSTPIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type RXSTPIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKOUTIS` writer - NAKed OUT Interrupt Set"] -pub type NAKOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type NAKOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKINIS` writer - NAKed IN Interrupt Set"] -pub type NAKINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type NAKINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `STALLEDIS` writer - STALLed Interrupt Set"] -pub type STALLEDIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type STALLEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Interrupt Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_INTRPT_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txinis(&mut self) -> TXINIS_W<0> { + pub fn txinis(&mut self) -> TXINIS_W { TXINIS_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxoutis(&mut self) -> RXOUTIS_W<1> { + pub fn rxoutis(&mut self) -> RXOUTIS_W { RXOUTIS_W::new(self) } #[doc = "Bit 2 - Received SETUP Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxstpis(&mut self) -> RXSTPIS_W<2> { + pub fn rxstpis(&mut self) -> RXSTPIS_W { RXSTPIS_W::new(self) } #[doc = "Bit 3 - NAKed OUT Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakoutis(&mut self) -> NAKOUTIS_W<3> { + pub fn nakoutis(&mut self) -> NAKOUTIS_W { NAKOUTIS_W::new(self) } #[doc = "Bit 4 - NAKed IN Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakinis(&mut self) -> NAKINIS_W<4> { + pub fn nakinis(&mut self) -> NAKINIS_W { NAKINIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - STALLed Interrupt Set"] #[inline(always)] #[must_use] - pub fn stalledis(&mut self) -> STALLEDIS_W<6> { + pub fn stalledis(&mut self) -> STALLEDIS_W { STALLEDIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpackets(&mut self) -> SHORTPACKETS_W<7> { + pub fn shortpackets(&mut self) -> SHORTPACKETS_W { SHORTPACKETS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptifr_intrpt_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIFR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIFR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptifr_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptifr_intrpt_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIFR_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_iso_mode.rs index ec1fe0bf..a23e5360 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptifr_iso_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `DEVEPTIFR_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TXINIS` writer - Transmitted IN Data Interrupt Set"] -pub type TXINIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type TXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXOUTIS` writer - Received OUT Data Interrupt Set"] -pub type RXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type RXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIS` writer - Underflow Interrupt Set"] -pub type UNDERFIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type UNDERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOINERRIS` writer - High Bandwidth Isochronous IN Underflow Error Interrupt Set"] -pub type HBISOINERRIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type HBISOINERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HBISOFLUSHIS` writer - High Bandwidth Isochronous IN Flush Interrupt Set"] -pub type HBISOFLUSHIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type HBISOFLUSHIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERRIS` writer - CRC Error Interrupt Set"] -pub type CRCERRIS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type CRCERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type SHORTPACKETS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Interrupt Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, DEVEPTIFR_ISO_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Transmitted IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txinis(&mut self) -> TXINIS_W<0> { + pub fn txinis(&mut self) -> TXINIS_W { TXINIS_W::new(self) } #[doc = "Bit 1 - Received OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxoutis(&mut self) -> RXOUTIS_W<1> { + pub fn rxoutis(&mut self) -> RXOUTIS_W { RXOUTIS_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn underfis(&mut self) -> UNDERFIS_W<2> { + pub fn underfis(&mut self) -> UNDERFIS_W { UNDERFIS_W::new(self) } #[doc = "Bit 3 - High Bandwidth Isochronous IN Underflow Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn hbisoinerris(&mut self) -> HBISOINERRIS_W<3> { + pub fn hbisoinerris(&mut self) -> HBISOINERRIS_W { HBISOINERRIS_W::new(self) } #[doc = "Bit 4 - High Bandwidth Isochronous IN Flush Interrupt Set"] #[inline(always)] #[must_use] - pub fn hbisoflushis(&mut self) -> HBISOFLUSHIS_W<4> { + pub fn hbisoflushis(&mut self) -> HBISOFLUSHIS_W { HBISOFLUSHIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn crcerris(&mut self) -> CRCERRIS_W<6> { + pub fn crcerris(&mut self) -> CRCERRIS_W { CRCERRIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpackets(&mut self) -> SHORTPACKETS_W<7> { + pub fn shortpackets(&mut self) -> SHORTPACKETS_W { SHORTPACKETS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Interrupt Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Endpoint Interrupt Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptifr_iso_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deveptifr_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIFR_ISO_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIFR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [deveptifr_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`deveptifr_iso_mode::W`](W) writer structure"] impl crate::Writable for DEVEPTIFR_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_blk_mode.rs index bfa62fd7..ca5faf25 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_blk_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTIMR_BLK_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINE` reader - Transmitted IN Data Interrupt"] pub type TXINE_R = crate::BitReader; #[doc = "Field `RXOUTE` reader - Received OUT Data Interrupt"] @@ -120,15 +107,13 @@ impl R { STALLRQ_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "Device Endpoint Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptimr_blk_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_blk_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIMR_BLK_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIMR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptimr_blk_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTIMR_BLK_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptimr_blk_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTIMR_BLK_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTIMR_BLK_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTIMR_BLK_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_ctrl_mode.rs index a25a2667..04dd387e 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_ctrl_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTIMR_CTRL_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINE` reader - Transmitted IN Data Interrupt"] pub type TXINE_R = crate::BitReader; #[doc = "Field `RXOUTE` reader - Received OUT Data Interrupt"] @@ -120,15 +107,13 @@ impl R { STALLRQ_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "Device Endpoint Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptimr_ctrl_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_ctrl_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIMR_CTRL_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIMR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptimr_ctrl_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTIMR_CTRL_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptimr_ctrl_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTIMR_CTRL_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTIMR_CTRL_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTIMR_CTRL_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_intrpt_mode.rs index 9f7cf817..5cd9e54a 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_intrpt_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTIMR_INTRPT_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINE` reader - Transmitted IN Data Interrupt"] pub type TXINE_R = crate::BitReader; #[doc = "Field `RXOUTE` reader - Received OUT Data Interrupt"] @@ -120,15 +107,13 @@ impl R { STALLRQ_R::new(((self.bits >> 19) & 1) != 0) } } -#[doc = "Device Endpoint Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptimr_intrpt_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_intrpt_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIMR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIMR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptimr_intrpt_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTIMR_INTRPT_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptimr_intrpt_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTIMR_INTRPT_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTIMR_INTRPT_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTIMR_INTRPT_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_iso_mode.rs index 743b01af..932a7944 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptimr_iso_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTIMR_ISO_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINE` reader - Transmitted IN Data Interrupt"] pub type TXINE_R = crate::BitReader; #[doc = "Field `RXOUTE` reader - Received OUT Data Interrupt"] @@ -127,15 +114,13 @@ impl R { RSTDT_R::new(((self.bits >> 18) & 1) != 0) } } -#[doc = "Device Endpoint Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptimr_iso_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptimr_iso_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTIMR_ISO_MODE_SPEC; impl crate::RegisterSpec for DEVEPTIMR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptimr_iso_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTIMR_ISO_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptimr_iso_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTIMR_ISO_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTIMR_ISO_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTIMR_ISO_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_blk_mode.rs index 463335c9..7d1e069c 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_blk_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTISR_BLK_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINI` reader - Transmitted IN Data Interrupt"] pub type TXINI_R = crate::BitReader; #[doc = "Field `RXOUTI` reader - Received OUT Data Interrupt"] @@ -65,22 +52,22 @@ impl DTSEQ_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 } - #[doc = "Checks if the value of the field is `DATA2`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_data2(&self) -> bool { *self == DTSEQSELECT_A::DATA2 } - #[doc = "Checks if the value of the field is `MDATA`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_mdata(&self) -> bool { *self == DTSEQSELECT_A::MDATA @@ -122,22 +109,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -176,17 +163,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -277,15 +264,13 @@ impl R { BYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Device Endpoint Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptisr_blk_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_blk_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTISR_BLK_MODE_SPEC; impl crate::RegisterSpec for DEVEPTISR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptisr_blk_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTISR_BLK_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptisr_blk_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTISR_BLK_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTISR_BLK_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTISR_BLK_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_ctrl_mode.rs index aa21a98b..f01f07f6 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_ctrl_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTISR_CTRL_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINI` reader - Transmitted IN Data Interrupt"] pub type TXINI_R = crate::BitReader; #[doc = "Field `RXOUTI` reader - Received OUT Data Interrupt"] @@ -65,22 +52,22 @@ impl DTSEQ_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 } - #[doc = "Checks if the value of the field is `DATA2`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_data2(&self) -> bool { *self == DTSEQSELECT_A::DATA2 } - #[doc = "Checks if the value of the field is `MDATA`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_mdata(&self) -> bool { *self == DTSEQSELECT_A::MDATA @@ -122,22 +109,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -176,17 +163,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -277,15 +264,13 @@ impl R { BYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Device Endpoint Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptisr_ctrl_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_ctrl_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTISR_CTRL_MODE_SPEC; impl crate::RegisterSpec for DEVEPTISR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptisr_ctrl_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTISR_CTRL_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptisr_ctrl_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTISR_CTRL_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTISR_CTRL_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTISR_CTRL_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_intrpt_mode.rs index 159af127..23afd67c 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_intrpt_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTISR_INTRPT_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINI` reader - Transmitted IN Data Interrupt"] pub type TXINI_R = crate::BitReader; #[doc = "Field `RXOUTI` reader - Received OUT Data Interrupt"] @@ -65,22 +52,22 @@ impl DTSEQ_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 } - #[doc = "Checks if the value of the field is `DATA2`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_data2(&self) -> bool { *self == DTSEQSELECT_A::DATA2 } - #[doc = "Checks if the value of the field is `MDATA`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_mdata(&self) -> bool { *self == DTSEQSELECT_A::MDATA @@ -122,22 +109,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -176,17 +163,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -277,15 +264,13 @@ impl R { BYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Device Endpoint Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptisr_intrpt_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_intrpt_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTISR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for DEVEPTISR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptisr_intrpt_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTISR_INTRPT_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptisr_intrpt_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTISR_INTRPT_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTISR_INTRPT_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTISR_INTRPT_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_iso_mode.rs index aa4c929b..2cd06102 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/deveptisr_iso_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVEPTISR_ISO_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `TXINI` reader - Transmitted IN Data Interrupt"] pub type TXINI_R = crate::BitReader; #[doc = "Field `RXOUTI` reader - Received OUT Data Interrupt"] @@ -65,22 +52,22 @@ impl DTSEQ_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 } - #[doc = "Checks if the value of the field is `DATA2`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_data2(&self) -> bool { *self == DTSEQSELECT_A::DATA2 } - #[doc = "Checks if the value of the field is `MDATA`"] + #[doc = "Reserved for high-bandwidth isochronous endpoint"] #[inline(always)] pub fn is_mdata(&self) -> bool { *self == DTSEQSELECT_A::MDATA @@ -124,22 +111,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -178,17 +165,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -277,15 +264,13 @@ impl R { BYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Device Endpoint Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [deveptisr_iso_mode](index.html) module"] +#[doc = "Device Endpoint Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deveptisr_iso_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVEPTISR_ISO_MODE_SPEC; impl crate::RegisterSpec for DEVEPTISR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [deveptisr_iso_mode::R](R) reader structure"] -impl crate::Readable for DEVEPTISR_ISO_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`deveptisr_iso_mode::R`](R) reader structure"] +impl crate::Readable for DEVEPTISR_ISO_MODE_SPEC {} #[doc = "`reset()` method sets DEVEPTISR_ISO_MODE[%s] to value 0"] impl crate::Resettable for DEVEPTISR_ISO_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devfnum.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devfnum.rs index 127e047e..fc408ce6 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devfnum.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devfnum.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVFNUM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `MFNUM` reader - Micro Frame Number"] pub type MFNUM_R = crate::FieldReader; #[doc = "Field `FNUM` reader - Frame Number"] @@ -36,15 +23,13 @@ impl R { FNCERR_R::new(((self.bits >> 15) & 1) != 0) } } -#[doc = "Device Frame Number Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devfnum](index.html) module"] +#[doc = "Device Frame Number Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devfnum::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVFNUM_SPEC; impl crate::RegisterSpec for DEVFNUM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devfnum::R](R) reader structure"] -impl crate::Readable for DEVFNUM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`devfnum::R`](R) reader structure"] +impl crate::Readable for DEVFNUM_SPEC {} #[doc = "`reset()` method sets DEVFNUM to value 0"] impl crate::Resettable for DEVFNUM_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devicr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devicr.rs index 74b2cf2b..277011c4 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devicr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devicr.rs @@ -1,96 +1,76 @@ #[doc = "Register `DEVICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SUSPC` writer - Suspend Interrupt Clear"] -pub type SUSPC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type SUSPC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSOFC` writer - Micro Start of Frame Interrupt Clear"] -pub type MSOFC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type MSOFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFC` writer - Start of Frame Interrupt Clear"] -pub type SOFC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type SOFC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSTC` writer - End of Reset Interrupt Clear"] -pub type EORSTC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type EORSTC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAKEUPC` writer - Wake-Up Interrupt Clear"] -pub type WAKEUPC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type WAKEUPC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSMC` writer - End of Resume Interrupt Clear"] -pub type EORSMC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type EORSMC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPRSMC` writer - Upstream Resume Interrupt Clear"] -pub type UPRSMC_W<'a, const O: u8> = crate::BitWriter<'a, DEVICR_SPEC, O>; +pub type UPRSMC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Suspend Interrupt Clear"] #[inline(always)] #[must_use] - pub fn suspc(&mut self) -> SUSPC_W<0> { + pub fn suspc(&mut self) -> SUSPC_W { SUSPC_W::new(self) } #[doc = "Bit 1 - Micro Start of Frame Interrupt Clear"] #[inline(always)] #[must_use] - pub fn msofc(&mut self) -> MSOFC_W<1> { + pub fn msofc(&mut self) -> MSOFC_W { MSOFC_W::new(self) } #[doc = "Bit 2 - Start of Frame Interrupt Clear"] #[inline(always)] #[must_use] - pub fn sofc(&mut self) -> SOFC_W<2> { + pub fn sofc(&mut self) -> SOFC_W { SOFC_W::new(self) } #[doc = "Bit 3 - End of Reset Interrupt Clear"] #[inline(always)] #[must_use] - pub fn eorstc(&mut self) -> EORSTC_W<3> { + pub fn eorstc(&mut self) -> EORSTC_W { EORSTC_W::new(self) } #[doc = "Bit 4 - Wake-Up Interrupt Clear"] #[inline(always)] #[must_use] - pub fn wakeupc(&mut self) -> WAKEUPC_W<4> { + pub fn wakeupc(&mut self) -> WAKEUPC_W { WAKEUPC_W::new(self) } #[doc = "Bit 5 - End of Resume Interrupt Clear"] #[inline(always)] #[must_use] - pub fn eorsmc(&mut self) -> EORSMC_W<5> { + pub fn eorsmc(&mut self) -> EORSMC_W { EORSMC_W::new(self) } #[doc = "Bit 6 - Upstream Resume Interrupt Clear"] #[inline(always)] #[must_use] - pub fn uprsmc(&mut self) -> UPRSMC_W<6> { + pub fn uprsmc(&mut self) -> UPRSMC_W { UPRSMC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Global Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devicr](index.html) module"] +#[doc = "Device Global Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devicr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVICR_SPEC; impl crate::RegisterSpec for DEVICR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devicr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devicr::W`](W) writer structure"] impl crate::Writable for DEVICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devidr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devidr.rs index 25cf68e0..87757d61 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devidr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devidr.rs @@ -1,232 +1,212 @@ #[doc = "Register `DEVIDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SUSPEC` writer - Suspend Interrupt Disable"] -pub type SUSPEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type SUSPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSOFEC` writer - Micro Start of Frame Interrupt Disable"] -pub type MSOFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type MSOFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFEC` writer - Start of Frame Interrupt Disable"] -pub type SOFEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type SOFEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSTEC` writer - End of Reset Interrupt Disable"] -pub type EORSTEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type EORSTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAKEUPEC` writer - Wake-Up Interrupt Disable"] -pub type WAKEUPEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type WAKEUPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSMEC` writer - End of Resume Interrupt Disable"] -pub type EORSMEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type EORSMEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPRSMEC` writer - Upstream Resume Interrupt Disable"] -pub type UPRSMEC_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type UPRSMEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_0` writer - Endpoint 0 Interrupt Disable"] -pub type PEP_0_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_1` writer - Endpoint 1 Interrupt Disable"] -pub type PEP_1_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_2` writer - Endpoint 2 Interrupt Disable"] -pub type PEP_2_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_3` writer - Endpoint 3 Interrupt Disable"] -pub type PEP_3_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_4` writer - Endpoint 4 Interrupt Disable"] -pub type PEP_4_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_5` writer - Endpoint 5 Interrupt Disable"] -pub type PEP_5_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_6` writer - Endpoint 6 Interrupt Disable"] -pub type PEP_6_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_7` writer - Endpoint 7 Interrupt Disable"] -pub type PEP_7_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_8` writer - Endpoint 8 Interrupt Disable"] -pub type PEP_8_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_9` writer - Endpoint 9 Interrupt Disable"] -pub type PEP_9_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type PEP_9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` writer - DMA Channel 1 Interrupt Disable"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` writer - DMA Channel 2 Interrupt Disable"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` writer - DMA Channel 3 Interrupt Disable"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` writer - DMA Channel 4 Interrupt Disable"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` writer - DMA Channel 5 Interrupt Disable"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` writer - DMA Channel 6 Interrupt Disable"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7` writer - DMA Channel 7 Interrupt Disable"] -pub type DMA_7_W<'a, const O: u8> = crate::BitWriter<'a, DEVIDR_SPEC, O>; +pub type DMA_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Suspend Interrupt Disable"] #[inline(always)] #[must_use] - pub fn suspec(&mut self) -> SUSPEC_W<0> { + pub fn suspec(&mut self) -> SUSPEC_W { SUSPEC_W::new(self) } #[doc = "Bit 1 - Micro Start of Frame Interrupt Disable"] #[inline(always)] #[must_use] - pub fn msofec(&mut self) -> MSOFEC_W<1> { + pub fn msofec(&mut self) -> MSOFEC_W { MSOFEC_W::new(self) } #[doc = "Bit 2 - Start of Frame Interrupt Disable"] #[inline(always)] #[must_use] - pub fn sofec(&mut self) -> SOFEC_W<2> { + pub fn sofec(&mut self) -> SOFEC_W { SOFEC_W::new(self) } #[doc = "Bit 3 - End of Reset Interrupt Disable"] #[inline(always)] #[must_use] - pub fn eorstec(&mut self) -> EORSTEC_W<3> { + pub fn eorstec(&mut self) -> EORSTEC_W { EORSTEC_W::new(self) } #[doc = "Bit 4 - Wake-Up Interrupt Disable"] #[inline(always)] #[must_use] - pub fn wakeupec(&mut self) -> WAKEUPEC_W<4> { + pub fn wakeupec(&mut self) -> WAKEUPEC_W { WAKEUPEC_W::new(self) } #[doc = "Bit 5 - End of Resume Interrupt Disable"] #[inline(always)] #[must_use] - pub fn eorsmec(&mut self) -> EORSMEC_W<5> { + pub fn eorsmec(&mut self) -> EORSMEC_W { EORSMEC_W::new(self) } #[doc = "Bit 6 - Upstream Resume Interrupt Disable"] #[inline(always)] #[must_use] - pub fn uprsmec(&mut self) -> UPRSMEC_W<6> { + pub fn uprsmec(&mut self) -> UPRSMEC_W { UPRSMEC_W::new(self) } #[doc = "Bit 12 - Endpoint 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_0(&mut self) -> PEP_0_W<12> { + pub fn pep_0(&mut self) -> PEP_0_W { PEP_0_W::new(self) } #[doc = "Bit 13 - Endpoint 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_1(&mut self) -> PEP_1_W<13> { + pub fn pep_1(&mut self) -> PEP_1_W { PEP_1_W::new(self) } #[doc = "Bit 14 - Endpoint 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_2(&mut self) -> PEP_2_W<14> { + pub fn pep_2(&mut self) -> PEP_2_W { PEP_2_W::new(self) } #[doc = "Bit 15 - Endpoint 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_3(&mut self) -> PEP_3_W<15> { + pub fn pep_3(&mut self) -> PEP_3_W { PEP_3_W::new(self) } #[doc = "Bit 16 - Endpoint 4 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_4(&mut self) -> PEP_4_W<16> { + pub fn pep_4(&mut self) -> PEP_4_W { PEP_4_W::new(self) } #[doc = "Bit 17 - Endpoint 5 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_5(&mut self) -> PEP_5_W<17> { + pub fn pep_5(&mut self) -> PEP_5_W { PEP_5_W::new(self) } #[doc = "Bit 18 - Endpoint 6 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_6(&mut self) -> PEP_6_W<18> { + pub fn pep_6(&mut self) -> PEP_6_W { PEP_6_W::new(self) } #[doc = "Bit 19 - Endpoint 7 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_7(&mut self) -> PEP_7_W<19> { + pub fn pep_7(&mut self) -> PEP_7_W { PEP_7_W::new(self) } #[doc = "Bit 20 - Endpoint 8 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_8(&mut self) -> PEP_8_W<20> { + pub fn pep_8(&mut self) -> PEP_8_W { PEP_8_W::new(self) } #[doc = "Bit 21 - Endpoint 9 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_9(&mut self) -> PEP_9_W<21> { + pub fn pep_9(&mut self) -> PEP_9_W { PEP_9_W::new(self) } #[doc = "Bit 25 - DMA Channel 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<25> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 26 - DMA Channel 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<26> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 27 - DMA Channel 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<27> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 28 - DMA Channel 4 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<28> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 29 - DMA Channel 5 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<29> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 30 - DMA Channel 6 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<30> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 31 - DMA Channel 7 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_7(&mut self) -> DMA_7_W<31> { + pub fn dma_7(&mut self) -> DMA_7_W { DMA_7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Global Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devidr](index.html) module"] +#[doc = "Device Global Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devidr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVIDR_SPEC; impl crate::RegisterSpec for DEVIDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devidr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devidr::W`](W) writer structure"] impl crate::Writable for DEVIDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devier.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devier.rs index 32092db7..5b98bfed 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devier.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devier.rs @@ -1,232 +1,212 @@ #[doc = "Register `DEVIER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SUSPES` writer - Suspend Interrupt Enable"] -pub type SUSPES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type SUSPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSOFES` writer - Micro Start of Frame Interrupt Enable"] -pub type MSOFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type MSOFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFES` writer - Start of Frame Interrupt Enable"] -pub type SOFES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type SOFES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSTES` writer - End of Reset Interrupt Enable"] -pub type EORSTES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type EORSTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAKEUPES` writer - Wake-Up Interrupt Enable"] -pub type WAKEUPES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type WAKEUPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSMES` writer - End of Resume Interrupt Enable"] -pub type EORSMES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type EORSMES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPRSMES` writer - Upstream Resume Interrupt Enable"] -pub type UPRSMES_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type UPRSMES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_0` writer - Endpoint 0 Interrupt Enable"] -pub type PEP_0_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_1` writer - Endpoint 1 Interrupt Enable"] -pub type PEP_1_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_2` writer - Endpoint 2 Interrupt Enable"] -pub type PEP_2_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_3` writer - Endpoint 3 Interrupt Enable"] -pub type PEP_3_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_4` writer - Endpoint 4 Interrupt Enable"] -pub type PEP_4_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_5` writer - Endpoint 5 Interrupt Enable"] -pub type PEP_5_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_6` writer - Endpoint 6 Interrupt Enable"] -pub type PEP_6_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_7` writer - Endpoint 7 Interrupt Enable"] -pub type PEP_7_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_8` writer - Endpoint 8 Interrupt Enable"] -pub type PEP_8_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_9` writer - Endpoint 9 Interrupt Enable"] -pub type PEP_9_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type PEP_9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` writer - DMA Channel 1 Interrupt Enable"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` writer - DMA Channel 2 Interrupt Enable"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` writer - DMA Channel 3 Interrupt Enable"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` writer - DMA Channel 4 Interrupt Enable"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` writer - DMA Channel 5 Interrupt Enable"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` writer - DMA Channel 6 Interrupt Enable"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7` writer - DMA Channel 7 Interrupt Enable"] -pub type DMA_7_W<'a, const O: u8> = crate::BitWriter<'a, DEVIER_SPEC, O>; +pub type DMA_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Suspend Interrupt Enable"] #[inline(always)] #[must_use] - pub fn suspes(&mut self) -> SUSPES_W<0> { + pub fn suspes(&mut self) -> SUSPES_W { SUSPES_W::new(self) } #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable"] #[inline(always)] #[must_use] - pub fn msofes(&mut self) -> MSOFES_W<1> { + pub fn msofes(&mut self) -> MSOFES_W { MSOFES_W::new(self) } #[doc = "Bit 2 - Start of Frame Interrupt Enable"] #[inline(always)] #[must_use] - pub fn sofes(&mut self) -> SOFES_W<2> { + pub fn sofes(&mut self) -> SOFES_W { SOFES_W::new(self) } #[doc = "Bit 3 - End of Reset Interrupt Enable"] #[inline(always)] #[must_use] - pub fn eorstes(&mut self) -> EORSTES_W<3> { + pub fn eorstes(&mut self) -> EORSTES_W { EORSTES_W::new(self) } #[doc = "Bit 4 - Wake-Up Interrupt Enable"] #[inline(always)] #[must_use] - pub fn wakeupes(&mut self) -> WAKEUPES_W<4> { + pub fn wakeupes(&mut self) -> WAKEUPES_W { WAKEUPES_W::new(self) } #[doc = "Bit 5 - End of Resume Interrupt Enable"] #[inline(always)] #[must_use] - pub fn eorsmes(&mut self) -> EORSMES_W<5> { + pub fn eorsmes(&mut self) -> EORSMES_W { EORSMES_W::new(self) } #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] #[inline(always)] #[must_use] - pub fn uprsmes(&mut self) -> UPRSMES_W<6> { + pub fn uprsmes(&mut self) -> UPRSMES_W { UPRSMES_W::new(self) } #[doc = "Bit 12 - Endpoint 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_0(&mut self) -> PEP_0_W<12> { + pub fn pep_0(&mut self) -> PEP_0_W { PEP_0_W::new(self) } #[doc = "Bit 13 - Endpoint 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_1(&mut self) -> PEP_1_W<13> { + pub fn pep_1(&mut self) -> PEP_1_W { PEP_1_W::new(self) } #[doc = "Bit 14 - Endpoint 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_2(&mut self) -> PEP_2_W<14> { + pub fn pep_2(&mut self) -> PEP_2_W { PEP_2_W::new(self) } #[doc = "Bit 15 - Endpoint 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_3(&mut self) -> PEP_3_W<15> { + pub fn pep_3(&mut self) -> PEP_3_W { PEP_3_W::new(self) } #[doc = "Bit 16 - Endpoint 4 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_4(&mut self) -> PEP_4_W<16> { + pub fn pep_4(&mut self) -> PEP_4_W { PEP_4_W::new(self) } #[doc = "Bit 17 - Endpoint 5 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_5(&mut self) -> PEP_5_W<17> { + pub fn pep_5(&mut self) -> PEP_5_W { PEP_5_W::new(self) } #[doc = "Bit 18 - Endpoint 6 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_6(&mut self) -> PEP_6_W<18> { + pub fn pep_6(&mut self) -> PEP_6_W { PEP_6_W::new(self) } #[doc = "Bit 19 - Endpoint 7 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_7(&mut self) -> PEP_7_W<19> { + pub fn pep_7(&mut self) -> PEP_7_W { PEP_7_W::new(self) } #[doc = "Bit 20 - Endpoint 8 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_8(&mut self) -> PEP_8_W<20> { + pub fn pep_8(&mut self) -> PEP_8_W { PEP_8_W::new(self) } #[doc = "Bit 21 - Endpoint 9 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_9(&mut self) -> PEP_9_W<21> { + pub fn pep_9(&mut self) -> PEP_9_W { PEP_9_W::new(self) } #[doc = "Bit 25 - DMA Channel 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<25> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 26 - DMA Channel 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<26> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 27 - DMA Channel 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<27> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 28 - DMA Channel 4 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<28> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 29 - DMA Channel 5 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<29> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 30 - DMA Channel 6 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<30> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 31 - DMA Channel 7 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_7(&mut self) -> DMA_7_W<31> { + pub fn dma_7(&mut self) -> DMA_7_W { DMA_7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Global Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devier](index.html) module"] +#[doc = "Device Global Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVIER_SPEC; impl crate::RegisterSpec for DEVIER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devier::W`](W) writer structure"] impl crate::Writable for DEVIER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devifr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devifr.rs index e7d05a36..88107e74 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devifr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devifr.rs @@ -1,152 +1,132 @@ #[doc = "Register `DEVIFR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SUSPS` writer - Suspend Interrupt Set"] -pub type SUSPS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type SUSPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `MSOFS` writer - Micro Start of Frame Interrupt Set"] -pub type MSOFS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type MSOFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SOFS` writer - Start of Frame Interrupt Set"] -pub type SOFS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type SOFS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSTS` writer - End of Reset Interrupt Set"] -pub type EORSTS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type EORSTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WAKEUPS` writer - Wake-Up Interrupt Set"] -pub type WAKEUPS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type WAKEUPS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EORSMS` writer - End of Resume Interrupt Set"] -pub type EORSMS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type EORSMS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UPRSMS` writer - Upstream Resume Interrupt Set"] -pub type UPRSMS_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type UPRSMS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` writer - DMA Channel 1 Interrupt Set"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` writer - DMA Channel 2 Interrupt Set"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` writer - DMA Channel 3 Interrupt Set"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` writer - DMA Channel 4 Interrupt Set"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` writer - DMA Channel 5 Interrupt Set"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` writer - DMA Channel 6 Interrupt Set"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7` writer - DMA Channel 7 Interrupt Set"] -pub type DMA_7_W<'a, const O: u8> = crate::BitWriter<'a, DEVIFR_SPEC, O>; +pub type DMA_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Suspend Interrupt Set"] #[inline(always)] #[must_use] - pub fn susps(&mut self) -> SUSPS_W<0> { + pub fn susps(&mut self) -> SUSPS_W { SUSPS_W::new(self) } #[doc = "Bit 1 - Micro Start of Frame Interrupt Set"] #[inline(always)] #[must_use] - pub fn msofs(&mut self) -> MSOFS_W<1> { + pub fn msofs(&mut self) -> MSOFS_W { MSOFS_W::new(self) } #[doc = "Bit 2 - Start of Frame Interrupt Set"] #[inline(always)] #[must_use] - pub fn sofs(&mut self) -> SOFS_W<2> { + pub fn sofs(&mut self) -> SOFS_W { SOFS_W::new(self) } #[doc = "Bit 3 - End of Reset Interrupt Set"] #[inline(always)] #[must_use] - pub fn eorsts(&mut self) -> EORSTS_W<3> { + pub fn eorsts(&mut self) -> EORSTS_W { EORSTS_W::new(self) } #[doc = "Bit 4 - Wake-Up Interrupt Set"] #[inline(always)] #[must_use] - pub fn wakeups(&mut self) -> WAKEUPS_W<4> { + pub fn wakeups(&mut self) -> WAKEUPS_W { WAKEUPS_W::new(self) } #[doc = "Bit 5 - End of Resume Interrupt Set"] #[inline(always)] #[must_use] - pub fn eorsms(&mut self) -> EORSMS_W<5> { + pub fn eorsms(&mut self) -> EORSMS_W { EORSMS_W::new(self) } #[doc = "Bit 6 - Upstream Resume Interrupt Set"] #[inline(always)] #[must_use] - pub fn uprsms(&mut self) -> UPRSMS_W<6> { + pub fn uprsms(&mut self) -> UPRSMS_W { UPRSMS_W::new(self) } #[doc = "Bit 25 - DMA Channel 1 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<25> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 26 - DMA Channel 2 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<26> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 27 - DMA Channel 3 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<27> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 28 - DMA Channel 4 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<28> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 29 - DMA Channel 5 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<29> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 30 - DMA Channel 6 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<30> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 31 - DMA Channel 7 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_7(&mut self) -> DMA_7_W<31> { + pub fn dma_7(&mut self) -> DMA_7_W { DMA_7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device Global Interrupt Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devifr](index.html) module"] +#[doc = "Device Global Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devifr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVIFR_SPEC; impl crate::RegisterSpec for DEVIFR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [devifr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`devifr::W`](W) writer structure"] impl crate::Writable for DEVIFR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devimr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devimr.rs index 8e20af30..d27bad30 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devimr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devimr.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVIMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SUSPE` reader - Suspend Interrupt Mask"] pub type SUSPE_R = crate::BitReader; #[doc = "Field `MSOFE` reader - Micro Start of Frame Interrupt Mask"] @@ -183,15 +170,13 @@ impl R { DMA_7_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Device Global Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devimr](index.html) module"] +#[doc = "Device Global Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devimr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVIMR_SPEC; impl crate::RegisterSpec for DEVIMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devimr::R](R) reader structure"] -impl crate::Readable for DEVIMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`devimr::R`](R) reader structure"] +impl crate::Readable for DEVIMR_SPEC {} #[doc = "`reset()` method sets DEVIMR to value 0"] impl crate::Resettable for DEVIMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/devisr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/devisr.rs index ae2ca90e..d1917bf3 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/devisr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/devisr.rs @@ -1,18 +1,5 @@ #[doc = "Register `DEVISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SUSP` reader - Suspend Interrupt"] pub type SUSP_R = crate::BitReader; #[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt"] @@ -183,15 +170,13 @@ impl R { DMA_7_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Device Global Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devisr](index.html) module"] +#[doc = "Device Global Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVISR_SPEC; impl crate::RegisterSpec for DEVISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devisr::R](R) reader structure"] -impl crate::Readable for DEVISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`devisr::R`](R) reader structure"] +impl crate::Readable for DEVISR_SPEC {} #[doc = "`reset()` method sets DEVISR to value 0"] impl crate::Resettable for DEVISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr1.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr1.rs index 333c7e2f..610cc0be 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr1.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr1.rs @@ -1,55 +1,23 @@ #[doc = "Register `HSTADDR1` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTADDR1` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HSTADDRP0` reader - USB Host Address"] pub type HSTADDRP0_R = crate::FieldReader; #[doc = "Field `HSTADDRP0` writer - USB Host Address"] -pub type HSTADDRP0_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR1_SPEC, 7, O>; +pub type HSTADDRP0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP1` reader - USB Host Address"] pub type HSTADDRP1_R = crate::FieldReader; #[doc = "Field `HSTADDRP1` writer - USB Host Address"] -pub type HSTADDRP1_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR1_SPEC, 7, O>; +pub type HSTADDRP1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP2` reader - USB Host Address"] pub type HSTADDRP2_R = crate::FieldReader; #[doc = "Field `HSTADDRP2` writer - USB Host Address"] -pub type HSTADDRP2_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR1_SPEC, 7, O>; +pub type HSTADDRP2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP3` reader - USB Host Address"] pub type HSTADDRP3_R = crate::FieldReader; #[doc = "Field `HSTADDRP3` writer - USB Host Address"] -pub type HSTADDRP3_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR1_SPEC, 7, O>; +pub type HSTADDRP3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - USB Host Address"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp0(&mut self) -> HSTADDRP0_W<0> { + pub fn hstaddrp0(&mut self) -> HSTADDRP0_W { HSTADDRP0_W::new(self) } #[doc = "Bits 8:14 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp1(&mut self) -> HSTADDRP1_W<8> { + pub fn hstaddrp1(&mut self) -> HSTADDRP1_W { HSTADDRP1_W::new(self) } #[doc = "Bits 16:22 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp2(&mut self) -> HSTADDRP2_W<16> { + pub fn hstaddrp2(&mut self) -> HSTADDRP2_W { HSTADDRP2_W::new(self) } #[doc = "Bits 24:30 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp3(&mut self) -> HSTADDRP3_W<24> { + pub fn hstaddrp3(&mut self) -> HSTADDRP3_W { HSTADDRP3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Address 1 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstaddr1](index.html) module"] +#[doc = "Host Address 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstaddr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstaddr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTADDR1_SPEC; impl crate::RegisterSpec for HSTADDR1_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstaddr1::R](R) reader structure"] -impl crate::Readable for HSTADDR1_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstaddr1::W](W) writer structure"] +#[doc = "`read()` method returns [`hstaddr1::R`](R) reader structure"] +impl crate::Readable for HSTADDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstaddr1::W`](W) writer structure"] impl crate::Writable for HSTADDR1_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr2.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr2.rs index 44ba6990..c34404cc 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr2.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr2.rs @@ -1,55 +1,23 @@ #[doc = "Register `HSTADDR2` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTADDR2` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HSTADDRP4` reader - USB Host Address"] pub type HSTADDRP4_R = crate::FieldReader; #[doc = "Field `HSTADDRP4` writer - USB Host Address"] -pub type HSTADDRP4_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR2_SPEC, 7, O>; +pub type HSTADDRP4_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP5` reader - USB Host Address"] pub type HSTADDRP5_R = crate::FieldReader; #[doc = "Field `HSTADDRP5` writer - USB Host Address"] -pub type HSTADDRP5_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR2_SPEC, 7, O>; +pub type HSTADDRP5_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP6` reader - USB Host Address"] pub type HSTADDRP6_R = crate::FieldReader; #[doc = "Field `HSTADDRP6` writer - USB Host Address"] -pub type HSTADDRP6_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR2_SPEC, 7, O>; +pub type HSTADDRP6_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP7` reader - USB Host Address"] pub type HSTADDRP7_R = crate::FieldReader; #[doc = "Field `HSTADDRP7` writer - USB Host Address"] -pub type HSTADDRP7_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR2_SPEC, 7, O>; +pub type HSTADDRP7_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - USB Host Address"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:6 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp4(&mut self) -> HSTADDRP4_W<0> { + pub fn hstaddrp4(&mut self) -> HSTADDRP4_W { HSTADDRP4_W::new(self) } #[doc = "Bits 8:14 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp5(&mut self) -> HSTADDRP5_W<8> { + pub fn hstaddrp5(&mut self) -> HSTADDRP5_W { HSTADDRP5_W::new(self) } #[doc = "Bits 16:22 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp6(&mut self) -> HSTADDRP6_W<16> { + pub fn hstaddrp6(&mut self) -> HSTADDRP6_W { HSTADDRP6_W::new(self) } #[doc = "Bits 24:30 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp7(&mut self) -> HSTADDRP7_W<24> { + pub fn hstaddrp7(&mut self) -> HSTADDRP7_W { HSTADDRP7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Address 2 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstaddr2](index.html) module"] +#[doc = "Host Address 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstaddr2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstaddr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTADDR2_SPEC; impl crate::RegisterSpec for HSTADDR2_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstaddr2::R](R) reader structure"] -impl crate::Readable for HSTADDR2_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstaddr2::W](W) writer structure"] +#[doc = "`read()` method returns [`hstaddr2::R`](R) reader structure"] +impl crate::Readable for HSTADDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstaddr2::W`](W) writer structure"] impl crate::Writable for HSTADDR2_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr3.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr3.rs index e534f4b9..2cf7bb88 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr3.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstaddr3.rs @@ -1,47 +1,15 @@ #[doc = "Register `HSTADDR3` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTADDR3` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `HSTADDRP8` reader - USB Host Address"] pub type HSTADDRP8_R = crate::FieldReader; #[doc = "Field `HSTADDRP8` writer - USB Host Address"] -pub type HSTADDRP8_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR3_SPEC, 7, O>; +pub type HSTADDRP8_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; #[doc = "Field `HSTADDRP9` reader - USB Host Address"] pub type HSTADDRP9_R = crate::FieldReader; #[doc = "Field `HSTADDRP9` writer - USB Host Address"] -pub type HSTADDRP9_W<'a, const O: u8> = crate::FieldWriter<'a, HSTADDR3_SPEC, 7, O>; +pub type HSTADDRP9_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O>; impl R { #[doc = "Bits 0:6 - USB Host Address"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:6 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp8(&mut self) -> HSTADDRP8_W<0> { + pub fn hstaddrp8(&mut self) -> HSTADDRP8_W { HSTADDRP8_W::new(self) } #[doc = "Bits 8:14 - USB Host Address"] #[inline(always)] #[must_use] - pub fn hstaddrp9(&mut self) -> HSTADDRP9_W<8> { + pub fn hstaddrp9(&mut self) -> HSTADDRP9_W { HSTADDRP9_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Address 3 Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstaddr3](index.html) module"] +#[doc = "Host Address 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstaddr3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstaddr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTADDR3_SPEC; impl crate::RegisterSpec for HSTADDR3_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstaddr3::R](R) reader structure"] -impl crate::Readable for HSTADDR3_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstaddr3::W](W) writer structure"] +#[doc = "`read()` method returns [`hstaddr3::R`](R) reader structure"] +impl crate::Readable for HSTADDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstaddr3::W`](W) writer structure"] impl crate::Writable for HSTADDR3_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstctrl.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstctrl.rs index edc745ad..b862a555 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstctrl.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstctrl.rs @@ -1,51 +1,19 @@ #[doc = "Register `HSTCTRL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTCTRL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SOFE` reader - Start of Frame Generation Enable"] pub type SOFE_R = crate::BitReader; #[doc = "Field `SOFE` writer - Start of Frame Generation Enable"] -pub type SOFE_W<'a, const O: u8> = crate::BitWriter<'a, HSTCTRL_SPEC, O>; +pub type SOFE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESET` reader - Send USB Reset"] pub type RESET_R = crate::BitReader; #[doc = "Field `RESET` writer - Send USB Reset"] -pub type RESET_W<'a, const O: u8> = crate::BitWriter<'a, HSTCTRL_SPEC, O>; +pub type RESET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RESUME` reader - Send USB Resume"] pub type RESUME_R = crate::BitReader; #[doc = "Field `RESUME` writer - Send USB Resume"] -pub type RESUME_W<'a, const O: u8> = crate::BitWriter<'a, HSTCTRL_SPEC, O>; +pub type RESUME_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SPDCONF` reader - Mode Configuration"] pub type SPDCONF_R = crate::FieldReader; #[doc = "Mode Configuration\n\nValue on reset: 0"] @@ -82,49 +50,52 @@ impl SPDCONF_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NORMAL`"] + #[doc = "The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable."] #[inline(always)] pub fn is_normal(&self) -> bool { *self == SPDCONFSELECT_A::NORMAL } - #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[doc = "For a better consumption, if high speed is not needed."] #[inline(always)] pub fn is_low_power(&self) -> bool { *self == SPDCONFSELECT_A::LOW_POWER } - #[doc = "Checks if the value of the field is `HIGH_SPEED`"] + #[doc = "Forced high speed."] #[inline(always)] pub fn is_high_speed(&self) -> bool { *self == SPDCONFSELECT_A::HIGH_SPEED } - #[doc = "Checks if the value of the field is `FORCED_FS`"] + #[doc = "The host remains in Full-speed mode whatever the peripheral speed capability."] #[inline(always)] pub fn is_forced_fs(&self) -> bool { *self == SPDCONFSELECT_A::FORCED_FS } } #[doc = "Field `SPDCONF` writer - Mode Configuration"] -pub type SPDCONF_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, HSTCTRL_SPEC, 2, O, SPDCONFSELECT_A>; -impl<'a, const O: u8> SPDCONF_W<'a, O> { +pub type SPDCONF_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, SPDCONFSELECT_A>; +impl<'a, REG, const O: u8> SPDCONF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable."] #[inline(always)] - pub fn normal(self) -> &'a mut W { + pub fn normal(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::NORMAL) } #[doc = "For a better consumption, if high speed is not needed."] #[inline(always)] - pub fn low_power(self) -> &'a mut W { + pub fn low_power(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::LOW_POWER) } #[doc = "Forced high speed."] #[inline(always)] - pub fn high_speed(self) -> &'a mut W { + pub fn high_speed(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::HIGH_SPEED) } #[doc = "The host remains in Full-speed mode whatever the peripheral speed capability."] #[inline(always)] - pub fn forced_fs(self) -> &'a mut W { + pub fn forced_fs(self) -> &'a mut crate::W { self.variant(SPDCONFSELECT_A::FORCED_FS) } } @@ -154,46 +125,43 @@ impl W { #[doc = "Bit 8 - Start of Frame Generation Enable"] #[inline(always)] #[must_use] - pub fn sofe(&mut self) -> SOFE_W<8> { + pub fn sofe(&mut self) -> SOFE_W { SOFE_W::new(self) } #[doc = "Bit 9 - Send USB Reset"] #[inline(always)] #[must_use] - pub fn reset(&mut self) -> RESET_W<9> { + pub fn reset(&mut self) -> RESET_W { RESET_W::new(self) } #[doc = "Bit 10 - Send USB Resume"] #[inline(always)] #[must_use] - pub fn resume(&mut self) -> RESUME_W<10> { + pub fn resume(&mut self) -> RESUME_W { RESUME_W::new(self) } #[doc = "Bits 12:13 - Mode Configuration"] #[inline(always)] #[must_use] - pub fn spdconf(&mut self) -> SPDCONF_W<12> { + pub fn spdconf(&mut self) -> SPDCONF_W { SPDCONF_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host General Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstctrl](index.html) module"] +#[doc = "Host General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTCTRL_SPEC; impl crate::RegisterSpec for HSTCTRL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstctrl::R](R) reader structure"] -impl crate::Readable for HSTCTRL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstctrl::W](W) writer structure"] +#[doc = "`read()` method returns [`hstctrl::R`](R) reader structure"] +impl crate::Readable for HSTCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstctrl::W`](W) writer structure"] impl crate::Writable for HSTCTRL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstfnum.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstfnum.rs index 64ff92e3..de26b3f9 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstfnum.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstfnum.rs @@ -1,51 +1,19 @@ #[doc = "Register `HSTFNUM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTFNUM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `MFNUM` reader - Micro Frame Number"] pub type MFNUM_R = crate::FieldReader; #[doc = "Field `MFNUM` writer - Micro Frame Number"] -pub type MFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, HSTFNUM_SPEC, 3, O>; +pub type MFNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>; #[doc = "Field `FNUM` reader - Frame Number"] pub type FNUM_R = crate::FieldReader; #[doc = "Field `FNUM` writer - Frame Number"] -pub type FNUM_W<'a, const O: u8> = crate::FieldWriter<'a, HSTFNUM_SPEC, 11, O, u16>; +pub type FNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 11, O, u16>; #[doc = "Field `FLENHIGH` reader - Frame Length"] pub type FLENHIGH_R = crate::FieldReader; #[doc = "Field `FLENHIGH` writer - Frame Length"] -pub type FLENHIGH_W<'a, const O: u8> = crate::FieldWriter<'a, HSTFNUM_SPEC, 8, O>; +pub type FLENHIGH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bits 0:2 - Micro Frame Number"] #[inline(always)] @@ -67,40 +35,37 @@ impl W { #[doc = "Bits 0:2 - Micro Frame Number"] #[inline(always)] #[must_use] - pub fn mfnum(&mut self) -> MFNUM_W<0> { + pub fn mfnum(&mut self) -> MFNUM_W { MFNUM_W::new(self) } #[doc = "Bits 3:13 - Frame Number"] #[inline(always)] #[must_use] - pub fn fnum(&mut self) -> FNUM_W<3> { + pub fn fnum(&mut self) -> FNUM_W { FNUM_W::new(self) } #[doc = "Bits 16:23 - Frame Length"] #[inline(always)] #[must_use] - pub fn flenhigh(&mut self) -> FLENHIGH_W<16> { + pub fn flenhigh(&mut self) -> FLENHIGH_W { FLENHIGH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Frame Number Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstfnum](index.html) module"] +#[doc = "Host Frame Number Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstfnum::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstfnum::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTFNUM_SPEC; impl crate::RegisterSpec for HSTFNUM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstfnum::R](R) reader structure"] -impl crate::Readable for HSTFNUM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstfnum::W](W) writer structure"] +#[doc = "`read()` method returns [`hstfnum::R`](R) reader structure"] +impl crate::Readable for HSTFNUM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstfnum::W`](W) writer structure"] impl crate::Writable for HSTFNUM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hsticr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hsticr.rs index 347c9f40..784c8d86 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hsticr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hsticr.rs @@ -1,96 +1,76 @@ #[doc = "Register `HSTICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DCONNIC` writer - Device Connection Interrupt Clear"] -pub type DCONNIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type DCONNIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DDISCIC` writer - Device Disconnection Interrupt Clear"] -pub type DDISCIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type DDISCIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTIC` writer - USB Reset Sent Interrupt Clear"] -pub type RSTIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type RSTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSMEDIC` writer - Downstream Resume Sent Interrupt Clear"] -pub type RSMEDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type RSMEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRSMIC` writer - Upstream Resume Received Interrupt Clear"] -pub type RXRSMIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type RXRSMIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSOFIC` writer - Host Start of Frame Interrupt Clear"] -pub type HSOFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type HSOFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HWUPIC` writer - Host Wake-Up Interrupt Clear"] -pub type HWUPIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTICR_SPEC, O>; +pub type HWUPIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Device Connection Interrupt Clear"] #[inline(always)] #[must_use] - pub fn dconnic(&mut self) -> DCONNIC_W<0> { + pub fn dconnic(&mut self) -> DCONNIC_W { DCONNIC_W::new(self) } #[doc = "Bit 1 - Device Disconnection Interrupt Clear"] #[inline(always)] #[must_use] - pub fn ddiscic(&mut self) -> DDISCIC_W<1> { + pub fn ddiscic(&mut self) -> DDISCIC_W { DDISCIC_W::new(self) } #[doc = "Bit 2 - USB Reset Sent Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rstic(&mut self) -> RSTIC_W<2> { + pub fn rstic(&mut self) -> RSTIC_W { RSTIC_W::new(self) } #[doc = "Bit 3 - Downstream Resume Sent Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rsmedic(&mut self) -> RSMEDIC_W<3> { + pub fn rsmedic(&mut self) -> RSMEDIC_W { RSMEDIC_W::new(self) } #[doc = "Bit 4 - Upstream Resume Received Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxrsmic(&mut self) -> RXRSMIC_W<4> { + pub fn rxrsmic(&mut self) -> RXRSMIC_W { RXRSMIC_W::new(self) } #[doc = "Bit 5 - Host Start of Frame Interrupt Clear"] #[inline(always)] #[must_use] - pub fn hsofic(&mut self) -> HSOFIC_W<5> { + pub fn hsofic(&mut self) -> HSOFIC_W { HSOFIC_W::new(self) } #[doc = "Bit 6 - Host Wake-Up Interrupt Clear"] #[inline(always)] #[must_use] - pub fn hwupic(&mut self) -> HWUPIC_W<6> { + pub fn hwupic(&mut self) -> HWUPIC_W { HWUPIC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Global Interrupt Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hsticr](index.html) module"] +#[doc = "Host Global Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hsticr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTICR_SPEC; impl crate::RegisterSpec for HSTICR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hsticr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hsticr::W`](W) writer structure"] impl crate::Writable for HSTICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstidr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstidr.rs index fa7d5b9f..c340b0d4 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstidr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstidr.rs @@ -1,232 +1,212 @@ #[doc = "Register `HSTIDR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DCONNIEC` writer - Device Connection Interrupt Disable"] -pub type DCONNIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DCONNIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DDISCIEC` writer - Device Disconnection Interrupt Disable"] -pub type DDISCIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DDISCIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTIEC` writer - USB Reset Sent Interrupt Disable"] -pub type RSTIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type RSTIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSMEDIEC` writer - Downstream Resume Sent Interrupt Disable"] -pub type RSMEDIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type RSMEDIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRSMIEC` writer - Upstream Resume Received Interrupt Disable"] -pub type RXRSMIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type RXRSMIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSOFIEC` writer - Host Start of Frame Interrupt Disable"] -pub type HSOFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type HSOFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HWUPIEC` writer - Host Wake-Up Interrupt Disable"] -pub type HWUPIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type HWUPIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_0` writer - Pipe 0 Interrupt Disable"] -pub type PEP_0_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_1` writer - Pipe 1 Interrupt Disable"] -pub type PEP_1_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_2` writer - Pipe 2 Interrupt Disable"] -pub type PEP_2_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_3` writer - Pipe 3 Interrupt Disable"] -pub type PEP_3_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_4` writer - Pipe 4 Interrupt Disable"] -pub type PEP_4_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_5` writer - Pipe 5 Interrupt Disable"] -pub type PEP_5_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_6` writer - Pipe 6 Interrupt Disable"] -pub type PEP_6_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_7` writer - Pipe 7 Interrupt Disable"] -pub type PEP_7_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_8` writer - Pipe 8 Interrupt Disable"] -pub type PEP_8_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_9` writer - Pipe 9 Interrupt Disable"] -pub type PEP_9_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type PEP_9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` writer - DMA Channel 0 Interrupt Disable"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` writer - DMA Channel 1 Interrupt Disable"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` writer - DMA Channel 2 Interrupt Disable"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` writer - DMA Channel 3 Interrupt Disable"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` writer - DMA Channel 4 Interrupt Disable"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` writer - DMA Channel 5 Interrupt Disable"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7` writer - DMA Channel 6 Interrupt Disable"] -pub type DMA_7_W<'a, const O: u8> = crate::BitWriter<'a, HSTIDR_SPEC, O>; +pub type DMA_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Device Connection Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dconniec(&mut self) -> DCONNIEC_W<0> { + pub fn dconniec(&mut self) -> DCONNIEC_W { DCONNIEC_W::new(self) } #[doc = "Bit 1 - Device Disconnection Interrupt Disable"] #[inline(always)] #[must_use] - pub fn ddisciec(&mut self) -> DDISCIEC_W<1> { + pub fn ddisciec(&mut self) -> DDISCIEC_W { DDISCIEC_W::new(self) } #[doc = "Bit 2 - USB Reset Sent Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rstiec(&mut self) -> RSTIEC_W<2> { + pub fn rstiec(&mut self) -> RSTIEC_W { RSTIEC_W::new(self) } #[doc = "Bit 3 - Downstream Resume Sent Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rsmediec(&mut self) -> RSMEDIEC_W<3> { + pub fn rsmediec(&mut self) -> RSMEDIEC_W { RSMEDIEC_W::new(self) } #[doc = "Bit 4 - Upstream Resume Received Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxrsmiec(&mut self) -> RXRSMIEC_W<4> { + pub fn rxrsmiec(&mut self) -> RXRSMIEC_W { RXRSMIEC_W::new(self) } #[doc = "Bit 5 - Host Start of Frame Interrupt Disable"] #[inline(always)] #[must_use] - pub fn hsofiec(&mut self) -> HSOFIEC_W<5> { + pub fn hsofiec(&mut self) -> HSOFIEC_W { HSOFIEC_W::new(self) } #[doc = "Bit 6 - Host Wake-Up Interrupt Disable"] #[inline(always)] #[must_use] - pub fn hwupiec(&mut self) -> HWUPIEC_W<6> { + pub fn hwupiec(&mut self) -> HWUPIEC_W { HWUPIEC_W::new(self) } #[doc = "Bit 8 - Pipe 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_0(&mut self) -> PEP_0_W<8> { + pub fn pep_0(&mut self) -> PEP_0_W { PEP_0_W::new(self) } #[doc = "Bit 9 - Pipe 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_1(&mut self) -> PEP_1_W<9> { + pub fn pep_1(&mut self) -> PEP_1_W { PEP_1_W::new(self) } #[doc = "Bit 10 - Pipe 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_2(&mut self) -> PEP_2_W<10> { + pub fn pep_2(&mut self) -> PEP_2_W { PEP_2_W::new(self) } #[doc = "Bit 11 - Pipe 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_3(&mut self) -> PEP_3_W<11> { + pub fn pep_3(&mut self) -> PEP_3_W { PEP_3_W::new(self) } #[doc = "Bit 12 - Pipe 4 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_4(&mut self) -> PEP_4_W<12> { + pub fn pep_4(&mut self) -> PEP_4_W { PEP_4_W::new(self) } #[doc = "Bit 13 - Pipe 5 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_5(&mut self) -> PEP_5_W<13> { + pub fn pep_5(&mut self) -> PEP_5_W { PEP_5_W::new(self) } #[doc = "Bit 14 - Pipe 6 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_6(&mut self) -> PEP_6_W<14> { + pub fn pep_6(&mut self) -> PEP_6_W { PEP_6_W::new(self) } #[doc = "Bit 15 - Pipe 7 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_7(&mut self) -> PEP_7_W<15> { + pub fn pep_7(&mut self) -> PEP_7_W { PEP_7_W::new(self) } #[doc = "Bit 16 - Pipe 8 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_8(&mut self) -> PEP_8_W<16> { + pub fn pep_8(&mut self) -> PEP_8_W { PEP_8_W::new(self) } #[doc = "Bit 17 - Pipe 9 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn pep_9(&mut self) -> PEP_9_W<17> { + pub fn pep_9(&mut self) -> PEP_9_W { PEP_9_W::new(self) } #[doc = "Bit 25 - DMA Channel 0 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<25> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 26 - DMA Channel 1 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<26> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 27 - DMA Channel 2 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<27> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 28 - DMA Channel 3 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<28> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 29 - DMA Channel 4 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<29> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 30 - DMA Channel 5 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<30> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 31 - DMA Channel 6 Interrupt Disable"] #[inline(always)] #[must_use] - pub fn dma_7(&mut self) -> DMA_7_W<31> { + pub fn dma_7(&mut self) -> DMA_7_W { DMA_7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Global Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstidr](index.html) module"] +#[doc = "Host Global Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstidr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTIDR_SPEC; impl crate::RegisterSpec for HSTIDR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstidr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstidr::W`](W) writer structure"] impl crate::Writable for HSTIDR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstier.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstier.rs index e21f3e6d..2cb3a92e 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstier.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstier.rs @@ -1,232 +1,212 @@ #[doc = "Register `HSTIER` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DCONNIES` writer - Device Connection Interrupt Enable"] -pub type DCONNIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DCONNIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DDISCIES` writer - Device Disconnection Interrupt Enable"] -pub type DDISCIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DDISCIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTIES` writer - USB Reset Sent Interrupt Enable"] -pub type RSTIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type RSTIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSMEDIES` writer - Downstream Resume Sent Interrupt Enable"] -pub type RSMEDIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type RSMEDIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRSMIES` writer - Upstream Resume Received Interrupt Enable"] -pub type RXRSMIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type RXRSMIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSOFIES` writer - Host Start of Frame Interrupt Enable"] -pub type HSOFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type HSOFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HWUPIES` writer - Host Wake-Up Interrupt Enable"] -pub type HWUPIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type HWUPIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_0` writer - Pipe 0 Interrupt Enable"] -pub type PEP_0_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_1` writer - Pipe 1 Interrupt Enable"] -pub type PEP_1_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_2` writer - Pipe 2 Interrupt Enable"] -pub type PEP_2_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_3` writer - Pipe 3 Interrupt Enable"] -pub type PEP_3_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_4` writer - Pipe 4 Interrupt Enable"] -pub type PEP_4_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_5` writer - Pipe 5 Interrupt Enable"] -pub type PEP_5_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_6` writer - Pipe 6 Interrupt Enable"] -pub type PEP_6_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_7` writer - Pipe 7 Interrupt Enable"] -pub type PEP_7_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_8` writer - Pipe 8 Interrupt Enable"] -pub type PEP_8_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEP_9` writer - Pipe 9 Interrupt Enable"] -pub type PEP_9_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type PEP_9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` writer - DMA Channel 0 Interrupt Enable"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` writer - DMA Channel 1 Interrupt Enable"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` writer - DMA Channel 2 Interrupt Enable"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` writer - DMA Channel 3 Interrupt Enable"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` writer - DMA Channel 4 Interrupt Enable"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` writer - DMA Channel 5 Interrupt Enable"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7` writer - DMA Channel 6 Interrupt Enable"] -pub type DMA_7_W<'a, const O: u8> = crate::BitWriter<'a, HSTIER_SPEC, O>; +pub type DMA_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Device Connection Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dconnies(&mut self) -> DCONNIES_W<0> { + pub fn dconnies(&mut self) -> DCONNIES_W { DCONNIES_W::new(self) } #[doc = "Bit 1 - Device Disconnection Interrupt Enable"] #[inline(always)] #[must_use] - pub fn ddiscies(&mut self) -> DDISCIES_W<1> { + pub fn ddiscies(&mut self) -> DDISCIES_W { DDISCIES_W::new(self) } #[doc = "Bit 2 - USB Reset Sent Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rsties(&mut self) -> RSTIES_W<2> { + pub fn rsties(&mut self) -> RSTIES_W { RSTIES_W::new(self) } #[doc = "Bit 3 - Downstream Resume Sent Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rsmedies(&mut self) -> RSMEDIES_W<3> { + pub fn rsmedies(&mut self) -> RSMEDIES_W { RSMEDIES_W::new(self) } #[doc = "Bit 4 - Upstream Resume Received Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxrsmies(&mut self) -> RXRSMIES_W<4> { + pub fn rxrsmies(&mut self) -> RXRSMIES_W { RXRSMIES_W::new(self) } #[doc = "Bit 5 - Host Start of Frame Interrupt Enable"] #[inline(always)] #[must_use] - pub fn hsofies(&mut self) -> HSOFIES_W<5> { + pub fn hsofies(&mut self) -> HSOFIES_W { HSOFIES_W::new(self) } #[doc = "Bit 6 - Host Wake-Up Interrupt Enable"] #[inline(always)] #[must_use] - pub fn hwupies(&mut self) -> HWUPIES_W<6> { + pub fn hwupies(&mut self) -> HWUPIES_W { HWUPIES_W::new(self) } #[doc = "Bit 8 - Pipe 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_0(&mut self) -> PEP_0_W<8> { + pub fn pep_0(&mut self) -> PEP_0_W { PEP_0_W::new(self) } #[doc = "Bit 9 - Pipe 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_1(&mut self) -> PEP_1_W<9> { + pub fn pep_1(&mut self) -> PEP_1_W { PEP_1_W::new(self) } #[doc = "Bit 10 - Pipe 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_2(&mut self) -> PEP_2_W<10> { + pub fn pep_2(&mut self) -> PEP_2_W { PEP_2_W::new(self) } #[doc = "Bit 11 - Pipe 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_3(&mut self) -> PEP_3_W<11> { + pub fn pep_3(&mut self) -> PEP_3_W { PEP_3_W::new(self) } #[doc = "Bit 12 - Pipe 4 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_4(&mut self) -> PEP_4_W<12> { + pub fn pep_4(&mut self) -> PEP_4_W { PEP_4_W::new(self) } #[doc = "Bit 13 - Pipe 5 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_5(&mut self) -> PEP_5_W<13> { + pub fn pep_5(&mut self) -> PEP_5_W { PEP_5_W::new(self) } #[doc = "Bit 14 - Pipe 6 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_6(&mut self) -> PEP_6_W<14> { + pub fn pep_6(&mut self) -> PEP_6_W { PEP_6_W::new(self) } #[doc = "Bit 15 - Pipe 7 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_7(&mut self) -> PEP_7_W<15> { + pub fn pep_7(&mut self) -> PEP_7_W { PEP_7_W::new(self) } #[doc = "Bit 16 - Pipe 8 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_8(&mut self) -> PEP_8_W<16> { + pub fn pep_8(&mut self) -> PEP_8_W { PEP_8_W::new(self) } #[doc = "Bit 17 - Pipe 9 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn pep_9(&mut self) -> PEP_9_W<17> { + pub fn pep_9(&mut self) -> PEP_9_W { PEP_9_W::new(self) } #[doc = "Bit 25 - DMA Channel 0 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<25> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 26 - DMA Channel 1 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<26> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 27 - DMA Channel 2 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<27> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 28 - DMA Channel 3 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<28> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 29 - DMA Channel 4 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<29> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 30 - DMA Channel 5 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<30> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 31 - DMA Channel 6 Interrupt Enable"] #[inline(always)] #[must_use] - pub fn dma_7(&mut self) -> DMA_7_W<31> { + pub fn dma_7(&mut self) -> DMA_7_W { DMA_7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Global Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstier](index.html) module"] +#[doc = "Host Global Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstier::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTIER_SPEC; impl crate::RegisterSpec for HSTIER_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstier::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstier::W`](W) writer structure"] impl crate::Writable for HSTIER_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstifr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstifr.rs index e31a5f5d..ca120069 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstifr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstifr.rs @@ -1,152 +1,132 @@ #[doc = "Register `HSTIFR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DCONNIS` writer - Device Connection Interrupt Set"] -pub type DCONNIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DCONNIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DDISCIS` writer - Device Disconnection Interrupt Set"] -pub type DDISCIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DDISCIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTIS` writer - USB Reset Sent Interrupt Set"] -pub type RSTIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type RSTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSMEDIS` writer - Downstream Resume Sent Interrupt Set"] -pub type RSMEDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type RSMEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXRSMIS` writer - Upstream Resume Received Interrupt Set"] -pub type RXRSMIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type RXRSMIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HSOFIS` writer - Host Start of Frame Interrupt Set"] -pub type HSOFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type HSOFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `HWUPIS` writer - Host Wake-Up Interrupt Set"] -pub type HWUPIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type HWUPIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_1` writer - DMA Channel 0 Interrupt Set"] -pub type DMA_1_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_2` writer - DMA Channel 1 Interrupt Set"] -pub type DMA_2_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_3` writer - DMA Channel 2 Interrupt Set"] -pub type DMA_3_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_4` writer - DMA Channel 3 Interrupt Set"] -pub type DMA_4_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_5` writer - DMA Channel 4 Interrupt Set"] -pub type DMA_5_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_6` writer - DMA Channel 5 Interrupt Set"] -pub type DMA_6_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DMA_7` writer - DMA Channel 6 Interrupt Set"] -pub type DMA_7_W<'a, const O: u8> = crate::BitWriter<'a, HSTIFR_SPEC, O>; +pub type DMA_7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Device Connection Interrupt Set"] #[inline(always)] #[must_use] - pub fn dconnis(&mut self) -> DCONNIS_W<0> { + pub fn dconnis(&mut self) -> DCONNIS_W { DCONNIS_W::new(self) } #[doc = "Bit 1 - Device Disconnection Interrupt Set"] #[inline(always)] #[must_use] - pub fn ddiscis(&mut self) -> DDISCIS_W<1> { + pub fn ddiscis(&mut self) -> DDISCIS_W { DDISCIS_W::new(self) } #[doc = "Bit 2 - USB Reset Sent Interrupt Set"] #[inline(always)] #[must_use] - pub fn rstis(&mut self) -> RSTIS_W<2> { + pub fn rstis(&mut self) -> RSTIS_W { RSTIS_W::new(self) } #[doc = "Bit 3 - Downstream Resume Sent Interrupt Set"] #[inline(always)] #[must_use] - pub fn rsmedis(&mut self) -> RSMEDIS_W<3> { + pub fn rsmedis(&mut self) -> RSMEDIS_W { RSMEDIS_W::new(self) } #[doc = "Bit 4 - Upstream Resume Received Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxrsmis(&mut self) -> RXRSMIS_W<4> { + pub fn rxrsmis(&mut self) -> RXRSMIS_W { RXRSMIS_W::new(self) } #[doc = "Bit 5 - Host Start of Frame Interrupt Set"] #[inline(always)] #[must_use] - pub fn hsofis(&mut self) -> HSOFIS_W<5> { + pub fn hsofis(&mut self) -> HSOFIS_W { HSOFIS_W::new(self) } #[doc = "Bit 6 - Host Wake-Up Interrupt Set"] #[inline(always)] #[must_use] - pub fn hwupis(&mut self) -> HWUPIS_W<6> { + pub fn hwupis(&mut self) -> HWUPIS_W { HWUPIS_W::new(self) } #[doc = "Bit 25 - DMA Channel 0 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_1(&mut self) -> DMA_1_W<25> { + pub fn dma_1(&mut self) -> DMA_1_W { DMA_1_W::new(self) } #[doc = "Bit 26 - DMA Channel 1 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_2(&mut self) -> DMA_2_W<26> { + pub fn dma_2(&mut self) -> DMA_2_W { DMA_2_W::new(self) } #[doc = "Bit 27 - DMA Channel 2 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_3(&mut self) -> DMA_3_W<27> { + pub fn dma_3(&mut self) -> DMA_3_W { DMA_3_W::new(self) } #[doc = "Bit 28 - DMA Channel 3 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_4(&mut self) -> DMA_4_W<28> { + pub fn dma_4(&mut self) -> DMA_4_W { DMA_4_W::new(self) } #[doc = "Bit 29 - DMA Channel 4 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_5(&mut self) -> DMA_5_W<29> { + pub fn dma_5(&mut self) -> DMA_5_W { DMA_5_W::new(self) } #[doc = "Bit 30 - DMA Channel 5 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_6(&mut self) -> DMA_6_W<30> { + pub fn dma_6(&mut self) -> DMA_6_W { DMA_6_W::new(self) } #[doc = "Bit 31 - DMA Channel 6 Interrupt Set"] #[inline(always)] #[must_use] - pub fn dma_7(&mut self) -> DMA_7_W<31> { + pub fn dma_7(&mut self) -> DMA_7_W { DMA_7_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Global Interrupt Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstifr](index.html) module"] +#[doc = "Host Global Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstifr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTIFR_SPEC; impl crate::RegisterSpec for HSTIFR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstifr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstifr::W`](W) writer structure"] impl crate::Writable for HSTIFR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstimr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstimr.rs index dc4d8168..a7ff2342 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstimr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstimr.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTIMR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DCONNIE` reader - Device Connection Interrupt Enable"] pub type DCONNIE_R = crate::BitReader; #[doc = "Field `DDISCIE` reader - Device Disconnection Interrupt Enable"] @@ -183,15 +170,13 @@ impl R { DMA_7_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Host Global Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstimr](index.html) module"] +#[doc = "Host Global Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstimr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTIMR_SPEC; impl crate::RegisterSpec for HSTIMR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstimr::R](R) reader structure"] -impl crate::Readable for HSTIMR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstimr::R`](R) reader structure"] +impl crate::Readable for HSTIMR_SPEC {} #[doc = "`reset()` method sets HSTIMR to value 0"] impl crate::Resettable for HSTIMR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstisr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstisr.rs index afeaf65c..36c47a76 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstisr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstisr.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTISR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `DCONNI` reader - Device Connection Interrupt"] pub type DCONNI_R = crate::BitReader; #[doc = "Field `DDISCI` reader - Device Disconnection Interrupt"] @@ -183,15 +170,13 @@ impl R { DMA_7_R::new(((self.bits >> 31) & 1) != 0) } } -#[doc = "Host Global Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstisr](index.html) module"] +#[doc = "Host Global Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstisr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTISR_SPEC; impl crate::RegisterSpec for HSTISR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstisr::R](R) reader structure"] -impl crate::Readable for HSTISR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstisr::R`](R) reader structure"] +impl crate::Readable for HSTISR_SPEC {} #[doc = "`reset()` method sets HSTISR to value 0"] impl crate::Resettable for HSTISR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpip.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpip.rs index f2b7647e..8aacc76d 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpip.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpip.rs @@ -1,111 +1,79 @@ #[doc = "Register `HSTPIP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTPIP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PEN0` reader - Pipe 0 Enable"] pub type PEN0_R = crate::BitReader; #[doc = "Field `PEN0` writer - Pipe 0 Enable"] -pub type PEN0_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN1` reader - Pipe 1 Enable"] pub type PEN1_R = crate::BitReader; #[doc = "Field `PEN1` writer - Pipe 1 Enable"] -pub type PEN1_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN2` reader - Pipe 2 Enable"] pub type PEN2_R = crate::BitReader; #[doc = "Field `PEN2` writer - Pipe 2 Enable"] -pub type PEN2_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN3` reader - Pipe 3 Enable"] pub type PEN3_R = crate::BitReader; #[doc = "Field `PEN3` writer - Pipe 3 Enable"] -pub type PEN3_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN4` reader - Pipe 4 Enable"] pub type PEN4_R = crate::BitReader; #[doc = "Field `PEN4` writer - Pipe 4 Enable"] -pub type PEN4_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN5` reader - Pipe 5 Enable"] pub type PEN5_R = crate::BitReader; #[doc = "Field `PEN5` writer - Pipe 5 Enable"] -pub type PEN5_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN6` reader - Pipe 6 Enable"] pub type PEN6_R = crate::BitReader; #[doc = "Field `PEN6` writer - Pipe 6 Enable"] -pub type PEN6_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN7` reader - Pipe 7 Enable"] pub type PEN7_R = crate::BitReader; #[doc = "Field `PEN7` writer - Pipe 7 Enable"] -pub type PEN7_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PEN8` reader - Pipe 8 Enable"] pub type PEN8_R = crate::BitReader; #[doc = "Field `PEN8` writer - Pipe 8 Enable"] -pub type PEN8_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PEN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST0` reader - Pipe 0 Reset"] pub type PRST0_R = crate::BitReader; #[doc = "Field `PRST0` writer - Pipe 0 Reset"] -pub type PRST0_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST1` reader - Pipe 1 Reset"] pub type PRST1_R = crate::BitReader; #[doc = "Field `PRST1` writer - Pipe 1 Reset"] -pub type PRST1_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST2` reader - Pipe 2 Reset"] pub type PRST2_R = crate::BitReader; #[doc = "Field `PRST2` writer - Pipe 2 Reset"] -pub type PRST2_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST3` reader - Pipe 3 Reset"] pub type PRST3_R = crate::BitReader; #[doc = "Field `PRST3` writer - Pipe 3 Reset"] -pub type PRST3_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST4` reader - Pipe 4 Reset"] pub type PRST4_R = crate::BitReader; #[doc = "Field `PRST4` writer - Pipe 4 Reset"] -pub type PRST4_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST5` reader - Pipe 5 Reset"] pub type PRST5_R = crate::BitReader; #[doc = "Field `PRST5` writer - Pipe 5 Reset"] -pub type PRST5_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST6` reader - Pipe 6 Reset"] pub type PRST6_R = crate::BitReader; #[doc = "Field `PRST6` writer - Pipe 6 Reset"] -pub type PRST6_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST7` reader - Pipe 7 Reset"] pub type PRST7_R = crate::BitReader; #[doc = "Field `PRST7` writer - Pipe 7 Reset"] -pub type PRST7_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PRST8` reader - Pipe 8 Reset"] pub type PRST8_R = crate::BitReader; #[doc = "Field `PRST8` writer - Pipe 8 Reset"] -pub type PRST8_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIP_SPEC, O>; +pub type PRST8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Pipe 0 Enable"] #[inline(always)] @@ -202,130 +170,127 @@ impl W { #[doc = "Bit 0 - Pipe 0 Enable"] #[inline(always)] #[must_use] - pub fn pen0(&mut self) -> PEN0_W<0> { + pub fn pen0(&mut self) -> PEN0_W { PEN0_W::new(self) } #[doc = "Bit 1 - Pipe 1 Enable"] #[inline(always)] #[must_use] - pub fn pen1(&mut self) -> PEN1_W<1> { + pub fn pen1(&mut self) -> PEN1_W { PEN1_W::new(self) } #[doc = "Bit 2 - Pipe 2 Enable"] #[inline(always)] #[must_use] - pub fn pen2(&mut self) -> PEN2_W<2> { + pub fn pen2(&mut self) -> PEN2_W { PEN2_W::new(self) } #[doc = "Bit 3 - Pipe 3 Enable"] #[inline(always)] #[must_use] - pub fn pen3(&mut self) -> PEN3_W<3> { + pub fn pen3(&mut self) -> PEN3_W { PEN3_W::new(self) } #[doc = "Bit 4 - Pipe 4 Enable"] #[inline(always)] #[must_use] - pub fn pen4(&mut self) -> PEN4_W<4> { + pub fn pen4(&mut self) -> PEN4_W { PEN4_W::new(self) } #[doc = "Bit 5 - Pipe 5 Enable"] #[inline(always)] #[must_use] - pub fn pen5(&mut self) -> PEN5_W<5> { + pub fn pen5(&mut self) -> PEN5_W { PEN5_W::new(self) } #[doc = "Bit 6 - Pipe 6 Enable"] #[inline(always)] #[must_use] - pub fn pen6(&mut self) -> PEN6_W<6> { + pub fn pen6(&mut self) -> PEN6_W { PEN6_W::new(self) } #[doc = "Bit 7 - Pipe 7 Enable"] #[inline(always)] #[must_use] - pub fn pen7(&mut self) -> PEN7_W<7> { + pub fn pen7(&mut self) -> PEN7_W { PEN7_W::new(self) } #[doc = "Bit 8 - Pipe 8 Enable"] #[inline(always)] #[must_use] - pub fn pen8(&mut self) -> PEN8_W<8> { + pub fn pen8(&mut self) -> PEN8_W { PEN8_W::new(self) } #[doc = "Bit 16 - Pipe 0 Reset"] #[inline(always)] #[must_use] - pub fn prst0(&mut self) -> PRST0_W<16> { + pub fn prst0(&mut self) -> PRST0_W { PRST0_W::new(self) } #[doc = "Bit 17 - Pipe 1 Reset"] #[inline(always)] #[must_use] - pub fn prst1(&mut self) -> PRST1_W<17> { + pub fn prst1(&mut self) -> PRST1_W { PRST1_W::new(self) } #[doc = "Bit 18 - Pipe 2 Reset"] #[inline(always)] #[must_use] - pub fn prst2(&mut self) -> PRST2_W<18> { + pub fn prst2(&mut self) -> PRST2_W { PRST2_W::new(self) } #[doc = "Bit 19 - Pipe 3 Reset"] #[inline(always)] #[must_use] - pub fn prst3(&mut self) -> PRST3_W<19> { + pub fn prst3(&mut self) -> PRST3_W { PRST3_W::new(self) } #[doc = "Bit 20 - Pipe 4 Reset"] #[inline(always)] #[must_use] - pub fn prst4(&mut self) -> PRST4_W<20> { + pub fn prst4(&mut self) -> PRST4_W { PRST4_W::new(self) } #[doc = "Bit 21 - Pipe 5 Reset"] #[inline(always)] #[must_use] - pub fn prst5(&mut self) -> PRST5_W<21> { + pub fn prst5(&mut self) -> PRST5_W { PRST5_W::new(self) } #[doc = "Bit 22 - Pipe 6 Reset"] #[inline(always)] #[must_use] - pub fn prst6(&mut self) -> PRST6_W<22> { + pub fn prst6(&mut self) -> PRST6_W { PRST6_W::new(self) } #[doc = "Bit 23 - Pipe 7 Reset"] #[inline(always)] #[must_use] - pub fn prst7(&mut self) -> PRST7_W<23> { + pub fn prst7(&mut self) -> PRST7_W { PRST7_W::new(self) } #[doc = "Bit 24 - Pipe 8 Reset"] #[inline(always)] #[must_use] - pub fn prst8(&mut self) -> PRST8_W<24> { + pub fn prst8(&mut self) -> PRST8_W { PRST8_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpip](index.html) module"] +#[doc = "Host Pipe Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpip::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpip::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIP_SPEC; impl crate::RegisterSpec for HSTPIP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpip::R](R) reader structure"] -impl crate::Readable for HSTPIP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstpip::W](W) writer structure"] +#[doc = "`read()` method returns [`hstpip::R`](R) reader structure"] +impl crate::Readable for HSTPIP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstpip::W`](W) writer structure"] impl crate::Writable for HSTPIP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg.rs index 14b4836a..dd7adb65 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg.rs @@ -1,43 +1,11 @@ #[doc = "Register `HSTPIPCFG[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTPIPCFG[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALLOC` reader - Pipe Memory Allocate"] pub type ALLOC_R = crate::BitReader; #[doc = "Field `ALLOC` writer - Pipe Memory Allocate"] -pub type ALLOC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPCFG_SPEC, O>; +pub type ALLOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PBK` reader - Pipe Banks"] pub type PBK_R = crate::FieldReader; #[doc = "Pipe Banks\n\nValue on reset: 0"] @@ -71,38 +39,42 @@ impl PBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1_BANK`"] + #[doc = "Single-bank pipe"] #[inline(always)] pub fn is_1_bank(&self) -> bool { *self == PBKSELECT_A::_1_BANK } - #[doc = "Checks if the value of the field is `_2_BANK`"] + #[doc = "Double-bank pipe"] #[inline(always)] pub fn is_2_bank(&self) -> bool { *self == PBKSELECT_A::_2_BANK } - #[doc = "Checks if the value of the field is `_3_BANK`"] + #[doc = "Triple-bank pipe"] #[inline(always)] pub fn is_3_bank(&self) -> bool { *self == PBKSELECT_A::_3_BANK } } #[doc = "Field `PBK` writer - Pipe Banks"] -pub type PBK_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPCFG_SPEC, 2, O, PBKSELECT_A>; -impl<'a, const O: u8> PBK_W<'a, O> { +pub type PBK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, PBKSELECT_A>; +impl<'a, REG, const O: u8> PBK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Single-bank pipe"] #[inline(always)] - pub fn _1_bank(self) -> &'a mut W { + pub fn _1_bank(self) -> &'a mut crate::W { self.variant(PBKSELECT_A::_1_BANK) } #[doc = "Double-bank pipe"] #[inline(always)] - pub fn _2_bank(self) -> &'a mut W { + pub fn _2_bank(self) -> &'a mut crate::W { self.variant(PBKSELECT_A::_2_BANK) } #[doc = "Triple-bank pipe"] #[inline(always)] - pub fn _3_bank(self) -> &'a mut W { + pub fn _3_bank(self) -> &'a mut crate::W { self.variant(PBKSELECT_A::_3_BANK) } } @@ -154,88 +126,92 @@ impl PSIZE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8 bytes"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == PSIZESELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16 bytes"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == PSIZESELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32 bytes"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == PSIZESELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64 bytes"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == PSIZESELECT_A::_64_BYTE } - #[doc = "Checks if the value of the field is `_128_BYTE`"] + #[doc = "128 bytes"] #[inline(always)] pub fn is_128_byte(&self) -> bool { *self == PSIZESELECT_A::_128_BYTE } - #[doc = "Checks if the value of the field is `_256_BYTE`"] + #[doc = "256 bytes"] #[inline(always)] pub fn is_256_byte(&self) -> bool { *self == PSIZESELECT_A::_256_BYTE } - #[doc = "Checks if the value of the field is `_512_BYTE`"] + #[doc = "512 bytes"] #[inline(always)] pub fn is_512_byte(&self) -> bool { *self == PSIZESELECT_A::_512_BYTE } - #[doc = "Checks if the value of the field is `_1024_BYTE`"] + #[doc = "1024 bytes"] #[inline(always)] pub fn is_1024_byte(&self) -> bool { *self == PSIZESELECT_A::_1024_BYTE } } #[doc = "Field `PSIZE` writer - Pipe Size"] -pub type PSIZE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, HSTPIPCFG_SPEC, 3, O, PSIZESELECT_A>; -impl<'a, const O: u8> PSIZE_W<'a, O> { +pub type PSIZE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, PSIZESELECT_A>; +impl<'a, REG, const O: u8> PSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8 bytes"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_8_BYTE) } #[doc = "16 bytes"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_16_BYTE) } #[doc = "32 bytes"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_32_BYTE) } #[doc = "64 bytes"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_64_BYTE) } #[doc = "128 bytes"] #[inline(always)] - pub fn _128_byte(self) -> &'a mut W { + pub fn _128_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_128_BYTE) } #[doc = "256 bytes"] #[inline(always)] - pub fn _256_byte(self) -> &'a mut W { + pub fn _256_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_256_BYTE) } #[doc = "512 bytes"] #[inline(always)] - pub fn _512_byte(self) -> &'a mut W { + pub fn _512_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_512_BYTE) } #[doc = "1024 bytes"] #[inline(always)] - pub fn _1024_byte(self) -> &'a mut W { + pub fn _1024_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_1024_BYTE) } } @@ -272,45 +248,49 @@ impl PTOKEN_R { _ => None, } } - #[doc = "Checks if the value of the field is `SETUP`"] + #[doc = "SETUP"] #[inline(always)] pub fn is_setup(&self) -> bool { *self == PTOKENSELECT_A::SETUP } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "IN"] #[inline(always)] pub fn is_in(&self) -> bool { *self == PTOKENSELECT_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "OUT"] #[inline(always)] pub fn is_out(&self) -> bool { *self == PTOKENSELECT_A::OUT } } #[doc = "Field `PTOKEN` writer - Pipe Token"] -pub type PTOKEN_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPCFG_SPEC, 2, O, PTOKENSELECT_A>; -impl<'a, const O: u8> PTOKEN_W<'a, O> { +pub type PTOKEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, PTOKENSELECT_A>; +impl<'a, REG, const O: u8> PTOKEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "SETUP"] #[inline(always)] - pub fn setup(self) -> &'a mut W { + pub fn setup(self) -> &'a mut crate::W { self.variant(PTOKENSELECT_A::SETUP) } #[doc = "IN"] #[inline(always)] - pub fn in_(self) -> &'a mut W { + pub fn in_(self) -> &'a mut crate::W { self.variant(PTOKENSELECT_A::IN) } #[doc = "OUT"] #[inline(always)] - pub fn out(self) -> &'a mut W { + pub fn out(self) -> &'a mut crate::W { self.variant(PTOKENSELECT_A::OUT) } } #[doc = "Field `AUTOSW` reader - Automatic Switch"] pub type AUTOSW_R = crate::BitReader; #[doc = "Field `AUTOSW` writer - Automatic Switch"] -pub type AUTOSW_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPCFG_SPEC, O>; +pub type AUTOSW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTYPE` reader - Pipe Type"] pub type PTYPE_R = crate::FieldReader; #[doc = "Pipe Type\n\nValue on reset: 0"] @@ -347,59 +327,63 @@ impl PTYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CTRL`"] + #[doc = "Control"] #[inline(always)] pub fn is_ctrl(&self) -> bool { *self == PTYPESELECT_A::CTRL } - #[doc = "Checks if the value of the field is `ISO`"] + #[doc = "Isochronous"] #[inline(always)] pub fn is_iso(&self) -> bool { *self == PTYPESELECT_A::ISO } - #[doc = "Checks if the value of the field is `BLK`"] + #[doc = "Bulk"] #[inline(always)] pub fn is_blk(&self) -> bool { *self == PTYPESELECT_A::BLK } - #[doc = "Checks if the value of the field is `INTRPT`"] + #[doc = "Interrupt"] #[inline(always)] pub fn is_intrpt(&self) -> bool { *self == PTYPESELECT_A::INTRPT } } #[doc = "Field `PTYPE` writer - Pipe Type"] -pub type PTYPE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, HSTPIPCFG_SPEC, 2, O, PTYPESELECT_A>; -impl<'a, const O: u8> PTYPE_W<'a, O> { +pub type PTYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, PTYPESELECT_A>; +impl<'a, REG, const O: u8> PTYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Control"] #[inline(always)] - pub fn ctrl(self) -> &'a mut W { + pub fn ctrl(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::CTRL) } #[doc = "Isochronous"] #[inline(always)] - pub fn iso(self) -> &'a mut W { + pub fn iso(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::ISO) } #[doc = "Bulk"] #[inline(always)] - pub fn blk(self) -> &'a mut W { + pub fn blk(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::BLK) } #[doc = "Interrupt"] #[inline(always)] - pub fn intrpt(self) -> &'a mut W { + pub fn intrpt(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::INTRPT) } } #[doc = "Field `PEPNUM` reader - Pipe Endpoint Number"] pub type PEPNUM_R = crate::FieldReader; #[doc = "Field `PEPNUM` writer - Pipe Endpoint Number"] -pub type PEPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPCFG_SPEC, 4, O>; +pub type PEPNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `INTFRQ` reader - Pipe Interrupt Request Frequency"] pub type INTFRQ_R = crate::FieldReader; #[doc = "Field `INTFRQ` writer - Pipe Interrupt Request Frequency"] -pub type INTFRQ_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPCFG_SPEC, 8, O>; +pub type INTFRQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 1 - Pipe Memory Allocate"] #[inline(always)] @@ -446,70 +430,67 @@ impl W { #[doc = "Bit 1 - Pipe Memory Allocate"] #[inline(always)] #[must_use] - pub fn alloc(&mut self) -> ALLOC_W<1> { + pub fn alloc(&mut self) -> ALLOC_W { ALLOC_W::new(self) } #[doc = "Bits 2:3 - Pipe Banks"] #[inline(always)] #[must_use] - pub fn pbk(&mut self) -> PBK_W<2> { + pub fn pbk(&mut self) -> PBK_W { PBK_W::new(self) } #[doc = "Bits 4:6 - Pipe Size"] #[inline(always)] #[must_use] - pub fn psize(&mut self) -> PSIZE_W<4> { + pub fn psize(&mut self) -> PSIZE_W { PSIZE_W::new(self) } #[doc = "Bits 8:9 - Pipe Token"] #[inline(always)] #[must_use] - pub fn ptoken(&mut self) -> PTOKEN_W<8> { + pub fn ptoken(&mut self) -> PTOKEN_W { PTOKEN_W::new(self) } #[doc = "Bit 10 - Automatic Switch"] #[inline(always)] #[must_use] - pub fn autosw(&mut self) -> AUTOSW_W<10> { + pub fn autosw(&mut self) -> AUTOSW_W { AUTOSW_W::new(self) } #[doc = "Bits 12:13 - Pipe Type"] #[inline(always)] #[must_use] - pub fn ptype(&mut self) -> PTYPE_W<12> { + pub fn ptype(&mut self) -> PTYPE_W { PTYPE_W::new(self) } #[doc = "Bits 16:19 - Pipe Endpoint Number"] #[inline(always)] #[must_use] - pub fn pepnum(&mut self) -> PEPNUM_W<16> { + pub fn pepnum(&mut self) -> PEPNUM_W { PEPNUM_W::new(self) } #[doc = "Bits 24:31 - Pipe Interrupt Request Frequency"] #[inline(always)] #[must_use] - pub fn intfrq(&mut self) -> INTFRQ_W<24> { + pub fn intfrq(&mut self) -> INTFRQ_W { INTFRQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipcfg](index.html) module"] +#[doc = "Host Pipe Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPCFG_SPEC; impl crate::RegisterSpec for HSTPIPCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipcfg::R](R) reader structure"] -impl crate::Readable for HSTPIPCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstpipcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`hstpipcfg::R`](R) reader structure"] +impl crate::Readable for HSTPIPCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstpipcfg::W`](W) writer structure"] impl crate::Writable for HSTPIPCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg_ctrl_bulk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg_ctrl_bulk_mode.rs index 988a9080..f18cbb22 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg_ctrl_bulk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipcfg_ctrl_bulk_mode.rs @@ -1,43 +1,11 @@ #[doc = "Register `HSTPIPCFG_CTRL_BULK_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTPIPCFG_CTRL_BULK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ALLOC` reader - Pipe Memory Allocate"] pub type ALLOC_R = crate::BitReader; #[doc = "Field `ALLOC` writer - Pipe Memory Allocate"] -pub type ALLOC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, O>; +pub type ALLOC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PBK` reader - Pipe Banks"] pub type PBK_R = crate::FieldReader; #[doc = "Pipe Banks\n\nValue on reset: 0"] @@ -71,39 +39,42 @@ impl PBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `_1_BANK`"] + #[doc = "Single-bank pipe"] #[inline(always)] pub fn is_1_bank(&self) -> bool { *self == PBKSELECT_A::_1_BANK } - #[doc = "Checks if the value of the field is `_2_BANK`"] + #[doc = "Double-bank pipe"] #[inline(always)] pub fn is_2_bank(&self) -> bool { *self == PBKSELECT_A::_2_BANK } - #[doc = "Checks if the value of the field is `_3_BANK`"] + #[doc = "Triple-bank pipe"] #[inline(always)] pub fn is_3_bank(&self) -> bool { *self == PBKSELECT_A::_3_BANK } } #[doc = "Field `PBK` writer - Pipe Banks"] -pub type PBK_W<'a, const O: u8> = - crate::FieldWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, 2, O, PBKSELECT_A>; -impl<'a, const O: u8> PBK_W<'a, O> { +pub type PBK_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, PBKSELECT_A>; +impl<'a, REG, const O: u8> PBK_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Single-bank pipe"] #[inline(always)] - pub fn _1_bank(self) -> &'a mut W { + pub fn _1_bank(self) -> &'a mut crate::W { self.variant(PBKSELECT_A::_1_BANK) } #[doc = "Double-bank pipe"] #[inline(always)] - pub fn _2_bank(self) -> &'a mut W { + pub fn _2_bank(self) -> &'a mut crate::W { self.variant(PBKSELECT_A::_2_BANK) } #[doc = "Triple-bank pipe"] #[inline(always)] - pub fn _3_bank(self) -> &'a mut W { + pub fn _3_bank(self) -> &'a mut crate::W { self.variant(PBKSELECT_A::_3_BANK) } } @@ -155,89 +126,92 @@ impl PSIZE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_8_BYTE`"] + #[doc = "8 bytes"] #[inline(always)] pub fn is_8_byte(&self) -> bool { *self == PSIZESELECT_A::_8_BYTE } - #[doc = "Checks if the value of the field is `_16_BYTE`"] + #[doc = "16 bytes"] #[inline(always)] pub fn is_16_byte(&self) -> bool { *self == PSIZESELECT_A::_16_BYTE } - #[doc = "Checks if the value of the field is `_32_BYTE`"] + #[doc = "32 bytes"] #[inline(always)] pub fn is_32_byte(&self) -> bool { *self == PSIZESELECT_A::_32_BYTE } - #[doc = "Checks if the value of the field is `_64_BYTE`"] + #[doc = "64 bytes"] #[inline(always)] pub fn is_64_byte(&self) -> bool { *self == PSIZESELECT_A::_64_BYTE } - #[doc = "Checks if the value of the field is `_128_BYTE`"] + #[doc = "128 bytes"] #[inline(always)] pub fn is_128_byte(&self) -> bool { *self == PSIZESELECT_A::_128_BYTE } - #[doc = "Checks if the value of the field is `_256_BYTE`"] + #[doc = "256 bytes"] #[inline(always)] pub fn is_256_byte(&self) -> bool { *self == PSIZESELECT_A::_256_BYTE } - #[doc = "Checks if the value of the field is `_512_BYTE`"] + #[doc = "512 bytes"] #[inline(always)] pub fn is_512_byte(&self) -> bool { *self == PSIZESELECT_A::_512_BYTE } - #[doc = "Checks if the value of the field is `_1024_BYTE`"] + #[doc = "1024 bytes"] #[inline(always)] pub fn is_1024_byte(&self) -> bool { *self == PSIZESELECT_A::_1024_BYTE } } #[doc = "Field `PSIZE` writer - Pipe Size"] -pub type PSIZE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, 3, O, PSIZESELECT_A>; -impl<'a, const O: u8> PSIZE_W<'a, O> { +pub type PSIZE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 3, O, PSIZESELECT_A>; +impl<'a, REG, const O: u8> PSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "8 bytes"] #[inline(always)] - pub fn _8_byte(self) -> &'a mut W { + pub fn _8_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_8_BYTE) } #[doc = "16 bytes"] #[inline(always)] - pub fn _16_byte(self) -> &'a mut W { + pub fn _16_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_16_BYTE) } #[doc = "32 bytes"] #[inline(always)] - pub fn _32_byte(self) -> &'a mut W { + pub fn _32_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_32_BYTE) } #[doc = "64 bytes"] #[inline(always)] - pub fn _64_byte(self) -> &'a mut W { + pub fn _64_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_64_BYTE) } #[doc = "128 bytes"] #[inline(always)] - pub fn _128_byte(self) -> &'a mut W { + pub fn _128_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_128_BYTE) } #[doc = "256 bytes"] #[inline(always)] - pub fn _256_byte(self) -> &'a mut W { + pub fn _256_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_256_BYTE) } #[doc = "512 bytes"] #[inline(always)] - pub fn _512_byte(self) -> &'a mut W { + pub fn _512_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_512_BYTE) } #[doc = "1024 bytes"] #[inline(always)] - pub fn _1024_byte(self) -> &'a mut W { + pub fn _1024_byte(self) -> &'a mut crate::W { self.variant(PSIZESELECT_A::_1024_BYTE) } } @@ -274,46 +248,49 @@ impl PTOKEN_R { _ => None, } } - #[doc = "Checks if the value of the field is `SETUP`"] + #[doc = "SETUP"] #[inline(always)] pub fn is_setup(&self) -> bool { *self == PTOKENSELECT_A::SETUP } - #[doc = "Checks if the value of the field is `IN`"] + #[doc = "IN"] #[inline(always)] pub fn is_in(&self) -> bool { *self == PTOKENSELECT_A::IN } - #[doc = "Checks if the value of the field is `OUT`"] + #[doc = "OUT"] #[inline(always)] pub fn is_out(&self) -> bool { *self == PTOKENSELECT_A::OUT } } #[doc = "Field `PTOKEN` writer - Pipe Token"] -pub type PTOKEN_W<'a, const O: u8> = - crate::FieldWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, 2, O, PTOKENSELECT_A>; -impl<'a, const O: u8> PTOKEN_W<'a, O> { +pub type PTOKEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, PTOKENSELECT_A>; +impl<'a, REG, const O: u8> PTOKEN_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "SETUP"] #[inline(always)] - pub fn setup(self) -> &'a mut W { + pub fn setup(self) -> &'a mut crate::W { self.variant(PTOKENSELECT_A::SETUP) } #[doc = "IN"] #[inline(always)] - pub fn in_(self) -> &'a mut W { + pub fn in_(self) -> &'a mut crate::W { self.variant(PTOKENSELECT_A::IN) } #[doc = "OUT"] #[inline(always)] - pub fn out(self) -> &'a mut W { + pub fn out(self) -> &'a mut crate::W { self.variant(PTOKENSELECT_A::OUT) } } #[doc = "Field `AUTOSW` reader - Automatic Switch"] pub type AUTOSW_R = crate::BitReader; #[doc = "Field `AUTOSW` writer - Automatic Switch"] -pub type AUTOSW_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, O>; +pub type AUTOSW_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PTYPE` reader - Pipe Type"] pub type PTYPE_R = crate::FieldReader; #[doc = "Pipe Type\n\nValue on reset: 0"] @@ -350,64 +327,67 @@ impl PTYPE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `CTRL`"] + #[doc = "Control"] #[inline(always)] pub fn is_ctrl(&self) -> bool { *self == PTYPESELECT_A::CTRL } - #[doc = "Checks if the value of the field is `ISO`"] + #[doc = "Isochronous"] #[inline(always)] pub fn is_iso(&self) -> bool { *self == PTYPESELECT_A::ISO } - #[doc = "Checks if the value of the field is `BLK`"] + #[doc = "Bulk"] #[inline(always)] pub fn is_blk(&self) -> bool { *self == PTYPESELECT_A::BLK } - #[doc = "Checks if the value of the field is `INTRPT`"] + #[doc = "Interrupt"] #[inline(always)] pub fn is_intrpt(&self) -> bool { *self == PTYPESELECT_A::INTRPT } } #[doc = "Field `PTYPE` writer - Pipe Type"] -pub type PTYPE_W<'a, const O: u8> = - crate::FieldWriterSafe<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, 2, O, PTYPESELECT_A>; -impl<'a, const O: u8> PTYPE_W<'a, O> { +pub type PTYPE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, PTYPESELECT_A>; +impl<'a, REG, const O: u8> PTYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Control"] #[inline(always)] - pub fn ctrl(self) -> &'a mut W { + pub fn ctrl(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::CTRL) } #[doc = "Isochronous"] #[inline(always)] - pub fn iso(self) -> &'a mut W { + pub fn iso(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::ISO) } #[doc = "Bulk"] #[inline(always)] - pub fn blk(self) -> &'a mut W { + pub fn blk(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::BLK) } #[doc = "Interrupt"] #[inline(always)] - pub fn intrpt(self) -> &'a mut W { + pub fn intrpt(self) -> &'a mut crate::W { self.variant(PTYPESELECT_A::INTRPT) } } #[doc = "Field `PEPNUM` reader - Pipe Endpoint Number"] pub type PEPNUM_R = crate::FieldReader; #[doc = "Field `PEPNUM` writer - Pipe Endpoint Number"] -pub type PEPNUM_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, 4, O>; +pub type PEPNUM_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PINGEN` reader - Ping Enable"] pub type PINGEN_R = crate::BitReader; #[doc = "Field `PINGEN` writer - Ping Enable"] -pub type PINGEN_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, O>; +pub type PINGEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BINTERVAL` reader - bInterval Parameter for the Bulk-Out/Ping Transaction"] pub type BINTERVAL_R = crate::FieldReader; #[doc = "Field `BINTERVAL` writer - bInterval Parameter for the Bulk-Out/Ping Transaction"] -pub type BINTERVAL_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPCFG_CTRL_BULK_MODE_SPEC, 8, O>; +pub type BINTERVAL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; impl R { #[doc = "Bit 1 - Pipe Memory Allocate"] #[inline(always)] @@ -459,76 +439,73 @@ impl W { #[doc = "Bit 1 - Pipe Memory Allocate"] #[inline(always)] #[must_use] - pub fn alloc(&mut self) -> ALLOC_W<1> { + pub fn alloc(&mut self) -> ALLOC_W { ALLOC_W::new(self) } #[doc = "Bits 2:3 - Pipe Banks"] #[inline(always)] #[must_use] - pub fn pbk(&mut self) -> PBK_W<2> { + pub fn pbk(&mut self) -> PBK_W { PBK_W::new(self) } #[doc = "Bits 4:6 - Pipe Size"] #[inline(always)] #[must_use] - pub fn psize(&mut self) -> PSIZE_W<4> { + pub fn psize(&mut self) -> PSIZE_W { PSIZE_W::new(self) } #[doc = "Bits 8:9 - Pipe Token"] #[inline(always)] #[must_use] - pub fn ptoken(&mut self) -> PTOKEN_W<8> { + pub fn ptoken(&mut self) -> PTOKEN_W { PTOKEN_W::new(self) } #[doc = "Bit 10 - Automatic Switch"] #[inline(always)] #[must_use] - pub fn autosw(&mut self) -> AUTOSW_W<10> { + pub fn autosw(&mut self) -> AUTOSW_W { AUTOSW_W::new(self) } #[doc = "Bits 12:13 - Pipe Type"] #[inline(always)] #[must_use] - pub fn ptype(&mut self) -> PTYPE_W<12> { + pub fn ptype(&mut self) -> PTYPE_W { PTYPE_W::new(self) } #[doc = "Bits 16:19 - Pipe Endpoint Number"] #[inline(always)] #[must_use] - pub fn pepnum(&mut self) -> PEPNUM_W<16> { + pub fn pepnum(&mut self) -> PEPNUM_W { PEPNUM_W::new(self) } #[doc = "Bit 20 - Ping Enable"] #[inline(always)] #[must_use] - pub fn pingen(&mut self) -> PINGEN_W<20> { + pub fn pingen(&mut self) -> PINGEN_W { PINGEN_W::new(self) } #[doc = "Bits 24:31 - bInterval Parameter for the Bulk-Out/Ping Transaction"] #[inline(always)] #[must_use] - pub fn binterval(&mut self) -> BINTERVAL_W<24> { + pub fn binterval(&mut self) -> BINTERVAL_W { BINTERVAL_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipcfg_ctrl_bulk_mode](index.html) module"] +#[doc = "Host Pipe Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipcfg_ctrl_bulk_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipcfg_ctrl_bulk_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPCFG_CTRL_BULK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPCFG_CTRL_BULK_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipcfg_ctrl_bulk_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPCFG_CTRL_BULK_MODE_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstpipcfg_ctrl_bulk_mode::W](W) writer structure"] +#[doc = "`read()` method returns [`hstpipcfg_ctrl_bulk_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPCFG_CTRL_BULK_MODE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstpipcfg_ctrl_bulk_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPCFG_CTRL_BULK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpiperr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpiperr.rs index 98b54bfb..ab446643 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpiperr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpiperr.rs @@ -1,63 +1,31 @@ #[doc = "Register `HSTPIPERR[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTPIPERR[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DATATGL` reader - Data Toggle Error"] pub type DATATGL_R = crate::BitReader; #[doc = "Field `DATATGL` writer - Data Toggle Error"] -pub type DATATGL_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPERR_SPEC, O>; +pub type DATATGL_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DATAPID` reader - Data PID Error"] pub type DATAPID_R = crate::BitReader; #[doc = "Field `DATAPID` writer - Data PID Error"] -pub type DATAPID_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPERR_SPEC, O>; +pub type DATAPID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PID` reader - Data PID Error"] pub type PID_R = crate::BitReader; #[doc = "Field `PID` writer - Data PID Error"] -pub type PID_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPERR_SPEC, O>; +pub type PID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TIMEOUT` reader - Time-Out Error"] pub type TIMEOUT_R = crate::BitReader; #[doc = "Field `TIMEOUT` writer - Time-Out Error"] -pub type TIMEOUT_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPERR_SPEC, O>; +pub type TIMEOUT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRC16` reader - CRC16 Error"] pub type CRC16_R = crate::BitReader; #[doc = "Field `CRC16` writer - CRC16 Error"] -pub type CRC16_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPERR_SPEC, O>; +pub type CRC16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `COUNTER` reader - Error Counter"] pub type COUNTER_R = crate::FieldReader; #[doc = "Field `COUNTER` writer - Error Counter"] -pub type COUNTER_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPERR_SPEC, 2, O>; +pub type COUNTER_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O>; impl R { #[doc = "Bit 0 - Data Toggle Error"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bit 0 - Data Toggle Error"] #[inline(always)] #[must_use] - pub fn datatgl(&mut self) -> DATATGL_W<0> { + pub fn datatgl(&mut self) -> DATATGL_W { DATATGL_W::new(self) } #[doc = "Bit 1 - Data PID Error"] #[inline(always)] #[must_use] - pub fn datapid(&mut self) -> DATAPID_W<1> { + pub fn datapid(&mut self) -> DATAPID_W { DATAPID_W::new(self) } #[doc = "Bit 2 - Data PID Error"] #[inline(always)] #[must_use] - pub fn pid(&mut self) -> PID_W<2> { + pub fn pid(&mut self) -> PID_W { PID_W::new(self) } #[doc = "Bit 3 - Time-Out Error"] #[inline(always)] #[must_use] - pub fn timeout(&mut self) -> TIMEOUT_W<3> { + pub fn timeout(&mut self) -> TIMEOUT_W { TIMEOUT_W::new(self) } #[doc = "Bit 4 - CRC16 Error"] #[inline(always)] #[must_use] - pub fn crc16(&mut self) -> CRC16_W<4> { + pub fn crc16(&mut self) -> CRC16_W { CRC16_W::new(self) } #[doc = "Bits 5:6 - Error Counter"] #[inline(always)] #[must_use] - pub fn counter(&mut self) -> COUNTER_W<5> { + pub fn counter(&mut self) -> COUNTER_W { COUNTER_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Error Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpiperr](index.html) module"] +#[doc = "Host Pipe Error Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpiperr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpiperr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPERR_SPEC; impl crate::RegisterSpec for HSTPIPERR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpiperr::R](R) reader structure"] -impl crate::Readable for HSTPIPERR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstpiperr::W](W) writer structure"] +#[doc = "`read()` method returns [`hstpiperr::R`](R) reader structure"] +impl crate::Readable for HSTPIPERR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstpiperr::W`](W) writer structure"] impl crate::Writable for HSTPIPERR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_blk_mode.rs index 7e136dee..14eac5e3 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_blk_mode.rs @@ -1,96 +1,76 @@ #[doc = "Register `HSTPIPICR_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIC` writer - Received IN Data Interrupt Clear"] -pub type RXINIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type RXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIC` writer - Transmitted OUT Data Interrupt Clear"] -pub type TXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type TXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPIC` writer - Transmitted SETUP Interrupt Clear"] -pub type TXSTPIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type TXSTPIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIC` writer - NAKed Interrupt Clear"] -pub type NAKEDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type NAKEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDIC` writer - Received STALLed Interrupt Clear"] -pub type RXSTALLDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type RXSTALLDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_BLK_MODE_SPEC, O>; +pub type SHORTPACKETIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxinic(&mut self) -> RXINIC_W<0> { + pub fn rxinic(&mut self) -> RXINIC_W { RXINIC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txoutic(&mut self) -> TXOUTIC_W<1> { + pub fn txoutic(&mut self) -> TXOUTIC_W { TXOUTIC_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txstpic(&mut self) -> TXSTPIC_W<2> { + pub fn txstpic(&mut self) -> TXSTPIC_W { TXSTPIC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakedic(&mut self) -> NAKEDIC_W<4> { + pub fn nakedic(&mut self) -> NAKEDIC_W { NAKEDIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstalldic(&mut self) -> RXSTALLDIC_W<6> { + pub fn rxstalldic(&mut self) -> RXSTALLDIC_W { RXSTALLDIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W<7> { + pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W { SHORTPACKETIC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipicr_blk_mode](index.html) module"] +#[doc = "Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPICR_BLK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPICR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipicr_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipicr_blk_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPICR_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_ctrl_mode.rs index 0db4b1f6..c3377b41 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_ctrl_mode.rs @@ -1,96 +1,76 @@ #[doc = "Register `HSTPIPICR_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIC` writer - Received IN Data Interrupt Clear"] -pub type RXINIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type RXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIC` writer - Transmitted OUT Data Interrupt Clear"] -pub type TXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type TXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPIC` writer - Transmitted SETUP Interrupt Clear"] -pub type TXSTPIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type TXSTPIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIC` writer - NAKed Interrupt Clear"] -pub type NAKEDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type NAKEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDIC` writer - Received STALLed Interrupt Clear"] -pub type RXSTALLDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type RXSTALLDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxinic(&mut self) -> RXINIC_W<0> { + pub fn rxinic(&mut self) -> RXINIC_W { RXINIC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txoutic(&mut self) -> TXOUTIC_W<1> { + pub fn txoutic(&mut self) -> TXOUTIC_W { TXOUTIC_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txstpic(&mut self) -> TXSTPIC_W<2> { + pub fn txstpic(&mut self) -> TXSTPIC_W { TXSTPIC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakedic(&mut self) -> NAKEDIC_W<4> { + pub fn nakedic(&mut self) -> NAKEDIC_W { NAKEDIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstalldic(&mut self) -> RXSTALLDIC_W<6> { + pub fn rxstalldic(&mut self) -> RXSTALLDIC_W { RXSTALLDIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W<7> { + pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W { SHORTPACKETIC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipicr_ctrl_mode](index.html) module"] +#[doc = "Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPICR_CTRL_MODE_SPEC; impl crate::RegisterSpec for HSTPIPICR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipicr_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipicr_ctrl_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPICR_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_intrpt_mode.rs index f7e8c991..ab23842b 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_intrpt_mode.rs @@ -1,96 +1,76 @@ #[doc = "Register `HSTPIPICR_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIC` writer - Received IN Data Interrupt Clear"] -pub type RXINIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type RXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIC` writer - Transmitted OUT Data Interrupt Clear"] -pub type TXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type TXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIC` writer - Underflow Interrupt Clear"] -pub type UNDERFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type UNDERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIC` writer - NAKed Interrupt Clear"] -pub type NAKEDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type NAKEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDIC` writer - Received STALLed Interrupt Clear"] -pub type RXSTALLDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type RXSTALLDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxinic(&mut self) -> RXINIC_W<0> { + pub fn rxinic(&mut self) -> RXINIC_W { RXINIC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txoutic(&mut self) -> TXOUTIC_W<1> { + pub fn txoutic(&mut self) -> TXOUTIC_W { TXOUTIC_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn underfic(&mut self) -> UNDERFIC_W<2> { + pub fn underfic(&mut self) -> UNDERFIC_W { UNDERFIC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakedic(&mut self) -> NAKEDIC_W<4> { + pub fn nakedic(&mut self) -> NAKEDIC_W { NAKEDIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxstalldic(&mut self) -> RXSTALLDIC_W<6> { + pub fn rxstalldic(&mut self) -> RXSTALLDIC_W { RXSTALLDIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W<7> { + pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W { SHORTPACKETIC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipicr_intrpt_mode](index.html) module"] +#[doc = "Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPICR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for HSTPIPICR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipicr_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipicr_intrpt_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPICR_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_iso_mode.rs index d533f367..b5d16577 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipicr_iso_mode.rs @@ -1,96 +1,76 @@ #[doc = "Register `HSTPIPICR_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIC` writer - Received IN Data Interrupt Clear"] -pub type RXINIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type RXINIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIC` writer - Transmitted OUT Data Interrupt Clear"] -pub type TXOUTIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type TXOUTIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIC` writer - Underflow Interrupt Clear"] -pub type UNDERFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type UNDERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIC` writer - NAKed Interrupt Clear"] -pub type NAKEDIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type NAKEDIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIC` writer - Overflow Interrupt Clear"] -pub type OVERFIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type OVERFIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERRIC` writer - CRC Error Interrupt Clear"] -pub type CRCERRIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type CRCERRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIC` writer - Short Packet Interrupt Clear"] -pub type SHORTPACKETIC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPICR_ISO_MODE_SPEC, O>; +pub type SHORTPACKETIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rxinic(&mut self) -> RXINIC_W<0> { + pub fn rxinic(&mut self) -> RXINIC_W { RXINIC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Clear"] #[inline(always)] #[must_use] - pub fn txoutic(&mut self) -> TXOUTIC_W<1> { + pub fn txoutic(&mut self) -> TXOUTIC_W { TXOUTIC_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn underfic(&mut self) -> UNDERFIC_W<2> { + pub fn underfic(&mut self) -> UNDERFIC_W { UNDERFIC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Clear"] #[inline(always)] #[must_use] - pub fn nakedic(&mut self) -> NAKEDIC_W<4> { + pub fn nakedic(&mut self) -> NAKEDIC_W { NAKEDIC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Clear"] #[inline(always)] #[must_use] - pub fn overfic(&mut self) -> OVERFIC_W<5> { + pub fn overfic(&mut self) -> OVERFIC_W { OVERFIC_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Clear"] #[inline(always)] #[must_use] - pub fn crcerric(&mut self) -> CRCERRIC_W<6> { + pub fn crcerric(&mut self) -> CRCERRIC_W { CRCERRIC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Clear"] #[inline(always)] #[must_use] - pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W<7> { + pub fn shortpacketic(&mut self) -> SHORTPACKETIC_W { SHORTPACKETIC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipicr_iso_mode](index.html) module"] +#[doc = "Host Pipe Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipicr_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPICR_ISO_MODE_SPEC; impl crate::RegisterSpec for HSTPIPICR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipicr_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipicr_iso_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPICR_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_blk_mode.rs index 9a905b60..143106b0 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_blk_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIDR_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINEC` writer - Received IN Data Interrupt Disable"] -pub type RXINEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type RXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTEC` writer - Transmitted OUT Data Interrupt Disable"] -pub type TXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type TXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPEC` writer - Transmitted SETUP Interrupt Disable"] -pub type TXSTPEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type TXSTPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERREC` writer - Pipe Error Interrupt Disable"] -pub type PERREC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type PERREC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDEC` writer - NAKed Interrupt Disable"] -pub type NAKEDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type NAKEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIEC` writer - Overflow Interrupt Disable"] -pub type OVERFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type OVERFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDEC` writer - Received STALLed Interrupt Disable"] -pub type RXSTALLDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type RXSTALLDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIEC` writer - Short Packet Interrupt Disable"] -pub type SHORTPACKETIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type SHORTPACKETIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Disable"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Disable"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAC` writer - Pipe Interrupts Disable HDMA Request Disable"] -pub type PDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type PDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZEC` writer - Pipe Freeze Disable"] -pub type PFREEZEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_BLK_MODE_SPEC, O>; +pub type PFREEZEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxinec(&mut self) -> RXINEC_W<0> { + pub fn rxinec(&mut self) -> RXINEC_W { RXINEC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txoutec(&mut self) -> TXOUTEC_W<1> { + pub fn txoutec(&mut self) -> TXOUTEC_W { TXOUTEC_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txstpec(&mut self) -> TXSTPEC_W<2> { + pub fn txstpec(&mut self) -> TXSTPEC_W { TXSTPEC_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn perrec(&mut self) -> PERREC_W<3> { + pub fn perrec(&mut self) -> PERREC_W { PERREC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nakedec(&mut self) -> NAKEDEC_W<4> { + pub fn nakedec(&mut self) -> NAKEDEC_W { NAKEDEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn overfiec(&mut self) -> OVERFIEC_W<5> { + pub fn overfiec(&mut self) -> OVERFIEC_W { OVERFIEC_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxstalldec(&mut self) -> RXSTALLDEC_W<6> { + pub fn rxstalldec(&mut self) -> RXSTALLDEC_W { RXSTALLDEC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Disable"] #[inline(always)] #[must_use] - pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W<7> { + pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W { SHORTPACKETIEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Disable"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Disable"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Disable"] #[inline(always)] #[must_use] - pub fn pdishdmac(&mut self) -> PDISHDMAC_W<16> { + pub fn pdishdmac(&mut self) -> PDISHDMAC_W { PDISHDMAC_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Disable"] #[inline(always)] #[must_use] - pub fn pfreezec(&mut self) -> PFREEZEC_W<17> { + pub fn pfreezec(&mut self) -> PFREEZEC_W { PFREEZEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipidr_blk_mode](index.html) module"] +#[doc = "Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIDR_BLK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIDR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipidr_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipidr_blk_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIDR_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_ctrl_mode.rs index 5f37004c..8f9f91a0 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_ctrl_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIDR_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINEC` writer - Received IN Data Interrupt Disable"] -pub type RXINEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type RXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTEC` writer - Transmitted OUT Data Interrupt Disable"] -pub type TXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type TXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPEC` writer - Transmitted SETUP Interrupt Disable"] -pub type TXSTPEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type TXSTPEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERREC` writer - Pipe Error Interrupt Disable"] -pub type PERREC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type PERREC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDEC` writer - NAKed Interrupt Disable"] -pub type NAKEDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type NAKEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIEC` writer - Overflow Interrupt Disable"] -pub type OVERFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type OVERFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDEC` writer - Received STALLed Interrupt Disable"] -pub type RXSTALLDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type RXSTALLDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIEC` writer - Short Packet Interrupt Disable"] -pub type SHORTPACKETIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Disable"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Disable"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAC` writer - Pipe Interrupts Disable HDMA Request Disable"] -pub type PDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type PDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZEC` writer - Pipe Freeze Disable"] -pub type PFREEZEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_CTRL_MODE_SPEC, O>; +pub type PFREEZEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxinec(&mut self) -> RXINEC_W<0> { + pub fn rxinec(&mut self) -> RXINEC_W { RXINEC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txoutec(&mut self) -> TXOUTEC_W<1> { + pub fn txoutec(&mut self) -> TXOUTEC_W { TXOUTEC_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txstpec(&mut self) -> TXSTPEC_W<2> { + pub fn txstpec(&mut self) -> TXSTPEC_W { TXSTPEC_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn perrec(&mut self) -> PERREC_W<3> { + pub fn perrec(&mut self) -> PERREC_W { PERREC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nakedec(&mut self) -> NAKEDEC_W<4> { + pub fn nakedec(&mut self) -> NAKEDEC_W { NAKEDEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn overfiec(&mut self) -> OVERFIEC_W<5> { + pub fn overfiec(&mut self) -> OVERFIEC_W { OVERFIEC_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxstalldec(&mut self) -> RXSTALLDEC_W<6> { + pub fn rxstalldec(&mut self) -> RXSTALLDEC_W { RXSTALLDEC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Disable"] #[inline(always)] #[must_use] - pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W<7> { + pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W { SHORTPACKETIEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Disable"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Disable"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Disable"] #[inline(always)] #[must_use] - pub fn pdishdmac(&mut self) -> PDISHDMAC_W<16> { + pub fn pdishdmac(&mut self) -> PDISHDMAC_W { PDISHDMAC_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Disable"] #[inline(always)] #[must_use] - pub fn pfreezec(&mut self) -> PFREEZEC_W<17> { + pub fn pfreezec(&mut self) -> PFREEZEC_W { PFREEZEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipidr_ctrl_mode](index.html) module"] +#[doc = "Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIDR_CTRL_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIDR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipidr_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipidr_ctrl_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIDR_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_intrpt_mode.rs index 9ab28f14..7b0c1389 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_intrpt_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIDR_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINEC` writer - Received IN Data Interrupt Disable"] -pub type RXINEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type RXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTEC` writer - Transmitted OUT Data Interrupt Disable"] -pub type TXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type TXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIEC` writer - Underflow Interrupt Disable"] -pub type UNDERFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type UNDERFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERREC` writer - Pipe Error Interrupt Disable"] -pub type PERREC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type PERREC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDEC` writer - NAKed Interrupt Disable"] -pub type NAKEDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type NAKEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIEC` writer - Overflow Interrupt Disable"] -pub type OVERFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type OVERFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDEC` writer - Received STALLed Interrupt Disable"] -pub type RXSTALLDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type RXSTALLDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIEC` writer - Short Packet Interrupt Disable"] -pub type SHORTPACKETIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Disable"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Disable"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAC` writer - Pipe Interrupts Disable HDMA Request Disable"] -pub type PDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type PDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZEC` writer - Pipe Freeze Disable"] -pub type PFREEZEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_INTRPT_MODE_SPEC, O>; +pub type PFREEZEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxinec(&mut self) -> RXINEC_W<0> { + pub fn rxinec(&mut self) -> RXINEC_W { RXINEC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txoutec(&mut self) -> TXOUTEC_W<1> { + pub fn txoutec(&mut self) -> TXOUTEC_W { TXOUTEC_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn underfiec(&mut self) -> UNDERFIEC_W<2> { + pub fn underfiec(&mut self) -> UNDERFIEC_W { UNDERFIEC_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn perrec(&mut self) -> PERREC_W<3> { + pub fn perrec(&mut self) -> PERREC_W { PERREC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nakedec(&mut self) -> NAKEDEC_W<4> { + pub fn nakedec(&mut self) -> NAKEDEC_W { NAKEDEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn overfiec(&mut self) -> OVERFIEC_W<5> { + pub fn overfiec(&mut self) -> OVERFIEC_W { OVERFIEC_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxstalldec(&mut self) -> RXSTALLDEC_W<6> { + pub fn rxstalldec(&mut self) -> RXSTALLDEC_W { RXSTALLDEC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Disable"] #[inline(always)] #[must_use] - pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W<7> { + pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W { SHORTPACKETIEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Disable"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Disable"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Disable"] #[inline(always)] #[must_use] - pub fn pdishdmac(&mut self) -> PDISHDMAC_W<16> { + pub fn pdishdmac(&mut self) -> PDISHDMAC_W { PDISHDMAC_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Disable"] #[inline(always)] #[must_use] - pub fn pfreezec(&mut self) -> PFREEZEC_W<17> { + pub fn pfreezec(&mut self) -> PFREEZEC_W { PFREEZEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipidr_intrpt_mode](index.html) module"] +#[doc = "Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIDR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIDR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipidr_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipidr_intrpt_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIDR_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_iso_mode.rs index d3adb012..41784438 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipidr_iso_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIDR_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINEC` writer - Received IN Data Interrupt Disable"] -pub type RXINEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type RXINEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTEC` writer - Transmitted OUT Data Interrupt Disable"] -pub type TXOUTEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type TXOUTEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIEC` writer - Underflow Interrupt Disable"] -pub type UNDERFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type UNDERFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERREC` writer - Pipe Error Interrupt Disable"] -pub type PERREC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type PERREC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDEC` writer - NAKed Interrupt Disable"] -pub type NAKEDEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type NAKEDEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIEC` writer - Overflow Interrupt Disable"] -pub type OVERFIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type OVERFIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERREC` writer - CRC Error Interrupt Disable"] -pub type CRCERREC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type CRCERREC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIEC` writer - Short Packet Interrupt Disable"] -pub type SHORTPACKETIEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type SHORTPACKETIEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKEC` writer - Number of Busy Banks Disable"] -pub type NBUSYBKEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type NBUSYBKEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIFOCONC` writer - FIFO Control Disable"] -pub type FIFOCONC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type FIFOCONC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAC` writer - Pipe Interrupts Disable HDMA Request Disable"] -pub type PDISHDMAC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type PDISHDMAC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZEC` writer - Pipe Freeze Disable"] -pub type PFREEZEC_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIDR_ISO_MODE_SPEC, O>; +pub type PFREEZEC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn rxinec(&mut self) -> RXINEC_W<0> { + pub fn rxinec(&mut self) -> RXINEC_W { RXINEC_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Disable"] #[inline(always)] #[must_use] - pub fn txoutec(&mut self) -> TXOUTEC_W<1> { + pub fn txoutec(&mut self) -> TXOUTEC_W { TXOUTEC_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn underfiec(&mut self) -> UNDERFIEC_W<2> { + pub fn underfiec(&mut self) -> UNDERFIEC_W { UNDERFIEC_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn perrec(&mut self) -> PERREC_W<3> { + pub fn perrec(&mut self) -> PERREC_W { PERREC_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Disable"] #[inline(always)] #[must_use] - pub fn nakedec(&mut self) -> NAKEDEC_W<4> { + pub fn nakedec(&mut self) -> NAKEDEC_W { NAKEDEC_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Disable"] #[inline(always)] #[must_use] - pub fn overfiec(&mut self) -> OVERFIEC_W<5> { + pub fn overfiec(&mut self) -> OVERFIEC_W { OVERFIEC_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Disable"] #[inline(always)] #[must_use] - pub fn crcerrec(&mut self) -> CRCERREC_W<6> { + pub fn crcerrec(&mut self) -> CRCERREC_W { CRCERREC_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Disable"] #[inline(always)] #[must_use] - pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W<7> { + pub fn shortpacketiec(&mut self) -> SHORTPACKETIEC_W { SHORTPACKETIEC_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Disable"] #[inline(always)] #[must_use] - pub fn nbusybkec(&mut self) -> NBUSYBKEC_W<12> { + pub fn nbusybkec(&mut self) -> NBUSYBKEC_W { NBUSYBKEC_W::new(self) } #[doc = "Bit 14 - FIFO Control Disable"] #[inline(always)] #[must_use] - pub fn fifoconc(&mut self) -> FIFOCONC_W<14> { + pub fn fifoconc(&mut self) -> FIFOCONC_W { FIFOCONC_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Disable"] #[inline(always)] #[must_use] - pub fn pdishdmac(&mut self) -> PDISHDMAC_W<16> { + pub fn pdishdmac(&mut self) -> PDISHDMAC_W { PDISHDMAC_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Disable"] #[inline(always)] #[must_use] - pub fn pfreezec(&mut self) -> PFREEZEC_W<17> { + pub fn pfreezec(&mut self) -> PFREEZEC_W { PFREEZEC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipidr_iso_mode](index.html) module"] +#[doc = "Host Pipe Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipidr_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIDR_ISO_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIDR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipidr_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipidr_iso_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIDR_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_blk_mode.rs index 51ddac39..a15728ae 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_blk_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIER_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINES` writer - Received IN Data Interrupt Enable"] -pub type RXINES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type RXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTES` writer - Transmitted OUT Data Interrupt Enable"] -pub type TXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type TXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPES` writer - Transmitted SETUP Interrupt Enable"] -pub type TXSTPES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type TXSTPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRES` writer - Pipe Error Interrupt Enable"] -pub type PERRES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type PERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDES` writer - NAKed Interrupt Enable"] -pub type NAKEDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type NAKEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIES` writer - Overflow Interrupt Enable"] -pub type OVERFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type OVERFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDES` writer - Received STALLed Interrupt Enable"] -pub type RXSTALLDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type RXSTALLDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type SHORTPACKETIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAS` writer - Pipe Interrupts Disable HDMA Request Enable"] -pub type PDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type PDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZES` writer - Pipe Freeze Enable"] -pub type PFREEZES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type PFREEZES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_BLK_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxines(&mut self) -> RXINES_W<0> { + pub fn rxines(&mut self) -> RXINES_W { RXINES_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txoutes(&mut self) -> TXOUTES_W<1> { + pub fn txoutes(&mut self) -> TXOUTES_W { TXOUTES_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txstpes(&mut self) -> TXSTPES_W<2> { + pub fn txstpes(&mut self) -> TXSTPES_W { TXSTPES_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn perres(&mut self) -> PERRES_W<3> { + pub fn perres(&mut self) -> PERRES_W { PERRES_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakedes(&mut self) -> NAKEDES_W<4> { + pub fn nakedes(&mut self) -> NAKEDES_W { NAKEDES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfies(&mut self) -> OVERFIES_W<5> { + pub fn overfies(&mut self) -> OVERFIES_W { OVERFIES_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxstalldes(&mut self) -> RXSTALLDES_W<6> { + pub fn rxstalldes(&mut self) -> RXSTALLDES_W { RXSTALLDES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W<7> { + pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W { SHORTPACKETIES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn pdishdmas(&mut self) -> PDISHDMAS_W<16> { + pub fn pdishdmas(&mut self) -> PDISHDMAS_W { PDISHDMAS_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Enable"] #[inline(always)] #[must_use] - pub fn pfreezes(&mut self) -> PFREEZES_W<17> { + pub fn pfreezes(&mut self) -> PFREEZES_W { PFREEZES_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipier_blk_mode](index.html) module"] +#[doc = "Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIER_BLK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIER_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipier_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipier_blk_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIER_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_ctrl_mode.rs index 01ef40fe..f66fb745 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_ctrl_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIER_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINES` writer - Received IN Data Interrupt Enable"] -pub type RXINES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type RXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTES` writer - Transmitted OUT Data Interrupt Enable"] -pub type TXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type TXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPES` writer - Transmitted SETUP Interrupt Enable"] -pub type TXSTPES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type TXSTPES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRES` writer - Pipe Error Interrupt Enable"] -pub type PERRES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type PERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDES` writer - NAKed Interrupt Enable"] -pub type NAKEDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type NAKEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIES` writer - Overflow Interrupt Enable"] -pub type OVERFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type OVERFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDES` writer - Received STALLed Interrupt Enable"] -pub type RXSTALLDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type RXSTALLDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAS` writer - Pipe Interrupts Disable HDMA Request Enable"] -pub type PDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type PDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZES` writer - Pipe Freeze Enable"] -pub type PFREEZES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type PFREEZES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_CTRL_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxines(&mut self) -> RXINES_W<0> { + pub fn rxines(&mut self) -> RXINES_W { RXINES_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txoutes(&mut self) -> TXOUTES_W<1> { + pub fn txoutes(&mut self) -> TXOUTES_W { TXOUTES_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txstpes(&mut self) -> TXSTPES_W<2> { + pub fn txstpes(&mut self) -> TXSTPES_W { TXSTPES_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn perres(&mut self) -> PERRES_W<3> { + pub fn perres(&mut self) -> PERRES_W { PERRES_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakedes(&mut self) -> NAKEDES_W<4> { + pub fn nakedes(&mut self) -> NAKEDES_W { NAKEDES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfies(&mut self) -> OVERFIES_W<5> { + pub fn overfies(&mut self) -> OVERFIES_W { OVERFIES_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxstalldes(&mut self) -> RXSTALLDES_W<6> { + pub fn rxstalldes(&mut self) -> RXSTALLDES_W { RXSTALLDES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W<7> { + pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W { SHORTPACKETIES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn pdishdmas(&mut self) -> PDISHDMAS_W<16> { + pub fn pdishdmas(&mut self) -> PDISHDMAS_W { PDISHDMAS_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Enable"] #[inline(always)] #[must_use] - pub fn pfreezes(&mut self) -> PFREEZES_W<17> { + pub fn pfreezes(&mut self) -> PFREEZES_W { PFREEZES_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipier_ctrl_mode](index.html) module"] +#[doc = "Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIER_CTRL_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIER_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipier_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipier_ctrl_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIER_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_intrpt_mode.rs index 96687344..aa001970 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_intrpt_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIER_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINES` writer - Received IN Data Interrupt Enable"] -pub type RXINES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type RXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTES` writer - Transmitted OUT Data Interrupt Enable"] -pub type TXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type TXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIES` writer - Underflow Interrupt Enable"] -pub type UNDERFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type UNDERFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRES` writer - Pipe Error Interrupt Enable"] -pub type PERRES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type PERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDES` writer - NAKed Interrupt Enable"] -pub type NAKEDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type NAKEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIES` writer - Overflow Interrupt Enable"] -pub type OVERFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type OVERFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDES` writer - Received STALLed Interrupt Enable"] -pub type RXSTALLDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type RXSTALLDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAS` writer - Pipe Interrupts Disable HDMA Request Enable"] -pub type PDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type PDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZES` writer - Pipe Freeze Enable"] -pub type PFREEZES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type PFREEZES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_INTRPT_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxines(&mut self) -> RXINES_W<0> { + pub fn rxines(&mut self) -> RXINES_W { RXINES_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txoutes(&mut self) -> TXOUTES_W<1> { + pub fn txoutes(&mut self) -> TXOUTES_W { TXOUTES_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn underfies(&mut self) -> UNDERFIES_W<2> { + pub fn underfies(&mut self) -> UNDERFIES_W { UNDERFIES_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn perres(&mut self) -> PERRES_W<3> { + pub fn perres(&mut self) -> PERRES_W { PERRES_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakedes(&mut self) -> NAKEDES_W<4> { + pub fn nakedes(&mut self) -> NAKEDES_W { NAKEDES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfies(&mut self) -> OVERFIES_W<5> { + pub fn overfies(&mut self) -> OVERFIES_W { OVERFIES_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxstalldes(&mut self) -> RXSTALLDES_W<6> { + pub fn rxstalldes(&mut self) -> RXSTALLDES_W { RXSTALLDES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W<7> { + pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W { SHORTPACKETIES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn pdishdmas(&mut self) -> PDISHDMAS_W<16> { + pub fn pdishdmas(&mut self) -> PDISHDMAS_W { PDISHDMAS_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Enable"] #[inline(always)] #[must_use] - pub fn pfreezes(&mut self) -> PFREEZES_W<17> { + pub fn pfreezes(&mut self) -> PFREEZES_W { PFREEZES_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipier_intrpt_mode](index.html) module"] +#[doc = "Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIER_INTRPT_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIER_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipier_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipier_intrpt_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIER_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_iso_mode.rs index 1d836639..8b251c8b 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipier_iso_mode.rs @@ -1,136 +1,116 @@ #[doc = "Register `HSTPIPIER_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINES` writer - Received IN Data Interrupt Enable"] -pub type RXINES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type RXINES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTES` writer - Transmitted OUT Data Interrupt Enable"] -pub type TXOUTES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type TXOUTES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIES` writer - Underflow Interrupt Enable"] -pub type UNDERFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type UNDERFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRES` writer - Pipe Error Interrupt Enable"] -pub type PERRES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type PERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDES` writer - NAKed Interrupt Enable"] -pub type NAKEDES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type NAKEDES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIES` writer - Overflow Interrupt Enable"] -pub type OVERFIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type OVERFIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERRES` writer - CRC Error Interrupt Enable"] -pub type CRCERRES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type CRCERRES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIES` writer - Short Packet Interrupt Enable"] -pub type SHORTPACKETIES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type SHORTPACKETIES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKES` writer - Number of Busy Banks Enable"] -pub type NBUSYBKES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type NBUSYBKES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PDISHDMAS` writer - Pipe Interrupts Disable HDMA Request Enable"] -pub type PDISHDMAS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type PDISHDMAS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PFREEZES` writer - Pipe Freeze Enable"] -pub type PFREEZES_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type PFREEZES_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RSTDTS` writer - Reset Data Toggle Enable"] -pub type RSTDTS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIER_ISO_MODE_SPEC, O>; +pub type RSTDTS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn rxines(&mut self) -> RXINES_W<0> { + pub fn rxines(&mut self) -> RXINES_W { RXINES_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Enable"] #[inline(always)] #[must_use] - pub fn txoutes(&mut self) -> TXOUTES_W<1> { + pub fn txoutes(&mut self) -> TXOUTES_W { TXOUTES_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn underfies(&mut self) -> UNDERFIES_W<2> { + pub fn underfies(&mut self) -> UNDERFIES_W { UNDERFIES_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn perres(&mut self) -> PERRES_W<3> { + pub fn perres(&mut self) -> PERRES_W { PERRES_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Enable"] #[inline(always)] #[must_use] - pub fn nakedes(&mut self) -> NAKEDES_W<4> { + pub fn nakedes(&mut self) -> NAKEDES_W { NAKEDES_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Enable"] #[inline(always)] #[must_use] - pub fn overfies(&mut self) -> OVERFIES_W<5> { + pub fn overfies(&mut self) -> OVERFIES_W { OVERFIES_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Enable"] #[inline(always)] #[must_use] - pub fn crcerres(&mut self) -> CRCERRES_W<6> { + pub fn crcerres(&mut self) -> CRCERRES_W { CRCERRES_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Enable"] #[inline(always)] #[must_use] - pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W<7> { + pub fn shortpacketies(&mut self) -> SHORTPACKETIES_W { SHORTPACKETIES_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Enable"] #[inline(always)] #[must_use] - pub fn nbusybkes(&mut self) -> NBUSYBKES_W<12> { + pub fn nbusybkes(&mut self) -> NBUSYBKES_W { NBUSYBKES_W::new(self) } #[doc = "Bit 16 - Pipe Interrupts Disable HDMA Request Enable"] #[inline(always)] #[must_use] - pub fn pdishdmas(&mut self) -> PDISHDMAS_W<16> { + pub fn pdishdmas(&mut self) -> PDISHDMAS_W { PDISHDMAS_W::new(self) } #[doc = "Bit 17 - Pipe Freeze Enable"] #[inline(always)] #[must_use] - pub fn pfreezes(&mut self) -> PFREEZES_W<17> { + pub fn pfreezes(&mut self) -> PFREEZES_W { PFREEZES_W::new(self) } #[doc = "Bit 18 - Reset Data Toggle Enable"] #[inline(always)] #[must_use] - pub fn rstdts(&mut self) -> RSTDTS_W<18> { + pub fn rstdts(&mut self) -> RSTDTS_W { RSTDTS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipier_iso_mode](index.html) module"] +#[doc = "Host Pipe Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipier_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIER_ISO_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIER_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipier_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipier_iso_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIER_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_blk_mode.rs index 5422d524..853d91e8 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_blk_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `HSTPIPIFR_BLK_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIS` writer - Received IN Data Interrupt Set"] -pub type RXINIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type RXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIS` writer - Transmitted OUT Data Interrupt Set"] -pub type TXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type TXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPIS` writer - Transmitted SETUP Interrupt Set"] -pub type TXSTPIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type TXSTPIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRIS` writer - Pipe Error Interrupt Set"] -pub type PERRIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type PERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIS` writer - NAKed Interrupt Set"] -pub type NAKEDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type NAKEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDIS` writer - Received STALLed Interrupt Set"] -pub type RXSTALLDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type RXSTALLDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type SHORTPACKETIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_BLK_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxinis(&mut self) -> RXINIS_W<0> { + pub fn rxinis(&mut self) -> RXINIS_W { RXINIS_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txoutis(&mut self) -> TXOUTIS_W<1> { + pub fn txoutis(&mut self) -> TXOUTIS_W { TXOUTIS_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Set"] #[inline(always)] #[must_use] - pub fn txstpis(&mut self) -> TXSTPIS_W<2> { + pub fn txstpis(&mut self) -> TXSTPIS_W { TXSTPIS_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn perris(&mut self) -> PERRIS_W<3> { + pub fn perris(&mut self) -> PERRIS_W { PERRIS_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakedis(&mut self) -> NAKEDIS_W<4> { + pub fn nakedis(&mut self) -> NAKEDIS_W { NAKEDIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxstalldis(&mut self) -> RXSTALLDIS_W<6> { + pub fn rxstalldis(&mut self) -> RXSTALLDIS_W { RXSTALLDIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W<7> { + pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W { SHORTPACKETIS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipifr_blk_mode](index.html) module"] +#[doc = "Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_blk_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIFR_BLK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIFR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipifr_blk_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipifr_blk_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIFR_BLK_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_ctrl_mode.rs index 17736ef0..442b1d99 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_ctrl_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `HSTPIPIFR_CTRL_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIS` writer - Received IN Data Interrupt Set"] -pub type RXINIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type RXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIS` writer - Transmitted OUT Data Interrupt Set"] -pub type TXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type TXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXSTPIS` writer - Transmitted SETUP Interrupt Set"] -pub type TXSTPIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type TXSTPIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRIS` writer - Pipe Error Interrupt Set"] -pub type PERRIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type PERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIS` writer - NAKed Interrupt Set"] -pub type NAKEDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type NAKEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDIS` writer - Received STALLed Interrupt Set"] -pub type RXSTALLDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type RXSTALLDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type SHORTPACKETIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_CTRL_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxinis(&mut self) -> RXINIS_W<0> { + pub fn rxinis(&mut self) -> RXINIS_W { RXINIS_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txoutis(&mut self) -> TXOUTIS_W<1> { + pub fn txoutis(&mut self) -> TXOUTIS_W { TXOUTIS_W::new(self) } #[doc = "Bit 2 - Transmitted SETUP Interrupt Set"] #[inline(always)] #[must_use] - pub fn txstpis(&mut self) -> TXSTPIS_W<2> { + pub fn txstpis(&mut self) -> TXSTPIS_W { TXSTPIS_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn perris(&mut self) -> PERRIS_W<3> { + pub fn perris(&mut self) -> PERRIS_W { PERRIS_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakedis(&mut self) -> NAKEDIS_W<4> { + pub fn nakedis(&mut self) -> NAKEDIS_W { NAKEDIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxstalldis(&mut self) -> RXSTALLDIS_W<6> { + pub fn rxstalldis(&mut self) -> RXSTALLDIS_W { RXSTALLDIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W<7> { + pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W { SHORTPACKETIS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipifr_ctrl_mode](index.html) module"] +#[doc = "Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_ctrl_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIFR_CTRL_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIFR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipifr_ctrl_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipifr_ctrl_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIFR_CTRL_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_intrpt_mode.rs index d6392350..b416b17e 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_intrpt_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `HSTPIPIFR_INTRPT_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIS` writer - Received IN Data Interrupt Set"] -pub type RXINIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type RXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIS` writer - Transmitted OUT Data Interrupt Set"] -pub type TXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type TXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIS` writer - Underflow Interrupt Set"] -pub type UNDERFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type UNDERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRIS` writer - Pipe Error Interrupt Set"] -pub type PERRIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type PERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIS` writer - NAKed Interrupt Set"] -pub type NAKEDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type NAKEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RXSTALLDIS` writer - Received STALLed Interrupt Set"] -pub type RXSTALLDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type RXSTALLDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type SHORTPACKETIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_INTRPT_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxinis(&mut self) -> RXINIS_W<0> { + pub fn rxinis(&mut self) -> RXINIS_W { RXINIS_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txoutis(&mut self) -> TXOUTIS_W<1> { + pub fn txoutis(&mut self) -> TXOUTIS_W { TXOUTIS_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn underfis(&mut self) -> UNDERFIS_W<2> { + pub fn underfis(&mut self) -> UNDERFIS_W { UNDERFIS_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn perris(&mut self) -> PERRIS_W<3> { + pub fn perris(&mut self) -> PERRIS_W { PERRIS_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakedis(&mut self) -> NAKEDIS_W<4> { + pub fn nakedis(&mut self) -> NAKEDIS_W { NAKEDIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - Received STALLed Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxstalldis(&mut self) -> RXSTALLDIS_W<6> { + pub fn rxstalldis(&mut self) -> RXSTALLDIS_W { RXSTALLDIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W<7> { + pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W { SHORTPACKETIS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipifr_intrpt_mode](index.html) module"] +#[doc = "Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_intrpt_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIFR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIFR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipifr_intrpt_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipifr_intrpt_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIFR_INTRPT_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_iso_mode.rs index 22cee81c..9db071b3 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipifr_iso_mode.rs @@ -1,112 +1,92 @@ #[doc = "Register `HSTPIPIFR_ISO_MODE[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RXINIS` writer - Received IN Data Interrupt Set"] -pub type RXINIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type RXINIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `TXOUTIS` writer - Transmitted OUT Data Interrupt Set"] -pub type TXOUTIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type TXOUTIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UNDERFIS` writer - Underflow Interrupt Set"] -pub type UNDERFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type UNDERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `PERRIS` writer - Pipe Error Interrupt Set"] -pub type PERRIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type PERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NAKEDIS` writer - NAKed Interrupt Set"] -pub type NAKEDIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type NAKEDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `OVERFIS` writer - Overflow Interrupt Set"] -pub type OVERFIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type OVERFIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CRCERRIS` writer - CRC Error Interrupt Set"] -pub type CRCERRIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type CRCERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SHORTPACKETIS` writer - Short Packet Interrupt Set"] -pub type SHORTPACKETIS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type SHORTPACKETIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NBUSYBKS` writer - Number of Busy Banks Set"] -pub type NBUSYBKS_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPIFR_ISO_MODE_SPEC, O>; +pub type NBUSYBKS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - Received IN Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn rxinis(&mut self) -> RXINIS_W<0> { + pub fn rxinis(&mut self) -> RXINIS_W { RXINIS_W::new(self) } #[doc = "Bit 1 - Transmitted OUT Data Interrupt Set"] #[inline(always)] #[must_use] - pub fn txoutis(&mut self) -> TXOUTIS_W<1> { + pub fn txoutis(&mut self) -> TXOUTIS_W { TXOUTIS_W::new(self) } #[doc = "Bit 2 - Underflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn underfis(&mut self) -> UNDERFIS_W<2> { + pub fn underfis(&mut self) -> UNDERFIS_W { UNDERFIS_W::new(self) } #[doc = "Bit 3 - Pipe Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn perris(&mut self) -> PERRIS_W<3> { + pub fn perris(&mut self) -> PERRIS_W { PERRIS_W::new(self) } #[doc = "Bit 4 - NAKed Interrupt Set"] #[inline(always)] #[must_use] - pub fn nakedis(&mut self) -> NAKEDIS_W<4> { + pub fn nakedis(&mut self) -> NAKEDIS_W { NAKEDIS_W::new(self) } #[doc = "Bit 5 - Overflow Interrupt Set"] #[inline(always)] #[must_use] - pub fn overfis(&mut self) -> OVERFIS_W<5> { + pub fn overfis(&mut self) -> OVERFIS_W { OVERFIS_W::new(self) } #[doc = "Bit 6 - CRC Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn crcerris(&mut self) -> CRCERRIS_W<6> { + pub fn crcerris(&mut self) -> CRCERRIS_W { CRCERRIS_W::new(self) } #[doc = "Bit 7 - Short Packet Interrupt Set"] #[inline(always)] #[must_use] - pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W<7> { + pub fn shortpacketis(&mut self) -> SHORTPACKETIS_W { SHORTPACKETIS_W::new(self) } #[doc = "Bit 12 - Number of Busy Banks Set"] #[inline(always)] #[must_use] - pub fn nbusybks(&mut self) -> NBUSYBKS_W<12> { + pub fn nbusybks(&mut self) -> NBUSYBKS_W { NBUSYBKS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipifr_iso_mode](index.html) module"] +#[doc = "Host Pipe Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipifr_iso_mode::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIFR_ISO_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIFR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [hstpipifr_iso_mode::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`hstpipifr_iso_mode::W`](W) writer structure"] impl crate::Writable for HSTPIPIFR_ISO_MODE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_blk_mode.rs index 487c498b..42fabc63 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_blk_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPIMR_BLK_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINE` reader - Received IN Data Interrupt Enable"] pub type RXINE_R = crate::BitReader; #[doc = "Field `TXOUTE` reader - Transmitted OUT Data Interrupt Enable"] @@ -106,15 +93,13 @@ impl R { RSTDT_R::new(((self.bits >> 18) & 1) != 0) } } -#[doc = "Host Pipe Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipimr_blk_mode](index.html) module"] +#[doc = "Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_blk_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIMR_BLK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIMR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipimr_blk_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPIMR_BLK_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipimr_blk_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPIMR_BLK_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPIMR_BLK_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPIMR_BLK_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_ctrl_mode.rs index 5690710a..7c7c6faa 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_ctrl_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPIMR_CTRL_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINE` reader - Received IN Data Interrupt Enable"] pub type RXINE_R = crate::BitReader; #[doc = "Field `TXOUTE` reader - Transmitted OUT Data Interrupt Enable"] @@ -106,15 +93,13 @@ impl R { RSTDT_R::new(((self.bits >> 18) & 1) != 0) } } -#[doc = "Host Pipe Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipimr_ctrl_mode](index.html) module"] +#[doc = "Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_ctrl_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIMR_CTRL_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIMR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipimr_ctrl_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPIMR_CTRL_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipimr_ctrl_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPIMR_CTRL_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPIMR_CTRL_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPIMR_CTRL_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_intrpt_mode.rs index 2352ecf8..de5fe1f1 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_intrpt_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPIMR_INTRPT_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINE` reader - Received IN Data Interrupt Enable"] pub type RXINE_R = crate::BitReader; #[doc = "Field `TXOUTE` reader - Transmitted OUT Data Interrupt Enable"] @@ -106,15 +93,13 @@ impl R { RSTDT_R::new(((self.bits >> 18) & 1) != 0) } } -#[doc = "Host Pipe Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipimr_intrpt_mode](index.html) module"] +#[doc = "Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_intrpt_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIMR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIMR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipimr_intrpt_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPIMR_INTRPT_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipimr_intrpt_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPIMR_INTRPT_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPIMR_INTRPT_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPIMR_INTRPT_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_iso_mode.rs index 38a32756..ecca6067 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipimr_iso_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPIMR_ISO_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINE` reader - Received IN Data Interrupt Enable"] pub type RXINE_R = crate::BitReader; #[doc = "Field `TXOUTE` reader - Transmitted OUT Data Interrupt Enable"] @@ -106,15 +93,13 @@ impl R { RSTDT_R::new(((self.bits >> 18) & 1) != 0) } } -#[doc = "Host Pipe Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipimr_iso_mode](index.html) module"] +#[doc = "Host Pipe Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipimr_iso_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPIMR_ISO_MODE_SPEC; impl crate::RegisterSpec for HSTPIPIMR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipimr_iso_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPIMR_ISO_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipimr_iso_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPIMR_ISO_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPIMR_ISO_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPIMR_ISO_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipinrq.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipinrq.rs index b8c9dc99..5b261428 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipinrq.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipinrq.rs @@ -1,47 +1,15 @@ #[doc = "Register `HSTPIPINRQ[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTPIPINRQ[%s]` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `INRQ` reader - IN Request Number before Freeze"] pub type INRQ_R = crate::FieldReader; #[doc = "Field `INRQ` writer - IN Request Number before Freeze"] -pub type INRQ_W<'a, const O: u8> = crate::FieldWriter<'a, HSTPIPINRQ_SPEC, 8, O>; +pub type INRQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>; #[doc = "Field `INMODE` reader - IN Request Mode"] pub type INMODE_R = crate::BitReader; #[doc = "Field `INMODE` writer - IN Request Mode"] -pub type INMODE_W<'a, const O: u8> = crate::BitWriter<'a, HSTPIPINRQ_SPEC, O>; +pub type INMODE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:7 - IN Request Number before Freeze"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:7 - IN Request Number before Freeze"] #[inline(always)] #[must_use] - pub fn inrq(&mut self) -> INRQ_W<0> { + pub fn inrq(&mut self) -> INRQ_W { INRQ_W::new(self) } #[doc = "Bit 8 - IN Request Mode"] #[inline(always)] #[must_use] - pub fn inmode(&mut self) -> INMODE_W<8> { + pub fn inmode(&mut self) -> INMODE_W { INMODE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host Pipe IN Request Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipinrq](index.html) module"] +#[doc = "Host Pipe IN Request Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipinrq::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstpipinrq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPINRQ_SPEC; impl crate::RegisterSpec for HSTPIPINRQ_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipinrq::R](R) reader structure"] -impl crate::Readable for HSTPIPINRQ_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstpipinrq::W](W) writer structure"] +#[doc = "`read()` method returns [`hstpipinrq::R`](R) reader structure"] +impl crate::Readable for HSTPIPINRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstpipinrq::W`](W) writer structure"] impl crate::Writable for HSTPIPINRQ_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_blk_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_blk_mode.rs index 49b75d8d..06effb9d 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_blk_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_blk_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPISR_BLK_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINI` reader - Received IN Data Interrupt"] pub type RXINI_R = crate::BitReader; #[doc = "Field `TXOUTI` reader - Transmitted OUT Data Interrupt"] @@ -59,12 +46,12 @@ impl DTSEQ_R { _ => None, } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 @@ -106,22 +93,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -160,17 +147,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -254,15 +241,13 @@ impl R { PBYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Host Pipe Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipisr_blk_mode](index.html) module"] +#[doc = "Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_blk_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPISR_BLK_MODE_SPEC; impl crate::RegisterSpec for HSTPIPISR_BLK_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipisr_blk_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPISR_BLK_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipisr_blk_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPISR_BLK_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPISR_BLK_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPISR_BLK_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_ctrl_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_ctrl_mode.rs index 4013e73c..e5408bc6 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_ctrl_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_ctrl_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPISR_CTRL_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINI` reader - Received IN Data Interrupt"] pub type RXINI_R = crate::BitReader; #[doc = "Field `TXOUTI` reader - Transmitted OUT Data Interrupt"] @@ -59,12 +46,12 @@ impl DTSEQ_R { _ => None, } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 @@ -106,22 +93,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -160,17 +147,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -254,15 +241,13 @@ impl R { PBYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Host Pipe Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipisr_ctrl_mode](index.html) module"] +#[doc = "Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_ctrl_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPISR_CTRL_MODE_SPEC; impl crate::RegisterSpec for HSTPIPISR_CTRL_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipisr_ctrl_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPISR_CTRL_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipisr_ctrl_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPISR_CTRL_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPISR_CTRL_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPISR_CTRL_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_intrpt_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_intrpt_mode.rs index 4300954d..f69d8e93 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_intrpt_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_intrpt_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPISR_INTRPT_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINI` reader - Received IN Data Interrupt"] pub type RXINI_R = crate::BitReader; #[doc = "Field `TXOUTI` reader - Transmitted OUT Data Interrupt"] @@ -59,12 +46,12 @@ impl DTSEQ_R { _ => None, } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 @@ -106,22 +93,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -160,17 +147,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -254,15 +241,13 @@ impl R { PBYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Host Pipe Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipisr_intrpt_mode](index.html) module"] +#[doc = "Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_intrpt_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPISR_INTRPT_MODE_SPEC; impl crate::RegisterSpec for HSTPIPISR_INTRPT_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipisr_intrpt_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPISR_INTRPT_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipisr_intrpt_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPISR_INTRPT_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPISR_INTRPT_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPISR_INTRPT_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_iso_mode.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_iso_mode.rs index a551fa0b..ac370a63 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_iso_mode.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/hstpipisr_iso_mode.rs @@ -1,18 +1,5 @@ #[doc = "Register `HSTPIPISR_ISO_MODE[%s]` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RXINI` reader - Received IN Data Interrupt"] pub type RXINI_R = crate::BitReader; #[doc = "Field `TXOUTI` reader - Transmitted OUT Data Interrupt"] @@ -59,12 +46,12 @@ impl DTSEQ_R { _ => None, } } - #[doc = "Checks if the value of the field is `DATA0`"] + #[doc = "Data0 toggle sequence"] #[inline(always)] pub fn is_data0(&self) -> bool { *self == DTSEQSELECT_A::DATA0 } - #[doc = "Checks if the value of the field is `DATA1`"] + #[doc = "Data1 toggle sequence"] #[inline(always)] pub fn is_data1(&self) -> bool { *self == DTSEQSELECT_A::DATA1 @@ -106,22 +93,22 @@ impl NBUSYBK_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `_0_BUSY`"] + #[doc = "0 busy bank (all banks free)"] #[inline(always)] pub fn is_0_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_0_BUSY } - #[doc = "Checks if the value of the field is `_1_BUSY`"] + #[doc = "1 busy bank"] #[inline(always)] pub fn is_1_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_1_BUSY } - #[doc = "Checks if the value of the field is `_2_BUSY`"] + #[doc = "2 busy banks"] #[inline(always)] pub fn is_2_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_2_BUSY } - #[doc = "Checks if the value of the field is `_3_BUSY`"] + #[doc = "3 busy banks"] #[inline(always)] pub fn is_3_busy(&self) -> bool { *self == NBUSYBKSELECT_A::_3_BUSY @@ -160,17 +147,17 @@ impl CURRBK_R { _ => None, } } - #[doc = "Checks if the value of the field is `BANK0`"] + #[doc = "Current bank is bank0"] #[inline(always)] pub fn is_bank0(&self) -> bool { *self == CURRBKSELECT_A::BANK0 } - #[doc = "Checks if the value of the field is `BANK1`"] + #[doc = "Current bank is bank1"] #[inline(always)] pub fn is_bank1(&self) -> bool { *self == CURRBKSELECT_A::BANK1 } - #[doc = "Checks if the value of the field is `BANK2`"] + #[doc = "Current bank is bank2"] #[inline(always)] pub fn is_bank2(&self) -> bool { *self == CURRBKSELECT_A::BANK2 @@ -254,15 +241,13 @@ impl R { PBYCT_R::new(((self.bits >> 20) & 0x07ff) as u16) } } -#[doc = "Host Pipe Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstpipisr_iso_mode](index.html) module"] +#[doc = "Host Pipe Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstpipisr_iso_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTPIPISR_ISO_MODE_SPEC; impl crate::RegisterSpec for HSTPIPISR_ISO_MODE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstpipisr_iso_mode::R](R) reader structure"] -impl crate::Readable for HSTPIPISR_ISO_MODE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`hstpipisr_iso_mode::R`](R) reader structure"] +impl crate::Readable for HSTPIPISR_ISO_MODE_SPEC {} #[doc = "`reset()` method sets HSTPIPISR_ISO_MODE[%s] to value 0"] impl crate::Resettable for HSTPIPISR_ISO_MODE_SPEC { diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/scr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/scr.rs index 7cf8ecbf..9415ce1f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/scr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/scr.rs @@ -1,48 +1,28 @@ #[doc = "Register `SCR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDERRIC` writer - Remote Device Connection Error Interrupt Clear"] -pub type RDERRIC_W<'a, const O: u8> = crate::BitWriter<'a, SCR_SPEC, O>; +pub type RDERRIC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 4 - Remote Device Connection Error Interrupt Clear"] #[inline(always)] #[must_use] - pub fn rderric(&mut self) -> RDERRIC_W<4> { + pub fn rderric(&mut self) -> RDERRIC_W { RDERRIC_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "General Status Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scr](index.html) module"] +#[doc = "General Status Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SCR_SPEC; impl crate::RegisterSpec for SCR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [scr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] impl crate::Writable for SCR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/sfr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/sfr.rs index f7c6ca31..88eb0e1e 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/sfr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/sfr.rs @@ -1,56 +1,36 @@ #[doc = "Register `SFR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RDERRIS` writer - Remote Device Connection Error Interrupt Set"] -pub type RDERRIS_W<'a, const O: u8> = crate::BitWriter<'a, SFR_SPEC, O>; +pub type RDERRIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `VBUSRQS` writer - VBUS Request Set"] -pub type VBUSRQS_W<'a, const O: u8> = crate::BitWriter<'a, SFR_SPEC, O>; +pub type VBUSRQS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 4 - Remote Device Connection Error Interrupt Set"] #[inline(always)] #[must_use] - pub fn rderris(&mut self) -> RDERRIS_W<4> { + pub fn rderris(&mut self) -> RDERRIS_W { RDERRIS_W::new(self) } #[doc = "Bit 9 - VBUS Request Set"] #[inline(always)] #[must_use] - pub fn vbusrqs(&mut self) -> VBUSRQS_W<9> { + pub fn vbusrqs(&mut self) -> VBUSRQS_W { VBUSRQS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "General Status Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sfr](index.html) module"] +#[doc = "General Status Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SFR_SPEC; impl crate::RegisterSpec for SFR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [sfr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`sfr::W`](W) writer structure"] impl crate::Writable for SFR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/sr.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/sr.rs index 6253d1ea..bd91e266 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `RDERRI` reader - Remote Device Connection Error Interrupt (Host mode only)"] pub type RDERRI_R = crate::BitReader; #[doc = "Field `SPEED` reader - Speed Status (Device mode only)"] @@ -48,17 +35,17 @@ impl SPEED_R { _ => None, } } - #[doc = "Checks if the value of the field is `FULL_SPEED`"] + #[doc = "Full-Speed mode"] #[inline(always)] pub fn is_full_speed(&self) -> bool { *self == SPEEDSELECT_A::FULL_SPEED } - #[doc = "Checks if the value of the field is `HIGH_SPEED`"] + #[doc = "High-Speed mode"] #[inline(always)] pub fn is_high_speed(&self) -> bool { *self == SPEEDSELECT_A::HIGH_SPEED } - #[doc = "Checks if the value of the field is `LOW_SPEED`"] + #[doc = "Low-Speed mode"] #[inline(always)] pub fn is_low_speed(&self) -> bool { *self == SPEEDSELECT_A::LOW_SPEED @@ -83,15 +70,13 @@ impl R { CLKUSABLE_R::new(((self.bits >> 14) & 1) != 0) } } -#[doc = "General Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "General Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma.rs index 3189553b..37a8a35d 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma.rs @@ -10,19 +10,23 @@ pub struct USBHS_DEVDMA { #[doc = "0x0c - Device DMA Channel Status Register"] pub devdmastatus: DEVDMASTATUS, } -#[doc = "DEVDMANXTDSC (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVDMANXTDSC (rw) register accessor: Device DMA Channel Next Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmanxtdsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmanxtdsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devdmanxtdsc`] +module"] pub type DEVDMANXTDSC = crate::Reg; #[doc = "Device DMA Channel Next Descriptor Address Register"] pub mod devdmanxtdsc; -#[doc = "DEVDMAADDRESS (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVDMAADDRESS (rw) register accessor: Device DMA Channel Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmaaddress::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmaaddress::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devdmaaddress`] +module"] pub type DEVDMAADDRESS = crate::Reg; #[doc = "Device DMA Channel Address Register"] pub mod devdmaaddress; -#[doc = "DEVDMACONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVDMACONTROL (rw) register accessor: Device DMA Channel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmacontrol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmacontrol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devdmacontrol`] +module"] pub type DEVDMACONTROL = crate::Reg; #[doc = "Device DMA Channel Control Register"] pub mod devdmacontrol; -#[doc = "DEVDMASTATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "DEVDMASTATUS (rw) register accessor: Device DMA Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmastatus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmastatus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`devdmastatus`] +module"] pub type DEVDMASTATUS = crate::Reg; #[doc = "Device DMA Channel Status Register"] pub mod devdmastatus; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmaaddress.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmaaddress.rs index 1a6ce749..481f7052 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmaaddress.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmaaddress.rs @@ -1,43 +1,11 @@ #[doc = "Register `DEVDMAADDRESS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVDMAADDRESS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BUFF_ADD` reader - Buffer Address"] pub type BUFF_ADD_R = crate::FieldReader; #[doc = "Field `BUFF_ADD` writer - Buffer Address"] -pub type BUFF_ADD_W<'a, const O: u8> = crate::FieldWriter<'a, DEVDMAADDRESS_SPEC, 32, O, u32>; +pub type BUFF_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Buffer Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Buffer Address"] #[inline(always)] #[must_use] - pub fn buff_add(&mut self) -> BUFF_ADD_W<0> { + pub fn buff_add(&mut self) -> BUFF_ADD_W { BUFF_ADD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device DMA Channel Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devdmaaddress](index.html) module"] +#[doc = "Device DMA Channel Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmaaddress::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmaaddress::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVDMAADDRESS_SPEC; impl crate::RegisterSpec for DEVDMAADDRESS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devdmaaddress::R](R) reader structure"] -impl crate::Readable for DEVDMAADDRESS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [devdmaaddress::W](W) writer structure"] +#[doc = "`read()` method returns [`devdmaaddress::R`](R) reader structure"] +impl crate::Readable for DEVDMAADDRESS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devdmaaddress::W`](W) writer structure"] impl crate::Writable for DEVDMAADDRESS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmacontrol.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmacontrol.rs index 7b8fbbd3..87f34772 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmacontrol.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmacontrol.rs @@ -1,75 +1,43 @@ #[doc = "Register `DEVDMACONTROL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVDMACONTROL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHANN_ENB` reader - Channel Enable Command"] pub type CHANN_ENB_R = crate::BitReader; #[doc = "Field `CHANN_ENB` writer - Channel Enable Command"] -pub type CHANN_ENB_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type CHANN_ENB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDNXT_DSC` reader - Load Next Channel Transfer Descriptor Enable Command"] pub type LDNXT_DSC_R = crate::BitReader; #[doc = "Field `LDNXT_DSC` writer - Load Next Channel Transfer Descriptor Enable Command"] -pub type LDNXT_DSC_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type LDNXT_DSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_TR_EN` reader - End of Transfer Enable Control (OUT transfers only)"] pub type END_TR_EN_R = crate::BitReader; #[doc = "Field `END_TR_EN` writer - End of Transfer Enable Control (OUT transfers only)"] -pub type END_TR_EN_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type END_TR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_B_EN` reader - End of Buffer Enable Control"] pub type END_B_EN_R = crate::BitReader; #[doc = "Field `END_B_EN` writer - End of Buffer Enable Control"] -pub type END_B_EN_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type END_B_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_TR_IT` reader - End of Transfer Interrupt Enable"] pub type END_TR_IT_R = crate::BitReader; #[doc = "Field `END_TR_IT` writer - End of Transfer Interrupt Enable"] -pub type END_TR_IT_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type END_TR_IT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_BUFFIT` reader - End of Buffer Interrupt Enable"] pub type END_BUFFIT_R = crate::BitReader; #[doc = "Field `END_BUFFIT` writer - End of Buffer Interrupt Enable"] -pub type END_BUFFIT_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type END_BUFFIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DESC_LD_IT` reader - Descriptor Loaded Interrupt Enable"] pub type DESC_LD_IT_R = crate::BitReader; #[doc = "Field `DESC_LD_IT` writer - Descriptor Loaded Interrupt Enable"] -pub type DESC_LD_IT_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type DESC_LD_IT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BURST_LCK` reader - Burst Lock Enable"] pub type BURST_LCK_R = crate::BitReader; #[doc = "Field `BURST_LCK` writer - Burst Lock Enable"] -pub type BURST_LCK_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMACONTROL_SPEC, O>; +pub type BURST_LCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFF_LENGTH` reader - Buffer Byte Length (Write-only)"] pub type BUFF_LENGTH_R = crate::FieldReader; #[doc = "Field `BUFF_LENGTH` writer - Buffer Byte Length (Write-only)"] -pub type BUFF_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, DEVDMACONTROL_SPEC, 16, O, u16>; +pub type BUFF_LENGTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 0 - Channel Enable Command"] #[inline(always)] @@ -121,76 +89,73 @@ impl W { #[doc = "Bit 0 - Channel Enable Command"] #[inline(always)] #[must_use] - pub fn chann_enb(&mut self) -> CHANN_ENB_W<0> { + pub fn chann_enb(&mut self) -> CHANN_ENB_W { CHANN_ENB_W::new(self) } #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable Command"] #[inline(always)] #[must_use] - pub fn ldnxt_dsc(&mut self) -> LDNXT_DSC_W<1> { + pub fn ldnxt_dsc(&mut self) -> LDNXT_DSC_W { LDNXT_DSC_W::new(self) } #[doc = "Bit 2 - End of Transfer Enable Control (OUT transfers only)"] #[inline(always)] #[must_use] - pub fn end_tr_en(&mut self) -> END_TR_EN_W<2> { + pub fn end_tr_en(&mut self) -> END_TR_EN_W { END_TR_EN_W::new(self) } #[doc = "Bit 3 - End of Buffer Enable Control"] #[inline(always)] #[must_use] - pub fn end_b_en(&mut self) -> END_B_EN_W<3> { + pub fn end_b_en(&mut self) -> END_B_EN_W { END_B_EN_W::new(self) } #[doc = "Bit 4 - End of Transfer Interrupt Enable"] #[inline(always)] #[must_use] - pub fn end_tr_it(&mut self) -> END_TR_IT_W<4> { + pub fn end_tr_it(&mut self) -> END_TR_IT_W { END_TR_IT_W::new(self) } #[doc = "Bit 5 - End of Buffer Interrupt Enable"] #[inline(always)] #[must_use] - pub fn end_buffit(&mut self) -> END_BUFFIT_W<5> { + pub fn end_buffit(&mut self) -> END_BUFFIT_W { END_BUFFIT_W::new(self) } #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"] #[inline(always)] #[must_use] - pub fn desc_ld_it(&mut self) -> DESC_LD_IT_W<6> { + pub fn desc_ld_it(&mut self) -> DESC_LD_IT_W { DESC_LD_IT_W::new(self) } #[doc = "Bit 7 - Burst Lock Enable"] #[inline(always)] #[must_use] - pub fn burst_lck(&mut self) -> BURST_LCK_W<7> { + pub fn burst_lck(&mut self) -> BURST_LCK_W { BURST_LCK_W::new(self) } #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"] #[inline(always)] #[must_use] - pub fn buff_length(&mut self) -> BUFF_LENGTH_W<16> { + pub fn buff_length(&mut self) -> BUFF_LENGTH_W { BUFF_LENGTH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device DMA Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devdmacontrol](index.html) module"] +#[doc = "Device DMA Channel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmacontrol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmacontrol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVDMACONTROL_SPEC; impl crate::RegisterSpec for DEVDMACONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devdmacontrol::R](R) reader structure"] -impl crate::Readable for DEVDMACONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [devdmacontrol::W](W) writer structure"] +#[doc = "`read()` method returns [`devdmacontrol::R`](R) reader structure"] +impl crate::Readable for DEVDMACONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devdmacontrol::W`](W) writer structure"] impl crate::Writable for DEVDMACONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmanxtdsc.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmanxtdsc.rs index f78ba3b1..9a189cec 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmanxtdsc.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmanxtdsc.rs @@ -1,43 +1,11 @@ #[doc = "Register `DEVDMANXTDSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVDMANXTDSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NXT_DSC_ADD` reader - Next Descriptor Address"] pub type NXT_DSC_ADD_R = crate::FieldReader; #[doc = "Field `NXT_DSC_ADD` writer - Next Descriptor Address"] -pub type NXT_DSC_ADD_W<'a, const O: u8> = crate::FieldWriter<'a, DEVDMANXTDSC_SPEC, 32, O, u32>; +pub type NXT_DSC_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Next Descriptor Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Next Descriptor Address"] #[inline(always)] #[must_use] - pub fn nxt_dsc_add(&mut self) -> NXT_DSC_ADD_W<0> { + pub fn nxt_dsc_add(&mut self) -> NXT_DSC_ADD_W { NXT_DSC_ADD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device DMA Channel Next Descriptor Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devdmanxtdsc](index.html) module"] +#[doc = "Device DMA Channel Next Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmanxtdsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmanxtdsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVDMANXTDSC_SPEC; impl crate::RegisterSpec for DEVDMANXTDSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devdmanxtdsc::R](R) reader structure"] -impl crate::Readable for DEVDMANXTDSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [devdmanxtdsc::W](W) writer structure"] +#[doc = "`read()` method returns [`devdmanxtdsc::R`](R) reader structure"] +impl crate::Readable for DEVDMANXTDSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devdmanxtdsc::W`](W) writer structure"] impl crate::Writable for DEVDMANXTDSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmastatus.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmastatus.rs index 22bdfdaa..a9a725e3 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmastatus.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_devdma/devdmastatus.rs @@ -1,63 +1,31 @@ #[doc = "Register `DEVDMASTATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `DEVDMASTATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHANN_ENB` reader - Channel Enable Status"] pub type CHANN_ENB_R = crate::BitReader; #[doc = "Field `CHANN_ENB` writer - Channel Enable Status"] -pub type CHANN_ENB_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMASTATUS_SPEC, O>; +pub type CHANN_ENB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHANN_ACT` reader - Channel Active Status"] pub type CHANN_ACT_R = crate::BitReader; #[doc = "Field `CHANN_ACT` writer - Channel Active Status"] -pub type CHANN_ACT_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMASTATUS_SPEC, O>; +pub type CHANN_ACT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_TR_ST` reader - End of Channel Transfer Status"] pub type END_TR_ST_R = crate::BitReader; #[doc = "Field `END_TR_ST` writer - End of Channel Transfer Status"] -pub type END_TR_ST_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMASTATUS_SPEC, O>; +pub type END_TR_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_BF_ST` reader - End of Channel Buffer Status"] pub type END_BF_ST_R = crate::BitReader; #[doc = "Field `END_BF_ST` writer - End of Channel Buffer Status"] -pub type END_BF_ST_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMASTATUS_SPEC, O>; +pub type END_BF_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DESC_LDST` reader - Descriptor Loaded Status"] pub type DESC_LDST_R = crate::BitReader; #[doc = "Field `DESC_LDST` writer - Descriptor Loaded Status"] -pub type DESC_LDST_W<'a, const O: u8> = crate::BitWriter<'a, DEVDMASTATUS_SPEC, O>; +pub type DESC_LDST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFF_COUNT` reader - Buffer Byte Count"] pub type BUFF_COUNT_R = crate::FieldReader; #[doc = "Field `BUFF_COUNT` writer - Buffer Byte Count"] -pub type BUFF_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, DEVDMASTATUS_SPEC, 16, O, u16>; +pub type BUFF_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 0 - Channel Enable Status"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bit 0 - Channel Enable Status"] #[inline(always)] #[must_use] - pub fn chann_enb(&mut self) -> CHANN_ENB_W<0> { + pub fn chann_enb(&mut self) -> CHANN_ENB_W { CHANN_ENB_W::new(self) } #[doc = "Bit 1 - Channel Active Status"] #[inline(always)] #[must_use] - pub fn chann_act(&mut self) -> CHANN_ACT_W<1> { + pub fn chann_act(&mut self) -> CHANN_ACT_W { CHANN_ACT_W::new(self) } #[doc = "Bit 4 - End of Channel Transfer Status"] #[inline(always)] #[must_use] - pub fn end_tr_st(&mut self) -> END_TR_ST_W<4> { + pub fn end_tr_st(&mut self) -> END_TR_ST_W { END_TR_ST_W::new(self) } #[doc = "Bit 5 - End of Channel Buffer Status"] #[inline(always)] #[must_use] - pub fn end_bf_st(&mut self) -> END_BF_ST_W<5> { + pub fn end_bf_st(&mut self) -> END_BF_ST_W { END_BF_ST_W::new(self) } #[doc = "Bit 6 - Descriptor Loaded Status"] #[inline(always)] #[must_use] - pub fn desc_ldst(&mut self) -> DESC_LDST_W<6> { + pub fn desc_ldst(&mut self) -> DESC_LDST_W { DESC_LDST_W::new(self) } #[doc = "Bits 16:31 - Buffer Byte Count"] #[inline(always)] #[must_use] - pub fn buff_count(&mut self) -> BUFF_COUNT_W<16> { + pub fn buff_count(&mut self) -> BUFF_COUNT_W { BUFF_COUNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Device DMA Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devdmastatus](index.html) module"] +#[doc = "Device DMA Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`devdmastatus::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`devdmastatus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct DEVDMASTATUS_SPEC; impl crate::RegisterSpec for DEVDMASTATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [devdmastatus::R](R) reader structure"] -impl crate::Readable for DEVDMASTATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [devdmastatus::W](W) writer structure"] +#[doc = "`read()` method returns [`devdmastatus::R`](R) reader structure"] +impl crate::Readable for DEVDMASTATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devdmastatus::W`](W) writer structure"] impl crate::Writable for DEVDMASTATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma.rs index fb05bab6..18626c8d 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma.rs @@ -10,19 +10,23 @@ pub struct USBHS_HSTDMA { #[doc = "0x0c - Host DMA Channel Status Register"] pub hstdmastatus: HSTDMASTATUS, } -#[doc = "HSTDMANXTDSC (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTDMANXTDSC (rw) register accessor: Host DMA Channel Next Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmanxtdsc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmanxtdsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstdmanxtdsc`] +module"] pub type HSTDMANXTDSC = crate::Reg; #[doc = "Host DMA Channel Next Descriptor Address Register"] pub mod hstdmanxtdsc; -#[doc = "HSTDMAADDRESS (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTDMAADDRESS (rw) register accessor: Host DMA Channel Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmaaddress::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmaaddress::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstdmaaddress`] +module"] pub type HSTDMAADDRESS = crate::Reg; #[doc = "Host DMA Channel Address Register"] pub mod hstdmaaddress; -#[doc = "HSTDMACONTROL (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTDMACONTROL (rw) register accessor: Host DMA Channel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmacontrol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmacontrol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstdmacontrol`] +module"] pub type HSTDMACONTROL = crate::Reg; #[doc = "Host DMA Channel Control Register"] pub mod hstdmacontrol; -#[doc = "HSTDMASTATUS (rw) register accessor: an alias for `Reg`"] +#[doc = "HSTDMASTATUS (rw) register accessor: Host DMA Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmastatus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmastatus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`hstdmastatus`] +module"] pub type HSTDMASTATUS = crate::Reg; #[doc = "Host DMA Channel Status Register"] pub mod hstdmastatus; diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmaaddress.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmaaddress.rs index 7e906a41..ca304b4b 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmaaddress.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmaaddress.rs @@ -1,43 +1,11 @@ #[doc = "Register `HSTDMAADDRESS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTDMAADDRESS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BUFF_ADD` reader - Buffer Address"] pub type BUFF_ADD_R = crate::FieldReader; #[doc = "Field `BUFF_ADD` writer - Buffer Address"] -pub type BUFF_ADD_W<'a, const O: u8> = crate::FieldWriter<'a, HSTDMAADDRESS_SPEC, 32, O, u32>; +pub type BUFF_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Buffer Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Buffer Address"] #[inline(always)] #[must_use] - pub fn buff_add(&mut self) -> BUFF_ADD_W<0> { + pub fn buff_add(&mut self) -> BUFF_ADD_W { BUFF_ADD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host DMA Channel Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstdmaaddress](index.html) module"] +#[doc = "Host DMA Channel Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmaaddress::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmaaddress::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTDMAADDRESS_SPEC; impl crate::RegisterSpec for HSTDMAADDRESS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstdmaaddress::R](R) reader structure"] -impl crate::Readable for HSTDMAADDRESS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstdmaaddress::W](W) writer structure"] +#[doc = "`read()` method returns [`hstdmaaddress::R`](R) reader structure"] +impl crate::Readable for HSTDMAADDRESS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstdmaaddress::W`](W) writer structure"] impl crate::Writable for HSTDMAADDRESS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmacontrol.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmacontrol.rs index c76e764e..2135fa59 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmacontrol.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmacontrol.rs @@ -1,75 +1,43 @@ #[doc = "Register `HSTDMACONTROL` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTDMACONTROL` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHANN_ENB` reader - Channel Enable Command"] pub type CHANN_ENB_R = crate::BitReader; #[doc = "Field `CHANN_ENB` writer - Channel Enable Command"] -pub type CHANN_ENB_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type CHANN_ENB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LDNXT_DSC` reader - Load Next Channel Transfer Descriptor Enable Command"] pub type LDNXT_DSC_R = crate::BitReader; #[doc = "Field `LDNXT_DSC` writer - Load Next Channel Transfer Descriptor Enable Command"] -pub type LDNXT_DSC_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type LDNXT_DSC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_TR_EN` reader - End of Transfer Enable Control (OUT transfers only)"] pub type END_TR_EN_R = crate::BitReader; #[doc = "Field `END_TR_EN` writer - End of Transfer Enable Control (OUT transfers only)"] -pub type END_TR_EN_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type END_TR_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_B_EN` reader - End of Buffer Enable Control"] pub type END_B_EN_R = crate::BitReader; #[doc = "Field `END_B_EN` writer - End of Buffer Enable Control"] -pub type END_B_EN_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type END_B_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_TR_IT` reader - End of Transfer Interrupt Enable"] pub type END_TR_IT_R = crate::BitReader; #[doc = "Field `END_TR_IT` writer - End of Transfer Interrupt Enable"] -pub type END_TR_IT_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type END_TR_IT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_BUFFIT` reader - End of Buffer Interrupt Enable"] pub type END_BUFFIT_R = crate::BitReader; #[doc = "Field `END_BUFFIT` writer - End of Buffer Interrupt Enable"] -pub type END_BUFFIT_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type END_BUFFIT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DESC_LD_IT` reader - Descriptor Loaded Interrupt Enable"] pub type DESC_LD_IT_R = crate::BitReader; #[doc = "Field `DESC_LD_IT` writer - Descriptor Loaded Interrupt Enable"] -pub type DESC_LD_IT_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type DESC_LD_IT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BURST_LCK` reader - Burst Lock Enable"] pub type BURST_LCK_R = crate::BitReader; #[doc = "Field `BURST_LCK` writer - Burst Lock Enable"] -pub type BURST_LCK_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMACONTROL_SPEC, O>; +pub type BURST_LCK_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFF_LENGTH` reader - Buffer Byte Length (Write-only)"] pub type BUFF_LENGTH_R = crate::FieldReader; #[doc = "Field `BUFF_LENGTH` writer - Buffer Byte Length (Write-only)"] -pub type BUFF_LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, HSTDMACONTROL_SPEC, 16, O, u16>; +pub type BUFF_LENGTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 0 - Channel Enable Command"] #[inline(always)] @@ -121,76 +89,73 @@ impl W { #[doc = "Bit 0 - Channel Enable Command"] #[inline(always)] #[must_use] - pub fn chann_enb(&mut self) -> CHANN_ENB_W<0> { + pub fn chann_enb(&mut self) -> CHANN_ENB_W { CHANN_ENB_W::new(self) } #[doc = "Bit 1 - Load Next Channel Transfer Descriptor Enable Command"] #[inline(always)] #[must_use] - pub fn ldnxt_dsc(&mut self) -> LDNXT_DSC_W<1> { + pub fn ldnxt_dsc(&mut self) -> LDNXT_DSC_W { LDNXT_DSC_W::new(self) } #[doc = "Bit 2 - End of Transfer Enable Control (OUT transfers only)"] #[inline(always)] #[must_use] - pub fn end_tr_en(&mut self) -> END_TR_EN_W<2> { + pub fn end_tr_en(&mut self) -> END_TR_EN_W { END_TR_EN_W::new(self) } #[doc = "Bit 3 - End of Buffer Enable Control"] #[inline(always)] #[must_use] - pub fn end_b_en(&mut self) -> END_B_EN_W<3> { + pub fn end_b_en(&mut self) -> END_B_EN_W { END_B_EN_W::new(self) } #[doc = "Bit 4 - End of Transfer Interrupt Enable"] #[inline(always)] #[must_use] - pub fn end_tr_it(&mut self) -> END_TR_IT_W<4> { + pub fn end_tr_it(&mut self) -> END_TR_IT_W { END_TR_IT_W::new(self) } #[doc = "Bit 5 - End of Buffer Interrupt Enable"] #[inline(always)] #[must_use] - pub fn end_buffit(&mut self) -> END_BUFFIT_W<5> { + pub fn end_buffit(&mut self) -> END_BUFFIT_W { END_BUFFIT_W::new(self) } #[doc = "Bit 6 - Descriptor Loaded Interrupt Enable"] #[inline(always)] #[must_use] - pub fn desc_ld_it(&mut self) -> DESC_LD_IT_W<6> { + pub fn desc_ld_it(&mut self) -> DESC_LD_IT_W { DESC_LD_IT_W::new(self) } #[doc = "Bit 7 - Burst Lock Enable"] #[inline(always)] #[must_use] - pub fn burst_lck(&mut self) -> BURST_LCK_W<7> { + pub fn burst_lck(&mut self) -> BURST_LCK_W { BURST_LCK_W::new(self) } #[doc = "Bits 16:31 - Buffer Byte Length (Write-only)"] #[inline(always)] #[must_use] - pub fn buff_length(&mut self) -> BUFF_LENGTH_W<16> { + pub fn buff_length(&mut self) -> BUFF_LENGTH_W { BUFF_LENGTH_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host DMA Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstdmacontrol](index.html) module"] +#[doc = "Host DMA Channel Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmacontrol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmacontrol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTDMACONTROL_SPEC; impl crate::RegisterSpec for HSTDMACONTROL_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstdmacontrol::R](R) reader structure"] -impl crate::Readable for HSTDMACONTROL_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstdmacontrol::W](W) writer structure"] +#[doc = "`read()` method returns [`hstdmacontrol::R`](R) reader structure"] +impl crate::Readable for HSTDMACONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstdmacontrol::W`](W) writer structure"] impl crate::Writable for HSTDMACONTROL_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmanxtdsc.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmanxtdsc.rs index 41ee7aac..0467f87f 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmanxtdsc.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmanxtdsc.rs @@ -1,43 +1,11 @@ #[doc = "Register `HSTDMANXTDSC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTDMANXTDSC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NXT_DSC_ADD` reader - Next Descriptor Address"] pub type NXT_DSC_ADD_R = crate::FieldReader; #[doc = "Field `NXT_DSC_ADD` writer - Next Descriptor Address"] -pub type NXT_DSC_ADD_W<'a, const O: u8> = crate::FieldWriter<'a, HSTDMANXTDSC_SPEC, 32, O, u32>; +pub type NXT_DSC_ADD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Next Descriptor Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Next Descriptor Address"] #[inline(always)] #[must_use] - pub fn nxt_dsc_add(&mut self) -> NXT_DSC_ADD_W<0> { + pub fn nxt_dsc_add(&mut self) -> NXT_DSC_ADD_W { NXT_DSC_ADD_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host DMA Channel Next Descriptor Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstdmanxtdsc](index.html) module"] +#[doc = "Host DMA Channel Next Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmanxtdsc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmanxtdsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTDMANXTDSC_SPEC; impl crate::RegisterSpec for HSTDMANXTDSC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstdmanxtdsc::R](R) reader structure"] -impl crate::Readable for HSTDMANXTDSC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstdmanxtdsc::W](W) writer structure"] +#[doc = "`read()` method returns [`hstdmanxtdsc::R`](R) reader structure"] +impl crate::Readable for HSTDMANXTDSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstdmanxtdsc::W`](W) writer structure"] impl crate::Writable for HSTDMANXTDSC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmastatus.rs b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmastatus.rs index e53ca11f..2abb47b5 100644 --- a/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmastatus.rs +++ b/arch/cortex-m/samv71q21-pac/src/usbhs/usbhs_hstdma/hstdmastatus.rs @@ -1,63 +1,31 @@ #[doc = "Register `HSTDMASTATUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `HSTDMASTATUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CHANN_ENB` reader - Channel Enable Status"] pub type CHANN_ENB_R = crate::BitReader; #[doc = "Field `CHANN_ENB` writer - Channel Enable Status"] -pub type CHANN_ENB_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMASTATUS_SPEC, O>; +pub type CHANN_ENB_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CHANN_ACT` reader - Channel Active Status"] pub type CHANN_ACT_R = crate::BitReader; #[doc = "Field `CHANN_ACT` writer - Channel Active Status"] -pub type CHANN_ACT_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMASTATUS_SPEC, O>; +pub type CHANN_ACT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_TR_ST` reader - End of Channel Transfer Status"] pub type END_TR_ST_R = crate::BitReader; #[doc = "Field `END_TR_ST` writer - End of Channel Transfer Status"] -pub type END_TR_ST_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMASTATUS_SPEC, O>; +pub type END_TR_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `END_BF_ST` reader - End of Channel Buffer Status"] pub type END_BF_ST_R = crate::BitReader; #[doc = "Field `END_BF_ST` writer - End of Channel Buffer Status"] -pub type END_BF_ST_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMASTATUS_SPEC, O>; +pub type END_BF_ST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DESC_LDST` reader - Descriptor Loaded Status"] pub type DESC_LDST_R = crate::BitReader; #[doc = "Field `DESC_LDST` writer - Descriptor Loaded Status"] -pub type DESC_LDST_W<'a, const O: u8> = crate::BitWriter<'a, HSTDMASTATUS_SPEC, O>; +pub type DESC_LDST_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BUFF_COUNT` reader - Buffer Byte Count"] pub type BUFF_COUNT_R = crate::FieldReader; #[doc = "Field `BUFF_COUNT` writer - Buffer Byte Count"] -pub type BUFF_COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, HSTDMASTATUS_SPEC, 16, O, u16>; +pub type BUFF_COUNT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bit 0 - Channel Enable Status"] #[inline(always)] @@ -94,58 +62,55 @@ impl W { #[doc = "Bit 0 - Channel Enable Status"] #[inline(always)] #[must_use] - pub fn chann_enb(&mut self) -> CHANN_ENB_W<0> { + pub fn chann_enb(&mut self) -> CHANN_ENB_W { CHANN_ENB_W::new(self) } #[doc = "Bit 1 - Channel Active Status"] #[inline(always)] #[must_use] - pub fn chann_act(&mut self) -> CHANN_ACT_W<1> { + pub fn chann_act(&mut self) -> CHANN_ACT_W { CHANN_ACT_W::new(self) } #[doc = "Bit 4 - End of Channel Transfer Status"] #[inline(always)] #[must_use] - pub fn end_tr_st(&mut self) -> END_TR_ST_W<4> { + pub fn end_tr_st(&mut self) -> END_TR_ST_W { END_TR_ST_W::new(self) } #[doc = "Bit 5 - End of Channel Buffer Status"] #[inline(always)] #[must_use] - pub fn end_bf_st(&mut self) -> END_BF_ST_W<5> { + pub fn end_bf_st(&mut self) -> END_BF_ST_W { END_BF_ST_W::new(self) } #[doc = "Bit 6 - Descriptor Loaded Status"] #[inline(always)] #[must_use] - pub fn desc_ldst(&mut self) -> DESC_LDST_W<6> { + pub fn desc_ldst(&mut self) -> DESC_LDST_W { DESC_LDST_W::new(self) } #[doc = "Bits 16:31 - Buffer Byte Count"] #[inline(always)] #[must_use] - pub fn buff_count(&mut self) -> BUFF_COUNT_W<16> { + pub fn buff_count(&mut self) -> BUFF_COUNT_W { BUFF_COUNT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Host DMA Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hstdmastatus](index.html) module"] +#[doc = "Host DMA Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstdmastatus::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstdmastatus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct HSTDMASTATUS_SPEC; impl crate::RegisterSpec for HSTDMASTATUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [hstdmastatus::R](R) reader structure"] -impl crate::Readable for HSTDMASTATUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [hstdmastatus::W](W) writer structure"] +#[doc = "`read()` method returns [`hstdmastatus::R`](R) reader structure"] +impl crate::Readable for HSTDMASTATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstdmastatus::W`](W) writer structure"] impl crate::Writable for HSTDMASTATUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/utmi.rs b/arch/cortex-m/samv71q21-pac/src/utmi.rs index 758486b5..272e31e3 100644 --- a/arch/cortex-m/samv71q21-pac/src/utmi.rs +++ b/arch/cortex-m/samv71q21-pac/src/utmi.rs @@ -8,11 +8,13 @@ pub struct RegisterBlock { #[doc = "0x30 - UTMI Clock Trimming Register"] pub cktrim: CKTRIM, } -#[doc = "OHCIICR (rw) register accessor: an alias for `Reg`"] +#[doc = "OHCIICR (rw) register accessor: OHCI Interrupt Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ohciicr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ohciicr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ohciicr`] +module"] pub type OHCIICR = crate::Reg; #[doc = "OHCI Interrupt Configuration Register"] pub mod ohciicr; -#[doc = "CKTRIM (rw) register accessor: an alias for `Reg`"] +#[doc = "CKTRIM (rw) register accessor: UTMI Clock Trimming Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cktrim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cktrim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cktrim`] +module"] pub type CKTRIM = crate::Reg; #[doc = "UTMI Clock Trimming Register"] pub mod cktrim; diff --git a/arch/cortex-m/samv71q21-pac/src/utmi/cktrim.rs b/arch/cortex-m/samv71q21-pac/src/utmi/cktrim.rs index b492fb4e..4df4df59 100644 --- a/arch/cortex-m/samv71q21-pac/src/utmi/cktrim.rs +++ b/arch/cortex-m/samv71q21-pac/src/utmi/cktrim.rs @@ -1,39 +1,7 @@ #[doc = "Register `CKTRIM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CKTRIM` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `FREQ` reader - UTMI Reference Clock Frequency"] pub type FREQ_R = crate::FieldReader; #[doc = "UTMI Reference Clock Frequency\n\nValue on reset: 0"] @@ -64,28 +32,32 @@ impl FREQ_R { _ => None, } } - #[doc = "Checks if the value of the field is `XTAL12`"] + #[doc = "12 MHz reference clock"] #[inline(always)] pub fn is_xtal12(&self) -> bool { *self == FREQSELECT_A::XTAL12 } - #[doc = "Checks if the value of the field is `XTAL16`"] + #[doc = "16 MHz reference clock"] #[inline(always)] pub fn is_xtal16(&self) -> bool { *self == FREQSELECT_A::XTAL16 } } #[doc = "Field `FREQ` writer - UTMI Reference Clock Frequency"] -pub type FREQ_W<'a, const O: u8> = crate::FieldWriter<'a, CKTRIM_SPEC, 2, O, FREQSELECT_A>; -impl<'a, const O: u8> FREQ_W<'a, O> { +pub type FREQ_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, FREQSELECT_A>; +impl<'a, REG, const O: u8> FREQ_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "12 MHz reference clock"] #[inline(always)] - pub fn xtal12(self) -> &'a mut W { + pub fn xtal12(self) -> &'a mut crate::W { self.variant(FREQSELECT_A::XTAL12) } #[doc = "16 MHz reference clock"] #[inline(always)] - pub fn xtal16(self) -> &'a mut W { + pub fn xtal16(self) -> &'a mut crate::W { self.variant(FREQSELECT_A::XTAL16) } } @@ -100,28 +72,25 @@ impl W { #[doc = "Bits 0:1 - UTMI Reference Clock Frequency"] #[inline(always)] #[must_use] - pub fn freq(&mut self) -> FREQ_W<0> { + pub fn freq(&mut self) -> FREQ_W { FREQ_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "UTMI Clock Trimming Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cktrim](index.html) module"] +#[doc = "UTMI Clock Trimming Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cktrim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cktrim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CKTRIM_SPEC; impl crate::RegisterSpec for CKTRIM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cktrim::R](R) reader structure"] -impl crate::Readable for CKTRIM_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cktrim::W](W) writer structure"] +#[doc = "`read()` method returns [`cktrim::R`](R) reader structure"] +impl crate::Readable for CKTRIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cktrim::W`](W) writer structure"] impl crate::Writable for CKTRIM_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/utmi/ohciicr.rs b/arch/cortex-m/samv71q21-pac/src/utmi/ohciicr.rs index 8cd5cd5e..d615a206 100644 --- a/arch/cortex-m/samv71q21-pac/src/utmi/ohciicr.rs +++ b/arch/cortex-m/samv71q21-pac/src/utmi/ohciicr.rs @@ -1,55 +1,23 @@ #[doc = "Register `OHCIICR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `OHCIICR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RES0` reader - USB PORTx Reset"] pub type RES0_R = crate::BitReader; #[doc = "Field `RES0` writer - USB PORTx Reset"] -pub type RES0_W<'a, const O: u8> = crate::BitWriter<'a, OHCIICR_SPEC, O>; +pub type RES0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ARIE` reader - OHCI Asynchronous Resume Interrupt Enable"] pub type ARIE_R = crate::BitReader; #[doc = "Field `ARIE` writer - OHCI Asynchronous Resume Interrupt Enable"] -pub type ARIE_W<'a, const O: u8> = crate::BitWriter<'a, OHCIICR_SPEC, O>; +pub type ARIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `APPSTART` reader - "] pub type APPSTART_R = crate::BitReader; #[doc = "Field `APPSTART` writer - "] -pub type APPSTART_W<'a, const O: u8> = crate::BitWriter<'a, OHCIICR_SPEC, O>; +pub type APPSTART_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `UDPPUDIS` reader - USB Device Pull-up Disable"] pub type UDPPUDIS_R = crate::BitReader; #[doc = "Field `UDPPUDIS` writer - USB Device Pull-up Disable"] -pub type UDPPUDIS_W<'a, const O: u8> = crate::BitWriter<'a, OHCIICR_SPEC, O>; +pub type UDPPUDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - USB PORTx Reset"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bit 0 - USB PORTx Reset"] #[inline(always)] #[must_use] - pub fn res0(&mut self) -> RES0_W<0> { + pub fn res0(&mut self) -> RES0_W { RES0_W::new(self) } #[doc = "Bit 4 - OHCI Asynchronous Resume Interrupt Enable"] #[inline(always)] #[must_use] - pub fn arie(&mut self) -> ARIE_W<4> { + pub fn arie(&mut self) -> ARIE_W { ARIE_W::new(self) } #[doc = "Bit 5"] #[inline(always)] #[must_use] - pub fn appstart(&mut self) -> APPSTART_W<5> { + pub fn appstart(&mut self) -> APPSTART_W { APPSTART_W::new(self) } #[doc = "Bit 23 - USB Device Pull-up Disable"] #[inline(always)] #[must_use] - pub fn udppudis(&mut self) -> UDPPUDIS_W<23> { + pub fn udppudis(&mut self) -> UDPPUDIS_W { UDPPUDIS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "OHCI Interrupt Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ohciicr](index.html) module"] +#[doc = "OHCI Interrupt Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ohciicr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ohciicr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct OHCIICR_SPEC; impl crate::RegisterSpec for OHCIICR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [ohciicr::R](R) reader structure"] -impl crate::Readable for OHCIICR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [ohciicr::W](W) writer structure"] +#[doc = "`read()` method returns [`ohciicr::R`](R) reader structure"] +impl crate::Readable for OHCIICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ohciicr::W`](W) writer structure"] impl crate::Writable for OHCIICR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/wdt.rs b/arch/cortex-m/samv71q21-pac/src/wdt.rs index 7c245b25..71ec9362 100644 --- a/arch/cortex-m/samv71q21-pac/src/wdt.rs +++ b/arch/cortex-m/samv71q21-pac/src/wdt.rs @@ -8,15 +8,18 @@ pub struct RegisterBlock { #[doc = "0x08 - Status Register"] pub sr: SR, } -#[doc = "CR (w) register accessor: an alias for `Reg`"] +#[doc = "CR (w) register accessor: Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cr`] +module"] pub type CR = crate::Reg; #[doc = "Control Register"] pub mod cr; -#[doc = "MR (rw) register accessor: an alias for `Reg`"] +#[doc = "MR (rw) register accessor: Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mr`] +module"] pub type MR = crate::Reg; #[doc = "Mode Register"] pub mod mr; -#[doc = "SR (r) register accessor: an alias for `Reg`"] +#[doc = "SR (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`sr`] +module"] pub type SR = crate::Reg; #[doc = "Status Register"] pub mod sr; diff --git a/arch/cortex-m/samv71q21-pac/src/wdt/cr.rs b/arch/cortex-m/samv71q21-pac/src/wdt/cr.rs index e4413197..88eb0a88 100644 --- a/arch/cortex-m/samv71q21-pac/src/wdt/cr.rs +++ b/arch/cortex-m/samv71q21-pac/src/wdt/cr.rs @@ -1,26 +1,7 @@ #[doc = "Register `CR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WDRSTT` writer - Watchdog Restart"] -pub type WDRSTT_W<'a, const O: u8> = crate::BitWriter<'a, CR_SPEC, O>; +pub type WDRSTT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Password\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] #[repr(u8)] @@ -38,11 +19,15 @@ impl crate::FieldSpec for KEYSELECT_AW { type Ux = u8; } #[doc = "Field `KEY` writer - Password"] -pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, CR_SPEC, 8, O, KEYSELECT_AW>; -impl<'a, const O: u8> KEY_W<'a, O> { +pub type KEY_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O, KEYSELECT_AW>; +impl<'a, REG, const O: u8> KEY_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Writing any other value in this field aborts the write operation."] #[inline(always)] - pub fn passwd(self) -> &'a mut W { + pub fn passwd(self) -> &'a mut crate::W { self.variant(KEYSELECT_AW::PASSWD) } } @@ -50,30 +35,29 @@ impl W { #[doc = "Bit 0 - Watchdog Restart"] #[inline(always)] #[must_use] - pub fn wdrstt(&mut self) -> WDRSTT_W<0> { + pub fn wdrstt(&mut self) -> WDRSTT_W { WDRSTT_W::new(self) } #[doc = "Bits 24:31 - Password"] #[inline(always)] #[must_use] - pub fn key(&mut self) -> KEY_W<24> { + pub fn key(&mut self) -> KEY_W { KEY_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr](index.html) module"] +#[doc = "Control Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CR_SPEC; impl crate::RegisterSpec for CR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"] impl crate::Writable for CR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/wdt/mr.rs b/arch/cortex-m/samv71q21-pac/src/wdt/mr.rs index 11ec7ba1..748153ad 100644 --- a/arch/cortex-m/samv71q21-pac/src/wdt/mr.rs +++ b/arch/cortex-m/samv71q21-pac/src/wdt/mr.rs @@ -1,67 +1,35 @@ #[doc = "Register `MR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `MR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WDV` reader - Watchdog Counter Value"] pub type WDV_R = crate::FieldReader; #[doc = "Field `WDV` writer - Watchdog Counter Value"] -pub type WDV_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 12, O, u16>; +pub type WDV_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `WDFIEN` reader - Watchdog Fault Interrupt Enable"] pub type WDFIEN_R = crate::BitReader; #[doc = "Field `WDFIEN` writer - Watchdog Fault Interrupt Enable"] -pub type WDFIEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDFIEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDRSTEN` reader - Watchdog Reset Enable"] pub type WDRSTEN_R = crate::BitReader; #[doc = "Field `WDRSTEN` writer - Watchdog Reset Enable"] -pub type WDRSTEN_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDRSTEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDDIS` reader - Watchdog Disable"] pub type WDDIS_R = crate::BitReader; #[doc = "Field `WDDIS` writer - Watchdog Disable"] -pub type WDDIS_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDDIS_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDD` reader - Watchdog Delta Value"] pub type WDD_R = crate::FieldReader; #[doc = "Field `WDD` writer - Watchdog Delta Value"] -pub type WDD_W<'a, const O: u8> = crate::FieldWriter<'a, MR_SPEC, 12, O, u16>; +pub type WDD_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; #[doc = "Field `WDDBGHLT` reader - Watchdog Debug Halt"] pub type WDDBGHLT_R = crate::BitReader; #[doc = "Field `WDDBGHLT` writer - Watchdog Debug Halt"] -pub type WDDBGHLT_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDDBGHLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WDIDLEHLT` reader - Watchdog Idle Halt"] pub type WDIDLEHLT_R = crate::BitReader; #[doc = "Field `WDIDLEHLT` writer - Watchdog Idle Halt"] -pub type WDIDLEHLT_W<'a, const O: u8> = crate::BitWriter<'a, MR_SPEC, O>; +pub type WDIDLEHLT_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bits 0:11 - Watchdog Counter Value"] #[inline(always)] @@ -103,64 +71,61 @@ impl W { #[doc = "Bits 0:11 - Watchdog Counter Value"] #[inline(always)] #[must_use] - pub fn wdv(&mut self) -> WDV_W<0> { + pub fn wdv(&mut self) -> WDV_W { WDV_W::new(self) } #[doc = "Bit 12 - Watchdog Fault Interrupt Enable"] #[inline(always)] #[must_use] - pub fn wdfien(&mut self) -> WDFIEN_W<12> { + pub fn wdfien(&mut self) -> WDFIEN_W { WDFIEN_W::new(self) } #[doc = "Bit 13 - Watchdog Reset Enable"] #[inline(always)] #[must_use] - pub fn wdrsten(&mut self) -> WDRSTEN_W<13> { + pub fn wdrsten(&mut self) -> WDRSTEN_W { WDRSTEN_W::new(self) } #[doc = "Bit 15 - Watchdog Disable"] #[inline(always)] #[must_use] - pub fn wddis(&mut self) -> WDDIS_W<15> { + pub fn wddis(&mut self) -> WDDIS_W { WDDIS_W::new(self) } #[doc = "Bits 16:27 - Watchdog Delta Value"] #[inline(always)] #[must_use] - pub fn wdd(&mut self) -> WDD_W<16> { + pub fn wdd(&mut self) -> WDD_W { WDD_W::new(self) } #[doc = "Bit 28 - Watchdog Debug Halt"] #[inline(always)] #[must_use] - pub fn wddbghlt(&mut self) -> WDDBGHLT_W<28> { + pub fn wddbghlt(&mut self) -> WDDBGHLT_W { WDDBGHLT_W::new(self) } #[doc = "Bit 29 - Watchdog Idle Halt"] #[inline(always)] #[must_use] - pub fn wdidlehlt(&mut self) -> WDIDLEHLT_W<29> { + pub fn wdidlehlt(&mut self) -> WDIDLEHLT_W { WDIDLEHLT_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mr](index.html) module"] +#[doc = "Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct MR_SPEC; impl crate::RegisterSpec for MR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [mr::R](R) reader structure"] -impl crate::Readable for MR_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [mr::W](W) writer structure"] +#[doc = "`read()` method returns [`mr::R`](R) reader structure"] +impl crate::Readable for MR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mr::W`](W) writer structure"] impl crate::Writable for MR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/wdt/sr.rs b/arch/cortex-m/samv71q21-pac/src/wdt/sr.rs index d890bab1..14000164 100644 --- a/arch/cortex-m/samv71q21-pac/src/wdt/sr.rs +++ b/arch/cortex-m/samv71q21-pac/src/wdt/sr.rs @@ -1,18 +1,5 @@ #[doc = "Register `SR` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `WDUNF` reader - Watchdog Underflow (cleared on read)"] pub type WDUNF_R = crate::BitReader; #[doc = "Field `WDERR` reader - Watchdog Error (cleared on read)"] @@ -29,15 +16,13 @@ impl R { WDERR_R::new(((self.bits >> 1) & 1) != 0) } } -#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"] +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct SR_SPEC; impl crate::RegisterSpec for SR_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [sr::R](R) reader structure"] -impl crate::Readable for SR_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`sr::R`](R) reader structure"] +impl crate::Readable for SR_SPEC {} #[doc = "`reset()` method sets SR to value 0"] impl crate::Resettable for SR_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac.rs b/arch/cortex-m/samv71q21-pac/src/xdmac.rs index af277373..763f8dbd 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac.rs @@ -108,71 +108,88 @@ pub struct RegisterBlock { #[doc = "0x610..0x648 - Channel Interrupt Enable Register"] pub xdmac_chid23: XDMAC_CHID, } -#[doc = "GTYPE (r) register accessor: an alias for `Reg`"] +#[doc = "GTYPE (r) register accessor: Global Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtype::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gtype`] +module"] pub type GTYPE = crate::Reg; #[doc = "Global Type Register"] pub mod gtype; -#[doc = "GCFG (rw) register accessor: an alias for `Reg`"] +#[doc = "GCFG (rw) register accessor: Global Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gcfg`] +module"] pub type GCFG = crate::Reg; #[doc = "Global Configuration Register"] pub mod gcfg; -#[doc = "GWAC (rw) register accessor: an alias for `Reg`"] +#[doc = "GWAC (rw) register accessor: Global Weighted Arbiter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gwac::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gwac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gwac`] +module"] pub type GWAC = crate::Reg; #[doc = "Global Weighted Arbiter Configuration Register"] pub mod gwac; -#[doc = "GIE (w) register accessor: an alias for `Reg`"] +#[doc = "GIE (w) register accessor: Global Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gie::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gie`] +module"] pub type GIE = crate::Reg; #[doc = "Global Interrupt Enable Register"] pub mod gie; -#[doc = "GID (w) register accessor: an alias for `Reg`"] +#[doc = "GID (w) register accessor: Global Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gid::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gid`] +module"] pub type GID = crate::Reg; #[doc = "Global Interrupt Disable Register"] pub mod gid; -#[doc = "GIM (r) register accessor: an alias for `Reg`"] +#[doc = "GIM (r) register accessor: Global Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gim::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gim`] +module"] pub type GIM = crate::Reg; #[doc = "Global Interrupt Mask Register"] pub mod gim; -#[doc = "GIS (r) register accessor: an alias for `Reg`"] +#[doc = "GIS (r) register accessor: Global Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gis`] +module"] pub type GIS = crate::Reg; #[doc = "Global Interrupt Status Register"] pub mod gis; -#[doc = "GE (w) register accessor: an alias for `Reg`"] +#[doc = "GE (w) register accessor: Global Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ge::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`ge`] +module"] pub type GE = crate::Reg; #[doc = "Global Channel Enable Register"] pub mod ge; -#[doc = "GD (w) register accessor: an alias for `Reg`"] +#[doc = "GD (w) register accessor: Global Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gd`] +module"] pub type GD = crate::Reg; #[doc = "Global Channel Disable Register"] pub mod gd; -#[doc = "GS (r) register accessor: an alias for `Reg`"] +#[doc = "GS (r) register accessor: Global Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gs::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gs`] +module"] pub type GS = crate::Reg; #[doc = "Global Channel Status Register"] pub mod gs; -#[doc = "GRS (rw) register accessor: an alias for `Reg`"] +#[doc = "GRS (rw) register accessor: Global Channel Read Suspend Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`grs`] +module"] pub type GRS = crate::Reg; #[doc = "Global Channel Read Suspend Register"] pub mod grs; -#[doc = "GWS (rw) register accessor: an alias for `Reg`"] +#[doc = "GWS (rw) register accessor: Global Channel Write Suspend Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gws::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gws::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gws`] +module"] pub type GWS = crate::Reg; #[doc = "Global Channel Write Suspend Register"] pub mod gws; -#[doc = "GRWS (w) register accessor: an alias for `Reg`"] +#[doc = "GRWS (w) register accessor: Global Channel Read Write Suspend Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grws::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`grws`] +module"] pub type GRWS = crate::Reg; #[doc = "Global Channel Read Write Suspend Register"] pub mod grws; -#[doc = "GRWR (w) register accessor: an alias for `Reg`"] +#[doc = "GRWR (w) register accessor: Global Channel Read Write Resume Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grwr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`grwr`] +module"] pub type GRWR = crate::Reg; #[doc = "Global Channel Read Write Resume Register"] pub mod grwr; -#[doc = "GSWR (w) register accessor: an alias for `Reg`"] +#[doc = "GSWR (w) register accessor: Global Channel Software Request Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gswr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gswr`] +module"] pub type GSWR = crate::Reg; #[doc = "Global Channel Software Request Register"] pub mod gswr; -#[doc = "GSWS (r) register accessor: an alias for `Reg`"] +#[doc = "GSWS (r) register accessor: Global Channel Software Request Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gsws::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gsws`] +module"] pub type GSWS = crate::Reg; #[doc = "Global Channel Software Request Status Register"] pub mod gsws; -#[doc = "GSWF (w) register accessor: an alias for `Reg`"] +#[doc = "GSWF (w) register accessor: Global Channel Software Flush Request Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gswf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`gswf`] +module"] pub type GSWF = crate::Reg; #[doc = "Global Channel Software Flush Request Register"] pub mod gswf; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gcfg.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gcfg.rs index 9f56e6e2..8d32a7c6 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gcfg.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gcfg.rs @@ -1,59 +1,27 @@ #[doc = "Register `GCFG` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GCFG` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `CGDISREG` reader - Configuration Registers Clock Gating Disable"] pub type CGDISREG_R = crate::BitReader; #[doc = "Field `CGDISREG` writer - Configuration Registers Clock Gating Disable"] -pub type CGDISREG_W<'a, const O: u8> = crate::BitWriter<'a, GCFG_SPEC, O>; +pub type CGDISREG_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGDISPIPE` reader - Pipeline Clock Gating Disable"] pub type CGDISPIPE_R = crate::BitReader; #[doc = "Field `CGDISPIPE` writer - Pipeline Clock Gating Disable"] -pub type CGDISPIPE_W<'a, const O: u8> = crate::BitWriter<'a, GCFG_SPEC, O>; +pub type CGDISPIPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGDISFIFO` reader - FIFO Clock Gating Disable"] pub type CGDISFIFO_R = crate::BitReader; #[doc = "Field `CGDISFIFO` writer - FIFO Clock Gating Disable"] -pub type CGDISFIFO_W<'a, const O: u8> = crate::BitWriter<'a, GCFG_SPEC, O>; +pub type CGDISFIFO_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `CGDISIF` reader - Bus Interface Clock Gating Disable"] pub type CGDISIF_R = crate::BitReader; #[doc = "Field `CGDISIF` writer - Bus Interface Clock Gating Disable"] -pub type CGDISIF_W<'a, const O: u8> = crate::BitWriter<'a, GCFG_SPEC, O>; +pub type CGDISIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `BXKBEN` reader - Boundary X Kilobyte Enable"] pub type BXKBEN_R = crate::BitReader; #[doc = "Field `BXKBEN` writer - Boundary X Kilobyte Enable"] -pub type BXKBEN_W<'a, const O: u8> = crate::BitWriter<'a, GCFG_SPEC, O>; +pub type BXKBEN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - Configuration Registers Clock Gating Disable"] #[inline(always)] @@ -85,52 +53,49 @@ impl W { #[doc = "Bit 0 - Configuration Registers Clock Gating Disable"] #[inline(always)] #[must_use] - pub fn cgdisreg(&mut self) -> CGDISREG_W<0> { + pub fn cgdisreg(&mut self) -> CGDISREG_W { CGDISREG_W::new(self) } #[doc = "Bit 1 - Pipeline Clock Gating Disable"] #[inline(always)] #[must_use] - pub fn cgdispipe(&mut self) -> CGDISPIPE_W<1> { + pub fn cgdispipe(&mut self) -> CGDISPIPE_W { CGDISPIPE_W::new(self) } #[doc = "Bit 2 - FIFO Clock Gating Disable"] #[inline(always)] #[must_use] - pub fn cgdisfifo(&mut self) -> CGDISFIFO_W<2> { + pub fn cgdisfifo(&mut self) -> CGDISFIFO_W { CGDISFIFO_W::new(self) } #[doc = "Bit 3 - Bus Interface Clock Gating Disable"] #[inline(always)] #[must_use] - pub fn cgdisif(&mut self) -> CGDISIF_W<3> { + pub fn cgdisif(&mut self) -> CGDISIF_W { CGDISIF_W::new(self) } #[doc = "Bit 8 - Boundary X Kilobyte Enable"] #[inline(always)] #[must_use] - pub fn bxkben(&mut self) -> BXKBEN_W<8> { + pub fn bxkben(&mut self) -> BXKBEN_W { BXKBEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gcfg](index.html) module"] +#[doc = "Global Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GCFG_SPEC; impl crate::RegisterSpec for GCFG_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gcfg::R](R) reader structure"] -impl crate::Readable for GCFG_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gcfg::W](W) writer structure"] +#[doc = "`read()` method returns [`gcfg::R`](R) reader structure"] +impl crate::Readable for GCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gcfg::W`](W) writer structure"] impl crate::Writable for GCFG_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gd.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gd.rs index ca0ac6e0..21e1bf2e 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gd.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gd.rs @@ -1,232 +1,212 @@ #[doc = "Register `GD` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DI0` writer - XDMAC Channel 0 Disable Bit"] -pub type DI0_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI1` writer - XDMAC Channel 1 Disable Bit"] -pub type DI1_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI2` writer - XDMAC Channel 2 Disable Bit"] -pub type DI2_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI3` writer - XDMAC Channel 3 Disable Bit"] -pub type DI3_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI4` writer - XDMAC Channel 4 Disable Bit"] -pub type DI4_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI5` writer - XDMAC Channel 5 Disable Bit"] -pub type DI5_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI6` writer - XDMAC Channel 6 Disable Bit"] -pub type DI6_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI7` writer - XDMAC Channel 7 Disable Bit"] -pub type DI7_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI8` writer - XDMAC Channel 8 Disable Bit"] -pub type DI8_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI9` writer - XDMAC Channel 9 Disable Bit"] -pub type DI9_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI10` writer - XDMAC Channel 10 Disable Bit"] -pub type DI10_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI11` writer - XDMAC Channel 11 Disable Bit"] -pub type DI11_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI12` writer - XDMAC Channel 12 Disable Bit"] -pub type DI12_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI13` writer - XDMAC Channel 13 Disable Bit"] -pub type DI13_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI14` writer - XDMAC Channel 14 Disable Bit"] -pub type DI14_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI15` writer - XDMAC Channel 15 Disable Bit"] -pub type DI15_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI16` writer - XDMAC Channel 16 Disable Bit"] -pub type DI16_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI17` writer - XDMAC Channel 17 Disable Bit"] -pub type DI17_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI18` writer - XDMAC Channel 18 Disable Bit"] -pub type DI18_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI19` writer - XDMAC Channel 19 Disable Bit"] -pub type DI19_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI20` writer - XDMAC Channel 20 Disable Bit"] -pub type DI20_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI21` writer - XDMAC Channel 21 Disable Bit"] -pub type DI21_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI22` writer - XDMAC Channel 22 Disable Bit"] -pub type DI22_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DI23` writer - XDMAC Channel 23 Disable Bit"] -pub type DI23_W<'a, const O: u8> = crate::BitWriter<'a, GD_SPEC, O>; +pub type DI23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Disable Bit"] #[inline(always)] #[must_use] - pub fn di0(&mut self) -> DI0_W<0> { + pub fn di0(&mut self) -> DI0_W { DI0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Disable Bit"] #[inline(always)] #[must_use] - pub fn di1(&mut self) -> DI1_W<1> { + pub fn di1(&mut self) -> DI1_W { DI1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Disable Bit"] #[inline(always)] #[must_use] - pub fn di2(&mut self) -> DI2_W<2> { + pub fn di2(&mut self) -> DI2_W { DI2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Disable Bit"] #[inline(always)] #[must_use] - pub fn di3(&mut self) -> DI3_W<3> { + pub fn di3(&mut self) -> DI3_W { DI3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Disable Bit"] #[inline(always)] #[must_use] - pub fn di4(&mut self) -> DI4_W<4> { + pub fn di4(&mut self) -> DI4_W { DI4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Disable Bit"] #[inline(always)] #[must_use] - pub fn di5(&mut self) -> DI5_W<5> { + pub fn di5(&mut self) -> DI5_W { DI5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Disable Bit"] #[inline(always)] #[must_use] - pub fn di6(&mut self) -> DI6_W<6> { + pub fn di6(&mut self) -> DI6_W { DI6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Disable Bit"] #[inline(always)] #[must_use] - pub fn di7(&mut self) -> DI7_W<7> { + pub fn di7(&mut self) -> DI7_W { DI7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Disable Bit"] #[inline(always)] #[must_use] - pub fn di8(&mut self) -> DI8_W<8> { + pub fn di8(&mut self) -> DI8_W { DI8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Disable Bit"] #[inline(always)] #[must_use] - pub fn di9(&mut self) -> DI9_W<9> { + pub fn di9(&mut self) -> DI9_W { DI9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Disable Bit"] #[inline(always)] #[must_use] - pub fn di10(&mut self) -> DI10_W<10> { + pub fn di10(&mut self) -> DI10_W { DI10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Disable Bit"] #[inline(always)] #[must_use] - pub fn di11(&mut self) -> DI11_W<11> { + pub fn di11(&mut self) -> DI11_W { DI11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Disable Bit"] #[inline(always)] #[must_use] - pub fn di12(&mut self) -> DI12_W<12> { + pub fn di12(&mut self) -> DI12_W { DI12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Disable Bit"] #[inline(always)] #[must_use] - pub fn di13(&mut self) -> DI13_W<13> { + pub fn di13(&mut self) -> DI13_W { DI13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Disable Bit"] #[inline(always)] #[must_use] - pub fn di14(&mut self) -> DI14_W<14> { + pub fn di14(&mut self) -> DI14_W { DI14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Disable Bit"] #[inline(always)] #[must_use] - pub fn di15(&mut self) -> DI15_W<15> { + pub fn di15(&mut self) -> DI15_W { DI15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Disable Bit"] #[inline(always)] #[must_use] - pub fn di16(&mut self) -> DI16_W<16> { + pub fn di16(&mut self) -> DI16_W { DI16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Disable Bit"] #[inline(always)] #[must_use] - pub fn di17(&mut self) -> DI17_W<17> { + pub fn di17(&mut self) -> DI17_W { DI17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Disable Bit"] #[inline(always)] #[must_use] - pub fn di18(&mut self) -> DI18_W<18> { + pub fn di18(&mut self) -> DI18_W { DI18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Disable Bit"] #[inline(always)] #[must_use] - pub fn di19(&mut self) -> DI19_W<19> { + pub fn di19(&mut self) -> DI19_W { DI19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Disable Bit"] #[inline(always)] #[must_use] - pub fn di20(&mut self) -> DI20_W<20> { + pub fn di20(&mut self) -> DI20_W { DI20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Disable Bit"] #[inline(always)] #[must_use] - pub fn di21(&mut self) -> DI21_W<21> { + pub fn di21(&mut self) -> DI21_W { DI21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Disable Bit"] #[inline(always)] #[must_use] - pub fn di22(&mut self) -> DI22_W<22> { + pub fn di22(&mut self) -> DI22_W { DI22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Disable Bit"] #[inline(always)] #[must_use] - pub fn di23(&mut self) -> DI23_W<23> { + pub fn di23(&mut self) -> DI23_W { DI23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gd](index.html) module"] +#[doc = "Global Channel Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GD_SPEC; impl crate::RegisterSpec for GD_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gd::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gd::W`](W) writer structure"] impl crate::Writable for GD_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/ge.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/ge.rs index 3653e821..5859b5b8 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/ge.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/ge.rs @@ -1,232 +1,212 @@ #[doc = "Register `GE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `EN0` writer - XDMAC Channel 0 Enable Bit"] -pub type EN0_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN1` writer - XDMAC Channel 1 Enable Bit"] -pub type EN1_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN2` writer - XDMAC Channel 2 Enable Bit"] -pub type EN2_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN3` writer - XDMAC Channel 3 Enable Bit"] -pub type EN3_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN4` writer - XDMAC Channel 4 Enable Bit"] -pub type EN4_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN5` writer - XDMAC Channel 5 Enable Bit"] -pub type EN5_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN6` writer - XDMAC Channel 6 Enable Bit"] -pub type EN6_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN7` writer - XDMAC Channel 7 Enable Bit"] -pub type EN7_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN8` writer - XDMAC Channel 8 Enable Bit"] -pub type EN8_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN9` writer - XDMAC Channel 9 Enable Bit"] -pub type EN9_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN10` writer - XDMAC Channel 10 Enable Bit"] -pub type EN10_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN11` writer - XDMAC Channel 11 Enable Bit"] -pub type EN11_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN12` writer - XDMAC Channel 12 Enable Bit"] -pub type EN12_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN13` writer - XDMAC Channel 13 Enable Bit"] -pub type EN13_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN14` writer - XDMAC Channel 14 Enable Bit"] -pub type EN14_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN15` writer - XDMAC Channel 15 Enable Bit"] -pub type EN15_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN16` writer - XDMAC Channel 16 Enable Bit"] -pub type EN16_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN17` writer - XDMAC Channel 17 Enable Bit"] -pub type EN17_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN18` writer - XDMAC Channel 18 Enable Bit"] -pub type EN18_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN19` writer - XDMAC Channel 19 Enable Bit"] -pub type EN19_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN20` writer - XDMAC Channel 20 Enable Bit"] -pub type EN20_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN21` writer - XDMAC Channel 21 Enable Bit"] -pub type EN21_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN22` writer - XDMAC Channel 22 Enable Bit"] -pub type EN22_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `EN23` writer - XDMAC Channel 23 Enable Bit"] -pub type EN23_W<'a, const O: u8> = crate::BitWriter<'a, GE_SPEC, O>; +pub type EN23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Enable Bit"] #[inline(always)] #[must_use] - pub fn en0(&mut self) -> EN0_W<0> { + pub fn en0(&mut self) -> EN0_W { EN0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Enable Bit"] #[inline(always)] #[must_use] - pub fn en1(&mut self) -> EN1_W<1> { + pub fn en1(&mut self) -> EN1_W { EN1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Enable Bit"] #[inline(always)] #[must_use] - pub fn en2(&mut self) -> EN2_W<2> { + pub fn en2(&mut self) -> EN2_W { EN2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Enable Bit"] #[inline(always)] #[must_use] - pub fn en3(&mut self) -> EN3_W<3> { + pub fn en3(&mut self) -> EN3_W { EN3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Enable Bit"] #[inline(always)] #[must_use] - pub fn en4(&mut self) -> EN4_W<4> { + pub fn en4(&mut self) -> EN4_W { EN4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Enable Bit"] #[inline(always)] #[must_use] - pub fn en5(&mut self) -> EN5_W<5> { + pub fn en5(&mut self) -> EN5_W { EN5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Enable Bit"] #[inline(always)] #[must_use] - pub fn en6(&mut self) -> EN6_W<6> { + pub fn en6(&mut self) -> EN6_W { EN6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Enable Bit"] #[inline(always)] #[must_use] - pub fn en7(&mut self) -> EN7_W<7> { + pub fn en7(&mut self) -> EN7_W { EN7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Enable Bit"] #[inline(always)] #[must_use] - pub fn en8(&mut self) -> EN8_W<8> { + pub fn en8(&mut self) -> EN8_W { EN8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Enable Bit"] #[inline(always)] #[must_use] - pub fn en9(&mut self) -> EN9_W<9> { + pub fn en9(&mut self) -> EN9_W { EN9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Enable Bit"] #[inline(always)] #[must_use] - pub fn en10(&mut self) -> EN10_W<10> { + pub fn en10(&mut self) -> EN10_W { EN10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Enable Bit"] #[inline(always)] #[must_use] - pub fn en11(&mut self) -> EN11_W<11> { + pub fn en11(&mut self) -> EN11_W { EN11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Enable Bit"] #[inline(always)] #[must_use] - pub fn en12(&mut self) -> EN12_W<12> { + pub fn en12(&mut self) -> EN12_W { EN12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Enable Bit"] #[inline(always)] #[must_use] - pub fn en13(&mut self) -> EN13_W<13> { + pub fn en13(&mut self) -> EN13_W { EN13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Enable Bit"] #[inline(always)] #[must_use] - pub fn en14(&mut self) -> EN14_W<14> { + pub fn en14(&mut self) -> EN14_W { EN14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Enable Bit"] #[inline(always)] #[must_use] - pub fn en15(&mut self) -> EN15_W<15> { + pub fn en15(&mut self) -> EN15_W { EN15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Enable Bit"] #[inline(always)] #[must_use] - pub fn en16(&mut self) -> EN16_W<16> { + pub fn en16(&mut self) -> EN16_W { EN16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Enable Bit"] #[inline(always)] #[must_use] - pub fn en17(&mut self) -> EN17_W<17> { + pub fn en17(&mut self) -> EN17_W { EN17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Enable Bit"] #[inline(always)] #[must_use] - pub fn en18(&mut self) -> EN18_W<18> { + pub fn en18(&mut self) -> EN18_W { EN18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Enable Bit"] #[inline(always)] #[must_use] - pub fn en19(&mut self) -> EN19_W<19> { + pub fn en19(&mut self) -> EN19_W { EN19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Enable Bit"] #[inline(always)] #[must_use] - pub fn en20(&mut self) -> EN20_W<20> { + pub fn en20(&mut self) -> EN20_W { EN20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Enable Bit"] #[inline(always)] #[must_use] - pub fn en21(&mut self) -> EN21_W<21> { + pub fn en21(&mut self) -> EN21_W { EN21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Enable Bit"] #[inline(always)] #[must_use] - pub fn en22(&mut self) -> EN22_W<22> { + pub fn en22(&mut self) -> EN22_W { EN22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Enable Bit"] #[inline(always)] #[must_use] - pub fn en23(&mut self) -> EN23_W<23> { + pub fn en23(&mut self) -> EN23_W { EN23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ge](index.html) module"] +#[doc = "Global Channel Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ge::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GE_SPEC; impl crate::RegisterSpec for GE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [ge::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`ge::W`](W) writer structure"] impl crate::Writable for GE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gid.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gid.rs index 6991ebb7..2c25ddb7 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gid.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gid.rs @@ -1,232 +1,212 @@ #[doc = "Register `GID` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `ID0` writer - XDMAC Channel 0 Interrupt Disable Bit"] -pub type ID0_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID1` writer - XDMAC Channel 1 Interrupt Disable Bit"] -pub type ID1_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID2` writer - XDMAC Channel 2 Interrupt Disable Bit"] -pub type ID2_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID3` writer - XDMAC Channel 3 Interrupt Disable Bit"] -pub type ID3_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID4` writer - XDMAC Channel 4 Interrupt Disable Bit"] -pub type ID4_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID5` writer - XDMAC Channel 5 Interrupt Disable Bit"] -pub type ID5_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID6` writer - XDMAC Channel 6 Interrupt Disable Bit"] -pub type ID6_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID7` writer - XDMAC Channel 7 Interrupt Disable Bit"] -pub type ID7_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID8` writer - XDMAC Channel 8 Interrupt Disable Bit"] -pub type ID8_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID9` writer - XDMAC Channel 9 Interrupt Disable Bit"] -pub type ID9_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID10` writer - XDMAC Channel 10 Interrupt Disable Bit"] -pub type ID10_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID11` writer - XDMAC Channel 11 Interrupt Disable Bit"] -pub type ID11_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID12` writer - XDMAC Channel 12 Interrupt Disable Bit"] -pub type ID12_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID13` writer - XDMAC Channel 13 Interrupt Disable Bit"] -pub type ID13_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID14` writer - XDMAC Channel 14 Interrupt Disable Bit"] -pub type ID14_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID15` writer - XDMAC Channel 15 Interrupt Disable Bit"] -pub type ID15_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID16` writer - XDMAC Channel 16 Interrupt Disable Bit"] -pub type ID16_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID17` writer - XDMAC Channel 17 Interrupt Disable Bit"] -pub type ID17_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID18` writer - XDMAC Channel 18 Interrupt Disable Bit"] -pub type ID18_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID19` writer - XDMAC Channel 19 Interrupt Disable Bit"] -pub type ID19_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID20` writer - XDMAC Channel 20 Interrupt Disable Bit"] -pub type ID20_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID21` writer - XDMAC Channel 21 Interrupt Disable Bit"] -pub type ID21_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID22` writer - XDMAC Channel 22 Interrupt Disable Bit"] -pub type ID22_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ID23` writer - XDMAC Channel 23 Interrupt Disable Bit"] -pub type ID23_W<'a, const O: u8> = crate::BitWriter<'a, GID_SPEC, O>; +pub type ID23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id0(&mut self) -> ID0_W<0> { + pub fn id0(&mut self) -> ID0_W { ID0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id1(&mut self) -> ID1_W<1> { + pub fn id1(&mut self) -> ID1_W { ID1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id2(&mut self) -> ID2_W<2> { + pub fn id2(&mut self) -> ID2_W { ID2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id3(&mut self) -> ID3_W<3> { + pub fn id3(&mut self) -> ID3_W { ID3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id4(&mut self) -> ID4_W<4> { + pub fn id4(&mut self) -> ID4_W { ID4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id5(&mut self) -> ID5_W<5> { + pub fn id5(&mut self) -> ID5_W { ID5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id6(&mut self) -> ID6_W<6> { + pub fn id6(&mut self) -> ID6_W { ID6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id7(&mut self) -> ID7_W<7> { + pub fn id7(&mut self) -> ID7_W { ID7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id8(&mut self) -> ID8_W<8> { + pub fn id8(&mut self) -> ID8_W { ID8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id9(&mut self) -> ID9_W<9> { + pub fn id9(&mut self) -> ID9_W { ID9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id10(&mut self) -> ID10_W<10> { + pub fn id10(&mut self) -> ID10_W { ID10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id11(&mut self) -> ID11_W<11> { + pub fn id11(&mut self) -> ID11_W { ID11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id12(&mut self) -> ID12_W<12> { + pub fn id12(&mut self) -> ID12_W { ID12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id13(&mut self) -> ID13_W<13> { + pub fn id13(&mut self) -> ID13_W { ID13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id14(&mut self) -> ID14_W<14> { + pub fn id14(&mut self) -> ID14_W { ID14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id15(&mut self) -> ID15_W<15> { + pub fn id15(&mut self) -> ID15_W { ID15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id16(&mut self) -> ID16_W<16> { + pub fn id16(&mut self) -> ID16_W { ID16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id17(&mut self) -> ID17_W<17> { + pub fn id17(&mut self) -> ID17_W { ID17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id18(&mut self) -> ID18_W<18> { + pub fn id18(&mut self) -> ID18_W { ID18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id19(&mut self) -> ID19_W<19> { + pub fn id19(&mut self) -> ID19_W { ID19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id20(&mut self) -> ID20_W<20> { + pub fn id20(&mut self) -> ID20_W { ID20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id21(&mut self) -> ID21_W<21> { + pub fn id21(&mut self) -> ID21_W { ID21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id22(&mut self) -> ID22_W<22> { + pub fn id22(&mut self) -> ID22_W { ID22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn id23(&mut self) -> ID23_W<23> { + pub fn id23(&mut self) -> ID23_W { ID23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gid](index.html) module"] +#[doc = "Global Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gid::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GID_SPEC; impl crate::RegisterSpec for GID_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gid::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gid::W`](W) writer structure"] impl crate::Writable for GID_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gie.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gie.rs index 832cca5c..cbc3904a 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gie.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gie.rs @@ -1,232 +1,212 @@ #[doc = "Register `GIE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `IE0` writer - XDMAC Channel 0 Interrupt Enable Bit"] -pub type IE0_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE1` writer - XDMAC Channel 1 Interrupt Enable Bit"] -pub type IE1_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE2` writer - XDMAC Channel 2 Interrupt Enable Bit"] -pub type IE2_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE3` writer - XDMAC Channel 3 Interrupt Enable Bit"] -pub type IE3_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE4` writer - XDMAC Channel 4 Interrupt Enable Bit"] -pub type IE4_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE5` writer - XDMAC Channel 5 Interrupt Enable Bit"] -pub type IE5_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE6` writer - XDMAC Channel 6 Interrupt Enable Bit"] -pub type IE6_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE7` writer - XDMAC Channel 7 Interrupt Enable Bit"] -pub type IE7_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE8` writer - XDMAC Channel 8 Interrupt Enable Bit"] -pub type IE8_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE9` writer - XDMAC Channel 9 Interrupt Enable Bit"] -pub type IE9_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE10` writer - XDMAC Channel 10 Interrupt Enable Bit"] -pub type IE10_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE11` writer - XDMAC Channel 11 Interrupt Enable Bit"] -pub type IE11_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE12` writer - XDMAC Channel 12 Interrupt Enable Bit"] -pub type IE12_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE13` writer - XDMAC Channel 13 Interrupt Enable Bit"] -pub type IE13_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE14` writer - XDMAC Channel 14 Interrupt Enable Bit"] -pub type IE14_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE15` writer - XDMAC Channel 15 Interrupt Enable Bit"] -pub type IE15_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE16` writer - XDMAC Channel 16 Interrupt Enable Bit"] -pub type IE16_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE17` writer - XDMAC Channel 17 Interrupt Enable Bit"] -pub type IE17_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE18` writer - XDMAC Channel 18 Interrupt Enable Bit"] -pub type IE18_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE19` writer - XDMAC Channel 19 Interrupt Enable Bit"] -pub type IE19_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE20` writer - XDMAC Channel 20 Interrupt Enable Bit"] -pub type IE20_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE21` writer - XDMAC Channel 21 Interrupt Enable Bit"] -pub type IE21_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE22` writer - XDMAC Channel 22 Interrupt Enable Bit"] -pub type IE22_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `IE23` writer - XDMAC Channel 23 Interrupt Enable Bit"] -pub type IE23_W<'a, const O: u8> = crate::BitWriter<'a, GIE_SPEC, O>; +pub type IE23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie0(&mut self) -> IE0_W<0> { + pub fn ie0(&mut self) -> IE0_W { IE0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie1(&mut self) -> IE1_W<1> { + pub fn ie1(&mut self) -> IE1_W { IE1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie2(&mut self) -> IE2_W<2> { + pub fn ie2(&mut self) -> IE2_W { IE2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie3(&mut self) -> IE3_W<3> { + pub fn ie3(&mut self) -> IE3_W { IE3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie4(&mut self) -> IE4_W<4> { + pub fn ie4(&mut self) -> IE4_W { IE4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie5(&mut self) -> IE5_W<5> { + pub fn ie5(&mut self) -> IE5_W { IE5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie6(&mut self) -> IE6_W<6> { + pub fn ie6(&mut self) -> IE6_W { IE6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie7(&mut self) -> IE7_W<7> { + pub fn ie7(&mut self) -> IE7_W { IE7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie8(&mut self) -> IE8_W<8> { + pub fn ie8(&mut self) -> IE8_W { IE8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie9(&mut self) -> IE9_W<9> { + pub fn ie9(&mut self) -> IE9_W { IE9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie10(&mut self) -> IE10_W<10> { + pub fn ie10(&mut self) -> IE10_W { IE10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie11(&mut self) -> IE11_W<11> { + pub fn ie11(&mut self) -> IE11_W { IE11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie12(&mut self) -> IE12_W<12> { + pub fn ie12(&mut self) -> IE12_W { IE12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie13(&mut self) -> IE13_W<13> { + pub fn ie13(&mut self) -> IE13_W { IE13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie14(&mut self) -> IE14_W<14> { + pub fn ie14(&mut self) -> IE14_W { IE14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie15(&mut self) -> IE15_W<15> { + pub fn ie15(&mut self) -> IE15_W { IE15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie16(&mut self) -> IE16_W<16> { + pub fn ie16(&mut self) -> IE16_W { IE16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie17(&mut self) -> IE17_W<17> { + pub fn ie17(&mut self) -> IE17_W { IE17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie18(&mut self) -> IE18_W<18> { + pub fn ie18(&mut self) -> IE18_W { IE18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie19(&mut self) -> IE19_W<19> { + pub fn ie19(&mut self) -> IE19_W { IE19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie20(&mut self) -> IE20_W<20> { + pub fn ie20(&mut self) -> IE20_W { IE20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie21(&mut self) -> IE21_W<21> { + pub fn ie21(&mut self) -> IE21_W { IE21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie22(&mut self) -> IE22_W<22> { + pub fn ie22(&mut self) -> IE22_W { IE22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn ie23(&mut self) -> IE23_W<23> { + pub fn ie23(&mut self) -> IE23_W { IE23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gie](index.html) module"] +#[doc = "Global Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gie::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GIE_SPEC; impl crate::RegisterSpec for GIE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gie::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gie::W`](W) writer structure"] impl crate::Writable for GIE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gim.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gim.rs index 2a56b980..eeef74f5 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gim.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gim.rs @@ -1,18 +1,5 @@ #[doc = "Register `GIM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IM0` reader - XDMAC Channel 0 Interrupt Mask Bit"] pub type IM0_R = crate::BitReader; #[doc = "Field `IM1` reader - XDMAC Channel 1 Interrupt Mask Bit"] @@ -183,15 +170,13 @@ impl R { IM23_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "Global Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gim](index.html) module"] +#[doc = "Global Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gim::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GIM_SPEC; impl crate::RegisterSpec for GIM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gim::R](R) reader structure"] -impl crate::Readable for GIM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gim::R`](R) reader structure"] +impl crate::Readable for GIM_SPEC {} #[doc = "`reset()` method sets GIM to value 0"] impl crate::Resettable for GIM_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gis.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gis.rs index ae28c4fd..099d5ef8 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gis.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gis.rs @@ -1,18 +1,5 @@ #[doc = "Register `GIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `IS0` reader - XDMAC Channel 0 Interrupt Status Bit"] pub type IS0_R = crate::BitReader; #[doc = "Field `IS1` reader - XDMAC Channel 1 Interrupt Status Bit"] @@ -183,15 +170,13 @@ impl R { IS23_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "Global Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gis](index.html) module"] +#[doc = "Global Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GIS_SPEC; impl crate::RegisterSpec for GIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gis::R](R) reader structure"] -impl crate::Readable for GIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gis::R`](R) reader structure"] +impl crate::Readable for GIS_SPEC {} #[doc = "`reset()` method sets GIS to value 0"] impl crate::Resettable for GIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/grs.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/grs.rs index e287f666..0c58e973 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/grs.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/grs.rs @@ -1,135 +1,103 @@ #[doc = "Register `GRS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GRS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RS0` reader - XDMAC Channel 0 Read Suspend Bit"] pub type RS0_R = crate::BitReader; #[doc = "Field `RS0` writer - XDMAC Channel 0 Read Suspend Bit"] -pub type RS0_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS1` reader - XDMAC Channel 1 Read Suspend Bit"] pub type RS1_R = crate::BitReader; #[doc = "Field `RS1` writer - XDMAC Channel 1 Read Suspend Bit"] -pub type RS1_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS2` reader - XDMAC Channel 2 Read Suspend Bit"] pub type RS2_R = crate::BitReader; #[doc = "Field `RS2` writer - XDMAC Channel 2 Read Suspend Bit"] -pub type RS2_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS3` reader - XDMAC Channel 3 Read Suspend Bit"] pub type RS3_R = crate::BitReader; #[doc = "Field `RS3` writer - XDMAC Channel 3 Read Suspend Bit"] -pub type RS3_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS4` reader - XDMAC Channel 4 Read Suspend Bit"] pub type RS4_R = crate::BitReader; #[doc = "Field `RS4` writer - XDMAC Channel 4 Read Suspend Bit"] -pub type RS4_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS5` reader - XDMAC Channel 5 Read Suspend Bit"] pub type RS5_R = crate::BitReader; #[doc = "Field `RS5` writer - XDMAC Channel 5 Read Suspend Bit"] -pub type RS5_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS6` reader - XDMAC Channel 6 Read Suspend Bit"] pub type RS6_R = crate::BitReader; #[doc = "Field `RS6` writer - XDMAC Channel 6 Read Suspend Bit"] -pub type RS6_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS7` reader - XDMAC Channel 7 Read Suspend Bit"] pub type RS7_R = crate::BitReader; #[doc = "Field `RS7` writer - XDMAC Channel 7 Read Suspend Bit"] -pub type RS7_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS8` reader - XDMAC Channel 8 Read Suspend Bit"] pub type RS8_R = crate::BitReader; #[doc = "Field `RS8` writer - XDMAC Channel 8 Read Suspend Bit"] -pub type RS8_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS9` reader - XDMAC Channel 9 Read Suspend Bit"] pub type RS9_R = crate::BitReader; #[doc = "Field `RS9` writer - XDMAC Channel 9 Read Suspend Bit"] -pub type RS9_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS10` reader - XDMAC Channel 10 Read Suspend Bit"] pub type RS10_R = crate::BitReader; #[doc = "Field `RS10` writer - XDMAC Channel 10 Read Suspend Bit"] -pub type RS10_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS11` reader - XDMAC Channel 11 Read Suspend Bit"] pub type RS11_R = crate::BitReader; #[doc = "Field `RS11` writer - XDMAC Channel 11 Read Suspend Bit"] -pub type RS11_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS12` reader - XDMAC Channel 12 Read Suspend Bit"] pub type RS12_R = crate::BitReader; #[doc = "Field `RS12` writer - XDMAC Channel 12 Read Suspend Bit"] -pub type RS12_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS13` reader - XDMAC Channel 13 Read Suspend Bit"] pub type RS13_R = crate::BitReader; #[doc = "Field `RS13` writer - XDMAC Channel 13 Read Suspend Bit"] -pub type RS13_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS14` reader - XDMAC Channel 14 Read Suspend Bit"] pub type RS14_R = crate::BitReader; #[doc = "Field `RS14` writer - XDMAC Channel 14 Read Suspend Bit"] -pub type RS14_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS15` reader - XDMAC Channel 15 Read Suspend Bit"] pub type RS15_R = crate::BitReader; #[doc = "Field `RS15` writer - XDMAC Channel 15 Read Suspend Bit"] -pub type RS15_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS16` reader - XDMAC Channel 16 Read Suspend Bit"] pub type RS16_R = crate::BitReader; #[doc = "Field `RS16` writer - XDMAC Channel 16 Read Suspend Bit"] -pub type RS16_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS17` reader - XDMAC Channel 17 Read Suspend Bit"] pub type RS17_R = crate::BitReader; #[doc = "Field `RS17` writer - XDMAC Channel 17 Read Suspend Bit"] -pub type RS17_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS18` reader - XDMAC Channel 18 Read Suspend Bit"] pub type RS18_R = crate::BitReader; #[doc = "Field `RS18` writer - XDMAC Channel 18 Read Suspend Bit"] -pub type RS18_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS19` reader - XDMAC Channel 19 Read Suspend Bit"] pub type RS19_R = crate::BitReader; #[doc = "Field `RS19` writer - XDMAC Channel 19 Read Suspend Bit"] -pub type RS19_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS20` reader - XDMAC Channel 20 Read Suspend Bit"] pub type RS20_R = crate::BitReader; #[doc = "Field `RS20` writer - XDMAC Channel 20 Read Suspend Bit"] -pub type RS20_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS21` reader - XDMAC Channel 21 Read Suspend Bit"] pub type RS21_R = crate::BitReader; #[doc = "Field `RS21` writer - XDMAC Channel 21 Read Suspend Bit"] -pub type RS21_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS22` reader - XDMAC Channel 22 Read Suspend Bit"] pub type RS22_R = crate::BitReader; #[doc = "Field `RS22` writer - XDMAC Channel 22 Read Suspend Bit"] -pub type RS22_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RS23` reader - XDMAC Channel 23 Read Suspend Bit"] pub type RS23_R = crate::BitReader; #[doc = "Field `RS23` writer - XDMAC Channel 23 Read Suspend Bit"] -pub type RS23_W<'a, const O: u8> = crate::BitWriter<'a, GRS_SPEC, O>; +pub type RS23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - XDMAC Channel 0 Read Suspend Bit"] #[inline(always)] @@ -256,166 +224,163 @@ impl W { #[doc = "Bit 0 - XDMAC Channel 0 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs0(&mut self) -> RS0_W<0> { + pub fn rs0(&mut self) -> RS0_W { RS0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs1(&mut self) -> RS1_W<1> { + pub fn rs1(&mut self) -> RS1_W { RS1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs2(&mut self) -> RS2_W<2> { + pub fn rs2(&mut self) -> RS2_W { RS2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs3(&mut self) -> RS3_W<3> { + pub fn rs3(&mut self) -> RS3_W { RS3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs4(&mut self) -> RS4_W<4> { + pub fn rs4(&mut self) -> RS4_W { RS4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs5(&mut self) -> RS5_W<5> { + pub fn rs5(&mut self) -> RS5_W { RS5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs6(&mut self) -> RS6_W<6> { + pub fn rs6(&mut self) -> RS6_W { RS6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs7(&mut self) -> RS7_W<7> { + pub fn rs7(&mut self) -> RS7_W { RS7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs8(&mut self) -> RS8_W<8> { + pub fn rs8(&mut self) -> RS8_W { RS8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs9(&mut self) -> RS9_W<9> { + pub fn rs9(&mut self) -> RS9_W { RS9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs10(&mut self) -> RS10_W<10> { + pub fn rs10(&mut self) -> RS10_W { RS10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs11(&mut self) -> RS11_W<11> { + pub fn rs11(&mut self) -> RS11_W { RS11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs12(&mut self) -> RS12_W<12> { + pub fn rs12(&mut self) -> RS12_W { RS12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs13(&mut self) -> RS13_W<13> { + pub fn rs13(&mut self) -> RS13_W { RS13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs14(&mut self) -> RS14_W<14> { + pub fn rs14(&mut self) -> RS14_W { RS14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs15(&mut self) -> RS15_W<15> { + pub fn rs15(&mut self) -> RS15_W { RS15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs16(&mut self) -> RS16_W<16> { + pub fn rs16(&mut self) -> RS16_W { RS16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs17(&mut self) -> RS17_W<17> { + pub fn rs17(&mut self) -> RS17_W { RS17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs18(&mut self) -> RS18_W<18> { + pub fn rs18(&mut self) -> RS18_W { RS18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs19(&mut self) -> RS19_W<19> { + pub fn rs19(&mut self) -> RS19_W { RS19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs20(&mut self) -> RS20_W<20> { + pub fn rs20(&mut self) -> RS20_W { RS20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs21(&mut self) -> RS21_W<21> { + pub fn rs21(&mut self) -> RS21_W { RS21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs22(&mut self) -> RS22_W<22> { + pub fn rs22(&mut self) -> RS22_W { RS22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Read Suspend Bit"] #[inline(always)] #[must_use] - pub fn rs23(&mut self) -> RS23_W<23> { + pub fn rs23(&mut self) -> RS23_W { RS23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Read Suspend Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grs](index.html) module"] +#[doc = "Global Channel Read Suspend Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`grs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRS_SPEC; impl crate::RegisterSpec for GRS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [grs::R](R) reader structure"] -impl crate::Readable for GRS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [grs::W](W) writer structure"] +#[doc = "`read()` method returns [`grs::R`](R) reader structure"] +impl crate::Readable for GRS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`grs::W`](W) writer structure"] impl crate::Writable for GRS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/grwr.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/grwr.rs index 61492a68..9b85dd81 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/grwr.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/grwr.rs @@ -1,232 +1,212 @@ #[doc = "Register `GRWR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RWR0` writer - XDMAC Channel 0 Read Write Resume Bit"] -pub type RWR0_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR1` writer - XDMAC Channel 1 Read Write Resume Bit"] -pub type RWR1_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR2` writer - XDMAC Channel 2 Read Write Resume Bit"] -pub type RWR2_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR3` writer - XDMAC Channel 3 Read Write Resume Bit"] -pub type RWR3_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR4` writer - XDMAC Channel 4 Read Write Resume Bit"] -pub type RWR4_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR5` writer - XDMAC Channel 5 Read Write Resume Bit"] -pub type RWR5_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR6` writer - XDMAC Channel 6 Read Write Resume Bit"] -pub type RWR6_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR7` writer - XDMAC Channel 7 Read Write Resume Bit"] -pub type RWR7_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR8` writer - XDMAC Channel 8 Read Write Resume Bit"] -pub type RWR8_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR9` writer - XDMAC Channel 9 Read Write Resume Bit"] -pub type RWR9_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR10` writer - XDMAC Channel 10 Read Write Resume Bit"] -pub type RWR10_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR11` writer - XDMAC Channel 11 Read Write Resume Bit"] -pub type RWR11_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR12` writer - XDMAC Channel 12 Read Write Resume Bit"] -pub type RWR12_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR13` writer - XDMAC Channel 13 Read Write Resume Bit"] -pub type RWR13_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR14` writer - XDMAC Channel 14 Read Write Resume Bit"] -pub type RWR14_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR15` writer - XDMAC Channel 15 Read Write Resume Bit"] -pub type RWR15_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR16` writer - XDMAC Channel 16 Read Write Resume Bit"] -pub type RWR16_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR17` writer - XDMAC Channel 17 Read Write Resume Bit"] -pub type RWR17_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR18` writer - XDMAC Channel 18 Read Write Resume Bit"] -pub type RWR18_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR19` writer - XDMAC Channel 19 Read Write Resume Bit"] -pub type RWR19_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR20` writer - XDMAC Channel 20 Read Write Resume Bit"] -pub type RWR20_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR21` writer - XDMAC Channel 21 Read Write Resume Bit"] -pub type RWR21_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR22` writer - XDMAC Channel 22 Read Write Resume Bit"] -pub type RWR22_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWR23` writer - XDMAC Channel 23 Read Write Resume Bit"] -pub type RWR23_W<'a, const O: u8> = crate::BitWriter<'a, GRWR_SPEC, O>; +pub type RWR23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr0(&mut self) -> RWR0_W<0> { + pub fn rwr0(&mut self) -> RWR0_W { RWR0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr1(&mut self) -> RWR1_W<1> { + pub fn rwr1(&mut self) -> RWR1_W { RWR1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr2(&mut self) -> RWR2_W<2> { + pub fn rwr2(&mut self) -> RWR2_W { RWR2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr3(&mut self) -> RWR3_W<3> { + pub fn rwr3(&mut self) -> RWR3_W { RWR3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr4(&mut self) -> RWR4_W<4> { + pub fn rwr4(&mut self) -> RWR4_W { RWR4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr5(&mut self) -> RWR5_W<5> { + pub fn rwr5(&mut self) -> RWR5_W { RWR5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr6(&mut self) -> RWR6_W<6> { + pub fn rwr6(&mut self) -> RWR6_W { RWR6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr7(&mut self) -> RWR7_W<7> { + pub fn rwr7(&mut self) -> RWR7_W { RWR7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr8(&mut self) -> RWR8_W<8> { + pub fn rwr8(&mut self) -> RWR8_W { RWR8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr9(&mut self) -> RWR9_W<9> { + pub fn rwr9(&mut self) -> RWR9_W { RWR9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr10(&mut self) -> RWR10_W<10> { + pub fn rwr10(&mut self) -> RWR10_W { RWR10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr11(&mut self) -> RWR11_W<11> { + pub fn rwr11(&mut self) -> RWR11_W { RWR11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr12(&mut self) -> RWR12_W<12> { + pub fn rwr12(&mut self) -> RWR12_W { RWR12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr13(&mut self) -> RWR13_W<13> { + pub fn rwr13(&mut self) -> RWR13_W { RWR13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr14(&mut self) -> RWR14_W<14> { + pub fn rwr14(&mut self) -> RWR14_W { RWR14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr15(&mut self) -> RWR15_W<15> { + pub fn rwr15(&mut self) -> RWR15_W { RWR15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr16(&mut self) -> RWR16_W<16> { + pub fn rwr16(&mut self) -> RWR16_W { RWR16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr17(&mut self) -> RWR17_W<17> { + pub fn rwr17(&mut self) -> RWR17_W { RWR17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr18(&mut self) -> RWR18_W<18> { + pub fn rwr18(&mut self) -> RWR18_W { RWR18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr19(&mut self) -> RWR19_W<19> { + pub fn rwr19(&mut self) -> RWR19_W { RWR19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr20(&mut self) -> RWR20_W<20> { + pub fn rwr20(&mut self) -> RWR20_W { RWR20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr21(&mut self) -> RWR21_W<21> { + pub fn rwr21(&mut self) -> RWR21_W { RWR21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr22(&mut self) -> RWR22_W<22> { + pub fn rwr22(&mut self) -> RWR22_W { RWR22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Read Write Resume Bit"] #[inline(always)] #[must_use] - pub fn rwr23(&mut self) -> RWR23_W<23> { + pub fn rwr23(&mut self) -> RWR23_W { RWR23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Read Write Resume Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grwr](index.html) module"] +#[doc = "Global Channel Read Write Resume Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grwr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRWR_SPEC; impl crate::RegisterSpec for GRWR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [grwr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`grwr::W`](W) writer structure"] impl crate::Writable for GRWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/grws.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/grws.rs index d36a28b4..2445c06a 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/grws.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/grws.rs @@ -1,232 +1,212 @@ #[doc = "Register `GRWS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `RWS0` writer - XDMAC Channel 0 Read Write Suspend Bit"] -pub type RWS0_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS1` writer - XDMAC Channel 1 Read Write Suspend Bit"] -pub type RWS1_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS2` writer - XDMAC Channel 2 Read Write Suspend Bit"] -pub type RWS2_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS3` writer - XDMAC Channel 3 Read Write Suspend Bit"] -pub type RWS3_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS4` writer - XDMAC Channel 4 Read Write Suspend Bit"] -pub type RWS4_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS5` writer - XDMAC Channel 5 Read Write Suspend Bit"] -pub type RWS5_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS6` writer - XDMAC Channel 6 Read Write Suspend Bit"] -pub type RWS6_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS7` writer - XDMAC Channel 7 Read Write Suspend Bit"] -pub type RWS7_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS8` writer - XDMAC Channel 8 Read Write Suspend Bit"] -pub type RWS8_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS9` writer - XDMAC Channel 9 Read Write Suspend Bit"] -pub type RWS9_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS10` writer - XDMAC Channel 10 Read Write Suspend Bit"] -pub type RWS10_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS11` writer - XDMAC Channel 11 Read Write Suspend Bit"] -pub type RWS11_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS12` writer - XDMAC Channel 12 Read Write Suspend Bit"] -pub type RWS12_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS13` writer - XDMAC Channel 13 Read Write Suspend Bit"] -pub type RWS13_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS14` writer - XDMAC Channel 14 Read Write Suspend Bit"] -pub type RWS14_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS15` writer - XDMAC Channel 15 Read Write Suspend Bit"] -pub type RWS15_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS16` writer - XDMAC Channel 16 Read Write Suspend Bit"] -pub type RWS16_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS17` writer - XDMAC Channel 17 Read Write Suspend Bit"] -pub type RWS17_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS18` writer - XDMAC Channel 18 Read Write Suspend Bit"] -pub type RWS18_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS19` writer - XDMAC Channel 19 Read Write Suspend Bit"] -pub type RWS19_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS20` writer - XDMAC Channel 20 Read Write Suspend Bit"] -pub type RWS20_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS21` writer - XDMAC Channel 21 Read Write Suspend Bit"] -pub type RWS21_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS22` writer - XDMAC Channel 22 Read Write Suspend Bit"] -pub type RWS22_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RWS23` writer - XDMAC Channel 23 Read Write Suspend Bit"] -pub type RWS23_W<'a, const O: u8> = crate::BitWriter<'a, GRWS_SPEC, O>; +pub type RWS23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws0(&mut self) -> RWS0_W<0> { + pub fn rws0(&mut self) -> RWS0_W { RWS0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws1(&mut self) -> RWS1_W<1> { + pub fn rws1(&mut self) -> RWS1_W { RWS1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws2(&mut self) -> RWS2_W<2> { + pub fn rws2(&mut self) -> RWS2_W { RWS2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws3(&mut self) -> RWS3_W<3> { + pub fn rws3(&mut self) -> RWS3_W { RWS3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws4(&mut self) -> RWS4_W<4> { + pub fn rws4(&mut self) -> RWS4_W { RWS4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws5(&mut self) -> RWS5_W<5> { + pub fn rws5(&mut self) -> RWS5_W { RWS5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws6(&mut self) -> RWS6_W<6> { + pub fn rws6(&mut self) -> RWS6_W { RWS6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws7(&mut self) -> RWS7_W<7> { + pub fn rws7(&mut self) -> RWS7_W { RWS7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws8(&mut self) -> RWS8_W<8> { + pub fn rws8(&mut self) -> RWS8_W { RWS8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws9(&mut self) -> RWS9_W<9> { + pub fn rws9(&mut self) -> RWS9_W { RWS9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws10(&mut self) -> RWS10_W<10> { + pub fn rws10(&mut self) -> RWS10_W { RWS10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws11(&mut self) -> RWS11_W<11> { + pub fn rws11(&mut self) -> RWS11_W { RWS11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws12(&mut self) -> RWS12_W<12> { + pub fn rws12(&mut self) -> RWS12_W { RWS12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws13(&mut self) -> RWS13_W<13> { + pub fn rws13(&mut self) -> RWS13_W { RWS13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws14(&mut self) -> RWS14_W<14> { + pub fn rws14(&mut self) -> RWS14_W { RWS14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws15(&mut self) -> RWS15_W<15> { + pub fn rws15(&mut self) -> RWS15_W { RWS15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws16(&mut self) -> RWS16_W<16> { + pub fn rws16(&mut self) -> RWS16_W { RWS16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws17(&mut self) -> RWS17_W<17> { + pub fn rws17(&mut self) -> RWS17_W { RWS17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws18(&mut self) -> RWS18_W<18> { + pub fn rws18(&mut self) -> RWS18_W { RWS18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws19(&mut self) -> RWS19_W<19> { + pub fn rws19(&mut self) -> RWS19_W { RWS19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws20(&mut self) -> RWS20_W<20> { + pub fn rws20(&mut self) -> RWS20_W { RWS20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws21(&mut self) -> RWS21_W<21> { + pub fn rws21(&mut self) -> RWS21_W { RWS21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws22(&mut self) -> RWS22_W<22> { + pub fn rws22(&mut self) -> RWS22_W { RWS22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Read Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn rws23(&mut self) -> RWS23_W<23> { + pub fn rws23(&mut self) -> RWS23_W { RWS23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Read Write Suspend Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [grws](index.html) module"] +#[doc = "Global Channel Read Write Suspend Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`grws::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GRWS_SPEC; impl crate::RegisterSpec for GRWS_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [grws::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`grws::W`](W) writer structure"] impl crate::Writable for GRWS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gs.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gs.rs index 800ff0c8..c0c5752e 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gs.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gs.rs @@ -1,18 +1,5 @@ #[doc = "Register `GS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `ST0` reader - XDMAC Channel 0 Status Bit"] pub type ST0_R = crate::BitReader; #[doc = "Field `ST1` reader - XDMAC Channel 1 Status Bit"] @@ -183,15 +170,13 @@ impl R { ST23_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "Global Channel Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gs](index.html) module"] +#[doc = "Global Channel Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gs::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GS_SPEC; impl crate::RegisterSpec for GS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gs::R](R) reader structure"] -impl crate::Readable for GS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gs::R`](R) reader structure"] +impl crate::Readable for GS_SPEC {} #[doc = "`reset()` method sets GS to value 0"] impl crate::Resettable for GS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gswf.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gswf.rs index 8d7dfa3d..09a206c5 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gswf.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gswf.rs @@ -1,232 +1,212 @@ #[doc = "Register `GSWF` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWF0` writer - XDMAC Channel 0 Software Flush Request Bit"] -pub type SWF0_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF1` writer - XDMAC Channel 1 Software Flush Request Bit"] -pub type SWF1_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF2` writer - XDMAC Channel 2 Software Flush Request Bit"] -pub type SWF2_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF3` writer - XDMAC Channel 3 Software Flush Request Bit"] -pub type SWF3_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF4` writer - XDMAC Channel 4 Software Flush Request Bit"] -pub type SWF4_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF5` writer - XDMAC Channel 5 Software Flush Request Bit"] -pub type SWF5_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF6` writer - XDMAC Channel 6 Software Flush Request Bit"] -pub type SWF6_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF7` writer - XDMAC Channel 7 Software Flush Request Bit"] -pub type SWF7_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF8` writer - XDMAC Channel 8 Software Flush Request Bit"] -pub type SWF8_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF9` writer - XDMAC Channel 9 Software Flush Request Bit"] -pub type SWF9_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF10` writer - XDMAC Channel 10 Software Flush Request Bit"] -pub type SWF10_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF11` writer - XDMAC Channel 11 Software Flush Request Bit"] -pub type SWF11_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF12` writer - XDMAC Channel 12 Software Flush Request Bit"] -pub type SWF12_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF13` writer - XDMAC Channel 13 Software Flush Request Bit"] -pub type SWF13_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF14` writer - XDMAC Channel 14 Software Flush Request Bit"] -pub type SWF14_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF15` writer - XDMAC Channel 15 Software Flush Request Bit"] -pub type SWF15_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF16` writer - XDMAC Channel 16 Software Flush Request Bit"] -pub type SWF16_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF17` writer - XDMAC Channel 17 Software Flush Request Bit"] -pub type SWF17_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF18` writer - XDMAC Channel 18 Software Flush Request Bit"] -pub type SWF18_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF19` writer - XDMAC Channel 19 Software Flush Request Bit"] -pub type SWF19_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF20` writer - XDMAC Channel 20 Software Flush Request Bit"] -pub type SWF20_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF21` writer - XDMAC Channel 21 Software Flush Request Bit"] -pub type SWF21_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF22` writer - XDMAC Channel 22 Software Flush Request Bit"] -pub type SWF22_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWF23` writer - XDMAC Channel 23 Software Flush Request Bit"] -pub type SWF23_W<'a, const O: u8> = crate::BitWriter<'a, GSWF_SPEC, O>; +pub type SWF23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf0(&mut self) -> SWF0_W<0> { + pub fn swf0(&mut self) -> SWF0_W { SWF0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf1(&mut self) -> SWF1_W<1> { + pub fn swf1(&mut self) -> SWF1_W { SWF1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf2(&mut self) -> SWF2_W<2> { + pub fn swf2(&mut self) -> SWF2_W { SWF2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf3(&mut self) -> SWF3_W<3> { + pub fn swf3(&mut self) -> SWF3_W { SWF3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf4(&mut self) -> SWF4_W<4> { + pub fn swf4(&mut self) -> SWF4_W { SWF4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf5(&mut self) -> SWF5_W<5> { + pub fn swf5(&mut self) -> SWF5_W { SWF5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf6(&mut self) -> SWF6_W<6> { + pub fn swf6(&mut self) -> SWF6_W { SWF6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf7(&mut self) -> SWF7_W<7> { + pub fn swf7(&mut self) -> SWF7_W { SWF7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf8(&mut self) -> SWF8_W<8> { + pub fn swf8(&mut self) -> SWF8_W { SWF8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf9(&mut self) -> SWF9_W<9> { + pub fn swf9(&mut self) -> SWF9_W { SWF9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf10(&mut self) -> SWF10_W<10> { + pub fn swf10(&mut self) -> SWF10_W { SWF10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf11(&mut self) -> SWF11_W<11> { + pub fn swf11(&mut self) -> SWF11_W { SWF11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf12(&mut self) -> SWF12_W<12> { + pub fn swf12(&mut self) -> SWF12_W { SWF12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf13(&mut self) -> SWF13_W<13> { + pub fn swf13(&mut self) -> SWF13_W { SWF13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf14(&mut self) -> SWF14_W<14> { + pub fn swf14(&mut self) -> SWF14_W { SWF14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf15(&mut self) -> SWF15_W<15> { + pub fn swf15(&mut self) -> SWF15_W { SWF15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf16(&mut self) -> SWF16_W<16> { + pub fn swf16(&mut self) -> SWF16_W { SWF16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf17(&mut self) -> SWF17_W<17> { + pub fn swf17(&mut self) -> SWF17_W { SWF17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf18(&mut self) -> SWF18_W<18> { + pub fn swf18(&mut self) -> SWF18_W { SWF18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf19(&mut self) -> SWF19_W<19> { + pub fn swf19(&mut self) -> SWF19_W { SWF19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf20(&mut self) -> SWF20_W<20> { + pub fn swf20(&mut self) -> SWF20_W { SWF20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf21(&mut self) -> SWF21_W<21> { + pub fn swf21(&mut self) -> SWF21_W { SWF21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf22(&mut self) -> SWF22_W<22> { + pub fn swf22(&mut self) -> SWF22_W { SWF22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Software Flush Request Bit"] #[inline(always)] #[must_use] - pub fn swf23(&mut self) -> SWF23_W<23> { + pub fn swf23(&mut self) -> SWF23_W { SWF23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Software Flush Request Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gswf](index.html) module"] +#[doc = "Global Channel Software Flush Request Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gswf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GSWF_SPEC; impl crate::RegisterSpec for GSWF_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gswf::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gswf::W`](W) writer structure"] impl crate::Writable for GSWF_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gswr.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gswr.rs index 8abd0bf0..99836e3f 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gswr.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gswr.rs @@ -1,232 +1,212 @@ #[doc = "Register `GSWR` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SWREQ0` writer - XDMAC Channel 0 Software Request Bit"] -pub type SWREQ0_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ1` writer - XDMAC Channel 1 Software Request Bit"] -pub type SWREQ1_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ2` writer - XDMAC Channel 2 Software Request Bit"] -pub type SWREQ2_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ3` writer - XDMAC Channel 3 Software Request Bit"] -pub type SWREQ3_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ4` writer - XDMAC Channel 4 Software Request Bit"] -pub type SWREQ4_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ5` writer - XDMAC Channel 5 Software Request Bit"] -pub type SWREQ5_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ6` writer - XDMAC Channel 6 Software Request Bit"] -pub type SWREQ6_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ7` writer - XDMAC Channel 7 Software Request Bit"] -pub type SWREQ7_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ8` writer - XDMAC Channel 8 Software Request Bit"] -pub type SWREQ8_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ9` writer - XDMAC Channel 9 Software Request Bit"] -pub type SWREQ9_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ10` writer - XDMAC Channel 10 Software Request Bit"] -pub type SWREQ10_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ11` writer - XDMAC Channel 11 Software Request Bit"] -pub type SWREQ11_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ12` writer - XDMAC Channel 12 Software Request Bit"] -pub type SWREQ12_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ13` writer - XDMAC Channel 13 Software Request Bit"] -pub type SWREQ13_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ14` writer - XDMAC Channel 14 Software Request Bit"] -pub type SWREQ14_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ15` writer - XDMAC Channel 15 Software Request Bit"] -pub type SWREQ15_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ16` writer - XDMAC Channel 16 Software Request Bit"] -pub type SWREQ16_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ17` writer - XDMAC Channel 17 Software Request Bit"] -pub type SWREQ17_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ18` writer - XDMAC Channel 18 Software Request Bit"] -pub type SWREQ18_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ19` writer - XDMAC Channel 19 Software Request Bit"] -pub type SWREQ19_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ20` writer - XDMAC Channel 20 Software Request Bit"] -pub type SWREQ20_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ21` writer - XDMAC Channel 21 Software Request Bit"] -pub type SWREQ21_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ22` writer - XDMAC Channel 22 Software Request Bit"] -pub type SWREQ22_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `SWREQ23` writer - XDMAC Channel 23 Software Request Bit"] -pub type SWREQ23_W<'a, const O: u8> = crate::BitWriter<'a, GSWR_SPEC, O>; +pub type SWREQ23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - XDMAC Channel 0 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq0(&mut self) -> SWREQ0_W<0> { + pub fn swreq0(&mut self) -> SWREQ0_W { SWREQ0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq1(&mut self) -> SWREQ1_W<1> { + pub fn swreq1(&mut self) -> SWREQ1_W { SWREQ1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq2(&mut self) -> SWREQ2_W<2> { + pub fn swreq2(&mut self) -> SWREQ2_W { SWREQ2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq3(&mut self) -> SWREQ3_W<3> { + pub fn swreq3(&mut self) -> SWREQ3_W { SWREQ3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq4(&mut self) -> SWREQ4_W<4> { + pub fn swreq4(&mut self) -> SWREQ4_W { SWREQ4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq5(&mut self) -> SWREQ5_W<5> { + pub fn swreq5(&mut self) -> SWREQ5_W { SWREQ5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq6(&mut self) -> SWREQ6_W<6> { + pub fn swreq6(&mut self) -> SWREQ6_W { SWREQ6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq7(&mut self) -> SWREQ7_W<7> { + pub fn swreq7(&mut self) -> SWREQ7_W { SWREQ7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq8(&mut self) -> SWREQ8_W<8> { + pub fn swreq8(&mut self) -> SWREQ8_W { SWREQ8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq9(&mut self) -> SWREQ9_W<9> { + pub fn swreq9(&mut self) -> SWREQ9_W { SWREQ9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq10(&mut self) -> SWREQ10_W<10> { + pub fn swreq10(&mut self) -> SWREQ10_W { SWREQ10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq11(&mut self) -> SWREQ11_W<11> { + pub fn swreq11(&mut self) -> SWREQ11_W { SWREQ11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq12(&mut self) -> SWREQ12_W<12> { + pub fn swreq12(&mut self) -> SWREQ12_W { SWREQ12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq13(&mut self) -> SWREQ13_W<13> { + pub fn swreq13(&mut self) -> SWREQ13_W { SWREQ13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq14(&mut self) -> SWREQ14_W<14> { + pub fn swreq14(&mut self) -> SWREQ14_W { SWREQ14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq15(&mut self) -> SWREQ15_W<15> { + pub fn swreq15(&mut self) -> SWREQ15_W { SWREQ15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq16(&mut self) -> SWREQ16_W<16> { + pub fn swreq16(&mut self) -> SWREQ16_W { SWREQ16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq17(&mut self) -> SWREQ17_W<17> { + pub fn swreq17(&mut self) -> SWREQ17_W { SWREQ17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq18(&mut self) -> SWREQ18_W<18> { + pub fn swreq18(&mut self) -> SWREQ18_W { SWREQ18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq19(&mut self) -> SWREQ19_W<19> { + pub fn swreq19(&mut self) -> SWREQ19_W { SWREQ19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq20(&mut self) -> SWREQ20_W<20> { + pub fn swreq20(&mut self) -> SWREQ20_W { SWREQ20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq21(&mut self) -> SWREQ21_W<21> { + pub fn swreq21(&mut self) -> SWREQ21_W { SWREQ21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq22(&mut self) -> SWREQ22_W<22> { + pub fn swreq22(&mut self) -> SWREQ22_W { SWREQ22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Software Request Bit"] #[inline(always)] #[must_use] - pub fn swreq23(&mut self) -> SWREQ23_W<23> { + pub fn swreq23(&mut self) -> SWREQ23_W { SWREQ23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Software Request Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gswr](index.html) module"] +#[doc = "Global Channel Software Request Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gswr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GSWR_SPEC; impl crate::RegisterSpec for GSWR_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [gswr::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`gswr::W`](W) writer structure"] impl crate::Writable for GSWR_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gsws.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gsws.rs index 91fc4adf..d740d192 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gsws.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gsws.rs @@ -1,18 +1,5 @@ #[doc = "Register `GSWS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `SWRS0` reader - XDMAC Channel 0 Software Request Status Bit"] pub type SWRS0_R = crate::BitReader; #[doc = "Field `SWRS1` reader - XDMAC Channel 1 Software Request Status Bit"] @@ -183,15 +170,13 @@ impl R { SWRS23_R::new(((self.bits >> 23) & 1) != 0) } } -#[doc = "Global Channel Software Request Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gsws](index.html) module"] +#[doc = "Global Channel Software Request Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gsws::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GSWS_SPEC; impl crate::RegisterSpec for GSWS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gsws::R](R) reader structure"] -impl crate::Readable for GSWS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gsws::R`](R) reader structure"] +impl crate::Readable for GSWS_SPEC {} #[doc = "`reset()` method sets GSWS to value 0"] impl crate::Resettable for GSWS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gtype.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gtype.rs index d6a5274a..a35cfd38 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gtype.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gtype.rs @@ -1,18 +1,5 @@ #[doc = "Register `GTYPE` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `NB_CH` reader - Number of Channels Minus One"] pub type NB_CH_R = crate::FieldReader; #[doc = "Field `FIFO_SZ` reader - Number of Bytes"] @@ -36,15 +23,13 @@ impl R { NB_REQ_R::new(((self.bits >> 16) & 0x7f) as u8) } } -#[doc = "Global Type Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gtype](index.html) module"] +#[doc = "Global Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gtype::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GTYPE_SPEC; impl crate::RegisterSpec for GTYPE_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gtype::R](R) reader structure"] -impl crate::Readable for GTYPE_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`gtype::R`](R) reader structure"] +impl crate::Readable for GTYPE_SPEC {} #[doc = "`reset()` method sets GTYPE to value 0"] impl crate::Resettable for GTYPE_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gwac.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gwac.rs index f82a87ee..e38d6653 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gwac.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gwac.rs @@ -1,55 +1,23 @@ #[doc = "Register `GWAC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GWAC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `PW0` reader - Pool Weight 0"] pub type PW0_R = crate::FieldReader; #[doc = "Field `PW0` writer - Pool Weight 0"] -pub type PW0_W<'a, const O: u8> = crate::FieldWriter<'a, GWAC_SPEC, 4, O>; +pub type PW0_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PW1` reader - Pool Weight 1"] pub type PW1_R = crate::FieldReader; #[doc = "Field `PW1` writer - Pool Weight 1"] -pub type PW1_W<'a, const O: u8> = crate::FieldWriter<'a, GWAC_SPEC, 4, O>; +pub type PW1_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PW2` reader - Pool Weight 2"] pub type PW2_R = crate::FieldReader; #[doc = "Field `PW2` writer - Pool Weight 2"] -pub type PW2_W<'a, const O: u8> = crate::FieldWriter<'a, GWAC_SPEC, 4, O>; +pub type PW2_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; #[doc = "Field `PW3` reader - Pool Weight 3"] pub type PW3_R = crate::FieldReader; #[doc = "Field `PW3` writer - Pool Weight 3"] -pub type PW3_W<'a, const O: u8> = crate::FieldWriter<'a, GWAC_SPEC, 4, O>; +pub type PW3_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 4, O>; impl R { #[doc = "Bits 0:3 - Pool Weight 0"] #[inline(always)] @@ -76,46 +44,43 @@ impl W { #[doc = "Bits 0:3 - Pool Weight 0"] #[inline(always)] #[must_use] - pub fn pw0(&mut self) -> PW0_W<0> { + pub fn pw0(&mut self) -> PW0_W { PW0_W::new(self) } #[doc = "Bits 4:7 - Pool Weight 1"] #[inline(always)] #[must_use] - pub fn pw1(&mut self) -> PW1_W<4> { + pub fn pw1(&mut self) -> PW1_W { PW1_W::new(self) } #[doc = "Bits 8:11 - Pool Weight 2"] #[inline(always)] #[must_use] - pub fn pw2(&mut self) -> PW2_W<8> { + pub fn pw2(&mut self) -> PW2_W { PW2_W::new(self) } #[doc = "Bits 12:15 - Pool Weight 3"] #[inline(always)] #[must_use] - pub fn pw3(&mut self) -> PW3_W<12> { + pub fn pw3(&mut self) -> PW3_W { PW3_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Weighted Arbiter Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gwac](index.html) module"] +#[doc = "Global Weighted Arbiter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gwac::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gwac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GWAC_SPEC; impl crate::RegisterSpec for GWAC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gwac::R](R) reader structure"] -impl crate::Readable for GWAC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gwac::W](W) writer structure"] +#[doc = "`read()` method returns [`gwac::R`](R) reader structure"] +impl crate::Readable for GWAC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gwac::W`](W) writer structure"] impl crate::Writable for GWAC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/gws.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/gws.rs index 4079a16c..312ff49e 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/gws.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/gws.rs @@ -1,135 +1,103 @@ #[doc = "Register `GWS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `GWS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `WS0` reader - XDMAC Channel 0 Write Suspend Bit"] pub type WS0_R = crate::BitReader; #[doc = "Field `WS0` writer - XDMAC Channel 0 Write Suspend Bit"] -pub type WS0_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS0_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS1` reader - XDMAC Channel 1 Write Suspend Bit"] pub type WS1_R = crate::BitReader; #[doc = "Field `WS1` writer - XDMAC Channel 1 Write Suspend Bit"] -pub type WS1_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS1_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS2` reader - XDMAC Channel 2 Write Suspend Bit"] pub type WS2_R = crate::BitReader; #[doc = "Field `WS2` writer - XDMAC Channel 2 Write Suspend Bit"] -pub type WS2_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS2_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS3` reader - XDMAC Channel 3 Write Suspend Bit"] pub type WS3_R = crate::BitReader; #[doc = "Field `WS3` writer - XDMAC Channel 3 Write Suspend Bit"] -pub type WS3_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS3_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS4` reader - XDMAC Channel 4 Write Suspend Bit"] pub type WS4_R = crate::BitReader; #[doc = "Field `WS4` writer - XDMAC Channel 4 Write Suspend Bit"] -pub type WS4_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS4_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS5` reader - XDMAC Channel 5 Write Suspend Bit"] pub type WS5_R = crate::BitReader; #[doc = "Field `WS5` writer - XDMAC Channel 5 Write Suspend Bit"] -pub type WS5_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS5_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS6` reader - XDMAC Channel 6 Write Suspend Bit"] pub type WS6_R = crate::BitReader; #[doc = "Field `WS6` writer - XDMAC Channel 6 Write Suspend Bit"] -pub type WS6_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS6_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS7` reader - XDMAC Channel 7 Write Suspend Bit"] pub type WS7_R = crate::BitReader; #[doc = "Field `WS7` writer - XDMAC Channel 7 Write Suspend Bit"] -pub type WS7_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS7_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS8` reader - XDMAC Channel 8 Write Suspend Bit"] pub type WS8_R = crate::BitReader; #[doc = "Field `WS8` writer - XDMAC Channel 8 Write Suspend Bit"] -pub type WS8_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS8_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS9` reader - XDMAC Channel 9 Write Suspend Bit"] pub type WS9_R = crate::BitReader; #[doc = "Field `WS9` writer - XDMAC Channel 9 Write Suspend Bit"] -pub type WS9_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS9_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS10` reader - XDMAC Channel 10 Write Suspend Bit"] pub type WS10_R = crate::BitReader; #[doc = "Field `WS10` writer - XDMAC Channel 10 Write Suspend Bit"] -pub type WS10_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS10_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS11` reader - XDMAC Channel 11 Write Suspend Bit"] pub type WS11_R = crate::BitReader; #[doc = "Field `WS11` writer - XDMAC Channel 11 Write Suspend Bit"] -pub type WS11_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS11_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS12` reader - XDMAC Channel 12 Write Suspend Bit"] pub type WS12_R = crate::BitReader; #[doc = "Field `WS12` writer - XDMAC Channel 12 Write Suspend Bit"] -pub type WS12_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS12_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS13` reader - XDMAC Channel 13 Write Suspend Bit"] pub type WS13_R = crate::BitReader; #[doc = "Field `WS13` writer - XDMAC Channel 13 Write Suspend Bit"] -pub type WS13_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS13_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS14` reader - XDMAC Channel 14 Write Suspend Bit"] pub type WS14_R = crate::BitReader; #[doc = "Field `WS14` writer - XDMAC Channel 14 Write Suspend Bit"] -pub type WS14_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS14_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS15` reader - XDMAC Channel 15 Write Suspend Bit"] pub type WS15_R = crate::BitReader; #[doc = "Field `WS15` writer - XDMAC Channel 15 Write Suspend Bit"] -pub type WS15_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS15_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS16` reader - XDMAC Channel 16 Write Suspend Bit"] pub type WS16_R = crate::BitReader; #[doc = "Field `WS16` writer - XDMAC Channel 16 Write Suspend Bit"] -pub type WS16_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS16_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS17` reader - XDMAC Channel 17 Write Suspend Bit"] pub type WS17_R = crate::BitReader; #[doc = "Field `WS17` writer - XDMAC Channel 17 Write Suspend Bit"] -pub type WS17_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS17_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS18` reader - XDMAC Channel 18 Write Suspend Bit"] pub type WS18_R = crate::BitReader; #[doc = "Field `WS18` writer - XDMAC Channel 18 Write Suspend Bit"] -pub type WS18_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS18_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS19` reader - XDMAC Channel 19 Write Suspend Bit"] pub type WS19_R = crate::BitReader; #[doc = "Field `WS19` writer - XDMAC Channel 19 Write Suspend Bit"] -pub type WS19_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS19_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS20` reader - XDMAC Channel 20 Write Suspend Bit"] pub type WS20_R = crate::BitReader; #[doc = "Field `WS20` writer - XDMAC Channel 20 Write Suspend Bit"] -pub type WS20_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS20_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS21` reader - XDMAC Channel 21 Write Suspend Bit"] pub type WS21_R = crate::BitReader; #[doc = "Field `WS21` writer - XDMAC Channel 21 Write Suspend Bit"] -pub type WS21_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS21_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS22` reader - XDMAC Channel 22 Write Suspend Bit"] pub type WS22_R = crate::BitReader; #[doc = "Field `WS22` writer - XDMAC Channel 22 Write Suspend Bit"] -pub type WS22_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS22_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WS23` reader - XDMAC Channel 23 Write Suspend Bit"] pub type WS23_R = crate::BitReader; #[doc = "Field `WS23` writer - XDMAC Channel 23 Write Suspend Bit"] -pub type WS23_W<'a, const O: u8> = crate::BitWriter<'a, GWS_SPEC, O>; +pub type WS23_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl R { #[doc = "Bit 0 - XDMAC Channel 0 Write Suspend Bit"] #[inline(always)] @@ -256,166 +224,163 @@ impl W { #[doc = "Bit 0 - XDMAC Channel 0 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws0(&mut self) -> WS0_W<0> { + pub fn ws0(&mut self) -> WS0_W { WS0_W::new(self) } #[doc = "Bit 1 - XDMAC Channel 1 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws1(&mut self) -> WS1_W<1> { + pub fn ws1(&mut self) -> WS1_W { WS1_W::new(self) } #[doc = "Bit 2 - XDMAC Channel 2 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws2(&mut self) -> WS2_W<2> { + pub fn ws2(&mut self) -> WS2_W { WS2_W::new(self) } #[doc = "Bit 3 - XDMAC Channel 3 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws3(&mut self) -> WS3_W<3> { + pub fn ws3(&mut self) -> WS3_W { WS3_W::new(self) } #[doc = "Bit 4 - XDMAC Channel 4 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws4(&mut self) -> WS4_W<4> { + pub fn ws4(&mut self) -> WS4_W { WS4_W::new(self) } #[doc = "Bit 5 - XDMAC Channel 5 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws5(&mut self) -> WS5_W<5> { + pub fn ws5(&mut self) -> WS5_W { WS5_W::new(self) } #[doc = "Bit 6 - XDMAC Channel 6 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws6(&mut self) -> WS6_W<6> { + pub fn ws6(&mut self) -> WS6_W { WS6_W::new(self) } #[doc = "Bit 7 - XDMAC Channel 7 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws7(&mut self) -> WS7_W<7> { + pub fn ws7(&mut self) -> WS7_W { WS7_W::new(self) } #[doc = "Bit 8 - XDMAC Channel 8 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws8(&mut self) -> WS8_W<8> { + pub fn ws8(&mut self) -> WS8_W { WS8_W::new(self) } #[doc = "Bit 9 - XDMAC Channel 9 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws9(&mut self) -> WS9_W<9> { + pub fn ws9(&mut self) -> WS9_W { WS9_W::new(self) } #[doc = "Bit 10 - XDMAC Channel 10 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws10(&mut self) -> WS10_W<10> { + pub fn ws10(&mut self) -> WS10_W { WS10_W::new(self) } #[doc = "Bit 11 - XDMAC Channel 11 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws11(&mut self) -> WS11_W<11> { + pub fn ws11(&mut self) -> WS11_W { WS11_W::new(self) } #[doc = "Bit 12 - XDMAC Channel 12 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws12(&mut self) -> WS12_W<12> { + pub fn ws12(&mut self) -> WS12_W { WS12_W::new(self) } #[doc = "Bit 13 - XDMAC Channel 13 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws13(&mut self) -> WS13_W<13> { + pub fn ws13(&mut self) -> WS13_W { WS13_W::new(self) } #[doc = "Bit 14 - XDMAC Channel 14 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws14(&mut self) -> WS14_W<14> { + pub fn ws14(&mut self) -> WS14_W { WS14_W::new(self) } #[doc = "Bit 15 - XDMAC Channel 15 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws15(&mut self) -> WS15_W<15> { + pub fn ws15(&mut self) -> WS15_W { WS15_W::new(self) } #[doc = "Bit 16 - XDMAC Channel 16 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws16(&mut self) -> WS16_W<16> { + pub fn ws16(&mut self) -> WS16_W { WS16_W::new(self) } #[doc = "Bit 17 - XDMAC Channel 17 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws17(&mut self) -> WS17_W<17> { + pub fn ws17(&mut self) -> WS17_W { WS17_W::new(self) } #[doc = "Bit 18 - XDMAC Channel 18 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws18(&mut self) -> WS18_W<18> { + pub fn ws18(&mut self) -> WS18_W { WS18_W::new(self) } #[doc = "Bit 19 - XDMAC Channel 19 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws19(&mut self) -> WS19_W<19> { + pub fn ws19(&mut self) -> WS19_W { WS19_W::new(self) } #[doc = "Bit 20 - XDMAC Channel 20 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws20(&mut self) -> WS20_W<20> { + pub fn ws20(&mut self) -> WS20_W { WS20_W::new(self) } #[doc = "Bit 21 - XDMAC Channel 21 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws21(&mut self) -> WS21_W<21> { + pub fn ws21(&mut self) -> WS21_W { WS21_W::new(self) } #[doc = "Bit 22 - XDMAC Channel 22 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws22(&mut self) -> WS22_W<22> { + pub fn ws22(&mut self) -> WS22_W { WS22_W::new(self) } #[doc = "Bit 23 - XDMAC Channel 23 Write Suspend Bit"] #[inline(always)] #[must_use] - pub fn ws23(&mut self) -> WS23_W<23> { + pub fn ws23(&mut self) -> WS23_W { WS23_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Global Channel Write Suspend Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gws](index.html) module"] +#[doc = "Global Channel Write Suspend Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gws::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gws::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct GWS_SPEC; impl crate::RegisterSpec for GWS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [gws::R](R) reader structure"] -impl crate::Readable for GWS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [gws::W](W) writer structure"] +#[doc = "`read()` method returns [`gws::R`](R) reader structure"] +impl crate::Readable for GWS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gws::W`](W) writer structure"] impl crate::Writable for GWS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid.rs index 22ba6681..84915ff9 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid.rs @@ -30,59 +30,73 @@ pub struct XDMAC_CHID { #[doc = "0x34 - Channel Destination Microblock Stride"] pub cdus: CDUS, } -#[doc = "CIE (w) register accessor: an alias for `Reg`"] +#[doc = "CIE (w) register accessor: Channel Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cie::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cie`] +module"] pub type CIE = crate::Reg; #[doc = "Channel Interrupt Enable Register"] pub mod cie; -#[doc = "CID (w) register accessor: an alias for `Reg`"] +#[doc = "CID (w) register accessor: Channel Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cid`] +module"] pub type CID = crate::Reg; #[doc = "Channel Interrupt Disable Register"] pub mod cid; -#[doc = "CIM (r) register accessor: an alias for `Reg`"] +#[doc = "CIM (r) register accessor: Channel Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cim::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cim`] +module"] pub type CIM = crate::Reg; #[doc = "Channel Interrupt Mask Register"] pub mod cim; -#[doc = "CIS (r) register accessor: an alias for `Reg`"] +#[doc = "CIS (r) register accessor: Channel Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cis`] +module"] pub type CIS = crate::Reg; #[doc = "Channel Interrupt Status Register"] pub mod cis; -#[doc = "CSA (rw) register accessor: an alias for `Reg`"] +#[doc = "CSA (rw) register accessor: Channel Source Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csa::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`csa`] +module"] pub type CSA = crate::Reg; #[doc = "Channel Source Address Register"] pub mod csa; -#[doc = "CDA (rw) register accessor: an alias for `Reg`"] +#[doc = "CDA (rw) register accessor: Channel Destination Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cda::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cda::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cda`] +module"] pub type CDA = crate::Reg; #[doc = "Channel Destination Address Register"] pub mod cda; -#[doc = "CNDA (rw) register accessor: an alias for `Reg`"] +#[doc = "CNDA (rw) register accessor: Channel Next Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnda::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnda::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cnda`] +module"] pub type CNDA = crate::Reg; #[doc = "Channel Next Descriptor Address Register"] pub mod cnda; -#[doc = "CNDC (rw) register accessor: an alias for `Reg`"] +#[doc = "CNDC (rw) register accessor: Channel Next Descriptor Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cndc`] +module"] pub type CNDC = crate::Reg; #[doc = "Channel Next Descriptor Control Register"] pub mod cndc; -#[doc = "CUBC (rw) register accessor: an alias for `Reg`"] +#[doc = "CUBC (rw) register accessor: Channel Microblock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cubc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cubc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cubc`] +module"] pub type CUBC = crate::Reg; #[doc = "Channel Microblock Control Register"] pub mod cubc; -#[doc = "CBC (rw) register accessor: an alias for `Reg`"] +#[doc = "CBC (rw) register accessor: Channel Block Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cbc`] +module"] pub type CBC = crate::Reg; #[doc = "Channel Block Control Register"] pub mod cbc; -#[doc = "CC (rw) register accessor: an alias for `Reg`"] +#[doc = "CC (rw) register accessor: Channel Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cc`] +module"] pub type CC = crate::Reg; #[doc = "Channel Configuration Register"] pub mod cc; -#[doc = "CDS_MSP (rw) register accessor: an alias for `Reg`"] +#[doc = "CDS_MSP (rw) register accessor: Channel Data Stride Memory Set Pattern\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cds_msp::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cds_msp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cds_msp`] +module"] pub type CDS_MSP = crate::Reg; #[doc = "Channel Data Stride Memory Set Pattern"] pub mod cds_msp; -#[doc = "CSUS (rw) register accessor: an alias for `Reg`"] +#[doc = "CSUS (rw) register accessor: Channel Source Microblock Stride\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`csus`] +module"] pub type CSUS = crate::Reg; #[doc = "Channel Source Microblock Stride"] pub mod csus; -#[doc = "CDUS (rw) register accessor: an alias for `Reg`"] +#[doc = "CDUS (rw) register accessor: Channel Destination Microblock Stride\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdus::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdus::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`cdus`] +module"] pub type CDUS = crate::Reg; #[doc = "Channel Destination Microblock Stride"] pub mod cdus; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cbc.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cbc.rs index 02a3690f..8da4172e 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cbc.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cbc.rs @@ -1,43 +1,11 @@ #[doc = "Register `CBC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CBC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BLEN` reader - Channel x Block Length"] pub type BLEN_R = crate::FieldReader; #[doc = "Field `BLEN` writer - Channel x Block Length"] -pub type BLEN_W<'a, const O: u8> = crate::FieldWriter<'a, CBC_SPEC, 12, O, u16>; +pub type BLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 12, O, u16>; impl R { #[doc = "Bits 0:11 - Channel x Block Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:11 - Channel x Block Length"] #[inline(always)] #[must_use] - pub fn blen(&mut self) -> BLEN_W<0> { + pub fn blen(&mut self) -> BLEN_W { BLEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Block Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cbc](index.html) module"] +#[doc = "Channel Block Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cbc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cbc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CBC_SPEC; impl crate::RegisterSpec for CBC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cbc::R](R) reader structure"] -impl crate::Readable for CBC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cbc::W](W) writer structure"] +#[doc = "`read()` method returns [`cbc::R`](R) reader structure"] +impl crate::Readable for CBC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cbc::W`](W) writer structure"] impl crate::Writable for CBC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cc.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cc.rs index a1dc9db8..7e295889 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cc.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cc.rs @@ -1,39 +1,7 @@ #[doc = "Register `CC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `TYPE` reader - Channel x Transfer Type"] pub type TYPE_R = crate::BitReader; #[doc = "Channel x Transfer Type\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl TYPE_R { true => TYPESELECT_A::PER_TRAN, } } - #[doc = "Checks if the value of the field is `MEM_TRAN`"] + #[doc = "Self-triggered mode (memory-to-memory transfer)."] #[inline(always)] pub fn is_mem_tran(&self) -> bool { *self == TYPESELECT_A::MEM_TRAN } - #[doc = "Checks if the value of the field is `PER_TRAN`"] + #[doc = "Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer)."] #[inline(always)] pub fn is_per_tran(&self) -> bool { *self == TYPESELECT_A::PER_TRAN } } #[doc = "Field `TYPE` writer - Channel x Transfer Type"] -pub type TYPE_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, TYPESELECT_A>; -impl<'a, const O: u8> TYPE_W<'a, O> { +pub type TYPE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, TYPESELECT_A>; +impl<'a, REG, const O: u8> TYPE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Self-triggered mode (memory-to-memory transfer)."] #[inline(always)] - pub fn mem_tran(self) -> &'a mut W { + pub fn mem_tran(self) -> &'a mut crate::W { self.variant(TYPESELECT_A::MEM_TRAN) } #[doc = "Synchronized mode (peripheral-to-memory or memory-to-peripheral transfer)."] #[inline(always)] - pub fn per_tran(self) -> &'a mut W { + pub fn per_tran(self) -> &'a mut crate::W { self.variant(TYPESELECT_A::PER_TRAN) } } @@ -120,48 +91,52 @@ impl MBSIZE_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `SINGLE`"] + #[doc = "The memory burst size is set to one."] #[inline(always)] pub fn is_single(&self) -> bool { *self == MBSIZESELECT_A::SINGLE } - #[doc = "Checks if the value of the field is `FOUR`"] + #[doc = "The memory burst size is set to four."] #[inline(always)] pub fn is_four(&self) -> bool { *self == MBSIZESELECT_A::FOUR } - #[doc = "Checks if the value of the field is `EIGHT`"] + #[doc = "The memory burst size is set to eight."] #[inline(always)] pub fn is_eight(&self) -> bool { *self == MBSIZESELECT_A::EIGHT } - #[doc = "Checks if the value of the field is `SIXTEEN`"] + #[doc = "The memory burst size is set to sixteen."] #[inline(always)] pub fn is_sixteen(&self) -> bool { *self == MBSIZESELECT_A::SIXTEEN } } #[doc = "Field `MBSIZE` writer - Channel x Memory Burst Size"] -pub type MBSIZE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CC_SPEC, 2, O, MBSIZESELECT_A>; -impl<'a, const O: u8> MBSIZE_W<'a, O> { +pub type MBSIZE_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, MBSIZESELECT_A>; +impl<'a, REG, const O: u8> MBSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The memory burst size is set to one."] #[inline(always)] - pub fn single(self) -> &'a mut W { + pub fn single(self) -> &'a mut crate::W { self.variant(MBSIZESELECT_A::SINGLE) } #[doc = "The memory burst size is set to four."] #[inline(always)] - pub fn four(self) -> &'a mut W { + pub fn four(self) -> &'a mut crate::W { self.variant(MBSIZESELECT_A::FOUR) } #[doc = "The memory burst size is set to eight."] #[inline(always)] - pub fn eight(self) -> &'a mut W { + pub fn eight(self) -> &'a mut crate::W { self.variant(MBSIZESELECT_A::EIGHT) } #[doc = "The memory burst size is set to sixteen."] #[inline(always)] - pub fn sixteen(self) -> &'a mut W { + pub fn sixteen(self) -> &'a mut crate::W { self.variant(MBSIZESELECT_A::SIXTEEN) } } @@ -190,28 +165,31 @@ impl DSYNC_R { true => DSYNCSELECT_A::MEM2PER, } } - #[doc = "Checks if the value of the field is `PER2MEM`"] + #[doc = "Peripheral-to-memory transfer."] #[inline(always)] pub fn is_per2mem(&self) -> bool { *self == DSYNCSELECT_A::PER2MEM } - #[doc = "Checks if the value of the field is `MEM2PER`"] + #[doc = "Memory-to-peripheral transfer."] #[inline(always)] pub fn is_mem2per(&self) -> bool { *self == DSYNCSELECT_A::MEM2PER } } #[doc = "Field `DSYNC` writer - Channel x Synchronization"] -pub type DSYNC_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, DSYNCSELECT_A>; -impl<'a, const O: u8> DSYNC_W<'a, O> { +pub type DSYNC_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DSYNCSELECT_A>; +impl<'a, REG, const O: u8> DSYNC_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Peripheral-to-memory transfer."] #[inline(always)] - pub fn per2mem(self) -> &'a mut W { + pub fn per2mem(self) -> &'a mut crate::W { self.variant(DSYNCSELECT_A::PER2MEM) } #[doc = "Memory-to-peripheral transfer."] #[inline(always)] - pub fn mem2per(self) -> &'a mut W { + pub fn mem2per(self) -> &'a mut crate::W { self.variant(DSYNCSELECT_A::MEM2PER) } } @@ -240,28 +218,31 @@ impl SWREQ_R { true => SWREQSELECT_A::SWR_CONNECTED, } } - #[doc = "Checks if the value of the field is `HWR_CONNECTED`"] + #[doc = "Hardware request line is connected to the peripheral request line."] #[inline(always)] pub fn is_hwr_connected(&self) -> bool { *self == SWREQSELECT_A::HWR_CONNECTED } - #[doc = "Checks if the value of the field is `SWR_CONNECTED`"] + #[doc = "Software request is connected to the peripheral request line."] #[inline(always)] pub fn is_swr_connected(&self) -> bool { *self == SWREQSELECT_A::SWR_CONNECTED } } #[doc = "Field `SWREQ` writer - Channel x Software Request Trigger"] -pub type SWREQ_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, SWREQSELECT_A>; -impl<'a, const O: u8> SWREQ_W<'a, O> { +pub type SWREQ_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SWREQSELECT_A>; +impl<'a, REG, const O: u8> SWREQ_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Hardware request line is connected to the peripheral request line."] #[inline(always)] - pub fn hwr_connected(self) -> &'a mut W { + pub fn hwr_connected(self) -> &'a mut crate::W { self.variant(SWREQSELECT_A::HWR_CONNECTED) } #[doc = "Software request is connected to the peripheral request line."] #[inline(always)] - pub fn swr_connected(self) -> &'a mut W { + pub fn swr_connected(self) -> &'a mut crate::W { self.variant(SWREQSELECT_A::SWR_CONNECTED) } } @@ -290,28 +271,31 @@ impl MEMSET_R { true => MEMSETSELECT_A::HW_MODE, } } - #[doc = "Checks if the value of the field is `NORMAL_MODE`"] + #[doc = "Memset is not activated."] #[inline(always)] pub fn is_normal_mode(&self) -> bool { *self == MEMSETSELECT_A::NORMAL_MODE } - #[doc = "Checks if the value of the field is `HW_MODE`"] + #[doc = "Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis."] #[inline(always)] pub fn is_hw_mode(&self) -> bool { *self == MEMSETSELECT_A::HW_MODE } } #[doc = "Field `MEMSET` writer - Channel x Fill Block of memory"] -pub type MEMSET_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, MEMSETSELECT_A>; -impl<'a, const O: u8> MEMSET_W<'a, O> { +pub type MEMSET_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, MEMSETSELECT_A>; +impl<'a, REG, const O: u8> MEMSET_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Memset is not activated."] #[inline(always)] - pub fn normal_mode(self) -> &'a mut W { + pub fn normal_mode(self) -> &'a mut crate::W { self.variant(MEMSETSELECT_A::NORMAL_MODE) } #[doc = "Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis."] #[inline(always)] - pub fn hw_mode(self) -> &'a mut W { + pub fn hw_mode(self) -> &'a mut crate::W { self.variant(MEMSETSELECT_A::HW_MODE) } } @@ -354,58 +338,62 @@ impl CSIZE_R { _ => None, } } - #[doc = "Checks if the value of the field is `CHK_1`"] + #[doc = "1 data transferred"] #[inline(always)] pub fn is_chk_1(&self) -> bool { *self == CSIZESELECT_A::CHK_1 } - #[doc = "Checks if the value of the field is `CHK_2`"] + #[doc = "2 data transferred"] #[inline(always)] pub fn is_chk_2(&self) -> bool { *self == CSIZESELECT_A::CHK_2 } - #[doc = "Checks if the value of the field is `CHK_4`"] + #[doc = "4 data transferred"] #[inline(always)] pub fn is_chk_4(&self) -> bool { *self == CSIZESELECT_A::CHK_4 } - #[doc = "Checks if the value of the field is `CHK_8`"] + #[doc = "8 data transferred"] #[inline(always)] pub fn is_chk_8(&self) -> bool { *self == CSIZESELECT_A::CHK_8 } - #[doc = "Checks if the value of the field is `CHK_16`"] + #[doc = "16 data transferred"] #[inline(always)] pub fn is_chk_16(&self) -> bool { *self == CSIZESELECT_A::CHK_16 } } #[doc = "Field `CSIZE` writer - Channel x Chunk Size"] -pub type CSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, CC_SPEC, 3, O, CSIZESELECT_A>; -impl<'a, const O: u8> CSIZE_W<'a, O> { +pub type CSIZE_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O, CSIZESELECT_A>; +impl<'a, REG, const O: u8> CSIZE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "1 data transferred"] #[inline(always)] - pub fn chk_1(self) -> &'a mut W { + pub fn chk_1(self) -> &'a mut crate::W { self.variant(CSIZESELECT_A::CHK_1) } #[doc = "2 data transferred"] #[inline(always)] - pub fn chk_2(self) -> &'a mut W { + pub fn chk_2(self) -> &'a mut crate::W { self.variant(CSIZESELECT_A::CHK_2) } #[doc = "4 data transferred"] #[inline(always)] - pub fn chk_4(self) -> &'a mut W { + pub fn chk_4(self) -> &'a mut crate::W { self.variant(CSIZESELECT_A::CHK_4) } #[doc = "8 data transferred"] #[inline(always)] - pub fn chk_8(self) -> &'a mut W { + pub fn chk_8(self) -> &'a mut crate::W { self.variant(CSIZESELECT_A::CHK_8) } #[doc = "16 data transferred"] #[inline(always)] - pub fn chk_16(self) -> &'a mut W { + pub fn chk_16(self) -> &'a mut crate::W { self.variant(CSIZESELECT_A::CHK_16) } } @@ -442,38 +430,42 @@ impl DWIDTH_R { _ => None, } } - #[doc = "Checks if the value of the field is `BYTE`"] + #[doc = "The data size is set to 8 bits"] #[inline(always)] pub fn is_byte(&self) -> bool { *self == DWIDTHSELECT_A::BYTE } - #[doc = "Checks if the value of the field is `HALFWORD`"] + #[doc = "The data size is set to 16 bits"] #[inline(always)] pub fn is_halfword(&self) -> bool { *self == DWIDTHSELECT_A::HALFWORD } - #[doc = "Checks if the value of the field is `WORD`"] + #[doc = "The data size is set to 32 bits"] #[inline(always)] pub fn is_word(&self) -> bool { *self == DWIDTHSELECT_A::WORD } } #[doc = "Field `DWIDTH` writer - Channel x Data Width"] -pub type DWIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, CC_SPEC, 2, O, DWIDTHSELECT_A>; -impl<'a, const O: u8> DWIDTH_W<'a, O> { +pub type DWIDTH_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 2, O, DWIDTHSELECT_A>; +impl<'a, REG, const O: u8> DWIDTH_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The data size is set to 8 bits"] #[inline(always)] - pub fn byte(self) -> &'a mut W { + pub fn byte(self) -> &'a mut crate::W { self.variant(DWIDTHSELECT_A::BYTE) } #[doc = "The data size is set to 16 bits"] #[inline(always)] - pub fn halfword(self) -> &'a mut W { + pub fn halfword(self) -> &'a mut crate::W { self.variant(DWIDTHSELECT_A::HALFWORD) } #[doc = "The data size is set to 32 bits"] #[inline(always)] - pub fn word(self) -> &'a mut W { + pub fn word(self) -> &'a mut crate::W { self.variant(DWIDTHSELECT_A::WORD) } } @@ -502,28 +494,31 @@ impl SIF_R { true => SIFSELECT_A::AHB_IF1, } } - #[doc = "Checks if the value of the field is `AHB_IF0`"] + #[doc = "The data is read through the system bus interface 0."] #[inline(always)] pub fn is_ahb_if0(&self) -> bool { *self == SIFSELECT_A::AHB_IF0 } - #[doc = "Checks if the value of the field is `AHB_IF1`"] + #[doc = "The data is read through the system bus interface 1."] #[inline(always)] pub fn is_ahb_if1(&self) -> bool { *self == SIFSELECT_A::AHB_IF1 } } #[doc = "Field `SIF` writer - Channel x Source Interface Identifier"] -pub type SIF_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, SIFSELECT_A>; -impl<'a, const O: u8> SIF_W<'a, O> { +pub type SIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, SIFSELECT_A>; +impl<'a, REG, const O: u8> SIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The data is read through the system bus interface 0."] #[inline(always)] - pub fn ahb_if0(self) -> &'a mut W { + pub fn ahb_if0(self) -> &'a mut crate::W { self.variant(SIFSELECT_A::AHB_IF0) } #[doc = "The data is read through the system bus interface 1."] #[inline(always)] - pub fn ahb_if1(self) -> &'a mut W { + pub fn ahb_if1(self) -> &'a mut crate::W { self.variant(SIFSELECT_A::AHB_IF1) } } @@ -552,28 +547,31 @@ impl DIF_R { true => DIFSELECT_A::AHB_IF1, } } - #[doc = "Checks if the value of the field is `AHB_IF0`"] + #[doc = "The data is written through the system bus interface 0."] #[inline(always)] pub fn is_ahb_if0(&self) -> bool { *self == DIFSELECT_A::AHB_IF0 } - #[doc = "Checks if the value of the field is `AHB_IF1`"] + #[doc = "The data is written though the system bus interface 1."] #[inline(always)] pub fn is_ahb_if1(&self) -> bool { *self == DIFSELECT_A::AHB_IF1 } } #[doc = "Field `DIF` writer - Channel x Destination Interface Identifier"] -pub type DIF_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, DIFSELECT_A>; -impl<'a, const O: u8> DIF_W<'a, O> { +pub type DIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, DIFSELECT_A>; +impl<'a, REG, const O: u8> DIF_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "The data is written through the system bus interface 0."] #[inline(always)] - pub fn ahb_if0(self) -> &'a mut W { + pub fn ahb_if0(self) -> &'a mut crate::W { self.variant(DIFSELECT_A::AHB_IF0) } #[doc = "The data is written though the system bus interface 1."] #[inline(always)] - pub fn ahb_if1(self) -> &'a mut W { + pub fn ahb_if1(self) -> &'a mut crate::W { self.variant(DIFSELECT_A::AHB_IF1) } } @@ -613,48 +611,52 @@ impl SAM_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `FIXED_AM`"] + #[doc = "The address remains unchanged."] #[inline(always)] pub fn is_fixed_am(&self) -> bool { *self == SAMSELECT_A::FIXED_AM } - #[doc = "Checks if the value of the field is `INCREMENTED_AM`"] + #[doc = "The addressing mode is incremented (the increment size is set to the data size)."] #[inline(always)] pub fn is_incremented_am(&self) -> bool { *self == SAMSELECT_A::INCREMENTED_AM } - #[doc = "Checks if the value of the field is `UBS_AM`"] + #[doc = "The microblock stride is added at the microblock boundary."] #[inline(always)] pub fn is_ubs_am(&self) -> bool { *self == SAMSELECT_A::UBS_AM } - #[doc = "Checks if the value of the field is `UBS_DS_AM`"] + #[doc = "The microblock stride is added at the microblock boundary, the data stride is added at the data boundary."] #[inline(always)] pub fn is_ubs_ds_am(&self) -> bool { *self == SAMSELECT_A::UBS_DS_AM } } #[doc = "Field `SAM` writer - Channel x Source Addressing Mode"] -pub type SAM_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CC_SPEC, 2, O, SAMSELECT_A>; -impl<'a, const O: u8> SAM_W<'a, O> { +pub type SAM_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, SAMSELECT_A>; +impl<'a, REG, const O: u8> SAM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The address remains unchanged."] #[inline(always)] - pub fn fixed_am(self) -> &'a mut W { + pub fn fixed_am(self) -> &'a mut crate::W { self.variant(SAMSELECT_A::FIXED_AM) } #[doc = "The addressing mode is incremented (the increment size is set to the data size)."] #[inline(always)] - pub fn incremented_am(self) -> &'a mut W { + pub fn incremented_am(self) -> &'a mut crate::W { self.variant(SAMSELECT_A::INCREMENTED_AM) } #[doc = "The microblock stride is added at the microblock boundary."] #[inline(always)] - pub fn ubs_am(self) -> &'a mut W { + pub fn ubs_am(self) -> &'a mut crate::W { self.variant(SAMSELECT_A::UBS_AM) } #[doc = "The microblock stride is added at the microblock boundary, the data stride is added at the data boundary."] #[inline(always)] - pub fn ubs_ds_am(self) -> &'a mut W { + pub fn ubs_ds_am(self) -> &'a mut crate::W { self.variant(SAMSELECT_A::UBS_DS_AM) } } @@ -694,48 +696,52 @@ impl DAM_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `FIXED_AM`"] + #[doc = "The address remains unchanged."] #[inline(always)] pub fn is_fixed_am(&self) -> bool { *self == DAMSELECT_A::FIXED_AM } - #[doc = "Checks if the value of the field is `INCREMENTED_AM`"] + #[doc = "The addressing mode is incremented (the increment size is set to the data size)."] #[inline(always)] pub fn is_incremented_am(&self) -> bool { *self == DAMSELECT_A::INCREMENTED_AM } - #[doc = "Checks if the value of the field is `UBS_AM`"] + #[doc = "The microblock stride is added at the microblock boundary."] #[inline(always)] pub fn is_ubs_am(&self) -> bool { *self == DAMSELECT_A::UBS_AM } - #[doc = "Checks if the value of the field is `UBS_DS_AM`"] + #[doc = "The microblock stride is added at the microblock boundary; the data stride is added at the data boundary."] #[inline(always)] pub fn is_ubs_ds_am(&self) -> bool { *self == DAMSELECT_A::UBS_DS_AM } } #[doc = "Field `DAM` writer - Channel x Destination Addressing Mode"] -pub type DAM_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CC_SPEC, 2, O, DAMSELECT_A>; -impl<'a, const O: u8> DAM_W<'a, O> { +pub type DAM_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, DAMSELECT_A>; +impl<'a, REG, const O: u8> DAM_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "The address remains unchanged."] #[inline(always)] - pub fn fixed_am(self) -> &'a mut W { + pub fn fixed_am(self) -> &'a mut crate::W { self.variant(DAMSELECT_A::FIXED_AM) } #[doc = "The addressing mode is incremented (the increment size is set to the data size)."] #[inline(always)] - pub fn incremented_am(self) -> &'a mut W { + pub fn incremented_am(self) -> &'a mut crate::W { self.variant(DAMSELECT_A::INCREMENTED_AM) } #[doc = "The microblock stride is added at the microblock boundary."] #[inline(always)] - pub fn ubs_am(self) -> &'a mut W { + pub fn ubs_am(self) -> &'a mut crate::W { self.variant(DAMSELECT_A::UBS_AM) } #[doc = "The microblock stride is added at the microblock boundary; the data stride is added at the data boundary."] #[inline(always)] - pub fn ubs_ds_am(self) -> &'a mut W { + pub fn ubs_ds_am(self) -> &'a mut crate::W { self.variant(DAMSELECT_A::UBS_DS_AM) } } @@ -764,28 +770,31 @@ impl INITD_R { true => INITDSELECT_A::TERMINATED, } } - #[doc = "Checks if the value of the field is `IN_PROGRESS`"] + #[doc = "Channel initialization is in progress."] #[inline(always)] pub fn is_in_progress(&self) -> bool { *self == INITDSELECT_A::IN_PROGRESS } - #[doc = "Checks if the value of the field is `TERMINATED`"] + #[doc = "Channel initialization is completed."] #[inline(always)] pub fn is_terminated(&self) -> bool { *self == INITDSELECT_A::TERMINATED } } #[doc = "Field `INITD` writer - Channel Initialization Terminated (this bit is read-only)"] -pub type INITD_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, INITDSELECT_A>; -impl<'a, const O: u8> INITD_W<'a, O> { +pub type INITD_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, INITDSELECT_A>; +impl<'a, REG, const O: u8> INITD_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Channel initialization is in progress."] #[inline(always)] - pub fn in_progress(self) -> &'a mut W { + pub fn in_progress(self) -> &'a mut crate::W { self.variant(INITDSELECT_A::IN_PROGRESS) } #[doc = "Channel initialization is completed."] #[inline(always)] - pub fn terminated(self) -> &'a mut W { + pub fn terminated(self) -> &'a mut crate::W { self.variant(INITDSELECT_A::TERMINATED) } } @@ -814,28 +823,31 @@ impl RDIP_R { true => RDIPSELECT_A::IN_PROGRESS, } } - #[doc = "Checks if the value of the field is `DONE`"] + #[doc = "No active read transaction on the bus."] #[inline(always)] pub fn is_done(&self) -> bool { *self == RDIPSELECT_A::DONE } - #[doc = "Checks if the value of the field is `IN_PROGRESS`"] + #[doc = "A read transaction is in progress."] #[inline(always)] pub fn is_in_progress(&self) -> bool { *self == RDIPSELECT_A::IN_PROGRESS } } #[doc = "Field `RDIP` writer - Read in Progress (this bit is read-only)"] -pub type RDIP_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, RDIPSELECT_A>; -impl<'a, const O: u8> RDIP_W<'a, O> { +pub type RDIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, RDIPSELECT_A>; +impl<'a, REG, const O: u8> RDIP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No active read transaction on the bus."] #[inline(always)] - pub fn done(self) -> &'a mut W { + pub fn done(self) -> &'a mut crate::W { self.variant(RDIPSELECT_A::DONE) } #[doc = "A read transaction is in progress."] #[inline(always)] - pub fn in_progress(self) -> &'a mut W { + pub fn in_progress(self) -> &'a mut crate::W { self.variant(RDIPSELECT_A::IN_PROGRESS) } } @@ -864,28 +876,31 @@ impl WRIP_R { true => WRIPSELECT_A::IN_PROGRESS, } } - #[doc = "Checks if the value of the field is `DONE`"] + #[doc = "No active write transaction on the bus."] #[inline(always)] pub fn is_done(&self) -> bool { *self == WRIPSELECT_A::DONE } - #[doc = "Checks if the value of the field is `IN_PROGRESS`"] + #[doc = "A write transaction is in progress."] #[inline(always)] pub fn is_in_progress(&self) -> bool { *self == WRIPSELECT_A::IN_PROGRESS } } #[doc = "Field `WRIP` writer - Write in Progress (this bit is read-only)"] -pub type WRIP_W<'a, const O: u8> = crate::BitWriter<'a, CC_SPEC, O, WRIPSELECT_A>; -impl<'a, const O: u8> WRIP_W<'a, O> { +pub type WRIP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, WRIPSELECT_A>; +impl<'a, REG, const O: u8> WRIP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "No active write transaction on the bus."] #[inline(always)] - pub fn done(self) -> &'a mut W { + pub fn done(self) -> &'a mut crate::W { self.variant(WRIPSELECT_A::DONE) } #[doc = "A write transaction is in progress."] #[inline(always)] - pub fn in_progress(self) -> &'a mut W { + pub fn in_progress(self) -> &'a mut crate::W { self.variant(WRIPSELECT_A::IN_PROGRESS) } } @@ -1069,528 +1084,532 @@ impl PERID_R { _ => None, } } - #[doc = "Checks if the value of the field is `HSMCI`"] + #[doc = "HSMCI"] #[inline(always)] pub fn is_hsmci(&self) -> bool { *self == PERIDSELECT_A::HSMCI } - #[doc = "Checks if the value of the field is `SPI0_TX`"] + #[doc = "SPI0_TX"] #[inline(always)] pub fn is_spi0_tx(&self) -> bool { *self == PERIDSELECT_A::SPI0_TX } - #[doc = "Checks if the value of the field is `SPI0_RX`"] + #[doc = "SPI0_RX"] #[inline(always)] pub fn is_spi0_rx(&self) -> bool { *self == PERIDSELECT_A::SPI0_RX } - #[doc = "Checks if the value of the field is `SPI1_TX`"] + #[doc = "SPI1_TX"] #[inline(always)] pub fn is_spi1_tx(&self) -> bool { *self == PERIDSELECT_A::SPI1_TX } - #[doc = "Checks if the value of the field is `SPI1_RX`"] + #[doc = "SPI1_RX"] #[inline(always)] pub fn is_spi1_rx(&self) -> bool { *self == PERIDSELECT_A::SPI1_RX } - #[doc = "Checks if the value of the field is `QSPI_TX`"] + #[doc = "QSPI_TX"] #[inline(always)] pub fn is_qspi_tx(&self) -> bool { *self == PERIDSELECT_A::QSPI_TX } - #[doc = "Checks if the value of the field is `QSPI_RX`"] + #[doc = "QSPI_RX"] #[inline(always)] pub fn is_qspi_rx(&self) -> bool { *self == PERIDSELECT_A::QSPI_RX } - #[doc = "Checks if the value of the field is `USART0_TX`"] + #[doc = "USART0_TX"] #[inline(always)] pub fn is_usart0_tx(&self) -> bool { *self == PERIDSELECT_A::USART0_TX } - #[doc = "Checks if the value of the field is `USART0_RX`"] + #[doc = "USART0_RX"] #[inline(always)] pub fn is_usart0_rx(&self) -> bool { *self == PERIDSELECT_A::USART0_RX } - #[doc = "Checks if the value of the field is `USART1_TX`"] + #[doc = "USART1_TX"] #[inline(always)] pub fn is_usart1_tx(&self) -> bool { *self == PERIDSELECT_A::USART1_TX } - #[doc = "Checks if the value of the field is `USART1_RX`"] + #[doc = "USART1_RX"] #[inline(always)] pub fn is_usart1_rx(&self) -> bool { *self == PERIDSELECT_A::USART1_RX } - #[doc = "Checks if the value of the field is `USART2_TX`"] + #[doc = "USART2_TX"] #[inline(always)] pub fn is_usart2_tx(&self) -> bool { *self == PERIDSELECT_A::USART2_TX } - #[doc = "Checks if the value of the field is `USART2_RX`"] + #[doc = "USART2_RX"] #[inline(always)] pub fn is_usart2_rx(&self) -> bool { *self == PERIDSELECT_A::USART2_RX } - #[doc = "Checks if the value of the field is `PWM0`"] + #[doc = "PWM0"] #[inline(always)] pub fn is_pwm0(&self) -> bool { *self == PERIDSELECT_A::PWM0 } - #[doc = "Checks if the value of the field is `TWIHS0_TX`"] + #[doc = "TWIHS0_TX"] #[inline(always)] pub fn is_twihs0_tx(&self) -> bool { *self == PERIDSELECT_A::TWIHS0_TX } - #[doc = "Checks if the value of the field is `TWIHS0_RX`"] + #[doc = "TWIHS0_RX"] #[inline(always)] pub fn is_twihs0_rx(&self) -> bool { *self == PERIDSELECT_A::TWIHS0_RX } - #[doc = "Checks if the value of the field is `TWIHS1_TX`"] + #[doc = "TWIHS1_TX"] #[inline(always)] pub fn is_twihs1_tx(&self) -> bool { *self == PERIDSELECT_A::TWIHS1_TX } - #[doc = "Checks if the value of the field is `TWIHS1_RX`"] + #[doc = "TWIHS1_RX"] #[inline(always)] pub fn is_twihs1_rx(&self) -> bool { *self == PERIDSELECT_A::TWIHS1_RX } - #[doc = "Checks if the value of the field is `TWIHS2_TX`"] + #[doc = "TWIHS2_TX"] #[inline(always)] pub fn is_twihs2_tx(&self) -> bool { *self == PERIDSELECT_A::TWIHS2_TX } - #[doc = "Checks if the value of the field is `TWIHS2_RX`"] + #[doc = "TWIHS2_RX"] #[inline(always)] pub fn is_twihs2_rx(&self) -> bool { *self == PERIDSELECT_A::TWIHS2_RX } - #[doc = "Checks if the value of the field is `UART0_TX`"] + #[doc = "UART0_TX"] #[inline(always)] pub fn is_uart0_tx(&self) -> bool { *self == PERIDSELECT_A::UART0_TX } - #[doc = "Checks if the value of the field is `UART0_RX`"] + #[doc = "UART0_RX"] #[inline(always)] pub fn is_uart0_rx(&self) -> bool { *self == PERIDSELECT_A::UART0_RX } - #[doc = "Checks if the value of the field is `UART1_TX`"] + #[doc = "UART1_TX"] #[inline(always)] pub fn is_uart1_tx(&self) -> bool { *self == PERIDSELECT_A::UART1_TX } - #[doc = "Checks if the value of the field is `UART1_RX`"] + #[doc = "UART1_RX"] #[inline(always)] pub fn is_uart1_rx(&self) -> bool { *self == PERIDSELECT_A::UART1_RX } - #[doc = "Checks if the value of the field is `UART2_TX`"] + #[doc = "UART2_TX"] #[inline(always)] pub fn is_uart2_tx(&self) -> bool { *self == PERIDSELECT_A::UART2_TX } - #[doc = "Checks if the value of the field is `UART2_RX`"] + #[doc = "UART2_RX"] #[inline(always)] pub fn is_uart2_rx(&self) -> bool { *self == PERIDSELECT_A::UART2_RX } - #[doc = "Checks if the value of the field is `UART3_TX`"] + #[doc = "UART3_TX"] #[inline(always)] pub fn is_uart3_tx(&self) -> bool { *self == PERIDSELECT_A::UART3_TX } - #[doc = "Checks if the value of the field is `UART3_RX`"] + #[doc = "UART3_RX"] #[inline(always)] pub fn is_uart3_rx(&self) -> bool { *self == PERIDSELECT_A::UART3_RX } - #[doc = "Checks if the value of the field is `UART4_TX`"] + #[doc = "UART4_TX"] #[inline(always)] pub fn is_uart4_tx(&self) -> bool { *self == PERIDSELECT_A::UART4_TX } - #[doc = "Checks if the value of the field is `UART4_RX`"] + #[doc = "UART4_RX"] #[inline(always)] pub fn is_uart4_rx(&self) -> bool { *self == PERIDSELECT_A::UART4_RX } - #[doc = "Checks if the value of the field is `DACC0`"] + #[doc = "DACC0"] #[inline(always)] pub fn is_dacc0(&self) -> bool { *self == PERIDSELECT_A::DACC0 } - #[doc = "Checks if the value of the field is `DACC1`"] + #[doc = "DACC1"] #[inline(always)] pub fn is_dacc1(&self) -> bool { *self == PERIDSELECT_A::DACC1 } - #[doc = "Checks if the value of the field is `SSC_TX`"] + #[doc = "SSC_TX"] #[inline(always)] pub fn is_ssc_tx(&self) -> bool { *self == PERIDSELECT_A::SSC_TX } - #[doc = "Checks if the value of the field is `SSC_RX`"] + #[doc = "SSC_RX"] #[inline(always)] pub fn is_ssc_rx(&self) -> bool { *self == PERIDSELECT_A::SSC_RX } - #[doc = "Checks if the value of the field is `PIOA`"] + #[doc = "PIOA"] #[inline(always)] pub fn is_pioa(&self) -> bool { *self == PERIDSELECT_A::PIOA } - #[doc = "Checks if the value of the field is `AFEC0`"] + #[doc = "AFEC0"] #[inline(always)] pub fn is_afec0(&self) -> bool { *self == PERIDSELECT_A::AFEC0 } - #[doc = "Checks if the value of the field is `AFEC1`"] + #[doc = "AFEC1"] #[inline(always)] pub fn is_afec1(&self) -> bool { *self == PERIDSELECT_A::AFEC1 } - #[doc = "Checks if the value of the field is `AES_TX`"] + #[doc = "AES_TX"] #[inline(always)] pub fn is_aes_tx(&self) -> bool { *self == PERIDSELECT_A::AES_TX } - #[doc = "Checks if the value of the field is `AES_RX`"] + #[doc = "AES_RX"] #[inline(always)] pub fn is_aes_rx(&self) -> bool { *self == PERIDSELECT_A::AES_RX } - #[doc = "Checks if the value of the field is `PWM1`"] + #[doc = "PWM1"] #[inline(always)] pub fn is_pwm1(&self) -> bool { *self == PERIDSELECT_A::PWM1 } - #[doc = "Checks if the value of the field is `TC0`"] + #[doc = "TC0"] #[inline(always)] pub fn is_tc0(&self) -> bool { *self == PERIDSELECT_A::TC0 } - #[doc = "Checks if the value of the field is `TC3`"] + #[doc = "TC3"] #[inline(always)] pub fn is_tc3(&self) -> bool { *self == PERIDSELECT_A::TC3 } - #[doc = "Checks if the value of the field is `TC6`"] + #[doc = "TC6"] #[inline(always)] pub fn is_tc6(&self) -> bool { *self == PERIDSELECT_A::TC6 } - #[doc = "Checks if the value of the field is `TC9`"] + #[doc = "TC9"] #[inline(always)] pub fn is_tc9(&self) -> bool { *self == PERIDSELECT_A::TC9 } - #[doc = "Checks if the value of the field is `I2SC0_TX_LEFT`"] + #[doc = "I2SC0_TX_LEFT"] #[inline(always)] pub fn is_i2sc0_tx_left(&self) -> bool { *self == PERIDSELECT_A::I2SC0_TX_LEFT } - #[doc = "Checks if the value of the field is `I2SC0_RX_LEFT`"] + #[doc = "I2SC0_RX_LEFT"] #[inline(always)] pub fn is_i2sc0_rx_left(&self) -> bool { *self == PERIDSELECT_A::I2SC0_RX_LEFT } - #[doc = "Checks if the value of the field is `I2SC1_TX_LEFT`"] + #[doc = "I2SC1_TX_LEFT"] #[inline(always)] pub fn is_i2sc1_tx_left(&self) -> bool { *self == PERIDSELECT_A::I2SC1_TX_LEFT } - #[doc = "Checks if the value of the field is `I2SC1_RX_LEFT`"] + #[doc = "I2SC1_RX_LEFT"] #[inline(always)] pub fn is_i2sc1_rx_left(&self) -> bool { *self == PERIDSELECT_A::I2SC1_RX_LEFT } - #[doc = "Checks if the value of the field is `I2SC0_TX_RIGHT`"] + #[doc = "I2SC0_TX_RIGHT"] #[inline(always)] pub fn is_i2sc0_tx_right(&self) -> bool { *self == PERIDSELECT_A::I2SC0_TX_RIGHT } - #[doc = "Checks if the value of the field is `I2SC0_RX_RIGHT`"] + #[doc = "I2SC0_RX_RIGHT"] #[inline(always)] pub fn is_i2sc0_rx_right(&self) -> bool { *self == PERIDSELECT_A::I2SC0_RX_RIGHT } - #[doc = "Checks if the value of the field is `I2SC1_TX_RIGHT`"] + #[doc = "I2SC1_TX_RIGHT"] #[inline(always)] pub fn is_i2sc1_tx_right(&self) -> bool { *self == PERIDSELECT_A::I2SC1_TX_RIGHT } - #[doc = "Checks if the value of the field is `I2SC1_RX_RIGHT`"] + #[doc = "I2SC1_RX_RIGHT"] #[inline(always)] pub fn is_i2sc1_rx_right(&self) -> bool { *self == PERIDSELECT_A::I2SC1_RX_RIGHT } } #[doc = "Field `PERID` writer - Channel x Peripheral Hardware Request Line Identifier"] -pub type PERID_W<'a, const O: u8> = crate::FieldWriter<'a, CC_SPEC, 7, O, PERIDSELECT_A>; -impl<'a, const O: u8> PERID_W<'a, O> { +pub type PERID_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 7, O, PERIDSELECT_A>; +impl<'a, REG, const O: u8> PERID_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "HSMCI"] #[inline(always)] - pub fn hsmci(self) -> &'a mut W { + pub fn hsmci(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::HSMCI) } #[doc = "SPI0_TX"] #[inline(always)] - pub fn spi0_tx(self) -> &'a mut W { + pub fn spi0_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::SPI0_TX) } #[doc = "SPI0_RX"] #[inline(always)] - pub fn spi0_rx(self) -> &'a mut W { + pub fn spi0_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::SPI0_RX) } #[doc = "SPI1_TX"] #[inline(always)] - pub fn spi1_tx(self) -> &'a mut W { + pub fn spi1_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::SPI1_TX) } #[doc = "SPI1_RX"] #[inline(always)] - pub fn spi1_rx(self) -> &'a mut W { + pub fn spi1_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::SPI1_RX) } #[doc = "QSPI_TX"] #[inline(always)] - pub fn qspi_tx(self) -> &'a mut W { + pub fn qspi_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::QSPI_TX) } #[doc = "QSPI_RX"] #[inline(always)] - pub fn qspi_rx(self) -> &'a mut W { + pub fn qspi_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::QSPI_RX) } #[doc = "USART0_TX"] #[inline(always)] - pub fn usart0_tx(self) -> &'a mut W { + pub fn usart0_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::USART0_TX) } #[doc = "USART0_RX"] #[inline(always)] - pub fn usart0_rx(self) -> &'a mut W { + pub fn usart0_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::USART0_RX) } #[doc = "USART1_TX"] #[inline(always)] - pub fn usart1_tx(self) -> &'a mut W { + pub fn usart1_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::USART1_TX) } #[doc = "USART1_RX"] #[inline(always)] - pub fn usart1_rx(self) -> &'a mut W { + pub fn usart1_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::USART1_RX) } #[doc = "USART2_TX"] #[inline(always)] - pub fn usart2_tx(self) -> &'a mut W { + pub fn usart2_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::USART2_TX) } #[doc = "USART2_RX"] #[inline(always)] - pub fn usart2_rx(self) -> &'a mut W { + pub fn usart2_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::USART2_RX) } #[doc = "PWM0"] #[inline(always)] - pub fn pwm0(self) -> &'a mut W { + pub fn pwm0(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::PWM0) } #[doc = "TWIHS0_TX"] #[inline(always)] - pub fn twihs0_tx(self) -> &'a mut W { + pub fn twihs0_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TWIHS0_TX) } #[doc = "TWIHS0_RX"] #[inline(always)] - pub fn twihs0_rx(self) -> &'a mut W { + pub fn twihs0_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TWIHS0_RX) } #[doc = "TWIHS1_TX"] #[inline(always)] - pub fn twihs1_tx(self) -> &'a mut W { + pub fn twihs1_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TWIHS1_TX) } #[doc = "TWIHS1_RX"] #[inline(always)] - pub fn twihs1_rx(self) -> &'a mut W { + pub fn twihs1_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TWIHS1_RX) } #[doc = "TWIHS2_TX"] #[inline(always)] - pub fn twihs2_tx(self) -> &'a mut W { + pub fn twihs2_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TWIHS2_TX) } #[doc = "TWIHS2_RX"] #[inline(always)] - pub fn twihs2_rx(self) -> &'a mut W { + pub fn twihs2_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TWIHS2_RX) } #[doc = "UART0_TX"] #[inline(always)] - pub fn uart0_tx(self) -> &'a mut W { + pub fn uart0_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART0_TX) } #[doc = "UART0_RX"] #[inline(always)] - pub fn uart0_rx(self) -> &'a mut W { + pub fn uart0_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART0_RX) } #[doc = "UART1_TX"] #[inline(always)] - pub fn uart1_tx(self) -> &'a mut W { + pub fn uart1_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART1_TX) } #[doc = "UART1_RX"] #[inline(always)] - pub fn uart1_rx(self) -> &'a mut W { + pub fn uart1_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART1_RX) } #[doc = "UART2_TX"] #[inline(always)] - pub fn uart2_tx(self) -> &'a mut W { + pub fn uart2_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART2_TX) } #[doc = "UART2_RX"] #[inline(always)] - pub fn uart2_rx(self) -> &'a mut W { + pub fn uart2_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART2_RX) } #[doc = "UART3_TX"] #[inline(always)] - pub fn uart3_tx(self) -> &'a mut W { + pub fn uart3_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART3_TX) } #[doc = "UART3_RX"] #[inline(always)] - pub fn uart3_rx(self) -> &'a mut W { + pub fn uart3_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART3_RX) } #[doc = "UART4_TX"] #[inline(always)] - pub fn uart4_tx(self) -> &'a mut W { + pub fn uart4_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART4_TX) } #[doc = "UART4_RX"] #[inline(always)] - pub fn uart4_rx(self) -> &'a mut W { + pub fn uart4_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::UART4_RX) } #[doc = "DACC0"] #[inline(always)] - pub fn dacc0(self) -> &'a mut W { + pub fn dacc0(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::DACC0) } #[doc = "DACC1"] #[inline(always)] - pub fn dacc1(self) -> &'a mut W { + pub fn dacc1(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::DACC1) } #[doc = "SSC_TX"] #[inline(always)] - pub fn ssc_tx(self) -> &'a mut W { + pub fn ssc_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::SSC_TX) } #[doc = "SSC_RX"] #[inline(always)] - pub fn ssc_rx(self) -> &'a mut W { + pub fn ssc_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::SSC_RX) } #[doc = "PIOA"] #[inline(always)] - pub fn pioa(self) -> &'a mut W { + pub fn pioa(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::PIOA) } #[doc = "AFEC0"] #[inline(always)] - pub fn afec0(self) -> &'a mut W { + pub fn afec0(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::AFEC0) } #[doc = "AFEC1"] #[inline(always)] - pub fn afec1(self) -> &'a mut W { + pub fn afec1(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::AFEC1) } #[doc = "AES_TX"] #[inline(always)] - pub fn aes_tx(self) -> &'a mut W { + pub fn aes_tx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::AES_TX) } #[doc = "AES_RX"] #[inline(always)] - pub fn aes_rx(self) -> &'a mut W { + pub fn aes_rx(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::AES_RX) } #[doc = "PWM1"] #[inline(always)] - pub fn pwm1(self) -> &'a mut W { + pub fn pwm1(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::PWM1) } #[doc = "TC0"] #[inline(always)] - pub fn tc0(self) -> &'a mut W { + pub fn tc0(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TC0) } #[doc = "TC3"] #[inline(always)] - pub fn tc3(self) -> &'a mut W { + pub fn tc3(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TC3) } #[doc = "TC6"] #[inline(always)] - pub fn tc6(self) -> &'a mut W { + pub fn tc6(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TC6) } #[doc = "TC9"] #[inline(always)] - pub fn tc9(self) -> &'a mut W { + pub fn tc9(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::TC9) } #[doc = "I2SC0_TX_LEFT"] #[inline(always)] - pub fn i2sc0_tx_left(self) -> &'a mut W { + pub fn i2sc0_tx_left(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC0_TX_LEFT) } #[doc = "I2SC0_RX_LEFT"] #[inline(always)] - pub fn i2sc0_rx_left(self) -> &'a mut W { + pub fn i2sc0_rx_left(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC0_RX_LEFT) } #[doc = "I2SC1_TX_LEFT"] #[inline(always)] - pub fn i2sc1_tx_left(self) -> &'a mut W { + pub fn i2sc1_tx_left(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC1_TX_LEFT) } #[doc = "I2SC1_RX_LEFT"] #[inline(always)] - pub fn i2sc1_rx_left(self) -> &'a mut W { + pub fn i2sc1_rx_left(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC1_RX_LEFT) } #[doc = "I2SC0_TX_RIGHT"] #[inline(always)] - pub fn i2sc0_tx_right(self) -> &'a mut W { + pub fn i2sc0_tx_right(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC0_TX_RIGHT) } #[doc = "I2SC0_RX_RIGHT"] #[inline(always)] - pub fn i2sc0_rx_right(self) -> &'a mut W { + pub fn i2sc0_rx_right(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC0_RX_RIGHT) } #[doc = "I2SC1_TX_RIGHT"] #[inline(always)] - pub fn i2sc1_tx_right(self) -> &'a mut W { + pub fn i2sc1_tx_right(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC1_TX_RIGHT) } #[doc = "I2SC1_RX_RIGHT"] #[inline(always)] - pub fn i2sc1_rx_right(self) -> &'a mut W { + pub fn i2sc1_rx_right(self) -> &'a mut crate::W { self.variant(PERIDSELECT_A::I2SC1_RX_RIGHT) } } @@ -1675,112 +1694,109 @@ impl W { #[doc = "Bit 0 - Channel x Transfer Type"] #[inline(always)] #[must_use] - pub fn type_(&mut self) -> TYPE_W<0> { + pub fn type_(&mut self) -> TYPE_W { TYPE_W::new(self) } #[doc = "Bits 1:2 - Channel x Memory Burst Size"] #[inline(always)] #[must_use] - pub fn mbsize(&mut self) -> MBSIZE_W<1> { + pub fn mbsize(&mut self) -> MBSIZE_W { MBSIZE_W::new(self) } #[doc = "Bit 4 - Channel x Synchronization"] #[inline(always)] #[must_use] - pub fn dsync(&mut self) -> DSYNC_W<4> { + pub fn dsync(&mut self) -> DSYNC_W { DSYNC_W::new(self) } #[doc = "Bit 6 - Channel x Software Request Trigger"] #[inline(always)] #[must_use] - pub fn swreq(&mut self) -> SWREQ_W<6> { + pub fn swreq(&mut self) -> SWREQ_W { SWREQ_W::new(self) } #[doc = "Bit 7 - Channel x Fill Block of memory"] #[inline(always)] #[must_use] - pub fn memset(&mut self) -> MEMSET_W<7> { + pub fn memset(&mut self) -> MEMSET_W { MEMSET_W::new(self) } #[doc = "Bits 8:10 - Channel x Chunk Size"] #[inline(always)] #[must_use] - pub fn csize(&mut self) -> CSIZE_W<8> { + pub fn csize(&mut self) -> CSIZE_W { CSIZE_W::new(self) } #[doc = "Bits 11:12 - Channel x Data Width"] #[inline(always)] #[must_use] - pub fn dwidth(&mut self) -> DWIDTH_W<11> { + pub fn dwidth(&mut self) -> DWIDTH_W { DWIDTH_W::new(self) } #[doc = "Bit 13 - Channel x Source Interface Identifier"] #[inline(always)] #[must_use] - pub fn sif(&mut self) -> SIF_W<13> { + pub fn sif(&mut self) -> SIF_W { SIF_W::new(self) } #[doc = "Bit 14 - Channel x Destination Interface Identifier"] #[inline(always)] #[must_use] - pub fn dif(&mut self) -> DIF_W<14> { + pub fn dif(&mut self) -> DIF_W { DIF_W::new(self) } #[doc = "Bits 16:17 - Channel x Source Addressing Mode"] #[inline(always)] #[must_use] - pub fn sam(&mut self) -> SAM_W<16> { + pub fn sam(&mut self) -> SAM_W { SAM_W::new(self) } #[doc = "Bits 18:19 - Channel x Destination Addressing Mode"] #[inline(always)] #[must_use] - pub fn dam(&mut self) -> DAM_W<18> { + pub fn dam(&mut self) -> DAM_W { DAM_W::new(self) } #[doc = "Bit 21 - Channel Initialization Terminated (this bit is read-only)"] #[inline(always)] #[must_use] - pub fn initd(&mut self) -> INITD_W<21> { + pub fn initd(&mut self) -> INITD_W { INITD_W::new(self) } #[doc = "Bit 22 - Read in Progress (this bit is read-only)"] #[inline(always)] #[must_use] - pub fn rdip(&mut self) -> RDIP_W<22> { + pub fn rdip(&mut self) -> RDIP_W { RDIP_W::new(self) } #[doc = "Bit 23 - Write in Progress (this bit is read-only)"] #[inline(always)] #[must_use] - pub fn wrip(&mut self) -> WRIP_W<23> { + pub fn wrip(&mut self) -> WRIP_W { WRIP_W::new(self) } #[doc = "Bits 24:30 - Channel x Peripheral Hardware Request Line Identifier"] #[inline(always)] #[must_use] - pub fn perid(&mut self) -> PERID_W<24> { + pub fn perid(&mut self) -> PERID_W { PERID_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +#[doc = "Channel Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CC_SPEC; impl crate::RegisterSpec for CC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cc::R](R) reader structure"] -impl crate::Readable for CC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +#[doc = "`read()` method returns [`cc::R`](R) reader structure"] +impl crate::Readable for CC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cc::W`](W) writer structure"] impl crate::Writable for CC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cda.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cda.rs index 22df764a..1d64ef8a 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cda.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cda.rs @@ -1,43 +1,11 @@ #[doc = "Register `CDA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CDA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DA` reader - Channel x Destination Address"] pub type DA_R = crate::FieldReader; #[doc = "Field `DA` writer - Channel x Destination Address"] -pub type DA_W<'a, const O: u8> = crate::FieldWriter<'a, CDA_SPEC, 32, O, u32>; +pub type DA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Channel x Destination Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Channel x Destination Address"] #[inline(always)] #[must_use] - pub fn da(&mut self) -> DA_W<0> { + pub fn da(&mut self) -> DA_W { DA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Destination Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cda](index.html) module"] +#[doc = "Channel Destination Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cda::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cda::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDA_SPEC; impl crate::RegisterSpec for CDA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cda::R](R) reader structure"] -impl crate::Readable for CDA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cda::W](W) writer structure"] +#[doc = "`read()` method returns [`cda::R`](R) reader structure"] +impl crate::Readable for CDA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cda::W`](W) writer structure"] impl crate::Writable for CDA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cds_msp.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cds_msp.rs index 2fc32b22..89199b68 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cds_msp.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cds_msp.rs @@ -1,47 +1,15 @@ #[doc = "Register `CDS_MSP` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CDS_MSP` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SDS_MSP` reader - Channel x Source Data stride or Memory Set Pattern"] pub type SDS_MSP_R = crate::FieldReader; #[doc = "Field `SDS_MSP` writer - Channel x Source Data stride or Memory Set Pattern"] -pub type SDS_MSP_W<'a, const O: u8> = crate::FieldWriter<'a, CDS_MSP_SPEC, 16, O, u16>; +pub type SDS_MSP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; #[doc = "Field `DDS_MSP` reader - Channel x Destination Data Stride or Memory Set Pattern"] pub type DDS_MSP_R = crate::FieldReader; #[doc = "Field `DDS_MSP` writer - Channel x Destination Data Stride or Memory Set Pattern"] -pub type DDS_MSP_W<'a, const O: u8> = crate::FieldWriter<'a, CDS_MSP_SPEC, 16, O, u16>; +pub type DDS_MSP_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>; impl R { #[doc = "Bits 0:15 - Channel x Source Data stride or Memory Set Pattern"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bits 0:15 - Channel x Source Data stride or Memory Set Pattern"] #[inline(always)] #[must_use] - pub fn sds_msp(&mut self) -> SDS_MSP_W<0> { + pub fn sds_msp(&mut self) -> SDS_MSP_W { SDS_MSP_W::new(self) } #[doc = "Bits 16:31 - Channel x Destination Data Stride or Memory Set Pattern"] #[inline(always)] #[must_use] - pub fn dds_msp(&mut self) -> DDS_MSP_W<16> { + pub fn dds_msp(&mut self) -> DDS_MSP_W { DDS_MSP_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Data Stride Memory Set Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cds_msp](index.html) module"] +#[doc = "Channel Data Stride Memory Set Pattern\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cds_msp::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cds_msp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDS_MSP_SPEC; impl crate::RegisterSpec for CDS_MSP_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cds_msp::R](R) reader structure"] -impl crate::Readable for CDS_MSP_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cds_msp::W](W) writer structure"] +#[doc = "`read()` method returns [`cds_msp::R`](R) reader structure"] +impl crate::Readable for CDS_MSP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cds_msp::W`](W) writer structure"] impl crate::Writable for CDS_MSP_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cdus.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cdus.rs index edbaf3d2..9c73c92e 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cdus.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cdus.rs @@ -1,43 +1,11 @@ #[doc = "Register `CDUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CDUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `DUBS` reader - Channel x Destination Microblock Stride"] pub type DUBS_R = crate::FieldReader; #[doc = "Field `DUBS` writer - Channel x Destination Microblock Stride"] -pub type DUBS_W<'a, const O: u8> = crate::FieldWriter<'a, CDUS_SPEC, 24, O, u32>; +pub type DUBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Channel x Destination Microblock Stride"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Channel x Destination Microblock Stride"] #[inline(always)] #[must_use] - pub fn dubs(&mut self) -> DUBS_W<0> { + pub fn dubs(&mut self) -> DUBS_W { DUBS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Destination Microblock Stride\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cdus](index.html) module"] +#[doc = "Channel Destination Microblock Stride\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cdus::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cdus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CDUS_SPEC; impl crate::RegisterSpec for CDUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cdus::R](R) reader structure"] -impl crate::Readable for CDUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cdus::W](W) writer structure"] +#[doc = "`read()` method returns [`cdus::R`](R) reader structure"] +impl crate::Readable for CDUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cdus::W`](W) writer structure"] impl crate::Writable for CDUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cid.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cid.rs index ec60e5a2..a4b80a3a 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cid.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cid.rs @@ -1,96 +1,76 @@ #[doc = "Register `CID` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BID` writer - End of Block Interrupt Disable Bit"] -pub type BID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type BID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LID` writer - End of Linked List Interrupt Disable Bit"] -pub type LID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type LID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DID` writer - End of Disable Interrupt Disable Bit"] -pub type DID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type DID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FID` writer - End of Flush Interrupt Disable Bit"] -pub type FID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type FID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RBEID` writer - Read Bus Error Interrupt Disable Bit"] -pub type RBEID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type RBEID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WBEID` writer - Write Bus Error Interrupt Disable Bit"] -pub type WBEID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type WBEID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROID` writer - Request Overflow Error Interrupt Disable Bit"] -pub type ROID_W<'a, const O: u8> = crate::BitWriter<'a, CID_SPEC, O>; +pub type ROID_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - End of Block Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn bid(&mut self) -> BID_W<0> { + pub fn bid(&mut self) -> BID_W { BID_W::new(self) } #[doc = "Bit 1 - End of Linked List Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn lid(&mut self) -> LID_W<1> { + pub fn lid(&mut self) -> LID_W { LID_W::new(self) } #[doc = "Bit 2 - End of Disable Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn did(&mut self) -> DID_W<2> { + pub fn did(&mut self) -> DID_W { DID_W::new(self) } #[doc = "Bit 3 - End of Flush Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn fid(&mut self) -> FID_W<3> { + pub fn fid(&mut self) -> FID_W { FID_W::new(self) } #[doc = "Bit 4 - Read Bus Error Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn rbeid(&mut self) -> RBEID_W<4> { + pub fn rbeid(&mut self) -> RBEID_W { RBEID_W::new(self) } #[doc = "Bit 5 - Write Bus Error Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn wbeid(&mut self) -> WBEID_W<5> { + pub fn wbeid(&mut self) -> WBEID_W { WBEID_W::new(self) } #[doc = "Bit 6 - Request Overflow Error Interrupt Disable Bit"] #[inline(always)] #[must_use] - pub fn roid(&mut self) -> ROID_W<6> { + pub fn roid(&mut self) -> ROID_W { ROID_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Interrupt Disable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid](index.html) module"] +#[doc = "Channel Interrupt Disable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cid::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CID_SPEC; impl crate::RegisterSpec for CID_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cid::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cid::W`](W) writer structure"] impl crate::Writable for CID_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cie.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cie.rs index 414ba674..46fa7524 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cie.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cie.rs @@ -1,96 +1,76 @@ #[doc = "Register `CIE` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `BIE` writer - End of Block Interrupt Enable Bit"] -pub type BIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type BIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `LIE` writer - End of Linked List Interrupt Enable Bit"] -pub type LIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type LIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `DIE` writer - End of Disable Interrupt Enable Bit"] -pub type DIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type DIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `FIE` writer - End of Flush Interrupt Enable Bit"] -pub type FIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type FIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `RBIE` writer - Read Bus Error Interrupt Enable Bit"] -pub type RBIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type RBIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `WBIE` writer - Write Bus Error Interrupt Enable Bit"] -pub type WBIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type WBIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `ROIE` writer - Request Overflow Error Interrupt Enable Bit"] -pub type ROIE_W<'a, const O: u8> = crate::BitWriter<'a, CIE_SPEC, O>; +pub type ROIE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; impl W { #[doc = "Bit 0 - End of Block Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn bie(&mut self) -> BIE_W<0> { + pub fn bie(&mut self) -> BIE_W { BIE_W::new(self) } #[doc = "Bit 1 - End of Linked List Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn lie(&mut self) -> LIE_W<1> { + pub fn lie(&mut self) -> LIE_W { LIE_W::new(self) } #[doc = "Bit 2 - End of Disable Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn die(&mut self) -> DIE_W<2> { + pub fn die(&mut self) -> DIE_W { DIE_W::new(self) } #[doc = "Bit 3 - End of Flush Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn fie(&mut self) -> FIE_W<3> { + pub fn fie(&mut self) -> FIE_W { FIE_W::new(self) } #[doc = "Bit 4 - Read Bus Error Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn rbie(&mut self) -> RBIE_W<4> { + pub fn rbie(&mut self) -> RBIE_W { RBIE_W::new(self) } #[doc = "Bit 5 - Write Bus Error Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn wbie(&mut self) -> WBIE_W<5> { + pub fn wbie(&mut self) -> WBIE_W { WBIE_W::new(self) } #[doc = "Bit 6 - Request Overflow Error Interrupt Enable Bit"] #[inline(always)] #[must_use] - pub fn roie(&mut self) -> ROIE_W<6> { + pub fn roie(&mut self) -> ROIE_W { ROIE_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Interrupt Enable Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cie](index.html) module"] +#[doc = "Channel Interrupt Enable Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cie::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIE_SPEC; impl crate::RegisterSpec for CIE_SPEC { type Ux = u32; } -#[doc = "`write(|w| ..)` method takes [cie::W](W) writer structure"] +#[doc = "`write(|w| ..)` method takes [`cie::W`](W) writer structure"] impl crate::Writable for CIE_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cim.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cim.rs index 05060d04..32980254 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cim.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cim.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIM` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BIM` reader - End of Block Interrupt Mask Bit"] pub type BIM_R = crate::BitReader; #[doc = "Field `LIM` reader - End of Linked List Interrupt Mask Bit"] @@ -64,15 +51,13 @@ impl R { ROIM_R::new(((self.bits >> 6) & 1) != 0) } } -#[doc = "Channel Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cim](index.html) module"] +#[doc = "Channel Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cim::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIM_SPEC; impl crate::RegisterSpec for CIM_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cim::R](R) reader structure"] -impl crate::Readable for CIM_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cim::R`](R) reader structure"] +impl crate::Readable for CIM_SPEC {} #[doc = "`reset()` method sets CIM to value 0"] impl crate::Resettable for CIM_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cis.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cis.rs index 84a4e20e..a3999119 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cis.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cis.rs @@ -1,18 +1,5 @@ #[doc = "Register `CIS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Field `BIS` reader - End of Block Interrupt Status Bit"] pub type BIS_R = crate::BitReader; #[doc = "Field `LIS` reader - End of Linked List Interrupt Status Bit"] @@ -64,15 +51,13 @@ impl R { ROIS_R::new(((self.bits >> 6) & 1) != 0) } } -#[doc = "Channel Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cis](index.html) module"] +#[doc = "Channel Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CIS_SPEC; impl crate::RegisterSpec for CIS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cis::R](R) reader structure"] -impl crate::Readable for CIS_SPEC { - type Reader = R; -} +#[doc = "`read()` method returns [`cis::R`](R) reader structure"] +impl crate::Readable for CIS_SPEC {} #[doc = "`reset()` method sets CIS to value 0"] impl crate::Resettable for CIS_SPEC { const RESET_VALUE: Self::Ux = 0; diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cnda.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cnda.rs index 02bf0372..5b60a85a 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cnda.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cnda.rs @@ -1,47 +1,15 @@ #[doc = "Register `CNDA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNDA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NDAIF` reader - Channel x Next Descriptor Interface"] pub type NDAIF_R = crate::BitReader; #[doc = "Field `NDAIF` writer - Channel x Next Descriptor Interface"] -pub type NDAIF_W<'a, const O: u8> = crate::BitWriter<'a, CNDA_SPEC, O>; +pub type NDAIF_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>; #[doc = "Field `NDA` reader - Channel x Next Descriptor Address"] pub type NDA_R = crate::FieldReader; #[doc = "Field `NDA` writer - Channel x Next Descriptor Address"] -pub type NDA_W<'a, const O: u8> = crate::FieldWriter<'a, CNDA_SPEC, 30, O, u32>; +pub type NDA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 30, O, u32>; impl R { #[doc = "Bit 0 - Channel x Next Descriptor Interface"] #[inline(always)] @@ -58,34 +26,31 @@ impl W { #[doc = "Bit 0 - Channel x Next Descriptor Interface"] #[inline(always)] #[must_use] - pub fn ndaif(&mut self) -> NDAIF_W<0> { + pub fn ndaif(&mut self) -> NDAIF_W { NDAIF_W::new(self) } #[doc = "Bits 2:31 - Channel x Next Descriptor Address"] #[inline(always)] #[must_use] - pub fn nda(&mut self) -> NDA_W<2> { + pub fn nda(&mut self) -> NDA_W { NDA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Next Descriptor Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cnda](index.html) module"] +#[doc = "Channel Next Descriptor Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnda::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnda::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNDA_SPEC; impl crate::RegisterSpec for CNDA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cnda::R](R) reader structure"] -impl crate::Readable for CNDA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cnda::W](W) writer structure"] +#[doc = "`read()` method returns [`cnda::R`](R) reader structure"] +impl crate::Readable for CNDA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cnda::W`](W) writer structure"] impl crate::Writable for CNDA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cndc.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cndc.rs index 6920c20f..06ac03ff 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cndc.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cndc.rs @@ -1,39 +1,7 @@ #[doc = "Register `CNDC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CNDC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `NDE` reader - Channel x Next Descriptor Enable"] pub type NDE_R = crate::BitReader; #[doc = "Channel x Next Descriptor Enable\n\nValue on reset: 0"] @@ -59,28 +27,31 @@ impl NDE_R { true => NDESELECT_A::DSCR_FETCH_EN, } } - #[doc = "Checks if the value of the field is `DSCR_FETCH_DIS`"] + #[doc = "Descriptor fetch is disabled."] #[inline(always)] pub fn is_dscr_fetch_dis(&self) -> bool { *self == NDESELECT_A::DSCR_FETCH_DIS } - #[doc = "Checks if the value of the field is `DSCR_FETCH_EN`"] + #[doc = "Descriptor fetch is enabled."] #[inline(always)] pub fn is_dscr_fetch_en(&self) -> bool { *self == NDESELECT_A::DSCR_FETCH_EN } } #[doc = "Field `NDE` writer - Channel x Next Descriptor Enable"] -pub type NDE_W<'a, const O: u8> = crate::BitWriter<'a, CNDC_SPEC, O, NDESELECT_A>; -impl<'a, const O: u8> NDE_W<'a, O> { +pub type NDE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, NDESELECT_A>; +impl<'a, REG, const O: u8> NDE_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Descriptor fetch is disabled."] #[inline(always)] - pub fn dscr_fetch_dis(self) -> &'a mut W { + pub fn dscr_fetch_dis(self) -> &'a mut crate::W { self.variant(NDESELECT_A::DSCR_FETCH_DIS) } #[doc = "Descriptor fetch is enabled."] #[inline(always)] - pub fn dscr_fetch_en(self) -> &'a mut W { + pub fn dscr_fetch_en(self) -> &'a mut crate::W { self.variant(NDESELECT_A::DSCR_FETCH_EN) } } @@ -109,28 +80,31 @@ impl NDSUP_R { true => NDSUPSELECT_A::SRC_PARAMS_UPDATED, } } - #[doc = "Checks if the value of the field is `SRC_PARAMS_UNCHANGED`"] + #[doc = "Source parameters remain unchanged."] #[inline(always)] pub fn is_src_params_unchanged(&self) -> bool { *self == NDSUPSELECT_A::SRC_PARAMS_UNCHANGED } - #[doc = "Checks if the value of the field is `SRC_PARAMS_UPDATED`"] + #[doc = "Source parameters are updated when the descriptor is retrieved."] #[inline(always)] pub fn is_src_params_updated(&self) -> bool { *self == NDSUPSELECT_A::SRC_PARAMS_UPDATED } } #[doc = "Field `NDSUP` writer - Channel x Next Descriptor Source Update"] -pub type NDSUP_W<'a, const O: u8> = crate::BitWriter<'a, CNDC_SPEC, O, NDSUPSELECT_A>; -impl<'a, const O: u8> NDSUP_W<'a, O> { +pub type NDSUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, NDSUPSELECT_A>; +impl<'a, REG, const O: u8> NDSUP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Source parameters remain unchanged."] #[inline(always)] - pub fn src_params_unchanged(self) -> &'a mut W { + pub fn src_params_unchanged(self) -> &'a mut crate::W { self.variant(NDSUPSELECT_A::SRC_PARAMS_UNCHANGED) } #[doc = "Source parameters are updated when the descriptor is retrieved."] #[inline(always)] - pub fn src_params_updated(self) -> &'a mut W { + pub fn src_params_updated(self) -> &'a mut crate::W { self.variant(NDSUPSELECT_A::SRC_PARAMS_UPDATED) } } @@ -159,28 +133,31 @@ impl NDDUP_R { true => NDDUPSELECT_A::DST_PARAMS_UPDATED, } } - #[doc = "Checks if the value of the field is `DST_PARAMS_UNCHANGED`"] + #[doc = "Destination parameters remain unchanged."] #[inline(always)] pub fn is_dst_params_unchanged(&self) -> bool { *self == NDDUPSELECT_A::DST_PARAMS_UNCHANGED } - #[doc = "Checks if the value of the field is `DST_PARAMS_UPDATED`"] + #[doc = "Destination parameters are updated when the descriptor is retrieved."] #[inline(always)] pub fn is_dst_params_updated(&self) -> bool { *self == NDDUPSELECT_A::DST_PARAMS_UPDATED } } #[doc = "Field `NDDUP` writer - Channel x Next Descriptor Destination Update"] -pub type NDDUP_W<'a, const O: u8> = crate::BitWriter<'a, CNDC_SPEC, O, NDDUPSELECT_A>; -impl<'a, const O: u8> NDDUP_W<'a, O> { +pub type NDDUP_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O, NDDUPSELECT_A>; +impl<'a, REG, const O: u8> NDDUP_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, +{ #[doc = "Destination parameters remain unchanged."] #[inline(always)] - pub fn dst_params_unchanged(self) -> &'a mut W { + pub fn dst_params_unchanged(self) -> &'a mut crate::W { self.variant(NDDUPSELECT_A::DST_PARAMS_UNCHANGED) } #[doc = "Destination parameters are updated when the descriptor is retrieved."] #[inline(always)] - pub fn dst_params_updated(self) -> &'a mut W { + pub fn dst_params_updated(self) -> &'a mut crate::W { self.variant(NDDUPSELECT_A::DST_PARAMS_UPDATED) } } @@ -220,48 +197,52 @@ impl NDVIEW_R { _ => unreachable!(), } } - #[doc = "Checks if the value of the field is `NDV0`"] + #[doc = "Next Descriptor View 0"] #[inline(always)] pub fn is_ndv0(&self) -> bool { *self == NDVIEWSELECT_A::NDV0 } - #[doc = "Checks if the value of the field is `NDV1`"] + #[doc = "Next Descriptor View 1"] #[inline(always)] pub fn is_ndv1(&self) -> bool { *self == NDVIEWSELECT_A::NDV1 } - #[doc = "Checks if the value of the field is `NDV2`"] + #[doc = "Next Descriptor View 2"] #[inline(always)] pub fn is_ndv2(&self) -> bool { *self == NDVIEWSELECT_A::NDV2 } - #[doc = "Checks if the value of the field is `NDV3`"] + #[doc = "Next Descriptor View 3"] #[inline(always)] pub fn is_ndv3(&self) -> bool { *self == NDVIEWSELECT_A::NDV3 } } #[doc = "Field `NDVIEW` writer - Channel x Next Descriptor View"] -pub type NDVIEW_W<'a, const O: u8> = crate::FieldWriterSafe<'a, CNDC_SPEC, 2, O, NDVIEWSELECT_A>; -impl<'a, const O: u8> NDVIEW_W<'a, O> { +pub type NDVIEW_W<'a, REG, const O: u8> = crate::FieldWriterSafe<'a, REG, 2, O, NDVIEWSELECT_A>; +impl<'a, REG, const O: u8> NDVIEW_W<'a, REG, O> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ #[doc = "Next Descriptor View 0"] #[inline(always)] - pub fn ndv0(self) -> &'a mut W { + pub fn ndv0(self) -> &'a mut crate::W { self.variant(NDVIEWSELECT_A::NDV0) } #[doc = "Next Descriptor View 1"] #[inline(always)] - pub fn ndv1(self) -> &'a mut W { + pub fn ndv1(self) -> &'a mut crate::W { self.variant(NDVIEWSELECT_A::NDV1) } #[doc = "Next Descriptor View 2"] #[inline(always)] - pub fn ndv2(self) -> &'a mut W { + pub fn ndv2(self) -> &'a mut crate::W { self.variant(NDVIEWSELECT_A::NDV2) } #[doc = "Next Descriptor View 3"] #[inline(always)] - pub fn ndv3(self) -> &'a mut W { + pub fn ndv3(self) -> &'a mut crate::W { self.variant(NDVIEWSELECT_A::NDV3) } } @@ -291,46 +272,43 @@ impl W { #[doc = "Bit 0 - Channel x Next Descriptor Enable"] #[inline(always)] #[must_use] - pub fn nde(&mut self) -> NDE_W<0> { + pub fn nde(&mut self) -> NDE_W { NDE_W::new(self) } #[doc = "Bit 1 - Channel x Next Descriptor Source Update"] #[inline(always)] #[must_use] - pub fn ndsup(&mut self) -> NDSUP_W<1> { + pub fn ndsup(&mut self) -> NDSUP_W { NDSUP_W::new(self) } #[doc = "Bit 2 - Channel x Next Descriptor Destination Update"] #[inline(always)] #[must_use] - pub fn nddup(&mut self) -> NDDUP_W<2> { + pub fn nddup(&mut self) -> NDDUP_W { NDDUP_W::new(self) } #[doc = "Bits 3:4 - Channel x Next Descriptor View"] #[inline(always)] #[must_use] - pub fn ndview(&mut self) -> NDVIEW_W<3> { + pub fn ndview(&mut self) -> NDVIEW_W { NDVIEW_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Next Descriptor Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cndc](index.html) module"] +#[doc = "Channel Next Descriptor Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cndc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cndc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CNDC_SPEC; impl crate::RegisterSpec for CNDC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cndc::R](R) reader structure"] -impl crate::Readable for CNDC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cndc::W](W) writer structure"] +#[doc = "`read()` method returns [`cndc::R`](R) reader structure"] +impl crate::Readable for CNDC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cndc::W`](W) writer structure"] impl crate::Writable for CNDC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csa.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csa.rs index 98acb7aa..34337cbd 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csa.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csa.rs @@ -1,43 +1,11 @@ #[doc = "Register `CSA` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSA` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SA` reader - Channel x Source Address"] pub type SA_R = crate::FieldReader; #[doc = "Field `SA` writer - Channel x Source Address"] -pub type SA_W<'a, const O: u8> = crate::FieldWriter<'a, CSA_SPEC, 32, O, u32>; +pub type SA_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 32, O, u32>; impl R { #[doc = "Bits 0:31 - Channel x Source Address"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:31 - Channel x Source Address"] #[inline(always)] #[must_use] - pub fn sa(&mut self) -> SA_W<0> { + pub fn sa(&mut self) -> SA_W { SA_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Source Address Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csa](index.html) module"] +#[doc = "Channel Source Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csa::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSA_SPEC; impl crate::RegisterSpec for CSA_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [csa::R](R) reader structure"] -impl crate::Readable for CSA_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [csa::W](W) writer structure"] +#[doc = "`read()` method returns [`csa::R`](R) reader structure"] +impl crate::Readable for CSA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csa::W`](W) writer structure"] impl crate::Writable for CSA_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csus.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csus.rs index 92c0475d..2d40defd 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csus.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/csus.rs @@ -1,43 +1,11 @@ #[doc = "Register `CSUS` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CSUS` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `SUBS` reader - Channel x Source Microblock Stride"] pub type SUBS_R = crate::FieldReader; #[doc = "Field `SUBS` writer - Channel x Source Microblock Stride"] -pub type SUBS_W<'a, const O: u8> = crate::FieldWriter<'a, CSUS_SPEC, 24, O, u32>; +pub type SUBS_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Channel x Source Microblock Stride"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Channel x Source Microblock Stride"] #[inline(always)] #[must_use] - pub fn subs(&mut self) -> SUBS_W<0> { + pub fn subs(&mut self) -> SUBS_W { SUBS_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Source Microblock Stride\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csus](index.html) module"] +#[doc = "Channel Source Microblock Stride\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csus::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csus::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CSUS_SPEC; impl crate::RegisterSpec for CSUS_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [csus::R](R) reader structure"] -impl crate::Readable for CSUS_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [csus::W](W) writer structure"] +#[doc = "`read()` method returns [`csus::R`](R) reader structure"] +impl crate::Readable for CSUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csus::W`](W) writer structure"] impl crate::Writable for CSUS_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } diff --git a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cubc.rs b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cubc.rs index b119b721..be09d89e 100644 --- a/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cubc.rs +++ b/arch/cortex-m/samv71q21-pac/src/xdmac/xdmac_chid/cubc.rs @@ -1,43 +1,11 @@ #[doc = "Register `CUBC` reader"] -pub struct R(crate::R); -impl core::ops::Deref for R { - type Target = crate::R; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl From> for R { - #[inline(always)] - fn from(reader: crate::R) -> Self { - R(reader) - } -} +pub type R = crate::R; #[doc = "Register `CUBC` writer"] -pub struct W(crate::W); -impl core::ops::Deref for W { - type Target = crate::W; - #[inline(always)] - fn deref(&self) -> &Self::Target { - &self.0 - } -} -impl core::ops::DerefMut for W { - #[inline(always)] - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} -impl From> for W { - #[inline(always)] - fn from(writer: crate::W) -> Self { - W(writer) - } -} +pub type W = crate::W; #[doc = "Field `UBLEN` reader - Channel x Microblock Length"] pub type UBLEN_R = crate::FieldReader; #[doc = "Field `UBLEN` writer - Channel x Microblock Length"] -pub type UBLEN_W<'a, const O: u8> = crate::FieldWriter<'a, CUBC_SPEC, 24, O, u32>; +pub type UBLEN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 24, O, u32>; impl R { #[doc = "Bits 0:23 - Channel x Microblock Length"] #[inline(always)] @@ -49,28 +17,25 @@ impl W { #[doc = "Bits 0:23 - Channel x Microblock Length"] #[inline(always)] #[must_use] - pub fn ublen(&mut self) -> UBLEN_W<0> { + pub fn ublen(&mut self) -> UBLEN_W { UBLEN_W::new(self) } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.0.bits(bits); + self.bits = bits; self } } -#[doc = "Channel Microblock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cubc](index.html) module"] +#[doc = "Channel Microblock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cubc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cubc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] pub struct CUBC_SPEC; impl crate::RegisterSpec for CUBC_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [cubc::R](R) reader structure"] -impl crate::Readable for CUBC_SPEC { - type Reader = R; -} -#[doc = "`write(|w| ..)` method takes [cubc::W](W) writer structure"] +#[doc = "`read()` method returns [`cubc::R`](R) reader structure"] +impl crate::Readable for CUBC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cubc::W`](W) writer structure"] impl crate::Writable for CUBC_SPEC { - type Writer = W; const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; } From f1431e288fa522d7a39011165621f23be7b44214 Mon Sep 17 00:00:00 2001 From: Wojciech Olech Date: Mon, 4 Sep 2023 09:38:01 +0200 Subject: [PATCH 2/3] PAC: Removed `private_in_public` as it's been removed from Rust --- arch/cortex-m/samv71q21-pac/src/lib.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/cortex-m/samv71q21-pac/src/lib.rs b/arch/cortex-m/samv71q21-pac/src/lib.rs index 79ff81a7..71ddf720 100644 --- a/arch/cortex-m/samv71q21-pac/src/lib.rs +++ b/arch/cortex-m/samv71q21-pac/src/lib.rs @@ -8,7 +8,6 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] -#![deny(private_in_public)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] From 577733d28dbd6f64cc11c319e88ab992a2403d14 Mon Sep 17 00:00:00 2001 From: Wojciech Olech Date: Mon, 4 Sep 2023 10:32:14 +0200 Subject: [PATCH 3/3] PAC: Replaced removed lints and fixed doc links --- arch/cortex-m/samv71q21-pac/src/lib.rs | 2 ++ arch/cortex-m/samv71q21-pac/src/mcan0.rs | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/cortex-m/samv71q21-pac/src/lib.rs b/arch/cortex-m/samv71q21-pac/src/lib.rs index 71ddf720..583ea5eb 100644 --- a/arch/cortex-m/samv71q21-pac/src/lib.rs +++ b/arch/cortex-m/samv71q21-pac/src/lib.rs @@ -8,6 +8,8 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![deny(overflowing_literals)] #![deny(path_statements)] #![deny(patterns_in_fns_without_body)] +#![deny(private_interfaces)] +#![deny(private_bounds)] #![deny(unconditional_recursion)] #![deny(unused_allocation)] #![deny(unused_comparisons)] diff --git a/arch/cortex-m/samv71q21-pac/src/mcan0.rs b/arch/cortex-m/samv71q21-pac/src/mcan0.rs index 630bbf1e..29169ffc 100644 --- a/arch/cortex-m/samv71q21-pac/src/mcan0.rs +++ b/arch/cortex-m/samv71q21-pac/src/mcan0.rs @@ -121,7 +121,7 @@ module"] pub type DBTP = crate::Reg; #[doc = "Data Bit Timing and Prescaler Register"] pub mod dbtp; -#[doc = "TEST (rw) register accessor: Test Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`test`] +#[doc = "TEST (rw) register accessor: Test Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get `@test::R`, You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using `test::W`. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@test`] module"] pub type TEST = crate::Reg; #[doc = "Test Register"]