From 2de0018384197bab9910d921b3c8506df56e4a6e Mon Sep 17 00:00:00 2001
From: Wojciech Olech <wojciech_olech@hotmail.com>
Date: Thu, 19 Oct 2023 10:55:50 +0200
Subject: [PATCH] UART: Documentation tweaks

Co-authored-by: Filip Demski (Glamhoth) <Glamhoth@users.noreply.github.com>
---
 arch/cortex-m/samv71-hal/src/uart/reader.rs | 1 +
 arch/cortex-m/samv71-hal/src/uart/writer.rs | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/cortex-m/samv71-hal/src/uart/reader.rs b/arch/cortex-m/samv71-hal/src/uart/reader.rs
index 1cad5bf8..8836f90f 100644
--- a/arch/cortex-m/samv71-hal/src/uart/reader.rs
+++ b/arch/cortex-m/samv71-hal/src/uart/reader.rs
@@ -84,6 +84,7 @@ impl<Instance: UARTMetadata> Reader<Instance> {
     }
 
     /// Resets UART status by clearing status flags.
+    ///
     /// **This function should usually be called immediately after reading the status.**
     #[inline(always)]
     pub fn reset_status(&mut self) {
diff --git a/arch/cortex-m/samv71-hal/src/uart/writer.rs b/arch/cortex-m/samv71-hal/src/uart/writer.rs
index b5409a85..2c4365c3 100644
--- a/arch/cortex-m/samv71-hal/src/uart/writer.rs
+++ b/arch/cortex-m/samv71-hal/src/uart/writer.rs
@@ -30,6 +30,7 @@ pub struct Writer<Instance: UARTMetadata> {
 
 impl<Instance: UARTMetadata> Writer<Instance> {
     /// Transmits a single byte.
+    ///
     /// Waits for UART TX register to be empty.
     /// Does not wait until transmission is completed, use [`Writer::flush`] if you want to make sure
     /// of that.