From 8513af09430765c73d419278ac7906a7f10ab0e9 Mon Sep 17 00:00:00 2001 From: Dominykas Date: Fri, 17 May 2024 09:32:57 +0300 Subject: [PATCH 1/4] Fix a potential Static Initialization Order Fiasco --- .../LMS7002MCSR_To_LMS7002MCSR_Data.cpp | 1514 ++++++++--------- 1 file changed, 757 insertions(+), 757 deletions(-) diff --git a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp index fbeb411c..18982061 100644 --- a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp +++ b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp @@ -5,768 +5,768 @@ namespace lime { -static const std::unordered_map LMS7002MCSR_map = { - { LMS7002MCSR::LRST_TX_B, &LMS7002MCSR_Data::LRST_TX_B }, - { LMS7002MCSR::MRST_TX_B, &LMS7002MCSR_Data::MRST_TX_B }, - { LMS7002MCSR::LRST_TX_A, &LMS7002MCSR_Data::LRST_TX_A }, - { LMS7002MCSR::MRST_TX_A, &LMS7002MCSR_Data::MRST_TX_A }, - { LMS7002MCSR::LRST_RX_B, &LMS7002MCSR_Data::LRST_RX_B }, - { LMS7002MCSR::MRST_RX_B, &LMS7002MCSR_Data::MRST_RX_B }, - { LMS7002MCSR::LRST_RX_A, &LMS7002MCSR_Data::LRST_RX_A }, - { LMS7002MCSR::MRST_RX_A, &LMS7002MCSR_Data::MRST_RX_A }, - { LMS7002MCSR::SRST_RXFIFO, &LMS7002MCSR_Data::SRST_RXFIFO }, - { LMS7002MCSR::SRST_TXFIFO, &LMS7002MCSR_Data::SRST_TXFIFO }, - { LMS7002MCSR::RXEN_B, &LMS7002MCSR_Data::RXEN_B }, - { LMS7002MCSR::RXEN_A, &LMS7002MCSR_Data::RXEN_A }, - { LMS7002MCSR::TXEN_B, &LMS7002MCSR_Data::TXEN_B }, - { LMS7002MCSR::TXEN_A, &LMS7002MCSR_Data::TXEN_A }, - { LMS7002MCSR::MAC, &LMS7002MCSR_Data::MAC }, - { LMS7002MCSR::TX_CLK_PE, &LMS7002MCSR_Data::TX_CLK_PE }, - { LMS7002MCSR::RX_CLK_PE, &LMS7002MCSR_Data::RX_CLK_PE }, - { LMS7002MCSR::SDA_PE, &LMS7002MCSR_Data::SDA_PE }, - { LMS7002MCSR::SDA_DS, &LMS7002MCSR_Data::SDA_DS }, - { LMS7002MCSR::SCL_PE, &LMS7002MCSR_Data::SCL_PE }, - { LMS7002MCSR::SCL_DS, &LMS7002MCSR_Data::SCL_DS }, - { LMS7002MCSR::SDIO_DS, &LMS7002MCSR_Data::SDIO_DS }, - { LMS7002MCSR::SDIO_PE, &LMS7002MCSR_Data::SDIO_PE }, - { LMS7002MCSR::SDO_PE, &LMS7002MCSR_Data::SDO_PE }, - { LMS7002MCSR::SCLK_PE, &LMS7002MCSR_Data::SCLK_PE }, - { LMS7002MCSR::SEN_PE, &LMS7002MCSR_Data::SEN_PE }, - { LMS7002MCSR::SPIMODE, &LMS7002MCSR_Data::SPIMODE }, - { LMS7002MCSR::DIQ2_DS, &LMS7002MCSR_Data::DIQ2_DS }, - { LMS7002MCSR::DIQ2_PE, &LMS7002MCSR_Data::DIQ2_PE }, - { LMS7002MCSR::IQ_SEL_EN_2_PE, &LMS7002MCSR_Data::IQ_SEL_EN_2_PE }, - { LMS7002MCSR::TXNRX2_PE, &LMS7002MCSR_Data::TXNRX2_PE }, - { LMS7002MCSR::FCLK2_PE, &LMS7002MCSR_Data::FCLK2_PE }, - { LMS7002MCSR::MCLK2_PE, &LMS7002MCSR_Data::MCLK2_PE }, - { LMS7002MCSR::DIQ1_DS, &LMS7002MCSR_Data::DIQ1_DS }, - { LMS7002MCSR::DIQ1_PE, &LMS7002MCSR_Data::DIQ1_PE }, - { LMS7002MCSR::IQ_SEL_EN_1_PE, &LMS7002MCSR_Data::IQ_SEL_EN_1_PE }, - { LMS7002MCSR::TXNRX1_PE, &LMS7002MCSR_Data::TXNRX1_PE }, - { LMS7002MCSR::FCLK1_PE, &LMS7002MCSR_Data::FCLK1_PE }, - { LMS7002MCSR::MCLK1_PE, &LMS7002MCSR_Data::MCLK1_PE }, - { LMS7002MCSR::DIQDIRCTR2, &LMS7002MCSR_Data::DIQDIRCTR2 }, - { LMS7002MCSR::DIQDIR2, &LMS7002MCSR_Data::DIQDIR2 }, - { LMS7002MCSR::DIQDIRCTR1, &LMS7002MCSR_Data::DIQDIRCTR1 }, - { LMS7002MCSR::DIQDIR1, &LMS7002MCSR_Data::DIQDIR1 }, - { LMS7002MCSR::ENABLEDIRCTR2, &LMS7002MCSR_Data::ENABLEDIRCTR2 }, - { LMS7002MCSR::ENABLEDIR2, &LMS7002MCSR_Data::ENABLEDIR2 }, - { LMS7002MCSR::ENABLEDIRCTR1, &LMS7002MCSR_Data::ENABLEDIRCTR1 }, - { LMS7002MCSR::ENABLEDIR1, &LMS7002MCSR_Data::ENABLEDIR1 }, - { LMS7002MCSR::MOD_EN, &LMS7002MCSR_Data::MOD_EN }, - { LMS7002MCSR::LML2_FIDM, &LMS7002MCSR_Data::LML2_FIDM }, - { LMS7002MCSR::LML2_TXNRXIQ, &LMS7002MCSR_Data::LML2_TXNRXIQ }, - { LMS7002MCSR::LML2_MODE, &LMS7002MCSR_Data::LML2_MODE }, - { LMS7002MCSR::LML1_FIDM, &LMS7002MCSR_Data::LML1_FIDM }, - { LMS7002MCSR::LML1_TXNRXIQ, &LMS7002MCSR_Data::LML1_TXNRXIQ }, - { LMS7002MCSR::LML1_MODE, &LMS7002MCSR_Data::LML1_MODE }, - { LMS7002MCSR::LML1_S3S, &LMS7002MCSR_Data::LML1_S3S }, - { LMS7002MCSR::LML1_S2S, &LMS7002MCSR_Data::LML1_S2S }, - { LMS7002MCSR::LML1_S1S, &LMS7002MCSR_Data::LML1_S1S }, - { LMS7002MCSR::LML1_S0S, &LMS7002MCSR_Data::LML1_S0S }, - { LMS7002MCSR::LML1_BQP, &LMS7002MCSR_Data::LML1_BQP }, - { LMS7002MCSR::LML1_BIP, &LMS7002MCSR_Data::LML1_BIP }, - { LMS7002MCSR::LML1_AQP, &LMS7002MCSR_Data::LML1_AQP }, - { LMS7002MCSR::LML1_AIP, &LMS7002MCSR_Data::LML1_AIP }, - { LMS7002MCSR::LML1_BB2RF_PST, &LMS7002MCSR_Data::LML1_BB2RF_PST }, - { LMS7002MCSR::LML1_BB2RF_PRE, &LMS7002MCSR_Data::LML1_BB2RF_PRE }, - { LMS7002MCSR::LML1_RF2BB_PST, &LMS7002MCSR_Data::LML1_RF2BB_PST }, - { LMS7002MCSR::LML1_RF2BB_PRE, &LMS7002MCSR_Data::LML1_RF2BB_PRE }, - { LMS7002MCSR::LML2_S3S, &LMS7002MCSR_Data::LML2_S3S }, - { LMS7002MCSR::LML2_S2S, &LMS7002MCSR_Data::LML2_S2S }, - { LMS7002MCSR::LML2_S1S, &LMS7002MCSR_Data::LML2_S1S }, - { LMS7002MCSR::LML2_S0S, &LMS7002MCSR_Data::LML2_S0S }, - { LMS7002MCSR::LML2_BQP, &LMS7002MCSR_Data::LML2_BQP }, - { LMS7002MCSR::LML2_BIP, &LMS7002MCSR_Data::LML2_BIP }, - { LMS7002MCSR::LML2_AQP, &LMS7002MCSR_Data::LML2_AQP }, - { LMS7002MCSR::LML2_AIP, &LMS7002MCSR_Data::LML2_AIP }, - { LMS7002MCSR::LML2_BB2RF_PST, &LMS7002MCSR_Data::LML2_BB2RF_PST }, - { LMS7002MCSR::LML2_BB2RF_PRE, &LMS7002MCSR_Data::LML2_BB2RF_PRE }, - { LMS7002MCSR::LML2_RF2BB_PST, &LMS7002MCSR_Data::LML2_RF2BB_PST }, - { LMS7002MCSR::LML2_RF2BB_PRE, &LMS7002MCSR_Data::LML2_RF2BB_PRE }, - { LMS7002MCSR::FCLK2_DLY, &LMS7002MCSR_Data::FCLK2_DLY }, - { LMS7002MCSR::FCLK1_DLY, &LMS7002MCSR_Data::FCLK1_DLY }, - { LMS7002MCSR::RX_MUX, &LMS7002MCSR_Data::RX_MUX }, - { LMS7002MCSR::TX_MUX, &LMS7002MCSR_Data::TX_MUX }, - { LMS7002MCSR::TXRDCLK_MUX, &LMS7002MCSR_Data::TXRDCLK_MUX }, - { LMS7002MCSR::TXWRCLK_MUX, &LMS7002MCSR_Data::TXWRCLK_MUX }, - { LMS7002MCSR::RXRDCLK_MUX, &LMS7002MCSR_Data::RXRDCLK_MUX }, - { LMS7002MCSR::RXWRCLK_MUX, &LMS7002MCSR_Data::RXWRCLK_MUX }, - { LMS7002MCSR::FCLK2_INV, &LMS7002MCSR_Data::FCLK2_INV }, - { LMS7002MCSR::FCLK1_INV, &LMS7002MCSR_Data::FCLK1_INV }, - { LMS7002MCSR::MCLK2DLY, &LMS7002MCSR_Data::MCLK2DLY }, - { LMS7002MCSR::MCLK1DLY, &LMS7002MCSR_Data::MCLK1DLY }, - { LMS7002MCSR::MCLK2SRC, &LMS7002MCSR_Data::MCLK2SRC }, - { LMS7002MCSR::MCLK1SRC, &LMS7002MCSR_Data::MCLK1SRC }, - { LMS7002MCSR::TXDIVEN, &LMS7002MCSR_Data::TXDIVEN }, - { LMS7002MCSR::RXDIVEN, &LMS7002MCSR_Data::RXDIVEN }, - { LMS7002MCSR::TXTSPCLKA_DIV, &LMS7002MCSR_Data::TXTSPCLKA_DIV }, - { LMS7002MCSR::RXTSPCLKA_DIV, &LMS7002MCSR_Data::RXTSPCLKA_DIV }, - { LMS7002MCSR::MIMO_SISO, &LMS7002MCSR_Data::MIMO_SISO }, - { LMS7002MCSR::VER, &LMS7002MCSR_Data::VER }, - { LMS7002MCSR::REV, &LMS7002MCSR_Data::REV }, - { LMS7002MCSR::MASK, &LMS7002MCSR_Data::MASK }, - { LMS7002MCSR::EN_DIR_LDO, &LMS7002MCSR_Data::EN_DIR_LDO }, - { LMS7002MCSR::EN_DIR_CGEN, &LMS7002MCSR_Data::EN_DIR_CGEN }, - { LMS7002MCSR::EN_DIR_XBUF, &LMS7002MCSR_Data::EN_DIR_XBUF }, - { LMS7002MCSR::EN_DIR_AFE, &LMS7002MCSR_Data::EN_DIR_AFE }, - { LMS7002MCSR::ISEL_DAC_AFE, &LMS7002MCSR_Data::ISEL_DAC_AFE }, - { LMS7002MCSR::MODE_INTERLEAVE_AFE, &LMS7002MCSR_Data::MODE_INTERLEAVE_AFE }, - { LMS7002MCSR::MUX_AFE_1, &LMS7002MCSR_Data::MUX_AFE_1 }, - { LMS7002MCSR::MUX_AFE_2, &LMS7002MCSR_Data::MUX_AFE_2 }, - { LMS7002MCSR::PD_AFE, &LMS7002MCSR_Data::PD_AFE }, - { LMS7002MCSR::PD_RX_AFE1, &LMS7002MCSR_Data::PD_RX_AFE1 }, - { LMS7002MCSR::PD_RX_AFE2, &LMS7002MCSR_Data::PD_RX_AFE2 }, - { LMS7002MCSR::PD_TX_AFE1, &LMS7002MCSR_Data::PD_TX_AFE1 }, - { LMS7002MCSR::PD_TX_AFE2, &LMS7002MCSR_Data::PD_TX_AFE2 }, - { LMS7002MCSR::EN_G_AFE, &LMS7002MCSR_Data::EN_G_AFE }, - { LMS7002MCSR::MUX_BIAS_OUT, &LMS7002MCSR_Data::MUX_BIAS_OUT }, - { LMS7002MCSR::RP_CALIB_BIAS, &LMS7002MCSR_Data::RP_CALIB_BIAS }, - { LMS7002MCSR::PD_FRP_BIAS, &LMS7002MCSR_Data::PD_FRP_BIAS }, - { LMS7002MCSR::PD_F_BIAS, &LMS7002MCSR_Data::PD_F_BIAS }, - { LMS7002MCSR::PD_PTRP_BIAS, &LMS7002MCSR_Data::PD_PTRP_BIAS }, - { LMS7002MCSR::PD_PT_BIAS, &LMS7002MCSR_Data::PD_PT_BIAS }, - { LMS7002MCSR::PD_BIAS_MASTER, &LMS7002MCSR_Data::PD_BIAS_MASTER }, - { LMS7002MCSR::SLFB_XBUF_RX, &LMS7002MCSR_Data::SLFB_XBUF_RX }, - { LMS7002MCSR::SLFB_XBUF_TX, &LMS7002MCSR_Data::SLFB_XBUF_TX }, - { LMS7002MCSR::BYP_XBUF_RX, &LMS7002MCSR_Data::BYP_XBUF_RX }, - { LMS7002MCSR::BYP_XBUF_TX, &LMS7002MCSR_Data::BYP_XBUF_TX }, - { LMS7002MCSR::EN_OUT2_XBUF_TX, &LMS7002MCSR_Data::EN_OUT2_XBUF_TX }, - { LMS7002MCSR::EN_TBUFIN_XBUF_RX, &LMS7002MCSR_Data::EN_TBUFIN_XBUF_RX }, - { LMS7002MCSR::PD_XBUF_RX, &LMS7002MCSR_Data::PD_XBUF_RX }, - { LMS7002MCSR::PD_XBUF_TX, &LMS7002MCSR_Data::PD_XBUF_TX }, - { LMS7002MCSR::EN_G_XBUF, &LMS7002MCSR_Data::EN_G_XBUF }, - { LMS7002MCSR::SPDUP_VCO_CGEN, &LMS7002MCSR_Data::SPDUP_VCO_CGEN }, - { LMS7002MCSR::RESET_N_CGEN, &LMS7002MCSR_Data::RESET_N_CGEN }, - { LMS7002MCSR::EN_ADCCLKH_CLKGN, &LMS7002MCSR_Data::EN_ADCCLKH_CLKGN }, - { LMS7002MCSR::EN_COARSE_CKLGEN, &LMS7002MCSR_Data::EN_COARSE_CKLGEN }, - { LMS7002MCSR::EN_INTONLY_SDM_CGEN, &LMS7002MCSR_Data::EN_INTONLY_SDM_CGEN }, - { LMS7002MCSR::EN_SDM_CLK_CGEN, &LMS7002MCSR_Data::EN_SDM_CLK_CGEN }, - { LMS7002MCSR::PD_CP_CGEN, &LMS7002MCSR_Data::PD_CP_CGEN }, - { LMS7002MCSR::PD_FDIV_FB_CGEN, &LMS7002MCSR_Data::PD_FDIV_FB_CGEN }, - { LMS7002MCSR::PD_FDIV_O_CGEN, &LMS7002MCSR_Data::PD_FDIV_O_CGEN }, - { LMS7002MCSR::PD_SDM_CGEN, &LMS7002MCSR_Data::PD_SDM_CGEN }, - { LMS7002MCSR::PD_VCO_CGEN, &LMS7002MCSR_Data::PD_VCO_CGEN }, - { LMS7002MCSR::PD_VCO_COMP_CGEN, &LMS7002MCSR_Data::PD_VCO_COMP_CGEN }, - { LMS7002MCSR::EN_G_CGEN, &LMS7002MCSR_Data::EN_G_CGEN }, - { LMS7002MCSR::FRAC_SDM_CGEN_LSB, &LMS7002MCSR_Data::FRAC_SDM_CGEN_LSB }, - { LMS7002MCSR::INT_SDM_CGEN, &LMS7002MCSR_Data::INT_SDM_CGEN }, - { LMS7002MCSR::FRAC_SDM_CGEN_MSB, &LMS7002MCSR_Data::FRAC_SDM_CGEN_MSB }, - { LMS7002MCSR::REV_SDMCLK_CGEN, &LMS7002MCSR_Data::REV_SDMCLK_CGEN }, - { LMS7002MCSR::SEL_SDMCLK_CGEN, &LMS7002MCSR_Data::SEL_SDMCLK_CGEN }, - { LMS7002MCSR::SX_DITHER_EN_CGEN, &LMS7002MCSR_Data::SX_DITHER_EN_CGEN }, - { LMS7002MCSR::CLKH_OV_CLKL_CGEN, &LMS7002MCSR_Data::CLKH_OV_CLKL_CGEN }, - { LMS7002MCSR::DIV_OUTCH_CGEN, &LMS7002MCSR_Data::DIV_OUTCH_CGEN }, - { LMS7002MCSR::TST_CGEN, &LMS7002MCSR_Data::TST_CGEN }, - { LMS7002MCSR::REV_CLKDAC_CGEN, &LMS7002MCSR_Data::REV_CLKDAC_CGEN }, - { LMS7002MCSR::CMPLO_CTRL_CGEN, &LMS7002MCSR_Data::CMPLO_CTRL_CGEN }, - { LMS7002MCSR::REV_CLKADC_CGEN, &LMS7002MCSR_Data::REV_CLKADC_CGEN }, - { LMS7002MCSR::REVPH_PFD_CGEN, &LMS7002MCSR_Data::REVPH_PFD_CGEN }, - { LMS7002MCSR::IOFFSET_CP_CGEN, &LMS7002MCSR_Data::IOFFSET_CP_CGEN }, - { LMS7002MCSR::IPULSE_CP_CGEN, &LMS7002MCSR_Data::IPULSE_CP_CGEN }, - { LMS7002MCSR::ICT_VCO_CGEN, &LMS7002MCSR_Data::ICT_VCO_CGEN }, - { LMS7002MCSR::CSW_VCO_CGEN, &LMS7002MCSR_Data::CSW_VCO_CGEN }, - { LMS7002MCSR::COARSE_START_CGEN, &LMS7002MCSR_Data::COARSE_START_CGEN }, - { LMS7002MCSR::COARSE_STEPDONE_CGEN, &LMS7002MCSR_Data::COARSE_STEPDONE_CGEN }, - { LMS7002MCSR::COARSEPLL_COMPO_CGEN, &LMS7002MCSR_Data::COARSEPLL_COMPO_CGEN }, - { LMS7002MCSR::VCO_CMPHO_CGEN, &LMS7002MCSR_Data::VCO_CMPHO_CGEN }, - { LMS7002MCSR::VCO_CMPLO_CGEN, &LMS7002MCSR_Data::VCO_CMPLO_CGEN }, - { LMS7002MCSR::CP2_CGEN, &LMS7002MCSR_Data::CP2_CGEN }, - { LMS7002MCSR::CP3_CGEN, &LMS7002MCSR_Data::CP3_CGEN }, - { LMS7002MCSR::CZ_CGEN, &LMS7002MCSR_Data::CZ_CGEN }, - { LMS7002MCSR::EN_LDO_DIG, &LMS7002MCSR_Data::EN_LDO_DIG }, - { LMS7002MCSR::EN_LDO_DIGGN, &LMS7002MCSR_Data::EN_LDO_DIGGN }, - { LMS7002MCSR::EN_LDO_DIGSXR, &LMS7002MCSR_Data::EN_LDO_DIGSXR }, - { LMS7002MCSR::EN_LDO_DIGSXT, &LMS7002MCSR_Data::EN_LDO_DIGSXT }, - { LMS7002MCSR::EN_LDO_DIVGN, &LMS7002MCSR_Data::EN_LDO_DIVGN }, - { LMS7002MCSR::EN_LDO_DIVSXR, &LMS7002MCSR_Data::EN_LDO_DIVSXR }, - { LMS7002MCSR::EN_LDO_DIVSXT, &LMS7002MCSR_Data::EN_LDO_DIVSXT }, - { LMS7002MCSR::EN_LDO_LNA12, &LMS7002MCSR_Data::EN_LDO_LNA12 }, - { LMS7002MCSR::EN_LDO_LNA14, &LMS7002MCSR_Data::EN_LDO_LNA14 }, - { LMS7002MCSR::EN_LDO_MXRFE, &LMS7002MCSR_Data::EN_LDO_MXRFE }, - { LMS7002MCSR::EN_LDO_RBB, &LMS7002MCSR_Data::EN_LDO_RBB }, - { LMS7002MCSR::EN_LDO_RXBUF, &LMS7002MCSR_Data::EN_LDO_RXBUF }, - { LMS7002MCSR::EN_LDO_TBB, &LMS7002MCSR_Data::EN_LDO_TBB }, - { LMS7002MCSR::EN_LDO_TIA12, &LMS7002MCSR_Data::EN_LDO_TIA12 }, - { LMS7002MCSR::EN_LDO_TIA14, &LMS7002MCSR_Data::EN_LDO_TIA14 }, - { LMS7002MCSR::EN_G_LDO, &LMS7002MCSR_Data::EN_G_LDO }, - { LMS7002MCSR::EN_LOADIMP_LDO_TLOB, &LMS7002MCSR_Data::EN_LOADIMP_LDO_TLOB }, - { LMS7002MCSR::EN_LOADIMP_LDO_TPAD, &LMS7002MCSR_Data::EN_LOADIMP_LDO_TPAD }, - { LMS7002MCSR::EN_LOADIMP_LDO_TXBUF, &LMS7002MCSR_Data::EN_LOADIMP_LDO_TXBUF }, - { LMS7002MCSR::EN_LOADIMP_LDO_VCOGN, &LMS7002MCSR_Data::EN_LOADIMP_LDO_VCOGN }, - { LMS7002MCSR::EN_LOADIMP_LDO_VCOSXR, &LMS7002MCSR_Data::EN_LOADIMP_LDO_VCOSXR }, - { LMS7002MCSR::EN_LOADIMP_LDO_VCOSXT, &LMS7002MCSR_Data::EN_LOADIMP_LDO_VCOSXT }, - { LMS7002MCSR::EN_LDO_AFE, &LMS7002MCSR_Data::EN_LDO_AFE }, - { LMS7002MCSR::EN_LDO_CPGN, &LMS7002MCSR_Data::EN_LDO_CPGN }, - { LMS7002MCSR::EN_LDO_CPSXR, &LMS7002MCSR_Data::EN_LDO_CPSXR }, - { LMS7002MCSR::EN_LDO_TLOB, &LMS7002MCSR_Data::EN_LDO_TLOB }, - { LMS7002MCSR::EN_LDO_TPAD, &LMS7002MCSR_Data::EN_LDO_TPAD }, - { LMS7002MCSR::EN_LDO_TXBUF, &LMS7002MCSR_Data::EN_LDO_TXBUF }, - { LMS7002MCSR::EN_LDO_VCOGN, &LMS7002MCSR_Data::EN_LDO_VCOGN }, - { LMS7002MCSR::EN_LDO_VCOSXR, &LMS7002MCSR_Data::EN_LDO_VCOSXR }, - { LMS7002MCSR::EN_LDO_VCOSXT, &LMS7002MCSR_Data::EN_LDO_VCOSXT }, - { LMS7002MCSR::EN_LDO_CPSXT, &LMS7002MCSR_Data::EN_LDO_CPSXT }, - { LMS7002MCSR::EN_LOADIMP_LDO_CPSXT, &LMS7002MCSR_Data::EN_LOADIMP_LDO_CPSXT }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIG, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIG }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIGGN, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGGN }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIGSXR, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGSXR }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIGSXT, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGSXT }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIVGN, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIVGN }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIVSXR, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIVSXR }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIVSXT, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIVSXT }, - { LMS7002MCSR::EN_LOADIMP_LDO_LNA12, &LMS7002MCSR_Data::EN_LOADIMP_LDO_LNA12 }, - { LMS7002MCSR::EN_LOADIMP_LDO_LNA14, &LMS7002MCSR_Data::EN_LOADIMP_LDO_LNA14 }, - { LMS7002MCSR::EN_LOADIMP_LDO_MXRFE, &LMS7002MCSR_Data::EN_LOADIMP_LDO_MXRFE }, - { LMS7002MCSR::EN_LOADIMP_LDO_RBB, &LMS7002MCSR_Data::EN_LOADIMP_LDO_RBB }, - { LMS7002MCSR::EN_LOADIMP_LDO_RXBUF, &LMS7002MCSR_Data::EN_LOADIMP_LDO_RXBUF }, - { LMS7002MCSR::EN_LOADIMP_LDO_TBB, &LMS7002MCSR_Data::EN_LOADIMP_LDO_TBB }, - { LMS7002MCSR::EN_LOADIMP_LDO_TIA12, &LMS7002MCSR_Data::EN_LOADIMP_LDO_TIA12 }, - { LMS7002MCSR::EN_LOADIMP_LDO_TIA14, &LMS7002MCSR_Data::EN_LOADIMP_LDO_TIA14 }, - { LMS7002MCSR::BYP_LDO_TBB, &LMS7002MCSR_Data::BYP_LDO_TBB }, - { LMS7002MCSR::BYP_LDO_TIA12, &LMS7002MCSR_Data::BYP_LDO_TIA12 }, - { LMS7002MCSR::BYP_LDO_TIA14, &LMS7002MCSR_Data::BYP_LDO_TIA14 }, - { LMS7002MCSR::BYP_LDO_TLOB, &LMS7002MCSR_Data::BYP_LDO_TLOB }, - { LMS7002MCSR::BYP_LDO_TPAD, &LMS7002MCSR_Data::BYP_LDO_TPAD }, - { LMS7002MCSR::BYP_LDO_TXBUF, &LMS7002MCSR_Data::BYP_LDO_TXBUF }, - { LMS7002MCSR::BYP_LDO_VCOGN, &LMS7002MCSR_Data::BYP_LDO_VCOGN }, - { LMS7002MCSR::BYP_LDO_VCOSXR, &LMS7002MCSR_Data::BYP_LDO_VCOSXR }, - { LMS7002MCSR::BYP_LDO_VCOSXT, &LMS7002MCSR_Data::BYP_LDO_VCOSXT }, - { LMS7002MCSR::EN_LOADIMP_LDO_AFE, &LMS7002MCSR_Data::EN_LOADIMP_LDO_AFE }, - { LMS7002MCSR::EN_LOADIMP_LDO_CPGN, &LMS7002MCSR_Data::EN_LOADIMP_LDO_CPGN }, - { LMS7002MCSR::EN_LOADIMP_LDO_CPSXR, &LMS7002MCSR_Data::EN_LOADIMP_LDO_CPSXR }, - { LMS7002MCSR::BYP_LDO_AFE, &LMS7002MCSR_Data::BYP_LDO_AFE }, - { LMS7002MCSR::BYP_LDO_CPGN, &LMS7002MCSR_Data::BYP_LDO_CPGN }, - { LMS7002MCSR::BYP_LDO_CPSXR, &LMS7002MCSR_Data::BYP_LDO_CPSXR }, - { LMS7002MCSR::BYP_LDO_CPSXT, &LMS7002MCSR_Data::BYP_LDO_CPSXT }, - { LMS7002MCSR::BYP_LDO_DIG, &LMS7002MCSR_Data::BYP_LDO_DIG }, - { LMS7002MCSR::BYP_LDO_DIGGN, &LMS7002MCSR_Data::BYP_LDO_DIGGN }, - { LMS7002MCSR::BYP_LDO_DIGSXR, &LMS7002MCSR_Data::BYP_LDO_DIGSXR }, - { LMS7002MCSR::BYP_LDO_DIGSXT, &LMS7002MCSR_Data::BYP_LDO_DIGSXT }, - { LMS7002MCSR::BYP_LDO_DIVGN, &LMS7002MCSR_Data::BYP_LDO_DIVGN }, - { LMS7002MCSR::BYP_LDO_DIVSXR, &LMS7002MCSR_Data::BYP_LDO_DIVSXR }, - { LMS7002MCSR::BYP_LDO_DIVSXT, &LMS7002MCSR_Data::BYP_LDO_DIVSXT }, - { LMS7002MCSR::BYP_LDO_LNA12, &LMS7002MCSR_Data::BYP_LDO_LNA12 }, - { LMS7002MCSR::BYP_LDO_LNA14, &LMS7002MCSR_Data::BYP_LDO_LNA14 }, - { LMS7002MCSR::BYP_LDO_MXRFE, &LMS7002MCSR_Data::BYP_LDO_MXRFE }, - { LMS7002MCSR::BYP_LDO_RBB, &LMS7002MCSR_Data::BYP_LDO_RBB }, - { LMS7002MCSR::BYP_LDO_RXBUF, &LMS7002MCSR_Data::BYP_LDO_RXBUF }, - { LMS7002MCSR::SPDUP_LDO_DIVSXR, &LMS7002MCSR_Data::SPDUP_LDO_DIVSXR }, - { LMS7002MCSR::SPDUP_LDO_DIVSXT, &LMS7002MCSR_Data::SPDUP_LDO_DIVSXT }, - { LMS7002MCSR::SPDUP_LDO_LNA12, &LMS7002MCSR_Data::SPDUP_LDO_LNA12 }, - { LMS7002MCSR::SPDUP_LDO_LNA14, &LMS7002MCSR_Data::SPDUP_LDO_LNA14 }, - { LMS7002MCSR::SPDUP_LDO_MXRFE, &LMS7002MCSR_Data::SPDUP_LDO_MXRFE }, - { LMS7002MCSR::SPDUP_LDO_RBB, &LMS7002MCSR_Data::SPDUP_LDO_RBB }, - { LMS7002MCSR::SPDUP_LDO_RXBUF, &LMS7002MCSR_Data::SPDUP_LDO_RXBUF }, - { LMS7002MCSR::SPDUP_LDO_TBB, &LMS7002MCSR_Data::SPDUP_LDO_TBB }, - { LMS7002MCSR::SPDUP_LDO_TIA12, &LMS7002MCSR_Data::SPDUP_LDO_TIA12 }, - { LMS7002MCSR::SPDUP_LDO_TIA14, &LMS7002MCSR_Data::SPDUP_LDO_TIA14 }, - { LMS7002MCSR::SPDUP_LDO_TLOB, &LMS7002MCSR_Data::SPDUP_LDO_TLOB }, - { LMS7002MCSR::SPDUP_LDO_TPAD, &LMS7002MCSR_Data::SPDUP_LDO_TPAD }, - { LMS7002MCSR::SPDUP_LDO_TXBUF, &LMS7002MCSR_Data::SPDUP_LDO_TXBUF }, - { LMS7002MCSR::SPDUP_LDO_VCOGN, &LMS7002MCSR_Data::SPDUP_LDO_VCOGN }, - { LMS7002MCSR::SPDUP_LDO_VCOSXR, &LMS7002MCSR_Data::SPDUP_LDO_VCOSXR }, - { LMS7002MCSR::SPDUP_LDO_VCOSXT, &LMS7002MCSR_Data::SPDUP_LDO_VCOSXT }, - { LMS7002MCSR::SPDUP_LDO_AFE, &LMS7002MCSR_Data::SPDUP_LDO_AFE }, - { LMS7002MCSR::SPDUP_LDO_CPGN, &LMS7002MCSR_Data::SPDUP_LDO_CPGN }, - { LMS7002MCSR::SPDUP_LDO_CPSXR, &LMS7002MCSR_Data::SPDUP_LDO_CPSXR }, - { LMS7002MCSR::SPDUP_LDO_CPSXT, &LMS7002MCSR_Data::SPDUP_LDO_CPSXT }, - { LMS7002MCSR::SPDUP_LDO_DIG, &LMS7002MCSR_Data::SPDUP_LDO_DIG }, - { LMS7002MCSR::SPDUP_LDO_DIGGN, &LMS7002MCSR_Data::SPDUP_LDO_DIGGN }, - { LMS7002MCSR::SPDUP_LDO_DIGSXR, &LMS7002MCSR_Data::SPDUP_LDO_DIGSXR }, - { LMS7002MCSR::SPDUP_LDO_DIGSXT, &LMS7002MCSR_Data::SPDUP_LDO_DIGSXT }, - { LMS7002MCSR::SPDUP_LDO_DIVGN, &LMS7002MCSR_Data::SPDUP_LDO_DIVGN }, - { LMS7002MCSR::RDIV_VCOSXR, &LMS7002MCSR_Data::RDIV_VCOSXR }, - { LMS7002MCSR::RDIV_VCOSXT, &LMS7002MCSR_Data::RDIV_VCOSXT }, - { LMS7002MCSR::RDIV_TXBUF, &LMS7002MCSR_Data::RDIV_TXBUF }, - { LMS7002MCSR::RDIV_VCOGN, &LMS7002MCSR_Data::RDIV_VCOGN }, - { LMS7002MCSR::RDIV_TLOB, &LMS7002MCSR_Data::RDIV_TLOB }, - { LMS7002MCSR::RDIV_TPAD, &LMS7002MCSR_Data::RDIV_TPAD }, - { LMS7002MCSR::RDIV_TIA12, &LMS7002MCSR_Data::RDIV_TIA12 }, - { LMS7002MCSR::RDIV_TIA14, &LMS7002MCSR_Data::RDIV_TIA14 }, - { LMS7002MCSR::RDIV_RXBUF, &LMS7002MCSR_Data::RDIV_RXBUF }, - { LMS7002MCSR::RDIV_TBB, &LMS7002MCSR_Data::RDIV_TBB }, - { LMS7002MCSR::RDIV_MXRFE, &LMS7002MCSR_Data::RDIV_MXRFE }, - { LMS7002MCSR::RDIV_RBB, &LMS7002MCSR_Data::RDIV_RBB }, - { LMS7002MCSR::RDIV_LNA12, &LMS7002MCSR_Data::RDIV_LNA12 }, - { LMS7002MCSR::RDIV_LNA14, &LMS7002MCSR_Data::RDIV_LNA14 }, - { LMS7002MCSR::RDIV_DIVSXR, &LMS7002MCSR_Data::RDIV_DIVSXR }, - { LMS7002MCSR::RDIV_DIVSXT, &LMS7002MCSR_Data::RDIV_DIVSXT }, - { LMS7002MCSR::RDIV_DIGSXT, &LMS7002MCSR_Data::RDIV_DIGSXT }, - { LMS7002MCSR::RDIV_DIVGN, &LMS7002MCSR_Data::RDIV_DIVGN }, - { LMS7002MCSR::RDIV_DIGGN, &LMS7002MCSR_Data::RDIV_DIGGN }, - { LMS7002MCSR::RDIV_DIGSXR, &LMS7002MCSR_Data::RDIV_DIGSXR }, - { LMS7002MCSR::RDIV_CPSXT, &LMS7002MCSR_Data::RDIV_CPSXT }, - { LMS7002MCSR::RDIV_DIG, &LMS7002MCSR_Data::RDIV_DIG }, - { LMS7002MCSR::RDIV_CPGN, &LMS7002MCSR_Data::RDIV_CPGN }, - { LMS7002MCSR::RDIV_CPSXR, &LMS7002MCSR_Data::RDIV_CPSXR }, - { LMS7002MCSR::RDIV_SPIBUF, &LMS7002MCSR_Data::RDIV_SPIBUF }, - { LMS7002MCSR::RDIV_AFE, &LMS7002MCSR_Data::RDIV_AFE }, - { LMS7002MCSR::SPDUP_LDO_SPIBUF, &LMS7002MCSR_Data::SPDUP_LDO_SPIBUF }, - { LMS7002MCSR::SPDUP_LDO_DIGIp2, &LMS7002MCSR_Data::SPDUP_LDO_DIGIp2 }, - { LMS7002MCSR::SPDUP_LDO_DIGIp1, &LMS7002MCSR_Data::SPDUP_LDO_DIGIp1 }, - { LMS7002MCSR::BYP_LDO_SPIBUF, &LMS7002MCSR_Data::BYP_LDO_SPIBUF }, - { LMS7002MCSR::BYP_LDO_DIGIp2, &LMS7002MCSR_Data::BYP_LDO_DIGIp2 }, - { LMS7002MCSR::BYP_LDO_DIGIp1, &LMS7002MCSR_Data::BYP_LDO_DIGIp1 }, - { LMS7002MCSR::EN_LOADIMP_LDO_SPIBUF, &LMS7002MCSR_Data::EN_LOADIMP_LDO_SPIBUF }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIGIp2, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGIp2 }, - { LMS7002MCSR::EN_LOADIMP_LDO_DIGIp1, &LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGIp1 }, - { LMS7002MCSR::PD_LDO_SPIBUF, &LMS7002MCSR_Data::PD_LDO_SPIBUF }, - { LMS7002MCSR::PD_LDO_DIGIp2, &LMS7002MCSR_Data::PD_LDO_DIGIp2 }, - { LMS7002MCSR::PD_LDO_DIGIp1, &LMS7002MCSR_Data::PD_LDO_DIGIp1 }, - { LMS7002MCSR::EN_G_LDOP, &LMS7002MCSR_Data::EN_G_LDOP }, - { LMS7002MCSR::RDIV_DIGIp2, &LMS7002MCSR_Data::RDIV_DIGIp2 }, - { LMS7002MCSR::RDIV_DIGIp1, &LMS7002MCSR_Data::RDIV_DIGIp1 }, - { LMS7002MCSR::BSIGT, &LMS7002MCSR_Data::BSIGT }, - { LMS7002MCSR::BSTATE, &LMS7002MCSR_Data::BSTATE }, - { LMS7002MCSR::EN_SDM_TSTO_SXT, &LMS7002MCSR_Data::EN_SDM_TSTO_SXT }, - { LMS7002MCSR::EN_SDM_TSTO_SXR, &LMS7002MCSR_Data::EN_SDM_TSTO_SXR }, - { LMS7002MCSR::EN_SDM_TSTO_CGEN, &LMS7002MCSR_Data::EN_SDM_TSTO_CGEN }, - { LMS7002MCSR::BENC, &LMS7002MCSR_Data::BENC }, - { LMS7002MCSR::BENR, &LMS7002MCSR_Data::BENR }, - { LMS7002MCSR::BENT, &LMS7002MCSR_Data::BENT }, - { LMS7002MCSR::BSTART, &LMS7002MCSR_Data::BSTART }, - { LMS7002MCSR::BSIGR, &LMS7002MCSR_Data::BSIGR }, - { LMS7002MCSR::BSIGC, &LMS7002MCSR_Data::BSIGC }, - { LMS7002MCSR::CDS_MCLK2, &LMS7002MCSR_Data::CDS_MCLK2 }, - { LMS7002MCSR::CDS_MCLK1, &LMS7002MCSR_Data::CDS_MCLK1 }, - { LMS7002MCSR::CDSN_TXBTSP, &LMS7002MCSR_Data::CDSN_TXBTSP }, - { LMS7002MCSR::CDSN_TXATSP, &LMS7002MCSR_Data::CDSN_TXATSP }, - { LMS7002MCSR::CDSN_RXBTSP, &LMS7002MCSR_Data::CDSN_RXBTSP }, - { LMS7002MCSR::CDSN_RXATSP, &LMS7002MCSR_Data::CDSN_RXATSP }, - { LMS7002MCSR::CDSN_TXBLML, &LMS7002MCSR_Data::CDSN_TXBLML }, - { LMS7002MCSR::CDSN_TXALML, &LMS7002MCSR_Data::CDSN_TXALML }, - { LMS7002MCSR::CDSN_RXBLML, &LMS7002MCSR_Data::CDSN_RXBLML }, - { LMS7002MCSR::CDSN_RXALML, &LMS7002MCSR_Data::CDSN_RXALML }, - { LMS7002MCSR::CDSN_MCLK2, &LMS7002MCSR_Data::CDSN_MCLK2 }, - { LMS7002MCSR::CDSN_MCLK1, &LMS7002MCSR_Data::CDSN_MCLK1 }, - { LMS7002MCSR::CDS_TXBTSP, &LMS7002MCSR_Data::CDS_TXBTSP }, - { LMS7002MCSR::CDS_TXATSP, &LMS7002MCSR_Data::CDS_TXATSP }, - { LMS7002MCSR::CDS_RXBTSP, &LMS7002MCSR_Data::CDS_RXBTSP }, - { LMS7002MCSR::CDS_RXATSP, &LMS7002MCSR_Data::CDS_RXATSP }, - { LMS7002MCSR::CDS_TXBLML, &LMS7002MCSR_Data::CDS_TXBLML }, - { LMS7002MCSR::CDS_TXALML, &LMS7002MCSR_Data::CDS_TXALML }, - { LMS7002MCSR::CDS_RXBLML, &LMS7002MCSR_Data::CDS_RXBLML }, - { LMS7002MCSR::CDS_RXALML, &LMS7002MCSR_Data::CDS_RXALML }, - { LMS7002MCSR::EN_LOWBWLOMX_TMX_TRF, &LMS7002MCSR_Data::EN_LOWBWLOMX_TMX_TRF }, - { LMS7002MCSR::EN_NEXTTX_TRF, &LMS7002MCSR_Data::EN_NEXTTX_TRF }, - { LMS7002MCSR::EN_AMPHF_PDET_TRF, &LMS7002MCSR_Data::EN_AMPHF_PDET_TRF }, - { LMS7002MCSR::LOADR_PDET_TRF, &LMS7002MCSR_Data::LOADR_PDET_TRF }, - { LMS7002MCSR::PD_PDET_TRF, &LMS7002MCSR_Data::PD_PDET_TRF }, - { LMS7002MCSR::PD_TLOBUF_TRF, &LMS7002MCSR_Data::PD_TLOBUF_TRF }, - { LMS7002MCSR::PD_TXPAD_TRF, &LMS7002MCSR_Data::PD_TXPAD_TRF }, - { LMS7002MCSR::EN_G_TRF, &LMS7002MCSR_Data::EN_G_TRF }, - { LMS7002MCSR::F_TXPAD_TRF, &LMS7002MCSR_Data::F_TXPAD_TRF }, - { LMS7002MCSR::L_LOOPB_TXPAD_TRF, &LMS7002MCSR_Data::L_LOOPB_TXPAD_TRF }, - { LMS7002MCSR::LOSS_LIN_TXPAD_TRF, &LMS7002MCSR_Data::LOSS_LIN_TXPAD_TRF }, - { LMS7002MCSR::LOSS_MAIN_TXPAD_TRF, &LMS7002MCSR_Data::LOSS_MAIN_TXPAD_TRF }, - { LMS7002MCSR::EN_LOOPB_TXPAD_TRF, &LMS7002MCSR_Data::EN_LOOPB_TXPAD_TRF }, - { LMS7002MCSR::GCAS_GNDREF_TXPAD_TRF, &LMS7002MCSR_Data::GCAS_GNDREF_TXPAD_TRF }, - { LMS7002MCSR::ICT_LIN_TXPAD_TRF, &LMS7002MCSR_Data::ICT_LIN_TXPAD_TRF }, - { LMS7002MCSR::ICT_MAIN_TXPAD_TRF, &LMS7002MCSR_Data::ICT_MAIN_TXPAD_TRF }, - { LMS7002MCSR::VGCAS_TXPAD_TRF, &LMS7002MCSR_Data::VGCAS_TXPAD_TRF }, - { LMS7002MCSR::SEL_BAND1_TRF, &LMS7002MCSR_Data::SEL_BAND1_TRF }, - { LMS7002MCSR::SEL_BAND2_TRF, &LMS7002MCSR_Data::SEL_BAND2_TRF }, - { LMS7002MCSR::LOBIASN_TXM_TRF, &LMS7002MCSR_Data::LOBIASN_TXM_TRF }, - { LMS7002MCSR::LOBIASP_TXX_TRF, &LMS7002MCSR_Data::LOBIASP_TXX_TRF }, - { LMS7002MCSR::CDC_I_TRF, &LMS7002MCSR_Data::CDC_I_TRF }, - { LMS7002MCSR::CDC_Q_TRF, &LMS7002MCSR_Data::CDC_Q_TRF }, - { LMS7002MCSR::STATPULSE_TBB, &LMS7002MCSR_Data::STATPULSE_TBB }, - { LMS7002MCSR::LOOPB_TBB, &LMS7002MCSR_Data::LOOPB_TBB }, - { LMS7002MCSR::PD_LPFH_TBB, &LMS7002MCSR_Data::PD_LPFH_TBB }, - { LMS7002MCSR::PD_LPFIAMP_TBB, &LMS7002MCSR_Data::PD_LPFIAMP_TBB }, - { LMS7002MCSR::PD_LPFLAD_TBB, &LMS7002MCSR_Data::PD_LPFLAD_TBB }, - { LMS7002MCSR::PD_LPFS5_TBB, &LMS7002MCSR_Data::PD_LPFS5_TBB }, - { LMS7002MCSR::EN_G_TBB, &LMS7002MCSR_Data::EN_G_TBB }, - { LMS7002MCSR::ICT_LPFS5_F_TBB, &LMS7002MCSR_Data::ICT_LPFS5_F_TBB }, - { LMS7002MCSR::ICT_LPFS5_PT_TBB, &LMS7002MCSR_Data::ICT_LPFS5_PT_TBB }, - { LMS7002MCSR::ICT_LPF_H_PT_TBB, &LMS7002MCSR_Data::ICT_LPF_H_PT_TBB }, - { LMS7002MCSR::ICT_LPFH_F_TBB, &LMS7002MCSR_Data::ICT_LPFH_F_TBB }, - { LMS7002MCSR::ICT_LPFLAD_F_TBB, &LMS7002MCSR_Data::ICT_LPFLAD_F_TBB }, - { LMS7002MCSR::ICT_LPFLAD_PT_TBB, &LMS7002MCSR_Data::ICT_LPFLAD_PT_TBB }, - { LMS7002MCSR::CG_IAMP_TBB, &LMS7002MCSR_Data::CG_IAMP_TBB }, - { LMS7002MCSR::ICT_IAMP_FRP_TBB, &LMS7002MCSR_Data::ICT_IAMP_FRP_TBB }, - { LMS7002MCSR::ICT_IAMP_GG_FRP_TBB, &LMS7002MCSR_Data::ICT_IAMP_GG_FRP_TBB }, - { LMS7002MCSR::RCAL_LPFH_TBB, &LMS7002MCSR_Data::RCAL_LPFH_TBB }, - { LMS7002MCSR::RCAL_LPFLAD_TBB, &LMS7002MCSR_Data::RCAL_LPFLAD_TBB }, - { LMS7002MCSR::TSTIN_TBB, &LMS7002MCSR_Data::TSTIN_TBB }, - { LMS7002MCSR::BYPLADDER_TBB, &LMS7002MCSR_Data::BYPLADDER_TBB }, - { LMS7002MCSR::CCAL_LPFLAD_TBB, &LMS7002MCSR_Data::CCAL_LPFLAD_TBB }, - { LMS7002MCSR::RCAL_LPFS5_TBB, &LMS7002MCSR_Data::RCAL_LPFS5_TBB }, - { LMS7002MCSR::CDC_I_RFE, &LMS7002MCSR_Data::CDC_I_RFE }, - { LMS7002MCSR::CDC_Q_RFE, &LMS7002MCSR_Data::CDC_Q_RFE }, - { LMS7002MCSR::PD_LNA_RFE, &LMS7002MCSR_Data::PD_LNA_RFE }, - { LMS7002MCSR::PD_RLOOPB_1_RFE, &LMS7002MCSR_Data::PD_RLOOPB_1_RFE }, - { LMS7002MCSR::PD_RLOOPB_2_RFE, &LMS7002MCSR_Data::PD_RLOOPB_2_RFE }, - { LMS7002MCSR::PD_MXLOBUF_RFE, &LMS7002MCSR_Data::PD_MXLOBUF_RFE }, - { LMS7002MCSR::PD_QGEN_RFE, &LMS7002MCSR_Data::PD_QGEN_RFE }, - { LMS7002MCSR::PD_RSSI_RFE, &LMS7002MCSR_Data::PD_RSSI_RFE }, - { LMS7002MCSR::PD_TIA_RFE, &LMS7002MCSR_Data::PD_TIA_RFE }, - { LMS7002MCSR::EN_G_RFE, &LMS7002MCSR_Data::EN_G_RFE }, - { LMS7002MCSR::SEL_PATH_RFE, &LMS7002MCSR_Data::SEL_PATH_RFE }, - { LMS7002MCSR::EN_DCOFF_RXFE_RFE, &LMS7002MCSR_Data::EN_DCOFF_RXFE_RFE }, - { LMS7002MCSR::EN_INSHSW_LB1_RFE, &LMS7002MCSR_Data::EN_INSHSW_LB1_RFE }, - { LMS7002MCSR::EN_INSHSW_LB2_RFE, &LMS7002MCSR_Data::EN_INSHSW_LB2_RFE }, - { LMS7002MCSR::EN_INSHSW_L_RFE, &LMS7002MCSR_Data::EN_INSHSW_L_RFE }, - { LMS7002MCSR::EN_INSHSW_W_RFE, &LMS7002MCSR_Data::EN_INSHSW_W_RFE }, - { LMS7002MCSR::EN_NEXTRX_RFE, &LMS7002MCSR_Data::EN_NEXTRX_RFE }, - { LMS7002MCSR::DCOFFI_RFE, &LMS7002MCSR_Data::DCOFFI_RFE }, - { LMS7002MCSR::DCOFFQ_RFE, &LMS7002MCSR_Data::DCOFFQ_RFE }, - { LMS7002MCSR::ICT_LOOPB_RFE, &LMS7002MCSR_Data::ICT_LOOPB_RFE }, - { LMS7002MCSR::ICT_TIAMAIN_RFE, &LMS7002MCSR_Data::ICT_TIAMAIN_RFE }, - { LMS7002MCSR::ICT_TIAOUT_RFE, &LMS7002MCSR_Data::ICT_TIAOUT_RFE }, - { LMS7002MCSR::ICT_LNACMO_RFE, &LMS7002MCSR_Data::ICT_LNACMO_RFE }, - { LMS7002MCSR::ICT_LNA_RFE, &LMS7002MCSR_Data::ICT_LNA_RFE }, - { LMS7002MCSR::ICT_LODC_RFE, &LMS7002MCSR_Data::ICT_LODC_RFE }, - { LMS7002MCSR::CAP_RXMXO_RFE, &LMS7002MCSR_Data::CAP_RXMXO_RFE }, - { LMS7002MCSR::CGSIN_LNA_RFE, &LMS7002MCSR_Data::CGSIN_LNA_RFE }, - { LMS7002MCSR::CCOMP_TIA_RFE, &LMS7002MCSR_Data::CCOMP_TIA_RFE }, - { LMS7002MCSR::CFB_TIA_RFE, &LMS7002MCSR_Data::CFB_TIA_RFE }, - { LMS7002MCSR::G_LNA_RFE, &LMS7002MCSR_Data::G_LNA_RFE }, - { LMS7002MCSR::G_RXLOOPB_RFE, &LMS7002MCSR_Data::G_RXLOOPB_RFE }, - { LMS7002MCSR::G_TIA_RFE, &LMS7002MCSR_Data::G_TIA_RFE }, - { LMS7002MCSR::RCOMP_TIA_RFE, &LMS7002MCSR_Data::RCOMP_TIA_RFE }, - { LMS7002MCSR::RFB_TIA_RFE, &LMS7002MCSR_Data::RFB_TIA_RFE }, - { LMS7002MCSR::EN_LB_LPFH_RBB, &LMS7002MCSR_Data::EN_LB_LPFH_RBB }, - { LMS7002MCSR::EN_LB_LPFL_RBB, &LMS7002MCSR_Data::EN_LB_LPFL_RBB }, - { LMS7002MCSR::PD_LPFH_RBB, &LMS7002MCSR_Data::PD_LPFH_RBB }, - { LMS7002MCSR::PD_LPFL_RBB, &LMS7002MCSR_Data::PD_LPFL_RBB }, - { LMS7002MCSR::PD_PGA_RBB, &LMS7002MCSR_Data::PD_PGA_RBB }, - { LMS7002MCSR::EN_G_RBB, &LMS7002MCSR_Data::EN_G_RBB }, - { LMS7002MCSR::R_CTL_LPF_RBB, &LMS7002MCSR_Data::R_CTL_LPF_RBB }, - { LMS7002MCSR::RCC_CTL_LPFH_RBB, &LMS7002MCSR_Data::RCC_CTL_LPFH_RBB }, - { LMS7002MCSR::C_CTL_LPFH_RBB, &LMS7002MCSR_Data::C_CTL_LPFH_RBB }, - { LMS7002MCSR::RCC_CTL_LPFL_RBB, &LMS7002MCSR_Data::RCC_CTL_LPFL_RBB }, - { LMS7002MCSR::C_CTL_LPFL_RBB, &LMS7002MCSR_Data::C_CTL_LPFL_RBB }, - { LMS7002MCSR::INPUT_CTL_PGA_RBB, &LMS7002MCSR_Data::INPUT_CTL_PGA_RBB }, - { LMS7002MCSR::ICT_LPF_IN_RBB, &LMS7002MCSR_Data::ICT_LPF_IN_RBB }, - { LMS7002MCSR::ICT_LPF_OUT_RBB, &LMS7002MCSR_Data::ICT_LPF_OUT_RBB }, - { LMS7002MCSR::OSW_PGA_RBB, &LMS7002MCSR_Data::OSW_PGA_RBB }, - { LMS7002MCSR::ICT_PGA_OUT_RBB, &LMS7002MCSR_Data::ICT_PGA_OUT_RBB }, - { LMS7002MCSR::ICT_PGA_IN_RBB, &LMS7002MCSR_Data::ICT_PGA_IN_RBB }, - { LMS7002MCSR::G_PGA_RBB, &LMS7002MCSR_Data::G_PGA_RBB }, - { LMS7002MCSR::RCC_CTL_PGA_RBB, &LMS7002MCSR_Data::RCC_CTL_PGA_RBB }, - { LMS7002MCSR::C_CTL_PGA_RBB, &LMS7002MCSR_Data::C_CTL_PGA_RBB }, - { LMS7002MCSR::RESET_N, &LMS7002MCSR_Data::RESET_N }, - { LMS7002MCSR::SPDUP_VCO, &LMS7002MCSR_Data::SPDUP_VCO }, - { LMS7002MCSR::BYPLDO_VCO, &LMS7002MCSR_Data::BYPLDO_VCO }, - { LMS7002MCSR::EN_COARSEPLL, &LMS7002MCSR_Data::EN_COARSEPLL }, - { LMS7002MCSR::CURLIM_VCO, &LMS7002MCSR_Data::CURLIM_VCO }, - { LMS7002MCSR::EN_DIV2_DIVPROG, &LMS7002MCSR_Data::EN_DIV2_DIVPROG }, - { LMS7002MCSR::EN_INTONLY_SDM, &LMS7002MCSR_Data::EN_INTONLY_SDM }, - { LMS7002MCSR::EN_SDM_CLK, &LMS7002MCSR_Data::EN_SDM_CLK }, - { LMS7002MCSR::PD_FBDIV, &LMS7002MCSR_Data::PD_FBDIV }, - { LMS7002MCSR::PD_LOCH_T2RBUF, &LMS7002MCSR_Data::PD_LOCH_T2RBUF }, - { LMS7002MCSR::PD_CP, &LMS7002MCSR_Data::PD_CP }, - { LMS7002MCSR::PD_FDIV, &LMS7002MCSR_Data::PD_FDIV }, - { LMS7002MCSR::PD_SDM, &LMS7002MCSR_Data::PD_SDM }, - { LMS7002MCSR::PD_VCO_COMP, &LMS7002MCSR_Data::PD_VCO_COMP }, - { LMS7002MCSR::PD_VCO, &LMS7002MCSR_Data::PD_VCO }, - { LMS7002MCSR::EN_G, &LMS7002MCSR_Data::EN_G }, - { LMS7002MCSR::FRAC_SDM_LSB, &LMS7002MCSR_Data::FRAC_SDM_LSB }, - { LMS7002MCSR::INT_SDM, &LMS7002MCSR_Data::INT_SDM }, - { LMS7002MCSR::FRAC_SDM_MSB, &LMS7002MCSR_Data::FRAC_SDM_MSB }, - { LMS7002MCSR::PW_DIV2_LOCH, &LMS7002MCSR_Data::PW_DIV2_LOCH }, - { LMS7002MCSR::PW_DIV4_LOCH, &LMS7002MCSR_Data::PW_DIV4_LOCH }, - { LMS7002MCSR::DIV_LOCH, &LMS7002MCSR_Data::DIV_LOCH }, - { LMS7002MCSR::TST_SX, &LMS7002MCSR_Data::TST_SX }, - { LMS7002MCSR::SEL_SDMCLK, &LMS7002MCSR_Data::SEL_SDMCLK }, - { LMS7002MCSR::SX_DITHER_EN, &LMS7002MCSR_Data::SX_DITHER_EN }, - { LMS7002MCSR::REV_SDMCLK, &LMS7002MCSR_Data::REV_SDMCLK }, - { LMS7002MCSR::VDIV_VCO, &LMS7002MCSR_Data::VDIV_VCO }, - { LMS7002MCSR::ICT_VCO, &LMS7002MCSR_Data::ICT_VCO }, - { LMS7002MCSR::RSEL_LDO_VCO, &LMS7002MCSR_Data::RSEL_LDO_VCO }, - { LMS7002MCSR::CSW_VCO, &LMS7002MCSR_Data::CSW_VCO }, - { LMS7002MCSR::SEL_VCO, &LMS7002MCSR_Data::SEL_VCO }, - { LMS7002MCSR::COARSE_START, &LMS7002MCSR_Data::COARSE_START }, - { LMS7002MCSR::REVPH_PFD, &LMS7002MCSR_Data::REVPH_PFD }, - { LMS7002MCSR::IOFFSET_CP, &LMS7002MCSR_Data::IOFFSET_CP }, - { LMS7002MCSR::IPULSE_CP, &LMS7002MCSR_Data::IPULSE_CP }, - { LMS7002MCSR::COARSE_STEPDONE, &LMS7002MCSR_Data::COARSE_STEPDONE }, - { LMS7002MCSR::COARSEPLL_COMPO, &LMS7002MCSR_Data::COARSEPLL_COMPO }, - { LMS7002MCSR::VCO_CMPHO, &LMS7002MCSR_Data::VCO_CMPHO }, - { LMS7002MCSR::VCO_CMPLO, &LMS7002MCSR_Data::VCO_CMPLO }, - { LMS7002MCSR::CP2_PLL, &LMS7002MCSR_Data::CP2_PLL }, - { LMS7002MCSR::CP3_PLL, &LMS7002MCSR_Data::CP3_PLL }, - { LMS7002MCSR::CZ, &LMS7002MCSR_Data::CZ }, - { LMS7002MCSR::EN_DIR_SXRSXT, &LMS7002MCSR_Data::EN_DIR_SXRSXT }, - { LMS7002MCSR::EN_DIR_RBB, &LMS7002MCSR_Data::EN_DIR_RBB }, - { LMS7002MCSR::EN_DIR_RFE, &LMS7002MCSR_Data::EN_DIR_RFE }, - { LMS7002MCSR::EN_DIR_TBB, &LMS7002MCSR_Data::EN_DIR_TBB }, - { LMS7002MCSR::EN_DIR_TRF, &LMS7002MCSR_Data::EN_DIR_TRF }, - { LMS7002MCSR::TSGFC_TXTSP, &LMS7002MCSR_Data::TSGFC_TXTSP }, - { LMS7002MCSR::TSGFCW_TXTSP, &LMS7002MCSR_Data::TSGFCW_TXTSP }, - { LMS7002MCSR::TSGDCLDQ_TXTSP, &LMS7002MCSR_Data::TSGDCLDQ_TXTSP }, - { LMS7002MCSR::TSGDCLDI_TXTSP, &LMS7002MCSR_Data::TSGDCLDI_TXTSP }, - { LMS7002MCSR::TSGSWAPIQ_TXTSP, &LMS7002MCSR_Data::TSGSWAPIQ_TXTSP }, - { LMS7002MCSR::TSGMODE_TXTSP, &LMS7002MCSR_Data::TSGMODE_TXTSP }, - { LMS7002MCSR::INSEL_TXTSP, &LMS7002MCSR_Data::INSEL_TXTSP }, - { LMS7002MCSR::BSTART_TXTSP, &LMS7002MCSR_Data::BSTART_TXTSP }, - { LMS7002MCSR::EN_TXTSP, &LMS7002MCSR_Data::EN_TXTSP }, - { LMS7002MCSR::GCORRQ_TXTSP, &LMS7002MCSR_Data::GCORRQ_TXTSP }, - { LMS7002MCSR::GCORRI_TXTSP, &LMS7002MCSR_Data::GCORRI_TXTSP }, - { LMS7002MCSR::HBI_OVR_TXTSP, &LMS7002MCSR_Data::HBI_OVR_TXTSP }, - { LMS7002MCSR::IQCORR_TXTSP, &LMS7002MCSR_Data::IQCORR_TXTSP }, - { LMS7002MCSR::DCCORRI_TXTSP, &LMS7002MCSR_Data::DCCORRI_TXTSP }, - { LMS7002MCSR::DCCORRQ_TXTSP, &LMS7002MCSR_Data::DCCORRQ_TXTSP }, - { LMS7002MCSR::GFIR1_L_TXTSP, &LMS7002MCSR_Data::GFIR1_L_TXTSP }, - { LMS7002MCSR::GFIR1_N_TXTSP, &LMS7002MCSR_Data::GFIR1_N_TXTSP }, - { LMS7002MCSR::GFIR2_L_TXTSP, &LMS7002MCSR_Data::GFIR2_L_TXTSP }, - { LMS7002MCSR::GFIR2_N_TXTSP, &LMS7002MCSR_Data::GFIR2_N_TXTSP }, - { LMS7002MCSR::GFIR3_L_TXTSP, &LMS7002MCSR_Data::GFIR3_L_TXTSP }, - { LMS7002MCSR::GFIR3_N_TXTSP, &LMS7002MCSR_Data::GFIR3_N_TXTSP }, - { LMS7002MCSR::CMIX_GAIN_TXTSP, &LMS7002MCSR_Data::CMIX_GAIN_TXTSP }, - { LMS7002MCSR::CMIX_SC_TXTSP, &LMS7002MCSR_Data::CMIX_SC_TXTSP }, - { LMS7002MCSR::CMIX_BYP_TXTSP, &LMS7002MCSR_Data::CMIX_BYP_TXTSP }, - { LMS7002MCSR::ISINC_BYP_TXTSP, &LMS7002MCSR_Data::ISINC_BYP_TXTSP }, - { LMS7002MCSR::GFIR3_BYP_TXTSP, &LMS7002MCSR_Data::GFIR3_BYP_TXTSP }, - { LMS7002MCSR::GFIR2_BYP_TXTSP, &LMS7002MCSR_Data::GFIR2_BYP_TXTSP }, - { LMS7002MCSR::GFIR1_BYP_TXTSP, &LMS7002MCSR_Data::GFIR1_BYP_TXTSP }, - { LMS7002MCSR::DC_BYP_TXTSP, &LMS7002MCSR_Data::DC_BYP_TXTSP }, - { LMS7002MCSR::GC_BYP_TXTSP, &LMS7002MCSR_Data::GC_BYP_TXTSP }, - { LMS7002MCSR::PH_BYP_TXTSP, &LMS7002MCSR_Data::PH_BYP_TXTSP }, - { LMS7002MCSR::BSIGI_TXTSP, &LMS7002MCSR_Data::BSIGI_TXTSP }, - { LMS7002MCSR::BSTATE_TXTSP, &LMS7002MCSR_Data::BSTATE_TXTSP }, - { LMS7002MCSR::BSIGQ_TXTSP, &LMS7002MCSR_Data::BSIGQ_TXTSP }, - { LMS7002MCSR::DC_REG_TXTSP, &LMS7002MCSR_Data::DC_REG_TXTSP }, - { LMS7002MCSR::DTHBIT_TX, &LMS7002MCSR_Data::DTHBIT_TX }, - { LMS7002MCSR::SEL_TX, &LMS7002MCSR_Data::SEL_TX }, - { LMS7002MCSR::MODE_TX, &LMS7002MCSR_Data::MODE_TX }, - { LMS7002MCSR::PHO_TX, &LMS7002MCSR_Data::PHO_TX }, - { LMS7002MCSR::CAPTURE, &LMS7002MCSR_Data::CAPTURE }, - { LMS7002MCSR::CAPSEL, &LMS7002MCSR_Data::CAPSEL }, - { LMS7002MCSR::CAPSEL_ADC, &LMS7002MCSR_Data::CAPSEL_ADC }, - { LMS7002MCSR::TSGFC_RXTSP, &LMS7002MCSR_Data::TSGFC_RXTSP }, - { LMS7002MCSR::TSGFCW_RXTSP, &LMS7002MCSR_Data::TSGFCW_RXTSP }, - { LMS7002MCSR::TSGDCLDQ_RXTSP, &LMS7002MCSR_Data::TSGDCLDQ_RXTSP }, - { LMS7002MCSR::TSGDCLDI_RXTSP, &LMS7002MCSR_Data::TSGDCLDI_RXTSP }, - { LMS7002MCSR::TSGSWAPIQ_RXTSP, &LMS7002MCSR_Data::TSGSWAPIQ_RXTSP }, - { LMS7002MCSR::TSGMODE_RXTSP, &LMS7002MCSR_Data::TSGMODE_RXTSP }, - { LMS7002MCSR::INSEL_RXTSP, &LMS7002MCSR_Data::INSEL_RXTSP }, - { LMS7002MCSR::BSTART_RXTSP, &LMS7002MCSR_Data::BSTART_RXTSP }, - { LMS7002MCSR::EN_RXTSP, &LMS7002MCSR_Data::EN_RXTSP }, - { LMS7002MCSR::GCORRQ_RXTSP, &LMS7002MCSR_Data::GCORRQ_RXTSP }, - { LMS7002MCSR::GCORRI_RXTSP, &LMS7002MCSR_Data::GCORRI_RXTSP }, - { LMS7002MCSR::HBD_OVR_RXTSP, &LMS7002MCSR_Data::HBD_OVR_RXTSP }, - { LMS7002MCSR::IQCORR_RXTSP, &LMS7002MCSR_Data::IQCORR_RXTSP }, - { LMS7002MCSR::HBD_DLY, &LMS7002MCSR_Data::HBD_DLY }, - { LMS7002MCSR::DCCORR_AVG_RXTSP, &LMS7002MCSR_Data::DCCORR_AVG_RXTSP }, - { LMS7002MCSR::GFIR1_L_RXTSP, &LMS7002MCSR_Data::GFIR1_L_RXTSP }, - { LMS7002MCSR::GFIR1_N_RXTSP, &LMS7002MCSR_Data::GFIR1_N_RXTSP }, - { LMS7002MCSR::GFIR2_L_RXTSP, &LMS7002MCSR_Data::GFIR2_L_RXTSP }, - { LMS7002MCSR::GFIR2_N_RXTSP, &LMS7002MCSR_Data::GFIR2_N_RXTSP }, - { LMS7002MCSR::GFIR3_L_RXTSP, &LMS7002MCSR_Data::GFIR3_L_RXTSP }, - { LMS7002MCSR::GFIR3_N_RXTSP, &LMS7002MCSR_Data::GFIR3_N_RXTSP }, - { LMS7002MCSR::AGC_K_RXTSP, &LMS7002MCSR_Data::AGC_K_RXTSP }, - { LMS7002MCSR::AGC_ADESIRED_RXTSP, &LMS7002MCSR_Data::AGC_ADESIRED_RXTSP }, - { LMS7002MCSR::RSSI_MODE, &LMS7002MCSR_Data::RSSI_MODE }, - { LMS7002MCSR::AGC_MODE_RXTSP, &LMS7002MCSR_Data::AGC_MODE_RXTSP }, - { LMS7002MCSR::AGC_AVG_RXTSP, &LMS7002MCSR_Data::AGC_AVG_RXTSP }, - { LMS7002MCSR::DC_REG_RXTSP, &LMS7002MCSR_Data::DC_REG_RXTSP }, - { LMS7002MCSR::CMIX_GAIN_RXTSP, &LMS7002MCSR_Data::CMIX_GAIN_RXTSP }, - { LMS7002MCSR::CMIX_SC_RXTSP, &LMS7002MCSR_Data::CMIX_SC_RXTSP }, - { LMS7002MCSR::CMIX_BYP_RXTSP, &LMS7002MCSR_Data::CMIX_BYP_RXTSP }, - { LMS7002MCSR::AGC_BYP_RXTSP, &LMS7002MCSR_Data::AGC_BYP_RXTSP }, - { LMS7002MCSR::GFIR3_BYP_RXTSP, &LMS7002MCSR_Data::GFIR3_BYP_RXTSP }, - { LMS7002MCSR::GFIR2_BYP_RXTSP, &LMS7002MCSR_Data::GFIR2_BYP_RXTSP }, - { LMS7002MCSR::GFIR1_BYP_RXTSP, &LMS7002MCSR_Data::GFIR1_BYP_RXTSP }, - { LMS7002MCSR::DC_BYP_RXTSP, &LMS7002MCSR_Data::DC_BYP_RXTSP }, - { LMS7002MCSR::GC_BYP_RXTSP, &LMS7002MCSR_Data::GC_BYP_RXTSP }, - { LMS7002MCSR::PH_BYP_RXTSP, &LMS7002MCSR_Data::PH_BYP_RXTSP }, - { LMS7002MCSR::CAPD, &LMS7002MCSR_Data::CAPD }, - { LMS7002MCSR::DTHBIT_RX, &LMS7002MCSR_Data::DTHBIT_RX }, - { LMS7002MCSR::SEL_RX, &LMS7002MCSR_Data::SEL_RX }, - { LMS7002MCSR::MODE_RX, &LMS7002MCSR_Data::MODE_RX }, - { LMS7002MCSR::PHO_RX, &LMS7002MCSR_Data::PHO_RX }, - { LMS7002MCSR::TRX_GAIN_SRC, &LMS7002MCSR_Data::TRX_GAIN_SRC }, - { LMS7002MCSR::DCMODE, &LMS7002MCSR_Data::DCMODE }, - { LMS7002MCSR::PD_DCDAC_RXB, &LMS7002MCSR_Data::PD_DCDAC_RXB }, - { LMS7002MCSR::PD_DCDAC_RXA, &LMS7002MCSR_Data::PD_DCDAC_RXA }, - { LMS7002MCSR::PD_DCDAC_TXB, &LMS7002MCSR_Data::PD_DCDAC_TXB }, - { LMS7002MCSR::PD_DCDAC_TXA, &LMS7002MCSR_Data::PD_DCDAC_TXA }, - { LMS7002MCSR::PD_DCCMP_RXB, &LMS7002MCSR_Data::PD_DCCMP_RXB }, - { LMS7002MCSR::PD_DCCMP_RXA, &LMS7002MCSR_Data::PD_DCCMP_RXA }, - { LMS7002MCSR::PD_DCCMP_TXB, &LMS7002MCSR_Data::PD_DCCMP_TXB }, - { LMS7002MCSR::PD_DCCMP_TXA, &LMS7002MCSR_Data::PD_DCCMP_TXA }, - { LMS7002MCSR::DCCAL_CALSTATUS_RXBQ, &LMS7002MCSR_Data::DCCAL_CALSTATUS_RXBQ }, - { LMS7002MCSR::DCCAL_CALSTATUS_RXBI, &LMS7002MCSR_Data::DCCAL_CALSTATUS_RXBI }, - { LMS7002MCSR::DCCAL_CALSTATUS_RXAQ, &LMS7002MCSR_Data::DCCAL_CALSTATUS_RXAQ }, - { LMS7002MCSR::DCCAL_CALSTATUS_RXAI, &LMS7002MCSR_Data::DCCAL_CALSTATUS_RXAI }, - { LMS7002MCSR::DCCAL_CALSTATUS_TXBQ, &LMS7002MCSR_Data::DCCAL_CALSTATUS_TXBQ }, - { LMS7002MCSR::DCCAL_CALSTATUS_TXBI, &LMS7002MCSR_Data::DCCAL_CALSTATUS_TXBI }, - { LMS7002MCSR::DCCAL_CALSTATUS_TXAQ, &LMS7002MCSR_Data::DCCAL_CALSTATUS_TXAQ }, - { LMS7002MCSR::DCCAL_CALSTATUS_TXAI, &LMS7002MCSR_Data::DCCAL_CALSTATUS_TXAI }, - { LMS7002MCSR::DCCAL_CMPSTATUS_RXBQ, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXBQ }, - { LMS7002MCSR::DCCAL_CMPSTATUS_RXBI, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXBI }, - { LMS7002MCSR::DCCAL_CMPSTATUS_RXAQ, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXAQ }, - { LMS7002MCSR::DCCAL_CMPSTATUS_RXAI, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXAI }, - { LMS7002MCSR::DCCAL_CMPSTATUS_TXBQ, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXBQ }, - { LMS7002MCSR::DCCAL_CMPSTATUS_TXBI, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXBI }, - { LMS7002MCSR::DCCAL_CMPSTATUS_TXAQ, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXAQ }, - { LMS7002MCSR::DCCAL_CMPSTATUS_TXAI, &LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXAI }, - { LMS7002MCSR::DCCAL_CMPCFG_RXBQ, &LMS7002MCSR_Data::DCCAL_CMPCFG_RXBQ }, - { LMS7002MCSR::DCCAL_CMPCFG_RXBI, &LMS7002MCSR_Data::DCCAL_CMPCFG_RXBI }, - { LMS7002MCSR::DCCAL_CMPCFG_RXAQ, &LMS7002MCSR_Data::DCCAL_CMPCFG_RXAQ }, - { LMS7002MCSR::DCCAL_CMPCFG_RXAI, &LMS7002MCSR_Data::DCCAL_CMPCFG_RXAI }, - { LMS7002MCSR::DCCAL_CMPCFG_TXBQ, &LMS7002MCSR_Data::DCCAL_CMPCFG_TXBQ }, - { LMS7002MCSR::DCCAL_CMPCFG_TXBI, &LMS7002MCSR_Data::DCCAL_CMPCFG_TXBI }, - { LMS7002MCSR::DCCAL_CMPCFG_TXAQ, &LMS7002MCSR_Data::DCCAL_CMPCFG_TXAQ }, - { LMS7002MCSR::DCCAL_CMPCFG_TXAI, &LMS7002MCSR_Data::DCCAL_CMPCFG_TXAI }, - { LMS7002MCSR::DCCAL_START_RXBQ, &LMS7002MCSR_Data::DCCAL_START_RXBQ }, - { LMS7002MCSR::DCCAL_START_RXBI, &LMS7002MCSR_Data::DCCAL_START_RXBI }, - { LMS7002MCSR::DCCAL_START_RXAQ, &LMS7002MCSR_Data::DCCAL_START_RXAQ }, - { LMS7002MCSR::DCCAL_START_RXAI, &LMS7002MCSR_Data::DCCAL_START_RXAI }, - { LMS7002MCSR::DCCAL_START_TXBQ, &LMS7002MCSR_Data::DCCAL_START_TXBQ }, - { LMS7002MCSR::DCCAL_START_TXBI, &LMS7002MCSR_Data::DCCAL_START_TXBI }, - { LMS7002MCSR::DCCAL_START_TXAQ, &LMS7002MCSR_Data::DCCAL_START_TXAQ }, - { LMS7002MCSR::DCCAL_START_TXAI, &LMS7002MCSR_Data::DCCAL_START_TXAI }, - { LMS7002MCSR::DCWR_TXAI, &LMS7002MCSR_Data::DCWR_TXAI }, - { LMS7002MCSR::DCRD_TXAI, &LMS7002MCSR_Data::DCRD_TXAI }, - { LMS7002MCSR::DC_TXAI, &LMS7002MCSR_Data::DC_TXAI }, - { LMS7002MCSR::DCWR_TXAQ, &LMS7002MCSR_Data::DCWR_TXAQ }, - { LMS7002MCSR::DCRD_TXAQ, &LMS7002MCSR_Data::DCRD_TXAQ }, - { LMS7002MCSR::DC_TXAQ, &LMS7002MCSR_Data::DC_TXAQ }, - { LMS7002MCSR::DCWR_TXBI, &LMS7002MCSR_Data::DCWR_TXBI }, - { LMS7002MCSR::DCRD_TXBI, &LMS7002MCSR_Data::DCRD_TXBI }, - { LMS7002MCSR::DC_TXBI, &LMS7002MCSR_Data::DC_TXBI }, - { LMS7002MCSR::DCWR_TXBQ, &LMS7002MCSR_Data::DCWR_TXBQ }, - { LMS7002MCSR::DCRD_TXBQ, &LMS7002MCSR_Data::DCRD_TXBQ }, - { LMS7002MCSR::DC_TXBQ, &LMS7002MCSR_Data::DC_TXBQ }, - { LMS7002MCSR::DCWR_RXAI, &LMS7002MCSR_Data::DCWR_RXAI }, - { LMS7002MCSR::DCRD_RXAI, &LMS7002MCSR_Data::DCRD_RXAI }, - { LMS7002MCSR::DC_RXAI, &LMS7002MCSR_Data::DC_RXAI }, - { LMS7002MCSR::DCWR_RXAQ, &LMS7002MCSR_Data::DCWR_RXAQ }, - { LMS7002MCSR::DCRD_RXAQ, &LMS7002MCSR_Data::DCRD_RXAQ }, - { LMS7002MCSR::DC_RXAQ, &LMS7002MCSR_Data::DC_RXAQ }, - { LMS7002MCSR::DCWR_RXBI, &LMS7002MCSR_Data::DCWR_RXBI }, - { LMS7002MCSR::DCRD_RXBI, &LMS7002MCSR_Data::DCRD_RXBI }, - { LMS7002MCSR::DC_RXBI, &LMS7002MCSR_Data::DC_RXBI }, - { LMS7002MCSR::DCWR_RXBQ, &LMS7002MCSR_Data::DCWR_RXBQ }, - { LMS7002MCSR::DCRD_RXBQ, &LMS7002MCSR_Data::DCRD_RXBQ }, - { LMS7002MCSR::DC_RXBQ, &LMS7002MCSR_Data::DC_RXBQ }, - { LMS7002MCSR::DC_RXCDIV, &LMS7002MCSR_Data::DC_RXCDIV }, - { LMS7002MCSR::DC_TXCDIV, &LMS7002MCSR_Data::DC_TXCDIV }, - { LMS7002MCSR::HYSCMP_RXB, &LMS7002MCSR_Data::HYSCMP_RXB }, - { LMS7002MCSR::HYSCMP_RXA, &LMS7002MCSR_Data::HYSCMP_RXA }, - { LMS7002MCSR::HYSCMP_TXB, &LMS7002MCSR_Data::HYSCMP_TXB }, - { LMS7002MCSR::HYSCMP_TXA, &LMS7002MCSR_Data::HYSCMP_TXA }, - { LMS7002MCSR::DAC_CLKDIV, &LMS7002MCSR_Data::DAC_CLKDIV }, - { LMS7002MCSR::RSSI_RSSIMODE, &LMS7002MCSR_Data::RSSI_RSSIMODE }, - { LMS7002MCSR::RSSI_PD, &LMS7002MCSR_Data::RSSI_PD }, - { LMS7002MCSR::RSSI_BIAS, &LMS7002MCSR_Data::RSSI_BIAS }, - { LMS7002MCSR::RSSI_HYSCMP, &LMS7002MCSR_Data::RSSI_HYSCMP }, - { LMS7002MCSR::RSSI_DAC_VAL, &LMS7002MCSR_Data::RSSI_DAC_VAL }, - { LMS7002MCSR::RSSI_PDET2_VAL, &LMS7002MCSR_Data::RSSI_PDET2_VAL }, - { LMS7002MCSR::RSSI_PDET1_VAL, &LMS7002MCSR_Data::RSSI_PDET1_VAL }, - { LMS7002MCSR::RSSI_RSSI2_VAL, &LMS7002MCSR_Data::RSSI_RSSI2_VAL }, - { LMS7002MCSR::RSSI_RSSI1_VAL, &LMS7002MCSR_Data::RSSI_RSSI1_VAL }, - { LMS7002MCSR::RSSI_TREF_VAL, &LMS7002MCSR_Data::RSSI_TREF_VAL }, - { LMS7002MCSR::RSSI_TVPTAT_VAL, &LMS7002MCSR_Data::RSSI_TVPTAT_VAL }, - { LMS7002MCSR::RSSIDC_CMPSTATUS, &LMS7002MCSR_Data::RSSIDC_CMPSTATUS }, - { LMS7002MCSR::RSSIDC_RSEL, &LMS7002MCSR_Data::RSSIDC_RSEL }, - { LMS7002MCSR::RSSIDC_HYSCMP, &LMS7002MCSR_Data::RSSIDC_HYSCMP }, - { LMS7002MCSR::RSSIDC_PD, &LMS7002MCSR_Data::RSSIDC_PD }, - { LMS7002MCSR::RSSIDC_DCO2, &LMS7002MCSR_Data::RSSIDC_DCO2 }, - { LMS7002MCSR::RSSIDC_DCO1, &LMS7002MCSR_Data::RSSIDC_DCO1 }, - { LMS7002MCSR::LML2_TRXIQPULSE, &LMS7002MCSR_Data::LML2_TRXIQPULSE }, - { LMS7002MCSR::LML2_SISODDR, &LMS7002MCSR_Data::LML2_SISODDR }, - { LMS7002MCSR::LML1_TRXIQPULSE, &LMS7002MCSR_Data::LML1_TRXIQPULSE }, - { LMS7002MCSR::LML1_SISODDR, &LMS7002MCSR_Data::LML1_SISODDR }, - { LMS7002MCSR::MCLK2_DLY, &LMS7002MCSR_Data::MCLK2_DLY }, - { LMS7002MCSR::MCLK1_DLY, &LMS7002MCSR_Data::MCLK1_DLY }, - { LMS7002MCSR::MCLK2_INV, &LMS7002MCSR_Data::MCLK2_INV }, - { LMS7002MCSR::MCLK1_INV, &LMS7002MCSR_Data::MCLK1_INV }, - { LMS7002MCSR::CMIX_GAIN_TXTSP_R3, &LMS7002MCSR_Data::CMIX_GAIN_TXTSP_R3 }, - { LMS7002MCSR::CMIX_GAIN_RXTSP_R3, &LMS7002MCSR_Data::CMIX_GAIN_RXTSP_R3 }, - { LMS7002MCSR::R5_LPF_BYP_TBB, &LMS7002MCSR_Data::R5_LPF_BYP_TBB }, - { LMS7002MCSR::CG_IAMP_TBB_R3, &LMS7002MCSR_Data::CG_IAMP_TBB_R3 }, - { LMS7002MCSR::LOSS_LIN_TXPAD_R3, &LMS7002MCSR_Data::LOSS_LIN_TXPAD_R3 }, - { LMS7002MCSR::LOSS_MAIN_TXPAD_R3, &LMS7002MCSR_Data::LOSS_MAIN_TXPAD_R3 }, - { LMS7002MCSR::C_CTL_PGA_RBB_R3, &LMS7002MCSR_Data::C_CTL_PGA_RBB_R3 }, - { LMS7002MCSR::G_PGA_RBB_R3, &LMS7002MCSR_Data::G_PGA_RBB_R3 }, - { LMS7002MCSR::G_LNA_RFE_R3, &LMS7002MCSR_Data::G_LNA_RFE_R3 }, - { LMS7002MCSR::G_TIA_RFE_R3, &LMS7002MCSR_Data::G_TIA_RFE_R3 }, - { LMS7002MCSR::RZ_CTRL, &LMS7002MCSR_Data::RZ_CTRL }, - { LMS7002MCSR::CMPLO_CTRL_SX, &LMS7002MCSR_Data::CMPLO_CTRL_SX }, - { LMS7002MCSR::CMPLO_CTRL_CGEN_R3, &LMS7002MCSR_Data::CMPLO_CTRL_CGEN_R3 }, - { LMS7002MCSR::ISINK_SPIBUFF, &LMS7002MCSR_Data::ISINK_SPIBUFF }, - { LMS7002MCSR::DCMODE, &LMS7002MCSR_Data::DCMODE }, - { LMS7002MCSR::PD_DCDAC_RXB, &LMS7002MCSR_Data::PD_DCDAC_RXB }, - { LMS7002MCSR::PD_DCDAC_RXA, &LMS7002MCSR_Data::PD_DCDAC_RXA }, - { LMS7002MCSR::PD_DCDAC_TXB, &LMS7002MCSR_Data::PD_DCDAC_TXB }, - { LMS7002MCSR::PD_DCDAC_TXA, &LMS7002MCSR_Data::PD_DCDAC_TXA }, - { LMS7002MCSR::PD_DCCMP_RXB, &LMS7002MCSR_Data::PD_DCCMP_RXB }, - { LMS7002MCSR::PD_DCCMP_RXA, &LMS7002MCSR_Data::PD_DCCMP_RXA }, - { LMS7002MCSR::PD_DCCMP_TXB, &LMS7002MCSR_Data::PD_DCCMP_TXB }, - { LMS7002MCSR::PD_DCCMP_TXA, &LMS7002MCSR_Data::PD_DCCMP_TXA }, - { LMS7002MCSR::DCWR_TXAI, &LMS7002MCSR_Data::DCWR_TXAI }, - { LMS7002MCSR::DCRD_TXAI, &LMS7002MCSR_Data::DCRD_TXAI }, - { LMS7002MCSR::DC_TXAI, &LMS7002MCSR_Data::DC_TXAI }, - { LMS7002MCSR::DCWR_TXAQ, &LMS7002MCSR_Data::DCWR_TXAQ }, - { LMS7002MCSR::DCRD_TXAQ, &LMS7002MCSR_Data::DCRD_TXAQ }, - { LMS7002MCSR::DC_TXAQ, &LMS7002MCSR_Data::DC_TXAQ }, - { LMS7002MCSR::DCWR_TXBI, &LMS7002MCSR_Data::DCWR_TXBI }, - { LMS7002MCSR::DCRD_TXBI, &LMS7002MCSR_Data::DCRD_TXBI }, - { LMS7002MCSR::DC_TXBI, &LMS7002MCSR_Data::DC_TXBI }, - { LMS7002MCSR::DCWR_TXBQ, &LMS7002MCSR_Data::DCWR_TXBQ }, - { LMS7002MCSR::DCRD_TXBQ, &LMS7002MCSR_Data::DCRD_TXBQ }, - { LMS7002MCSR::DC_TXBQ, &LMS7002MCSR_Data::DC_TXBQ }, - { LMS7002MCSR::DCWR_RXAI, &LMS7002MCSR_Data::DCWR_RXAI }, - { LMS7002MCSR::DCRD_RXAI, &LMS7002MCSR_Data::DCRD_RXAI }, - { LMS7002MCSR::DC_RXAI, &LMS7002MCSR_Data::DC_RXAI }, - { LMS7002MCSR::DCWR_RXAQ, &LMS7002MCSR_Data::DCWR_RXAQ }, - { LMS7002MCSR::DCRD_RXAQ, &LMS7002MCSR_Data::DCRD_RXAQ }, - { LMS7002MCSR::DC_RXAQ, &LMS7002MCSR_Data::DC_RXAQ }, - { LMS7002MCSR::DCWR_RXBI, &LMS7002MCSR_Data::DCWR_RXBI }, - { LMS7002MCSR::DCRD_RXBI, &LMS7002MCSR_Data::DCRD_RXBI }, - { LMS7002MCSR::DC_RXBI, &LMS7002MCSR_Data::DC_RXBI }, - { LMS7002MCSR::DCWR_RXBQ, &LMS7002MCSR_Data::DCWR_RXBQ }, - { LMS7002MCSR::DCRD_RXBQ, &LMS7002MCSR_Data::DCRD_RXBQ }, - { LMS7002MCSR::DC_RXBQ, &LMS7002MCSR_Data::DC_RXBQ }, - { LMS7002MCSR::DC_RXCDIV, &LMS7002MCSR_Data::DC_RXCDIV }, - { LMS7002MCSR::DC_TXCDIV, &LMS7002MCSR_Data::DC_TXCDIV }, - { LMS7002MCSR::HYSCMP_RXB, &LMS7002MCSR_Data::HYSCMP_RXB }, - { LMS7002MCSR::HYSCMP_RXA, &LMS7002MCSR_Data::HYSCMP_RXA }, - { LMS7002MCSR::HYSCMP_TXB, &LMS7002MCSR_Data::HYSCMP_TXB }, - { LMS7002MCSR::HYSCMP_TXA, &LMS7002MCSR_Data::HYSCMP_TXA }, - { LMS7002MCSR::DAC_CLKDIV, &LMS7002MCSR_Data::DAC_CLKDIV }, - { LMS7002MCSR::RSSI_RSSIMODE, &LMS7002MCSR_Data::RSSI_RSSIMODE }, - { LMS7002MCSR::RSSI_PD, &LMS7002MCSR_Data::RSSI_PD }, - { LMS7002MCSR::INTADC_CMPSTATUS_TEMPREF, &LMS7002MCSR_Data::INTADC_CMPSTATUS_TEMPREF }, - { LMS7002MCSR::INTADC_CMPSTATUS_TEMPVPTAT, &LMS7002MCSR_Data::INTADC_CMPSTATUS_TEMPVPTAT }, - { LMS7002MCSR::INTADC_CMPSTATUS_RSSI2, &LMS7002MCSR_Data::INTADC_CMPSTATUS_RSSI2 }, - { LMS7002MCSR::INTADC_CMPSTATUS_RSSI1, &LMS7002MCSR_Data::INTADC_CMPSTATUS_RSSI1 }, - { LMS7002MCSR::INTADC_CMPSTATUS_PDET2, &LMS7002MCSR_Data::INTADC_CMPSTATUS_PDET2 }, - { LMS7002MCSR::INTADC_CMPSTATUS_PDET1, &LMS7002MCSR_Data::INTADC_CMPSTATUS_PDET1 }, - { LMS7002MCSR::RSSI_BIAS, &LMS7002MCSR_Data::RSSI_BIAS }, - { LMS7002MCSR::RSSI_HYSCMP, &LMS7002MCSR_Data::RSSI_HYSCMP }, - { LMS7002MCSR::INTADC_CMPCFG_TEMPREF, &LMS7002MCSR_Data::INTADC_CMPCFG_TEMPREF }, - { LMS7002MCSR::INTADC_CMPCFG_TEMPVPTAT, &LMS7002MCSR_Data::INTADC_CMPCFG_TEMPVPTAT }, - { LMS7002MCSR::INTADC_CMPCFG_RSSI2, &LMS7002MCSR_Data::INTADC_CMPCFG_RSSI2 }, - { LMS7002MCSR::INTADC_CMPCFG_RSSI1, &LMS7002MCSR_Data::INTADC_CMPCFG_RSSI1 }, - { LMS7002MCSR::INTADC_CMPCFG_PDET2, &LMS7002MCSR_Data::INTADC_CMPCFG_PDET2 }, - { LMS7002MCSR::INTADC_CMPCFG_PDET1, &LMS7002MCSR_Data::INTADC_CMPCFG_PDET1 }, - { LMS7002MCSR::RSSI_DAC_VAL, &LMS7002MCSR_Data::RSSI_DAC_VAL }, - { LMS7002MCSR::RSSI_PDET2_VAL, &LMS7002MCSR_Data::RSSI_PDET2_VAL }, - { LMS7002MCSR::RSSI_PDET1_VAL, &LMS7002MCSR_Data::RSSI_PDET1_VAL }, - { LMS7002MCSR::RSSI_RSSI2_VAL, &LMS7002MCSR_Data::RSSI_RSSI2_VAL }, - { LMS7002MCSR::RSSI_RSSI1_VAL, &LMS7002MCSR_Data::RSSI_RSSI1_VAL }, - { LMS7002MCSR::RSSI_TREF_VAL, &LMS7002MCSR_Data::RSSI_TREF_VAL }, - { LMS7002MCSR::RSSI_TVPTAT_VAL, &LMS7002MCSR_Data::RSSI_TVPTAT_VAL }, - { LMS7002MCSR::RSSIDC_CMPSTATUS, &LMS7002MCSR_Data::RSSIDC_CMPSTATUS }, - { LMS7002MCSR::RSSIDC_RSEL, &LMS7002MCSR_Data::RSSIDC_RSEL }, - { LMS7002MCSR::RSSIDC_HYSCMP, &LMS7002MCSR_Data::RSSIDC_HYSCMP }, - { LMS7002MCSR::RSSIDC_PD, &LMS7002MCSR_Data::RSSIDC_PD }, - { LMS7002MCSR::RSSIDC_DCO2, &LMS7002MCSR_Data::RSSIDC_DCO2 }, - { LMS7002MCSR::RSSIDC_DCO1, &LMS7002MCSR_Data::RSSIDC_DCO1 }, - { LMS7002MCSR::DCLOOP_STOP, &LMS7002MCSR_Data::DCLOOP_STOP }, -}; - static const LMS7002MCSR_Data::CSRegister InvalidReg; LIME_API const lime::LMS7002MCSR_Data::CSRegister& GetRegister(lime::LMS7002MCSR csr_enum) { + static const std::unordered_map LMS7002MCSR_map = { + { LMS7002MCSR::LRST_TX_B, LMS7002MCSR_Data::LRST_TX_B }, + { LMS7002MCSR::MRST_TX_B, LMS7002MCSR_Data::MRST_TX_B }, + { LMS7002MCSR::LRST_TX_A, LMS7002MCSR_Data::LRST_TX_A }, + { LMS7002MCSR::MRST_TX_A, LMS7002MCSR_Data::MRST_TX_A }, + { LMS7002MCSR::LRST_RX_B, LMS7002MCSR_Data::LRST_RX_B }, + { LMS7002MCSR::MRST_RX_B, LMS7002MCSR_Data::MRST_RX_B }, + { LMS7002MCSR::LRST_RX_A, LMS7002MCSR_Data::LRST_RX_A }, + { LMS7002MCSR::MRST_RX_A, LMS7002MCSR_Data::MRST_RX_A }, + { LMS7002MCSR::SRST_RXFIFO, LMS7002MCSR_Data::SRST_RXFIFO }, + { LMS7002MCSR::SRST_TXFIFO, LMS7002MCSR_Data::SRST_TXFIFO }, + { LMS7002MCSR::RXEN_B, LMS7002MCSR_Data::RXEN_B }, + { LMS7002MCSR::RXEN_A, LMS7002MCSR_Data::RXEN_A }, + { LMS7002MCSR::TXEN_B, LMS7002MCSR_Data::TXEN_B }, + { LMS7002MCSR::TXEN_A, LMS7002MCSR_Data::TXEN_A }, + { LMS7002MCSR::MAC, LMS7002MCSR_Data::MAC }, + { LMS7002MCSR::TX_CLK_PE, LMS7002MCSR_Data::TX_CLK_PE }, + { LMS7002MCSR::RX_CLK_PE, LMS7002MCSR_Data::RX_CLK_PE }, + { LMS7002MCSR::SDA_PE, LMS7002MCSR_Data::SDA_PE }, + { LMS7002MCSR::SDA_DS, LMS7002MCSR_Data::SDA_DS }, + { LMS7002MCSR::SCL_PE, LMS7002MCSR_Data::SCL_PE }, + { LMS7002MCSR::SCL_DS, LMS7002MCSR_Data::SCL_DS }, + { LMS7002MCSR::SDIO_DS, LMS7002MCSR_Data::SDIO_DS }, + { LMS7002MCSR::SDIO_PE, LMS7002MCSR_Data::SDIO_PE }, + { LMS7002MCSR::SDO_PE, LMS7002MCSR_Data::SDO_PE }, + { LMS7002MCSR::SCLK_PE, LMS7002MCSR_Data::SCLK_PE }, + { LMS7002MCSR::SEN_PE, LMS7002MCSR_Data::SEN_PE }, + { LMS7002MCSR::SPIMODE, LMS7002MCSR_Data::SPIMODE }, + { LMS7002MCSR::DIQ2_DS, LMS7002MCSR_Data::DIQ2_DS }, + { LMS7002MCSR::DIQ2_PE, LMS7002MCSR_Data::DIQ2_PE }, + { LMS7002MCSR::IQ_SEL_EN_2_PE, LMS7002MCSR_Data::IQ_SEL_EN_2_PE }, + { LMS7002MCSR::TXNRX2_PE, LMS7002MCSR_Data::TXNRX2_PE }, + { LMS7002MCSR::FCLK2_PE, LMS7002MCSR_Data::FCLK2_PE }, + { LMS7002MCSR::MCLK2_PE, LMS7002MCSR_Data::MCLK2_PE }, + { LMS7002MCSR::DIQ1_DS, LMS7002MCSR_Data::DIQ1_DS }, + { LMS7002MCSR::DIQ1_PE, LMS7002MCSR_Data::DIQ1_PE }, + { LMS7002MCSR::IQ_SEL_EN_1_PE, LMS7002MCSR_Data::IQ_SEL_EN_1_PE }, + { LMS7002MCSR::TXNRX1_PE, LMS7002MCSR_Data::TXNRX1_PE }, + { LMS7002MCSR::FCLK1_PE, LMS7002MCSR_Data::FCLK1_PE }, + { LMS7002MCSR::MCLK1_PE, LMS7002MCSR_Data::MCLK1_PE }, + { LMS7002MCSR::DIQDIRCTR2, LMS7002MCSR_Data::DIQDIRCTR2 }, + { LMS7002MCSR::DIQDIR2, LMS7002MCSR_Data::DIQDIR2 }, + { LMS7002MCSR::DIQDIRCTR1, LMS7002MCSR_Data::DIQDIRCTR1 }, + { LMS7002MCSR::DIQDIR1, LMS7002MCSR_Data::DIQDIR1 }, + { LMS7002MCSR::ENABLEDIRCTR2, LMS7002MCSR_Data::ENABLEDIRCTR2 }, + { LMS7002MCSR::ENABLEDIR2, LMS7002MCSR_Data::ENABLEDIR2 }, + { LMS7002MCSR::ENABLEDIRCTR1, LMS7002MCSR_Data::ENABLEDIRCTR1 }, + { LMS7002MCSR::ENABLEDIR1, LMS7002MCSR_Data::ENABLEDIR1 }, + { LMS7002MCSR::MOD_EN, LMS7002MCSR_Data::MOD_EN }, + { LMS7002MCSR::LML2_FIDM, LMS7002MCSR_Data::LML2_FIDM }, + { LMS7002MCSR::LML2_TXNRXIQ, LMS7002MCSR_Data::LML2_TXNRXIQ }, + { LMS7002MCSR::LML2_MODE, LMS7002MCSR_Data::LML2_MODE }, + { LMS7002MCSR::LML1_FIDM, LMS7002MCSR_Data::LML1_FIDM }, + { LMS7002MCSR::LML1_TXNRXIQ, LMS7002MCSR_Data::LML1_TXNRXIQ }, + { LMS7002MCSR::LML1_MODE, LMS7002MCSR_Data::LML1_MODE }, + { LMS7002MCSR::LML1_S3S, LMS7002MCSR_Data::LML1_S3S }, + { LMS7002MCSR::LML1_S2S, LMS7002MCSR_Data::LML1_S2S }, + { LMS7002MCSR::LML1_S1S, LMS7002MCSR_Data::LML1_S1S }, + { LMS7002MCSR::LML1_S0S, LMS7002MCSR_Data::LML1_S0S }, + { LMS7002MCSR::LML1_BQP, LMS7002MCSR_Data::LML1_BQP }, + { LMS7002MCSR::LML1_BIP, LMS7002MCSR_Data::LML1_BIP }, + { LMS7002MCSR::LML1_AQP, LMS7002MCSR_Data::LML1_AQP }, + { LMS7002MCSR::LML1_AIP, LMS7002MCSR_Data::LML1_AIP }, + { LMS7002MCSR::LML1_BB2RF_PST, LMS7002MCSR_Data::LML1_BB2RF_PST }, + { LMS7002MCSR::LML1_BB2RF_PRE, LMS7002MCSR_Data::LML1_BB2RF_PRE }, + { LMS7002MCSR::LML1_RF2BB_PST, LMS7002MCSR_Data::LML1_RF2BB_PST }, + { LMS7002MCSR::LML1_RF2BB_PRE, LMS7002MCSR_Data::LML1_RF2BB_PRE }, + { LMS7002MCSR::LML2_S3S, LMS7002MCSR_Data::LML2_S3S }, + { LMS7002MCSR::LML2_S2S, LMS7002MCSR_Data::LML2_S2S }, + { LMS7002MCSR::LML2_S1S, LMS7002MCSR_Data::LML2_S1S }, + { LMS7002MCSR::LML2_S0S, LMS7002MCSR_Data::LML2_S0S }, + { LMS7002MCSR::LML2_BQP, LMS7002MCSR_Data::LML2_BQP }, + { LMS7002MCSR::LML2_BIP, LMS7002MCSR_Data::LML2_BIP }, + { LMS7002MCSR::LML2_AQP, LMS7002MCSR_Data::LML2_AQP }, + { LMS7002MCSR::LML2_AIP, LMS7002MCSR_Data::LML2_AIP }, + { LMS7002MCSR::LML2_BB2RF_PST, LMS7002MCSR_Data::LML2_BB2RF_PST }, + { LMS7002MCSR::LML2_BB2RF_PRE, LMS7002MCSR_Data::LML2_BB2RF_PRE }, + { LMS7002MCSR::LML2_RF2BB_PST, LMS7002MCSR_Data::LML2_RF2BB_PST }, + { LMS7002MCSR::LML2_RF2BB_PRE, LMS7002MCSR_Data::LML2_RF2BB_PRE }, + { LMS7002MCSR::FCLK2_DLY, LMS7002MCSR_Data::FCLK2_DLY }, + { LMS7002MCSR::FCLK1_DLY, LMS7002MCSR_Data::FCLK1_DLY }, + { LMS7002MCSR::RX_MUX, LMS7002MCSR_Data::RX_MUX }, + { LMS7002MCSR::TX_MUX, LMS7002MCSR_Data::TX_MUX }, + { LMS7002MCSR::TXRDCLK_MUX, LMS7002MCSR_Data::TXRDCLK_MUX }, + { LMS7002MCSR::TXWRCLK_MUX, LMS7002MCSR_Data::TXWRCLK_MUX }, + { LMS7002MCSR::RXRDCLK_MUX, LMS7002MCSR_Data::RXRDCLK_MUX }, + { LMS7002MCSR::RXWRCLK_MUX, LMS7002MCSR_Data::RXWRCLK_MUX }, + { LMS7002MCSR::FCLK2_INV, LMS7002MCSR_Data::FCLK2_INV }, + { LMS7002MCSR::FCLK1_INV, LMS7002MCSR_Data::FCLK1_INV }, + { LMS7002MCSR::MCLK2DLY, LMS7002MCSR_Data::MCLK2DLY }, + { LMS7002MCSR::MCLK1DLY, LMS7002MCSR_Data::MCLK1DLY }, + { LMS7002MCSR::MCLK2SRC, LMS7002MCSR_Data::MCLK2SRC }, + { LMS7002MCSR::MCLK1SRC, LMS7002MCSR_Data::MCLK1SRC }, + { LMS7002MCSR::TXDIVEN, LMS7002MCSR_Data::TXDIVEN }, + { LMS7002MCSR::RXDIVEN, LMS7002MCSR_Data::RXDIVEN }, + { LMS7002MCSR::TXTSPCLKA_DIV, LMS7002MCSR_Data::TXTSPCLKA_DIV }, + { LMS7002MCSR::RXTSPCLKA_DIV, LMS7002MCSR_Data::RXTSPCLKA_DIV }, + { LMS7002MCSR::MIMO_SISO, LMS7002MCSR_Data::MIMO_SISO }, + { LMS7002MCSR::VER, LMS7002MCSR_Data::VER }, + { LMS7002MCSR::REV, LMS7002MCSR_Data::REV }, + { LMS7002MCSR::MASK, LMS7002MCSR_Data::MASK }, + { LMS7002MCSR::EN_DIR_LDO, LMS7002MCSR_Data::EN_DIR_LDO }, + { LMS7002MCSR::EN_DIR_CGEN, LMS7002MCSR_Data::EN_DIR_CGEN }, + { LMS7002MCSR::EN_DIR_XBUF, LMS7002MCSR_Data::EN_DIR_XBUF }, + { LMS7002MCSR::EN_DIR_AFE, LMS7002MCSR_Data::EN_DIR_AFE }, + { LMS7002MCSR::ISEL_DAC_AFE, LMS7002MCSR_Data::ISEL_DAC_AFE }, + { LMS7002MCSR::MODE_INTERLEAVE_AFE, LMS7002MCSR_Data::MODE_INTERLEAVE_AFE }, + { LMS7002MCSR::MUX_AFE_1, LMS7002MCSR_Data::MUX_AFE_1 }, + { LMS7002MCSR::MUX_AFE_2, LMS7002MCSR_Data::MUX_AFE_2 }, + { LMS7002MCSR::PD_AFE, LMS7002MCSR_Data::PD_AFE }, + { LMS7002MCSR::PD_RX_AFE1, LMS7002MCSR_Data::PD_RX_AFE1 }, + { LMS7002MCSR::PD_RX_AFE2, LMS7002MCSR_Data::PD_RX_AFE2 }, + { LMS7002MCSR::PD_TX_AFE1, LMS7002MCSR_Data::PD_TX_AFE1 }, + { LMS7002MCSR::PD_TX_AFE2, LMS7002MCSR_Data::PD_TX_AFE2 }, + { LMS7002MCSR::EN_G_AFE, LMS7002MCSR_Data::EN_G_AFE }, + { LMS7002MCSR::MUX_BIAS_OUT, LMS7002MCSR_Data::MUX_BIAS_OUT }, + { LMS7002MCSR::RP_CALIB_BIAS, LMS7002MCSR_Data::RP_CALIB_BIAS }, + { LMS7002MCSR::PD_FRP_BIAS, LMS7002MCSR_Data::PD_FRP_BIAS }, + { LMS7002MCSR::PD_F_BIAS, LMS7002MCSR_Data::PD_F_BIAS }, + { LMS7002MCSR::PD_PTRP_BIAS, LMS7002MCSR_Data::PD_PTRP_BIAS }, + { LMS7002MCSR::PD_PT_BIAS, LMS7002MCSR_Data::PD_PT_BIAS }, + { LMS7002MCSR::PD_BIAS_MASTER, LMS7002MCSR_Data::PD_BIAS_MASTER }, + { LMS7002MCSR::SLFB_XBUF_RX, LMS7002MCSR_Data::SLFB_XBUF_RX }, + { LMS7002MCSR::SLFB_XBUF_TX, LMS7002MCSR_Data::SLFB_XBUF_TX }, + { LMS7002MCSR::BYP_XBUF_RX, LMS7002MCSR_Data::BYP_XBUF_RX }, + { LMS7002MCSR::BYP_XBUF_TX, LMS7002MCSR_Data::BYP_XBUF_TX }, + { LMS7002MCSR::EN_OUT2_XBUF_TX, LMS7002MCSR_Data::EN_OUT2_XBUF_TX }, + { LMS7002MCSR::EN_TBUFIN_XBUF_RX, LMS7002MCSR_Data::EN_TBUFIN_XBUF_RX }, + { LMS7002MCSR::PD_XBUF_RX, LMS7002MCSR_Data::PD_XBUF_RX }, + { LMS7002MCSR::PD_XBUF_TX, LMS7002MCSR_Data::PD_XBUF_TX }, + { LMS7002MCSR::EN_G_XBUF, LMS7002MCSR_Data::EN_G_XBUF }, + { LMS7002MCSR::SPDUP_VCO_CGEN, LMS7002MCSR_Data::SPDUP_VCO_CGEN }, + { LMS7002MCSR::RESET_N_CGEN, LMS7002MCSR_Data::RESET_N_CGEN }, + { LMS7002MCSR::EN_ADCCLKH_CLKGN, LMS7002MCSR_Data::EN_ADCCLKH_CLKGN }, + { LMS7002MCSR::EN_COARSE_CKLGEN, LMS7002MCSR_Data::EN_COARSE_CKLGEN }, + { LMS7002MCSR::EN_INTONLY_SDM_CGEN, LMS7002MCSR_Data::EN_INTONLY_SDM_CGEN }, + { LMS7002MCSR::EN_SDM_CLK_CGEN, LMS7002MCSR_Data::EN_SDM_CLK_CGEN }, + { LMS7002MCSR::PD_CP_CGEN, LMS7002MCSR_Data::PD_CP_CGEN }, + { LMS7002MCSR::PD_FDIV_FB_CGEN, LMS7002MCSR_Data::PD_FDIV_FB_CGEN }, + { LMS7002MCSR::PD_FDIV_O_CGEN, LMS7002MCSR_Data::PD_FDIV_O_CGEN }, + { LMS7002MCSR::PD_SDM_CGEN, LMS7002MCSR_Data::PD_SDM_CGEN }, + { LMS7002MCSR::PD_VCO_CGEN, LMS7002MCSR_Data::PD_VCO_CGEN }, + { LMS7002MCSR::PD_VCO_COMP_CGEN, LMS7002MCSR_Data::PD_VCO_COMP_CGEN }, + { LMS7002MCSR::EN_G_CGEN, LMS7002MCSR_Data::EN_G_CGEN }, + { LMS7002MCSR::FRAC_SDM_CGEN_LSB, LMS7002MCSR_Data::FRAC_SDM_CGEN_LSB }, + { LMS7002MCSR::INT_SDM_CGEN, LMS7002MCSR_Data::INT_SDM_CGEN }, + { LMS7002MCSR::FRAC_SDM_CGEN_MSB, LMS7002MCSR_Data::FRAC_SDM_CGEN_MSB }, + { LMS7002MCSR::REV_SDMCLK_CGEN, LMS7002MCSR_Data::REV_SDMCLK_CGEN }, + { LMS7002MCSR::SEL_SDMCLK_CGEN, LMS7002MCSR_Data::SEL_SDMCLK_CGEN }, + { LMS7002MCSR::SX_DITHER_EN_CGEN, LMS7002MCSR_Data::SX_DITHER_EN_CGEN }, + { LMS7002MCSR::CLKH_OV_CLKL_CGEN, LMS7002MCSR_Data::CLKH_OV_CLKL_CGEN }, + { LMS7002MCSR::DIV_OUTCH_CGEN, LMS7002MCSR_Data::DIV_OUTCH_CGEN }, + { LMS7002MCSR::TST_CGEN, LMS7002MCSR_Data::TST_CGEN }, + { LMS7002MCSR::REV_CLKDAC_CGEN, LMS7002MCSR_Data::REV_CLKDAC_CGEN }, + { LMS7002MCSR::CMPLO_CTRL_CGEN, LMS7002MCSR_Data::CMPLO_CTRL_CGEN }, + { LMS7002MCSR::REV_CLKADC_CGEN, LMS7002MCSR_Data::REV_CLKADC_CGEN }, + { LMS7002MCSR::REVPH_PFD_CGEN, LMS7002MCSR_Data::REVPH_PFD_CGEN }, + { LMS7002MCSR::IOFFSET_CP_CGEN, LMS7002MCSR_Data::IOFFSET_CP_CGEN }, + { LMS7002MCSR::IPULSE_CP_CGEN, LMS7002MCSR_Data::IPULSE_CP_CGEN }, + { LMS7002MCSR::ICT_VCO_CGEN, LMS7002MCSR_Data::ICT_VCO_CGEN }, + { LMS7002MCSR::CSW_VCO_CGEN, LMS7002MCSR_Data::CSW_VCO_CGEN }, + { LMS7002MCSR::COARSE_START_CGEN, LMS7002MCSR_Data::COARSE_START_CGEN }, + { LMS7002MCSR::COARSE_STEPDONE_CGEN, LMS7002MCSR_Data::COARSE_STEPDONE_CGEN }, + { LMS7002MCSR::COARSEPLL_COMPO_CGEN, LMS7002MCSR_Data::COARSEPLL_COMPO_CGEN }, + { LMS7002MCSR::VCO_CMPHO_CGEN, LMS7002MCSR_Data::VCO_CMPHO_CGEN }, + { LMS7002MCSR::VCO_CMPLO_CGEN, LMS7002MCSR_Data::VCO_CMPLO_CGEN }, + { LMS7002MCSR::CP2_CGEN, LMS7002MCSR_Data::CP2_CGEN }, + { LMS7002MCSR::CP3_CGEN, LMS7002MCSR_Data::CP3_CGEN }, + { LMS7002MCSR::CZ_CGEN, LMS7002MCSR_Data::CZ_CGEN }, + { LMS7002MCSR::EN_LDO_DIG, LMS7002MCSR_Data::EN_LDO_DIG }, + { LMS7002MCSR::EN_LDO_DIGGN, LMS7002MCSR_Data::EN_LDO_DIGGN }, + { LMS7002MCSR::EN_LDO_DIGSXR, LMS7002MCSR_Data::EN_LDO_DIGSXR }, + { LMS7002MCSR::EN_LDO_DIGSXT, LMS7002MCSR_Data::EN_LDO_DIGSXT }, + { LMS7002MCSR::EN_LDO_DIVGN, LMS7002MCSR_Data::EN_LDO_DIVGN }, + { LMS7002MCSR::EN_LDO_DIVSXR, LMS7002MCSR_Data::EN_LDO_DIVSXR }, + { LMS7002MCSR::EN_LDO_DIVSXT, LMS7002MCSR_Data::EN_LDO_DIVSXT }, + { LMS7002MCSR::EN_LDO_LNA12, LMS7002MCSR_Data::EN_LDO_LNA12 }, + { LMS7002MCSR::EN_LDO_LNA14, LMS7002MCSR_Data::EN_LDO_LNA14 }, + { LMS7002MCSR::EN_LDO_MXRFE, LMS7002MCSR_Data::EN_LDO_MXRFE }, + { LMS7002MCSR::EN_LDO_RBB, LMS7002MCSR_Data::EN_LDO_RBB }, + { LMS7002MCSR::EN_LDO_RXBUF, LMS7002MCSR_Data::EN_LDO_RXBUF }, + { LMS7002MCSR::EN_LDO_TBB, LMS7002MCSR_Data::EN_LDO_TBB }, + { LMS7002MCSR::EN_LDO_TIA12, LMS7002MCSR_Data::EN_LDO_TIA12 }, + { LMS7002MCSR::EN_LDO_TIA14, LMS7002MCSR_Data::EN_LDO_TIA14 }, + { LMS7002MCSR::EN_G_LDO, LMS7002MCSR_Data::EN_G_LDO }, + { LMS7002MCSR::EN_LOADIMP_LDO_TLOB, LMS7002MCSR_Data::EN_LOADIMP_LDO_TLOB }, + { LMS7002MCSR::EN_LOADIMP_LDO_TPAD, LMS7002MCSR_Data::EN_LOADIMP_LDO_TPAD }, + { LMS7002MCSR::EN_LOADIMP_LDO_TXBUF, LMS7002MCSR_Data::EN_LOADIMP_LDO_TXBUF }, + { LMS7002MCSR::EN_LOADIMP_LDO_VCOGN, LMS7002MCSR_Data::EN_LOADIMP_LDO_VCOGN }, + { LMS7002MCSR::EN_LOADIMP_LDO_VCOSXR, LMS7002MCSR_Data::EN_LOADIMP_LDO_VCOSXR }, + { LMS7002MCSR::EN_LOADIMP_LDO_VCOSXT, LMS7002MCSR_Data::EN_LOADIMP_LDO_VCOSXT }, + { LMS7002MCSR::EN_LDO_AFE, LMS7002MCSR_Data::EN_LDO_AFE }, + { LMS7002MCSR::EN_LDO_CPGN, LMS7002MCSR_Data::EN_LDO_CPGN }, + { LMS7002MCSR::EN_LDO_CPSXR, LMS7002MCSR_Data::EN_LDO_CPSXR }, + { LMS7002MCSR::EN_LDO_TLOB, LMS7002MCSR_Data::EN_LDO_TLOB }, + { LMS7002MCSR::EN_LDO_TPAD, LMS7002MCSR_Data::EN_LDO_TPAD }, + { LMS7002MCSR::EN_LDO_TXBUF, LMS7002MCSR_Data::EN_LDO_TXBUF }, + { LMS7002MCSR::EN_LDO_VCOGN, LMS7002MCSR_Data::EN_LDO_VCOGN }, + { LMS7002MCSR::EN_LDO_VCOSXR, LMS7002MCSR_Data::EN_LDO_VCOSXR }, + { LMS7002MCSR::EN_LDO_VCOSXT, LMS7002MCSR_Data::EN_LDO_VCOSXT }, + { LMS7002MCSR::EN_LDO_CPSXT, LMS7002MCSR_Data::EN_LDO_CPSXT }, + { LMS7002MCSR::EN_LOADIMP_LDO_CPSXT, LMS7002MCSR_Data::EN_LOADIMP_LDO_CPSXT }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIG, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIG }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIGGN, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGGN }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIGSXR, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGSXR }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIGSXT, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGSXT }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIVGN, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIVGN }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIVSXR, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIVSXR }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIVSXT, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIVSXT }, + { LMS7002MCSR::EN_LOADIMP_LDO_LNA12, LMS7002MCSR_Data::EN_LOADIMP_LDO_LNA12 }, + { LMS7002MCSR::EN_LOADIMP_LDO_LNA14, LMS7002MCSR_Data::EN_LOADIMP_LDO_LNA14 }, + { LMS7002MCSR::EN_LOADIMP_LDO_MXRFE, LMS7002MCSR_Data::EN_LOADIMP_LDO_MXRFE }, + { LMS7002MCSR::EN_LOADIMP_LDO_RBB, LMS7002MCSR_Data::EN_LOADIMP_LDO_RBB }, + { LMS7002MCSR::EN_LOADIMP_LDO_RXBUF, LMS7002MCSR_Data::EN_LOADIMP_LDO_RXBUF }, + { LMS7002MCSR::EN_LOADIMP_LDO_TBB, LMS7002MCSR_Data::EN_LOADIMP_LDO_TBB }, + { LMS7002MCSR::EN_LOADIMP_LDO_TIA12, LMS7002MCSR_Data::EN_LOADIMP_LDO_TIA12 }, + { LMS7002MCSR::EN_LOADIMP_LDO_TIA14, LMS7002MCSR_Data::EN_LOADIMP_LDO_TIA14 }, + { LMS7002MCSR::BYP_LDO_TBB, LMS7002MCSR_Data::BYP_LDO_TBB }, + { LMS7002MCSR::BYP_LDO_TIA12, LMS7002MCSR_Data::BYP_LDO_TIA12 }, + { LMS7002MCSR::BYP_LDO_TIA14, LMS7002MCSR_Data::BYP_LDO_TIA14 }, + { LMS7002MCSR::BYP_LDO_TLOB, LMS7002MCSR_Data::BYP_LDO_TLOB }, + { LMS7002MCSR::BYP_LDO_TPAD, LMS7002MCSR_Data::BYP_LDO_TPAD }, + { LMS7002MCSR::BYP_LDO_TXBUF, LMS7002MCSR_Data::BYP_LDO_TXBUF }, + { LMS7002MCSR::BYP_LDO_VCOGN, LMS7002MCSR_Data::BYP_LDO_VCOGN }, + { LMS7002MCSR::BYP_LDO_VCOSXR, LMS7002MCSR_Data::BYP_LDO_VCOSXR }, + { LMS7002MCSR::BYP_LDO_VCOSXT, LMS7002MCSR_Data::BYP_LDO_VCOSXT }, + { LMS7002MCSR::EN_LOADIMP_LDO_AFE, LMS7002MCSR_Data::EN_LOADIMP_LDO_AFE }, + { LMS7002MCSR::EN_LOADIMP_LDO_CPGN, LMS7002MCSR_Data::EN_LOADIMP_LDO_CPGN }, + { LMS7002MCSR::EN_LOADIMP_LDO_CPSXR, LMS7002MCSR_Data::EN_LOADIMP_LDO_CPSXR }, + { LMS7002MCSR::BYP_LDO_AFE, LMS7002MCSR_Data::BYP_LDO_AFE }, + { LMS7002MCSR::BYP_LDO_CPGN, LMS7002MCSR_Data::BYP_LDO_CPGN }, + { LMS7002MCSR::BYP_LDO_CPSXR, LMS7002MCSR_Data::BYP_LDO_CPSXR }, + { LMS7002MCSR::BYP_LDO_CPSXT, LMS7002MCSR_Data::BYP_LDO_CPSXT }, + { LMS7002MCSR::BYP_LDO_DIG, LMS7002MCSR_Data::BYP_LDO_DIG }, + { LMS7002MCSR::BYP_LDO_DIGGN, LMS7002MCSR_Data::BYP_LDO_DIGGN }, + { LMS7002MCSR::BYP_LDO_DIGSXR, LMS7002MCSR_Data::BYP_LDO_DIGSXR }, + { LMS7002MCSR::BYP_LDO_DIGSXT, LMS7002MCSR_Data::BYP_LDO_DIGSXT }, + { LMS7002MCSR::BYP_LDO_DIVGN, LMS7002MCSR_Data::BYP_LDO_DIVGN }, + { LMS7002MCSR::BYP_LDO_DIVSXR, LMS7002MCSR_Data::BYP_LDO_DIVSXR }, + { LMS7002MCSR::BYP_LDO_DIVSXT, LMS7002MCSR_Data::BYP_LDO_DIVSXT }, + { LMS7002MCSR::BYP_LDO_LNA12, LMS7002MCSR_Data::BYP_LDO_LNA12 }, + { LMS7002MCSR::BYP_LDO_LNA14, LMS7002MCSR_Data::BYP_LDO_LNA14 }, + { LMS7002MCSR::BYP_LDO_MXRFE, LMS7002MCSR_Data::BYP_LDO_MXRFE }, + { LMS7002MCSR::BYP_LDO_RBB, LMS7002MCSR_Data::BYP_LDO_RBB }, + { LMS7002MCSR::BYP_LDO_RXBUF, LMS7002MCSR_Data::BYP_LDO_RXBUF }, + { LMS7002MCSR::SPDUP_LDO_DIVSXR, LMS7002MCSR_Data::SPDUP_LDO_DIVSXR }, + { LMS7002MCSR::SPDUP_LDO_DIVSXT, LMS7002MCSR_Data::SPDUP_LDO_DIVSXT }, + { LMS7002MCSR::SPDUP_LDO_LNA12, LMS7002MCSR_Data::SPDUP_LDO_LNA12 }, + { LMS7002MCSR::SPDUP_LDO_LNA14, LMS7002MCSR_Data::SPDUP_LDO_LNA14 }, + { LMS7002MCSR::SPDUP_LDO_MXRFE, LMS7002MCSR_Data::SPDUP_LDO_MXRFE }, + { LMS7002MCSR::SPDUP_LDO_RBB, LMS7002MCSR_Data::SPDUP_LDO_RBB }, + { LMS7002MCSR::SPDUP_LDO_RXBUF, LMS7002MCSR_Data::SPDUP_LDO_RXBUF }, + { LMS7002MCSR::SPDUP_LDO_TBB, LMS7002MCSR_Data::SPDUP_LDO_TBB }, + { LMS7002MCSR::SPDUP_LDO_TIA12, LMS7002MCSR_Data::SPDUP_LDO_TIA12 }, + { LMS7002MCSR::SPDUP_LDO_TIA14, LMS7002MCSR_Data::SPDUP_LDO_TIA14 }, + { LMS7002MCSR::SPDUP_LDO_TLOB, LMS7002MCSR_Data::SPDUP_LDO_TLOB }, + { LMS7002MCSR::SPDUP_LDO_TPAD, LMS7002MCSR_Data::SPDUP_LDO_TPAD }, + { LMS7002MCSR::SPDUP_LDO_TXBUF, LMS7002MCSR_Data::SPDUP_LDO_TXBUF }, + { LMS7002MCSR::SPDUP_LDO_VCOGN, LMS7002MCSR_Data::SPDUP_LDO_VCOGN }, + { LMS7002MCSR::SPDUP_LDO_VCOSXR, LMS7002MCSR_Data::SPDUP_LDO_VCOSXR }, + { LMS7002MCSR::SPDUP_LDO_VCOSXT, LMS7002MCSR_Data::SPDUP_LDO_VCOSXT }, + { LMS7002MCSR::SPDUP_LDO_AFE, LMS7002MCSR_Data::SPDUP_LDO_AFE }, + { LMS7002MCSR::SPDUP_LDO_CPGN, LMS7002MCSR_Data::SPDUP_LDO_CPGN }, + { LMS7002MCSR::SPDUP_LDO_CPSXR, LMS7002MCSR_Data::SPDUP_LDO_CPSXR }, + { LMS7002MCSR::SPDUP_LDO_CPSXT, LMS7002MCSR_Data::SPDUP_LDO_CPSXT }, + { LMS7002MCSR::SPDUP_LDO_DIG, LMS7002MCSR_Data::SPDUP_LDO_DIG }, + { LMS7002MCSR::SPDUP_LDO_DIGGN, LMS7002MCSR_Data::SPDUP_LDO_DIGGN }, + { LMS7002MCSR::SPDUP_LDO_DIGSXR, LMS7002MCSR_Data::SPDUP_LDO_DIGSXR }, + { LMS7002MCSR::SPDUP_LDO_DIGSXT, LMS7002MCSR_Data::SPDUP_LDO_DIGSXT }, + { LMS7002MCSR::SPDUP_LDO_DIVGN, LMS7002MCSR_Data::SPDUP_LDO_DIVGN }, + { LMS7002MCSR::RDIV_VCOSXR, LMS7002MCSR_Data::RDIV_VCOSXR }, + { LMS7002MCSR::RDIV_VCOSXT, LMS7002MCSR_Data::RDIV_VCOSXT }, + { LMS7002MCSR::RDIV_TXBUF, LMS7002MCSR_Data::RDIV_TXBUF }, + { LMS7002MCSR::RDIV_VCOGN, LMS7002MCSR_Data::RDIV_VCOGN }, + { LMS7002MCSR::RDIV_TLOB, LMS7002MCSR_Data::RDIV_TLOB }, + { LMS7002MCSR::RDIV_TPAD, LMS7002MCSR_Data::RDIV_TPAD }, + { LMS7002MCSR::RDIV_TIA12, LMS7002MCSR_Data::RDIV_TIA12 }, + { LMS7002MCSR::RDIV_TIA14, LMS7002MCSR_Data::RDIV_TIA14 }, + { LMS7002MCSR::RDIV_RXBUF, LMS7002MCSR_Data::RDIV_RXBUF }, + { LMS7002MCSR::RDIV_TBB, LMS7002MCSR_Data::RDIV_TBB }, + { LMS7002MCSR::RDIV_MXRFE, LMS7002MCSR_Data::RDIV_MXRFE }, + { LMS7002MCSR::RDIV_RBB, LMS7002MCSR_Data::RDIV_RBB }, + { LMS7002MCSR::RDIV_LNA12, LMS7002MCSR_Data::RDIV_LNA12 }, + { LMS7002MCSR::RDIV_LNA14, LMS7002MCSR_Data::RDIV_LNA14 }, + { LMS7002MCSR::RDIV_DIVSXR, LMS7002MCSR_Data::RDIV_DIVSXR }, + { LMS7002MCSR::RDIV_DIVSXT, LMS7002MCSR_Data::RDIV_DIVSXT }, + { LMS7002MCSR::RDIV_DIGSXT, LMS7002MCSR_Data::RDIV_DIGSXT }, + { LMS7002MCSR::RDIV_DIVGN, LMS7002MCSR_Data::RDIV_DIVGN }, + { LMS7002MCSR::RDIV_DIGGN, LMS7002MCSR_Data::RDIV_DIGGN }, + { LMS7002MCSR::RDIV_DIGSXR, LMS7002MCSR_Data::RDIV_DIGSXR }, + { LMS7002MCSR::RDIV_CPSXT, LMS7002MCSR_Data::RDIV_CPSXT }, + { LMS7002MCSR::RDIV_DIG, LMS7002MCSR_Data::RDIV_DIG }, + { LMS7002MCSR::RDIV_CPGN, LMS7002MCSR_Data::RDIV_CPGN }, + { LMS7002MCSR::RDIV_CPSXR, LMS7002MCSR_Data::RDIV_CPSXR }, + { LMS7002MCSR::RDIV_SPIBUF, LMS7002MCSR_Data::RDIV_SPIBUF }, + { LMS7002MCSR::RDIV_AFE, LMS7002MCSR_Data::RDIV_AFE }, + { LMS7002MCSR::SPDUP_LDO_SPIBUF, LMS7002MCSR_Data::SPDUP_LDO_SPIBUF }, + { LMS7002MCSR::SPDUP_LDO_DIGIp2, LMS7002MCSR_Data::SPDUP_LDO_DIGIp2 }, + { LMS7002MCSR::SPDUP_LDO_DIGIp1, LMS7002MCSR_Data::SPDUP_LDO_DIGIp1 }, + { LMS7002MCSR::BYP_LDO_SPIBUF, LMS7002MCSR_Data::BYP_LDO_SPIBUF }, + { LMS7002MCSR::BYP_LDO_DIGIp2, LMS7002MCSR_Data::BYP_LDO_DIGIp2 }, + { LMS7002MCSR::BYP_LDO_DIGIp1, LMS7002MCSR_Data::BYP_LDO_DIGIp1 }, + { LMS7002MCSR::EN_LOADIMP_LDO_SPIBUF, LMS7002MCSR_Data::EN_LOADIMP_LDO_SPIBUF }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIGIp2, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGIp2 }, + { LMS7002MCSR::EN_LOADIMP_LDO_DIGIp1, LMS7002MCSR_Data::EN_LOADIMP_LDO_DIGIp1 }, + { LMS7002MCSR::PD_LDO_SPIBUF, LMS7002MCSR_Data::PD_LDO_SPIBUF }, + { LMS7002MCSR::PD_LDO_DIGIp2, LMS7002MCSR_Data::PD_LDO_DIGIp2 }, + { LMS7002MCSR::PD_LDO_DIGIp1, LMS7002MCSR_Data::PD_LDO_DIGIp1 }, + { LMS7002MCSR::EN_G_LDOP, LMS7002MCSR_Data::EN_G_LDOP }, + { LMS7002MCSR::RDIV_DIGIp2, LMS7002MCSR_Data::RDIV_DIGIp2 }, + { LMS7002MCSR::RDIV_DIGIp1, LMS7002MCSR_Data::RDIV_DIGIp1 }, + { LMS7002MCSR::BSIGT, LMS7002MCSR_Data::BSIGT }, + { LMS7002MCSR::BSTATE, LMS7002MCSR_Data::BSTATE }, + { LMS7002MCSR::EN_SDM_TSTO_SXT, LMS7002MCSR_Data::EN_SDM_TSTO_SXT }, + { LMS7002MCSR::EN_SDM_TSTO_SXR, LMS7002MCSR_Data::EN_SDM_TSTO_SXR }, + { LMS7002MCSR::EN_SDM_TSTO_CGEN, LMS7002MCSR_Data::EN_SDM_TSTO_CGEN }, + { LMS7002MCSR::BENC, LMS7002MCSR_Data::BENC }, + { LMS7002MCSR::BENR, LMS7002MCSR_Data::BENR }, + { LMS7002MCSR::BENT, LMS7002MCSR_Data::BENT }, + { LMS7002MCSR::BSTART, LMS7002MCSR_Data::BSTART }, + { LMS7002MCSR::BSIGR, LMS7002MCSR_Data::BSIGR }, + { LMS7002MCSR::BSIGC, LMS7002MCSR_Data::BSIGC }, + { LMS7002MCSR::CDS_MCLK2, LMS7002MCSR_Data::CDS_MCLK2 }, + { LMS7002MCSR::CDS_MCLK1, LMS7002MCSR_Data::CDS_MCLK1 }, + { LMS7002MCSR::CDSN_TXBTSP, LMS7002MCSR_Data::CDSN_TXBTSP }, + { LMS7002MCSR::CDSN_TXATSP, LMS7002MCSR_Data::CDSN_TXATSP }, + { LMS7002MCSR::CDSN_RXBTSP, LMS7002MCSR_Data::CDSN_RXBTSP }, + { LMS7002MCSR::CDSN_RXATSP, LMS7002MCSR_Data::CDSN_RXATSP }, + { LMS7002MCSR::CDSN_TXBLML, LMS7002MCSR_Data::CDSN_TXBLML }, + { LMS7002MCSR::CDSN_TXALML, LMS7002MCSR_Data::CDSN_TXALML }, + { LMS7002MCSR::CDSN_RXBLML, LMS7002MCSR_Data::CDSN_RXBLML }, + { LMS7002MCSR::CDSN_RXALML, LMS7002MCSR_Data::CDSN_RXALML }, + { LMS7002MCSR::CDSN_MCLK2, LMS7002MCSR_Data::CDSN_MCLK2 }, + { LMS7002MCSR::CDSN_MCLK1, LMS7002MCSR_Data::CDSN_MCLK1 }, + { LMS7002MCSR::CDS_TXBTSP, LMS7002MCSR_Data::CDS_TXBTSP }, + { LMS7002MCSR::CDS_TXATSP, LMS7002MCSR_Data::CDS_TXATSP }, + { LMS7002MCSR::CDS_RXBTSP, LMS7002MCSR_Data::CDS_RXBTSP }, + { LMS7002MCSR::CDS_RXATSP, LMS7002MCSR_Data::CDS_RXATSP }, + { LMS7002MCSR::CDS_TXBLML, LMS7002MCSR_Data::CDS_TXBLML }, + { LMS7002MCSR::CDS_TXALML, LMS7002MCSR_Data::CDS_TXALML }, + { LMS7002MCSR::CDS_RXBLML, LMS7002MCSR_Data::CDS_RXBLML }, + { LMS7002MCSR::CDS_RXALML, LMS7002MCSR_Data::CDS_RXALML }, + { LMS7002MCSR::EN_LOWBWLOMX_TMX_TRF, LMS7002MCSR_Data::EN_LOWBWLOMX_TMX_TRF }, + { LMS7002MCSR::EN_NEXTTX_TRF, LMS7002MCSR_Data::EN_NEXTTX_TRF }, + { LMS7002MCSR::EN_AMPHF_PDET_TRF, LMS7002MCSR_Data::EN_AMPHF_PDET_TRF }, + { LMS7002MCSR::LOADR_PDET_TRF, LMS7002MCSR_Data::LOADR_PDET_TRF }, + { LMS7002MCSR::PD_PDET_TRF, LMS7002MCSR_Data::PD_PDET_TRF }, + { LMS7002MCSR::PD_TLOBUF_TRF, LMS7002MCSR_Data::PD_TLOBUF_TRF }, + { LMS7002MCSR::PD_TXPAD_TRF, LMS7002MCSR_Data::PD_TXPAD_TRF }, + { LMS7002MCSR::EN_G_TRF, LMS7002MCSR_Data::EN_G_TRF }, + { LMS7002MCSR::F_TXPAD_TRF, LMS7002MCSR_Data::F_TXPAD_TRF }, + { LMS7002MCSR::L_LOOPB_TXPAD_TRF, LMS7002MCSR_Data::L_LOOPB_TXPAD_TRF }, + { LMS7002MCSR::LOSS_LIN_TXPAD_TRF, LMS7002MCSR_Data::LOSS_LIN_TXPAD_TRF }, + { LMS7002MCSR::LOSS_MAIN_TXPAD_TRF, LMS7002MCSR_Data::LOSS_MAIN_TXPAD_TRF }, + { LMS7002MCSR::EN_LOOPB_TXPAD_TRF, LMS7002MCSR_Data::EN_LOOPB_TXPAD_TRF }, + { LMS7002MCSR::GCAS_GNDREF_TXPAD_TRF, LMS7002MCSR_Data::GCAS_GNDREF_TXPAD_TRF }, + { LMS7002MCSR::ICT_LIN_TXPAD_TRF, LMS7002MCSR_Data::ICT_LIN_TXPAD_TRF }, + { LMS7002MCSR::ICT_MAIN_TXPAD_TRF, LMS7002MCSR_Data::ICT_MAIN_TXPAD_TRF }, + { LMS7002MCSR::VGCAS_TXPAD_TRF, LMS7002MCSR_Data::VGCAS_TXPAD_TRF }, + { LMS7002MCSR::SEL_BAND1_TRF, LMS7002MCSR_Data::SEL_BAND1_TRF }, + { LMS7002MCSR::SEL_BAND2_TRF, LMS7002MCSR_Data::SEL_BAND2_TRF }, + { LMS7002MCSR::LOBIASN_TXM_TRF, LMS7002MCSR_Data::LOBIASN_TXM_TRF }, + { LMS7002MCSR::LOBIASP_TXX_TRF, LMS7002MCSR_Data::LOBIASP_TXX_TRF }, + { LMS7002MCSR::CDC_I_TRF, LMS7002MCSR_Data::CDC_I_TRF }, + { LMS7002MCSR::CDC_Q_TRF, LMS7002MCSR_Data::CDC_Q_TRF }, + { LMS7002MCSR::STATPULSE_TBB, LMS7002MCSR_Data::STATPULSE_TBB }, + { LMS7002MCSR::LOOPB_TBB, LMS7002MCSR_Data::LOOPB_TBB }, + { LMS7002MCSR::PD_LPFH_TBB, LMS7002MCSR_Data::PD_LPFH_TBB }, + { LMS7002MCSR::PD_LPFIAMP_TBB, LMS7002MCSR_Data::PD_LPFIAMP_TBB }, + { LMS7002MCSR::PD_LPFLAD_TBB, LMS7002MCSR_Data::PD_LPFLAD_TBB }, + { LMS7002MCSR::PD_LPFS5_TBB, LMS7002MCSR_Data::PD_LPFS5_TBB }, + { LMS7002MCSR::EN_G_TBB, LMS7002MCSR_Data::EN_G_TBB }, + { LMS7002MCSR::ICT_LPFS5_F_TBB, LMS7002MCSR_Data::ICT_LPFS5_F_TBB }, + { LMS7002MCSR::ICT_LPFS5_PT_TBB, LMS7002MCSR_Data::ICT_LPFS5_PT_TBB }, + { LMS7002MCSR::ICT_LPF_H_PT_TBB, LMS7002MCSR_Data::ICT_LPF_H_PT_TBB }, + { LMS7002MCSR::ICT_LPFH_F_TBB, LMS7002MCSR_Data::ICT_LPFH_F_TBB }, + { LMS7002MCSR::ICT_LPFLAD_F_TBB, LMS7002MCSR_Data::ICT_LPFLAD_F_TBB }, + { LMS7002MCSR::ICT_LPFLAD_PT_TBB, LMS7002MCSR_Data::ICT_LPFLAD_PT_TBB }, + { LMS7002MCSR::CG_IAMP_TBB, LMS7002MCSR_Data::CG_IAMP_TBB }, + { LMS7002MCSR::ICT_IAMP_FRP_TBB, LMS7002MCSR_Data::ICT_IAMP_FRP_TBB }, + { LMS7002MCSR::ICT_IAMP_GG_FRP_TBB, LMS7002MCSR_Data::ICT_IAMP_GG_FRP_TBB }, + { LMS7002MCSR::RCAL_LPFH_TBB, LMS7002MCSR_Data::RCAL_LPFH_TBB }, + { LMS7002MCSR::RCAL_LPFLAD_TBB, LMS7002MCSR_Data::RCAL_LPFLAD_TBB }, + { LMS7002MCSR::TSTIN_TBB, LMS7002MCSR_Data::TSTIN_TBB }, + { LMS7002MCSR::BYPLADDER_TBB, LMS7002MCSR_Data::BYPLADDER_TBB }, + { LMS7002MCSR::CCAL_LPFLAD_TBB, LMS7002MCSR_Data::CCAL_LPFLAD_TBB }, + { LMS7002MCSR::RCAL_LPFS5_TBB, LMS7002MCSR_Data::RCAL_LPFS5_TBB }, + { LMS7002MCSR::CDC_I_RFE, LMS7002MCSR_Data::CDC_I_RFE }, + { LMS7002MCSR::CDC_Q_RFE, LMS7002MCSR_Data::CDC_Q_RFE }, + { LMS7002MCSR::PD_LNA_RFE, LMS7002MCSR_Data::PD_LNA_RFE }, + { LMS7002MCSR::PD_RLOOPB_1_RFE, LMS7002MCSR_Data::PD_RLOOPB_1_RFE }, + { LMS7002MCSR::PD_RLOOPB_2_RFE, LMS7002MCSR_Data::PD_RLOOPB_2_RFE }, + { LMS7002MCSR::PD_MXLOBUF_RFE, LMS7002MCSR_Data::PD_MXLOBUF_RFE }, + { LMS7002MCSR::PD_QGEN_RFE, LMS7002MCSR_Data::PD_QGEN_RFE }, + { LMS7002MCSR::PD_RSSI_RFE, LMS7002MCSR_Data::PD_RSSI_RFE }, + { LMS7002MCSR::PD_TIA_RFE, LMS7002MCSR_Data::PD_TIA_RFE }, + { LMS7002MCSR::EN_G_RFE, LMS7002MCSR_Data::EN_G_RFE }, + { LMS7002MCSR::SEL_PATH_RFE, LMS7002MCSR_Data::SEL_PATH_RFE }, + { LMS7002MCSR::EN_DCOFF_RXFE_RFE, LMS7002MCSR_Data::EN_DCOFF_RXFE_RFE }, + { LMS7002MCSR::EN_INSHSW_LB1_RFE, LMS7002MCSR_Data::EN_INSHSW_LB1_RFE }, + { LMS7002MCSR::EN_INSHSW_LB2_RFE, LMS7002MCSR_Data::EN_INSHSW_LB2_RFE }, + { LMS7002MCSR::EN_INSHSW_L_RFE, LMS7002MCSR_Data::EN_INSHSW_L_RFE }, + { LMS7002MCSR::EN_INSHSW_W_RFE, LMS7002MCSR_Data::EN_INSHSW_W_RFE }, + { LMS7002MCSR::EN_NEXTRX_RFE, LMS7002MCSR_Data::EN_NEXTRX_RFE }, + { LMS7002MCSR::DCOFFI_RFE, LMS7002MCSR_Data::DCOFFI_RFE }, + { LMS7002MCSR::DCOFFQ_RFE, LMS7002MCSR_Data::DCOFFQ_RFE }, + { LMS7002MCSR::ICT_LOOPB_RFE, LMS7002MCSR_Data::ICT_LOOPB_RFE }, + { LMS7002MCSR::ICT_TIAMAIN_RFE, LMS7002MCSR_Data::ICT_TIAMAIN_RFE }, + { LMS7002MCSR::ICT_TIAOUT_RFE, LMS7002MCSR_Data::ICT_TIAOUT_RFE }, + { LMS7002MCSR::ICT_LNACMO_RFE, LMS7002MCSR_Data::ICT_LNACMO_RFE }, + { LMS7002MCSR::ICT_LNA_RFE, LMS7002MCSR_Data::ICT_LNA_RFE }, + { LMS7002MCSR::ICT_LODC_RFE, LMS7002MCSR_Data::ICT_LODC_RFE }, + { LMS7002MCSR::CAP_RXMXO_RFE, LMS7002MCSR_Data::CAP_RXMXO_RFE }, + { LMS7002MCSR::CGSIN_LNA_RFE, LMS7002MCSR_Data::CGSIN_LNA_RFE }, + { LMS7002MCSR::CCOMP_TIA_RFE, LMS7002MCSR_Data::CCOMP_TIA_RFE }, + { LMS7002MCSR::CFB_TIA_RFE, LMS7002MCSR_Data::CFB_TIA_RFE }, + { LMS7002MCSR::G_LNA_RFE, LMS7002MCSR_Data::G_LNA_RFE }, + { LMS7002MCSR::G_RXLOOPB_RFE, LMS7002MCSR_Data::G_RXLOOPB_RFE }, + { LMS7002MCSR::G_TIA_RFE, LMS7002MCSR_Data::G_TIA_RFE }, + { LMS7002MCSR::RCOMP_TIA_RFE, LMS7002MCSR_Data::RCOMP_TIA_RFE }, + { LMS7002MCSR::RFB_TIA_RFE, LMS7002MCSR_Data::RFB_TIA_RFE }, + { LMS7002MCSR::EN_LB_LPFH_RBB, LMS7002MCSR_Data::EN_LB_LPFH_RBB }, + { LMS7002MCSR::EN_LB_LPFL_RBB, LMS7002MCSR_Data::EN_LB_LPFL_RBB }, + { LMS7002MCSR::PD_LPFH_RBB, LMS7002MCSR_Data::PD_LPFH_RBB }, + { LMS7002MCSR::PD_LPFL_RBB, LMS7002MCSR_Data::PD_LPFL_RBB }, + { LMS7002MCSR::PD_PGA_RBB, LMS7002MCSR_Data::PD_PGA_RBB }, + { LMS7002MCSR::EN_G_RBB, LMS7002MCSR_Data::EN_G_RBB }, + { LMS7002MCSR::R_CTL_LPF_RBB, LMS7002MCSR_Data::R_CTL_LPF_RBB }, + { LMS7002MCSR::RCC_CTL_LPFH_RBB, LMS7002MCSR_Data::RCC_CTL_LPFH_RBB }, + { LMS7002MCSR::C_CTL_LPFH_RBB, LMS7002MCSR_Data::C_CTL_LPFH_RBB }, + { LMS7002MCSR::RCC_CTL_LPFL_RBB, LMS7002MCSR_Data::RCC_CTL_LPFL_RBB }, + { LMS7002MCSR::C_CTL_LPFL_RBB, LMS7002MCSR_Data::C_CTL_LPFL_RBB }, + { LMS7002MCSR::INPUT_CTL_PGA_RBB, LMS7002MCSR_Data::INPUT_CTL_PGA_RBB }, + { LMS7002MCSR::ICT_LPF_IN_RBB, LMS7002MCSR_Data::ICT_LPF_IN_RBB }, + { LMS7002MCSR::ICT_LPF_OUT_RBB, LMS7002MCSR_Data::ICT_LPF_OUT_RBB }, + { LMS7002MCSR::OSW_PGA_RBB, LMS7002MCSR_Data::OSW_PGA_RBB }, + { LMS7002MCSR::ICT_PGA_OUT_RBB, LMS7002MCSR_Data::ICT_PGA_OUT_RBB }, + { LMS7002MCSR::ICT_PGA_IN_RBB, LMS7002MCSR_Data::ICT_PGA_IN_RBB }, + { LMS7002MCSR::G_PGA_RBB, LMS7002MCSR_Data::G_PGA_RBB }, + { LMS7002MCSR::RCC_CTL_PGA_RBB, LMS7002MCSR_Data::RCC_CTL_PGA_RBB }, + { LMS7002MCSR::C_CTL_PGA_RBB, LMS7002MCSR_Data::C_CTL_PGA_RBB }, + { LMS7002MCSR::RESET_N, LMS7002MCSR_Data::RESET_N }, + { LMS7002MCSR::SPDUP_VCO, LMS7002MCSR_Data::SPDUP_VCO }, + { LMS7002MCSR::BYPLDO_VCO, LMS7002MCSR_Data::BYPLDO_VCO }, + { LMS7002MCSR::EN_COARSEPLL, LMS7002MCSR_Data::EN_COARSEPLL }, + { LMS7002MCSR::CURLIM_VCO, LMS7002MCSR_Data::CURLIM_VCO }, + { LMS7002MCSR::EN_DIV2_DIVPROG, LMS7002MCSR_Data::EN_DIV2_DIVPROG }, + { LMS7002MCSR::EN_INTONLY_SDM, LMS7002MCSR_Data::EN_INTONLY_SDM }, + { LMS7002MCSR::EN_SDM_CLK, LMS7002MCSR_Data::EN_SDM_CLK }, + { LMS7002MCSR::PD_FBDIV, LMS7002MCSR_Data::PD_FBDIV }, + { LMS7002MCSR::PD_LOCH_T2RBUF, LMS7002MCSR_Data::PD_LOCH_T2RBUF }, + { LMS7002MCSR::PD_CP, LMS7002MCSR_Data::PD_CP }, + { LMS7002MCSR::PD_FDIV, LMS7002MCSR_Data::PD_FDIV }, + { LMS7002MCSR::PD_SDM, LMS7002MCSR_Data::PD_SDM }, + { LMS7002MCSR::PD_VCO_COMP, LMS7002MCSR_Data::PD_VCO_COMP }, + { LMS7002MCSR::PD_VCO, LMS7002MCSR_Data::PD_VCO }, + { LMS7002MCSR::EN_G, LMS7002MCSR_Data::EN_G }, + { LMS7002MCSR::FRAC_SDM_LSB, LMS7002MCSR_Data::FRAC_SDM_LSB }, + { LMS7002MCSR::INT_SDM, LMS7002MCSR_Data::INT_SDM }, + { LMS7002MCSR::FRAC_SDM_MSB, LMS7002MCSR_Data::FRAC_SDM_MSB }, + { LMS7002MCSR::PW_DIV2_LOCH, LMS7002MCSR_Data::PW_DIV2_LOCH }, + { LMS7002MCSR::PW_DIV4_LOCH, LMS7002MCSR_Data::PW_DIV4_LOCH }, + { LMS7002MCSR::DIV_LOCH, LMS7002MCSR_Data::DIV_LOCH }, + { LMS7002MCSR::TST_SX, LMS7002MCSR_Data::TST_SX }, + { LMS7002MCSR::SEL_SDMCLK, LMS7002MCSR_Data::SEL_SDMCLK }, + { LMS7002MCSR::SX_DITHER_EN, LMS7002MCSR_Data::SX_DITHER_EN }, + { LMS7002MCSR::REV_SDMCLK, LMS7002MCSR_Data::REV_SDMCLK }, + { LMS7002MCSR::VDIV_VCO, LMS7002MCSR_Data::VDIV_VCO }, + { LMS7002MCSR::ICT_VCO, LMS7002MCSR_Data::ICT_VCO }, + { LMS7002MCSR::RSEL_LDO_VCO, LMS7002MCSR_Data::RSEL_LDO_VCO }, + { LMS7002MCSR::CSW_VCO, LMS7002MCSR_Data::CSW_VCO }, + { LMS7002MCSR::SEL_VCO, LMS7002MCSR_Data::SEL_VCO }, + { LMS7002MCSR::COARSE_START, LMS7002MCSR_Data::COARSE_START }, + { LMS7002MCSR::REVPH_PFD, LMS7002MCSR_Data::REVPH_PFD }, + { LMS7002MCSR::IOFFSET_CP, LMS7002MCSR_Data::IOFFSET_CP }, + { LMS7002MCSR::IPULSE_CP, LMS7002MCSR_Data::IPULSE_CP }, + { LMS7002MCSR::COARSE_STEPDONE, LMS7002MCSR_Data::COARSE_STEPDONE }, + { LMS7002MCSR::COARSEPLL_COMPO, LMS7002MCSR_Data::COARSEPLL_COMPO }, + { LMS7002MCSR::VCO_CMPHO, LMS7002MCSR_Data::VCO_CMPHO }, + { LMS7002MCSR::VCO_CMPLO, LMS7002MCSR_Data::VCO_CMPLO }, + { LMS7002MCSR::CP2_PLL, LMS7002MCSR_Data::CP2_PLL }, + { LMS7002MCSR::CP3_PLL, LMS7002MCSR_Data::CP3_PLL }, + { LMS7002MCSR::CZ, LMS7002MCSR_Data::CZ }, + { LMS7002MCSR::EN_DIR_SXRSXT, LMS7002MCSR_Data::EN_DIR_SXRSXT }, + { LMS7002MCSR::EN_DIR_RBB, LMS7002MCSR_Data::EN_DIR_RBB }, + { LMS7002MCSR::EN_DIR_RFE, LMS7002MCSR_Data::EN_DIR_RFE }, + { LMS7002MCSR::EN_DIR_TBB, LMS7002MCSR_Data::EN_DIR_TBB }, + { LMS7002MCSR::EN_DIR_TRF, LMS7002MCSR_Data::EN_DIR_TRF }, + { LMS7002MCSR::TSGFC_TXTSP, LMS7002MCSR_Data::TSGFC_TXTSP }, + { LMS7002MCSR::TSGFCW_TXTSP, LMS7002MCSR_Data::TSGFCW_TXTSP }, + { LMS7002MCSR::TSGDCLDQ_TXTSP, LMS7002MCSR_Data::TSGDCLDQ_TXTSP }, + { LMS7002MCSR::TSGDCLDI_TXTSP, LMS7002MCSR_Data::TSGDCLDI_TXTSP }, + { LMS7002MCSR::TSGSWAPIQ_TXTSP, LMS7002MCSR_Data::TSGSWAPIQ_TXTSP }, + { LMS7002MCSR::TSGMODE_TXTSP, LMS7002MCSR_Data::TSGMODE_TXTSP }, + { LMS7002MCSR::INSEL_TXTSP, LMS7002MCSR_Data::INSEL_TXTSP }, + { LMS7002MCSR::BSTART_TXTSP, LMS7002MCSR_Data::BSTART_TXTSP }, + { LMS7002MCSR::EN_TXTSP, LMS7002MCSR_Data::EN_TXTSP }, + { LMS7002MCSR::GCORRQ_TXTSP, LMS7002MCSR_Data::GCORRQ_TXTSP }, + { LMS7002MCSR::GCORRI_TXTSP, LMS7002MCSR_Data::GCORRI_TXTSP }, + { LMS7002MCSR::HBI_OVR_TXTSP, LMS7002MCSR_Data::HBI_OVR_TXTSP }, + { LMS7002MCSR::IQCORR_TXTSP, LMS7002MCSR_Data::IQCORR_TXTSP }, + { LMS7002MCSR::DCCORRI_TXTSP, LMS7002MCSR_Data::DCCORRI_TXTSP }, + { LMS7002MCSR::DCCORRQ_TXTSP, LMS7002MCSR_Data::DCCORRQ_TXTSP }, + { LMS7002MCSR::GFIR1_L_TXTSP, LMS7002MCSR_Data::GFIR1_L_TXTSP }, + { LMS7002MCSR::GFIR1_N_TXTSP, LMS7002MCSR_Data::GFIR1_N_TXTSP }, + { LMS7002MCSR::GFIR2_L_TXTSP, LMS7002MCSR_Data::GFIR2_L_TXTSP }, + { LMS7002MCSR::GFIR2_N_TXTSP, LMS7002MCSR_Data::GFIR2_N_TXTSP }, + { LMS7002MCSR::GFIR3_L_TXTSP, LMS7002MCSR_Data::GFIR3_L_TXTSP }, + { LMS7002MCSR::GFIR3_N_TXTSP, LMS7002MCSR_Data::GFIR3_N_TXTSP }, + { LMS7002MCSR::CMIX_GAIN_TXTSP, LMS7002MCSR_Data::CMIX_GAIN_TXTSP }, + { LMS7002MCSR::CMIX_SC_TXTSP, LMS7002MCSR_Data::CMIX_SC_TXTSP }, + { LMS7002MCSR::CMIX_BYP_TXTSP, LMS7002MCSR_Data::CMIX_BYP_TXTSP }, + { LMS7002MCSR::ISINC_BYP_TXTSP, LMS7002MCSR_Data::ISINC_BYP_TXTSP }, + { LMS7002MCSR::GFIR3_BYP_TXTSP, LMS7002MCSR_Data::GFIR3_BYP_TXTSP }, + { LMS7002MCSR::GFIR2_BYP_TXTSP, LMS7002MCSR_Data::GFIR2_BYP_TXTSP }, + { LMS7002MCSR::GFIR1_BYP_TXTSP, LMS7002MCSR_Data::GFIR1_BYP_TXTSP }, + { LMS7002MCSR::DC_BYP_TXTSP, LMS7002MCSR_Data::DC_BYP_TXTSP }, + { LMS7002MCSR::GC_BYP_TXTSP, LMS7002MCSR_Data::GC_BYP_TXTSP }, + { LMS7002MCSR::PH_BYP_TXTSP, LMS7002MCSR_Data::PH_BYP_TXTSP }, + { LMS7002MCSR::BSIGI_TXTSP, LMS7002MCSR_Data::BSIGI_TXTSP }, + { LMS7002MCSR::BSTATE_TXTSP, LMS7002MCSR_Data::BSTATE_TXTSP }, + { LMS7002MCSR::BSIGQ_TXTSP, LMS7002MCSR_Data::BSIGQ_TXTSP }, + { LMS7002MCSR::DC_REG_TXTSP, LMS7002MCSR_Data::DC_REG_TXTSP }, + { LMS7002MCSR::DTHBIT_TX, LMS7002MCSR_Data::DTHBIT_TX }, + { LMS7002MCSR::SEL_TX, LMS7002MCSR_Data::SEL_TX }, + { LMS7002MCSR::MODE_TX, LMS7002MCSR_Data::MODE_TX }, + { LMS7002MCSR::PHO_TX, LMS7002MCSR_Data::PHO_TX }, + { LMS7002MCSR::CAPTURE, LMS7002MCSR_Data::CAPTURE }, + { LMS7002MCSR::CAPSEL, LMS7002MCSR_Data::CAPSEL }, + { LMS7002MCSR::CAPSEL_ADC, LMS7002MCSR_Data::CAPSEL_ADC }, + { LMS7002MCSR::TSGFC_RXTSP, LMS7002MCSR_Data::TSGFC_RXTSP }, + { LMS7002MCSR::TSGFCW_RXTSP, LMS7002MCSR_Data::TSGFCW_RXTSP }, + { LMS7002MCSR::TSGDCLDQ_RXTSP, LMS7002MCSR_Data::TSGDCLDQ_RXTSP }, + { LMS7002MCSR::TSGDCLDI_RXTSP, LMS7002MCSR_Data::TSGDCLDI_RXTSP }, + { LMS7002MCSR::TSGSWAPIQ_RXTSP, LMS7002MCSR_Data::TSGSWAPIQ_RXTSP }, + { LMS7002MCSR::TSGMODE_RXTSP, LMS7002MCSR_Data::TSGMODE_RXTSP }, + { LMS7002MCSR::INSEL_RXTSP, LMS7002MCSR_Data::INSEL_RXTSP }, + { LMS7002MCSR::BSTART_RXTSP, LMS7002MCSR_Data::BSTART_RXTSP }, + { LMS7002MCSR::EN_RXTSP, LMS7002MCSR_Data::EN_RXTSP }, + { LMS7002MCSR::GCORRQ_RXTSP, LMS7002MCSR_Data::GCORRQ_RXTSP }, + { LMS7002MCSR::GCORRI_RXTSP, LMS7002MCSR_Data::GCORRI_RXTSP }, + { LMS7002MCSR::HBD_OVR_RXTSP, LMS7002MCSR_Data::HBD_OVR_RXTSP }, + { LMS7002MCSR::IQCORR_RXTSP, LMS7002MCSR_Data::IQCORR_RXTSP }, + { LMS7002MCSR::HBD_DLY, LMS7002MCSR_Data::HBD_DLY }, + { LMS7002MCSR::DCCORR_AVG_RXTSP, LMS7002MCSR_Data::DCCORR_AVG_RXTSP }, + { LMS7002MCSR::GFIR1_L_RXTSP, LMS7002MCSR_Data::GFIR1_L_RXTSP }, + { LMS7002MCSR::GFIR1_N_RXTSP, LMS7002MCSR_Data::GFIR1_N_RXTSP }, + { LMS7002MCSR::GFIR2_L_RXTSP, LMS7002MCSR_Data::GFIR2_L_RXTSP }, + { LMS7002MCSR::GFIR2_N_RXTSP, LMS7002MCSR_Data::GFIR2_N_RXTSP }, + { LMS7002MCSR::GFIR3_L_RXTSP, LMS7002MCSR_Data::GFIR3_L_RXTSP }, + { LMS7002MCSR::GFIR3_N_RXTSP, LMS7002MCSR_Data::GFIR3_N_RXTSP }, + { LMS7002MCSR::AGC_K_RXTSP, LMS7002MCSR_Data::AGC_K_RXTSP }, + { LMS7002MCSR::AGC_ADESIRED_RXTSP, LMS7002MCSR_Data::AGC_ADESIRED_RXTSP }, + { LMS7002MCSR::RSSI_MODE, LMS7002MCSR_Data::RSSI_MODE }, + { LMS7002MCSR::AGC_MODE_RXTSP, LMS7002MCSR_Data::AGC_MODE_RXTSP }, + { LMS7002MCSR::AGC_AVG_RXTSP, LMS7002MCSR_Data::AGC_AVG_RXTSP }, + { LMS7002MCSR::DC_REG_RXTSP, LMS7002MCSR_Data::DC_REG_RXTSP }, + { LMS7002MCSR::CMIX_GAIN_RXTSP, LMS7002MCSR_Data::CMIX_GAIN_RXTSP }, + { LMS7002MCSR::CMIX_SC_RXTSP, LMS7002MCSR_Data::CMIX_SC_RXTSP }, + { LMS7002MCSR::CMIX_BYP_RXTSP, LMS7002MCSR_Data::CMIX_BYP_RXTSP }, + { LMS7002MCSR::AGC_BYP_RXTSP, LMS7002MCSR_Data::AGC_BYP_RXTSP }, + { LMS7002MCSR::GFIR3_BYP_RXTSP, LMS7002MCSR_Data::GFIR3_BYP_RXTSP }, + { LMS7002MCSR::GFIR2_BYP_RXTSP, LMS7002MCSR_Data::GFIR2_BYP_RXTSP }, + { LMS7002MCSR::GFIR1_BYP_RXTSP, LMS7002MCSR_Data::GFIR1_BYP_RXTSP }, + { LMS7002MCSR::DC_BYP_RXTSP, LMS7002MCSR_Data::DC_BYP_RXTSP }, + { LMS7002MCSR::GC_BYP_RXTSP, LMS7002MCSR_Data::GC_BYP_RXTSP }, + { LMS7002MCSR::PH_BYP_RXTSP, LMS7002MCSR_Data::PH_BYP_RXTSP }, + { LMS7002MCSR::CAPD, LMS7002MCSR_Data::CAPD }, + { LMS7002MCSR::DTHBIT_RX, LMS7002MCSR_Data::DTHBIT_RX }, + { LMS7002MCSR::SEL_RX, LMS7002MCSR_Data::SEL_RX }, + { LMS7002MCSR::MODE_RX, LMS7002MCSR_Data::MODE_RX }, + { LMS7002MCSR::PHO_RX, LMS7002MCSR_Data::PHO_RX }, + { LMS7002MCSR::TRX_GAIN_SRC, LMS7002MCSR_Data::TRX_GAIN_SRC }, + { LMS7002MCSR::DCMODE, LMS7002MCSR_Data::DCMODE }, + { LMS7002MCSR::PD_DCDAC_RXB, LMS7002MCSR_Data::PD_DCDAC_RXB }, + { LMS7002MCSR::PD_DCDAC_RXA, LMS7002MCSR_Data::PD_DCDAC_RXA }, + { LMS7002MCSR::PD_DCDAC_TXB, LMS7002MCSR_Data::PD_DCDAC_TXB }, + { LMS7002MCSR::PD_DCDAC_TXA, LMS7002MCSR_Data::PD_DCDAC_TXA }, + { LMS7002MCSR::PD_DCCMP_RXB, LMS7002MCSR_Data::PD_DCCMP_RXB }, + { LMS7002MCSR::PD_DCCMP_RXA, LMS7002MCSR_Data::PD_DCCMP_RXA }, + { LMS7002MCSR::PD_DCCMP_TXB, LMS7002MCSR_Data::PD_DCCMP_TXB }, + { LMS7002MCSR::PD_DCCMP_TXA, LMS7002MCSR_Data::PD_DCCMP_TXA }, + { LMS7002MCSR::DCCAL_CALSTATUS_RXBQ, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXBQ }, + { LMS7002MCSR::DCCAL_CALSTATUS_RXBI, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXBI }, + { LMS7002MCSR::DCCAL_CALSTATUS_RXAQ, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXAQ }, + { LMS7002MCSR::DCCAL_CALSTATUS_RXAI, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXAI }, + { LMS7002MCSR::DCCAL_CALSTATUS_TXBQ, LMS7002MCSR_Data::DCCAL_CALSTATUS_TXBQ }, + { LMS7002MCSR::DCCAL_CALSTATUS_TXBI, LMS7002MCSR_Data::DCCAL_CALSTATUS_TXBI }, + { LMS7002MCSR::DCCAL_CALSTATUS_TXAQ, LMS7002MCSR_Data::DCCAL_CALSTATUS_TXAQ }, + { LMS7002MCSR::DCCAL_CALSTATUS_TXAI, LMS7002MCSR_Data::DCCAL_CALSTATUS_TXAI }, + { LMS7002MCSR::DCCAL_CMPSTATUS_RXBQ, LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXBQ }, + { LMS7002MCSR::DCCAL_CMPSTATUS_RXBI, LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXBI }, + { LMS7002MCSR::DCCAL_CMPSTATUS_RXAQ, LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXAQ }, + { LMS7002MCSR::DCCAL_CMPSTATUS_RXAI, LMS7002MCSR_Data::DCCAL_CMPSTATUS_RXAI }, + { LMS7002MCSR::DCCAL_CMPSTATUS_TXBQ, LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXBQ }, + { LMS7002MCSR::DCCAL_CMPSTATUS_TXBI, LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXBI }, + { LMS7002MCSR::DCCAL_CMPSTATUS_TXAQ, LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXAQ }, + { LMS7002MCSR::DCCAL_CMPSTATUS_TXAI, LMS7002MCSR_Data::DCCAL_CMPSTATUS_TXAI }, + { LMS7002MCSR::DCCAL_CMPCFG_RXBQ, LMS7002MCSR_Data::DCCAL_CMPCFG_RXBQ }, + { LMS7002MCSR::DCCAL_CMPCFG_RXBI, LMS7002MCSR_Data::DCCAL_CMPCFG_RXBI }, + { LMS7002MCSR::DCCAL_CMPCFG_RXAQ, LMS7002MCSR_Data::DCCAL_CMPCFG_RXAQ }, + { LMS7002MCSR::DCCAL_CMPCFG_RXAI, LMS7002MCSR_Data::DCCAL_CMPCFG_RXAI }, + { LMS7002MCSR::DCCAL_CMPCFG_TXBQ, LMS7002MCSR_Data::DCCAL_CMPCFG_TXBQ }, + { LMS7002MCSR::DCCAL_CMPCFG_TXBI, LMS7002MCSR_Data::DCCAL_CMPCFG_TXBI }, + { LMS7002MCSR::DCCAL_CMPCFG_TXAQ, LMS7002MCSR_Data::DCCAL_CMPCFG_TXAQ }, + { LMS7002MCSR::DCCAL_CMPCFG_TXAI, LMS7002MCSR_Data::DCCAL_CMPCFG_TXAI }, + { LMS7002MCSR::DCCAL_START_RXBQ, LMS7002MCSR_Data::DCCAL_START_RXBQ }, + { LMS7002MCSR::DCCAL_START_RXBI, LMS7002MCSR_Data::DCCAL_START_RXBI }, + { LMS7002MCSR::DCCAL_START_RXAQ, LMS7002MCSR_Data::DCCAL_START_RXAQ }, + { LMS7002MCSR::DCCAL_START_RXAI, LMS7002MCSR_Data::DCCAL_START_RXAI }, + { LMS7002MCSR::DCCAL_START_TXBQ, LMS7002MCSR_Data::DCCAL_START_TXBQ }, + { LMS7002MCSR::DCCAL_START_TXBI, LMS7002MCSR_Data::DCCAL_START_TXBI }, + { LMS7002MCSR::DCCAL_START_TXAQ, LMS7002MCSR_Data::DCCAL_START_TXAQ }, + { LMS7002MCSR::DCCAL_START_TXAI, LMS7002MCSR_Data::DCCAL_START_TXAI }, + { LMS7002MCSR::DCWR_TXAI, LMS7002MCSR_Data::DCWR_TXAI }, + { LMS7002MCSR::DCRD_TXAI, LMS7002MCSR_Data::DCRD_TXAI }, + { LMS7002MCSR::DC_TXAI, LMS7002MCSR_Data::DC_TXAI }, + { LMS7002MCSR::DCWR_TXAQ, LMS7002MCSR_Data::DCWR_TXAQ }, + { LMS7002MCSR::DCRD_TXAQ, LMS7002MCSR_Data::DCRD_TXAQ }, + { LMS7002MCSR::DC_TXAQ, LMS7002MCSR_Data::DC_TXAQ }, + { LMS7002MCSR::DCWR_TXBI, LMS7002MCSR_Data::DCWR_TXBI }, + { LMS7002MCSR::DCRD_TXBI, LMS7002MCSR_Data::DCRD_TXBI }, + { LMS7002MCSR::DC_TXBI, LMS7002MCSR_Data::DC_TXBI }, + { LMS7002MCSR::DCWR_TXBQ, LMS7002MCSR_Data::DCWR_TXBQ }, + { LMS7002MCSR::DCRD_TXBQ, LMS7002MCSR_Data::DCRD_TXBQ }, + { LMS7002MCSR::DC_TXBQ, LMS7002MCSR_Data::DC_TXBQ }, + { LMS7002MCSR::DCWR_RXAI, LMS7002MCSR_Data::DCWR_RXAI }, + { LMS7002MCSR::DCRD_RXAI, LMS7002MCSR_Data::DCRD_RXAI }, + { LMS7002MCSR::DC_RXAI, LMS7002MCSR_Data::DC_RXAI }, + { LMS7002MCSR::DCWR_RXAQ, LMS7002MCSR_Data::DCWR_RXAQ }, + { LMS7002MCSR::DCRD_RXAQ, LMS7002MCSR_Data::DCRD_RXAQ }, + { LMS7002MCSR::DC_RXAQ, LMS7002MCSR_Data::DC_RXAQ }, + { LMS7002MCSR::DCWR_RXBI, LMS7002MCSR_Data::DCWR_RXBI }, + { LMS7002MCSR::DCRD_RXBI, LMS7002MCSR_Data::DCRD_RXBI }, + { LMS7002MCSR::DC_RXBI, LMS7002MCSR_Data::DC_RXBI }, + { LMS7002MCSR::DCWR_RXBQ, LMS7002MCSR_Data::DCWR_RXBQ }, + { LMS7002MCSR::DCRD_RXBQ, LMS7002MCSR_Data::DCRD_RXBQ }, + { LMS7002MCSR::DC_RXBQ, LMS7002MCSR_Data::DC_RXBQ }, + { LMS7002MCSR::DC_RXCDIV, LMS7002MCSR_Data::DC_RXCDIV }, + { LMS7002MCSR::DC_TXCDIV, LMS7002MCSR_Data::DC_TXCDIV }, + { LMS7002MCSR::HYSCMP_RXB, LMS7002MCSR_Data::HYSCMP_RXB }, + { LMS7002MCSR::HYSCMP_RXA, LMS7002MCSR_Data::HYSCMP_RXA }, + { LMS7002MCSR::HYSCMP_TXB, LMS7002MCSR_Data::HYSCMP_TXB }, + { LMS7002MCSR::HYSCMP_TXA, LMS7002MCSR_Data::HYSCMP_TXA }, + { LMS7002MCSR::DAC_CLKDIV, LMS7002MCSR_Data::DAC_CLKDIV }, + { LMS7002MCSR::RSSI_RSSIMODE, LMS7002MCSR_Data::RSSI_RSSIMODE }, + { LMS7002MCSR::RSSI_PD, LMS7002MCSR_Data::RSSI_PD }, + { LMS7002MCSR::RSSI_BIAS, LMS7002MCSR_Data::RSSI_BIAS }, + { LMS7002MCSR::RSSI_HYSCMP, LMS7002MCSR_Data::RSSI_HYSCMP }, + { LMS7002MCSR::RSSI_DAC_VAL, LMS7002MCSR_Data::RSSI_DAC_VAL }, + { LMS7002MCSR::RSSI_PDET2_VAL, LMS7002MCSR_Data::RSSI_PDET2_VAL }, + { LMS7002MCSR::RSSI_PDET1_VAL, LMS7002MCSR_Data::RSSI_PDET1_VAL }, + { LMS7002MCSR::RSSI_RSSI2_VAL, LMS7002MCSR_Data::RSSI_RSSI2_VAL }, + { LMS7002MCSR::RSSI_RSSI1_VAL, LMS7002MCSR_Data::RSSI_RSSI1_VAL }, + { LMS7002MCSR::RSSI_TREF_VAL, LMS7002MCSR_Data::RSSI_TREF_VAL }, + { LMS7002MCSR::RSSI_TVPTAT_VAL, LMS7002MCSR_Data::RSSI_TVPTAT_VAL }, + { LMS7002MCSR::RSSIDC_CMPSTATUS, LMS7002MCSR_Data::RSSIDC_CMPSTATUS }, + { LMS7002MCSR::RSSIDC_RSEL, LMS7002MCSR_Data::RSSIDC_RSEL }, + { LMS7002MCSR::RSSIDC_HYSCMP, LMS7002MCSR_Data::RSSIDC_HYSCMP }, + { LMS7002MCSR::RSSIDC_PD, LMS7002MCSR_Data::RSSIDC_PD }, + { LMS7002MCSR::RSSIDC_DCO2, LMS7002MCSR_Data::RSSIDC_DCO2 }, + { LMS7002MCSR::RSSIDC_DCO1, LMS7002MCSR_Data::RSSIDC_DCO1 }, + { LMS7002MCSR::LML2_TRXIQPULSE, LMS7002MCSR_Data::LML2_TRXIQPULSE }, + { LMS7002MCSR::LML2_SISODDR, LMS7002MCSR_Data::LML2_SISODDR }, + { LMS7002MCSR::LML1_TRXIQPULSE, LMS7002MCSR_Data::LML1_TRXIQPULSE }, + { LMS7002MCSR::LML1_SISODDR, LMS7002MCSR_Data::LML1_SISODDR }, + { LMS7002MCSR::MCLK2_DLY, LMS7002MCSR_Data::MCLK2_DLY }, + { LMS7002MCSR::MCLK1_DLY, LMS7002MCSR_Data::MCLK1_DLY }, + { LMS7002MCSR::MCLK2_INV, LMS7002MCSR_Data::MCLK2_INV }, + { LMS7002MCSR::MCLK1_INV, LMS7002MCSR_Data::MCLK1_INV }, + { LMS7002MCSR::CMIX_GAIN_TXTSP_R3, LMS7002MCSR_Data::CMIX_GAIN_TXTSP_R3 }, + { LMS7002MCSR::CMIX_GAIN_RXTSP_R3, LMS7002MCSR_Data::CMIX_GAIN_RXTSP_R3 }, + { LMS7002MCSR::R5_LPF_BYP_TBB, LMS7002MCSR_Data::R5_LPF_BYP_TBB }, + { LMS7002MCSR::CG_IAMP_TBB_R3, LMS7002MCSR_Data::CG_IAMP_TBB_R3 }, + { LMS7002MCSR::LOSS_LIN_TXPAD_R3, LMS7002MCSR_Data::LOSS_LIN_TXPAD_R3 }, + { LMS7002MCSR::LOSS_MAIN_TXPAD_R3, LMS7002MCSR_Data::LOSS_MAIN_TXPAD_R3 }, + { LMS7002MCSR::C_CTL_PGA_RBB_R3, LMS7002MCSR_Data::C_CTL_PGA_RBB_R3 }, + { LMS7002MCSR::G_PGA_RBB_R3, LMS7002MCSR_Data::G_PGA_RBB_R3 }, + { LMS7002MCSR::G_LNA_RFE_R3, LMS7002MCSR_Data::G_LNA_RFE_R3 }, + { LMS7002MCSR::G_TIA_RFE_R3, LMS7002MCSR_Data::G_TIA_RFE_R3 }, + { LMS7002MCSR::RZ_CTRL, LMS7002MCSR_Data::RZ_CTRL }, + { LMS7002MCSR::CMPLO_CTRL_SX, LMS7002MCSR_Data::CMPLO_CTRL_SX }, + { LMS7002MCSR::CMPLO_CTRL_CGEN_R3, LMS7002MCSR_Data::CMPLO_CTRL_CGEN_R3 }, + { LMS7002MCSR::ISINK_SPIBUFF, LMS7002MCSR_Data::ISINK_SPIBUFF }, + { LMS7002MCSR::DCMODE, LMS7002MCSR_Data::DCMODE }, + { LMS7002MCSR::PD_DCDAC_RXB, LMS7002MCSR_Data::PD_DCDAC_RXB }, + { LMS7002MCSR::PD_DCDAC_RXA, LMS7002MCSR_Data::PD_DCDAC_RXA }, + { LMS7002MCSR::PD_DCDAC_TXB, LMS7002MCSR_Data::PD_DCDAC_TXB }, + { LMS7002MCSR::PD_DCDAC_TXA, LMS7002MCSR_Data::PD_DCDAC_TXA }, + { LMS7002MCSR::PD_DCCMP_RXB, LMS7002MCSR_Data::PD_DCCMP_RXB }, + { LMS7002MCSR::PD_DCCMP_RXA, LMS7002MCSR_Data::PD_DCCMP_RXA }, + { LMS7002MCSR::PD_DCCMP_TXB, LMS7002MCSR_Data::PD_DCCMP_TXB }, + { LMS7002MCSR::PD_DCCMP_TXA, LMS7002MCSR_Data::PD_DCCMP_TXA }, + { LMS7002MCSR::DCWR_TXAI, LMS7002MCSR_Data::DCWR_TXAI }, + { LMS7002MCSR::DCRD_TXAI, LMS7002MCSR_Data::DCRD_TXAI }, + { LMS7002MCSR::DC_TXAI, LMS7002MCSR_Data::DC_TXAI }, + { LMS7002MCSR::DCWR_TXAQ, LMS7002MCSR_Data::DCWR_TXAQ }, + { LMS7002MCSR::DCRD_TXAQ, LMS7002MCSR_Data::DCRD_TXAQ }, + { LMS7002MCSR::DC_TXAQ, LMS7002MCSR_Data::DC_TXAQ }, + { LMS7002MCSR::DCWR_TXBI, LMS7002MCSR_Data::DCWR_TXBI }, + { LMS7002MCSR::DCRD_TXBI, LMS7002MCSR_Data::DCRD_TXBI }, + { LMS7002MCSR::DC_TXBI, LMS7002MCSR_Data::DC_TXBI }, + { LMS7002MCSR::DCWR_TXBQ, LMS7002MCSR_Data::DCWR_TXBQ }, + { LMS7002MCSR::DCRD_TXBQ, LMS7002MCSR_Data::DCRD_TXBQ }, + { LMS7002MCSR::DC_TXBQ, LMS7002MCSR_Data::DC_TXBQ }, + { LMS7002MCSR::DCWR_RXAI, LMS7002MCSR_Data::DCWR_RXAI }, + { LMS7002MCSR::DCRD_RXAI, LMS7002MCSR_Data::DCRD_RXAI }, + { LMS7002MCSR::DC_RXAI, LMS7002MCSR_Data::DC_RXAI }, + { LMS7002MCSR::DCWR_RXAQ, LMS7002MCSR_Data::DCWR_RXAQ }, + { LMS7002MCSR::DCRD_RXAQ, LMS7002MCSR_Data::DCRD_RXAQ }, + { LMS7002MCSR::DC_RXAQ, LMS7002MCSR_Data::DC_RXAQ }, + { LMS7002MCSR::DCWR_RXBI, LMS7002MCSR_Data::DCWR_RXBI }, + { LMS7002MCSR::DCRD_RXBI, LMS7002MCSR_Data::DCRD_RXBI }, + { LMS7002MCSR::DC_RXBI, LMS7002MCSR_Data::DC_RXBI }, + { LMS7002MCSR::DCWR_RXBQ, LMS7002MCSR_Data::DCWR_RXBQ }, + { LMS7002MCSR::DCRD_RXBQ, LMS7002MCSR_Data::DCRD_RXBQ }, + { LMS7002MCSR::DC_RXBQ, LMS7002MCSR_Data::DC_RXBQ }, + { LMS7002MCSR::DC_RXCDIV, LMS7002MCSR_Data::DC_RXCDIV }, + { LMS7002MCSR::DC_TXCDIV, LMS7002MCSR_Data::DC_TXCDIV }, + { LMS7002MCSR::HYSCMP_RXB, LMS7002MCSR_Data::HYSCMP_RXB }, + { LMS7002MCSR::HYSCMP_RXA, LMS7002MCSR_Data::HYSCMP_RXA }, + { LMS7002MCSR::HYSCMP_TXB, LMS7002MCSR_Data::HYSCMP_TXB }, + { LMS7002MCSR::HYSCMP_TXA, LMS7002MCSR_Data::HYSCMP_TXA }, + { LMS7002MCSR::DAC_CLKDIV, LMS7002MCSR_Data::DAC_CLKDIV }, + { LMS7002MCSR::RSSI_RSSIMODE, LMS7002MCSR_Data::RSSI_RSSIMODE }, + { LMS7002MCSR::RSSI_PD, LMS7002MCSR_Data::RSSI_PD }, + { LMS7002MCSR::INTADC_CMPSTATUS_TEMPREF, LMS7002MCSR_Data::INTADC_CMPSTATUS_TEMPREF }, + { LMS7002MCSR::INTADC_CMPSTATUS_TEMPVPTAT, LMS7002MCSR_Data::INTADC_CMPSTATUS_TEMPVPTAT }, + { LMS7002MCSR::INTADC_CMPSTATUS_RSSI2, LMS7002MCSR_Data::INTADC_CMPSTATUS_RSSI2 }, + { LMS7002MCSR::INTADC_CMPSTATUS_RSSI1, LMS7002MCSR_Data::INTADC_CMPSTATUS_RSSI1 }, + { LMS7002MCSR::INTADC_CMPSTATUS_PDET2, LMS7002MCSR_Data::INTADC_CMPSTATUS_PDET2 }, + { LMS7002MCSR::INTADC_CMPSTATUS_PDET1, LMS7002MCSR_Data::INTADC_CMPSTATUS_PDET1 }, + { LMS7002MCSR::RSSI_BIAS, LMS7002MCSR_Data::RSSI_BIAS }, + { LMS7002MCSR::RSSI_HYSCMP, LMS7002MCSR_Data::RSSI_HYSCMP }, + { LMS7002MCSR::INTADC_CMPCFG_TEMPREF, LMS7002MCSR_Data::INTADC_CMPCFG_TEMPREF }, + { LMS7002MCSR::INTADC_CMPCFG_TEMPVPTAT, LMS7002MCSR_Data::INTADC_CMPCFG_TEMPVPTAT }, + { LMS7002MCSR::INTADC_CMPCFG_RSSI2, LMS7002MCSR_Data::INTADC_CMPCFG_RSSI2 }, + { LMS7002MCSR::INTADC_CMPCFG_RSSI1, LMS7002MCSR_Data::INTADC_CMPCFG_RSSI1 }, + { LMS7002MCSR::INTADC_CMPCFG_PDET2, LMS7002MCSR_Data::INTADC_CMPCFG_PDET2 }, + { LMS7002MCSR::INTADC_CMPCFG_PDET1, LMS7002MCSR_Data::INTADC_CMPCFG_PDET1 }, + { LMS7002MCSR::RSSI_DAC_VAL, LMS7002MCSR_Data::RSSI_DAC_VAL }, + { LMS7002MCSR::RSSI_PDET2_VAL, LMS7002MCSR_Data::RSSI_PDET2_VAL }, + { LMS7002MCSR::RSSI_PDET1_VAL, LMS7002MCSR_Data::RSSI_PDET1_VAL }, + { LMS7002MCSR::RSSI_RSSI2_VAL, LMS7002MCSR_Data::RSSI_RSSI2_VAL }, + { LMS7002MCSR::RSSI_RSSI1_VAL, LMS7002MCSR_Data::RSSI_RSSI1_VAL }, + { LMS7002MCSR::RSSI_TREF_VAL, LMS7002MCSR_Data::RSSI_TREF_VAL }, + { LMS7002MCSR::RSSI_TVPTAT_VAL, LMS7002MCSR_Data::RSSI_TVPTAT_VAL }, + { LMS7002MCSR::RSSIDC_CMPSTATUS, LMS7002MCSR_Data::RSSIDC_CMPSTATUS }, + { LMS7002MCSR::RSSIDC_RSEL, LMS7002MCSR_Data::RSSIDC_RSEL }, + { LMS7002MCSR::RSSIDC_HYSCMP, LMS7002MCSR_Data::RSSIDC_HYSCMP }, + { LMS7002MCSR::RSSIDC_PD, LMS7002MCSR_Data::RSSIDC_PD }, + { LMS7002MCSR::RSSIDC_DCO2, LMS7002MCSR_Data::RSSIDC_DCO2 }, + { LMS7002MCSR::RSSIDC_DCO1, LMS7002MCSR_Data::RSSIDC_DCO1 }, + { LMS7002MCSR::DCLOOP_STOP, LMS7002MCSR_Data::DCLOOP_STOP }, + }; + try { - return *LMS7002MCSR_map.at(csr_enum); + return LMS7002MCSR_map.at(csr_enum); } catch (std::out_of_range& e) { return InvalidReg; From 29a69baa3674d257941f5a06f7b57cb3ca65461a Mon Sep 17 00:00:00 2001 From: Dominykas Date: Fri, 17 May 2024 10:16:34 +0300 Subject: [PATCH 2/4] Add an assertion to check if none of the enumerator values are missed --- src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp index 18982061..dffcc98a 100644 --- a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp +++ b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp @@ -1,5 +1,6 @@ #include "LMS7002MCSR_Data.h" +#include #include #include @@ -764,6 +765,8 @@ LIME_API const lime::LMS7002MCSR_Data::CSRegister& GetRegister(lime::LMS7002MCSR { LMS7002MCSR::DCLOOP_STOP, LMS7002MCSR_Data::DCLOOP_STOP }, }; + assert(LMS7002MCSR_map.size() == static_cast(LMS7002MCSR::ENUM_COUNT)); + try { return LMS7002MCSR_map.at(csr_enum); From 960938c343c3f0138716c41c2c70b646e2e0074a Mon Sep 17 00:00:00 2001 From: Dominykas Date: Fri, 17 May 2024 10:18:42 +0300 Subject: [PATCH 3/4] Correct the catch statement to catch a const & --- src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp index dffcc98a..c34b9a79 100644 --- a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp +++ b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp @@ -770,7 +770,7 @@ LIME_API const lime::LMS7002MCSR_Data::CSRegister& GetRegister(lime::LMS7002MCSR try { return LMS7002MCSR_map.at(csr_enum); - } catch (std::out_of_range& e) + } catch ([[maybe_unused]] const std::out_of_range& e) { return InvalidReg; } From 4fe243680a10f169592114605d75df53c004a50e Mon Sep 17 00:00:00 2001 From: Dominykas Date: Fri, 17 May 2024 10:53:50 +0300 Subject: [PATCH 4/4] Remove duplicated entries --- .../LMS7002MCSR_To_LMS7002MCSR_Data.cpp | 57 ------------------- 1 file changed, 57 deletions(-) diff --git a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp index c34b9a79..899d6e9c 100644 --- a/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp +++ b/src/chips/LMS7002M/LMS7002MCSR_To_LMS7002MCSR_Data.cpp @@ -582,15 +582,6 @@ LIME_API const lime::LMS7002MCSR_Data::CSRegister& GetRegister(lime::LMS7002MCSR { LMS7002MCSR::MODE_RX, LMS7002MCSR_Data::MODE_RX }, { LMS7002MCSR::PHO_RX, LMS7002MCSR_Data::PHO_RX }, { LMS7002MCSR::TRX_GAIN_SRC, LMS7002MCSR_Data::TRX_GAIN_SRC }, - { LMS7002MCSR::DCMODE, LMS7002MCSR_Data::DCMODE }, - { LMS7002MCSR::PD_DCDAC_RXB, LMS7002MCSR_Data::PD_DCDAC_RXB }, - { LMS7002MCSR::PD_DCDAC_RXA, LMS7002MCSR_Data::PD_DCDAC_RXA }, - { LMS7002MCSR::PD_DCDAC_TXB, LMS7002MCSR_Data::PD_DCDAC_TXB }, - { LMS7002MCSR::PD_DCDAC_TXA, LMS7002MCSR_Data::PD_DCDAC_TXA }, - { LMS7002MCSR::PD_DCCMP_RXB, LMS7002MCSR_Data::PD_DCCMP_RXB }, - { LMS7002MCSR::PD_DCCMP_RXA, LMS7002MCSR_Data::PD_DCCMP_RXA }, - { LMS7002MCSR::PD_DCCMP_TXB, LMS7002MCSR_Data::PD_DCCMP_TXB }, - { LMS7002MCSR::PD_DCCMP_TXA, LMS7002MCSR_Data::PD_DCCMP_TXA }, { LMS7002MCSR::DCCAL_CALSTATUS_RXBQ, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXBQ }, { LMS7002MCSR::DCCAL_CALSTATUS_RXBI, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXBI }, { LMS7002MCSR::DCCAL_CALSTATUS_RXAQ, LMS7002MCSR_Data::DCCAL_CALSTATUS_RXAQ }, @@ -623,54 +614,6 @@ LIME_API const lime::LMS7002MCSR_Data::CSRegister& GetRegister(lime::LMS7002MCSR { LMS7002MCSR::DCCAL_START_TXBI, LMS7002MCSR_Data::DCCAL_START_TXBI }, { LMS7002MCSR::DCCAL_START_TXAQ, LMS7002MCSR_Data::DCCAL_START_TXAQ }, { LMS7002MCSR::DCCAL_START_TXAI, LMS7002MCSR_Data::DCCAL_START_TXAI }, - { LMS7002MCSR::DCWR_TXAI, LMS7002MCSR_Data::DCWR_TXAI }, - { LMS7002MCSR::DCRD_TXAI, LMS7002MCSR_Data::DCRD_TXAI }, - { LMS7002MCSR::DC_TXAI, LMS7002MCSR_Data::DC_TXAI }, - { LMS7002MCSR::DCWR_TXAQ, LMS7002MCSR_Data::DCWR_TXAQ }, - { LMS7002MCSR::DCRD_TXAQ, LMS7002MCSR_Data::DCRD_TXAQ }, - { LMS7002MCSR::DC_TXAQ, LMS7002MCSR_Data::DC_TXAQ }, - { LMS7002MCSR::DCWR_TXBI, LMS7002MCSR_Data::DCWR_TXBI }, - { LMS7002MCSR::DCRD_TXBI, LMS7002MCSR_Data::DCRD_TXBI }, - { LMS7002MCSR::DC_TXBI, LMS7002MCSR_Data::DC_TXBI }, - { LMS7002MCSR::DCWR_TXBQ, LMS7002MCSR_Data::DCWR_TXBQ }, - { LMS7002MCSR::DCRD_TXBQ, LMS7002MCSR_Data::DCRD_TXBQ }, - { LMS7002MCSR::DC_TXBQ, LMS7002MCSR_Data::DC_TXBQ }, - { LMS7002MCSR::DCWR_RXAI, LMS7002MCSR_Data::DCWR_RXAI }, - { LMS7002MCSR::DCRD_RXAI, LMS7002MCSR_Data::DCRD_RXAI }, - { LMS7002MCSR::DC_RXAI, LMS7002MCSR_Data::DC_RXAI }, - { LMS7002MCSR::DCWR_RXAQ, LMS7002MCSR_Data::DCWR_RXAQ }, - { LMS7002MCSR::DCRD_RXAQ, LMS7002MCSR_Data::DCRD_RXAQ }, - { LMS7002MCSR::DC_RXAQ, LMS7002MCSR_Data::DC_RXAQ }, - { LMS7002MCSR::DCWR_RXBI, LMS7002MCSR_Data::DCWR_RXBI }, - { LMS7002MCSR::DCRD_RXBI, LMS7002MCSR_Data::DCRD_RXBI }, - { LMS7002MCSR::DC_RXBI, LMS7002MCSR_Data::DC_RXBI }, - { LMS7002MCSR::DCWR_RXBQ, LMS7002MCSR_Data::DCWR_RXBQ }, - { LMS7002MCSR::DCRD_RXBQ, LMS7002MCSR_Data::DCRD_RXBQ }, - { LMS7002MCSR::DC_RXBQ, LMS7002MCSR_Data::DC_RXBQ }, - { LMS7002MCSR::DC_RXCDIV, LMS7002MCSR_Data::DC_RXCDIV }, - { LMS7002MCSR::DC_TXCDIV, LMS7002MCSR_Data::DC_TXCDIV }, - { LMS7002MCSR::HYSCMP_RXB, LMS7002MCSR_Data::HYSCMP_RXB }, - { LMS7002MCSR::HYSCMP_RXA, LMS7002MCSR_Data::HYSCMP_RXA }, - { LMS7002MCSR::HYSCMP_TXB, LMS7002MCSR_Data::HYSCMP_TXB }, - { LMS7002MCSR::HYSCMP_TXA, LMS7002MCSR_Data::HYSCMP_TXA }, - { LMS7002MCSR::DAC_CLKDIV, LMS7002MCSR_Data::DAC_CLKDIV }, - { LMS7002MCSR::RSSI_RSSIMODE, LMS7002MCSR_Data::RSSI_RSSIMODE }, - { LMS7002MCSR::RSSI_PD, LMS7002MCSR_Data::RSSI_PD }, - { LMS7002MCSR::RSSI_BIAS, LMS7002MCSR_Data::RSSI_BIAS }, - { LMS7002MCSR::RSSI_HYSCMP, LMS7002MCSR_Data::RSSI_HYSCMP }, - { LMS7002MCSR::RSSI_DAC_VAL, LMS7002MCSR_Data::RSSI_DAC_VAL }, - { LMS7002MCSR::RSSI_PDET2_VAL, LMS7002MCSR_Data::RSSI_PDET2_VAL }, - { LMS7002MCSR::RSSI_PDET1_VAL, LMS7002MCSR_Data::RSSI_PDET1_VAL }, - { LMS7002MCSR::RSSI_RSSI2_VAL, LMS7002MCSR_Data::RSSI_RSSI2_VAL }, - { LMS7002MCSR::RSSI_RSSI1_VAL, LMS7002MCSR_Data::RSSI_RSSI1_VAL }, - { LMS7002MCSR::RSSI_TREF_VAL, LMS7002MCSR_Data::RSSI_TREF_VAL }, - { LMS7002MCSR::RSSI_TVPTAT_VAL, LMS7002MCSR_Data::RSSI_TVPTAT_VAL }, - { LMS7002MCSR::RSSIDC_CMPSTATUS, LMS7002MCSR_Data::RSSIDC_CMPSTATUS }, - { LMS7002MCSR::RSSIDC_RSEL, LMS7002MCSR_Data::RSSIDC_RSEL }, - { LMS7002MCSR::RSSIDC_HYSCMP, LMS7002MCSR_Data::RSSIDC_HYSCMP }, - { LMS7002MCSR::RSSIDC_PD, LMS7002MCSR_Data::RSSIDC_PD }, - { LMS7002MCSR::RSSIDC_DCO2, LMS7002MCSR_Data::RSSIDC_DCO2 }, - { LMS7002MCSR::RSSIDC_DCO1, LMS7002MCSR_Data::RSSIDC_DCO1 }, { LMS7002MCSR::LML2_TRXIQPULSE, LMS7002MCSR_Data::LML2_TRXIQPULSE }, { LMS7002MCSR::LML2_SISODDR, LMS7002MCSR_Data::LML2_SISODDR }, { LMS7002MCSR::LML1_TRXIQPULSE, LMS7002MCSR_Data::LML1_TRXIQPULSE },