[stm32] Disable MASRX in STM32H7 SPI

Follow-up to 678fd9a and #1223.
It seems that once the RX FIFO has been cleared and emptied, the next
transmitted byte always enters SUSP mode. It is unclear why this
happens. When MASRX is not set, neither SUSP nor OVR are seen for the
same transmit sequence.

src/modm/platform/spi/stm32h7/spi_hal_impl.hpp.in

@@ -56,8 +56,7 @@ SpiHal{{ id }}::initialize(Prescaler prescaler,
 	// initialize with unlimited transfer size
 	setTransferSize(0);
 
-	// Pause master transfer if RX FIFO is full
-	SPI{{ id }}->CR1 = SPI_CR1_MASRX;
+	SPI{{ id }}->CR1 = 0;
 
 	SPI{{ id }}->CFG2 = static_cast<uint32_t>(dataMode)
 		| static_cast<uint32_t>(dataOrder)