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YoDawg_map.map
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YoDawg_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'YoDawg'
Design Information
------------------
Command Line : map -intstyle ise -p xc7a100t-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off
-power off -o YoDawg_map.ncd YoDawg.ngd YoDawg.pcf
Target Device : xc7a100t
Target Package : csg324
Target Speed : -3
Mapper Version : artix7 -- $Revision: 1.55 $
Mapped Date : Mon May 23 20:00:10 2016
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 3 mins 7 secs
Total CPU time at the beginning of Placer: 2 mins 45 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b905ba20) REAL time: 3 mins 37 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:b905ba20) REAL time: 3 mins 38 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:b905ba20) REAL time: 3 mins 38 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:8d2749b5) REAL time: 4 mins 4 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:8d2749b5) REAL time: 4 mins 4 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:8d2749b5) REAL time: 4 mins 5 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:8d2749b5) REAL time: 4 mins 5 secs
Phase 8.8 Global Placement
........................................
.....................
...........................................
...............................
..............................
Phase 8.8 Global Placement (Checksum:c4272c88) REAL time: 7 mins 22 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:c4272c88) REAL time: 7 mins 23 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:335f940f) REAL time: 8 mins 19 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:335f940f) REAL time: 8 mins 19 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:335f940f) REAL time: 8 mins 19 secs
Total REAL time to Placer completion: 8 mins 20 secs
Total CPU time to Placer completion: 7 mins 47 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 399 out of 126,800 1%
Number used as Flip Flops: 384
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 15
Number of Slice LUTs: 1,187 out of 63,400 1%
Number used as logic: 1,177 out of 63,400 1%
Number using O6 output only: 887
Number using O5 output only: 151
Number using O5 and O6: 139
Number used as ROM: 0
Number used as Memory: 0 out of 19,000 0%
Number used exclusively as route-thrus: 10
Number with same-slice register load: 0
Number with same-slice carry load: 10
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 521 out of 15,850 3%
Number of LUT Flip Flop pairs used: 1,218
Number with an unused Flip Flop: 821 out of 1,218 67%
Number with an unused LUT: 31 out of 1,218 2%
Number of fully used LUT-FF pairs: 366 out of 1,218 30%
Number of unique control sets: 28
Number of slice register sites lost
to control set restrictions: 160 out of 126,800 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 23 out of 210 10%
Number of LOCed IOBs: 23 out of 23 100%
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 103 out of 135 76%
Number using RAMB36E1 only: 103
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 1 out of 270 1%
Number using RAMB18E1 only: 1
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Number used as BUFGs: 1
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 300 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 300 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 300 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 24 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 24 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 3 out of 240 1%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 6 0%
Number of IN_FIFOs: 0 out of 24 0%
Number of MMCME2_ADVs: 0 out of 6 0%
Number of OUT_FIFOs: 0 out of 24 0%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 0 out of 6 0%
Number of PHY_CONTROLs: 0 out of 6 0%
Number of PLLE2_ADVs: 0 out of 6 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 5.68
Peak Memory Usage: 960 MB
Total REAL time to MAP completion: 8 mins 31 secs
Total CPU time to MAP completion: 7 mins 57 secs
Mapping completed.
See MAP report file "YoDawg_map.mrp" for details.