patent.ipynb

{
 "cells": [
  {
   "cell_type": "code",
   "execution_count": 3,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "[\"normal , activ region mosfet reverse-bias respect substrat . thu , adjac devic fabric substrat electr isol without requir separ isol diffus . the bulk semiconductor region normal inact sinc current flow confin thin surfac channel directli gate . the bulk mo transistor call `` bodi '' `` back gate '' , effici oper , normal tie potenti sourc .\", 'convent approach packag downhol electron modul includ “ pot ” electron modul foam silicon substanc . while pot viabl solut surviv harsh downhol environ , subject potenti manufactur field mainten problem . for exampl , signific invest build test electron modul , becom damag beyond repair subsequ foaming/pot process . when pot cure , instanc , move wire and/or place stress variou electron compon circuit board , therebi increas failur rate circuit board .', 'transient voltag suppressor ( tv ) devic use protect integr circuit damag caus voltag impos onto integr circuit . An integr circuit design oper normal rang voltag . howev , situat electrostat discharg ( esd ) , electr fast transient lightn , unexpect uncontrol high voltag may accident strike onto circuit . the tv devic requir provid protect circumv damag like occur integr circuit voltag condit occur .', 'overvoltag protect devic semiconductor type well adapt protect stream commun circuit surg transient voltag would otherwis damag destroy stream circuit . transient voltag suppressor ( tv ) readili avail use overvoltag protect devic .', 'In design electron circuit system , computer-autom design system use defin verifi variou prototyp circuit configur . As part circuit definit , delay constraint specifi circuit design . these delay constraint satisfi prototyp circuit fabric . In convent approach circuit design , follow step typic perform : ( 1 ) load capacit cell circuit estim use fanout-bas model ; ( 2 ) size cell set optim time circuit ; ( 3 ) cell place , net ( wire ) length circuit estim ; ( 4 ) wire rout ; ( 5 ) final analysi made determin whether time closur ( i.e. , satisfact time constraint ) achiev .', 'variou techniqu use grow materi use semiconductor devic . one popular techniqu molecular beam epitaxi . gener , molecular beam epitaxi deposit process , thin film materi deposit onto substrat direct molecular atom beam deposit region substrat posit , typic substrat manipul capabl heat substrat . deposit atom molecul migrat energet prefer lattic posit heat substrat , yield film growth high crystallin qualiti puriti , optimum thick uniform . molecular beam epitaxi wide use compound semiconductor research semiconductor devic fabric industri , thin-film deposit semiconductor , oxid , metal insul layer .', 'molecular beam epitaxi ( mbe ) use grow high-qual singl crystal oxid film . In mbe process , direct thermal beam atom molecul heat effus cell react clean surfac substrat held high temperatur ultra-high vacuum condit form epitaxi film .', 'the invent concern process treatment ring multilay wafer made layer transfer compos materi chosen among semiconduct materi [ ... ] .', 'solder may use secur heat sink , solder ground plane print circuit board . In embodi , heat sink lead solder pin may extend beyond end through-hol one top bottom surfac print circuit board .', 'In waveguid photodetector , absorpt length greater 90 % absorpt absorb ingaa 3 .mu.m . with typic waveguid width 4 .mu.m 6 .mu.m wide , absorpt small area impos limit satur power photodetector . the natur answer would increas area absorb , e.g . increas length waveguid . howev , deplet photodetector associ electr capacit , also known deplet capacit . the larger junction area , greater capacit . with given load resist , increas capacit lead proportion lower devic bandwidth .', \"the wafer level packag type chip scale packag enabl integr circuit ( IC ) die attach directli print circuit board ( pcb ) face , , ic input/output ( i/o ) pad connect pcb 's pad individu solder ball .\", \"trace locat within differ layer typic connect electr layer and/or compon mount surfac substrat electr interconnect , `` via '' . A via made form hole layer substrat coat plate interior hole surfac electr conduct materi copper tungsten . via accordingli sometim refer plate hole . when via extend associ substrat one surfac , via refer `` blind '' via . via diamet less arbitrari size , e. g. , defin ipc 0.006 inch 150 micron , often refer `` microvia . ''\", 'electr via may allow electr access electron devic microelectromechan system ( mem ) encapsul Hd wafer , form devic packag . [ ... ] fig . 1 illustr typic prior art process form electr via electropl .', 'structur method fabric bump metal ( ubm ) structur metal seed layer electroless nickel deposit layer disclos involv ubm structur compris semiconductor substrat , least one final metal layer , passiv layer , metal seed layer , metal layer .', 'In convent semiconductor fabric , wafer , prior cut individu chip , test probe , also known probe card , evalu function semiconductor chip thereon normal . dure test , plural probe needl pin probe physic contact test pad wafer test measur electr properti semiconductor devic form wafer .', 'the invent relat plasma etch process , exampl fabric sub-micron featur substrat silicon like . [ ... ] plasma etch silicon substrat cryo temperatur [ ... ] known produc vertic sidewal profil . [ ... ] In accord present invent , plasma etch process compris expos substrat mask plasma work composit adapt , work temperatur , etch substrat mask form caviti passiv layer form side wall , character initi phase etch process , plasma composit modifi temperatur lower caus thicker passiv layer form entranc region caviti would otherwis form normal work temperatur composit , return temperatur composit normal work valu .', \"after microstructur defin gener manner , least variou sacrifici layer remov expos microstructur variou sacrifici layer one etchant . thi commonli call `` releas '' microstructur substrat , typic allow least degre rel movement microstructur substrat . the term `` sacrifici layer '' , therefor , mean layer portion thereof surfac micromachin microstructur use fabric microstructur , exist final configur . exemplari materi sacrifici layer describ herein includ undop silicon dioxid silicon oxid , dope silicon dioxid silicon oxid ( `` dope '' indic addit element materi ad film deposit ) .\", \"In microelectron industri packag denot compon system interconnect support semiconductor logic memori chip . the packag carri signal chip , distribut electr power chip , dissip heat , provid mechan support , protect chip circuitri physic environ damag . packag compon simpl mold plastic chip-carri box complex multichip modul found today 's high-spe comput .\", 'In method , semiconductor chip least one solder bump compris alloy tin lead melt temperatur higher solder past use .', 'the second die attach correspond first die place second termin 146 overlay plate pad contact correspond first contact use reflow process , thermal heat process , electr physic coupl second die correspond first die .', 'It well known integr circuit ( ic ) compris microelectron compon transistor , diod , resistor , capacitor , etc. , substrat , metal interconnect connect compon circuit .', 'application-specif integr circuit ( asic ) integr circuit design perform specif task . asic may found wide rang devic includ , exampl , cellular telephon , automobil , alarm clock . asic made cell perform smaller task connect togeth accomplish desir function asic . the cell includ regist cell process data memori cell store data . becaus cell cooper cell must synchron . synchron accomplish distribut clock signal cell .', 'A system interconnect set devic chip mean array microjoint dispos interconnect carrier taught .', 'the recent trend portabl wireless comput one hand commod price cell phone person comput ( pc ) hand creat need smaller integr circuit ( IC ) , IC packag , electron product low cost , capabl high perform . wafer level packag ( wlp ) , includ flip chip technolog , address need . wlp IC packag form wafer level . with wlp , IC interconnect fabric en mass wafer , complet IC modul built wafer dice . benefit gain use wlp includ , exampl , increas i/o densiti , improv oper speed , enhanc power densiti thermal manag , decreas packag size .', 'test pattern design find particular fail mechan may model particular fault type . test pattern also design activ exercis path order captur specif data integr circuit measur particular behavior perform . exampl fault type includ , stuck one stuck zero fault , bridg fault ( model defect creat unwant connect two path ) , pattern fault ( model complex behavior ) . when test pattern appli pattern input point , result pattern creat test pattern propag along path circuit element path , result pattern observ observ point .', \"To facilit better understand present invent , brief descript given follow regard basic structur event base test system method data storag event memori test system gener test vector . within context invent , term `` test vector '' mean test pattern ( ex . drive event strobe event ) test ordinari IC devic term `` scan vector '' mean test pattern test scan design IC devic .\", 'although peak surfac cnt materi remov planar , valley , void , remain planar may hinder fabric memori cell .', 'A chuck top use wafer prober inspect wafer mount wafer-mount surfac , wherein reflect least portion portion mount said wafer said wafer-mount surfac smaller reflect wafer inspect .', 'thermocompress bond techniqu wherebi devic mount substrat submount use heat pressur , therebi creat conduct bond devic submount . typic , vacuum collet use pick devic physic place contact submount form materi solder use may form alloy . onc devic contact submount , forc appli devic collet . through combin heat pressur , solder becom alloy submount devic weld place .', 'when integr circuit initi fabric form wafer . A wafer round disc thin materi , usual silicon . the size disc current rang 4 12 inch diamet . mani hundr even thousand individu devic , call die , fit onto wafer . the circuitri layer one layer time disc devic built . dure process , contact pad also built provid place power appli signal move devic .', \"system , method , technolog integr circuit ( IC ) packag critic import computer global economi . one final stage involv fabric IC devic packag IC chip . dure packag process , one IC chip mount packag substrat , connect electr contact , coat mold materi compris electr insul epoxi silicon mold compound . the result structur - commonli known `` IC packag '' - connect electr compon , exampl , print circuit board ( pcb ) use comput like .\", 'the ball grid array packag includ carrier substrat first surfac form plural conduct contact pad , may turn electr connect conduct pattern trace , via contact pad area carrier substrat .', 'Of grid array packag , simpl least costli land grid array packag . most grid array packag success implement product . howev , land grid array packag technic limit stand way wide accept technolog useabl product . the technic limit includ fact land grid array packag limit current carri capabl . current , land land grid array use either carri input/output signal carri power . simpli put , capabl individu land carri power limit due small size land grid array electr connect made land grid array . thi limit amount power input packag .', \"[ T ] addit packag bcc qfn tape-substr base lga packag . these refer gener herein `` lga '' packag , although convent lga packag usual includ area array well peripher array interconnect pad [ ... ] .\", 'In manufactur integr circuit , semiconductor die place insid packag . the packag protect die damag , provid thermal conduct path away die order dissip heat , provid electr connect circuit element . the electr connect packag call lead . In pin grid array , lead metal extens ( pin ) protrud downward undersid packag . the lead place point along rectangular matrix ( grid ) . In order integr pin grid array circuit board , packag insert mate connector rectangular matrix hole receiv lead pin grid array . the mate connector either mount circuit board form circuit board . pin grid array packag usual chosen integr circuit larg number lead .', 'typic interfac scheme integr circuit packag includ pin grid array ( pga ) , ball grid array ( bga ) , land grid array ( lga ) . pga packag use two-dimension array pin directli connect solder insert through-hol pad print circuit board ( pcb ) .', 'integr circuit ( IC ) packag , particularli area array packag ball grid array ( bga ) land grid array ( lga ) , often contain sophist electr subsystem connect mani compon die devic circuit board .', 'A through-silicon-via ( tsv ) electr connect pass complet integr circuit die one surfac die opposit surfac die .', 'A tsv typic hole extend integr circuit die subsequ fill electrically-conduct materi form electr connect .', 'In system-on-chip ( soc ) , compon soc integr singl chip .', 'systems-on-chip ( soc ) integr circuit typic incorpor multipl function core macro interconnect common system bu . the function core compris varieti third parti intellectu properti ( IP ) core , logic core , memori core , processor core , dust logic core and/or input/output system core . these soc becom increasingli larger denser increas number varieti core .', 'certain embodi invent relat integr circuit . more specif , certain embodi invent relat method system mitig risk electrostat discharg system chip ( soc ) .', \"A modern type compon technolog known surfac mount devic ( `` smd '' ) . these compon design without wire lead protrud bodi compon . instead , smd compon incorpor integr pad directli attach bodi compon . these pad serv mount smd print circuit board , thu make necessari connect .\", 'the prefer frequenc use RF power suppli 55 13.56 mhz . thi frequenc industri frequenc set asid fcc applic similar one describ herein commonli employ industri plasma gener . the frequenc , howev , RF power suppli 55 limit thereto , may classifi high frequenc frequenc greater 60 Hz .', 'the present invent solv need problem field manufactur thin die provid , prefer form , method provid substrat . A substrat bond materi deposit substrat plural die place substrat . the method accord prefer teach present invent cure substrat bond materi secur plural die substrat . the substrat plural die cover mask materi . A back grind tape appli surfac mask materi . the substrat plural die ground thin plural die . A UV transfer tape appli die film frame . the mask materi back grind tape remov . the plural die , UV transfer tape , film frame place face UV cure station . the UV transfer tape UV illumin , plural die remov UV transfer tape .', 'programm chip programm logic devic ( pld ) , complex pld ( cpld ) , programm array logic ( pal ) , programm logic array ( pla ) , field pla ( fpla ) , eras pld ( epld ) , field programm gate array ( fpga ) , provid varieti benefit includ design flexibl reconfigur .', 'An approach repres polygon integr circuit ( IC ) layout provid . [ ... ] accord anoth aspect invent , approach perform valid check polygon data provid . first , first polygon second polygon select one polygon check . then , canon direct first polygon second polygon determin . final , base upon canon direct first polygon second polygon , determin made whether space first polygon second polygon satisfi set predetermin space criteria . If space first polygon second polygon satisfi set predetermin space criteria , second polygon move respect first polygon direct opposit direct two side first polygon closest second polygon .', '[ D ] ure design flow , variou IC compon creat standard librari cell creat given wafer fabric facil , given technolog ( i.e. , devic geometri ) within wafer fabric facil use character data avail facil . In addit , number custom cell may also use creat larger custom compon block . [ ... ] the custom block may includ standard cell custom cell may non-uniform size compar standard librari cell . sinc convent place rout tool may capabl place rout custom block compos non-standard cell , particularli time area requir critic , custom design tool flow ( refer megacel flow ) creat automat compos custom block .', \"the term `` land '' use herein refer part metal pattern print circuit board compon compon lead join solder .\", 'the term pad use herein typic refer locat solder place appli , may also refer contact .', '[ ... ] wherein print circuit board land pad second thermal conduct layer thermal conduct physic attach [ ... ]', \"laser assist devic alter ( lada ) techniqu employ test debug stage chip design . It specif use isol critic perform limit node complex , defect-fre integr circuit . It also found wide use local process defect lada effect easili modul transistor characterist path process defect . the lada techniqu base abil continu wave ( CW ) laser gener local photocurr integr circuit 's backsid , thu chang pass/fail outcom test stimulu `` sensit '' transistor identifi locat fault . the laser typic short wavelength varieti order 1064 nm , photon energi silicon indirect band gap ( 1107nm ) . thi photon energi requir order initi singl photon effect use chang transistor 's behavior . due limit select wavelength laser , current spatial resolut local fault 240 nm .\", \"thi invent field laser-bas defect local analysi integr circuit ( IC ) . more specif , invent design debug and/or failur analysi ic use laser assist devic alter ( lada ) technique. [ ... ] lada ( laser- assist devic alter ) techniqu depend abil continuous-wav ( CW ) laser gener local photocurr integr circuit backsid thu chang pass/fail outcom test stimulu `` sensit '' transistor , therebi local sensit area includ design process defect . the laser use temporarili alter oper characterist transistor devic . the current spatial resolut use 1064nm continu wave laser 240nm .\", \"there two type convent soi devic : partially-deplet soi ( pd-soi ) devic , fully-deplet ( fd-soi ) devic . A convent pd-soi transistor devic one bodi thick thicker maximum width deplet layer silicon devic oper . A convent fd-soi transistor devic one bodi thick thinner maximum width deplet layer silicon devic oper . consequ , oper , pd-soi devic experi `` partial '' deplet silicon bodi , fd-soi experi `` full '' deplet thereof . the convent pd-soi fd-soi devic planar devic thu form plane wafer . [ ... ] more particularli , fully-deplet silicon-on-insul ( fd-soi ) transistor form region 120c , 12od compris thin silicon 108c , 108d , partially-deplet silicon-on-insul ( pd-soi ) transistor form region 120a , 120b compris thin silicon 108a , 108b .\", 'the present invent relat method treat semiconductor substrat especi treat silicon substrat order remov certain surfac contamin hydrogen passiv suitabl subsequ growth format materi gate oxid , epitaxi grown silicon metal silicid thereon .', 'ttl - transistor-transistor logic class digit circuit built bipolar junction transistor ( bjt ) , resistor . It call transistor-transistor logic logic gate function ( e.g . and ) amplifi function perform transistor [ ... ] .', 'ttl , i.e . transistor-transistor logic , common semiconductor technolog known art build discret digit logic integr circuit .']\n"
     ]
    }
   ],
   "source": [
    "#Data Import and Preprocessing\n",
    "\n",
    "import numpy as np\n",
    "import pandas as pd\n",
    "from nltk.corpus import stopwords\n",
    "from nltk.tokenize import word_tokenize\n",
    "from nltk.stem import PorterStemmer\n",
    "from nltk.tokenize import sent_tokenize, word_tokenize\n",
    "\n",
    "stop_words = set(stopwords.words('english'))\n",
    "\n",
    "\n",
    "ps = PorterStemmer()\n",
    "\n",
    "data = pd.read_csv(\"ELEC_IntegratedCircuits.csv\");\n",
    "t = data.iloc[:,1:2];\n",
    "ft=t.values.tolist();\n",
    "\n",
    "text=[]\n",
    "for i in ft:\n",
    "    for j in i:\n",
    "        word_tokens = word_tokenize(j)\n",
    "        filtered_sentence = [ps.stem(w) for w in word_tokens if not w in stop_words]\n",
    "        p=' '.join(word for word in filtered_sentence)\n",
    "        text.append(p);\n",
    "\n",
    "print(text);"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "['006', '006 inch', '006 inch 150', '1064', '1064 nm', '1064 nm photon', '1064nm', '1064nm continu', '1064nm continu wave', '108a', '108a 108b', '108b', '108c', '108c 108d', '108c 108d partially', '108d', '108d partially', '108d partially deplet', '1107nm', '1107nm thi', '1107nm thi photon', '12', '12 inch', '12 inch diamet', '120a', '120a 120b', '120a 120b compris', '120b', '120b compris', '120b compris thin', '120c', '120c 12od', '120c 12od compris', '12od', '12od compris', '12od compris thin', '13', '13 56', '13 56 mhz', '146', '146 overlay', '146 overlay plate', '150', '150 micron', '150 micron often', '240', '240 nm', '240nm', '55', '55 13', '55 13 56', '55 limit', '55 limit thereto', '56', '56 mhz', '56 mhz thi', '60', '60 hz', '90', '90 absorpt', '90 absorpt absorb', 'abil', 'abil continu', 'abil continu wave', 'abil continuous', 'abil continuous wav', 'absorb', 'absorb increas', 'absorb increas length', 'absorb ingaa', 'absorb ingaa mu', 'absorpt', 'absorpt absorb', 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multilay', 'trend', 'trend portabl', 'trend portabl wireless', 'tsv', 'tsv electr', 'tsv electr connect', 'tsv typic', 'tsv typic hole', 'ttl', 'ttl transistor', 'ttl transistor transistor', 'tungsten', 'tungsten via', 'tungsten via accordingli', 'turn', 'turn electr', 'turn electr connect', 'tv', 'tv devic', 'tv devic requir', 'tv devic use', 'tv readili', 'tv readili avail', 'two', 'two dimension', 'two dimension array', 'two path', 'two path pattern', 'two side', 'two side first', 'two type', 'two type convent', 'type', 'type chip', 'type chip scale', 'type compon', 'type compon technolog', 'type convent', 'type convent soi', 'type includ', 'type includ stuck', 'type test', 'type test pattern', 'type well', 'type well adapt', 'typic', 'typic allow', 'typic allow least', 'typic connect', 'typic connect electr', 'typic hole', 'typic hole extend', 'typic incorpor', 'typic incorpor multipl', 'typic interfac', 'typic interfac scheme', 'typic perform', 'typic perform load', 'typic prior', 'typic prior art', 'typic refer', 'typic refer locat', 'typic short', 'typic short wavelength', 'typic substrat', 'typic substrat manipul', 'typic vacuum', 'typic vacuum collet', 'typic waveguid', 'typic waveguid width', 'ubm', 'ubm structur', 'ubm structur compris', 'ubm structur metal', 'ultra', 'ultra high', 'ultra high vacuum', 'uncontrol', 'uncontrol high', 'uncontrol high voltag', 'undersid', 'undersid packag', 'undersid packag the', 'understand', 'understand present', 'understand present invent', 'undop', 'undop silicon', 'undop silicon dioxid', 'unexpect', 'unexpect uncontrol', 'unexpect uncontrol high', 'uniform', 'uniform molecular', 'uniform molecular beam', 'uniform size', 'uniform size compar', 'unwant', 'unwant connect', 'unwant connect two', 'upon', 'upon canon', 'upon canon direct', 'ure', 'ure design', 'ure design flow', 'use', 'use 1064nm', 'use 1064nm continu', 'use chang', 'use chang transistor', 'use character', 'use character data', 'use compound', 'use compound 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'wherein print', 'wherein print circuit', 'wherein reflect', 'wherein reflect least', 'whether', 'whether space', 'whether space first', 'whether time', 'whether time closur', 'while', 'while pot', 'while pot viabl', 'wide', 'wide absorpt', 'wide absorpt small', 'wide accept', 'wide accept technolog', 'wide rang', 'wide rang devic', 'wide use', 'wide use compound', 'wide use local', 'width', 'width deplet', 'width deplet layer', 'width mu', 'width mu mu', 'wire', 'wire and', 'wire and or', 'wire lead', 'wire lead protrud', 'wire length', 'wire length circuit', 'wire rout', 'wire rout final', 'wireless', 'wireless comput', 'wireless comput one', 'with', 'with given', 'with given load', 'with typic', 'with typic waveguid', 'with wlp', 'with wlp ic', 'within', 'within context', 'within context invent', 'within differ', 'within differ layer', 'within wafer', 'within wafer fabric', 'without', 'without requir', 'without requir separ', 'without wire', 'without wire lead', 'wlp', 'wlp ic', 'wlp ic interconnect', 'wlp ic packag', 'wlp includ', 'wlp includ exampl', 'wlp includ flip', 'work', 'work composit', 'work composit adapt', 'work temperatur', 'work temperatur composit', 'work temperatur etch', 'work valu', 'would', 'would increas', 'would increas area', 'would otherwis', 'would otherwis damag', 'would otherwis form', 'yield', 'yield film', 'yield film growth', 'zero', 'zero fault', 'zero fault bridg']\n",
      "[array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0.068606, 0.068606, 0.068606, ..., 0.      , 0.      , 0.      ]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0.        , 0.        , 0.        , ..., 0.05749983, 0.05749983,\n",
      "       0.05749983]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.]), array([0., 0., 0., ..., 0., 0., 0.])]\n"
     ]
    }
   ],
   "source": [
    "#Vectorizing\n",
    "\n",
    "from sklearn.feature_extraction.text import TfidfVectorizer\n",
    "\n",
    "# tokenize and build vocab\n",
    "vectorizer = TfidfVectorizer(ngram_range=(1,3))\n",
    "vectorizer.fit(text)\n",
    "print(vectorizer.get_feature_names())\n",
    "X=[]\n",
    "for i in text:\n",
    "    vector = vectorizer.transform([i]);\n",
    "    for j in vector.toarray():\n",
    "        X.append(j);\n",
    "print(X);"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 5,
   "metadata": {
    "scrolled": false
   },
   "outputs": [
    {
     "data": {
      "image/png": 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      "text/plain": [
       "<Figure size 2160x1440 with 1 Axes>"
      ]
     },
     "metadata": {
      "needs_background": "light"
     },
     "output_type": "display_data"
    }
   ],
   "source": [
    "#Hierarchical Clustering\n",
    "\n",
    "from scipy.cluster.hierarchy import dendrogram, linkage\n",
    "from matplotlib import pyplot as plt\n",
    "\n",
    "linked = linkage(X, 'average')\n",
    "ll = data.iloc[:,0:1];\n",
    "\n",
    "labelList = ll.values.tolist();\n",
    "plt.figure(figsize=(30, 20))  \n",
    "dendrogram(linked)\n",
    "plt.show()\n",
    "plt.close('all')"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 37,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "[2 2 0 0 2 2 1 0 2 0 0 2 2 2 0 1 2 2 0 1 0 0 2 0 0 0 0 1]\n"
     ]
    }
   ],
   "source": [
    "#KMeans Clustering\n",
    "\n",
    "from sklearn.cluster import KMeans\n",
    "\n",
    "kmeans = KMeans(n_clusters=3, random_state=1)\n",
    "kmeans.fit(X)\n",
    "labels = kmeans.labels_;\n",
    "print (labels)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": [
    "from dec import DeepEmbeddingClustering"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {
    "scrolled": true
   },
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {
    "scrolled": true
   },
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": 59,
   "metadata": {},
   "outputs": [
    {
     "name": "stderr",
     "output_type": "stream",
     "text": [
      "[nltk_data] Downloading package wordnet to /Users/lakshay/nltk_data...\n",
      "[nltk_data]   Package wordnet is already up-to-date!\n"
     ]
    }
   ],
   "source": [
    "import gensim\n",
    "from gensim.utils import simple_preprocess\n",
    "from gensim.parsing.preprocessing import STOPWORDS\n",
    "from nltk.stem import WordNetLemmatizer, SnowballStemmer\n",
    "from nltk.stem.porter import *\n",
    "from gensim import corpora, models\n",
    "import numpy as np\n",
    "np.random.seed(2018)\n",
    "import nltk\n",
    "nltk.download('wordnet')\n",
    "\n",
    "import numpy as np\n",
    "import pandas as pd\n",
    "from nltk.corpus import stopwords\n",
    "from nltk.tokenize import word_tokenize\n",
    "from nltk.stem import PorterStemmer\n",
    "from nltk.tokenize import sent_tokenize, word_tokenize\n",
    "\n",
    "stop_words = set(stopwords.words('english')) n\n",
    "\n",
    "ps = PorterStemmer()\n",
    "\n",
    "data = pd.read_csv(\"ELEC_IntegratedCircuits.csv\");\n",
    "t = data.iloc[:,1:2];\n",
    "ft=t.values.tolist();\n",
    "\n",
    "text=[]\n",
    "for i in ft:\n",
    "    for j in i:\n",
    "        word_tokens = word_tokenize(j)\n",
    "        filtered_sentence = [ps.stem(w) for w in word_tokens if not w in stop_words]\n",
    "        text.append(filtered_sentence);\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 54,
   "metadata": {
    "scrolled": true
   },
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "Dictionary(844 unique tokens: ['activ', 'adjac', 'back', 'bodi', 'bulk']...)\n"
     ]
    }
   ],
   "source": [
    "dictionary = gensim.corpora.Dictionary(text);\n",
    "\n",
    "print(dictionary)\n",
    "        \n",
    "bow_corpus = [dictionary.doc2bow(doc) for doc in text]"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 60,
   "metadata": {
    "scrolled": true
   },
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
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      " (771, 0.10225264807389528),\n",
      " (772, 0.10225264807389528),\n",
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      " (786, 0.10225264807389528),\n",
      " (787, 0.10225264807389528),\n"
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    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      " (788, 0.10225264807389528),\n",
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      " (824, 0.08243984749829963),\n",
      " (825, 0.08243984749829963)]\n",
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      " (833, 0.4453215877726649)]\n",
      "[(5, 0.13314850830057562),\n",
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      " (276, 0.18328085321393225),\n",
      " (367, 0.29071439656699305),\n",
      " (442, 0.39944552490172686),\n",
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      " (498, 0.16109693718933835),\n",
      " (605, 0.18328085321393225),\n",
      " (834, 0.22120450814436796),\n",
      " (835, 0.22120450814436796),\n",
      " (836, 0.22120450814436796),\n",
      " (837, 0.22120450814436796),\n",
      " (838, 0.22120450814436796),\n",
      " (839, 0.18328085321393225),\n",
      " (840, 0.3665617064278645),\n",
      " (841, 0.18328085321393225)]\n",
      "[(28, 0.14828490239511663),\n",
      " (45, 0.28540640880885726),\n",
      " (46, 0.06366145820315842),\n",
      " (106, 0.08507304091980257),\n",
      " (277, 0.17867303059507167),\n",
      " (342, 0.28540640880885726),\n",
      " (442, 0.41467984163045024),\n",
      " (524, 0.19180641913358815),\n",
      " (671, 0.28540640880885726),\n",
      " (839, 0.28540640880885726),\n",
      " (840, 0.28540640880885726),\n",
      " (841, 0.28540640880885726),\n",
      " (842, 0.3444614272289658),\n",
      " (843, 0.3444614272289658)]\n"
     ]
    }
   ],
   "source": [
    "from gensim import corpora, models\n",
    "tfidf = models.TfidfModel(bow_corpus)\n",
    "corpus_tfidf = tfidf[bow_corpus]\n",
    "from pprint import pprint\n",
    "for doc in corpus_tfidf:\n",
    "    pprint(doc)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 61,
   "metadata": {},
   "outputs": [],
   "source": [
    "lda_model = gensim.models.LdaMulticore(corpus_tfidf, num_topics=10, id2word=dictionary, passes=2, workers=2)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 62,
   "metadata": {
    "scrolled": false
   },
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "Topic: 0 \n",
      "Words: 0.007*\"frequenc\" + 0.006*\"submount\" + 0.006*\"voltag\" + 0.005*\"die\" + 0.005*\"surfac\" + 0.005*\"test\" + 0.005*\"solder\" + 0.005*\"sink\" + 0.005*\"event\" + 0.004*\"logic\"\n",
      "Topic: 1 \n",
      "Words: 0.007*\"beam\" + 0.007*\"programm\" + 0.006*\"array\" + 0.006*\"cell\" + 0.006*\"refer\" + 0.005*\"molecular\" + 0.005*\"epitaxi\" + 0.005*\"asic\" + 0.005*\"typic\" + 0.005*\"fill\"\n",
      "Topic: 2 \n",
      "Words: 0.006*\"substrat\" + 0.005*\"packag\" + 0.005*\"pad\" + 0.005*\"carrier\" + 0.005*\"grid\" + 0.005*\"ic\" + 0.005*\"treat\" + 0.005*\"etch\" + 0.004*\"pcb\" + 0.004*\"conduct\"\n",
      "Topic: 3 \n",
      "Words: 0.008*\"IC\" + 0.007*\"packag\" + 0.006*\"thermal\" + 0.005*\"conduct\" + 0.005*\"wlp\" + 0.005*\"array\" + 0.004*\"land\" + 0.004*\"board\" + 0.004*\"grid\" + 0.004*\"...\"\n",
      "Topic: 4 \n",
      "Words: 0.007*\"pattern\" + 0.006*\"die\" + 0.005*\"solder\" + 0.005*\"correspond\" + 0.005*\"transfer\" + 0.004*\"part\" + 0.004*\"tape\" + 0.004*\"UV\" + 0.004*\"lead\" + 0.004*\"join\"\n",
      "Topic: 5 \n",
      "Words: 0.007*\"soc\" + 0.006*\"custom\" + 0.005*\"planar\" + 0.005*\"system-on-chip\" + 0.005*\"metal\" + 0.005*\"layer\" + 0.005*\"cell\" + 0.005*\"logic\" + 0.005*\"interconnect\" + 0.004*\"taught\"\n",
      "Topic: 6 \n",
      "Words: 0.007*\"probe\" + 0.006*\"via\" + 0.005*\"disc\" + 0.005*\"wafer\" + 0.005*\"test\" + 0.005*\"land\" + 0.005*\"grid\" + 0.005*\"embodi\" + 0.005*\"certain\" + 0.004*\"pot\"\n",
      "Topic: 7 \n",
      "Words: 0.010*\"polygon\" + 0.007*\"smd\" + 0.005*\"compon\" + 0.004*\"first\" + 0.004*\"bodi\" + 0.004*\"second\" + 0.004*\"these\" + 0.003*\"mount\" + 0.003*\"space\" + 0.003*\"make\"\n",
      "Topic: 8 \n",
      "Words: 0.010*\"core\" + 0.007*\"microstructur\" + 0.005*\"sacrifici\" + 0.005*\"support\" + 0.004*\"chip\" + 0.003*\"layer\" + 0.003*\"logic\" + 0.003*\"packag\" + 0.003*\"dope\" + 0.003*\"dioxid\"\n",
      "Topic: 9 \n",
      "Words: 0.006*\"lga\" + 0.005*\"laser\" + 0.005*\"packag\" + 0.004*\"alter\" + 0.004*\"local\" + 0.003*\"tape-substr\" + 0.003*\"T\" + 0.003*\"peripher\" + 0.003*\"bcc\" + 0.003*\"qfn\"\n"
     ]
    }
   ],
   "source": [
    "for idx, topic in lda_model.print_topics():\n",
    "    print('Topic: {} \\nWords: {}'.format(idx, topic))"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {
    "scrolled": false
   },
   "outputs": [],
   "source": []
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  }
 ],
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