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[dv,cosim] Implement internal interrupts in co-sim #1732

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GregAC opened this issue Jul 28, 2022 · 4 comments · May be fixed by #1811
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[dv,cosim] Implement internal interrupts in co-sim #1732

GregAC opened this issue Jul 28, 2022 · 4 comments · May be fixed by #1811
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@ctopal
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Component:DV Design verification (DV) or testing issue Type:Enhancement Feature requests, enhancements
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@GregAC
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GregAC commented Jul 28, 2022 •
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Add support to cosim for internal interrupts (documented at https://ibex-core.readthedocs.io/en/latest/03_reference/exception_interrupts.html#internal-interrupts)

estimate 8
remaining 2022-10-06 4
remaining 2022-10-14 2
remaining 2022-11-01 1
@GregAC GregAC added this to the V2 milestone Jul 28, 2022
@GregAC GregAC added Component:DV Design verification (DV) or testing issue Type:Enhancement Feature requests, enhancements labels Jul 28, 2022
@GregAC GregAC changed the title [dv] Implement internal interrupts in co-sim [dv,cosim] Implement internal interrupts in co-sim Jul 28, 2022
@GregAC GregAC mentioned this issue Jul 28, 2022
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@ctopal ctopal mentioned this issue Sep 20, 2022
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ctopal commented Oct 14, 2022 •
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remaining 2022-10-14 2

@GregAC
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GregAC commented Oct 25, 2022

@GregAC to add write suppression on ECC failures on load to co-sim environment

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GregAC commented Nov 1, 2022

I have a set of commits on top of Canberk's work in #1811 but no PR yet. Once that is merged this will be complete.

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GregAC commented Nov 16, 2022

Completed by #1907

@GregAC GregAC closed this as completed Nov 16, 2022
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[dv] Integrity error generation in memory busses ctopal/ibex
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