Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

l3_cache_size seems incorrect for Zen CPUs #12

Open
brunocodutra opened this issue Jul 31, 2022 · 0 comments
Open

l3_cache_size seems incorrect for Zen CPUs #12

brunocodutra opened this issue Jul 31, 2022 · 0 comments

Comments

@brunocodutra
Copy link

The documentation for l3cache_size is not very clear, but I believe the value is reported in multiples of 512KB, not 1KB, as assumed by cache-size.

Specifies the L3 cache size range

(L3Size[31:18] * 512KB) <= L3 cache size < ((L3Size[31:18]+1) * 512KB).

Indeed, l3cache_size it's implemented as get_bits(self.edx, 18, 31) as u16 and should be scaled by 512KB according to the expression above.

On my Ryzen 1700 machine, l3_cache_size returns 32 * 1024, however lscpu reports that the L3 cache is 16MB (see below), which is exactly 512 times the size reported by l3_cache_size and thus consistent with my interpretation that raw-cpuid reports the L3 cache size on AMD machines in multiples of 512KB, not 1KB.

Architecture:            x86_64
  CPU op-mode(s):        32-bit, 64-bit
  Address sizes:         43 bits physical, 48 bits virtual
  Byte Order:            Little Endian
CPU(s):                  16
  On-line CPU(s) list:   0-15
Vendor ID:               AuthenticAMD
  Model name:            AMD Ryzen 7 1700 Eight-Core Processor
    CPU family:          23
    Model:               1
    Thread(s) per core:  2
    Core(s) per socket:  8
    Socket(s):           1
    Stepping:            1
    Frequency boost:     disabled
    CPU(s) scaling MHz:  53%
    CPU max MHz:         3650.0000
    CPU min MHz:         1550.0000
    BogoMIPS:            7302.68
    Flags:               fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pg
                         e mca cmov pat pse36 clflush mmx fxsr sse sse2 ht s
                         yscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constan
                         t_tsc rep_good nopl nonstop_tsc cpuid extd_apicid a
                         perfmperf rapl pni pclmulqdq monitor ssse3 fma cx16
                          sse4_1 sse4_2 movbe popcnt aes xsave avx f16c rdra
                         nd lahf_lm cmp_legacy svm extapic cr8_legacy abm ss
                         e4a misalignsse 3dnowprefetch osvw skinit wdt tce t
                         opoext perfctr_core perfctr_nb bpext perfctr_llc mw
                         aitx cpb hw_pstate ssbd ibpb vmmcall fsgsbase bmi1 
                         avx2 smep bmi2 rdseed adx smap clflushopt sha_ni xs
                         aveopt xsavec xgetbv1 xsaves clzero irperf xsaveerp
                         tr arat npt lbrv svm_lock nrip_save tsc_scale vmcb_
                         clean flushbyasid decodeassists pausefilter pfthres
                         hold avic v_vmsave_vmload vgif overflow_recov succo
                         r smca sev
Virtualization features: 
  Virtualization:        AMD-V
Caches (sum of all):     
  L1d:                   256 KiB (8 instances)
  L1i:                   512 KiB (8 instances)
  L2:                    4 MiB (8 instances)
  L3:                    16 MiB (2 instances)
NUMA:                    
  NUMA node(s):          1
  NUMA node0 CPU(s):     0-15
Vulnerabilities:         
  Itlb multihit:         Not affected
  L1tf:                  Not affected
  Mds:                   Not affected
  Meltdown:              Not affected
  Mmio stale data:       Not affected
  Retbleed:              Mitigation; untrained return thunk; SMT vulnerable
  Spec store bypass:     Mitigation; Speculative Store Bypass disabled via p
                         rctl
  Spectre v1:            Mitigation; usercopy/swapgs barriers and __user poi
                         nter sanitization
  Spectre v2:            Mitigation; Retpolines, IBPB conditional, STIBP dis
                         abled, RSB filling
  Srbds:                 Not affected
  Tsx async abort:       Not affected
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant