README.md

verilog_vivado

Contents:

• Expression Implementation
• Half Adder
• Full Adder
• Half Subtractor
• Full Subtractor
• Full Subtractor using 4 by 1 MUX
• 8 by 1 MUX
• 3-bit parallel adder
• 4-bit parallel adder/subtractor using same circuit
• Priority encoder
• Sequence Detector(overlapping and non-overlapping)

Flip Flops:

• SR Flip Flop
• D Flip Flop
• JK Flip Flop
• T Flip Flop

Registers:

• SISO(serial in serial out)
• SIPO(serial in parallel out)
• PISO(parallel in serial out, SHIFT/LOAD)
• PIPO(parallel in parallel out)

Counters:

• 3-bit up counter using JK flip flop
• Up/Down counter using JK flip flop
• Sequence counter(random sequence, synchronous)