From 280ffb2266dad69d02c7154e0dc07e852d9ea235 Mon Sep 17 00:00:00 2001
From: jnk0le <jnk0le@hotmail.com>
Date: Wed, 2 Aug 2023 20:07:48 +0200
Subject: [PATCH] estate is actually WPRI

---
 riscv-total-embedded.adoc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-total-embedded.adoc b/riscv-total-embedded.adoc
index 3c3315c..b837ef5 100644
--- a/riscv-total-embedded.adoc
+++ b/riscv-total-embedded.adoc
@@ -1,7 +1,7 @@
 
 = riscv-total-embedded
 Jan Oleksiewicz <jnk0le@hotmail.com>
-:appversion: 0.17.26
+:appversion: 0.17.27
 :toc:
 :toclevels: 5
 :sectnums:
@@ -1122,7 +1122,7 @@ NOTE: `vect_offset` can also be implemented as a read only constant pointing to
 [cols="1,2,1,2,6",options=header]
 |====
 | bit | name | type | reset value | description
-| [31:0] | `estate_nl` | WLRL | undefined | implementation specified pattern
+| [31:0] | `estate_nl` | WPRI | undefined | implementation specified pattern
 used to recover execution state upon interrupt return. Covers certain csr registers:
 (`fcsr`, `vcsr`, `vstart` etc.), and (optionally) multi cycle instruction progress. The content read as
 well as the write to this register is valid only at the lowest implemented nesting level.