diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD
index 9023c1fdbc..76c25da32f 100644
--- a/xls/modules/zstd/memory/BUILD
+++ b/xls/modules/zstd/memory/BUILD
@@ -725,3 +725,29 @@ place_and_route(
     tags = ["manual"],
     target_die_utilization_percentage = "10",
 )
+
+py_test(
+    name = "mem_writer_cocotb_test",
+    srcs = ["mem_writer_cocotb_test.py"],
+    data = [
+        ":mem_writer.v",
+        ":mem_writer_wrapper.v",
+        "@com_icarus_iverilog//:iverilog",
+        "@com_icarus_iverilog//:vvp",
+    ],
+    imports = ["."],
+    tags = ["manual"],
+    visibility = ["//xls:xls_users"],
+    deps = [
+        requirement("cocotb"),
+        requirement("cocotbext-axi"),
+        requirement("pytest"),
+        "//xls/common:runfiles",
+        "//xls/modules/zstd/cocotb:channel",
+        "//xls/modules/zstd/cocotb:utils",
+        "//xls/modules/zstd/cocotb:xlsstruct",
+        "@com_google_absl_py//absl:app",
+        "@com_google_absl_py//absl/flags",
+        "@com_google_protobuf//:protobuf_python",
+    ],
+)
diff --git a/xls/modules/zstd/memory/mem_writer_cocotb_test.py b/xls/modules/zstd/memory/mem_writer_cocotb_test.py
new file mode 100644
index 0000000000..5bbbdc92d9
--- /dev/null
+++ b/xls/modules/zstd/memory/mem_writer_cocotb_test.py
@@ -0,0 +1,571 @@
+#!/usr/bin/env python
+# Copyright 2024 The XLS Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+import random
+import logging
+from pathlib import Path
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import ClockCycles, Event
+from cocotb.binary import BinaryValue
+from cocotb_bus.scoreboard import Scoreboard
+
+from cocotbext.axi.axis import AxiStreamSource, AxiStreamBus, AxiStreamFrame
+from cocotbext.axi.axi_channels import AxiAWBus, AxiWBus, AxiBBus, AxiWriteBus, AxiAWMonitor, AxiWMonitor, AxiBMonitor
+from cocotbext.axi.axi_ram import AxiRamWrite
+from cocotbext.axi.sparse_memory import SparseMemory
+
+from xls.modules.zstd.cocotb.channel import (
+  XLSChannel,
+  XLSChannelDriver,
+  XLSChannelMonitor,
+)
+from xls.modules.zstd.cocotb.utils import reset, run_test
+from xls.modules.zstd.cocotb.xlsstruct import XLSStruct, xls_dataclass
+
+DATA_WIDTH = 32
+ADDR_WIDTH = 16
+
+@xls_dataclass
+class DataInStruct(XLSStruct):
+  data: DATA_WIDTH
+  length: ADDR_WIDTH
+  last: 1
+
+@xls_dataclass
+class WriteReqStruct(XLSStruct):
+  offset: ADDR_WIDTH
+  length: ADDR_WIDTH
+
+@xls_dataclass
+class AxiWriterRespStruct(XLSStruct):
+  status: 1
+
+@xls_dataclass
+class WriteRequestStruct(XLSStruct):
+  address: ADDR_WIDTH
+  length: ADDR_WIDTH
+
+@xls_dataclass
+class CtrlStruct(XLSStruct):
+  base: ADDR_WIDTH
+
+def set_termination_event(monitor, event, transactions):
+  def terminate_cb(_):
+    if monitor.stats.received_transactions == transactions:
+      event.set()
+  monitor.add_callback(terminate_cb)
+
+async def test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt):
+  GENERIC_CTRL_CHANNEL = "ctrl"
+  GENERIC_WRITE_REQ_CHANNEL = "req"
+  GENERIC_WRITE_RESP_CHANNEL = "resp"
+  GENERIC_DATA_IN_CHANNEL = "data_in"
+  AXI_AW_CHANNEL = "axi_aw"
+  AXI_W_CHANNEL = "axi_w"
+  AXI_B_CHANNEL = "axi_b"
+
+  terminate = Event()
+
+  dut.rst.setimmediatevalue(0)
+
+  clock = Clock(dut.clk, 10, units="us")
+  cocotb.start_soon(clock.start())
+
+  resp_bus = XLSChannel(dut, GENERIC_WRITE_RESP_CHANNEL, dut.clk, start_now=True)
+
+  driver_ctrl = XLSChannelDriver(dut, GENERIC_CTRL_CHANNEL, dut.clk)
+  driver_write_req = XLSChannelDriver(dut, GENERIC_WRITE_REQ_CHANNEL, dut.clk)
+  driver_data_in = XLSChannelDriver(dut, GENERIC_DATA_IN_CHANNEL, dut.clk)
+
+  bus_axi_aw = AxiAWBus.from_prefix(dut, AXI_AW_CHANNEL)
+  bus_axi_w = AxiWBus.from_prefix(dut, AXI_W_CHANNEL)
+  bus_axi_b = AxiBBus.from_prefix(dut, AXI_B_CHANNEL)
+  bus_axi_write = AxiWriteBus(bus_axi_aw, bus_axi_w, bus_axi_b)
+
+  monitor_ctrl = XLSChannelMonitor(dut, GENERIC_CTRL_CHANNEL, dut.clk, CtrlStruct)
+  monitor_write_req = XLSChannelMonitor(dut, GENERIC_WRITE_REQ_CHANNEL, dut.clk, WriteRequestStruct)
+  monitor_data_in = XLSChannelMonitor(dut, GENERIC_DATA_IN_CHANNEL, dut.clk, WriteRequestStruct)
+  monitor_write_resp = XLSChannelMonitor(dut, GENERIC_WRITE_RESP_CHANNEL, dut.clk, AxiWriterRespStruct)
+  monitor_axi_aw = AxiAWMonitor(bus_axi_aw, dut.clk, dut.rst)
+  monitor_axi_w = AxiWMonitor(bus_axi_w, dut.clk, dut.rst)
+  monitor_axi_b = AxiBMonitor(bus_axi_b, dut.clk, dut.rst)
+
+  set_termination_event(monitor_write_resp, terminate, resp_cnt)
+
+  memory = AxiRamWrite(bus_axi_write, dut.clk, dut.rst, size=mem_size)
+
+  log = logging.getLogger("cocotb.tb")
+  log.setLevel(logging.WARNING)
+  memory.log.setLevel(logging.WARNING)
+
+  scoreboard = Scoreboard(dut)
+  scoreboard.add_interface(monitor_write_resp, write_resp_expect)
+
+  await reset(dut.clk, dut.rst, cycles=10)
+  await cocotb.start(driver_ctrl.send(ctrl_input))
+  await cocotb.start(driver_write_req.send(write_req_input))
+  await cocotb.start(driver_data_in.send(data_in_input))
+
+  await terminate.wait()
+
+  for bundle in memory_verification:
+    memory_contents = bytearray(memory.read(bundle["base_address"], bundle["length"]))
+    expected_memory_contents = bytearray(expected_memory.read(bundle["base_address"], bundle["length"]))
+    assert memory_contents == expected_memory_contents, "{} bytes of memory contents at base address {}:\n{}\nvs\n{}\nHEXDUMP:\n{}\nvs\n{}".format(hex(bundle["length"]), hex(bundle["base_address"]), memory_contents, expected_memory_contents, memory.hexdump(bundle["base_address"], bundle["length"]), expected_memory.hexdump(bundle["base_address"], bundle["length"]))
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_single_burst_1_transfer(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_single_burst_1_transfer)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_single_burst_2_transfers(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_single_burst_2_transfers)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_single_burst_almost_max_burst_transfer(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_single_burst_almost_max_burst_transfer)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_single_burst_max_burst_transfer(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_single_burst_max_burst_transfer)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_multiburst_2_full_bursts(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_multiburst_2_full_bursts)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_multiburst_1_full_burst_and_single_transfer(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_multiburst_1_full_burst_and_single_transfer)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_multiburst_crossing_4kb_boundary(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_multiburst_crossing_4kb_boundary)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer(dut):
+  mem_size = 2**ADDR_WIDTH
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_arbitrary(mem_size, test_cases_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+@cocotb.test(timeout_time=20000, timeout_unit="ms")
+async def ram_test_random(dut):
+  mem_size = 2**ADDR_WIDTH
+  test_count = 200
+
+  (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt) = generate_test_data_random(test_count, mem_size)
+  await test_writer(dut, mem_size, ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, expected_memory, resp_cnt)
+
+def generate_test_data_random(test_count, mem_size):
+  AXI_AXSIZE_ENCODING_MAX_4B_TRANSFER = 2 # Must be in sync with AXI_AXSIZE_ENCODING enum in axi.x
+
+  ctrl_input = []
+  write_req_input = []
+  data_in_input = []
+  write_resp_expect = []
+  memory_verification = []
+  memory = SparseMemory(mem_size)
+
+  random.seed(1234)
+
+  xfer_baseaddr = random.randrange(0, (mem_size / 2))
+  ctrl = CtrlStruct(base = xfer_baseaddr)
+  ctrl_input.append(ctrl)
+
+  for i in range(test_count):
+    # Generate offset from the absolute address
+    max_xfer_offset = mem_size - xfer_baseaddr
+    xfer_offset = random.randrange(0, max_xfer_offset)
+    xfer_addr = xfer_baseaddr + xfer_offset
+    # Make sure we don't write beyond available memory
+    memory_size_max_xfer_len = mem_size - xfer_addr
+    arbitrary_max_xfer_len = 0x5000 # 20kB
+    xfer_max_len = min(arbitrary_max_xfer_len, memory_size_max_xfer_len)
+    xfer_len = random.randrange(1, xfer_max_len)
+
+    write_req = WriteReqStruct(
+      offset = xfer_offset,
+      length = xfer_len,
+    )
+    write_req_input.append(write_req)
+
+    data_to_write = random.randbytes(xfer_len)
+    rem = xfer_len % 4
+    for j in list(range(0, xfer_len-3, 4)):
+      last = ((j + 4) >= xfer_len) & (rem == 0)
+      data_in = DataInStruct(
+          data = int.from_bytes(data_to_write[j:j+4], byteorder='little'),
+          length = 4,
+          last = last
+      )
+      data_in_input.append(data_in)
+    if (rem > 0):
+      data_in = DataInStruct(
+          data = int.from_bytes(data_to_write[-rem:], byteorder='little'),
+          length = rem,
+          last = True
+      )
+      data_in_input.append(data_in)
+
+
+    transfer_req = WriteRequestStruct(
+      address = xfer_addr,
+      length = xfer_len,
+    )
+    write_expected_memory(transfer_req, data_to_write, memory)
+
+    memory_bundle = {
+            "base_address": transfer_req.address,
+            "length": transfer_req.length,
+    }
+    memory_verification.append(memory_bundle)
+
+  write_resp_expect = [AxiWriterRespStruct(status=False)] * test_count
+
+  return (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, memory, test_count)
+
+def bytes_to_4k_boundary(addr):
+    AXI_4K_BOUNDARY = 0x1000
+    return AXI_4K_BOUNDARY - (addr % AXI_4K_BOUNDARY)
+
+def write_expected_memory(transfer_req, data_to_write, memory):
+    """
+    Write test data to reference memory keeping the AXI 4kb boundary
+    by spliting the write requests into smaller ones.
+    """
+    prev_id = 0
+    address = transfer_req.address
+    length = transfer_req.length
+
+    BYTES_IN_TRANSFER = 4
+    MAX_AXI_BURST_BYTES = 256 * BYTES_IN_TRANSFER
+
+    while (length > 0):
+      bytes_to_4k = bytes_to_4k_boundary(address)
+      new_len = min(length, min(bytes_to_4k, MAX_AXI_BURST_BYTES))
+      new_data = data_to_write[prev_id:prev_id+new_len]
+      memory.write(address, new_data)
+      address = address + new_len
+      length = length - new_len
+      prev_id = prev_id + new_len
+
+def generate_test_data_arbitrary(mem_size, test_cases):
+  AXI_AXSIZE_ENCODING_MAX_4B_TRANSFER = 2 # Must be in sync with AXI_AXSIZE_ENCODING enum in axi.x
+  test_count = len(test_cases)
+
+  random.seed(1234)
+
+  ctrl_input = []
+  write_req_input = []
+  data_in_input = []
+  write_resp_expect = []
+  memory_verification = []
+  memory = SparseMemory(mem_size)
+
+  xfer_baseaddr = 0x0
+  assert xfer_baseaddr < mem_size
+
+  max_xfer_offset = mem_size - xfer_baseaddr
+
+  ctrl = CtrlStruct(base = xfer_baseaddr)
+  ctrl_input.append(ctrl)
+
+  for i in range(test_count):
+    test_case = test_cases[i]
+    xfer_offset = test_case[0]
+    assert xfer_offset <= max_xfer_offset
+    xfer_addr = xfer_baseaddr + xfer_offset
+    # Make sure we don't write beyond available memory
+    memory_size_max_xfer_len = mem_size - xfer_addr
+    arbitrary_max_xfer_len = 0x5000 # 20kB
+    xfer_max_len = min(arbitrary_max_xfer_len, memory_size_max_xfer_len)
+    xfer_len = test_case[1]
+    assert xfer_len <= xfer_max_len
+
+    write_req = WriteReqStruct(
+      offset = xfer_offset,
+      length = xfer_len,
+    )
+    write_req_input.append(write_req)
+
+    data_to_write = random.randbytes(xfer_len)
+    rem = xfer_len % 4
+    for j in list(range(0, xfer_len-3, 4)):
+      last = ((j + 4) >= xfer_len) & (rem == 0)
+      data_in = DataInStruct(
+          data = int.from_bytes(data_to_write[j:j+4], byteorder='little'),
+          length = 4,
+          last = last
+      )
+      data_in_input.append(data_in)
+    if (rem > 0):
+      data_in = DataInStruct(
+          data = int.from_bytes(data_to_write[-rem:], byteorder='little'),
+          length = rem,
+          last = True
+      )
+      data_in_input.append(data_in)
+
+
+    transfer_req = WriteRequestStruct(
+      address = xfer_addr,
+      length = xfer_len,
+    )
+    write_expected_memory(transfer_req, data_to_write, memory)
+
+    memory_bundle = {
+            "base_address": transfer_req.address,
+            "length": transfer_req.length,
+    }
+    memory_verification.append(memory_bundle)
+
+  write_resp_expect = [AxiWriterRespStruct(status=False)] * test_count
+
+  return (ctrl_input, write_req_input, data_in_input, write_resp_expect, memory_verification, memory, test_count)
+
+if __name__ == "__main__":
+    toplevel = "mem_writer_wrapper"
+    verilog_sources = [
+      "xls/modules/zstd/memory/mem_writer.v",
+      "xls/modules/zstd/memory/mem_writer_wrapper.v",
+    ]
+    test_module=[Path(__file__).stem]
+    run_test(toplevel, test_module, verilog_sources)
+
+test_cases_single_burst_1_transfer = [
+  # Aligned Address; Aligned Length
+  (0x0, 0x4),
+  # Aligned Address; Unaligned Length
+  (0x10, 0x1),
+  (0x24, 0x2),
+  (0x38, 0x3),
+  # Unaligned Address; Aligned Length
+  (0x41, 0x4),
+  (0x52, 0x4),
+  (0x63, 0x4),
+  # Unaligned Address; Unaligned Length
+  (0x71, 0x1),
+  (0x81, 0x2),
+  (0x91, 0x3),
+  (0xa2, 0x1),
+  (0xb2, 0x2),
+  (0xc2, 0x3),
+  (0xd3, 0x1),
+  (0xe3, 0x2),
+  (0xf3, 0x3)
+]
+
+test_cases_single_burst_2_transfers = [
+  # Aligned Address; Aligned Length
+  (0x100, 0x8),
+  # Aligned Address; Unaligned Length
+  (0x110, 0x5),
+  (0x120, 0x6),
+  (0x130, 0x7),
+  # Unaligned Address; Aligned Length
+  (0x141, 0x8),
+  (0x152, 0x8),
+  (0x163, 0x8),
+  # Unaligned Address; Unaligned Length
+  (0x171, 0x5),
+  (0x182, 0x5),
+  (0x193, 0x5),
+  (0x1A1, 0x6),
+  (0x1B2, 0x6),
+  (0x1C3, 0x6),
+  (0x1D1, 0x7),
+  (0x1E2, 0x7),
+  (0x1F3, 0x7)
+]
+
+test_cases_single_burst_almost_max_burst_transfer = [
+  # Aligned Address; Aligned Length
+  (0x200, 0x3FC),
+  # Aligned Address; Unaligned Length
+  (0x600, 0x3F9),
+  (0xA00, 0x3FA),
+  (0x1000, 0x3FB),
+  # Unaligned Address; Aligned Length
+  (0x1401, 0x3FC),
+  (0x1802, 0x3FC),
+  (0x2003, 0x3FC),
+  # Unaligned Address; Unaligned Length
+  (0x2401, 0x3F9),
+  (0x2802, 0x3F9),
+  (0x2C03, 0x3F9),
+  (0x3001, 0x3FA),
+  (0x3402, 0x3FA),
+  (0x3803, 0x3FA),
+  (0x3C01, 0x3FB),
+  (0x4002, 0x3FB),
+  (0x4403, 0x3FB)
+]
+
+test_cases_single_burst_max_burst_transfer = [
+  # Aligned Address; Aligned Length
+  (0x4800, 0x400),
+  # Aligned Address; Unaligned Length
+  (0x4C00, 0x3FD),
+  (0x5000, 0x3FE),
+  (0x5400, 0x3FF),
+  # Unaligned Address; Aligned Length
+  (0x5801, 0x400),
+  (0x6002, 0x400),
+  (0x6803, 0x400),
+  # Unaligned Address; Unaligned Length
+  (0x7001, 0x3FD),
+  (0x7802, 0x3FD),
+  (0x8003, 0x3FD),
+  (0x8801, 0x3FE),
+  (0x9002, 0x3FE),
+  (0x9803, 0x3FE),
+  (0xA001, 0x3FF),
+  (0xA802, 0x3FF),
+  (0xB003, 0x3FF)
+]
+
+test_cases_multiburst_2_full_bursts = [
+  # Aligned Address; Aligned Length
+  (0x0400, 0x800),
+  # Aligned Address; Unaligned Length
+  (0x1000, 0x7FD),
+  (0x1800, 0x7FE),
+  (0x2000, 0x7FF),
+  # Unaligned Address; Aligned Length
+  (0x2801, 0x800),
+  (0x3002, 0x800),
+  (0x3803, 0x800),
+  # Unaligned Address; Unaligned Length
+  (0x4001, 0x7FD),
+  (0x5002, 0x7FD),
+  (0x6003, 0x7FD),
+  (0x7001, 0x7FE),
+  (0x8002, 0x7FE),
+  (0x9003, 0x7FE),
+  (0xA001, 0x7FF),
+  (0xB002, 0x7FF),
+  (0xF003, 0x7FF)
+]
+
+test_cases_multiburst_1_full_burst_and_single_transfer = [
+  # Aligned Address; Aligned Length; Multi-Burst
+  (0x0000, 0x404),
+  # Aligned Address; Unaligned Length; Multi-Burst
+  (0x0800, 0x401),
+  (0x1000, 0x402),
+  (0x1800, 0x403),
+  # Unaligned Address; Aligned Length; Multi-Burst
+  (0x2000, 0x404),
+  (0x2800, 0x404),
+  (0x3000, 0x404),
+  # Unaligned Address; Unaligned Length; Multi-Burst
+  (0x3801, 0x401),
+  (0x5002, 0x401),
+  (0x5803, 0x401),
+  (0x6001, 0x402),
+  (0x6802, 0x402),
+  (0x7003, 0x402),
+  (0x7801, 0x403),
+  (0x8002, 0x403),
+  (0x8803, 0x403)
+]
+
+test_cases_multiburst_crossing_4kb_boundary = [
+  # Aligned Address; Aligned Length
+  (0x0FFC, 0x8),
+  # Aligned Address; Unaligned Length
+  (0x1FFC, 0x5),
+  (0x2FFC, 0x6),
+  (0x3FFC, 0x7),
+  # Unaligned Address; Aligned Length
+  (0x4FFD, 0x8),
+  (0x5FFE, 0x8),
+  (0x6FFF, 0x8),
+  # Unaligned Address; Unaligned Length
+  (0x7FFD, 0x5),
+  (0x8FFD, 0x6),
+  (0x9FFD, 0x7),
+  (0xAFFE, 0x5),
+  (0xBFFE, 0x6),
+  (0xCFFE, 0x7),
+  (0xDFFF, 0x5),
+  (0xEFFF, 0x6),
+  # End of address space - wrap around
+  (0x0FFF, 0x7),
+]
+
+test_cases_multiburst_crossing_4kb_boundary_with_perfectly_aligned_full_bursts = [
+  # Aligned Address; Aligned Length; Multi-Burst; crossing 4kB boundary with perfectly aligned full bursts
+  (0x0C00, 0x800),
+  # Unaligned Address; Unaligned Length; Multi-Burst; crossing 4kB boundary with perfectly aligned full bursts
+  (0x1C01, 0x7FF),
+  (0x2C02, 0x7FE),
+  (0x3C03, 0x7FD),
+]
+
+test_cases_multiburst_crossing_4kb_boundary_with_2_full_bursts_and_1_transfer = [
+  # Aligned Address; Aligned Length
+  (0x0C04, 0x800),
+  # Aligned Address; Unaligned Length
+  (0x1C04, 0x801),
+  (0x2C04, 0x802),
+  (0x3C04, 0x803),
+  # Unaligned Address; Aligned Length
+  (0x4C01, 0x800),
+  (0x5C02, 0x800),
+  (0x6C03, 0x800),
+  # Unaligned Address; Unaligned Length
+  (0x7C01, 0x801),
+  (0x8C02, 0x802),
+  (0x9C03, 0x803),
+  (0xAC01, 0x802),
+  (0xBC02, 0x802),
+  (0xCC03, 0x802),
+  (0xDC01, 0x803),
+  (0xEC02, 0x803),
+  # End of address space - wrap around
+  (0x0C03, 0x803),
+]
diff --git a/xls/modules/zstd/memory/mem_writer_wrapper.v b/xls/modules/zstd/memory/mem_writer_wrapper.v
new file mode 100644
index 0000000000..6064d967fa
--- /dev/null
+++ b/xls/modules/zstd/memory/mem_writer_wrapper.v
@@ -0,0 +1,191 @@
+// Copyright 2024 The XLS Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`default_nettype none
+
+module mem_writer_wrapper (
+    input wire clk,
+    input wire rst,
+
+    input wire [15:0] ctrl_data,
+    input wire ctrl_vld,
+    output wire ctrl_rdy,
+
+    input wire [31:0] req_data,
+    input wire req_vld,
+    output wire req_rdy,
+
+    input wire [48:0] data_in_data,
+    input wire data_in_vld,
+    output wire data_in_rdy,
+
+    output wire resp_data,
+    output wire resp_vld,
+    input  wire resp_rdy,
+
+    output wire [3:0] axi_aw_awid,
+    output wire [15:0] axi_aw_awaddr,
+    output wire [2:0] axi_aw_awsize,
+    output wire [7:0] axi_aw_awlen,
+    output wire [1:0] axi_aw_awburst,
+    output wire axi_aw_awvalid,
+    input wire axi_aw_awready,
+
+    output wire [31:0] axi_w_wdata,
+    output wire [3:0] axi_w_wstrb,
+    output wire [0:0] axi_w_wlast,
+    output wire axi_w_wvalid,
+    input wire axi_w_wready,
+
+    input wire [1:0] axi_b_bresp,
+    input wire [3:0] axi_b_bid,
+    input wire axi_b_bvalid,
+    output wire axi_b_bready
+);
+
+  wire [15:0] ctrl_f_base;
+
+  wire [15:0] req_f_offset;
+  wire [15:0] req_f_length;
+
+  wire [31:0] data_in_f_data;
+  wire [15:0] data_in_f_length;
+  wire [0:0] data_in_f_last;
+
+  wire [36:0] axi_w_data;
+  wire axi_w_vld;
+  wire axi_w_rdy;
+
+  wire [32:0] axi_aw_data;
+  wire axi_aw_vld;
+  wire axi_aw_rdy;
+
+  wire [6:0] axi_b_data;
+  wire axi_b_rdy;
+  wire axi_b_vld;
+
+  assign ctrl_f_base = ctrl_data;
+
+  assign {req_f_offset, req_f_length} = req_data;
+
+  assign {data_in_f_data, data_in_f_length, data_in_f_last} = data_in_data;
+
+  assign {axi_aw_awid, axi_aw_awaddr, axi_aw_awsize, axi_aw_awlen, axi_aw_awburst} = axi_aw_data;
+  assign axi_aw_awvalid = axi_aw_vld;
+  assign axi_aw_rdy = axi_aw_awready;
+
+  assign {axi_w_wdata, axi_w_wstrb, axi_w_wlast} = axi_w_data;
+  assign axi_w_wvalid = axi_w_vld;
+  assign axi_w_rdy = axi_w_wready;
+
+  assign axi_b_data = {axi_b_bresp, axi_b_bid};
+  assign axi_b_vld = axi_b_bvalid;
+  assign axi_b_bready = axi_b_rdy;
+
+  wire [15:0] axi_writer_write_req_address;
+  wire [15:0] axi_writer_write_req_length;
+  wire [ 0:0] axi_writer_write_req_valid;
+  wire [ 0:0] axi_writer_write_req_ready;
+
+  wire [15:0] padding_write_req_address;
+  wire [15:0] padding_write_req_length;
+  wire [ 0:0] padding_write_req_valid;
+  wire [ 0:0] padding_write_req_ready;
+
+  wire [31:0] axi_stream_raw_tdata;
+  wire [ 3:0] axi_stream_raw_tstr;
+  wire [ 3:0] axi_stream_raw_tkeep;
+  wire [ 0:0] axi_stream_raw_tlast;
+  wire [ 3:0] axi_stream_raw_tid;
+  wire [ 3:0] axi_stream_raw_tdest;
+  wire [ 0:0] axi_stream_raw_tvalid;
+  wire [ 0:0] axi_stream_raw_tready;
+
+  wire [31:0] axi_stream_padded_tdata;
+  wire [ 3:0] axi_stream_padded_tstr;
+  wire [ 3:0] axi_stream_padded_tkeep;
+  wire [ 0:0] axi_stream_padded_tlast;
+  wire [ 3:0] axi_stream_padded_tid;
+  wire [ 3:0] axi_stream_padded_tdest;
+  wire [ 0:0] axi_stream_padded_tvalid;
+  wire [ 0:0] axi_stream_padded_tready;
+
+  assign {axi_writer_write_req_address, axi_writer_write_req_length} = mem_writer.mem_writer__1_inst2.mem_writer__axi_writer_req_data;
+  assign axi_writer_write_req_valid = mem_writer.mem_writer__1_inst2.mem_writer__axi_writer_req_vld;
+  assign axi_writer_write_req_ready = mem_writer.mem_writer__1_inst2.mem_writer__axi_writer_req_rdy;
+
+  assign {padding_write_req_address, padding_write_req_length} = mem_writer.mem_writer__1_inst2.mem_writer__padding_req_data;
+  assign padding_write_req_valid = mem_writer.mem_writer__1_inst2.mem_writer__padding_req_vld;
+  assign padding_write_req_ready = mem_writer.mem_writer__1_inst2.mem_writer__padding_req_rdy;
+
+  assign { axi_stream_raw_tdata,
+           axi_stream_raw_tstr,
+           axi_stream_raw_tkeep,
+           axi_stream_raw_tlast,
+           axi_stream_raw_tid,
+           axi_stream_raw_tdest } = mem_writer.mem_writer__1_inst2.mem_writer__axi_st_raw_data;
+  assign axi_stream_raw_tvalid = mem_writer.mem_writer__1_inst2.mem_writer__axi_st_raw_vld;
+  assign axi_stream_raw_tready = mem_writer.mem_writer__1_inst2.mem_writer__axi_st_raw_rdy;
+
+  assign { axi_stream_padded_tdata,
+           axi_stream_padded_tstr,
+           axi_stream_padded_tkeep,
+           axi_stream_padded_tlast,
+           axi_stream_padded_tid,
+           axi_stream_padded_tdest } = mem_writer.__xls_modules_zstd_memory_axi_stream_add_empty__MemWriterInst__MemWriter_0__AxiStreamAddEmpty_0__16_32_4_2_4_4_next_inst0.mem_writer__axi_st_padded_data;
+  assign axi_stream_padded_tvalid = mem_writer.__xls_modules_zstd_memory_axi_stream_add_empty__MemWriterInst__MemWriter_0__AxiStreamAddEmpty_0__16_32_4_2_4_4_next_inst0.mem_writer__axi_st_padded_vld;
+  assign axi_stream_padded_tready = mem_writer.__xls_modules_zstd_memory_axi_stream_add_empty__MemWriterInst__MemWriter_0__AxiStreamAddEmpty_0__16_32_4_2_4_4_next_inst0.mem_writer__axi_st_padded_rdy;
+
+  wire [15:0] absolute_write_request_address;
+  assign absolute_write_request_address = ctrl_f_base + req_f_offset;
+
+  mem_writer mem_writer (
+      .clk(clk),
+      .rst(rst),
+
+      // Control
+      .mem_writer__ctrl_r_data(ctrl_data),
+      .mem_writer__ctrl_r_vld (ctrl_vld),
+      .mem_writer__ctrl_r_rdy (ctrl_rdy),
+
+      // MemWriter Write Request
+      .mem_writer__req_in_r_data(req_data),
+      .mem_writer__req_in_r_vld (req_vld),
+      .mem_writer__req_in_r_rdy (req_rdy),
+
+      // Data to write
+      .mem_writer__data_in_r_data(data_in_data),
+      .mem_writer__data_in_r_vld (data_in_vld),
+      .mem_writer__data_in_r_rdy (data_in_rdy),
+
+      // Response channel
+      .mem_writer__resp_s_data(resp_data),
+      .mem_writer__resp_s_rdy (resp_rdy),
+      .mem_writer__resp_s_vld (resp_vld),
+
+      // Memory AXI
+      .mem_writer__axi_w_s_data(axi_w_data),
+      .mem_writer__axi_w_s_vld (axi_w_vld),
+      .mem_writer__axi_w_s_rdy (axi_w_rdy),
+
+      .mem_writer__axi_aw_s_data(axi_aw_data),
+      .mem_writer__axi_aw_s_vld (axi_aw_vld),
+      .mem_writer__axi_aw_s_rdy (axi_aw_rdy),
+
+      .mem_writer__axi_b_r_data(axi_b_data),
+      .mem_writer__axi_b_r_vld (axi_b_vld),
+      .mem_writer__axi_b_r_rdy (axi_b_rdy)
+  );
+
+endmodule : mem_writer_wrapper