-
Notifications
You must be signed in to change notification settings - Fork 31
Issues: ghdl/ghdl-yosys-plugin
Feature suggestion: add a
ghdl_write_vhdl
command to yosys ...
#112
opened Apr 22, 2020 by
rlee287
Open
5
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
The project Keccak_PPL has several VHDL compilation issues (Fails to synthesize).
#190
opened Sep 17, 2023 by
alaindargelas
Another case of "wire not found for $posedge" - related to async resets?
#164
opened Jan 5, 2022 by
robinsonb5
VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names
#153
opened Aug 10, 2021 by
71GA
Mixed synthesis with a Verilog top-level fails when parameters are specified
#136
opened Oct 11, 2020 by
rodrigomelo9
"ERROR: wire not found for $posedge" when synthesizing dynamic array insertion
#130
opened Aug 22, 2020 by
Xiretza
Previous Next
ProTip!
What’s not been updated in a month: updated:<2024-10-23.