diff --git a/Platform/Qualcomm/sm6225/Apriori.fdf.inc b/Platform/Qualcomm/sm6225/Apriori.fdf.inc index fbdc7a68f..d0f3f163f 100644 --- a/Platform/Qualcomm/sm6225/Apriori.fdf.inc +++ b/Platform/Qualcomm/sm6225/Apriori.fdf.inc @@ -3,16 +3,16 @@ APRIORI DXE { # # PI DXE Drivers producing Architectural Protocols (EFI Services) # - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - INF MdeModulePkg/Core/Dxe/DxeMain.inf - # INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - # INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf @@ -26,76 +26,59 @@ APRIORI DXE { INF Platform/EFI_Binaries/Drivers/sm6225/VcsDxe/VcsDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/ClockDxe/ClockDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf - # INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.inf - FILE DRIVER = 4b4973ee-401b-4f36-a6a9-533dfccdfc33 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.efi - SECTION UI = "ScmDxeLA" - } + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UFSDxe/UFSDxe.inf - INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf - INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UFSDxe/UFSDxe.inf - - INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - - # INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf - - FILE DRIVER = cf6dfc66-14ab-4e13-84db-9c02912d1404 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.efi - SECTION UI = "TzDxeLA" - } + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/SPMIDxe/SPMIDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf - !if $(SECURE_BOOT_ENABLE) == TRUE - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf - INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf !endif - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/I2CDxe/I2CDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf INF Platform/EFI_Binaries/Drivers/sm6225/ChargerExDxe/ChargerExDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/UsbConfigDxe/UsbConfigDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ButtonsDxe/ButtonsDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf - INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf - INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf -} + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf +} \ No newline at end of file diff --git a/Platform/Qualcomm/sm6225/Apriori.fog.fdf.inc b/Platform/Qualcomm/sm6225/Apriori.fog.fdf.inc deleted file mode 100644 index 65be2ba98..000000000 --- a/Platform/Qualcomm/sm6225/Apriori.fog.fdf.inc +++ /dev/null @@ -1,108 +0,0 @@ -APRIORI DXE { - - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - INF MdeModulePkg/Core/Dxe/DxeMain.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/HWIODxe/HWIODxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ChipInfoDxe/ChipInfoDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PlatformInfoDxe/PlatformInfoDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/HALIOMMUDxe/HALIOMMUDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/GLinkDxe/GLinkDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ULogDxe/ULogDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/NpaDxe/NpaDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/VcsDxe/VcsDxe.inf - INF Platform/EFI_Binaries/Drivers/Devices/fog/ClockDxe/ClockDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf - # INF Platform/EFI_Binaries/Drivers/sm6225/ScmDxe/ScmDxe.inf - - FILE DRIVER = 4b4973ee-401b-4f36-a6a9-533dfccdfc33 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/ScmDxe/ScmDxe.efi - SECTION UI = "ScmDxe" - } - - FILE DRIVER = 6B38F7B4-AD98-40E9-9093-ACA2B5A253C4 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/fog/DiskIoDxe/DiskIoDxe.efi - SECTION UI = "DiskIoDxe" - } - - FILE DRIVER = 1FA1F39E-FEFF-4AAE-BD7B-38A070A3B609 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/fog/PartitionDxe/PartitionDxe.efi - SECTION UI = "PartitionDxe" - } - - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf - INF Platform/EFI_Binaries/Drivers/Devices/fog/UFSDxe/UFSDxe.inf - - INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf - INF FatPkg/EnhancedFatDxe/Fat.inf - - # INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxe.inf - - FILE DRIVER = cf6dfc66-14ab-4e13-84db-9c02912d1404 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.efi - SECTION UI = "TzDxe" - } - - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/SPMIDxe/SPMIDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf - - -!if $(SECURE_BOOT_ENABLE) == TRUE - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf - INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf -!endif - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf - - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ChargerExDxe/ChargerExDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbConfigDxe/UsbConfigDxe.inf - INF Platform/EFI_Binaries/Drivers/Devices/fog/ButtonsDxe/ButtonsDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf - - INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf - - INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf -} diff --git a/Platform/Qualcomm/sm6225/dxe.fdf.inc b/Platform/Qualcomm/sm6225/dxe.fdf.inc index 62530fe09..9219c25cb 100644 --- a/Platform/Qualcomm/sm6225/dxe.fdf.inc +++ b/Platform/Qualcomm/sm6225/dxe.fdf.inc @@ -1,53 +1,42 @@ - INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/HWIODxe/HWIODxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ChipInfoDxe/ChipInfoDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PlatformInfoDxe/PlatformInfoDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/HALIOMMUDxe/HALIOMMUDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/GLinkDxe/GLinkDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/ULogDxe/ULogDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/NpaDxe/NpaDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/VcsDxe/VcsDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/ClockDxe/ClockDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf - # INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.inf - - FILE DRIVER = 4b4973ee-401b-4f36-a6a9-533dfccdfc33 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.efi - SECTION UI = "ScmDxeLA" - } - - INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UFSDxe/UFSDxe.inf - - # INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf - FILE DRIVER = cf6dfc66-14ab-4e13-84db-9c02912d1404 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.efi - SECTION UI = "TzDxeLA" - } - - INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/HALIOMMUDxe/HALIOMMUDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/HWIODxe/HWIODxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/I2CDxe/I2CDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/SPMIDxe/SPMIDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UFSDxe/UFSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PlatformInfoDxe/PlatformInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf INF Platform/EFI_Binaries/Drivers/sm6225/ChargerExDxe/ChargerExDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbMsdDxe/UsbMsdDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/UsbDeviceDxe/UsbDeviceDxe.inf INF Platform/EFI_Binaries/Drivers/sm6225/UsbConfigDxe/UsbConfigDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ButtonsDxe/ButtonsDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf - - INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf \ No newline at end of file diff --git a/Platform/Qualcomm/sm6225/dxe.fog.fdf.inc b/Platform/Qualcomm/sm6225/dxe.fog.fdf.inc deleted file mode 100644 index 6d05cb6e9..000000000 --- a/Platform/Qualcomm/sm6225/dxe.fog.fdf.inc +++ /dev/null @@ -1,113 +0,0 @@ - INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/HWIODxe/HWIODxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ChipInfoDxe/ChipInfoDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PlatformInfoDxe/PlatformInfoDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/HALIOMMUDxe/HALIOMMUDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/GLinkDxe/GLinkDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ULogDxe/ULogDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/NpaDxe/NpaDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/VcsDxe/VcsDxe.inf - INF Platform/EFI_Binaries/Drivers/Devices/fog/ClockDxe/ClockDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf - # INF Platform/EFI_Binaries/Drivers/sm6225/ScmDxe/ScmDxe.inf - - FILE DRIVER = 4b4973ee-401b-4f36-a6a9-533dfccdfc33 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/ScmDxe/ScmDxe.efi - SECTION UI = "ScmDxe" - } - - INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf - INF Platform/EFI_Binaries/Drivers/Devices/fog/UFSDxe/UFSDxe.inf - - # INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf - - FILE DRIVER = cf6dfc66-14ab-4e13-84db-9c02912d1404 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.efi - SECTION UI = "TzDxe" - } - - FILE FREEFORM = A91D838E-A5FA-4138-825D-455E2303079E { - SECTION UI = "BDS_Menu.cfg" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/BDS_Menu.cfg - } - - FILE FREEFORM = 02E0AF91-5D44-424F-828F-211ADC520B0C { - SECTION UI = "Panel_truly_td4330_fhd_cmd.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_cmd.xml - } - - FILE FREEFORM = 9BAE75D9-A217-4B31-9DCD-00D2609BC6AE { - SECTION UI = "Panel_truly_td4330_fhd_vid.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_vid.xml - } - - FILE FREEFORM = C0DECCE0-BD15-480F-BD18-5FF4C530176C { - SECTION UI = "Panel_c3q_35_02_0a_fhdp_video.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_c3q_35_02_0a_fhdp_video.xml - } - - FILE FREEFORM = 8CB43165-DA92-41B6-85EB-5E15802F9A07 { - SECTION UI = "Panel_c3q_43_03_0b_fhdp_video.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_c3q_43_03_0b_fhdp_video.xml - } - - FILE FREEFORM = A1E235DE-E825-4591-9623-C43175811826 { - SECTION UI = "SecParti.cfg" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/SecParti.cfg - } - - FILE FREEFORM = 21E9BDD9-6C3F-4F10-84A5-BBEC322741F1 { - SECTION UI = "uefipil.cfg" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/uefipil.cfg - } - - FILE FREEFORM = 45FE4B7C-150C-45DA-A021-4BEB2048EC6F { - SECTION UI = "QcomChargerCfg.cfg" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/QcomChargerCfg.cfg - } - - FILE FREEFORM = F780C779-DD7C-47CD-BD1A-5EB414C51704 { - SECTION UI = "BATTERY.PROVISION" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/BATTERY.PROVISION - } - - FILE FREEFORM = F52EC379-FD2E-4229-BF74-319444BAF482 { - SECTION UI = "Panel_c3q_45_02_0c_fhdp_video.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_c3q_45_02_0c_fhdp_video.xml - } - - FILE FREEFORM = 9BAE75D9-A217-4B31-9DCD-00D2609B6784 { - SECTION UI = "Panel_truly_nt36525_hd_plus_vid.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_nt36525_hd_plus_vid.xml - } - - FILE FREEFORM = 9BAE75D9-A217-4B31-9DCD-00D2609B6785 { - SECTION UI = "Panel_nt36525_hd_plus_90hz_vid.xml" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/Panel_nt36525_hd_plus_90hz_vid.xml - } - - INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/SPMIDxe/SPMIDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf - INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf - INF Platform/EFI_Binaries/Drivers/sm6225/ChargerExDxe/ChargerExDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbMsdDxe/UsbMsdDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbDeviceDxe/UsbDeviceDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/UsbConfigDxe/UsbConfigDxe.inf - INF Platform/EFI_Binaries/Drivers/Devices/fog/ButtonsDxe/ButtonsDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf - - INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf - INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf - - INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf diff --git a/Platform/Qualcomm/sm6225/sm6225.dsc b/Platform/Qualcomm/sm6225/sm6225.dsc index cd7e4c003..e62fe128a 100644 --- a/Platform/Qualcomm/sm6225/sm6225.dsc +++ b/Platform/Qualcomm/sm6225/sm6225.dsc @@ -28,10 +28,13 @@ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x5FF8C000 # CPU Vectors gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|19200000 - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|17 - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|18 - gArmTokenSpaceGuid.PcdGicDistributorBase|0x0F200000 - gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x0F300000 + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|18 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|20 + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|30 + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26 + gArmTokenSpaceGuid.PcdGicDistributorBase|0xf200000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xf300000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xf200000 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00006225 gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x5FF90000 # UEFI Stack @@ -42,8 +45,6 @@ gQcomTokenSpaceGuid.PcdUefiMemPoolSize|0x0E000000 # UefiMemorySize, DXE heap size gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x5C000000 - gQcomTokenSpaceGuid.PcdDebugUartPortBase|0xa90000 - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 gArmPlatformTokenSpaceGuid.PcdClusterCount|2 @@ -53,9 +54,7 @@ gSimpleInitTokenSpaceGuid.PcdDeviceTreeStore|0x53F00000 gSimpleInitTokenSpaceGuid.PcdLoggerdUseConsole|FALSE - [LibraryClasses.common] - # Ported from SurfaceDuoPkg AslUpdateLib|Silicon/Qualcomm/QcomPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf @@ -63,4 +62,6 @@ PlatformPeiLib|Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.inf PlatformPrePiLib|Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformPrePiLib.inf MsPlatformDevicesLib|Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf - SOCSmbiosInfoLib|Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf \ No newline at end of file + SOCSmbiosInfoLib|Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf + +[Components.common] diff --git a/Platform/Qualcomm/sm6225/sm6225.fdf b/Platform/Qualcomm/sm6225/sm6225.fdf index 2b50067cb..7a3413144 100644 --- a/Platform/Qualcomm/sm6225/sm6225.fdf +++ b/Platform/Qualcomm/sm6225/sm6225.fdf @@ -131,6 +131,9 @@ READ_LOCK_STATUS = TRUE # BSP drivers !include Platform/Qualcomm/sm6225/dxe.fdf.inc + # INF Silicon/Qualcomm/sdm845/Drivers/sdm845Dxe/sdm845Dxe.inf // not sdm845 + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + # # Helper drivers # @@ -139,14 +142,14 @@ READ_LOCK_STATUS = TRUE # # USB Host Support # - # INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - # INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf # # FAT filesystem + GPT/MBR partitioning # - # INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf INF FatPkg/EnhancedFatDxe/Fat.inf INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf @@ -219,8 +222,8 @@ READ_LOCK_STATUS = TRUE } INF Platform/RenegadePkg/Application/Reboot2PayloadApp/Reboot2PayloadApp.inf - !endif + # Device specific fdf !include $(DEVICE_DXE_FV_COMPONENTS) @@ -250,6 +253,11 @@ READ_LOCK_STATUS = TRUE } } + FILE FREEFORM = DDE58710-41CD-4306-DBFB-3FA90BB1D2DD { + SECTION UI = "uefiplat.cfg" + SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/uefiplat.cfg + } + !include Silicon/Qualcomm/QcomPkg/QcomCommonFdf.inc diff --git a/Platform/Qualcomm/sm6225/sm6225.fog.dsc b/Platform/Qualcomm/sm6225/sm6225.fog.dsc deleted file mode 100644 index e95a3cf7b..000000000 --- a/Platform/Qualcomm/sm6225/sm6225.fog.dsc +++ /dev/null @@ -1,71 +0,0 @@ -## @file -# -# Copyright (c) 2011-2015, ARM Limited. All rights reserved. -# Copyright (c) 2014, Linaro Limited. All rights reserved. -# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. -# Copyright (c) 2018 - 2019, Bingxing Wang. All rights reserved. -# Copyright (c) 2022, Xilin Wu. All rights reserved. -# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -################################################################################ -# -# Defines Section - statements that will be processed to create a Makefile. -# -################################################################################ - -[Defines] - SOC_PLATFORM = sm6225 - USE_PHYSICAL_TIMER = TRUE - -!include Silicon/Qualcomm/QcomPkg/QcomCommonDsc.inc - -[PcdsFixedAtBuild.common] - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000 # Starting address - gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 - - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x5FF8C000 # CPU Vectors - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|19200000 - gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|1 - gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|2 - gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|3 - gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|0 - gArmTokenSpaceGuid.PcdGicDistributorBase|0xf200000 - gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xf300000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xf200000 - - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00006225 - gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x5FF90000 # UEFI Stack - gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x00040000 # 256K stack - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 - - gQcomTokenSpaceGuid.PcdUefiMemPoolBase|0x63900000 # DXE Heap base address - gQcomTokenSpaceGuid.PcdUefiMemPoolSize|0x0E000000 # UefiMemorySize, DXE heap size - gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x5C000000 - - gQcomTokenSpaceGuid.PcdDebugUartPortBase|0xa90000 - - gArmPlatformTokenSpaceGuid.PcdCoreCount|8 - gArmPlatformTokenSpaceGuid.PcdClusterCount|2 - - # - # SimpleInit - # - gSimpleInitTokenSpaceGuid.PcdDeviceTreeStore|0x53F00000 - gSimpleInitTokenSpaceGuid.PcdLoggerdUseConsole|FALSE - - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000048 - -[LibraryClasses.common] - - # Ported from SurfaceDuoPkg - AslUpdateLib|Silicon/Qualcomm/QcomPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf - SerialPortLib|Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.inf - #SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf - PlatformMemoryMapLib|Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf - PlatformPeiLib|Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.inf - PlatformPrePiLib|Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformPrePiLib.inf - MsPlatformDevicesLib|Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf - SOCSmbiosInfoLib|Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf diff --git a/Platform/Qualcomm/sm6225/sm6225.fog.fdf b/Platform/Qualcomm/sm6225/sm6225.fog.fdf deleted file mode 100644 index 3639c97f8..000000000 --- a/Platform/Qualcomm/sm6225/sm6225.fog.fdf +++ /dev/null @@ -1,269 +0,0 @@ -# -# Copyright (c) 2018, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# - -################################################################################ -# -# FD Section -# The [FD] Section is made up of the definition statements and a -# description of what goes into the Flash Device Image. Each FD section -# defines one flash "device" image. A flash device image may be one of -# the following: Removable media bootable image (like a boot floppy -# image,) an Option ROM image (that would be "flashed" into an add-in -# card,) a System "Flash" image (that would be burned into a system's -# flash) or an Update ("Capsule") image that will be used to update and -# existing system flash. -# -################################################################################ - -[FD.sm6225_UEFI] -BaseAddress = $(FD_BASE)|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware -Size = $(FD_SIZE)|gArmTokenSpaceGuid.PcdFdSize -ErasePolarity = 1 - -# This one is tricky, it must be: BlockSize * NumBlocks = Size -BlockSize = 0x00001000 -NumBlocks = 0x700 - -################################################################################ -# -# Following are lists of FD Region layout which correspond to the locations of different -# images within the flash device. -# -# Regions must be defined in ascending order and may not overlap. -# -# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by -# the pipe "|" character, followed by the size of the region, also in hex with the leading -# "0x" characters. Like: -# Offset|Size -# PcdOffsetCName|PcdSizeCName -# RegionType -# -################################################################################ - -0x00000000|0x00700000 -gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize -FV = FVMAIN_COMPACT - - -################################################################################ -# -# FV Section -# -# [FV] section is used to define what components or modules are placed within a flash -# device file. This section also defines order the components and modules are positioned -# within the image. The [FV] section consists of define statements, set statements and -# module statements. -# -################################################################################ - -[FV.FvMain] -BlockSize = 0x40 -NumBlocks = 0 # This FV gets compressed so make it just big enough -FvAlignment = 8 # FV alignment and FV attributes setting. -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - -# Apriori -!include Platform/Qualcomm/sm6225/Apriori.fog.fdf.inc - - INF MdeModulePkg/Core/Dxe/DxeMain.inf - - # - # PI DXE Drivers producing Architectural Protocols (EFI Services) - # - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf - INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - -!if $(SECURE_BOOT_ENABLE) == TRUE -!include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc - INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf - INF SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf - INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf -!endif - - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf - INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf - INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf - - INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf - - # - # Multiple Console IO support - # - INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf - INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf - INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf - INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf - INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - - INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - - INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf - -# BSP drivers -!include Platform/Qualcomm/sm6225/dxe.fog.fdf.inc - - # - # Helper drivers - # - INF Platform/RenegadePkg/Drivers/SetCPUFreqDxe/SetCPUFreqDxe.inf - - # - # USB Host Support - # - # INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf - INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf - # INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf - - # - # FAT filesystem + GPT/MBR partitioning - # - - FILE DRIVER = 6B38F7B4-AD98-40E9-9093-ACA2B5A253C4 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/fog/DiskIoDxe/DiskIoDxe.efi - SECTION UI = "DiskIoDxe" - } - - FILE DRIVER = 1FA1F39E-FEFF-4AAE-BD7B-38A070A3B609 { - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/fog/PartitionDxe/PartitionDxe.efi - SECTION UI = "PartitionDxe" - } - - INF FatPkg/EnhancedFatDxe/Fat.inf - INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf - INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf - - INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf - - # - # ACPI Support - # - INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf - INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf - INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf - - # - # FDT support - # - INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf - - # - # SMBIOS Support - # - INF Platform/RenegadePkg/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf - INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf - - # - # UEFI applications - # - INF ShellPkg/Application/Shell/Shell.inf -!ifdef $(INCLUDE_TFTP_COMMAND) - INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf -!endif #$(INCLUDE_TFTP_COMMAND) - - INF Platform/EFI_Binaries/Applications/LinuxSimpleMassStorage/LinuxSimpleMassStorage.inf - - # - # Bds - # - INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf - INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf - INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf - INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf - INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf - INF MdeModulePkg/Application/UiApp/UiApp.inf - INF Platform/RenegadePkg/Drivers/LogoDxe/LogoDxe.inf - - # - # Windows kernel patcher - # - INF Platform/RenegadePkg/Drivers/KernelErrataPatcher/KernelErrataPatcher.inf - - # - # Simple Init GUI - # - INF src/main/SimpleInitMain.inf - - INF src/kernelfdt/KernelFdtDxe.inf - -!if $(AB_SLOTS_SUPPORT) == TRUE - INF GPLDrivers/Drivers/BootSlotDxe/BootSlotDxe.inf - INF GPLDrivers/Application/SwitchSlotsApp/SwitchSlotsApp.inf -!endif - -!if $(ENABLE_LINUX_UTILS) == 1 - FILE FREEFORM = 4b0364cf-1c5b-47aa-9073-d7b5039ce49b { - SECTION RAW = tools/simpleinit.static.uefi.cfg - SECTION UI = "simpleinit.static.uefi.cfg" - } - - INF Platform/RenegadePkg/Application/Reboot2PayloadApp/Reboot2PayloadApp.inf - -!endif -# Device specific fdf -!include $(DEVICE_DXE_FV_COMPONENTS) - -[FV.FVMAIN_COMPACT] -FvAlignment = 8 -ERASE_POLARITY = 1 -MEMORY_MAPPED = TRUE -STICKY_WRITE = TRUE -LOCK_CAP = TRUE -LOCK_STATUS = TRUE -WRITE_DISABLED_CAP = TRUE -WRITE_ENABLED_CAP = TRUE -WRITE_STATUS = TRUE -WRITE_LOCK_CAP = TRUE -WRITE_LOCK_STATUS = TRUE -READ_DISABLED_CAP = TRUE -READ_ENABLED_CAP = TRUE -READ_STATUS = TRUE -READ_LOCK_CAP = TRUE -READ_LOCK_STATUS = TRUE - - INF Silicon/Qualcomm/QcomPkg/PrePi/PrePi.inf - - FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { - SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { - SECTION FV_IMAGE = FVMAIN - } - } - - FILE FREEFORM = DDE58710-41CD-4306-DBFB-3FA90BB1D2DD { - SECTION UI = "uefiplat.cfg" - SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/uefiplat.cfg - } - -!include Silicon/Qualcomm/QcomPkg/QcomCommonFdf.inc - - diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml new file mode 100644 index 000000000..55d210163 Binary files /dev/null and b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml differ diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.dsl new file mode 100644 index 000000000..35857ed9d --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.dsl @@ -0,0 +1,99 @@ +DefinitionBlock ("", "DSDT", 2, "QCOMM ", "SM6225 ", 0x00000003) +{ + Scope (_SB) + { + Name (PSUB, "MTP06225") + Name (SOID, 0xFFFFFFFF) + Name (STOR, 0xABCABCAB) + Name (SIDS, "899800000000000") + Name (SIDV, 0xFFFFFFFF) + Name (SVMJ, 0xFFFF) + Name (SVMI, 0xFFFF) + Name (SDFE, 0xFFFF) + Name (SFES, "899800000000000") + Name (SIDM, 0x0000000FFFFFFFFF) + Name (SUFS, 0xFFFFFFFF) + Name (PUS3, 0xFFFFFFFF) + Name (SUS3, 0xFFFFFFFF) + Name (SIDT, 0xFFFFFFFF) + Name (SOSN, 0xAAAAAAAABBBBBBBB) + Name (PLST, 0xFFFFFFFF) + Name (EMUL, 0xFFFFFFFF) + Name (SJTG, 0xFFFFFFFF) + Name (RMTB, 0xAAAAAAAA) + Name (RMTX, 0xBBBBBBBB) + Name (RFMB, 0xCCCCCCCC) + Name (RFMS, 0xDDDDDDDD) + Name (RFAB, 0xEEEEEEEE) + Name (RFAS, 0x77777777) + Name (TCMA, 0xDEADBEEF) + Name (TCML, 0xBEEFDEAD) + Name (SOSI, 0xDEADBEEFFFFFFFFF) + Name (PRP0, 0xFFFFFFFF) + Name (PRP1, 0xFFFFFFFF) + Name (PRP2, 0xFFFFFFFF) + Name (PRP3, 0xFFFFFFFF) + Name (PRP4, 0xFFFFFFFF) + Name (PRP5, 0xFFFFFFFF) + Name (PRP6, 0xFFFFFFFF) + + Device (UFS0) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_HID, "QCOM24A5") // _HID: Hardware ID + Alias (^EMUL, EMUL) + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x04804000, // Address Base + 0x00014000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000184, + } + }) + Return (RBUF) /* \_SB_.UFS0._CRS.RBUF */ + } + + Device (DEV0) + { + Method (_ADR, 0, NotSerialized) // _ADR: Address + { + Return (0x08) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + } + } + + Include("abd.dsl") + + Include("pmic_core.dsl") + + Include("scm.dsl"); + + Include("spmi.dsl"); + + Include("qcgpio.dsl"); + + Include("btns.dsl"); + + Include("pep_lpi.dsl"); + + Include("usb.dsl"); + + } +} + diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/abd.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/abd.dsl new file mode 100644 index 000000000..e8762357b --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/abd.dsl @@ -0,0 +1,20 @@ +Device (ABD) +{ + Name (_HID, "QCOM0527") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (ROP1, GenericSerialBus, Zero, 0x0100) + Name (AVBL, Zero) + Alias (PSUB, _SUB) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If ((Arg0 == 0x09)) + { + AVBL = Arg1 + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xF) + } +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/btns.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/btns.dsl new file mode 100644 index 000000000..6f1295bbe --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/btns.dsl @@ -0,0 +1,74 @@ +Device (BTNS) +{ + Name (_HID, "ACPI0011" /* Generic Buttons Device */) // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullDown, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0000 + } + GpioInt (Edge, ActiveBoth, Exclusive, PullUp, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0085 + } + GpioInt (Edge, ActiveBoth, Exclusive, PullDown, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0001 + } + }) + Return (RBUF) /* \_SB_.BTNS._CRS.RBUF */ + } + + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("fa6bd625-9ce8-470d-a2c7-b3ca36c4282e") /* Generic Buttons Device */, + Package (0x04) + { + Package (0x05) // Portable Device Control + { + Zero, + One, + Zero, + One, + 0x0D + }, + + Package (0x05) // Power + { + One, + Zero, + One, + One, + 0x81 + }, + + Package (0x05) // Vol Up + { + One, + One, + One, + 0x0C, + 0xE9 + }, + + Package (0x05) // Vol Down + { + One, + 0x02, + One, + 0x0C, + 0xEA + } + } + }) +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/gpio.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/gpio.dsl new file mode 100644 index 000000000..533a449b3 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/gpio.dsl @@ -0,0 +1,90 @@ + Device (GIO0) + { + Name (_HID, "QCOM050D") // _HID: Hardware ID + Name (_CID, "QCOMFFE3") // _CID: Compatible ID + Name (_UID, Zero) // _UID: Unique ID + Alias (\_SB.PSUB, _SUB) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00400000, // Address Base + 0x00C00000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000249, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, ) + { + 0x0000025B, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000259, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x0000022C, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x0000024E, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000292, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000239, + } + }) + Return (RBUF) /* \_SB_.GIO0._CRS.RBUF */ + } + + Method (OFNI, 0, NotSerialized) + { + Name (RBUF, Buffer (0x02) + { + 0xAF, 0x00 // .. + }) + Return (RBUF) /* \_SB_.GIO0.OFNI.RBUF */ + } + + Name (GABL, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If ((Arg0 == 0x08)) + { + GABL = Arg1 + } + } + + Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts + { + GpioInt (Edge, ActiveHigh, Exclusive, PullDown, 0x01F4, + "\\_SB.GIO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x00BD + } + }) + Method (_EBD, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.GPU0, 0x92) // Device-Specific + } + } \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/pep_lpi.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/pep_lpi.dsl new file mode 100644 index 000000000..8884bbe03 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/pep_lpi.dsl @@ -0,0 +1,1680 @@ + Device (SYSM) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x00100000) // _UID: Unique ID + Device (APC0) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x0100) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x02000000, + 0x03, + Package (0x0A) + { + 0x0BB8, + 0x044C, + One, + Zero, + Zero, + Zero, + 0x0400, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "CCI.E3" + }, + + Package (0x0A) + { + 0x0DAC, + 0x047E, + One, + Zero, + Zero, + Zero, + 0x0500, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "CCI.E3+RPM" + }, + + Package (0x0A) + { + 0x80E8, + 0x01F4, + One, + 0x20, + Zero, + Zero, + 0x0300, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "platform.xo" + } + }) + Device (CL0) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x01000000, + 0x03, + Package (0x0A) + { + 0x012C, + 0x82, + Zero, + Zero, + Zero, + Zero, + 0x20, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D2d" + }, + + Package (0x0A) + { + 0x015E, + 0x96, + Zero, + Zero, + Zero, + Zero, + 0x30, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D2e" + }, + + Package (0x0A) + { + 0x1900, + 0x0384, + One, + Zero, + Zero, + 0x03, + 0x40, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D4" + } + }) + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C3_NI" + } + }) + } + + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C3_NI" + } + }) + } + + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C3_NI" + } + }) + } + + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C3_NI" + } + }) + } + } + + Device (CL1) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x20) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x01000000, + 0x03, + Package (0x0A) + { + 0x0384, + 0xC8, + Zero, + Zero, + Zero, + Zero, + 0x20, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D2d" + }, + + Package (0x0A) + { + 0x03E8, + 0x0190, + Zero, + Zero, + Zero, + Zero, + 0x30, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D2e" + }, + + Package (0x0A) + { + 0x1770, + 0x04B0, + One, + Zero, + Zero, + 0x03, + 0x40, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D4" + } + }) + Device (CPU4) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C3_NI" + } + }) + } + + Device (CPU5) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C3_NI" + } + }) + } + + Device (CPU6) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C3_NI" + } + }) + } + + Device (CPU7) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C3_NI" + } + }) + } + } + } + } diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/pmic_core.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/pmic_core.dsl new file mode 100644 index 000000000..89a2efbb5 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/pmic_core.dsl @@ -0,0 +1,200 @@ +Device (PMIC) +{ + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + SPMI + }) + Name (_HID, "QCOM052E") // _HID: Hardware ID + Name (_CID, "PNP0CA3") // _CID: Compatible ID + Alias (PSUB, _SUB) + Method (PMCF, 0, NotSerialized) + { + Name (CFG0, Package (0x04) + { + 0x02, + Package (0x02) + { + Zero, + One + }, + + Package (0x02) + { + 0x02, + 0x03 + } + }) + Return (CFG0) /* \_SB_.PMIC.PMCF.CFG0 */ + } +} + +Device (PM01) +{ + Name (_HID, "QCOM0530") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, One) // _UID: Unique ID + Name (_DEP, Package (One) // _DEP: Dependencies + { + PMIC + }) + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x000000D7, + } + }) + Return (RBUF) /* \_SB_.PM01._CRS.RBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + While (One) + { + Name (_T_0, Buffer (0x01) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z + { + 0x00 // . + }) + CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.PM01._DSM._T_0 */ + If ((_T_0 == ToUUID ("4f248f40-d5e2-499f-834c-27758ea1cd3f") /* GPIO Controller */)) + { + While (One) + { + Name (_T_1, 0x00) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z + _T_1 = ToInteger (Arg2) + If ((_T_1 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + ElseIf ((_T_1 == One)) + { + Return (Package (0x02) + { + Zero, + One + }) + } + Else + { + } + + Break + } + } + Else + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Break + } + } +} + +Device (PMAP) +{ + Name (_HID, "QCOM052F") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_DEP, Package (0x03) // _DEP: Dependencies + { + PMIC, + ABD, + SCM0 + }) + Method (GEPT, 0, NotSerialized) + { + Name (BUFF, Buffer (0x04){}) + CreateByteField (BUFF, Zero, STAT) + CreateWordField (BUFF, 0x02, DATA) + DATA = 0x02 + Return (DATA) /* \_SB_.PMAP.GEPT.DATA */ + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, Buffer (0x02) + { + 0x79, 0x00 // y. + }) + Return (RBUF) /* \_SB_.PMAP._CRS.RBUF */ + } +} + +Device (PRTC) +{ + Name (_HID, "ACPI000E" /* Time and Alarm Device */) // _HID: Hardware ID + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + PMAP + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_GCP, 0, NotSerialized) // _GCP: Get Capabilities + { + Return (0x04) + } + + Field (\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + Connection ( + I2cSerialBusV2 (0x0002, ControllerInitiated, 0x00000000, + AddressingMode7Bit, "\\_SB.ABD", + 0x00, ResourceConsumer, , Exclusive, + ) + ), + AccessAs (BufferAcc, AttribRawBytes (0x18)), + FLD0, 192 + } + + Method (_GRT, 0, NotSerialized) // _GRT: Get Real Time + { + Name (BUFF, Buffer (0x1A){}) + CreateField (BUFF, 0x10, 0x80, TME1) + CreateField (BUFF, 0x90, 0x20, ACT1) + CreateField (BUFF, 0xB0, 0x20, ACW1) + BUFF = FLD0 /* \_SB_.PRTC.FLD0 */ + Return (TME1) /* \_SB_.PRTC._GRT.TME1 */ + } + + Method (_SRT, 1, NotSerialized) // _SRT: Set Real Time + { + Name (BUFF, Buffer (0x32){}) + CreateByteField (BUFF, Zero, STAT) + CreateField (BUFF, 0x10, 0x80, TME1) + CreateField (BUFF, 0x90, 0x20, ACT1) + CreateField (BUFF, 0xB0, 0x20, ACW1) + ACT1 = Zero + TME1 = Arg0 + ACW1 = Zero + BUFF = FLD0 = BUFF /* \_SB_.PRTC._SRT.BUFF */ + If ((STAT != Zero)) + { + Return (One) + } + + Return (Zero) + } +} + +Device (PEXT) +{ + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + SPMI, + PMIC + }) + Name (_HID, "QCOM05CE") // _HID: Hardware ID + Alias (PSUB, _SUB) +} diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/qcgpio.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/qcgpio.dsl new file mode 100644 index 000000000..44067b4d9 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/qcgpio.dsl @@ -0,0 +1,41 @@ +Device (GIO0) +{ + Name (_HID, "QCOM0217") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TLMM register address space + Memory32Fixed (ReadWrite, 0x00400000, 0x00C00000) + + // Summary Interrupt shared by all banks + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {648} // For PDC Wake up ::TLMM GPIo 126 SD Card Detection + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {568} // For PDC Wake up ::TLMM GPIo 54 + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {646} // For PDC Wake up ::TLMM GPIo 124, Hall sensor used for lid + }) + Return (RBUF) + } + // ACPI method to return Num pins + Method(OFNI, 0x0, NotSerialized) { + Name(RBUF, Buffer() + { + 0x96, // 0: TOTAL_GPIO_PINS + 0x00 // 1: TOTAL_GPIO_PINS + }) + Return (RBUF) + } + + Name(GABL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(LEqual(Arg0, 0x8)) + { + Store(Arg1, GABL) + } + } +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/scm.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/scm.dsl new file mode 100644 index 000000000..3c6567239 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/scm.dsl @@ -0,0 +1,6 @@ +Device (SCM0) +{ + Name (_HID, "QCOM050B") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/spmi.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/spmi.dsl new file mode 100644 index 000000000..3550574f0 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/spmi.dsl @@ -0,0 +1,31 @@ +Device (SPMI) +{ + Name (_HID, "QCOM050C") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_CID, "PNP0CA2") // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x01C00000, // Address Base + 0x02800000, // Address Length + ) + }) + Return (RBUF) /* \_SB_.SPMI._CRS.RBUF */ + } + + Method (CONF, 0, NotSerialized) + { + Name (XBUF, Buffer (0x1A) + { + /* 0000 */ 0x00, 0x01, 0x01, 0x01, 0xFF, 0x00, 0x02, 0x00, // ........ + /* 0008 */ 0x0A, 0x07, 0x04, 0x07, 0x01, 0xFF, 0x10, 0x01, // ........ + /* 0010 */ 0x00, 0x01, 0x01, 0xC0, 0x00, 0x00, 0x02, 0x80, // ...@.... + /* 0018 */ 0x00, 0x00 // .. + }) + Return (XBUF) /* \_SB_.SPMI.CONF.XBUF */ + } +} diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/usb.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/usb.dsl new file mode 100644 index 000000000..1dbe690fc --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/usb.dsl @@ -0,0 +1,416 @@ +Name (QUFN, Zero) + Name (DPP0, Buffer (One) + { + 0x00 // . + }) + Name (DPP1, Buffer (One) + { + 0x00 // . + }) + Name (MPP0, Buffer (One) + { + 0x00 // . + }) + Name (MPP1, Buffer (One) + { + 0x00 // . + }) + Name (HPDB, Zero) + Name (HPDS, Buffer (One) + { + 0x00 // . + }) + Name (PINA, Zero) + Name (DPPN, 0x0D) + Name (CCST, Buffer (One) + { + 0x02 // . + }) + Name (PORT, Buffer (One) + { + 0x02 // . + }) + Name (HIRQ, Buffer (One) + { + 0x00 // . + }) + Name (HSFL, Buffer (One) + { + 0x00 // . + }) + Name (USBC, Buffer (One) + { + 0x0B // . + }) + Name (MUXC, Buffer (One) + { + 0x00 // . + }) + Device (URS0) + { + Method (URSI, 0, NotSerialized) + { + If ((QUFN == Zero)) + { + Return ("QCOM0497") + } + Else + { + Return ("QCOM0498") + } + } + + Alias (URSI, _HID) + Name (_CID, "PNP0CA1") // _CID: Compatible ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x04E00000, // Address Base + 0x00100000, // Address Length + ) + }) + Device (USB0) + { + Name (_ADR, Zero) // _ADR: Address + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "BACK", + PLD_VerticalPosition = "CENTER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "VERTICALRECTANGLE", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0xFFFF, + PLD_HorizontalOffset = 0xFFFF) + + }) + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + One, + 0x09, + Zero, + Zero + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x0000011F, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000001C6, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000000D8, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, ) + { + 0x000000DC, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, ) + { + 0x0000014E, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (DPM0, 1, NotSerialized) + { + DPP0 = Arg0 + } + + Method (CCVL, 0, NotSerialized) + { + Return (CCST) /* \_SB_.CCST */ + } + + Method (HSEN, 0, NotSerialized) + { + Return (HSFL) /* \_SB_.HSFL */ + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Switch (ToBuffer (Arg0)) + { + Case (ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899") /* USB Controller */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x1D // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (0x02) + { + Return (Zero) + Break + } + Case (0x03) + { + Return (Zero) + Break + } + Case (0x04) + { + Return (0x02) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + + Method (PHYC, 0, NotSerialized) + { + Name (CFG0, Package (0x00) {}) + Return (CFG0) /* \_SB_.URS0.USB0.PHYC.CFG0 */ + } + } + + Device (UFN0) + { + Name (_ADR, One) // _ADR: Address + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "BACK", + PLD_VerticalPosition = "CENTER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "VERTICALRECTANGLE", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0xFFFF, + PLD_HorizontalOffset = 0xFFFF) + + }) + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + One, + 0x09, + Zero, + Zero + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x0000011F, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000001C6, + } + }) + Method (CCVL, 0, NotSerialized) + { + Return (CCST) /* \_SB_.CCST */ + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Switch (ToBuffer (Arg0)) + { + Case (ToUUID ("fe56cfeb-49d5-4378-a8a2-2978dbe54ad2") /* Unknown UUID */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (One) + { + Return (0x20) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Case (ToUUID ("18de299f-9476-4fc9-b43b-8aeb713ed751") /* Unknown UUID */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (One) + { + Return (0x39) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + + Method (PHYC, 0, NotSerialized) + { + Name (CFG0, Package (0x00) {}) + Return (CFG0) /* \_SB_.URS0.UFN0.PHYC.CFG0 */ + } + } + } diff --git a/Platform/Xiaomi/sm6225/fog.dsc b/Platform/Xiaomi/sm6225/fog.dsc index 82c50c7a4..37c793ded 100644 --- a/Platform/Xiaomi/sm6225/fog.dsc +++ b/Platform/Xiaomi/sm6225/fog.dsc @@ -8,16 +8,16 @@ SUPPORTED_ARCHITECTURES = AARCH64 BUILD_TARGETS = DEBUG|RELEASE SKUID_IDENTIFIER = DEFAULT - FLASH_DEFINITION = Platform/Qualcomm/sm6225/sm6225.fog.fdf + FLASH_DEFINITION = Platform/Qualcomm/sm6225/sm6225.fdf DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm6225/fog.fdf.inc # Enable A/B Slot Environment AB_SLOTS_SUPPORT = TRUE -!include Platform/Qualcomm/sm6225/sm6225.fog.dsc +!include Platform/Qualcomm/sm6225/sm6225.dsc [BuildOptions.common] - GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT [PcdsFixedAtBuild.common] gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|720 diff --git a/Platform/Xiaomi/sm6225/fog.fdf.inc b/Platform/Xiaomi/sm6225/fog.fdf.inc index dddb53e0a..058940a99 100644 --- a/Platform/Xiaomi/sm6225/fog.fdf.inc +++ b/Platform/Xiaomi/sm6225/fog.fdf.inc @@ -1,8 +1,17 @@ // per-device BSP DXEs +INF Platform/EFI_Binaries/Drivers/sm6225/ButtonsDxe/ButtonsDxe.inf // ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml + SECTION RAW = Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml + SECTION RAW = Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml + SECTION UI = "AcpiTables" +} -FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { +// Mainline device tree blob + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { SECTION RAW = Platform/Xiaomi/sm6225/FdtBlob_compat/fog.dtb } diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml new file mode 100644 index 000000000..68703c947 Binary files /dev/null and b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml differ diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/FADT.dsl b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.dsl new file mode 100644 index 000000000..ddbf2a406 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.dsl @@ -0,0 +1,164 @@ +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000114 +[008h 0008 1] Revision : 06 +[009h 0009 1] Checksum : 25 +[00Ah 0010 6] Oem ID : "QCOM " +[010h 0016 8] Oem Table ID : "QCOMEDK2" +[018h 0024 4] Oem Revision : 00006225 +[01Ch 0028 4] Asl Compiler ID : "INTL" +[020h 0032 4] Asl Compiler Revision : 20200925 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 08 [Tablet] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00300000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 03 [EmbeddedControl] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 03 [DWord Access:32] +[078h 0120 8] Address : 00000000009020B4 + +[080h 0128 1] Value to cause reset : 01 +[081h 0129 2] ARM Flags (decoded below) : 0001 + PSCI Compliant : 1 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +[10Ch 0268 8] Hypervisor ID : 000000004D4F4351 \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml new file mode 100644 index 000000000..e5731bd7c Binary files /dev/null and b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml differ diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.dsl b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.dsl new file mode 100644 index 000000000..6100a05e0 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.dsl @@ -0,0 +1,63 @@ +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 0000009C +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 91 +[00Ah 0010 6] Oem ID : "QCOM " +[010h 0016 8] Oem Table ID : "QCOMEDK2" +[018h 0024 4] Oem Revision : 00006225 +[01Ch 0028 4] Asl Compiler ID : "INTL" +[020h 0032 4] Asl Compiler Revision : 20200925 + +[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 00000011 +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 00000012 +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[040h 0064 4] Virtual Timer Interrupt : 00000013 +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 00000010 +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF + +[058h 0088 4] Platform Timer Count : 00000001 +[05Ch 0092 4] Platform Timer Offset : 00000060 + +[060h 0096 1] Subtable Type : 00 [Generic Timer Block] +[061h 0097 2] Length : 003C +[063h 0099 1] Reserved : 00 +[064h 0100 8] Block Address : 000000000F120000 +[06Ch 0108 4] Timer Count : 00000001 +[070h 0112 4] Timer Offset : 00000014 + +[074h 0116 1] Frame Number : 00 +[075h 0117 3] Reserved : 000000 +[078h 0120 8] Base Address : 000000000F121000 +[080h 0128 8] EL0 Base Address : 000000000F122000 +[088h 0136 4] Timer Interrupt : 00000028 +[08Ch 0140 4] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[090h 0144 4] Virtual Timer Interrupt : 00000027 +[094h 0148 4] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[098h 0152 4] Common Flags (decoded below) : 00000002 + Secure : 0 + Always On : 1 \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml new file mode 100644 index 000000000..d027d5c91 Binary files /dev/null and b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml differ diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/MADT.dsl b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.dsl new file mode 100644 index 000000000..c70f6b92f --- /dev/null +++ b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.dsl @@ -0,0 +1,212 @@ +[000h 0000 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 004h] Table Length : 000002EC +[008h 0008 001h] Revision : 05 +[009h 0009 001h] Checksum : 1A +[00Ah 0010 006h] Oem ID : "QCOM " +[010h 0016 008h] Oem Table ID : "QCOMEDK2" +[018h 0024 004h] Oem Revision : 00006225 +[01Ch 0028 004h] Asl Compiler ID : "INTL" +[020h 0032 004h] Asl Compiler Revision : 20230628 + +[024h 0036 004h] Local Apic Address : 00000000 +[028h 0040 004h] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 001h] Subtable Type : 0B [Generic Interrupt Controller] +[02Dh 0045 001h] Length : 50 +[02Eh 0046 002h] Reserved : 0000 +[030h 0048 004h] CPU Interface Number : 00000000 +[034h 0052 004h] Processor UID : 00000000 +[038h 0056 004h] Flags (decoded below) : 00000001 + Processor Enabled : 0 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[03Ch 0060 004h] Parking Protocol Version : 00000000 +[040h 0064 004h] Performance Interrupt : 00000016 +[044h 0068 008h] Parked Address : 0000000000000000 +[04Ch 0076 008h] Base Address : 0000000000000000 +[054h 0084 008h] Virtual GIC Base Address : 0000000000000000 +[05Ch 0092 008h] Hypervisor GIC Base Address : 0000000000000000 +[064h 0100 004h] Virtual GIC Interrupt : 00000018 +[068h 0104 008h] Redistributor Base Address : 0000000000000000 +[070h 0112 008h] ARM MPIDR : 0000000000000000 +[078h 0120 001h] Efficiency Class : 00 +[079h 0121 001h] Reserved : 00 +[07Ah 0122 002h] SPE Overflow Interrupt : 0000 +[07Ch 0124 002h] TRBE Interrupt : 500B + +[07Eh 0126 001h] Subtable Type : 0B [Generic Interrupt Controller] +[07Fh 0127 001h] Length : 50 +[080h 0128 002h] Reserved : 0000 +[082h 0130 004h] CPU Interface Number : 00000001 +[086h 0134 004h] Processor UID : 00000001 +[08Ah 0138 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[08Eh 0142 004h] Parking Protocol Version : 00000000 +[092h 0146 004h] Performance Interrupt : 00000016 +[096h 0150 008h] Parked Address : 0000000000000000 +[09Eh 0158 008h] Base Address : 0000000000000000 +[0A6h 0166 008h] Virtual GIC Base Address : 0000000000000000 +[0AEh 0174 008h] Hypervisor GIC Base Address : 0000000000000000 +[0B6h 0182 004h] Virtual GIC Interrupt : 00000018 +[0BAh 0186 008h] Redistributor Base Address : 0000000000000000 +[0C2h 0194 008h] ARM MPIDR : 0000000000000001 +[0CAh 0202 001h] Efficiency Class : 00 +[0CBh 0203 001h] Reserved : 00 +[0CCh 0204 002h] SPE Overflow Interrupt : 0000 +[0CEh 0206 002h] TRBE Interrupt : 500B + +[0D0h 0208 001h] Subtable Type : 0B [Generic Interrupt Controller] +[0D1h 0209 001h] Length : 50 +[0D2h 0210 002h] Reserved : 0000 +[0D4h 0212 004h] CPU Interface Number : 00000002 +[0D8h 0216 004h] Processor UID : 00000002 +[0DCh 0220 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0E0h 0224 004h] Parking Protocol Version : 00000000 +[0E4h 0228 004h] Performance Interrupt : 00000016 +[0E8h 0232 008h] Parked Address : 0000000000000000 +[0F0h 0240 008h] Base Address : 0000000000000000 +[0F8h 0248 008h] Virtual GIC Base Address : 0000000000000000 +[100h 0256 008h] Hypervisor GIC Base Address : 0000000000000000 +[108h 0264 004h] Virtual GIC Interrupt : 00000018 +[10Ch 0268 008h] Redistributor Base Address : 0000000000000000 +[114h 0276 008h] ARM MPIDR : 0000000000000002 +[11Ch 0284 001h] Efficiency Class : 00 +[11Dh 0285 001h] Reserved : 00 +[11Eh 0286 002h] SPE Overflow Interrupt : 0000 +[120h 0288 002h] TRBE Interrupt : 500B + +[122h 0290 001h] Subtable Type : 0B [Generic Interrupt Controller] +[123h 0291 001h] Length : 50 +[124h 0292 002h] Reserved : 0000 +[126h 0294 004h] CPU Interface Number : 00000003 +[12Ah 0298 004h] Processor UID : 00000003 +[12Eh 0302 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[132h 0306 004h] Parking Protocol Version : 00000000 +[136h 0310 004h] Performance Interrupt : 00000016 +[13Ah 0314 008h] Parked Address : 0000000000000000 +[142h 0322 008h] Base Address : 0000000000000000 +[14Ah 0330 008h] Virtual GIC Base Address : 0000000000000000 +[152h 0338 008h] Hypervisor GIC Base Address : 0000000000000000 +[15Ah 0346 004h] Virtual GIC Interrupt : 00000018 +[15Eh 0350 008h] Redistributor Base Address : 0000000000000000 +[166h 0358 008h] ARM MPIDR : 0000000000000003 +[16Eh 0366 001h] Efficiency Class : 00 +[16Fh 0367 001h] Reserved : 00 +[170h 0368 002h] SPE Overflow Interrupt : 0000 +[172h 0370 002h] TRBE Interrupt : 500B + +[174h 0372 001h] Subtable Type : 0B [Generic Interrupt Controller] +[175h 0373 001h] Length : 50 +[176h 0374 002h] Reserved : 0000 +[178h 0376 004h] CPU Interface Number : 00000004 +[17Ch 0380 004h] Processor UID : 00000004 +[180h 0384 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[184h 0388 004h] Parking Protocol Version : 00000000 +[188h 0392 004h] Performance Interrupt : 00000016 +[18Ch 0396 008h] Parked Address : 0000000000000000 +[194h 0404 008h] Base Address : 0000000000000000 +[19Ch 0412 008h] Virtual GIC Base Address : 0000000000000000 +[1A4h 0420 008h] Hypervisor GIC Base Address : 0000000000000000 +[1ACh 0428 004h] Virtual GIC Interrupt : 00000018 +[1B0h 0432 008h] Redistributor Base Address : 0000000000000000 +[1B8h 0440 008h] ARM MPIDR : 0000000000000100 +[1C0h 0448 001h] Efficiency Class : 01 +[1C1h 0449 001h] Reserved : 00 +[1C2h 0450 002h] SPE Overflow Interrupt : 0000 +[1C4h 0452 002h] TRBE Interrupt : 500B + +[1C6h 0454 001h] Subtable Type : 0B [Generic Interrupt Controller] +[1C7h 0455 001h] Length : 50 +[1C8h 0456 002h] Reserved : 0000 +[1CAh 0458 004h] CPU Interface Number : 00000005 +[1CEh 0462 004h] Processor UID : 00000005 +[1D2h 0466 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[1D6h 0470 004h] Parking Protocol Version : 00000000 +[1DAh 0474 004h] Performance Interrupt : 00000016 +[1DEh 0478 008h] Parked Address : 0000000000000000 +[1E6h 0486 008h] Base Address : 0000000000000000 +[1EEh 0494 008h] Virtual GIC Base Address : 0000000000000000 +[1F6h 0502 008h] Hypervisor GIC Base Address : 0000000000000000 +[1FEh 0510 004h] Virtual GIC Interrupt : 00000018 +[202h 0514 008h] Redistributor Base Address : 0000000000000000 +[20Ah 0522 008h] ARM MPIDR : 0000000000000101 +[212h 0530 001h] Efficiency Class : 01 +[213h 0531 001h] Reserved : 00 +[214h 0532 002h] SPE Overflow Interrupt : 0000 +[216h 0534 002h] TRBE Interrupt : 500B + +[218h 0536 001h] Subtable Type : 0B [Generic Interrupt Controller] +[219h 0537 001h] Length : 50 +[21Ah 0538 002h] Reserved : 0000 +[21Ch 0540 004h] CPU Interface Number : 00000006 +[220h 0544 004h] Processor UID : 00000006 +[224h 0548 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[228h 0552 004h] Parking Protocol Version : 00000000 +[22Ch 0556 004h] Performance Interrupt : 00000016 +[230h 0560 008h] Parked Address : 0000000000000000 +[238h 0568 008h] Base Address : 0000000000000000 +[240h 0576 008h] Virtual GIC Base Address : 0000000000000000 +[248h 0584 008h] Hypervisor GIC Base Address : 0000000000000000 +[250h 0592 004h] Virtual GIC Interrupt : 00000018 +[254h 0596 008h] Redistributor Base Address : 0000000000000000 +[25Ch 0604 008h] ARM MPIDR : 0000000000000102 +[264h 0612 001h] Efficiency Class : 01 +[265h 0613 001h] Reserved : 00 +[266h 0614 002h] SPE Overflow Interrupt : 0000 +[268h 0616 002h] TRBE Interrupt : 500B + +[26Ah 0618 001h] Subtable Type : 0B [Generic Interrupt Controller] +[26Bh 0619 001h] Length : 50 +[26Ch 0620 002h] Reserved : 0000 +[26Eh 0622 004h] CPU Interface Number : 00000007 +[272h 0626 004h] Processor UID : 00000007 +[276h 0630 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[27Ah 0634 004h] Parking Protocol Version : 00000000 +[27Eh 0638 004h] Performance Interrupt : 00000016 +[282h 0642 008h] Parked Address : 0000000000000000 +[28Ah 0650 008h] Base Address : 0000000000000000 +[292h 0658 008h] Virtual GIC Base Address : 0000000000000000 +[29Ah 0666 008h] Hypervisor GIC Base Address : 0000000000000000 +[2A2h 0674 004h] Virtual GIC Interrupt : 00000018 +[2A6h 0678 008h] Redistributor Base Address : 0000000000000000 +[2AEh 0686 008h] ARM MPIDR : 0000000000000103 +[2B6h 0694 001h] Efficiency Class : 01 +[2B7h 0695 001h] Reserved : 00 +[2B8h 0696 002h] SPE Overflow Interrupt : 0000 +[2BAh 0698 002h] TRBE Interrupt : 500C + +[2BCh 0700 001h] Subtable Type : 0C [Generic Interrupt Distributor] +[2BDh 0701 001h] Length : 18 +[2BEh 0702 002h] Reserved : 0000 +[2C0h 0704 004h] Local GIC Hardware ID : 00000000 +[2C4h 0708 008h] Base Address : 000000000F200000 +[2CCh 0716 004h] Interrupt Base : 00000000 +[2D0h 0720 001h] Version : 03 +[2D1h 0721 003h] Reserved : 000000 + +[2D4h 0724 001h] Subtable Type : 0E [Generic Interrupt Redistributor] +[2D5h 0725 001h] Length : 10 +[2D6h 0726 002h] Reserved : 0000 +[2D8h 0728 008h] Base Address : 000000000F300000 +[2E0h 0736 004h] Length : 00100000 diff --git a/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h b/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h index fa13619b3..edb96ba35 100644 --- a/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h +++ b/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h @@ -10,37 +10,37 @@ typedef struct { static CONFIGURATION_DESCRIPTOR_EX gDeviceConfigurationDescriptorEx[] = { {"NumCpusFuseAddr", 0x5C04C}, - {"EnableShell", 0x1}, - {"SharedIMEMBaseAddr", 0x0C125000}, - {"DloadCookieAddr", 0x003D3000}, - {"DloadCookieValue", 0x10}, - {"NumCpus", 8}, - {"NumActiveCores", 8}, - {"MaxLogFileSize", 0x400000}, - {"UefiMemUseThreshold", 0x77}, - {"USBHS1_Config", 0x0}, - {"UsbFnIoRevNum", 0x00010001}, - {"PwrBtnShutdownFlag", 0x0}, - {"Sdc1GpioConfigOn", 0x1E92}, - {"Sdc2GpioConfigOn", 0x1E92}, - {"Sdc1GpioConfigOff", 0xA00}, - {"Sdc2GpioConfigOff", 0xA00}, - {"EnableSDHCSwitch", 0x1}, - {"EnableUfsIOC", 0}, - {"UfsSmmuConfigForOtherBootDev", 1}, - {"SecurityFlag", 0xC4}, - {"TzAppsRegnAddr", 0x61800000}, - {"TzAppsRegnSize", 0x02100000}, - {"TzAppsRegnSizeLowRAM", 0xB00000}, - {"EnableLogFsSyncInRetail", 0x0}, - {"ShmBridgememSize", 0xA00000}, - {"EnableMultiThreading", 1}, - {"MaxCoreCnt", 8}, - {"EarlyInitCoreCnt", 1}, - {"EnableDisplayThread", 1}, - {"EnableUefiSecAppDebugLogDump", 0x1}, - {"AllowNonPersistentVarsInRetail", 0x1}, - {"MinidumpTALoadingCfg", 0x0}, + {"EnableShell", 0x1}, + {"SharedIMEMBaseAddr", 0x0C125000}, + {"DloadCookieAddr", 0x003D3000}, + {"DloadCookieValue", 0x10}, + {"NumCpus", 8}, + {"NumActiveCores", 8}, + {"MaxLogFileSize", 0x400000}, + {"UefiMemUseThreshold", 0x77}, + {"USBHS1_Config", 0x0}, + {"UsbFnIoRevNum", 0x00010001}, + {"PwrBtnShutdownFlag", 0x0}, + {"Sdc1GpioConfigOn", 0x1E92}, + {"Sdc2GpioConfigOn", 0x1E92}, + {"Sdc1GpioConfigOff", 0xA00}, + {"Sdc2GpioConfigOff", 0xA00}, + {"EnableSDHCSwitch", 0x1}, + {"EnableUfsIOC", 0}, + {"UfsSmmuConfigForOtherBootDev", 1}, + {"SecurityFlag", 0xC4}, + {"TzAppsRegnAddr", 0x61800000}, + {"TzAppsRegnSize", 0x02100000}, + {"TzAppsRegnSizeLowRAM", 0xB00000}, + {"EnableLogFsSyncInRetail", 0x0}, + {"ShmBridgememSize", 0xA00000}, + {"EnableMultiThreading", 1}, + {"MaxCoreCnt", 8}, + {"EarlyInitCoreCnt", 1}, + {"EnableDisplayThread", 1}, + {"EnableUefiSecAppDebugLogDump", 0x1}, + {"AllowNonPersistentVarsInRetail", 0x1}, + {"MinidumpTALoadingCfg", 0x0}, /* Terminator */ {"Terminator", 0xFFFFFFFF}}; diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c index f983fdcf0..f5b5da16d 100644 --- a/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c +++ b/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -5,78 +5,96 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { /* EFI_RESOURCE_ EFI_RESOURCE_ATTRIBUTE_ EFI_MEMORY_TYPE ARM_REGION_ATTRIBUTE_ MemLabel(32 Char.), MemBase, MemSize, BuildHob, ResourceType, ResourceAttribute, MemoryType, CacheAttributes --------------------- DDR --------------------- */ - { "Kernel", 0x40000000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - { "HYP", 0x45700000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - { "Boot Info", 0x45D00000, 0x00020000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, -// { "AOP CMD DB", 0x85F00000, 0x00040000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - { "SMEM", 0x46000000, 0x00200000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - { "RAM Partition", 0x53F00000, 0x02800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - { "PIL Reserved", 0x4AB00000, 0x0A400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - { "DBI Dump", 0x56700000, 0x00A00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, - { "Sched Heap", 0x57100000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - { "Display Reserved", 0x5C000000, 0x01000000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, - { "LAST LOG", 0x5D000000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - { "FV Region", 0x5F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - { "ABOOT FV", 0x5FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK}, - { "UEFI FD", 0x5FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, - { "SEC Heap", 0x5FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - { "CPU Vectors", 0x5FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, - { "MMU PageTables", 0x5FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - { "UEFI Stack", 0x5FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - { "Log Buffer", 0x5FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, - { "Info Blk", 0x5FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, - /* Memory hole (0x60000000 - 0x638FFFFF) */ - { "DXE Heap", 0x63900000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK}, - { "UEFI FD", 0x71900000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, - /* DDR Bank 0 End */ - /* Carveout Region (0x7DD00000 -> 0x80000000, size 0x02300000) */ - /* DDR Bank 1 Start */ - { "RAM Partition", 0x80000000, 0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - /* DDR Bank 1 End */ - /* DDR Bank 2 Start */ - { "RAM Partition", 0xC0000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x40000000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Hypervisor", 0x45700000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x45D00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x46000000, 0x00200000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x46200000, 0x04900000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"PIL Reserved", 0x4AB00000, 0x0A400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x54F00000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"DXE Heap", 0x63900000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK}, + {"RAM Partition", 0x67E00000, 0x09B00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"DBI Dump", 0x56700000, 0x00A00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"Sched Heap", 0x57100000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x57500000, 0x04B00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x5C000000, 0x01000000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"LAST LOG", 0x5D000000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x5D400000, 0x02400000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"FV Region", 0x5F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x5FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0x5FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"SEC Heap", 0x5FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x5FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x5FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x5FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x5FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x5FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Info Blk", 0x5FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + //==================================================3GB RAM Setup================================================== + // This RAM parition starts just after Info Blk and ends with DDR Bank 0 + {"RAM Partition", 0x60000000, 0x1E580000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + // DDR Bank 0 end + + // DDR Bank 1 start + {"RAM Partition", 0x80000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + // As RAM starts at 0x80000000 (2GB) and this is a 3GB device, so it must ends at 5GB, then 0x140000000 = 0xC0000000 + 0x80000000 + {"RAM Partition", 0xC0000000,0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +//================================================================================================================= + +//==================================================4GB RAM Setup================================================== + // This RAM parition starts just after Info Blk and ends with DDR Bank 0 + {"RAM Partition", 0x60000000, 0x1DD00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + // DDR Bank 0 end + + // DDR Bank 1 start + {"RAM Partition", 0x80000000, 0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + // As RAM starts at 0x80000000 (2GB) and this is a 4GB device, so it must ends at 6GB, then 0x180000000 = 0x100000000 + 0x80000000 + {"RAM Partition", 0xC0000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +//================================================================================================================= //--------------------- Other --------------------- - { "RPM_SS_MSG_RAM", 0x045F0000, 0x00007000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, - { "IMEM Base", 0x0C100000, 0x00026000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, - { "IMEM Cookie Base", 0x0C125000, 0x00001000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"RPM_SS_MSG_RAM", 0x045F0000, 0x00007000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Base", 0x0C100000, 0x00026000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x0C125000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + // Register regions + {"TCSR_TCSR_REGS", 0x003C0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x00500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x00900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_EAST", 0x00D00000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GCC CLK CTL", 0x01400000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PMIC ARB SPMI", 0x01C00000, 0x02800000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MMCX_CPR3", 0x01648000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01B00000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x01B40000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x01B50000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SLP_CNTR", 0x04403000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0", 0x04410000 ,0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0_TM", 0x04411000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PSHOLD", 0x0440B000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x04A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x04C00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"UFS UFS REGS", 0x04800000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x04700000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x04E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x0597D000, 0x0000C000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x05990000, 0x00009000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"VIDEO_CC", 0x05B00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MDSS", 0x05E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"DISP_CC_DISP_CC", 0x05F00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x0C600000, 0x00080000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_WDT_TMR1", 0x0F017000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QTIMER", 0x0F020000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APCS_ALIAS0_GLB", 0x0F111000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_GIC500_GICD", 0x0F200000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_GIC500_GICR", 0x0F300000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"OSM_RAIL", 0x0F520000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_ACTPM_WRAP", 0x0F500000, 0x000B0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB2", 0x01610000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MCCC_MCCC_MSTR", 0x0447D000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, -//--------------------- Register --------------------- - { "TCSR_TCSR_REGS", 0x003C0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "TLMM_WEST", 0x00500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "TLMM_SOUTH", 0x00900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "TLMM_EAST", 0x00D00000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "GCC_CLK_CTL", 0x01400000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "PMIC ARB SPMI", 0x01C00000, 0x02800000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "MMCX_CPR3", 0x01648000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "CRYPTO0 CRYPTO", 0x01B00000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "SECURITY CONTROL", 0x01B40000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "PRNG_CFG_PRNG", 0x01B50000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "SLP_CNTR", 0x04403000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "TSENS0", 0x04410000 ,0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "TSENS0_TM", 0x04411000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "PSHOLD", 0x0440B000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "QUPV3_0_GSI", 0x04A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "QUPV3_1_GSI", 0x04C00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "UFS UFS REGS", 0x04800000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "PERIPH_SS", 0x04700000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "USB30_PRIM", 0x04E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "GPU_GMU_CX_BLK", 0x0597D000, 0x0000C000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "GPU_CC", 0x05990000, 0x00009000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "VIDEO_CC", 0x05B00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "MDSS", 0x05E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "DISP_CC", 0x05F00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "SMMU", 0x0C600000, 0x00080000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "APSS_WDT_TMR1", 0x0F017000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "QTIMER", 0x0F020000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "APCS_ALIAS0_GLB", 0x0F111000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "APSS_GIC500_GICD", 0x0F200000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "APSS_GIC500_GICR", 0x0F300000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "OSM_RAIL", 0x0F520000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "APSS_ACTPM_WRAP", 0x0F500000, 0x000B0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "USB2", 0x01610000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - { "MCCC_MCCC_MSTR", 0x0447D000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, /* Terminator for MMU */ {"Terminator", 0, 0, 0, 0, 0, 0, 0}};