diff --git a/common/verilog/core/clock_divider.v b/common/verilog/core/clock_divider.v new file mode 100644 index 00000000..8fab607d --- /dev/null +++ b/common/verilog/core/clock_divider.v @@ -0,0 +1,27 @@ +module clock_divider #( + parameter p_divisor = 2 // Clock division factor +) ( + output reg o_w_clk, // Output divided clock + input wire i_w_clk, // Input clock + input wire i_w_reset // Reset signal +); + + // Compute the size of the counter for the division + localparam l_p_counter_width = $clog2(p_divisor) + 1; + reg [l_p_counter_width:0] counter; + + always @(posedge i_w_clk or negedge i_w_reset) begin + if (!i_w_reset) begin + counter <= 0; + o_w_clk <= 0; + end else begin + if (counter == (p_divisor - 1)) begin + counter <= 0; + o_w_clk <= ~o_w_clk; + end else begin + counter <= counter + 1; + end + end + end + +endmodule \ No newline at end of file diff --git a/common/verilog/core/debouncer.v b/common/verilog/core/debouncer.v new file mode 100644 index 00000000..aa9b72ac --- /dev/null +++ b/common/verilog/core/debouncer.v @@ -0,0 +1,31 @@ +module debouncer #( + parameter p_no_cycles = 1000000 // Clock cycles for debouncing +) ( + output reg o_w_out, // Debounced output + input wire i_w_in, // Input signal + input wire i_w_clk, // Clock signal + input wire i_w_reset // Reset signal +); + + // Compute the size of the counter for the debouncing + localparam l_p_counter_width = $clog2(p_no_cycles); + reg[(l_p_counter_width - 1):0] l_r_counter; + + always @(posedge i_w_clk or negedge i_w_reset) begin + if(!i_w_reset) begin + l_r_counter <= 0; + o_w_out <= 0; + end else begin + if(i_w_in == o_w_out) begin + l_r_counter <= 0; + end else begin + if(l_r_counter == (p_no_cycles - 1)) begin + o_w_out <= i_w_in; + l_r_counter <= 0; + end else begin + l_r_counter <= l_r_counter + 1; + end + end + end + end +endmodule diff --git a/common/verilog/led7hex.v b/common/verilog/core/led7hex.v similarity index 72% rename from common/verilog/led7hex.v rename to common/verilog/core/led7hex.v index 2d206fc9..605d8fb3 100644 --- a/common/verilog/led7hex.v +++ b/common/verilog/core/led7hex.v @@ -1,16 +1,7 @@ -module led7conv ( - output wire o_w_ca, - output wire o_w_cb, - output wire o_w_cc, - output wire o_w_cd, - output wire o_w_ce, - output wire o_w_cf, - output wire o_w_cg, - output wire o_w_dp, +module led7hex ( + output reg [7:0] l_r_led7, input wire [3:0] i_w_value ); - reg [7:0] l_r_led7; - always @(*) begin case (i_w_value) 4'h0: l_r_led7 = 8'b1100_0000; @@ -32,7 +23,4 @@ module led7conv ( default: l_r_led7 = 8'b1111_1111; endcase end - - assign {o_w_dp, o_w_cg, o_w_cf, o_w_ce, o_w_cd, o_w_cc, o_w_cb, o_w_ca} = l_r_led7; - endmodule \ No newline at end of file diff --git a/common/verilog/core/otp_button.v b/common/verilog/core/otp_button.v new file mode 100644 index 00000000..8ded5b25 --- /dev/null +++ b/common/verilog/core/otp_button.v @@ -0,0 +1,42 @@ +module otp_button ( + output wire o_w_button_press, + input wire i_w_clk, + input wire i_w_button +); + + localparam l_p_state_ButtonReleased = 2'd0; + localparam l_p_state_ButtonFirstPressed = 2'd1; + localparam l_p_state_ButtonPressed = 2'd2; + + reg [1:0] l_r_state; + reg [1:0] l_r_next_state; + + always @(posedge i_w_clk) begin + l_r_state <= l_r_next_state; + end + + always @(*) begin + l_r_next_state = l_p_state_ButtonReleased; + case(l_r_state) + l_p_state_ButtonReleased: begin + if (i_w_button) + l_r_next_state = l_p_state_ButtonFirstPressed; + else + l_r_next_state = l_p_state_ButtonReleased; + end + l_p_state_ButtonFirstPressed: begin + l_r_next_state = l_p_state_ButtonPressed; + end + l_p_state_ButtonPressed: begin + if (i_w_button) + l_r_next_state = l_p_state_ButtonPressed; + else + l_r_next_state = l_p_state_ButtonReleased; + end + default: l_r_next_state = l_p_state_ButtonReleased; + endcase + end + + assign o_w_button_press = (l_r_state == l_p_state_ButtonFirstPressed); + +endmodule \ No newline at end of file diff --git a/common/verilog/labcpu/Makefile b/common/verilog/labcpu/Makefile index aa77cd81..fbbe0a38 100644 --- a/common/verilog/labcpu/Makefile +++ b/common/verilog/labcpu/Makefile @@ -1,20 +1,37 @@ -all: build -build: build_project/build.xpr +COMPILER=iverilog +INTERPRETER=vvp +SIMULATOR=gtkwave +FLAGS=-Wall -Winfloop + +# TODO: use the command line to pass the following parameters +TOP_MODULE=cpu_debugger +OTHER_SOURCES=alu.v bus.v cpu.v control_unit.v cram.v state_display.v +RAM_DATA_FILE=cram.data +MEMORY_SOURCES=../memory/block_ram.v ../memory/block_dpram.v ../memory/register.v ../memory/regfile.v +CORE_SOURCES=../core/clock_divider.v ../core/debouncer.v ../core/led7hex.v ../core/otp_button.v -build_project/build.xpr: - vivado -mode batch -source tcl_files/build.tcl +# compute the filenames +TOP_MODULE_FILE=$(TOP_MODULE).v +TOP_SIM_MODULE_FILE=test_${TOP_MODULE}.v +TOP_MODULE_BIN=$(TOP_MODULE).vvp -run: build_project/build.xpr - vivado -mode batch -source tcl_files/run.tcl +all: build -simulation: build_project/build.xpr - vivado -mode batch -source tcl_files/simulation.tcl +build: + $(COMPILER) $(FLAGS) $(TOP_MODULE_FILE) $(TOP_SIM_MODULE_FILE) $(OTHER_SOURCES) $(MEMORY_SOURCES) $(CORE_SOURCES) -o $(TOP_MODULE_BIN) + @echo "Build completed" -vivado: build_project/build.xpr - vivado build_project/build.xpr +run: build + $(INTERPRETER) $(TOP_MODULE_BIN) clean: + rm $(TOP_MODULE_BIN) + +vivado: + vivado -mode batch -source tcl_files/vivado.tcl + +clean_vivado: rm -rf vivado* rm -rf build_project rm -rf .Xil \ No newline at end of file diff --git a/common/verilog/labcpu/alu.v b/common/verilog/labcpu/alu.v index 0e45a4c0..1167590a 100644 --- a/common/verilog/labcpu/alu.v +++ b/common/verilog/labcpu/alu.v @@ -1,29 +1,30 @@ -`timescale 1ns / 1ps module alu #( parameter p_data_width = 16, - parameter p_flags_width = 5 -)( + parameter p_flags_width = 5, + parameter p_opcode_width = 4, + parameter p_opcode_ADC = 4'd0, + parameter p_opcode_SBB1 = 4'd1, + parameter p_opcode_SBB2 = 4'd2, + parameter p_opcode_NOT = 4'd3, + parameter p_opcode_AND = 4'd4, + parameter p_opcode_OR = 4'd5, + parameter p_opcode_XOR = 4'd6, + parameter p_opcode_SHL = 4'd7, + parameter p_opcode_SHR = 4'd8, + parameter p_opcode_SAR = 4'd9 +) ( output wire [(p_data_width-1):0] o_w_out, output wire [(p_flags_width-1):0] o_w_flags, input wire [(p_data_width-1):0] i_w_in1, input wire [(p_data_width-1):0] i_w_in2, - input wire [3:0] i_w_opcode, + input wire [(p_opcode_width-1):0] i_w_opcode, input wire i_w_carry, input wire i_w_oe ); -localparam ADC = 4'd0; -localparam SBB1 = 4'd1; -localparam SBB2 = 4'd2; -localparam NOT = 4'd3; -localparam AND = 4'd4; -localparam OR = 4'd5; -localparam XOR = 4'd6; -localparam SHL = 4'd7; -localparam SHR = 4'd8; -localparam SAR = 4'd9; - +// result reg [(p_data_width-1) : 0] l_r_result; +// flags reg l_r_parity; reg l_r_sign; reg l_r_zero; @@ -32,61 +33,62 @@ reg l_r_carry; always @(*) begin case(i_w_opcode) - ADC: begin + p_opcode_ADC: begin {l_r_carry, l_r_result} = i_w_in1 + i_w_in2 + i_w_carry; l_r_overflow = (i_w_in1[p_data_width-1] == i_w_in2[p_data_width-1]) && (i_w_in1[p_data_width-1] != l_r_result[p_data_width-1]); end - SBB1: begin + p_opcode_SBB1: begin {l_r_carry, l_r_result} = i_w_in1 - i_w_in2 - i_w_carry; l_r_overflow = (i_w_in1[p_data_width-1] != i_w_in2[p_data_width-1]) && (i_w_in1[p_data_width-1] != l_r_result[p_data_width-1]); end - SBB2: begin + p_opcode_SBB2: begin {l_r_carry, l_r_result} = i_w_in2 - i_w_in1 - i_w_carry; l_r_overflow = (i_w_in2[p_data_width-1] != i_w_in1[p_data_width-1]) && (i_w_in2[p_data_width-1] != l_r_result[p_data_width-1]); end - AND: begin - l_r_result = i_w_in1 & i_w_in2; + p_opcode_NOT: begin + l_r_result = ~(i_w_in1 | i_w_in2); l_r_carry = 0; l_r_overflow = 0; end - OR: begin - l_r_result = i_w_in1 | i_w_in2; + p_opcode_AND: begin + l_r_result = i_w_in1 & i_w_in2; l_r_carry = 0; l_r_overflow = 0; end - XOR: begin - l_r_result = i_w_in1 ^ i_w_in2; + p_opcode_OR: begin + l_r_result = i_w_in1 | i_w_in2; l_r_carry = 0; l_r_overflow = 0; end - NOT: begin - l_r_result = ~(i_w_in1 | i_w_in2); + p_opcode_XOR: begin + l_r_result = i_w_in1 ^ i_w_in2; l_r_carry = 0; l_r_overflow = 0; end - SHL: begin + + p_opcode_SHL: begin l_r_result = (i_w_in1 << 1) | (i_w_in2 << 1); l_r_carry = i_w_in1[p_data_width-1] | i_w_in2[p_data_width - 1]; l_r_overflow = l_r_result[p_data_width-1] != l_r_carry; end - SHR: begin + p_opcode_SHR: begin l_r_result = (i_w_in1 >> 1) | (i_w_in2 >> 1); l_r_carry = i_w_in1[0] | i_w_in2[0]; l_r_overflow = i_w_in1[p_data_width-1] | i_w_in2[p_data_width-1]; end - SAR: begin + p_opcode_SAR: begin l_r_result = {i_w_in1[p_data_width-1], i_w_in1[p_data_width-1:1]} | {i_w_in2[p_data_width-1], i_w_in2[p_data_width-1:1]}; l_r_carry = i_w_in1[0] | i_w_in2[0]; diff --git a/common/verilog/labcpu/bus.v b/common/verilog/labcpu/bus.v index 159d7fa7..de5e3e91 100644 --- a/common/verilog/labcpu/bus.v +++ b/common/verilog/labcpu/bus.v @@ -1,23 +1,26 @@ -`timescale 1ns / 1ps +`define DEBUG 1 module bus #( parameter p_data_width = 16 ) ( + `ifdef DEBUG + output wire [(p_data_width - 1) : 0] o_w_disp_out, + `endif output wire [(p_data_width - 1) : 0] o_w_bus_to_ram, output wire [(p_data_width - 1) : 0] o_w_bus_to_io, output wire [(p_data_width - 1) : 0] o_w_bus_to_regs, - output wire [(p_data_width - 1) : 0] o_w_bus_to_cp, - output wire [(p_data_width - 1) : 0] o_w_bus_to_ind, - output wire [(p_data_width - 1) : 0] o_w_bus_to_am, - output wire [(p_data_width - 1) : 0] o_w_bus_to_aie, + output wire [(p_data_width - 1) : 0] o_w_bus_to_pc, + output wire [(p_data_width - 1) : 0] o_w_bus_to_flags, + output wire [(p_data_width - 1) : 0] o_w_bus_to_ma, + output wire [(p_data_width - 1) : 0] o_w_bus_to_ioa, output wire [(p_data_width - 1) : 0] o_w_bus_to_t1, output wire [(p_data_width - 1) : 0] o_w_bus_to_t2, - output wire [(p_data_width - 1) : 0] o_w_bus_to_ri, + output wire [(p_data_width - 1) : 0] o_w_bus_to_ir, input wire [(p_data_width - 1) : 0] i_w_alu_to_bus, input wire [(p_data_width - 1) : 0] i_w_ram_to_bus, input wire [(p_data_width - 1) : 0] i_w_io_to_bus, input wire [(p_data_width - 1) : 0] i_w_regs_to_bus, - input wire [(p_data_width - 1) : 0] i_w_cp_to_bus, - input wire [(p_data_width - 1) : 0] i_w_ind_to_bus, + input wire [(p_data_width - 1) : 0] i_w_pc_to_bus, + input wire [(p_data_width - 1) : 0] i_w_flags_to_bus, input wire [(p_data_width - 1) : 0] i_w_offset_to_bus ); @@ -27,19 +30,21 @@ assign l_w_bus = i_w_alu_to_bus | i_w_ram_to_bus | i_w_io_to_bus | i_w_regs_to_bus | - i_w_cp_to_bus | - i_w_ind_to_bus | + i_w_pc_to_bus | + i_w_flags_to_bus | i_w_offset_to_bus; assign o_w_bus_to_ram = l_w_bus; assign o_w_bus_to_io = l_w_bus; assign o_w_bus_to_regs = l_w_bus; -assign o_w_bus_to_cp = l_w_bus; -assign o_w_bus_to_ind = l_w_bus; -assign o_w_bus_to_am = l_w_bus; -assign o_w_bus_to_aie = l_w_bus; +assign o_w_bus_to_pc = l_w_bus; +assign o_w_bus_to_flags = l_w_bus; +assign o_w_bus_to_ma = l_w_bus; +assign o_w_bus_to_ioa = l_w_bus; assign o_w_bus_to_t1 = l_w_bus; assign o_w_bus_to_t2 = l_w_bus; -assign o_w_bus_to_ri = l_w_bus; +assign o_w_bus_to_ir = l_w_bus; + +assign o_w_disp_out = l_w_bus; endmodule diff --git a/common/verilog/labcpu/control_unit.v b/common/verilog/labcpu/control_unit.v new file mode 100644 index 00000000..cf34a7dd --- /dev/null +++ b/common/verilog/labcpu/control_unit.v @@ -0,0 +1,510 @@ +module control_unit #( + parameter p_data_width = 16, + parameter p_opcode_width = 4, + parameter p_opcode_ADC = 4'd0, + parameter p_opcode_SBB1 = 4'd1, + parameter p_opcode_SBB2 = 4'd2, + parameter p_opcode_NOT = 4'd3, + parameter p_opcode_AND = 4'd4, + parameter p_opcode_OR = 4'd5, + parameter p_opcode_XOR = 4'd6, + parameter p_opcode_SHL = 4'd7, + parameter p_opcode_SHR = 4'd8, + parameter p_opcode_SAR = 4'd9, + parameter p_regs_address_width = 3, + parameter p_RA_address = 3'd0, + parameter p_RB_address = 3'd1, + parameter p_RC_address = 3'd2, + parameter p_SP_address = 3'd3, + parameter p_XA_address = 3'd4, + parameter p_XB_address = 3'd5, + parameter p_BA_address = 3'd6, + parameter p_BB_address = 3'd7 +) ( + `ifdef DEBUG + output wire [(p_data_width - 1) : 0] o_w_state_disp_out, + `endif + output reg o_r_alu_oe, + output reg o_r_alu_carry, + output reg [(p_opcode_width-1) : 0] o_r_alu_opcode, + output reg o_r_ram_oe, + output reg o_r_ram_we, + output reg o_r_io_oe, + output reg o_r_io_we, + output reg [(p_regs_address_width-1) : 0] o_r_regs_addr, + output reg o_r_regs_oe, + output reg o_r_regs_we, + output reg o_r_pc_oe, + output reg o_r_pc_we, + output reg o_r_flags_sel, // controls FR register input (0 = bus, 1 = alu flags) + output reg o_r_flags_oe, + output reg o_r_flags_we, + output reg o_r_ma_oe, + output reg o_r_ma_we, + output reg o_r_ioa_oe, + output reg o_r_ioa_we, + output reg o_r_t1_oe, + output reg o_r_t1_we, + output reg o_r_t2_oe, + output reg o_r_t2_we, + output reg o_r_ir_oe, // controls IR register output which generates the offset for Jcond instructions + output reg o_r_ir_we, + input wire i_w_clk, + input wire i_w_reset, + input wire [(p_data_width - 1) : 0] i_w_ir, + input wire [(p_data_width - 1) : 0] i_w_flags +); + +localparam l_p_state_width = 16; + + +wire [0:6] l_w_cop; +wire l_w_d; +wire [0:1] l_w_mod; +wire [0:2] l_w_rg; +wire [0:2] l_w_rm; + +// l_p_state_DECODE instruction +// oeration code +assign l_w_cop = {i_w_ir[0], i_w_ir[1], i_w_ir[2], i_w_ir[3], i_w_ir[4], i_w_ir[5], i_w_ir[6]}; +// direction bit +assign l_w_d = {i_w_ir[7]}; +// addressing mode +assign l_w_mod = {i_w_ir[8], i_w_ir[9]}; +// register +assign l_w_rg = {i_w_ir[10], i_w_ir[11], i_w_ir[12]}; +// register/memory +assign l_w_rm = {i_w_ir[13], i_w_ir[14], i_w_ir[15]}; + +localparam l_p_state_RESET = 16'h00; // l_p_state_RESET state +localparam l_p_state_FETCH = 16'h10; // load instruction to instruction register +localparam l_p_state_DECODE = 16'h20; // analyze loaded instruction +localparam l_p_state_ADDR_SUM = 16'h30; // computes address of the form [By+Xz] with y,z in {A, B} +localparam l_p_state_ADDR_REG = 16'h34; // computes address of the form [yz] with y in {X, B} and z in {A, B} +localparam l_p_state_ADDR_IO = 16'h3c; // computes address of IO port +localparam l_p_state_LOAD_SRC_REG = 16'h40; // load source operand from register +localparam l_p_state_LOAD_SRC_MEM = 16'h44; // load source operand from memory +localparam l_p_state_LOAD_SRC_IO = 16'h4c; // load source operand from IO port +localparam l_p_state_LOAD_DST_REG = 16'h50; // load destination operand from register +localparam l_p_state_LOAD_DST_MEM = 16'h54; // load destination operand from memory +localparam l_p_state_NO_LOAD_DST_REG = 16'h60; // like l_p_state_LOAD_DST_REG but without the loading; equals a nop +localparam l_p_state_NO_LOAD_DST_IO = 16'h6c; // like load_dst_io but without the loading; equals loading of aie +localparam l_p_state_EXEC_ONE_OP = 16'h70; // execute 1 operand instructions +localparam l_p_state_EXEC_TWO_OP = 16'h74; // execute 2 operand instructions +localparam l_p_state_EXEC_TRANSFER = 16'h78; // execute transfer instructions +localparam l_p_state_STORE_REG = 16'h80; // store result to register +localparam l_p_state_STORE_MEM = 16'h84; // store result to memory +localparam l_p_state_STORE_IO = 16'h8c; // store result to IO port +localparam l_p_state_INC_PC = 16'h90; // increment program counter + +reg [(l_p_state_width - 1) : 0] l_r_state = l_p_state_RESET, l_r_state_next; +reg [(l_p_state_width - 1) : 0] l_r_decoded_src, l_r_decoded_src_next; // stores decoded source operand load state +reg [(l_p_state_width - 1) : 0] l_r_decoded_dst, l_r_decoded_dst_next; // stores decoded destination operand load state +reg [(l_p_state_width - 1) : 0] l_r_decoded_exec, l_r_decoded_exec_next; // stores decoded execute state +reg [(l_p_state_width - 1) : 0] l_r_decoded_store, l_r_decoded_store_next; // stores decoded store state +reg l_r_decoded_d, l_r_decoded_d_next; // stores decoded direction bit +reg [0:2] l_r_decoded_rg, l_r_decoded_rg_next; // stores decoded REG operand + +// FSM - sequential part +always @(posedge i_w_clk or negedge i_w_reset) begin + if (!i_w_reset) begin + l_r_state <= l_p_state_RESET; + end else begin + l_r_state <= l_r_state_next; + if(l_r_state == l_p_state_DECODE) begin + l_r_decoded_src <= l_r_decoded_src_next; + l_r_decoded_dst <= l_r_decoded_dst_next; + l_r_decoded_exec <= l_r_decoded_exec_next; + l_r_decoded_store <= l_r_decoded_store_next; + l_r_decoded_d <= l_r_decoded_d_next; + l_r_decoded_rg <= l_r_decoded_rg_next; + end + end +end + +// FSM - combinational part +always @(*) begin + l_r_state_next = l_p_state_RESET; + l_r_decoded_src_next = l_p_state_RESET; + l_r_decoded_dst_next = l_p_state_RESET; + l_r_decoded_exec_next = l_p_state_RESET; + l_r_decoded_store_next = l_p_state_RESET; + l_r_decoded_d_next = 0; + l_r_decoded_rg_next = 0; + o_r_alu_oe = 0; + o_r_alu_carry = 0; + o_r_alu_opcode = 0; + o_r_ram_oe = 0; + o_r_ram_we = 0; + o_r_io_oe = 0; + o_r_io_we = 0; + o_r_regs_addr = 0; + o_r_regs_oe = 0; + o_r_regs_we = 0; + o_r_pc_oe = 0; + o_r_pc_we = 0; + o_r_flags_sel = 0; + o_r_flags_oe = 0; + o_r_flags_we = 0; + o_r_ma_oe = 0; + o_r_ma_we = 0; + o_r_ioa_oe = 0; + o_r_ioa_we = 0; + o_r_t1_oe = 0; + o_r_t1_we = 0; + o_r_t2_oe = 0; + o_r_t2_we = 0; + o_r_ir_oe = 0; + o_r_ir_we = 0; + + case(l_r_state) + l_p_state_RESET: begin + l_r_state_next = l_p_state_FETCH; + end + + l_p_state_FETCH: begin + o_r_pc_oe = 1; + o_r_ma_we = 1; + + l_r_state_next = l_p_state_FETCH + 1; + end + + l_p_state_FETCH + 'd1: begin + o_r_ma_oe = 1; + + l_r_state_next = l_p_state_FETCH + 2; + end + + // TODO: Test if this is correct + // different cycles the memory address is l_p_state_RESET to 0 + l_p_state_FETCH + 'd2: begin + o_r_ram_oe = 1; + o_r_ir_we = 1; + + l_r_state_next = l_p_state_DECODE; + end + + l_p_state_DECODE: begin + // l_p_state_DECODE location of operands and operation + if(l_w_cop[0:3] == 4'b0001) begin // one operand instructions + l_r_decoded_d_next = 0; + l_r_decoded_rg_next = l_w_rg; + l_r_decoded_dst_next = l_w_mod == 2'b11 ? l_p_state_LOAD_DST_REG : l_p_state_LOAD_DST_MEM; + l_r_decoded_src_next = l_r_decoded_dst_next; + l_r_decoded_exec_next = l_p_state_EXEC_ONE_OP; + l_r_decoded_store_next = l_w_mod == 2'b11 ? l_p_state_STORE_REG : l_p_state_STORE_MEM; + end + else if(l_w_cop[0:2] == 3'b010) begin // two operand instructions + l_r_decoded_d_next = l_w_d; + l_r_decoded_rg_next = l_w_rg; + l_r_decoded_dst_next = (l_w_mod == 2'b11) || (l_w_d == 1) ? l_p_state_LOAD_DST_REG : l_p_state_LOAD_DST_MEM; + l_r_decoded_src_next = (l_w_mod == 2'b11) || (l_w_d == 0) ? l_p_state_LOAD_SRC_REG : l_p_state_LOAD_SRC_MEM; + l_r_decoded_exec_next = l_p_state_EXEC_TWO_OP; + l_r_decoded_store_next = !l_w_cop[3] ? l_p_state_INC_PC : ((l_w_mod == 2'b11) || (l_w_d == 1) ? l_p_state_STORE_REG : l_p_state_STORE_MEM); + end + else if(l_w_cop[0:5] == 6'b100000) begin // IO instructions + l_r_decoded_d_next = !l_w_cop[6] ? 1 : 0; + l_r_decoded_rg_next = p_RA_address; + l_r_decoded_dst_next = !l_w_cop[6] ? l_p_state_NO_LOAD_DST_REG : l_p_state_NO_LOAD_DST_IO; + l_r_decoded_src_next = !l_w_cop[6] ? l_p_state_LOAD_SRC_IO : l_p_state_LOAD_SRC_REG; + l_r_decoded_exec_next = l_p_state_EXEC_TRANSFER; + l_r_decoded_store_next = !l_w_cop[6] ? l_p_state_STORE_REG : l_p_state_STORE_IO; + end + + // l_p_state_DECODE address calculation mode + if(l_w_cop[0] == 0) begin + case(l_w_mod) + 2'b00: begin + l_r_state_next = l_w_rm[0] ? l_p_state_ADDR_REG : l_p_state_ADDR_SUM; + end + + 2'b11: begin + l_r_state_next = l_r_decoded_src_next; + end + endcase + end + else begin + if(l_w_cop[0:5] == 6'b100000) begin // IO instructions + l_r_state_next = l_p_state_ADDR_IO; + end + end + end + + l_p_state_ADDR_SUM: begin + o_r_regs_addr = l_w_rm[1] ? p_BB_address : p_BA_address; + o_r_regs_oe = 1; + o_r_t1_we = 1; + + l_r_state_next = l_p_state_ADDR_SUM + 1; + end + + l_p_state_ADDR_SUM + 'd1: begin + o_r_regs_addr = l_w_rm[2] ? p_XB_address : p_XA_address; + o_r_regs_oe = 1; + o_r_t2_we = 1; + + l_r_state_next = l_p_state_ADDR_SUM + 2; + end + + l_p_state_ADDR_SUM + 'd2: begin + o_r_t1_oe = 1; + o_r_t2_oe = 1; + o_r_alu_carry = 0; + o_r_alu_opcode = p_opcode_ADC; + o_r_alu_oe = 1; + if(l_r_decoded_d) + o_r_t2_we = 1; + else + o_r_t1_we = 1; + + l_r_state_next = l_r_decoded_src; + end + + l_p_state_ADDR_REG: begin + o_r_regs_addr = l_w_rm; + o_r_regs_oe = 1; + if(l_r_decoded_d) + o_r_t2_we = 1; + else + o_r_t1_we = 1; + + l_r_state_next = l_r_decoded_src; + end + + l_p_state_ADDR_IO: begin + o_r_ir_oe = 1; + if(l_r_decoded_d) + o_r_t2_we = 1; + else + o_r_t1_we = 1; + + l_r_state_next = l_r_decoded_src; + end + + l_p_state_LOAD_SRC_REG: begin + o_r_regs_addr = l_r_decoded_d ? l_w_rm : l_r_decoded_rg; + o_r_regs_oe = 1; + o_r_t2_we = 1; + + l_r_state_next = l_r_decoded_dst; + end + + l_p_state_LOAD_SRC_MEM: begin + o_r_t1_oe = 0; + o_r_t2_oe = 1; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_ma_we = 1; + + l_r_state_next = l_p_state_LOAD_SRC_MEM + 1; + end + + l_p_state_LOAD_SRC_MEM + 'd1: begin + o_r_ma_oe = 1; + + l_r_state_next = l_p_state_LOAD_SRC_MEM + 2; + end + + l_p_state_LOAD_SRC_MEM + 'd2: begin + o_r_ram_oe = 1; + o_r_t2_we = 1; + + l_r_state_next = l_r_decoded_dst; + end + + l_p_state_LOAD_SRC_IO: begin + o_r_t1_oe = 0; + o_r_t2_oe = 1; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_ioa_we = 1; + + l_r_state_next = l_p_state_LOAD_SRC_IO + 1; + end + + l_p_state_LOAD_SRC_IO + 'd1: begin + o_r_ioa_oe = 1; + o_r_io_oe = 1; + o_r_t2_we = 1; + + l_r_state_next = l_r_decoded_dst; + end + + l_p_state_LOAD_DST_REG: begin + o_r_regs_addr = l_r_decoded_d ? l_r_decoded_rg : l_w_rm; + o_r_regs_oe = 1; + o_r_t1_we = 1; + + l_r_state_next = l_r_decoded_exec; + end + + l_p_state_LOAD_DST_MEM: begin + o_r_t1_oe = 1; + o_r_t2_oe = 0; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_ma_we = 1; + + l_r_state_next = l_p_state_LOAD_DST_MEM + 1; + end + + l_p_state_LOAD_DST_MEM + 'd1: begin + o_r_ma_oe = 1; + + l_r_state_next = l_p_state_LOAD_DST_MEM + 2; + end + + l_p_state_LOAD_DST_MEM + 'd2: begin + o_r_ram_oe = 1; + o_r_t1_we = 1; + + l_r_state_next = l_r_decoded_exec; + end + + l_p_state_NO_LOAD_DST_REG: begin + l_r_state_next = l_r_decoded_exec; + end + + l_p_state_NO_LOAD_DST_IO: begin + o_r_t1_oe = 1; + o_r_t2_oe = 0; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_ioa_we = 1; + + l_r_state_next = l_r_decoded_exec; + end + + l_p_state_EXEC_ONE_OP: begin + o_r_t1_oe = 1; + case(l_w_cop[4:6]) + 3'b000: begin // INC + o_r_alu_carry = 1; + o_r_alu_opcode = p_opcode_ADC; + end + 3'b001: begin // DEC + o_r_alu_carry = 1; + o_r_alu_opcode = p_opcode_SBB1; + end + 3'b010: begin // NEG + o_r_alu_carry = 0; + o_r_alu_opcode = p_opcode_SBB2; + end + 3'b011: begin // NOT + o_r_alu_opcode = p_opcode_NOT; + end + 3'b100: o_r_alu_opcode = p_opcode_SHL; // SHL/SAL + 3'b101: o_r_alu_opcode = p_opcode_SHR; // SHR + 3'b110: o_r_alu_opcode = p_opcode_SAR; // SAR + endcase + o_r_alu_oe = 1; + o_r_t1_we = 1; + o_r_flags_sel = 1; + o_r_flags_we = 1; + + l_r_state_next = l_r_decoded_store; + end + + l_p_state_EXEC_TWO_OP: begin + o_r_t1_oe = 1; + o_r_t2_oe = 1; + case(l_w_cop[4:6]) + 3'b000: begin // ADD + o_r_alu_carry = 0; + o_r_alu_opcode = p_opcode_ADC; + end + 3'b001: begin // ADC + o_r_alu_carry = i_w_flags[0]; + o_r_alu_opcode = p_opcode_ADC; + end + 3'b010: begin // SUB/CMP + o_r_alu_carry = 0; + o_r_alu_opcode = p_opcode_SBB1; + end + 3'b011: begin // SBB + o_r_alu_carry = i_w_flags[0]; + o_r_alu_opcode = p_opcode_SBB1; + end + 3'b100: o_r_alu_opcode = p_opcode_AND; // AND/TEST + 3'b101: o_r_alu_opcode = p_opcode_OR; // OR + 3'b110: o_r_alu_opcode = p_opcode_XOR; // XOR + endcase + o_r_alu_oe = 1; + o_r_t1_we = 1; + o_r_flags_sel = 1; + o_r_flags_we = 1; + + l_r_state_next = l_r_decoded_store; + end + + l_p_state_EXEC_TRANSFER: begin + o_r_t1_oe = 0; + o_r_t2_oe = 1; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_t1_we = 1; + + l_r_state_next = l_r_decoded_store; + end + + l_p_state_STORE_REG: begin + o_r_t1_oe = 1; + o_r_t2_oe = 0; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_regs_addr = l_r_decoded_d ? l_r_decoded_rg : l_w_rm; + o_r_regs_we = 1; + + l_r_state_next = l_p_state_INC_PC; + end + + l_p_state_STORE_MEM: begin + o_r_t1_oe = 1; + o_r_t2_oe = 0; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_ma_oe = 1; + o_r_ram_we = 1; + + l_r_state_next = l_p_state_STORE_MEM + 1; + end + + l_p_state_STORE_MEM + 'd1: begin + l_r_state_next = l_p_state_INC_PC; + end + + l_p_state_STORE_IO: begin + o_r_t1_oe = 1; + o_r_t2_oe = 0; + o_r_alu_opcode = p_opcode_OR; + o_r_alu_oe = 1; + o_r_ioa_oe = 1; + o_r_io_we = 1; + + l_r_state_next = l_p_state_INC_PC; + end + + l_p_state_INC_PC: begin + o_r_pc_oe = 1; + o_r_t1_we = 1; + + l_r_state_next = l_p_state_INC_PC + 1; + end + + l_p_state_INC_PC + 'd1: begin + o_r_t1_oe = 1; + o_r_pc_we = 1; + o_r_alu_oe = 1; + o_r_alu_carry = 1; + o_r_alu_opcode = p_opcode_ADC; + + l_r_state_next = l_p_state_FETCH; + end + + default: l_r_state_next = l_p_state_RESET; + endcase +end + +assign o_w_state_disp_out = l_r_state; + +endmodule diff --git a/common/verilog/labcpu/cpu.v b/common/verilog/labcpu/cpu.v index 4b778252..398602b3 100644 --- a/common/verilog/labcpu/cpu.v +++ b/common/verilog/labcpu/cpu.v @@ -1,11 +1,22 @@ -`timescale 1ns / 1ps +`define DEBUG 1 module cpu #( parameter p_data_width = 16, parameter p_address_width = 10, - parameter p_port_width = 8 -)( + parameter p_port_width = 8, + parameter p_regs_address_width = 3 +) ( + `ifdef DEBUG + output wire [(p_data_width - 1) : 0] o_w_regs_disp_out, + input wire [p_regs_address_width : 0] i_w_regs_disp_addr, + output wire [(p_data_width - 1) : 0] o_w_ram_disp_out, + input wire [(p_address_width - 1) : 0] i_w_ram_disp_addr, + output wire [(p_data_width - 1) : 0] o_w_state_disp_out, + output wire [(p_data_width - 1) : 0] o_w_bus_disp_out, + `endif input wire i_w_clk, + input wire i_w_ram_clk, input wire i_w_reset, + // IO port input wire [(p_data_width - 1) : 0] i_w_io_out, output wire o_w_io_oe, output wire o_w_io_we, @@ -13,255 +24,403 @@ module cpu #( output wire [(p_data_width - 1) : 0] o_w_io_in ); - // instantiate CP register and related connections - wire l_w_cp_oe; - wire l_w_cp_we; - wire[(p_data_width - 1) : 0] l_w_cp_in; - wire[(p_data_width - 1) : 0] l_w_cp_out; + // GENERAL PURPOSE REGISTERS + // General purpose registers + wire l_w_regs_oe; + wire l_w_regs_we; + wire[(p_regs_address_width-1) : 0] l_w_regs_addr; + wire[(p_data_width - 1) : 0] l_w_regs_in; + wire[(p_data_width - 1) : 0] l_w_regs_out; + + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_regs_disp_out; + wire[(p_regs_address_width-1) : 0] l_w_regs_disp_addr; + + /* + MSB of i_w_regs_disp_addr is used to select beetween + general purpose registers (0) and special registers (1) + */ + assign l_w_regs_disp_addr = i_w_regs_disp_addr[(p_regs_address_width-1) : 1]; + `endif + + regfile #( + .p_data_width(p_data_width), + .p_address_width(p_regs_address_width) + ) l_m_regfile ( + `ifdef DEBUG + .o_w_disp_out(l_w_regs_disp_out), + .i_w_disp_reg(l_w_regs_disp_addr), + `endif + .o_w_out(l_w_regs_out), + .i_w_in(l_w_regs_in), + .i_w_reg(l_w_regs_addr), + .i_w_we(l_w_regs_we), + .i_w_oe(l_w_regs_oe), + .i_w_reset(i_w_reset), + .i_w_clk(i_w_clk) + ); + + // SPECIAL PURPOSE REGISTERS + + // instantiate PC register and related connections + wire l_w_pc_oe; + wire l_w_pc_we; + wire[(p_data_width - 1) : 0] l_w_pc_in; + wire[(p_data_width - 1) : 0] l_w_pc_out; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_pc_disp_out; + `endif register #( .p_data_width(p_data_width) - ) l_m_register_cp( - .o_w_out(l_w_cp_out), + ) l_m_register_program_counter ( + `ifdef DEBUG + .o_w_disp_out(l_w_pc_disp_out), + `endif + .o_w_out(l_w_pc_out), + .i_w_in(l_w_pc_in), .i_w_clk(i_w_clk), .i_w_reset(i_w_reset), - .i_w_in(l_w_cp_in), - .i_w_we(l_w_cp_we), - .i_w_oe(l_w_cp_oe) + .i_w_we(l_w_pc_we), + .i_w_oe(l_w_pc_oe) ); - // instantiate IND register and related connections - wire l_w_ind_oe; - wire l_w_ind_we; - wire[(p_data_width - 1) : 0] l_w_ind_in; - wire[(p_data_width - 1) : 0] l_w_ind_out; - wire[(p_data_width - 1) : 0] l_w_ind_disp_out; + + + // instantiate IR register and related connections + wire l_w_ir_oe; + wire l_w_ir_we; + wire[(p_data_width - 1) : 0] l_w_ir_in; + wire[(p_data_width - 1) : 0] l_w_ir_out; + wire[(p_data_width - 1) : 0] l_w_ir_internal; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_ir_disp_out; + `endif register #( .p_data_width(p_data_width) - ) l_m_register_ind( - .o_w_out(l_w_ind_out), - .o_w_disp_out(l_w_ind_disp_out), + ) l_m_register_instruction_register ( + `ifdef DEBUG + .o_w_disp_out(l_w_ir_disp_out), + `endif + .o_w_out(l_w_ir_internal), .i_w_clk(i_w_clk), .i_w_reset(i_w_reset), - .i_w_in(l_w_ind_in), - .i_w_we(l_w_ind_we), - .i_w_oe(l_w_ind_oe) + .i_w_in(l_w_ir_in), + .i_w_we(l_w_ir_we), + .i_w_oe(1'b1) ); + // IR always output the internal value to the control unit + // for mag will be a different signal + assign l_w_ir_out = (l_w_ir_oe) ? l_w_ir_internal : {p_data_width{1'b0}}; -// instantiate AM register and related connections -wire l_w_am_oe; -wire l_w_am_we; -wire[(p_data_width - 1) : 0] l_w_am_in; -wire[(p_data_width - 1) : 0] l_w_am_out; -register #( - .p_data_width(p_data_width) -) l_m_register_am( - .o_w_out(l_w_am_out), - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_in(l_w_am_in), - .i_w_we(l_w_am_we), - .i_w_oe(l_w_am_oe) -); + // instantiate FR register and related connections + wire l_w_flags_oe; + wire l_w_flags_we; + wire[(p_data_width - 1) : 0] l_w_flags_in; + wire[(p_data_width - 1) : 0] l_w_flags_out; + wire[(p_data_width - 1) : 0] l_w_flags_internal; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_flags_disp_out; + `endif + register #( + .p_data_width(p_data_width) + ) l_m_register_flags ( + `ifdef DEBUG + .o_w_disp_out(l_w_flags_disp_out), + `endif + .o_w_out(l_w_flags_internal), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_in(l_w_flags_in), + .i_w_we(l_w_flags_we), + .i_w_oe(1'b1) + ); + // FLAGS always output the internal value to the control unit + // for mag will be a different signal + assign l_w_flags_out = (l_w_flags_oe) ? l_w_flags_internal : {p_data_width{1'b0}}; -// instantiate AIE register and related connections -wire l_w_aie_oe; -wire l_w_aie_we; -wire[(p_data_width - 1) : 0] l_w_aie_in; -wire[(p_data_width - 1) : 0] l_w_aie_out; -register #( - .p_data_width(p_data_width) -) l_m_register_aie( - .o_w_out(l_w_aie_out), - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_in(l_w_aie_in), - .i_w_we(l_w_aie_we), - .i_w_oe(l_w_aie_oe) -); -// instantiate T1 register and related connections -wire l_w_t1_oe; -wire l_w_t1_we; -wire[(p_data_width - 1) : 0] l_w_t1_in; -wire[(p_data_width - 1) : 0] l_w_t1_out; -register #( - .p_data_width(p_data_width) -) l_m_register_t1( - .o_w_out(l_w_t1_out), - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_in(l_w_t1_in), - .i_w_we(l_w_t1_we), - .i_w_oe(l_w_t1_oe) -); -// instantiate T2 register and related connections -wire l_w_t2_oe; -wire l_w_t2_we; -wire[(p_data_width - 1) : 0] l_w_t2_in; -wire[(p_data_width - 1) : 0] l_w_t2_out; -register #( - .p_data_width(p_data_width) -) l_m_register_t2( - .o_w_out(l_w_t2_out), - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_in(l_w_t2_in), - .i_w_we(l_w_t2_we), - .i_w_oe(l_w_t2_oe) -); -// instantiate RI register and related connections -wire l_w_ri_oe; -wire l_w_ri_we; -wire[(p_data_width - 1) : 0] l_w_ri_in; -wire[(p_data_width - 1) : 0] l_w_ri_out; -wire[(p_data_width - 1) : 0] l_w_ri_disp_out; -register #( - .p_data_width(p_data_width) -) l_m_register_ri( - .o_w_out(l_w_ri_out), - .o_w_disp_out(l_w_ri_disp_out), - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_in(l_w_ri_in), - .i_w_we(l_w_ri_we), - .i_w_oe(l_w_ri_oe) -); + // instantiate MA register and related connections + wire l_w_ma_oe; + wire l_w_ma_we; + wire[(p_data_width - 1) : 0] l_w_ma_in; + wire[(p_data_width - 1) : 0] l_w_ma_out; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_ma_disp_out; + `endif + register #( + .p_data_width(p_data_width) + ) l_m_register_memory_address ( + `ifdef DEBUG + .o_w_disp_out(l_w_ma_disp_out), + `endif + .o_w_out(l_w_ma_out), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_in(l_w_ma_in), + .i_w_we(l_w_ma_we), + .i_w_oe(l_w_ma_oe) + ); -// instantiate ALU and related connections -wire[(p_data_width - 1) : 0] l_w_alu_out; -wire[4 : 0] l_w_alu_flags; -wire[3 : 0] l_w_alu_opcode; -wire l_w_alu_carry; -wire l_w_alu_oe; -alu #( - .p_data_width(p_data_width), - .p_flags_width(5) -) l_m_alu( - .o_w_out(l_w_alu_out), - .o_w_flags(l_w_alu_flags), - .i_w_in1(l_w_t1_out), - .i_w_in2(l_w_t2_out), - .i_w_opcode(l_w_alu_opcode), - .i_w_carry(l_w_alu_carry), - .i_w_oe(l_w_alu_oe) -); + // instantiate IOA register and related connections + wire l_w_ioa_oe; + wire l_w_ioa_we; + wire[(p_data_width - 1) : 0] l_w_ioa_in; + wire[(p_data_width - 1) : 0] l_w_ioa_out; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_ioa_disp_out; + `endif + register #( + .p_data_width(p_data_width) + ) l_m_register_input_output_address ( + `ifdef DEBUG + .o_w_disp_out(l_w_ioa_disp_out), + `endif + .o_w_out(l_w_ioa_out), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_in(l_w_ioa_in), + .i_w_we(l_w_ioa_we), + .i_w_oe(l_w_ioa_oe) + ); -// instantiate RAM and related connections -//synthesis attribute box_type ram "black_box" -wire l_w_ram_oe; -wire l_w_ram_we; -wire[(p_data_width - 1) : 0] l_w_ram_in; -wire[(p_data_width - 1) : 0] l_w_ram_out; -cram #( - .p_data_width(p_data_width), - .p_address_width(p_address_width) -) l_m_ram ( - .o_w_out(l_w_ram_out), - .i_w_in(l_w_ram_in), - .i_w_address(l_w_am_out[(p_address_width-1) : 0]), - .i_w_we(l_w_ram_we), - .i_w_oe(l_w_ram_oe), - .i_w_clk(i_w_clk) -); -// it appears ssra does not work correctly in simulation so we need to implement RAM output enable manually -//assign ram_out = ram_oe ? ram_tmp : 0; + // instantiate T1 register and related connections + wire l_w_t1_oe; + wire l_w_t1_we; + wire[(p_data_width - 1) : 0] l_w_t1_in; + wire[(p_data_width - 1) : 0] l_w_t1_out; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_t1_disp_out; + `endif + register #( + .p_data_width(p_data_width) + ) l_m_register_t1 ( + `ifdef DEBUG + .o_w_disp_out(l_w_t1_disp_out), + `endif + .o_w_out(l_w_t1_out), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_in(l_w_t1_in), + .i_w_we(l_w_t1_we), + .i_w_oe(l_w_t1_oe) + ); -// create the custom logic for IO port address output -assign o_w_io_port = l_w_aie_out[(p_port_width - 1) : 0]; + // instantiate T2 register and related connections + wire l_w_t2_oe; + wire l_w_t2_we; + wire[(p_data_width - 1) : 0] l_w_t2_in; + wire[(p_data_width - 1) : 0] l_w_t2_out; + `ifdef DEBUG + wire[(p_data_width - 1) : 0] l_w_t2_disp_out; + `endif + register #( + .p_data_width(p_data_width) + ) l_m_register_t2 ( + `ifdef DEBUG + .o_w_disp_out(l_w_t2_disp_out), + `endif + .o_w_out(l_w_t2_out), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_in(l_w_t2_in), + .i_w_we(l_w_t2_we), + .i_w_oe(l_w_t2_oe) + ); -// instantiate the register file and related connections -wire l_w_regs_oe; -wire l_w_regs_we; -wire[2 : 0] l_w_regs_addr; -wire[(p_data_width - 1) : 0] l_w_regs_in; -wire[(p_data_width - 1) : 0] l_w_regs_out; -registers #( - .p_data_width(p_data_width), - .p_address_width(3) -) l_m_registers ( - .o_w_out(l_w_regs_out), - .i_w_in(l_w_regs_in), - .i_w_address(l_w_regs_addr), - .i_w_we(l_w_regs_we), - .i_w_oe(l_w_regs_oe), - .i_w_clk(i_w_clk) -); + // set the disp registers + `ifdef DEBUG + assign o_w_regs_disp_out = (i_w_regs_disp_addr[p_regs_address_width] == 0) ? l_w_regs_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b000) ? l_w_pc_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b001) ? l_w_flags_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b010) ? l_w_ma_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b011) ? l_w_ioa_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b100) ? l_w_t1_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b101) ? l_w_t2_disp_out : ( + (i_w_regs_disp_addr[(p_regs_address_width-1):0] == 3'b110) ? l_w_ir_disp_out : 0 + ) + ) + ) + ) + ) + ) + ); + `endif -// create the custom logic for IND register input and necessary control signal -wire l_w_ind_sel; -wire[(p_data_width - 1) : 0] l_w_ind_mag; -assign l_w_ind_in = l_w_ind_sel ? l_w_alu_flags : l_w_ind_mag; + // RAM + // instantiate RAM and related connections + // synthesis attribute box_type ram "block RAM" + wire l_w_ram_oe; + wire l_w_ram_we; + wire[(p_data_width - 1) : 0] l_w_ram_in; + wire[(p_data_width - 1) : 0] l_w_ram_out; + cram #( + .p_data_width(p_data_width), + .p_address_width(p_address_width) + ) l_m_ram ( + `ifdef DEBUG + .o_w_disp_out(o_w_ram_disp_out), + .i_w_disp_address(i_w_ram_disp_addr), + `endif + .o_w_out(l_w_ram_out), + .i_w_in(l_w_ram_in), + .i_w_address(l_w_ma_out[(p_address_width-1) : 0]), + .i_w_we(l_w_ram_we), + .i_w_oe(l_w_ram_oe), + .i_w_clk(i_w_clk), + .i_w_ram_clk(i_w_ram_clk) + ); -// create the custom logic for conditional jump offset (RI[8:15]) generation -wire[(p_data_width - 1) : 0] l_w_offset_out; -assign l_w_offset_out = { - {8{l_w_ri_out[8]}}, - l_w_ri_out[8], - l_w_ri_out[9], - l_w_ri_out[10], - l_w_ri_out[11], - l_w_ri_out[12], - l_w_ri_out[13], - l_w_ri_out[14], - l_w_ri_out[15] -}; -// instatiate the bus that connects everything toghether -bus #( - .p_data_width(p_data_width) -) l_m_bus ( - .i_w_alu_to_bus(l_w_alu_out), - .i_w_ram_to_bus(l_w_ram_out), - .i_w_io_to_bus(i_w_io_out), - .i_w_regs_to_bus(l_w_regs_out), - .i_w_cp_to_bus(l_w_cp_out), - .i_w_ind_to_bus(l_w_ind_out), - .i_w_offset_to_bus(l_w_offset_out), - .o_w_bus_to_ram(l_w_ram_in), - .o_w_bus_to_io(o_w_io_in), - .o_w_bus_to_regs(l_w_regs_in), - .o_w_bus_to_cp(l_w_cp_in), - .o_w_bus_to_ind(l_w_ind_in), - .o_w_bus_to_am(l_w_am_in), - .o_w_bus_to_aie(l_w_aie_in), - .o_w_bus_to_t1(l_w_t1_in), - .o_w_bus_to_t2(l_w_t2_in), - .o_w_bus_to_ri(l_w_ri_in) -); + // ALU + // instantiate ALU and related connections + // ALU parameters + parameter l_p_opcode_width = 4; + parameter l_p_opcode_ADC = 4'd0; + parameter l_p_opcode_SBB1 = 4'd1; + parameter l_p_opcode_SBB2 = 4'd2; + parameter l_p_opcode_NOT = 4'd3; + parameter l_p_opcode_AND = 4'd4; + parameter l_p_opcode_OR = 4'd5; + parameter l_p_opcode_XOR = 4'd6; + parameter l_p_opcode_SHL = 4'd7; + parameter l_p_opcode_SHR = 4'd8; + parameter l_p_opcode_SAR = 4'd9; + parameter l_p_flags_width = 5; + // ALU connections + wire[(p_data_width - 1) : 0] l_w_alu_out; + wire[(l_p_flags_width - 1) : 0] l_w_alu_flags; + wire[(l_p_opcode_width - 1) : 0] l_w_alu_opcode; + wire l_w_alu_carry; + wire l_w_alu_oe; + // ALU instantiation + alu #( + .p_data_width(p_data_width), + .p_flags_width(l_p_flags_width), + .p_opcode_width(l_p_opcode_width), + .p_opcode_ADC(l_p_opcode_ADC), + .p_opcode_SBB1(l_p_opcode_SBB1), + .p_opcode_SBB2(l_p_opcode_SBB2), + .p_opcode_NOT(l_p_opcode_NOT), + .p_opcode_AND(l_p_opcode_AND), + .p_opcode_OR(l_p_opcode_OR), + .p_opcode_XOR(l_p_opcode_XOR), + .p_opcode_SHL(l_p_opcode_SHL), + .p_opcode_SHR(l_p_opcode_SHR), + .p_opcode_SAR(l_p_opcode_SAR) + ) l_m_alu ( + .o_w_out(l_w_alu_out), + .o_w_flags(l_w_alu_flags), + .i_w_in1(l_w_t1_out), + .i_w_in2(l_w_t2_out), + .i_w_opcode(l_w_alu_opcode), + .i_w_carry(l_w_alu_carry), + .i_w_oe(l_w_alu_oe) + ); + + + // OTHER CONNECTIONS + + // create the custom logic for IO port address output + assign o_w_io_port = l_w_ioa_out[(p_port_width - 1) : 0]; + + + // create the custom logic for FR register input and necessary control signal + wire l_w_flags_sel; + wire[(p_data_width - 1) : 0] l_w_flags_bus; + // flags register can be written from the bus or from the ALU + assign l_w_flags_in = l_w_flags_sel ? l_w_alu_flags : l_w_flags_bus; + + // create the custom logic for conditional jump offset (RI[8:15]) generation + wire[(p_data_width - 1) : 0] l_w_offset_out; + assign l_w_offset_out = { + {8{l_w_ir_out[8]}}, + l_w_ir_out[8], + l_w_ir_out[9], + l_w_ir_out[10], + l_w_ir_out[11], + l_w_ir_out[12], + l_w_ir_out[13], + l_w_ir_out[14], + l_w_ir_out[15] + }; + + // BUS CONNECTIONS + // instatiate the bus that connects everything toghether + bus #( + .p_data_width(p_data_width) + ) l_m_bus ( + `ifdef DEBUG + .o_w_disp_out(o_w_bus_disp_out), + `endif + .o_w_bus_to_ram(l_w_ram_in), + .o_w_bus_to_io(o_w_io_in), + .o_w_bus_to_regs(l_w_regs_in), + .o_w_bus_to_pc(l_w_pc_in), + .o_w_bus_to_flags(l_w_flags_bus), + .o_w_bus_to_ma(l_w_ma_in), + .o_w_bus_to_ioa(l_w_ioa_in), + .o_w_bus_to_t1(l_w_t1_in), + .o_w_bus_to_t2(l_w_t2_in), + .o_w_bus_to_ir(l_w_ir_in), + .i_w_alu_to_bus(l_w_alu_out), + .i_w_ram_to_bus(l_w_ram_out), + .i_w_io_to_bus(i_w_io_out), + .i_w_regs_to_bus(l_w_regs_out), + .i_w_pc_to_bus(l_w_pc_out), + .i_w_flags_to_bus(l_w_flags_out), + .i_w_offset_to_bus(l_w_offset_out) + ); + + // CONTROL UNIT MODULE + control_unit #( + .p_data_width(p_data_width), + .p_opcode_width(l_p_opcode_width), + .p_opcode_ADC(l_p_opcode_ADC), + .p_opcode_SBB1(l_p_opcode_SBB1), + .p_opcode_SBB2(l_p_opcode_SBB2), + .p_opcode_NOT(l_p_opcode_NOT), + .p_opcode_AND(l_p_opcode_AND), + .p_opcode_OR(l_p_opcode_OR), + .p_opcode_XOR(l_p_opcode_XOR), + .p_opcode_SHL(l_p_opcode_SHL), + .p_opcode_SHR(l_p_opcode_SHR), + .p_opcode_SAR(l_p_opcode_SAR), + .p_regs_address_width(p_regs_address_width) + ) l_m_cu ( + `ifdef DEBUG + .o_w_state_disp_out(o_w_state_disp_out), + `endif + .o_r_alu_oe(l_w_alu_oe), + .o_r_alu_carry(l_w_alu_carry), + .o_r_alu_opcode(l_w_alu_opcode), + .o_r_ram_oe(l_w_ram_oe), + .o_r_ram_we(l_w_ram_we), + .o_r_io_oe(o_w_io_oe), + .o_r_io_we(o_w_io_we), + .o_r_regs_addr(l_w_regs_addr), + .o_r_regs_oe(l_w_regs_oe), + .o_r_regs_we(l_w_regs_we), + .o_r_pc_oe(l_w_pc_oe), + .o_r_pc_we(l_w_pc_we), + .o_r_flags_sel(l_w_flags_sel), // controls FR register input (0 = bus, 1 = alu flags) + .o_r_flags_oe(l_w_flags_oe), + .o_r_flags_we(l_w_flags_we), + .o_r_ma_oe(l_w_ma_oe), + .o_r_ma_we(l_w_ma_we), + .o_r_ioa_oe(l_w_ioa_oe), + .o_r_ioa_we(l_w_ioa_we), + .o_r_t1_oe(l_w_t1_oe), + .o_r_t1_we(l_w_t1_we), + .o_r_t2_oe(l_w_t2_oe), + .o_r_t2_we(l_w_t2_we), + .o_r_ir_oe(l_w_ir_oe), // controls IR register output which generates the offset for Jcond instructions + .o_r_ir_we(l_w_ir_we), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_ir(l_w_ir_internal), + .i_w_flags(l_w_flags_internal) + ); + -// instantiate command unit -uc #( - .p_data_width(p_data_width) -) l_m_uc ( - .o_r_alu_oe(l_w_alu_oe), - .o_r_alu_carry(l_w_alu_carry), - .o_r_alu_opcode(l_w_alu_opcode), - .o_r_ram_oe(l_w_ram_oe), - .o_r_ram_we(l_w_ram_we), - .o_r_io_oe(o_w_io_oe), - .o_r_io_we(o_w_io_we), - .o_r_regs_addr(l_w_regs_addr), - .o_r_regs_oe(l_w_regs_oe), - .o_r_regs_we(l_w_regs_we), - .o_r_cp_oe(l_w_cp_oe), - .o_r_cp_we(l_w_cp_we), - .o_r_ind_sel(l_w_ind_sel), // controls IND register input (0 = bus, 1 = alu flags) - .o_r_ind_oe(l_w_ind_oe), - .o_r_ind_we(l_w_ind_we), - .o_r_am_oe(l_w_am_oe), - .o_r_am_we(l_w_am_we), - .o_r_aie_oe(l_w_aie_oe), - .o_r_aie_we(l_w_aie_we), - .o_r_t1_oe(l_w_t1_oe), - .o_r_t1_we(l_w_t1_we), - .o_r_t2_oe(l_w_t2_oe), - .o_r_t2_we(l_w_t2_we), - .o_r_ri_oe(l_w_ri_oe), // controls RI register output which generates the offset for Jcond instructions - .o_r_ri_we(l_w_ri_we), - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_ri(l_w_ri_disp_out), - .i_w_ind(l_w_ind_disp_out) -); endmodule diff --git a/common/verilog/labcpu/cpu_debugger.v b/common/verilog/labcpu/cpu_debugger.v new file mode 100644 index 00000000..67b6fcd6 --- /dev/null +++ b/common/verilog/labcpu/cpu_debugger.v @@ -0,0 +1,116 @@ +`define DEBUG 1 +module cpu_debugger #( + parameter p_data_width = 16, + parameter p_address_width = 10, + parameter p_regs_address_width = 3, + parameter p_no_cycles = 1000000, // number of cycles for debouncing + parameter p_divisor = 104167 // 104167 for 480 Hz ( 60Hz * 8 digits), 50% duty cycle +) ( + output wire [7:0] o_w_7_led_seg, + output wire [7:0] o_w_an, + output wire o_w_sim_clk, + input wire [(p_address_width-1):0] i_w_in, + input wire i_w_next, + input wire i_w_prev, + input wire i_w_clk, // the main clock + input wire i_w_debug_clk, // the debug clock on a switch (for debugging) + input wire i_w_reset +); + + // CPU + wire [(p_data_width - 1) : 0] l_w_cpu_regs_out; + wire [(p_data_width - 1) : 0] l_w_cpu_ram; + wire [(p_data_width - 1) : 0] l_w_cpu_state; + wire [(p_data_width - 1) : 0] l_w_cpu_bus; + wire [p_regs_address_width : 0] l_w_cpu_regs_addr; + assign l_w_cpu_regs_addr = i_w_in[p_regs_address_width : 0]; + wire [(p_address_width - 1) : 0] l_w_cpu_ram_addr; + assign l_w_cpu_ram_addr = i_w_in[(p_address_width - 1) : 0]; + + cpu #( + .p_data_width(p_data_width), + .p_address_width(p_address_width), + .p_regs_address_width(p_regs_address_width) + ) l_m_cpu ( + .o_w_regs_disp_out(l_w_cpu_regs_out), + .o_w_ram_disp_out(l_w_cpu_ram), + .o_w_state_disp_out(l_w_cpu_state), + .o_w_bus_disp_out(l_w_cpu_bus), + .i_w_regs_disp_addr(l_w_cpu_regs_addr), + .i_w_ram_disp_addr(l_w_cpu_ram_addr), + .i_w_clk(i_w_debug_clk), + .i_w_ram_clk(i_w_clk), + .i_w_reset(i_w_reset), + .i_w_io_out(16'h0) + ); + + // 7 seg display for state + + // The clock divider + wire l_w_480HZ_clk; + assign o_w_sim_clk = l_w_480HZ_clk; + + clock_divider #( + .p_divisor(p_divisor) + ) l_m_clk_divider ( + .o_w_clk(l_w_480HZ_clk), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset) + ); + // Debounce the next and prev buttons + wire l_w_next_debounced; + wire l_w_prev_debounced; + + debouncer #( + .p_no_cycles(p_no_cycles) + ) l_m_debouncer_next ( + .o_w_out(l_w_next_debounced), + .i_w_in(i_w_next), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset) + ); + + debouncer #( + .p_no_cycles(p_no_cycles) + ) l_m_debouncer_prev ( + .o_w_out(l_w_prev_debounced), + .i_w_in(i_w_prev), + .i_w_clk(i_w_clk), + .i_w_reset(i_w_reset) + ); + + // make to register just one button pressed per cycle + wire l_w_next_action; + wire l_w_prev_action; + + otp_button l_m_opt_button_next ( + .o_w_button_press(l_w_next_action), + .i_w_clk(l_w_480HZ_clk), + .i_w_button(l_w_next_debounced) + ); + otp_button l_m_opt_button_prev ( + .o_w_button_press(l_w_prev_action), + .i_w_clk(l_w_480HZ_clk), + .i_w_button(l_w_prev_debounced) + ); + + // 7 seg display for state + state_display #( + .p_data_width(p_data_width), + .p_address_width(p_address_width), + .p_regs_address_width(p_regs_address_width) + ) l_m_state_display ( + .o_w_7_led_seg(o_w_7_led_seg), + .o_w_an(o_w_an), + .i_w_regs_addr(l_w_cpu_regs_addr), + .i_w_regs(l_w_cpu_regs_out), + .i_w_ram(l_w_cpu_ram), + .i_w_state(l_w_cpu_state), + .i_w_bus(l_w_cpu_bus), + .i_w_next(l_w_next_action), + .i_w_prev(l_w_prev_action), + .i_w_clk(l_w_480HZ_clk), + .i_w_reset(i_w_reset) + ); + +endmodule \ No newline at end of file diff --git a/common/verilog/labcpu/cpu_debugger.vvp b/common/verilog/labcpu/cpu_debugger.vvp new file mode 100755 index 00000000..97d436b2 --- /dev/null +++ b/common/verilog/labcpu/cpu_debugger.vvp @@ -0,0 +1,4622 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x584af5d2b7d0 .scope module, "block_ram" "block_ram" 2 2; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "o_r_out"; + .port_info 1 /INPUT 8 "i_w_in"; + .port_info 2 /INPUT 20 "i_w_address"; + .port_info 3 /INPUT 1 "i_w_we"; + .port_info 4 /INPUT 1 "i_w_cs"; + .port_info 5 /INPUT 1 "i_w_clk"; +P_0x584af5cfada0 .param/l "l_p_depth" 1 2 14, +C4<00000000000100000000000000000000>; +P_0x584af5cfade0 .param/l "p_address_width" 0 2 4, +C4<00000000000000000000000000010100>; +P_0x584af5cfae20 .param/l "p_data_width" 0 2 3, +C4<00000000000000000000000000001000>; +o0x795a1e256018 .functor BUFZ 20, C4; HiZ drive +v0x584af5cb3a40_0 .net "i_w_address", 19 0, o0x795a1e256018; 0 drivers +o0x795a1e256048 .functor BUFZ 1, C4; HiZ drive +v0x584af5cb7a90_0 .net "i_w_clk", 0 0, o0x795a1e256048; 0 drivers +o0x795a1e256078 .functor BUFZ 1, C4; HiZ drive +v0x584af5cb5780_0 .net "i_w_cs", 0 0, o0x795a1e256078; 0 drivers +o0x795a1e2560a8 .functor BUFZ 8, C4; HiZ drive +v0x584af5cb7d70_0 .net "i_w_in", 7 0, o0x795a1e2560a8; 0 drivers +o0x795a1e2560d8 .functor BUFZ 1, C4; HiZ drive +v0x584af5cb5a10_0 .net "i_w_we", 0 0, o0x795a1e2560d8; 0 drivers +v0x584af5bc6cd0 .array "l_r_data", 0 1048575, 7 0; +v0x584af5d46010_0 .var "o_r_out", 7 0; +E_0x584af5bb1e10 .event posedge, v0x584af5cb7a90_0; +S_0x584af5cbe910 .scope module, "test_cpu_debugger" "test_cpu_debugger" 3 1; + .timescale 0 0; +P_0x584af5cb5050 .param/l "p_address_width" 0 3 5, +C4<00000000000000000000000000001010>; +P_0x584af5cb5090 .param/l "p_data_width" 0 3 4, +C4<00000000000000000000000000010000>; +P_0x584af5cb50d0 .param/l "p_regs_address_width" 0 3 6, +C4<00000000000000000000000000000011>; +v0x584af5d67db0_0 .var "i_w_clk", 0 0; +v0x584af5d67e70_0 .var "i_w_debug_clk", 0 0; +v0x584af5d67f30_0 .var "i_w_in", 9 0; +v0x584af5d67fd0_0 .var "i_w_next", 0 0; +v0x584af5d68070_0 .var "i_w_prev", 0 0; +v0x584af5d681b0_0 .var "i_w_reset", 0 0; +v0x584af5d68250_0 .net "o_w_7_led_seg", 7 0, L_0x584af5d80910; 1 drivers +v0x584af5d68340_0 .net "o_w_an", 7 0, L_0x584af5d80620; 1 drivers +v0x584af5d68430_0 .net "o_w_sim_clk", 0 0, L_0x584af5d800d0; 1 drivers +S_0x584af5cb28a0 .scope module, "uut" "cpu_debugger" 3 29, 4 2 0, S_0x584af5cbe910; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "o_w_7_led_seg"; + .port_info 1 /OUTPUT 8 "o_w_an"; + .port_info 2 /OUTPUT 1 "o_w_sim_clk"; + .port_info 3 /INPUT 10 "i_w_in"; + .port_info 4 /INPUT 1 "i_w_next"; + .port_info 5 /INPUT 1 "i_w_prev"; + .port_info 6 /INPUT 1 "i_w_clk"; + .port_info 7 /INPUT 1 "i_w_debug_clk"; + .port_info 8 /INPUT 1 "i_w_reset"; +P_0x584af5d461d0 .param/l "p_address_width" 0 4 4, +C4<00000000000000000000000000001010>; +P_0x584af5d46210 .param/l "p_data_width" 0 4 3, +C4<00000000000000000000000000010000>; +P_0x584af5d46250 .param/l "p_divisor" 0 4 7, +C4<00000000000000000000000000000100>; +P_0x584af5d46290 .param/l "p_no_cycles" 0 4 6, +C4<00000000000000000000000000000001>; +P_0x584af5d462d0 .param/l "p_regs_address_width" 0 4 5, +C4<00000000000000000000000000000011>; +L_0x584af5cb6500 .functor BUFZ 10, v0x584af5d67f30_0, C4<0000000000>, C4<0000000000>, C4<0000000000>; +L_0x584af5d800d0 .functor BUFZ 1, v0x584af5d469e0_0, C4<0>, C4<0>, C4<0>; +v0x584af5d66b10_0 .net "i_w_clk", 0 0, v0x584af5d67db0_0; 1 drivers +v0x584af5d66bd0_0 .net "i_w_debug_clk", 0 0, v0x584af5d67e70_0; 1 drivers +v0x584af5d66c90_0 .net "i_w_in", 9 0, v0x584af5d67f30_0; 1 drivers +v0x584af5d66d60_0 .net "i_w_next", 0 0, v0x584af5d67fd0_0; 1 drivers +v0x584af5d66e30_0 .net "i_w_prev", 0 0, v0x584af5d68070_0; 1 drivers +v0x584af5d66f20_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; 1 drivers +v0x584af5d66fc0_0 .net "l_w_480HZ_clk", 0 0, v0x584af5d469e0_0; 1 drivers +v0x584af5d67060_0 .net "l_w_cpu_bus", 15 0, L_0x584af5d7eac0; 1 drivers +v0x584af5d67100_0 .net "l_w_cpu_ram", 15 0, v0x584af5d51950_0; 1 drivers +v0x584af5d672c0_0 .net "l_w_cpu_ram_addr", 9 0, L_0x584af5cb6500; 1 drivers +v0x584af5d67380_0 .net "l_w_cpu_regs_addr", 3 0, L_0x584af5d684d0; 1 drivers +v0x584af5d67440_0 .net "l_w_cpu_regs_out", 15 0, L_0x584af5d7be70; 1 drivers +v0x584af5d67500_0 .net "l_w_cpu_state", 15 0, L_0x584af5d7f6d0; 1 drivers +v0x584af5d675c0_0 .net "l_w_next_action", 0 0, L_0x584af5d80140; 1 drivers +v0x584af5d67660_0 .net "l_w_next_debounced", 0 0, v0x584af5d60340_0; 1 drivers +v0x584af5d67750_0 .net "l_w_prev_action", 0 0, L_0x584af5d80440; 1 drivers +v0x584af5d67840_0 .net "l_w_prev_debounced", 0 0, v0x584af5d60b00_0; 1 drivers +v0x584af5d67a40_0 .net "o_w_7_led_seg", 7 0, L_0x584af5d80910; alias, 1 drivers +v0x584af5d67b00_0 .net "o_w_an", 7 0, L_0x584af5d80620; alias, 1 drivers +v0x584af5d67ba0_0 .net "o_w_sim_clk", 0 0, L_0x584af5d800d0; alias, 1 drivers +L_0x584af5d684d0 .part v0x584af5d67f30_0, 0, 4; +S_0x584af5cb8140 .scope module, "l_m_clk_divider" "clock_divider" 4 55, 5 1 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "o_w_clk"; + .port_info 1 /INPUT 1 "i_w_clk"; + .port_info 2 /INPUT 1 "i_w_reset"; +P_0x584af5cb75e0 .param/l "l_p_counter_width" 1 5 10, +C4<000000000000000000000000000000011>; +P_0x584af5cb7620 .param/l "p_divisor" 0 5 2, +C4<00000000000000000000000000000100>; +v0x584af5d46750_0 .var "counter", 3 0; +v0x584af5d46850_0 .net "i_w_clk", 0 0, v0x584af5d67db0_0; alias, 1 drivers +v0x584af5d46910_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d469e0_0 .var "o_w_clk", 0 0; +E_0x584af5bb23a0/0 .event negedge, v0x584af5d46910_0; +E_0x584af5bb23a0/1 .event posedge, v0x584af5d46850_0; +E_0x584af5bb23a0 .event/or E_0x584af5bb23a0/0, E_0x584af5bb23a0/1; +S_0x584af5cbbb70 .scope module, "l_m_cpu" "cpu" 4 34, 6 2 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_regs_disp_out"; + .port_info 1 /INPUT 4 "i_w_regs_disp_addr"; + .port_info 2 /OUTPUT 16 "o_w_ram_disp_out"; + .port_info 3 /INPUT 10 "i_w_ram_disp_addr"; + .port_info 4 /OUTPUT 16 "o_w_state_disp_out"; + .port_info 5 /OUTPUT 16 "o_w_bus_disp_out"; + .port_info 6 /INPUT 1 "i_w_clk"; + .port_info 7 /INPUT 1 "i_w_ram_clk"; + .port_info 8 /INPUT 1 "i_w_reset"; + .port_info 9 /INPUT 16 "i_w_io_out"; + .port_info 10 /OUTPUT 1 "o_w_io_oe"; + .port_info 11 /OUTPUT 1 "o_w_io_we"; + .port_info 12 /OUTPUT 8 "o_w_io_port"; + .port_info 13 /OUTPUT 16 "o_w_io_in"; +P_0x584af5d46b70 .param/l "l_p_flags_width" 0 6 289, +C4<00000000000000000000000000000101>; +P_0x584af5d46bb0 .param/l "l_p_opcode_ADC" 0 6 279, C4<0000>; +P_0x584af5d46bf0 .param/l "l_p_opcode_AND" 0 6 283, C4<0100>; +P_0x584af5d46c30 .param/l "l_p_opcode_NOT" 0 6 282, C4<0011>; +P_0x584af5d46c70 .param/l "l_p_opcode_OR" 0 6 284, C4<0101>; +P_0x584af5d46cb0 .param/l "l_p_opcode_SAR" 0 6 288, C4<1001>; +P_0x584af5d46cf0 .param/l "l_p_opcode_SBB1" 0 6 280, C4<0001>; +P_0x584af5d46d30 .param/l "l_p_opcode_SBB2" 0 6 281, C4<0010>; +P_0x584af5d46d70 .param/l "l_p_opcode_SHL" 0 6 286, C4<0111>; +P_0x584af5d46db0 .param/l "l_p_opcode_SHR" 0 6 287, C4<1000>; +P_0x584af5d46df0 .param/l "l_p_opcode_XOR" 0 6 285, C4<0110>; +P_0x584af5d46e30 .param/l "l_p_opcode_width" 0 6 278, +C4<00000000000000000000000000000100>; +P_0x584af5d46e70 .param/l "p_address_width" 0 6 4, +C4<00000000000000000000000000001010>; +P_0x584af5d46eb0 .param/l "p_data_width" 0 6 3, +C4<00000000000000000000000000010000>; +P_0x584af5d46ef0 .param/l "p_port_width" 0 6 5, +C4<00000000000000000000000000001000>; +P_0x584af5d46f30 .param/l "p_regs_address_width" 0 6 6, +C4<00000000000000000000000000000011>; +v0x584af5d59150_0 .net *"_ivl_1", 1 0, L_0x584af5d68640; 1 drivers +v0x584af5d59250_0 .net *"_ivl_100", 7 0, L_0x584af5d7cd70; 1 drivers +v0x584af5d59330_0 .net *"_ivl_103", 0 0, L_0x584af5d7ceb0; 1 drivers +v0x584af5d59420_0 .net *"_ivl_105", 0 0, L_0x584af5d7cc50; 1 drivers +v0x584af5d59500_0 .net *"_ivl_107", 0 0, L_0x584af5d7d080; 1 drivers +v0x584af5d595e0_0 .net *"_ivl_109", 0 0, L_0x584af5d7d260; 1 drivers +v0x584af5d596c0_0 .net *"_ivl_111", 0 0, L_0x584af5d7d300; 1 drivers +v0x584af5d597a0_0 .net *"_ivl_113", 0 0, L_0x584af5d7d4f0; 1 drivers +v0x584af5d59880_0 .net *"_ivl_115", 0 0, L_0x584af5d7d6a0; 1 drivers +v0x584af5d599f0_0 .net *"_ivl_117", 0 0, L_0x584af5d7d8a0; 1 drivers +L_0x795a1e20d258 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d59ad0_0 .net/2u *"_ivl_14", 15 0, L_0x795a1e20d258; 1 drivers +v0x584af5d59bb0_0 .net *"_ivl_19", 0 0, L_0x584af5d79d20; 1 drivers +v0x584af5d59c90_0 .net *"_ivl_20", 31 0, L_0x584af5d79dc0; 1 drivers +L_0x795a1e20d3c0 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d59d70_0 .net *"_ivl_23", 30 0, L_0x795a1e20d3c0; 1 drivers +L_0x795a1e20d408 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d59e50_0 .net/2u *"_ivl_24", 31 0, L_0x795a1e20d408; 1 drivers +v0x584af5d59f30_0 .net *"_ivl_26", 0 0, L_0x584af5d79f40; 1 drivers +v0x584af5d59ff0_0 .net *"_ivl_29", 2 0, L_0x584af5d7a080; 1 drivers +L_0x795a1e20d450 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; +v0x584af5d5a1e0_0 .net/2u *"_ivl_30", 2 0, L_0x795a1e20d450; 1 drivers +v0x584af5d5a2c0_0 .net *"_ivl_32", 0 0, L_0x584af5d7a170; 1 drivers +v0x584af5d5a380_0 .net *"_ivl_35", 2 0, L_0x584af5d7a2b0; 1 drivers +L_0x795a1e20d498 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; +v0x584af5d5a460_0 .net/2u *"_ivl_36", 2 0, L_0x795a1e20d498; 1 drivers +v0x584af5d5a540_0 .net *"_ivl_38", 0 0, L_0x584af5d7a4c0; 1 drivers +v0x584af5d5a600_0 .net *"_ivl_41", 2 0, L_0x584af5d7a5b0; 1 drivers +L_0x795a1e20d4e0 .functor BUFT 1, C4<010>, C4<0>, C4<0>, C4<0>; +v0x584af5d5a6e0_0 .net/2u *"_ivl_42", 2 0, L_0x795a1e20d4e0; 1 drivers +v0x584af5d5a7c0_0 .net *"_ivl_44", 0 0, L_0x584af5d7a7d0; 1 drivers +v0x584af5d5a880_0 .net *"_ivl_47", 2 0, L_0x584af5d7a910; 1 drivers +L_0x795a1e20d528 .functor BUFT 1, C4<011>, C4<0>, C4<0>, C4<0>; +v0x584af5d5a960_0 .net/2u *"_ivl_48", 2 0, L_0x795a1e20d528; 1 drivers +L_0x795a1e20d018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +v0x584af5d5aa40_0 .net *"_ivl_5", 0 0, L_0x795a1e20d018; 1 drivers +v0x584af5d5ab20_0 .net *"_ivl_50", 0 0, L_0x584af5d7aa30; 1 drivers +v0x584af5d5abe0_0 .net *"_ivl_53", 2 0, L_0x584af5d7ab70; 1 drivers +L_0x795a1e20d570 .functor BUFT 1, C4<100>, C4<0>, C4<0>, C4<0>; +v0x584af5d5acc0_0 .net/2u *"_ivl_54", 2 0, L_0x795a1e20d570; 1 drivers +v0x584af5d5ada0_0 .net *"_ivl_56", 0 0, L_0x584af5d7aca0; 1 drivers +v0x584af5d5ae60_0 .net *"_ivl_59", 2 0, L_0x584af5d7ade0; 1 drivers +L_0x795a1e20d5b8 .functor BUFT 1, C4<101>, C4<0>, C4<0>, C4<0>; +v0x584af5d5af40_0 .net/2u *"_ivl_60", 2 0, L_0x795a1e20d5b8; 1 drivers +v0x584af5d5b020_0 .net *"_ivl_62", 0 0, L_0x584af5d7af20; 1 drivers +v0x584af5d5b0e0_0 .net *"_ivl_65", 2 0, L_0x584af5d7b060; 1 drivers +L_0x795a1e20d600 .functor BUFT 1, C4<110>, C4<0>, C4<0>, C4<0>; +v0x584af5d5b1c0_0 .net/2u *"_ivl_66", 2 0, L_0x795a1e20d600; 1 drivers +v0x584af5d5b2a0_0 .net *"_ivl_68", 0 0, L_0x584af5d7ae80; 1 drivers +L_0x795a1e20d648 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d5b360_0 .net/2u *"_ivl_70", 15 0, L_0x795a1e20d648; 1 drivers +v0x584af5d5b440_0 .net *"_ivl_72", 15 0, L_0x584af5d7b250; 1 drivers +v0x584af5d5b520_0 .net *"_ivl_74", 15 0, L_0x584af5d7b450; 1 drivers +v0x584af5d5b600_0 .net *"_ivl_76", 15 0, L_0x584af5d7b590; 1 drivers +v0x584af5d5b6e0_0 .net *"_ivl_78", 15 0, L_0x584af5d7b7a0; 1 drivers +L_0x795a1e20d1c8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d5b7c0_0 .net/2u *"_ivl_8", 15 0, L_0x795a1e20d1c8; 1 drivers +v0x584af5d5b8a0_0 .net *"_ivl_80", 15 0, L_0x584af5d7b8e0; 1 drivers +v0x584af5d5b980_0 .net *"_ivl_82", 15 0, L_0x584af5d7bb00; 1 drivers +v0x584af5d5ba60_0 .net *"_ivl_84", 15 0, L_0x584af5d7bc40; 1 drivers +v0x584af5d5bb40_0 .net *"_ivl_92", 15 0, L_0x584af5d7c780; 1 drivers +L_0x795a1e20d840 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d5bc20_0 .net *"_ivl_95", 10 0, L_0x795a1e20d840; 1 drivers +v0x584af5d5bd00_0 .net *"_ivl_99", 0 0, L_0x584af5d7cb60; 1 drivers +v0x584af5d5bde0_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +L_0x795a1e20d888 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d5be80_0 .net "i_w_io_out", 15 0, L_0x795a1e20d888; 1 drivers +v0x584af5d5bf40_0 .net "i_w_ram_clk", 0 0, v0x584af5d67db0_0; alias, 1 drivers +v0x584af5d5bfe0_0 .net "i_w_ram_disp_addr", 9 0, L_0x584af5cb6500; alias, 1 drivers +v0x584af5d5c080_0 .net "i_w_regs_disp_addr", 3 0, L_0x584af5d684d0; alias, 1 drivers +v0x584af5d5c160_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d5c200_0 .net "l_w_alu_carry", 0 0, v0x584af5d4ecd0_0; 1 drivers +v0x584af5d5c2f0_0 .net "l_w_alu_flags", 4 0, L_0x584af5d7c5f0; 1 drivers +v0x584af5d5c3b0_0 .net "l_w_alu_oe", 0 0, v0x584af5d4eda0_0; 1 drivers +v0x584af5d5c4a0_0 .net "l_w_alu_opcode", 3 0, v0x584af5d4ee70_0; 1 drivers +v0x584af5d5c590_0 .net "l_w_alu_out", 15 0, L_0x584af5d7c500; 1 drivers +v0x584af5d5c6a0_0 .net "l_w_flags_bus", 15 0, L_0x584af5d7e600; 1 drivers +v0x584af5d5c760_0 .net "l_w_flags_disp_out", 15 0, L_0x584af5d2b760; 1 drivers +v0x584af5d5c800_0 .net "l_w_flags_in", 15 0, L_0x584af5d7c980; 1 drivers +v0x584af5d5c8a0_0 .net "l_w_flags_internal", 15 0, L_0x584af5d80a90; 1 drivers +v0x584af5d5cda0_0 .net "l_w_flags_oe", 0 0, v0x584af5d4ef40_0; 1 drivers +v0x584af5d5ce40_0 .net "l_w_flags_out", 15 0, L_0x584af5d792a0; 1 drivers +v0x584af5d5cee0_0 .net "l_w_flags_sel", 0 0, v0x584af5d4efe0_0; 1 drivers +v0x584af5d5cfb0_0 .net "l_w_flags_we", 0 0, v0x584af5d4f080_0; 1 drivers +v0x584af5d5d0a0_0 .net "l_w_ioa_disp_out", 15 0, L_0x584af5d79770; 1 drivers +v0x584af5d5d140_0 .net "l_w_ioa_in", 15 0, L_0x584af5d7e750; 1 drivers +v0x584af5d5d230_0 .net "l_w_ioa_oe", 0 0, v0x584af5d4f2c0_0; 1 drivers +v0x584af5d5d320_0 .net "l_w_ioa_out", 15 0, L_0x584af5d79630; 1 drivers +v0x584af5d5d3c0_0 .net "l_w_ioa_we", 0 0, v0x584af5d4f380_0; 1 drivers +v0x584af5d5d4b0_0 .net "l_w_ir_disp_out", 15 0, L_0x584af5cb3880; 1 drivers +v0x584af5d5d550_0 .net "l_w_ir_in", 15 0, L_0x584af5d7e9c0; 1 drivers +v0x584af5d5d640_0 .net "l_w_ir_internal", 15 0, L_0x584af5d809d0; 1 drivers +v0x584af5d5d750_0 .net "l_w_ir_oe", 0 0, v0x584af5d4f440_0; 1 drivers +v0x584af5d5d7f0_0 .net "l_w_ir_out", 15 0, L_0x584af5d79080; 1 drivers +v0x584af5d5d8b0_0 .net "l_w_ir_we", 0 0, v0x584af5d4f500_0; 1 drivers +v0x584af5d5d9a0_0 .net "l_w_ma_disp_out", 15 0, L_0x584af5d79520; 1 drivers +v0x584af5d5da60_0 .net "l_w_ma_in", 15 0, L_0x584af5d7e670; 1 drivers +v0x584af5d5db50_0 .net "l_w_ma_oe", 0 0, v0x584af5d4f5c0_0; 1 drivers +v0x584af5d5dc40_0 .net "l_w_ma_out", 15 0, L_0x584af5d793e0; 1 drivers +v0x584af5d5dd00_0 .net "l_w_ma_we", 0 0, v0x584af5d4f680_0; 1 drivers +v0x584af5d5ddf0_0 .net "l_w_offset_out", 15 0, L_0x584af5d7d940; 1 drivers +v0x584af5d5de90_0 .net "l_w_pc_disp_out", 15 0, L_0x584af5cb8860; 1 drivers +v0x584af5d5df30_0 .net "l_w_pc_in", 15 0, L_0x584af5d7e530; 1 drivers +v0x584af5d5e020_0 .net "l_w_pc_oe", 0 0, v0x584af5d4f740_0; 1 drivers +v0x584af5d5e110_0 .net "l_w_pc_out", 15 0, L_0x584af5d78e80; 1 drivers +v0x584af5d5e220_0 .net "l_w_pc_we", 0 0, v0x584af5d4f800_0; 1 drivers +v0x584af5d5e310_0 .net "l_w_ram_in", 15 0, L_0x584af5d7e220; 1 drivers +v0x584af5d5e3d0_0 .net "l_w_ram_oe", 0 0, v0x584af5d4f8c0_0; 1 drivers +v0x584af5d5e4c0_0 .net "l_w_ram_out", 15 0, L_0x584af5d7c180; 1 drivers +v0x584af5d5e5d0_0 .net "l_w_ram_we", 0 0, v0x584af5d4f980_0; 1 drivers +v0x584af5d5e670_0 .net "l_w_regs_addr", 2 0, v0x584af5d4fa40_0; 1 drivers +v0x584af5d5e780_0 .net "l_w_regs_disp_addr", 2 0, L_0x584af5d68770; 1 drivers +v0x584af5d5e840_0 .net "l_w_regs_disp_out", 15 0, L_0x584af5cbc290; 1 drivers +v0x584af5d5e8e0_0 .net "l_w_regs_in", 15 0, L_0x584af5d7e430; 1 drivers +v0x584af5d5e9d0_0 .net "l_w_regs_oe", 0 0, v0x584af5d4fb20_0; 1 drivers +v0x584af5d5eac0_0 .net "l_w_regs_out", 15 0, L_0x584af5d78a70; 1 drivers +v0x584af5d5ebd0_0 .net "l_w_regs_we", 0 0, v0x584af5d4fbe0_0; 1 drivers +v0x584af5d5ecc0_0 .net "l_w_t1_disp_out", 15 0, L_0x584af5d799b0; 1 drivers +v0x584af5d5ed80_0 .net "l_w_t1_in", 15 0, L_0x584af5d7e8d0; 1 drivers +v0x584af5d5ee70_0 .net "l_w_t1_oe", 0 0, v0x584af5d4fca0_0; 1 drivers +v0x584af5d5ef60_0 .net "l_w_t1_out", 15 0, L_0x584af5d798a0; 1 drivers +v0x584af5d5f070_0 .net "l_w_t1_we", 0 0, v0x584af5d4fd60_0; 1 drivers +v0x584af5d5f160_0 .net "l_w_t2_disp_out", 15 0, L_0x584af5d79bf0; 1 drivers +v0x584af5d5f220_0 .net "l_w_t2_in", 15 0, L_0x584af5d7e6e0; 1 drivers +v0x584af5d5f310_0 .net "l_w_t2_oe", 0 0, v0x584af5d4fe20_0; 1 drivers +v0x584af5d5f400_0 .net "l_w_t2_out", 15 0, L_0x584af5d79ae0; 1 drivers +v0x584af5d5f510_0 .net "l_w_t2_we", 0 0, v0x584af5d4fee0_0; 1 drivers +v0x584af5d5f600_0 .net "o_w_bus_disp_out", 15 0, L_0x584af5d7eac0; alias, 1 drivers +v0x584af5d5f6c0_0 .net "o_w_io_in", 15 0, L_0x584af5d7e320; 1 drivers +v0x584af5d5f760_0 .net "o_w_io_oe", 0 0, v0x584af5d4f140_0; 1 drivers +v0x584af5d5f800_0 .net "o_w_io_port", 7 0, L_0x584af5d7c6e0; 1 drivers +v0x584af5d5f8a0_0 .net "o_w_io_we", 0 0, v0x584af5d4f200_0; 1 drivers +v0x584af5d5f940_0 .net "o_w_ram_disp_out", 15 0, v0x584af5d51950_0; alias, 1 drivers +v0x584af5d5fa30_0 .net "o_w_regs_disp_out", 15 0, L_0x584af5d7be70; alias, 1 drivers +v0x584af5d5fb10_0 .net "o_w_state_disp_out", 15 0, L_0x584af5d7f6d0; alias, 1 drivers +L_0x584af5d68640 .part L_0x584af5d684d0, 1, 2; +L_0x584af5d68770 .concat [ 2 1 0 0], L_0x584af5d68640, L_0x795a1e20d018; +L_0x584af5d79080 .functor MUXZ 16, L_0x795a1e20d1c8, L_0x584af5d809d0, v0x584af5d4f440_0, C4<>; +L_0x584af5d792a0 .functor MUXZ 16, L_0x795a1e20d258, L_0x584af5d80a90, v0x584af5d4ef40_0, C4<>; +L_0x584af5d79d20 .part L_0x584af5d684d0, 3, 1; +L_0x584af5d79dc0 .concat [ 1 31 0 0], L_0x584af5d79d20, L_0x795a1e20d3c0; +L_0x584af5d79f40 .cmp/eq 32, L_0x584af5d79dc0, L_0x795a1e20d408; +L_0x584af5d7a080 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7a170 .cmp/eq 3, L_0x584af5d7a080, L_0x795a1e20d450; +L_0x584af5d7a2b0 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7a4c0 .cmp/eq 3, L_0x584af5d7a2b0, L_0x795a1e20d498; +L_0x584af5d7a5b0 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7a7d0 .cmp/eq 3, L_0x584af5d7a5b0, L_0x795a1e20d4e0; +L_0x584af5d7a910 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7aa30 .cmp/eq 3, L_0x584af5d7a910, L_0x795a1e20d528; +L_0x584af5d7ab70 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7aca0 .cmp/eq 3, L_0x584af5d7ab70, L_0x795a1e20d570; +L_0x584af5d7ade0 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7af20 .cmp/eq 3, L_0x584af5d7ade0, L_0x795a1e20d5b8; +L_0x584af5d7b060 .part L_0x584af5d684d0, 0, 3; +L_0x584af5d7ae80 .cmp/eq 3, L_0x584af5d7b060, L_0x795a1e20d600; +L_0x584af5d7b250 .functor MUXZ 16, L_0x795a1e20d648, L_0x584af5cb3880, L_0x584af5d7ae80, C4<>; +L_0x584af5d7b450 .functor MUXZ 16, L_0x584af5d7b250, L_0x584af5d79bf0, L_0x584af5d7af20, C4<>; +L_0x584af5d7b590 .functor MUXZ 16, L_0x584af5d7b450, L_0x584af5d799b0, L_0x584af5d7aca0, C4<>; +L_0x584af5d7b7a0 .functor MUXZ 16, L_0x584af5d7b590, L_0x584af5d79770, L_0x584af5d7aa30, C4<>; +L_0x584af5d7b8e0 .functor MUXZ 16, L_0x584af5d7b7a0, L_0x584af5d79520, L_0x584af5d7a7d0, C4<>; +L_0x584af5d7bb00 .functor MUXZ 16, L_0x584af5d7b8e0, L_0x584af5d2b760, L_0x584af5d7a4c0, C4<>; +L_0x584af5d7bc40 .functor MUXZ 16, L_0x584af5d7bb00, L_0x584af5cb8860, L_0x584af5d7a170, C4<>; +L_0x584af5d7be70 .functor MUXZ 16, L_0x584af5d7bc40, L_0x584af5cbc290, L_0x584af5d79f40, C4<>; +L_0x584af5d7c310 .part L_0x584af5d793e0, 0, 10; +L_0x584af5d7c6e0 .part L_0x584af5d79630, 0, 8; +L_0x584af5d7c780 .concat [ 5 11 0 0], L_0x584af5d7c5f0, L_0x795a1e20d840; +L_0x584af5d7c980 .functor MUXZ 16, L_0x584af5d7e600, L_0x584af5d7c780, v0x584af5d4efe0_0, C4<>; +L_0x584af5d7cb60 .part L_0x584af5d79080, 8, 1; +LS_0x584af5d7cd70_0_0 .concat [ 1 1 1 1], L_0x584af5d7cb60, L_0x584af5d7cb60, L_0x584af5d7cb60, L_0x584af5d7cb60; +LS_0x584af5d7cd70_0_4 .concat [ 1 1 1 1], L_0x584af5d7cb60, L_0x584af5d7cb60, L_0x584af5d7cb60, L_0x584af5d7cb60; +L_0x584af5d7cd70 .concat [ 4 4 0 0], LS_0x584af5d7cd70_0_0, LS_0x584af5d7cd70_0_4; +L_0x584af5d7ceb0 .part L_0x584af5d79080, 8, 1; +L_0x584af5d7cc50 .part L_0x584af5d79080, 9, 1; +L_0x584af5d7d080 .part L_0x584af5d79080, 10, 1; +L_0x584af5d7d260 .part L_0x584af5d79080, 11, 1; +L_0x584af5d7d300 .part L_0x584af5d79080, 12, 1; +L_0x584af5d7d4f0 .part L_0x584af5d79080, 13, 1; +L_0x584af5d7d6a0 .part L_0x584af5d79080, 14, 1; +L_0x584af5d7d8a0 .part L_0x584af5d79080, 15, 1; +LS_0x584af5d7d940_0_0 .concat [ 1 1 1 1], L_0x584af5d7d8a0, L_0x584af5d7d6a0, L_0x584af5d7d4f0, L_0x584af5d7d300; +LS_0x584af5d7d940_0_4 .concat [ 1 1 1 1], L_0x584af5d7d260, L_0x584af5d7d080, L_0x584af5d7cc50, L_0x584af5d7ceb0; +LS_0x584af5d7d940_0_8 .concat [ 8 0 0 0], L_0x584af5d7cd70; +L_0x584af5d7d940 .concat [ 4 4 8 0], LS_0x584af5d7d940_0_0, LS_0x584af5d7d940_0_4, LS_0x584af5d7d940_0_8; +S_0x584af5cb5de0 .scope module, "l_m_alu" "alu" 6 311, 7 1 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_out"; + .port_info 1 /OUTPUT 5 "o_w_flags"; + .port_info 2 /INPUT 16 "i_w_in1"; + .port_info 3 /INPUT 16 "i_w_in2"; + .port_info 4 /INPUT 4 "i_w_opcode"; + .port_info 5 /INPUT 1 "i_w_carry"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d47890 .param/l "p_data_width" 0 7 2, +C4<00000000000000000000000000010000>; +P_0x584af5d478d0 .param/l "p_flags_width" 0 7 3, +C4<00000000000000000000000000000101>; +P_0x584af5d47910 .param/l "p_opcode_ADC" 0 7 5, C4<0000>; +P_0x584af5d47950 .param/l "p_opcode_AND" 0 7 9, C4<0100>; +P_0x584af5d47990 .param/l "p_opcode_NOT" 0 7 8, C4<0011>; +P_0x584af5d479d0 .param/l "p_opcode_OR" 0 7 10, C4<0101>; +P_0x584af5d47a10 .param/l "p_opcode_SAR" 0 7 14, C4<1001>; +P_0x584af5d47a50 .param/l "p_opcode_SBB1" 0 7 6, C4<0001>; +P_0x584af5d47a90 .param/l "p_opcode_SBB2" 0 7 7, C4<0010>; +P_0x584af5d47ad0 .param/l "p_opcode_SHL" 0 7 12, C4<0111>; +P_0x584af5d47b10 .param/l "p_opcode_SHR" 0 7 13, C4<1000>; +P_0x584af5d47b50 .param/l "p_opcode_XOR" 0 7 11, C4<0110>; +P_0x584af5d47b90 .param/l "p_opcode_width" 0 7 4, +C4<00000000000000000000000000000100>; +L_0x795a1e20d7f8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d48220_0 .net/2u *"_ivl_0", 15 0, L_0x795a1e20d7f8; 1 drivers +v0x584af5d48320_0 .net "i_w_carry", 0 0, v0x584af5d4ecd0_0; alias, 1 drivers +v0x584af5d483e0_0 .net "i_w_in1", 15 0, L_0x584af5d798a0; alias, 1 drivers +v0x584af5d484d0_0 .net "i_w_in2", 15 0, L_0x584af5d79ae0; alias, 1 drivers +v0x584af5d485b0_0 .net "i_w_oe", 0 0, v0x584af5d4eda0_0; alias, 1 drivers +v0x584af5d486c0_0 .net "i_w_opcode", 3 0, v0x584af5d4ee70_0; alias, 1 drivers +v0x584af5d487a0_0 .var "l_r_carry", 0 0; +v0x584af5d48860_0 .var "l_r_overflow", 0 0; +v0x584af5d48920_0 .var "l_r_parity", 0 0; +v0x584af5d489e0_0 .var "l_r_result", 15 0; +v0x584af5d48ac0_0 .var "l_r_sign", 0 0; +v0x584af5d48b80_0 .var "l_r_zero", 0 0; +v0x584af5d48c40_0 .net "o_w_flags", 4 0, L_0x584af5d7c5f0; alias, 1 drivers +v0x584af5d48d20_0 .net "o_w_out", 15 0, L_0x584af5d7c500; alias, 1 drivers +E_0x584af5d2e4d0/0 .event edge, v0x584af5d486c0_0, v0x584af5d483e0_0, v0x584af5d484d0_0, v0x584af5d48320_0; +E_0x584af5d2e4d0/1 .event edge, v0x584af5d489e0_0, v0x584af5d487a0_0; +E_0x584af5d2e4d0 .event/or E_0x584af5d2e4d0/0, E_0x584af5d2e4d0/1; +L_0x584af5d7c500 .functor MUXZ 16, L_0x795a1e20d7f8, v0x584af5d489e0_0, v0x584af5d4eda0_0, C4<>; +LS_0x584af5d7c5f0_0_0 .concat [ 1 1 1 1], v0x584af5d487a0_0, v0x584af5d48860_0, v0x584af5d48b80_0, v0x584af5d48ac0_0; +LS_0x584af5d7c5f0_0_4 .concat [ 1 0 0 0], v0x584af5d48920_0; +L_0x584af5d7c5f0 .concat [ 4 1 0 0], LS_0x584af5d7c5f0_0_0, LS_0x584af5d7c5f0_0_4; +S_0x584af5cba4a0 .scope module, "l_m_bus" "bus" 6 352, 8 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_bus_to_ram"; + .port_info 2 /OUTPUT 16 "o_w_bus_to_io"; + .port_info 3 /OUTPUT 16 "o_w_bus_to_regs"; + .port_info 4 /OUTPUT 16 "o_w_bus_to_pc"; + .port_info 5 /OUTPUT 16 "o_w_bus_to_flags"; + .port_info 6 /OUTPUT 16 "o_w_bus_to_ma"; + .port_info 7 /OUTPUT 16 "o_w_bus_to_ioa"; + .port_info 8 /OUTPUT 16 "o_w_bus_to_t1"; + .port_info 9 /OUTPUT 16 "o_w_bus_to_t2"; + .port_info 10 /OUTPUT 16 "o_w_bus_to_ir"; + .port_info 11 /INPUT 16 "i_w_alu_to_bus"; + .port_info 12 /INPUT 16 "i_w_ram_to_bus"; + .port_info 13 /INPUT 16 "i_w_io_to_bus"; + .port_info 14 /INPUT 16 "i_w_regs_to_bus"; + .port_info 15 /INPUT 16 "i_w_pc_to_bus"; + .port_info 16 /INPUT 16 "i_w_flags_to_bus"; + .port_info 17 /INPUT 16 "i_w_offset_to_bus"; +P_0x584af5d48f00 .param/l "p_data_width" 0 8 3, +C4<00000000000000000000000000010000>; +L_0x584af5d7dd80 .functor OR 16, L_0x584af5d7c500, L_0x584af5d7c180, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7ddf0 .functor OR 16, L_0x584af5d7dd80, L_0x795a1e20d888, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7de60 .functor OR 16, L_0x584af5d7ddf0, L_0x584af5d78a70, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7dfb0 .functor OR 16, L_0x584af5d7de60, L_0x584af5d78e80, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e0b0 .functor OR 16, L_0x584af5d7dfb0, L_0x584af5d792a0, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e120 .functor OR 16, L_0x584af5d7e0b0, L_0x584af5d7d940, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e220 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e320 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e430 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e530 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e600 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e670 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e750 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e8d0 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e6e0 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7e9c0 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d7eac0 .functor BUFZ 16, L_0x584af5d7e120, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x584af5d49290_0 .net *"_ivl_0", 15 0, L_0x584af5d7dd80; 1 drivers +v0x584af5d49370_0 .net *"_ivl_2", 15 0, L_0x584af5d7ddf0; 1 drivers +v0x584af5d49450_0 .net *"_ivl_4", 15 0, L_0x584af5d7de60; 1 drivers +v0x584af5d49540_0 .net *"_ivl_6", 15 0, L_0x584af5d7dfb0; 1 drivers +v0x584af5d49620_0 .net *"_ivl_8", 15 0, L_0x584af5d7e0b0; 1 drivers +v0x584af5d49750_0 .net "i_w_alu_to_bus", 15 0, L_0x584af5d7c500; alias, 1 drivers +v0x584af5d49810_0 .net "i_w_flags_to_bus", 15 0, L_0x584af5d792a0; alias, 1 drivers +v0x584af5d498d0_0 .net "i_w_io_to_bus", 15 0, L_0x795a1e20d888; alias, 1 drivers +v0x584af5d499b0_0 .net "i_w_offset_to_bus", 15 0, L_0x584af5d7d940; alias, 1 drivers +v0x584af5d49a90_0 .net "i_w_pc_to_bus", 15 0, L_0x584af5d78e80; alias, 1 drivers +v0x584af5d49b70_0 .net "i_w_ram_to_bus", 15 0, L_0x584af5d7c180; alias, 1 drivers +v0x584af5d49c50_0 .net "i_w_regs_to_bus", 15 0, L_0x584af5d78a70; alias, 1 drivers +v0x584af5d49d30_0 .net "l_w_bus", 15 0, L_0x584af5d7e120; 1 drivers +v0x584af5d49e10_0 .net "o_w_bus_to_flags", 15 0, L_0x584af5d7e600; alias, 1 drivers +v0x584af5d49ef0_0 .net "o_w_bus_to_io", 15 0, L_0x584af5d7e320; alias, 1 drivers +v0x584af5d49fd0_0 .net "o_w_bus_to_ioa", 15 0, L_0x584af5d7e750; alias, 1 drivers +v0x584af5d4a0b0_0 .net "o_w_bus_to_ir", 15 0, L_0x584af5d7e9c0; alias, 1 drivers +v0x584af5d4a190_0 .net "o_w_bus_to_ma", 15 0, L_0x584af5d7e670; alias, 1 drivers +v0x584af5d4a270_0 .net "o_w_bus_to_pc", 15 0, L_0x584af5d7e530; alias, 1 drivers +v0x584af5d4a350_0 .net "o_w_bus_to_ram", 15 0, L_0x584af5d7e220; alias, 1 drivers +v0x584af5d4a430_0 .net "o_w_bus_to_regs", 15 0, L_0x584af5d7e430; alias, 1 drivers +v0x584af5d4a510_0 .net "o_w_bus_to_t1", 15 0, L_0x584af5d7e8d0; alias, 1 drivers +v0x584af5d4a5f0_0 .net "o_w_bus_to_t2", 15 0, L_0x584af5d7e6e0; alias, 1 drivers +v0x584af5d4a6d0_0 .net "o_w_disp_out", 15 0, L_0x584af5d7eac0; alias, 1 drivers +S_0x584af5cb4710 .scope module, "l_m_cu" "control_unit" 6 390, 9 1 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_state_disp_out"; + .port_info 1 /OUTPUT 1 "o_r_alu_oe"; + .port_info 2 /OUTPUT 1 "o_r_alu_carry"; + .port_info 3 /OUTPUT 4 "o_r_alu_opcode"; + .port_info 4 /OUTPUT 1 "o_r_ram_oe"; + .port_info 5 /OUTPUT 1 "o_r_ram_we"; + .port_info 6 /OUTPUT 1 "o_r_io_oe"; + .port_info 7 /OUTPUT 1 "o_r_io_we"; + .port_info 8 /OUTPUT 3 "o_r_regs_addr"; + .port_info 9 /OUTPUT 1 "o_r_regs_oe"; + .port_info 10 /OUTPUT 1 "o_r_regs_we"; + .port_info 11 /OUTPUT 1 "o_r_pc_oe"; + .port_info 12 /OUTPUT 1 "o_r_pc_we"; + .port_info 13 /OUTPUT 1 "o_r_flags_sel"; + .port_info 14 /OUTPUT 1 "o_r_flags_oe"; + .port_info 15 /OUTPUT 1 "o_r_flags_we"; + .port_info 16 /OUTPUT 1 "o_r_ma_oe"; + .port_info 17 /OUTPUT 1 "o_r_ma_we"; + .port_info 18 /OUTPUT 1 "o_r_ioa_oe"; + .port_info 19 /OUTPUT 1 "o_r_ioa_we"; + .port_info 20 /OUTPUT 1 "o_r_t1_oe"; + .port_info 21 /OUTPUT 1 "o_r_t1_we"; + .port_info 22 /OUTPUT 1 "o_r_t2_oe"; + .port_info 23 /OUTPUT 1 "o_r_t2_we"; + .port_info 24 /OUTPUT 1 "o_r_ir_oe"; + .port_info 25 /OUTPUT 1 "o_r_ir_we"; + .port_info 26 /INPUT 1 "i_w_clk"; + .port_info 27 /INPUT 1 "i_w_reset"; + .port_info 28 /INPUT 16 "i_w_ir"; + .port_info 29 /INPUT 16 "i_w_flags"; +P_0x584af5d4aac0 .param/l "l_p_state_ADDR_IO" 1 9 84, C4<0000000000111100>; +P_0x584af5d4ab00 .param/l "l_p_state_ADDR_REG" 1 9 83, C4<0000000000110100>; +P_0x584af5d4ab40 .param/l "l_p_state_ADDR_SUM" 1 9 82, C4<0000000000110000>; +P_0x584af5d4ab80 .param/l "l_p_state_DECODE" 1 9 81, C4<0000000000100000>; +P_0x584af5d4abc0 .param/l "l_p_state_EXEC_ONE_OP" 1 9 92, C4<0000000001110000>; +P_0x584af5d4ac00 .param/l "l_p_state_EXEC_TRANSFER" 1 9 94, C4<0000000001111000>; +P_0x584af5d4ac40 .param/l "l_p_state_EXEC_TWO_OP" 1 9 93, C4<0000000001110100>; +P_0x584af5d4ac80 .param/l "l_p_state_FETCH" 1 9 80, C4<0000000000010000>; +P_0x584af5d4acc0 .param/l "l_p_state_INC_PC" 1 9 98, C4<0000000010010000>; +P_0x584af5d4ad00 .param/l "l_p_state_LOAD_DST_MEM" 1 9 89, C4<0000000001010100>; +P_0x584af5d4ad40 .param/l "l_p_state_LOAD_DST_REG" 1 9 88, C4<0000000001010000>; +P_0x584af5d4ad80 .param/l "l_p_state_LOAD_SRC_IO" 1 9 87, C4<0000000001001100>; +P_0x584af5d4adc0 .param/l "l_p_state_LOAD_SRC_MEM" 1 9 86, C4<0000000001000100>; +P_0x584af5d4ae00 .param/l "l_p_state_LOAD_SRC_REG" 1 9 85, C4<0000000001000000>; +P_0x584af5d4ae40 .param/l "l_p_state_NO_LOAD_DST_IO" 1 9 91, C4<0000000001101100>; +P_0x584af5d4ae80 .param/l "l_p_state_NO_LOAD_DST_REG" 1 9 90, C4<0000000001100000>; +P_0x584af5d4aec0 .param/l "l_p_state_RESET" 1 9 79, C4<0000000000000000>; +P_0x584af5d4af00 .param/l "l_p_state_STORE_IO" 1 9 97, C4<0000000010001100>; +P_0x584af5d4af40 .param/l "l_p_state_STORE_MEM" 1 9 96, C4<0000000010000100>; +P_0x584af5d4af80 .param/l "l_p_state_STORE_REG" 1 9 95, C4<0000000010000000>; +P_0x584af5d4afc0 .param/l "l_p_state_width" 1 9 58, +C4<00000000000000000000000000010000>; +P_0x584af5d4b000 .param/l "p_BA_address" 0 9 21, C4<110>; +P_0x584af5d4b040 .param/l "p_BB_address" 0 9 22, C4<111>; +P_0x584af5d4b080 .param/l "p_RA_address" 0 9 15, C4<000>; +P_0x584af5d4b0c0 .param/l "p_RB_address" 0 9 16, C4<001>; +P_0x584af5d4b100 .param/l "p_RC_address" 0 9 17, C4<010>; +P_0x584af5d4b140 .param/l "p_SP_address" 0 9 18, C4<011>; +P_0x584af5d4b180 .param/l "p_XA_address" 0 9 19, C4<100>; +P_0x584af5d4b1c0 .param/l "p_XB_address" 0 9 20, C4<101>; +P_0x584af5d4b200 .param/l "p_data_width" 0 9 2, +C4<00000000000000000000000000010000>; +P_0x584af5d4b240 .param/l "p_opcode_ADC" 0 9 4, C4<0000>; +P_0x584af5d4b280 .param/l "p_opcode_AND" 0 9 8, C4<0100>; +P_0x584af5d4b2c0 .param/l "p_opcode_NOT" 0 9 7, C4<0011>; +P_0x584af5d4b300 .param/l "p_opcode_OR" 0 9 9, C4<0101>; +P_0x584af5d4b340 .param/l "p_opcode_SAR" 0 9 13, C4<1001>; +P_0x584af5d4b380 .param/l "p_opcode_SBB1" 0 9 5, C4<0001>; +P_0x584af5d4b3c0 .param/l "p_opcode_SBB2" 0 9 6, C4<0010>; +P_0x584af5d4b400 .param/l "p_opcode_SHL" 0 9 11, C4<0111>; +P_0x584af5d4b440 .param/l "p_opcode_SHR" 0 9 12, C4<1000>; +P_0x584af5d4b480 .param/l "p_opcode_XOR" 0 9 10, C4<0110>; +P_0x584af5d4b4c0 .param/l "p_opcode_width" 0 9 3, +C4<00000000000000000000000000000100>; +P_0x584af5d4b500 .param/l "p_regs_address_width" 0 9 14, +C4<00000000000000000000000000000011>; +L_0x584af5d7f6d0 .functor BUFZ 16, v0x584af5d4e6d0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x584af5d49030_0 .net *"_ivl_1", 0 0, L_0x584af5d7eb30; 1 drivers +v0x584af5d4cc60_0 .net *"_ivl_11", 0 0, L_0x584af5d7eff0; 1 drivers +v0x584af5d4cd40_0 .net *"_ivl_13", 0 0, L_0x584af5d7f0d0; 1 drivers +v0x584af5d4ce30_0 .net *"_ivl_17", 0 0, L_0x584af5d7f3a0; 1 drivers +v0x584af5d4cf10_0 .net *"_ivl_21", 0 0, L_0x584af5d7f590; 1 drivers +v0x584af5d4cff0_0 .net *"_ivl_23", 0 0, L_0x584af5d7f630; 1 drivers +v0x584af5d4d0d0_0 .net *"_ivl_27", 0 0, L_0x584af5d7f830; 1 drivers +v0x584af5d4d1b0_0 .net *"_ivl_29", 0 0, L_0x584af5d7f950; 1 drivers +v0x584af5d4d290_0 .net *"_ivl_3", 0 0, L_0x584af5d7ec60; 1 drivers +v0x584af5d4d370_0 .net *"_ivl_31", 0 0, L_0x584af5d7f9f0; 1 drivers +v0x584af5d4d450_0 .net *"_ivl_35", 0 0, L_0x584af5d7fcb0; 1 drivers +v0x584af5d4d530_0 .net *"_ivl_37", 0 0, L_0x584af5d7fdf0; 1 drivers +v0x584af5d4d610_0 .net *"_ivl_39", 0 0, L_0x584af5d7fe90; 1 drivers +v0x584af5d4d6f0_0 .net *"_ivl_5", 0 0, L_0x584af5d7ed00; 1 drivers +v0x584af5d4d7d0_0 .net *"_ivl_7", 0 0, L_0x584af5d7eda0; 1 drivers +v0x584af5d4d8b0_0 .net *"_ivl_9", 0 0, L_0x584af5d7ee40; 1 drivers +v0x584af5d4d990_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d4da50_0 .net "i_w_flags", 15 0, L_0x584af5d80a90; alias, 1 drivers +v0x584af5d4db30_0 .net "i_w_ir", 15 0, L_0x584af5d809d0; alias, 1 drivers +v0x584af5d4dc10_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d4dcb0_0 .var "l_r_decoded_d", 0 0; +v0x584af5d4dd50_0 .var "l_r_decoded_d_next", 0 0; +v0x584af5d4de10_0 .var "l_r_decoded_dst", 15 0; +v0x584af5d4def0_0 .var "l_r_decoded_dst_next", 15 0; +v0x584af5d4dfd0_0 .var "l_r_decoded_exec", 15 0; +v0x584af5d4e0b0_0 .var "l_r_decoded_exec_next", 15 0; +v0x584af5d4e190_0 .var "l_r_decoded_rg", 0 2; +v0x584af5d4e270_0 .var "l_r_decoded_rg_next", 0 2; +v0x584af5d4e350_0 .var "l_r_decoded_src", 15 0; +v0x584af5d4e430_0 .var "l_r_decoded_src_next", 15 0; +v0x584af5d4e510_0 .var "l_r_decoded_store", 15 0; +v0x584af5d4e5f0_0 .var "l_r_decoded_store_next", 15 0; +v0x584af5d4e6d0_0 .var "l_r_state", 15 0; +v0x584af5d4e7b0_0 .var "l_r_state_next", 15 0; +v0x584af5d4e890_0 .net "l_w_cop", 0 6, L_0x584af5d7f170; 1 drivers +v0x584af5d4e970_0 .net "l_w_d", 0 0, L_0x584af5d7f440; 1 drivers +v0x584af5d4ea30_0 .net "l_w_mod", 0 1, L_0x584af5d7f740; 1 drivers +v0x584af5d4eb10_0 .net "l_w_rg", 0 2, L_0x584af5d7fb20; 1 drivers +v0x584af5d4ebf0_0 .net "l_w_rm", 0 2, L_0x584af5d7fd50; 1 drivers +v0x584af5d4ecd0_0 .var "o_r_alu_carry", 0 0; +v0x584af5d4eda0_0 .var "o_r_alu_oe", 0 0; +v0x584af5d4ee70_0 .var "o_r_alu_opcode", 3 0; +v0x584af5d4ef40_0 .var "o_r_flags_oe", 0 0; +v0x584af5d4efe0_0 .var "o_r_flags_sel", 0 0; +v0x584af5d4f080_0 .var "o_r_flags_we", 0 0; +v0x584af5d4f140_0 .var "o_r_io_oe", 0 0; +v0x584af5d4f200_0 .var "o_r_io_we", 0 0; +v0x584af5d4f2c0_0 .var "o_r_ioa_oe", 0 0; +v0x584af5d4f380_0 .var "o_r_ioa_we", 0 0; +v0x584af5d4f440_0 .var "o_r_ir_oe", 0 0; +v0x584af5d4f500_0 .var "o_r_ir_we", 0 0; +v0x584af5d4f5c0_0 .var "o_r_ma_oe", 0 0; +v0x584af5d4f680_0 .var "o_r_ma_we", 0 0; +v0x584af5d4f740_0 .var "o_r_pc_oe", 0 0; +v0x584af5d4f800_0 .var "o_r_pc_we", 0 0; +v0x584af5d4f8c0_0 .var "o_r_ram_oe", 0 0; +v0x584af5d4f980_0 .var "o_r_ram_we", 0 0; +v0x584af5d4fa40_0 .var "o_r_regs_addr", 2 0; +v0x584af5d4fb20_0 .var "o_r_regs_oe", 0 0; +v0x584af5d4fbe0_0 .var "o_r_regs_we", 0 0; +v0x584af5d4fca0_0 .var "o_r_t1_oe", 0 0; +v0x584af5d4fd60_0 .var "o_r_t1_we", 0 0; +v0x584af5d4fe20_0 .var "o_r_t2_oe", 0 0; +v0x584af5d4fee0_0 .var "o_r_t2_we", 0 0; +v0x584af5d4ffa0_0 .net "o_w_state_disp_out", 15 0, L_0x584af5d7f6d0; alias, 1 drivers +E_0x584af5b8bd70/0 .event edge, v0x584af5d4e6d0_0, v0x584af5d4e890_0, v0x584af5d4eb10_0, v0x584af5d4ea30_0; +E_0x584af5b8bd70/1 .event edge, v0x584af5d4def0_0, v0x584af5d4e970_0, v0x584af5d4ebf0_0, v0x584af5d4e430_0; +E_0x584af5b8bd70/2 .event edge, v0x584af5d4dcb0_0, v0x584af5d4e350_0, v0x584af5d4e190_0, v0x584af5d4de10_0; +E_0x584af5b8bd70/3 .event edge, v0x584af5d4dfd0_0, v0x584af5d4e510_0, v0x584af5d4da50_0; +E_0x584af5b8bd70 .event/or E_0x584af5b8bd70/0, E_0x584af5b8bd70/1, E_0x584af5b8bd70/2, E_0x584af5b8bd70/3; +E_0x584af5d4cba0/0 .event negedge, v0x584af5d46910_0; +E_0x584af5d4cba0/1 .event posedge, v0x584af5d4d990_0; +E_0x584af5d4cba0 .event/or E_0x584af5d4cba0/0, E_0x584af5d4cba0/1; +L_0x584af5d7eb30 .part L_0x584af5d809d0, 0, 1; +L_0x584af5d7ec60 .part L_0x584af5d809d0, 1, 1; +L_0x584af5d7ed00 .part L_0x584af5d809d0, 2, 1; +L_0x584af5d7eda0 .part L_0x584af5d809d0, 3, 1; +L_0x584af5d7ee40 .part L_0x584af5d809d0, 4, 1; +L_0x584af5d7eff0 .part L_0x584af5d809d0, 5, 1; +L_0x584af5d7f0d0 .part L_0x584af5d809d0, 6, 1; +LS_0x584af5d7f170_0_0 .concat [ 1 1 1 1], L_0x584af5d7f0d0, L_0x584af5d7eff0, L_0x584af5d7ee40, L_0x584af5d7eda0; +LS_0x584af5d7f170_0_4 .concat [ 1 1 1 0], L_0x584af5d7ed00, L_0x584af5d7ec60, L_0x584af5d7eb30; +L_0x584af5d7f170 .concat [ 4 3 0 0], LS_0x584af5d7f170_0_0, LS_0x584af5d7f170_0_4; +L_0x584af5d7f3a0 .part L_0x584af5d809d0, 7, 1; +L_0x584af5d7f440 .concat [ 1 0 0 0], L_0x584af5d7f3a0; +L_0x584af5d7f590 .part L_0x584af5d809d0, 8, 1; +L_0x584af5d7f630 .part L_0x584af5d809d0, 9, 1; +L_0x584af5d7f740 .concat [ 1 1 0 0], L_0x584af5d7f630, L_0x584af5d7f590; +L_0x584af5d7f830 .part L_0x584af5d809d0, 10, 1; +L_0x584af5d7f950 .part L_0x584af5d809d0, 11, 1; +L_0x584af5d7f9f0 .part L_0x584af5d809d0, 12, 1; +L_0x584af5d7fb20 .concat [ 1 1 1 0], L_0x584af5d7f9f0, L_0x584af5d7f950, L_0x584af5d7f830; +L_0x584af5d7fcb0 .part L_0x584af5d809d0, 13, 1; +L_0x584af5d7fdf0 .part L_0x584af5d809d0, 14, 1; +L_0x584af5d7fe90 .part L_0x584af5d809d0, 15, 1; +L_0x584af5d7fd50 .concat [ 1 1 1 0], L_0x584af5d7fe90, L_0x584af5d7fdf0, L_0x584af5d7fcb0; +S_0x584af5cbd240 .scope module, "l_m_ram" "cram" 6 260, 10 1 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /INPUT 10 "i_w_disp_address"; + .port_info 2 /OUTPUT 16 "o_w_out"; + .port_info 3 /INPUT 16 "i_w_in"; + .port_info 4 /INPUT 10 "i_w_address"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; + .port_info 7 /INPUT 1 "i_w_clk"; + .port_info 8 /INPUT 1 "i_w_ram_clk"; +P_0x584af5d48fa0 .param/l "p_address_width" 0 10 3, +C4<00000000000000000000000000001010>; +P_0x584af5d48fe0 .param/l "p_data_width" 0 10 2, +C4<00000000000000000000000000010000>; +L_0x795a1e20d720 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +L_0x584af5d7a760 .functor XNOR 1, v0x584af5d4f8c0_0, L_0x795a1e20d720, C4<0>, C4<0>; +L_0x795a1e20d768 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; +L_0x584af5d7c000 .functor XNOR 1, v0x584af5d4f980_0, L_0x795a1e20d768, C4<0>, C4<0>; +L_0x584af5d7c070 .functor AND 1, L_0x584af5d7a760, L_0x584af5d7c000, C4<1>, C4<1>; +v0x584af5d51b70_0 .net *"_ivl_10", 0 0, L_0x584af5d7c000; 1 drivers +v0x584af5d51c50_0 .net *"_ivl_13", 0 0, L_0x584af5d7c070; 1 drivers +L_0x795a1e20d7b0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d51d10_0 .net/2u *"_ivl_14", 15 0, L_0x795a1e20d7b0; 1 drivers +v0x584af5d51e00_0 .net/2u *"_ivl_4", 0 0, L_0x795a1e20d720; 1 drivers +v0x584af5d51ee0_0 .net *"_ivl_6", 0 0, L_0x584af5d7a760; 1 drivers +v0x584af5d51fa0_0 .net/2u *"_ivl_8", 0 0, L_0x795a1e20d768; 1 drivers +v0x584af5d52080_0 .net "i_w_address", 9 0, L_0x584af5d7c310; 1 drivers +v0x584af5d52140_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d52230_0 .net "i_w_disp_address", 9 0, L_0x584af5cb6500; alias, 1 drivers +v0x584af5d52360_0 .net "i_w_in", 15 0, L_0x584af5d7e220; alias, 1 drivers +v0x584af5d52400_0 .net "i_w_oe", 0 0, v0x584af5d4f8c0_0; alias, 1 drivers +v0x584af5d524a0_0 .net "i_w_ram_clk", 0 0, v0x584af5d67db0_0; alias, 1 drivers +v0x584af5d52590_0 .net "i_w_we", 0 0, v0x584af5d4f980_0; alias, 1 drivers +v0x584af5d52680_0 .net "l_w_out", 15 0, v0x584af5d51870_0; 1 drivers +v0x584af5d52720_0 .net "o_w_disp_out", 15 0, v0x584af5d51950_0; alias, 1 drivers +v0x584af5d527c0_0 .net "o_w_out", 15 0, L_0x584af5d7c180; alias, 1 drivers +L_0x584af5d7c180 .functor MUXZ 16, L_0x795a1e20d7b0, v0x584af5d51870_0, L_0x584af5d7c070, C4<>; +S_0x584af5d50c10 .scope module, "block_ram_inst" "block_dpram" 10 27, 11 2 0, S_0x584af5cbd240; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_r_out_a"; + .port_info 1 /OUTPUT 16 "o_r_out_b"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 10 "i_w_address_a"; + .port_info 4 /INPUT 10 "i_w_address_b"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_cs_a"; + .port_info 7 /INPUT 1 "i_w_cs_b"; + .port_info 8 /INPUT 1 "i_w_clk_a"; + .port_info 9 /INPUT 1 "i_w_clk_b"; +P_0x584af5cb4f50 .param/l "l_p_depth" 1 11 18, +C4<00000000000000000000010000000000>; +P_0x584af5cb4f90 .param/l "p_address_width" 0 11 4, +C4<00000000000000000000000000001010>; +P_0x584af5cb4fd0 .param/l "p_data_width" 0 11 3, +C4<00000000000000000000000000010000>; +v0x584af5d51070_0 .net "i_w_address_a", 9 0, L_0x584af5d7c310; alias, 1 drivers +v0x584af5d51170_0 .net "i_w_address_b", 9 0, L_0x584af5cb6500; alias, 1 drivers +v0x584af5d51250_0 .net "i_w_clk_a", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d51350_0 .net "i_w_clk_b", 0 0, v0x584af5d67db0_0; alias, 1 drivers +L_0x795a1e20d690 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x584af5d51420_0 .net "i_w_cs_a", 0 0, L_0x795a1e20d690; 1 drivers +L_0x795a1e20d6d8 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x584af5d51510_0 .net "i_w_cs_b", 0 0, L_0x795a1e20d6d8; 1 drivers +v0x584af5d515b0_0 .net "i_w_in", 15 0, L_0x584af5d7e220; alias, 1 drivers +v0x584af5d51650_0 .net "i_w_we", 0 0, v0x584af5d4f980_0; alias, 1 drivers +v0x584af5d51720 .array "l_r_data", 0 1023, 15 0; +v0x584af5d51870_0 .var "o_r_out_a", 15 0; +v0x584af5d51950_0 .var "o_r_out_b", 15 0; +E_0x584af5d50f90 .event posedge, v0x584af5d46850_0; +E_0x584af5d51010 .event posedge, v0x584af5d4d990_0; +S_0x584af5d529e0 .scope module, "l_m_regfile" "regfile" 6 49, 12 3 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /INPUT 3 "i_w_disp_reg"; + .port_info 2 /OUTPUT 16 "o_w_out"; + .port_info 3 /INPUT 16 "i_w_in"; + .port_info 4 /INPUT 3 "i_w_reg"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; + .port_info 7 /INPUT 1 "i_w_reset"; + .port_info 8 /INPUT 1 "i_w_clk"; +P_0x584af5cbdb80 .param/l "l_p_depth" 1 12 21, +C4<00000000000000000000000000001000>; +P_0x584af5cbdbc0 .param/l "p_address_width" 0 12 5, +C4<00000000000000000000000000000011>; +P_0x584af5cbdc00 .param/l "p_data_width" 0 12 4, +C4<00000000000000000000000000010000>; +L_0x584af5cbc290 .functor BUFZ 16, L_0x584af5d78bb0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x584af5d52ed0_0 .net *"_ivl_0", 15 0, L_0x584af5d68880; 1 drivers +v0x584af5d52fd0_0 .net *"_ivl_10", 15 0, L_0x584af5d78bb0; 1 drivers +v0x584af5d530b0_0 .net *"_ivl_12", 4 0, L_0x584af5d78c50; 1 drivers +L_0x795a1e20d0f0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x584af5d531a0_0 .net *"_ivl_15", 1 0, L_0x795a1e20d0f0; 1 drivers +v0x584af5d53280_0 .net *"_ivl_2", 4 0, L_0x584af5d68920; 1 drivers +L_0x795a1e20d060 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x584af5d533b0_0 .net *"_ivl_5", 1 0, L_0x795a1e20d060; 1 drivers +L_0x795a1e20d0a8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d53490_0 .net/2u *"_ivl_6", 15 0, L_0x795a1e20d0a8; 1 drivers +v0x584af5d53570_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d53610_0 .net "i_w_disp_reg", 2 0, L_0x584af5d68770; alias, 1 drivers +v0x584af5d536f0_0 .net "i_w_in", 15 0, L_0x584af5d7e430; alias, 1 drivers +v0x584af5d537b0_0 .net "i_w_oe", 0 0, v0x584af5d4fb20_0; alias, 1 drivers +v0x584af5d53880_0 .net "i_w_reg", 2 0, v0x584af5d4fa40_0; alias, 1 drivers +v0x584af5d53950_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d539f0_0 .net "i_w_we", 0 0, v0x584af5d4fbe0_0; alias, 1 drivers +v0x584af5d53a90_0 .var "index", 3 0; +v0x584af5d53b30 .array "l_r_data", 0 7, 15 0; +v0x584af5d53bd0_0 .net "o_w_disp_out", 15 0, L_0x584af5cbc290; alias, 1 drivers +v0x584af5d53cb0_0 .net "o_w_out", 15 0, L_0x584af5d78a70; alias, 1 drivers +L_0x584af5d68880 .array/port v0x584af5d53b30, L_0x584af5d68920; +L_0x584af5d68920 .concat [ 3 2 0 0], v0x584af5d4fa40_0, L_0x795a1e20d060; +L_0x584af5d78a70 .functor MUXZ 16, L_0x795a1e20d0a8, L_0x584af5d68880, v0x584af5d4fb20_0, C4<>; +L_0x584af5d78bb0 .array/port v0x584af5d53b30, L_0x584af5d78c50; +L_0x584af5d78c50 .concat [ 3 2 0 0], L_0x584af5d68770, L_0x795a1e20d0f0; +S_0x584af5d53ef0 .scope module, "l_m_register_flags" "register" 6 126, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d54080 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5d2b760 .functor BUFZ 16, v0x584af5d54540_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d80a90 .functor BUFT 16, v0x584af5d54540_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x584af5d54190_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d54250_0 .net "i_w_in", 15 0, L_0x584af5d7c980; alias, 1 drivers +L_0x795a1e20d210 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x584af5d54330_0 .net "i_w_oe", 0 0, L_0x795a1e20d210; 1 drivers +v0x584af5d54400_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d544a0_0 .net "i_w_we", 0 0, v0x584af5d4f080_0; alias, 1 drivers +v0x584af5d54540_0 .var "l_r_data", 15 0; +v0x584af5d54600_0 .net "o_w_disp_out", 15 0, L_0x584af5d2b760; alias, 1 drivers +v0x584af5d546e0_0 .net "o_w_out", 15 0, L_0x584af5d80a90; alias, 1 drivers +S_0x584af5d548d0 .scope module, "l_m_register_input_output_address" "register" 6 175, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d54ab0 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5d79770 .functor BUFZ 16, v0x584af5d551e0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x795a1e20d2e8 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d54cc0_0 .net/2u *"_ivl_0", 15 0, L_0x795a1e20d2e8; 1 drivers +v0x584af5d54dc0_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d54e80_0 .net "i_w_in", 15 0, L_0x584af5d7e750; alias, 1 drivers +v0x584af5d54f80_0 .net "i_w_oe", 0 0, v0x584af5d4f2c0_0; alias, 1 drivers +v0x584af5d55050_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d55140_0 .net "i_w_we", 0 0, v0x584af5d4f380_0; alias, 1 drivers +v0x584af5d551e0_0 .var "l_r_data", 15 0; +v0x584af5d55280_0 .net "o_w_disp_out", 15 0, L_0x584af5d79770; alias, 1 drivers +v0x584af5d55320_0 .net "o_w_out", 15 0, L_0x584af5d79630; alias, 1 drivers +L_0x584af5d79630 .functor MUXZ 16, L_0x795a1e20d2e8, v0x584af5d551e0_0, v0x584af5d4f2c0_0, C4<>; +S_0x584af5d555b0 .scope module, "l_m_register_instruction_register" "register" 6 100, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d53320 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5cb3880 .functor BUFZ 16, v0x584af5d55d10_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x584af5d809d0 .functor BUFT 16, v0x584af5d55d10_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +v0x584af5d55900_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d559c0_0 .net "i_w_in", 15 0, L_0x584af5d7e9c0; alias, 1 drivers +L_0x795a1e20d180 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>; +v0x584af5d55ab0_0 .net "i_w_oe", 0 0, L_0x795a1e20d180; 1 drivers +v0x584af5d55b80_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d55c20_0 .net "i_w_we", 0 0, v0x584af5d4f500_0; alias, 1 drivers +v0x584af5d55d10_0 .var "l_r_data", 15 0; +v0x584af5d55db0_0 .net "o_w_disp_out", 15 0, L_0x584af5cb3880; alias, 1 drivers +v0x584af5d55e90_0 .net "o_w_out", 15 0, L_0x584af5d809d0; alias, 1 drivers +S_0x584af5d56080 .scope module, "l_m_register_memory_address" "register" 6 153, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d52b70 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5d79520 .functor BUFZ 16, v0x584af5d56940_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x795a1e20d2a0 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d56420_0 .net/2u *"_ivl_0", 15 0, L_0x795a1e20d2a0; 1 drivers +v0x584af5d56520_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d565e0_0 .net "i_w_in", 15 0, L_0x584af5d7e670; alias, 1 drivers +v0x584af5d566e0_0 .net "i_w_oe", 0 0, v0x584af5d4f5c0_0; alias, 1 drivers +v0x584af5d567b0_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d568a0_0 .net "i_w_we", 0 0, v0x584af5d4f680_0; alias, 1 drivers +v0x584af5d56940_0 .var "l_r_data", 15 0; +v0x584af5d569e0_0 .net "o_w_disp_out", 15 0, L_0x584af5d79520; alias, 1 drivers +v0x584af5d56a80_0 .net "o_w_out", 15 0, L_0x584af5d793e0; alias, 1 drivers +L_0x584af5d793e0 .functor MUXZ 16, L_0x795a1e20d2a0, v0x584af5d56940_0, v0x584af5d4f5c0_0, C4<>; +S_0x584af5d56c80 .scope module, "l_m_register_program_counter" "register" 6 75, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d56e10 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5cb8860 .functor BUFZ 16, v0x584af5d57650_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x795a1e20d138 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d57020_0 .net/2u *"_ivl_0", 15 0, L_0x795a1e20d138; 1 drivers +v0x584af5d57120_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d572f0_0 .net "i_w_in", 15 0, L_0x584af5d7e530; alias, 1 drivers +v0x584af5d573f0_0 .net "i_w_oe", 0 0, v0x584af5d4f740_0; alias, 1 drivers +v0x584af5d574c0_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d575b0_0 .net "i_w_we", 0 0, v0x584af5d4f800_0; alias, 1 drivers +v0x584af5d57650_0 .var "l_r_data", 15 0; +v0x584af5d576f0_0 .net "o_w_disp_out", 15 0, L_0x584af5cb8860; alias, 1 drivers +v0x584af5d57790_0 .net "o_w_out", 15 0, L_0x584af5d78e80; alias, 1 drivers +L_0x584af5d78e80 .functor MUXZ 16, L_0x795a1e20d138, v0x584af5d57650_0, v0x584af5d4f740_0, C4<>; +S_0x584af5d57980 .scope module, "l_m_register_t1" "register" 6 197, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d57b10 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5d799b0 .functor BUFZ 16, v0x584af5d582c0_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x795a1e20d330 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d57c90_0 .net/2u *"_ivl_0", 15 0, L_0x795a1e20d330; 1 drivers +v0x584af5d57d90_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d57e50_0 .net "i_w_in", 15 0, L_0x584af5d7e8d0; alias, 1 drivers +v0x584af5d57f50_0 .net "i_w_oe", 0 0, v0x584af5d4fca0_0; alias, 1 drivers +v0x584af5d58020_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d58220_0 .net "i_w_we", 0 0, v0x584af5d4fd60_0; alias, 1 drivers +v0x584af5d582c0_0 .var "l_r_data", 15 0; +v0x584af5d58360_0 .net "o_w_disp_out", 15 0, L_0x584af5d799b0; alias, 1 drivers +v0x584af5d58400_0 .net "o_w_out", 15 0, L_0x584af5d798a0; alias, 1 drivers +L_0x584af5d798a0 .functor MUXZ 16, L_0x795a1e20d330, v0x584af5d582c0_0, v0x584af5d4fca0_0, C4<>; +S_0x584af5d585f0 .scope module, "l_m_register_t2" "register" 6 219, 13 2 0, S_0x584af5cbbb70; + .timescale 0 0; + .port_info 0 /OUTPUT 16 "o_w_disp_out"; + .port_info 1 /OUTPUT 16 "o_w_out"; + .port_info 2 /INPUT 16 "i_w_in"; + .port_info 3 /INPUT 1 "i_w_clk"; + .port_info 4 /INPUT 1 "i_w_reset"; + .port_info 5 /INPUT 1 "i_w_we"; + .port_info 6 /INPUT 1 "i_w_oe"; +P_0x584af5d58780 .param/l "p_data_width" 0 13 3, +C4<00000000000000000000000000010000>; +L_0x584af5d79bf0 .functor BUFZ 16, v0x584af5d58e20_0, C4<0000000000000000>, C4<0000000000000000>, C4<0000000000000000>; +L_0x795a1e20d378 .functor BUFT 1, C4<0000000000000000>, C4<0>, C4<0>, C4<0>; +v0x584af5d58900_0 .net/2u *"_ivl_0", 15 0, L_0x795a1e20d378; 1 drivers +v0x584af5d58a00_0 .net "i_w_clk", 0 0, v0x584af5d67e70_0; alias, 1 drivers +v0x584af5d58ac0_0 .net "i_w_in", 15 0, L_0x584af5d7e6e0; alias, 1 drivers +v0x584af5d58bc0_0 .net "i_w_oe", 0 0, v0x584af5d4fe20_0; alias, 1 drivers +v0x584af5d58c90_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d58d80_0 .net "i_w_we", 0 0, v0x584af5d4fee0_0; alias, 1 drivers +v0x584af5d58e20_0 .var "l_r_data", 15 0; +v0x584af5d58ec0_0 .net "o_w_disp_out", 15 0, L_0x584af5d79bf0; alias, 1 drivers +v0x584af5d58f60_0 .net "o_w_out", 15 0, L_0x584af5d79ae0; alias, 1 drivers +L_0x584af5d79ae0 .functor MUXZ 16, L_0x795a1e20d378, v0x584af5d58e20_0, v0x584af5d4fe20_0, C4<>; +S_0x584af5d5fd70 .scope module, "l_m_debouncer_next" "debouncer" 4 66, 14 1 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "o_w_out"; + .port_info 1 /INPUT 1 "i_w_in"; + .port_info 2 /INPUT 1 "i_w_clk"; + .port_info 3 /INPUT 1 "i_w_reset"; +P_0x584af5d59920 .param/l "l_p_counter_width" 1 14 11, +C4<00000000000000000000000000000000>; +P_0x584af5d59960 .param/l "p_no_cycles" 0 14 2, +C4<00000000000000000000000000000001>; +v0x584af5d60080_0 .net "i_w_clk", 0 0, v0x584af5d67db0_0; alias, 1 drivers +v0x584af5d60120_0 .net "i_w_in", 0 0, v0x584af5d67fd0_0; alias, 1 drivers +v0x584af5d601e0_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d60280_0 .var "l_r_counter", -1 0; +v0x584af5d60340_0 .var "o_w_out", 0 0; +S_0x584af5d60480 .scope module, "l_m_debouncer_prev" "debouncer" 4 75, 14 1 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "o_w_out"; + .port_info 1 /INPUT 1 "i_w_in"; + .port_info 2 /INPUT 1 "i_w_clk"; + .port_info 3 /INPUT 1 "i_w_reset"; +P_0x584af5d60660 .param/l "l_p_counter_width" 1 14 11, +C4<00000000000000000000000000000000>; +P_0x584af5d606a0 .param/l "p_no_cycles" 0 14 2, +C4<00000000000000000000000000000001>; +v0x584af5d60820_0 .net "i_w_clk", 0 0, v0x584af5d67db0_0; alias, 1 drivers +v0x584af5d608e0_0 .net "i_w_in", 0 0, v0x584af5d68070_0; alias, 1 drivers +v0x584af5d609a0_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d60a40_0 .var "l_r_counter", -1 0; +v0x584af5d60b00_0 .var "o_w_out", 0 0; +S_0x584af5d60c90 .scope module, "l_m_opt_button_next" "otp_button" 4 86, 15 1 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "o_w_button_press"; + .port_info 1 /INPUT 1 "i_w_clk"; + .port_info 2 /INPUT 1 "i_w_button"; +P_0x584af5cbda80 .param/l "l_p_state_ButtonFirstPressed" 1 15 8, C4<01>; +P_0x584af5cbdac0 .param/l "l_p_state_ButtonPressed" 1 15 9, C4<10>; +P_0x584af5cbdb00 .param/l "l_p_state_ButtonReleased" 1 15 7, C4<00>; +L_0x795a1e20d8d0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v0x584af5d61120_0 .net/2u *"_ivl_0", 1 0, L_0x795a1e20d8d0; 1 drivers +v0x584af5d61220_0 .net "i_w_button", 0 0, v0x584af5d60340_0; alias, 1 drivers +v0x584af5d612e0_0 .net "i_w_clk", 0 0, v0x584af5d469e0_0; alias, 1 drivers +v0x584af5d61380_0 .var "l_r_next_state", 1 0; +v0x584af5d61420_0 .var "l_r_state", 1 0; +v0x584af5d61510_0 .net "o_w_button_press", 0 0, L_0x584af5d80140; alias, 1 drivers +E_0x584af5d54150 .event edge, v0x584af5d61420_0, v0x584af5d60340_0; +E_0x584af5d610c0 .event posedge, v0x584af5d469e0_0; +L_0x584af5d80140 .cmp/eq 2, v0x584af5d61420_0, L_0x795a1e20d8d0; +S_0x584af5d61650 .scope module, "l_m_opt_button_prev" "otp_button" 4 91, 15 1 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 1 "o_w_button_press"; + .port_info 1 /INPUT 1 "i_w_clk"; + .port_info 2 /INPUT 1 "i_w_button"; +P_0x584af5cbf250 .param/l "l_p_state_ButtonFirstPressed" 1 15 8, C4<01>; +P_0x584af5cbf290 .param/l "l_p_state_ButtonPressed" 1 15 9, C4<10>; +P_0x584af5cbf2d0 .param/l "l_p_state_ButtonReleased" 1 15 7, C4<00>; +L_0x795a1e20d918 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>; +v0x584af5d61a50_0 .net/2u *"_ivl_0", 1 0, L_0x795a1e20d918; 1 drivers +v0x584af5d61b50_0 .net "i_w_button", 0 0, v0x584af5d60b00_0; alias, 1 drivers +v0x584af5d61c10_0 .net "i_w_clk", 0 0, v0x584af5d469e0_0; alias, 1 drivers +v0x584af5d61d00_0 .var "l_r_next_state", 1 0; +v0x584af5d61da0_0 .var "l_r_state", 1 0; +v0x584af5d61eb0_0 .net "o_w_button_press", 0 0, L_0x584af5d80440; alias, 1 drivers +E_0x584af5d619d0 .event edge, v0x584af5d61da0_0, v0x584af5d60b00_0; +L_0x584af5d80440 .cmp/eq 2, v0x584af5d61da0_0, L_0x795a1e20d918; +S_0x584af5d61ff0 .scope module, "l_m_state_display" "state_display" 4 102, 16 1 0, S_0x584af5cb28a0; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "o_w_7_led_seg"; + .port_info 1 /OUTPUT 8 "o_w_an"; + .port_info 2 /INPUT 4 "i_w_regs_addr"; + .port_info 3 /INPUT 16 "i_w_regs"; + .port_info 4 /INPUT 16 "i_w_ram"; + .port_info 5 /INPUT 16 "i_w_state"; + .port_info 6 /INPUT 16 "i_w_bus"; + .port_info 7 /INPUT 1 "i_w_next"; + .port_info 8 /INPUT 1 "i_w_prev"; + .port_info 9 /INPUT 1 "i_w_clk"; + .port_info 10 /INPUT 1 "i_w_reset"; +P_0x584af5d621d0 .param/l "addr_io" 1 16 24, C4<0000000000111100>; +P_0x584af5d62210 .param/l "addr_reg" 1 16 23, C4<0000000000110100>; +P_0x584af5d62250 .param/l "addr_sum" 1 16 22, C4<0000000000110000>; +P_0x584af5d62290 .param/l "decode" 1 16 21, C4<0000000000100000>; +P_0x584af5d622d0 .param/l "exec_1op" 1 16 32, C4<0000000001110000>; +P_0x584af5d62310 .param/l "exec_2op" 1 16 33, C4<0000000001110100>; +P_0x584af5d62350 .param/l "exec_transf" 1 16 34, C4<0000000001111000>; +P_0x584af5d62390 .param/l "fetch" 1 16 20, C4<0000000000010000>; +P_0x584af5d623d0 .param/l "inc_cp" 1 16 38, C4<0000000010010000>; +P_0x584af5d62410 .param/l "l_p_BA_address" 1 16 48, C4<0110>; +P_0x584af5d62450 .param/l "l_p_BB_address" 1 16 49, C4<0111>; +P_0x584af5d62490 .param/l "l_p_FR_address" 1 16 51, C4<1001>; +P_0x584af5d624d0 .param/l "l_p_IOA_address" 1 16 53, C4<1011>; +P_0x584af5d62510 .param/l "l_p_IR_address" 1 16 56, C4<1110>; +P_0x584af5d62550 .param/l "l_p_MA_address" 1 16 52, C4<1010>; +P_0x584af5d62590 .param/l "l_p_PC_address" 1 16 50, C4<1000>; +P_0x584af5d625d0 .param/l "l_p_RA_address" 1 16 42, C4<0000>; +P_0x584af5d62610 .param/l "l_p_RB_address" 1 16 43, C4<0001>; +P_0x584af5d62650 .param/l "l_p_RC_address" 1 16 44, C4<0010>; +P_0x584af5d62690 .param/l "l_p_SP_address" 1 16 45, C4<0011>; +P_0x584af5d626d0 .param/l "l_p_T1_address" 1 16 54, C4<1100>; +P_0x584af5d62710 .param/l "l_p_T2_address" 1 16 55, C4<1101>; +P_0x584af5d62750 .param/l "l_p_XA_address" 1 16 46, C4<0100>; +P_0x584af5d62790 .param/l "l_p_XB_address" 1 16 47, C4<0101>; +P_0x584af5d627d0 .param/l "l_p_state_BUS" 1 16 65, C4<10>; +P_0x584af5d62810 .param/l "l_p_state_FSM" 1 16 67, C4<11>; +P_0x584af5d62850 .param/l "l_p_state_RAM" 1 16 63, C4<01>; +P_0x584af5d62890 .param/l "l_p_state_REGS" 1 16 61, C4<00>; +P_0x584af5d628d0 .param/l "load_dst_mem" 1 16 29, C4<0000000001010100>; +P_0x584af5d62910 .param/l "load_dst_reg" 1 16 28, C4<0000000001010000>; +P_0x584af5d62950 .param/l "load_src_io" 1 16 27, C4<0000000001001100>; +P_0x584af5d62990 .param/l "load_src_mem" 1 16 26, C4<0000000001000100>; +P_0x584af5d629d0 .param/l "load_src_reg" 1 16 25, C4<0000000001000000>; +P_0x584af5d62a10 .param/l "noload_dst_io" 1 16 31, C4<0000000001101100>; +P_0x584af5d62a50 .param/l "noload_dst_reg" 1 16 30, C4<0000000001100000>; +P_0x584af5d62a90 .param/l "p_address_width" 0 16 3, +C4<00000000000000000000000000001010>; +P_0x584af5d62ad0 .param/l "p_data_width" 0 16 2, +C4<00000000000000000000000000010000>; +P_0x584af5d62b10 .param/l "p_regs_address_width" 0 16 4, +C4<00000000000000000000000000000011>; +P_0x584af5d62b50 .param/l "reset" 1 16 19, C4<0000000000000000>; +P_0x584af5d62b90 .param/l "store_io" 1 16 37, C4<0000000010001100>; +P_0x584af5d62bd0 .param/l "store_mem" 1 16 36, C4<0000000010000100>; +P_0x584af5d62c10 .param/l "store_reg" 1 16 35, C4<0000000010000000>; +L_0x584af5d80620 .functor NOT 8, L_0x584af5d80530, C4<00000000>, C4<00000000>, C4<00000000>; +L_0x584af5d80910 .functor BUFZ 8, L_0x584af5d806e0, C4<00000000>, C4<00000000>, C4<00000000>; +v0x584af5d653b0_0 .net *"_ivl_10", 7 0, L_0x584af5d806e0; 1 drivers +v0x584af5d65490_0 .net *"_ivl_12", 4 0, L_0x584af5d80780; 1 drivers +L_0x795a1e20d9a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; +v0x584af5d65570_0 .net *"_ivl_15", 1 0, L_0x795a1e20d9a8; 1 drivers +L_0x795a1e20d960 .functor BUFT 1, C4<00000001>, C4<0>, C4<0>, C4<0>; +v0x584af5d65660_0 .net/2s *"_ivl_4", 7 0, L_0x795a1e20d960; 1 drivers +v0x584af5d65740_0 .net *"_ivl_6", 7 0, L_0x584af5d80530; 1 drivers +v0x584af5d65870_0 .net "i_w_bus", 15 0, L_0x584af5d7eac0; alias, 1 drivers +v0x584af5d65980_0 .net "i_w_clk", 0 0, v0x584af5d469e0_0; alias, 1 drivers +v0x584af5d65a20_0 .net "i_w_next", 0 0, L_0x584af5d80140; alias, 1 drivers +v0x584af5d65ac0_0 .net "i_w_prev", 0 0, L_0x584af5d80440; alias, 1 drivers +v0x584af5d65b60_0 .net "i_w_ram", 15 0, v0x584af5d51950_0; alias, 1 drivers +v0x584af5d65c00_0 .net "i_w_regs", 15 0, L_0x584af5d7be70; alias, 1 drivers +v0x584af5d65cd0_0 .net "i_w_regs_addr", 3 0, L_0x584af5d684d0; alias, 1 drivers +v0x584af5d65da0_0 .net "i_w_reset", 0 0, v0x584af5d681b0_0; alias, 1 drivers +v0x584af5d65e40_0 .net "i_w_state", 15 0, L_0x584af5d7f6d0; alias, 1 drivers +v0x584af5d65ee0_0 .var "l_r_digit", 2 0; +v0x584af5d65fc0 .array "l_r_digit_7seg", 0 7, 7 0; +v0x584af5d66080 .array "l_r_in", 0 3, 3 0; +v0x584af5d66310_0 .var "l_r_next_state", 1 0; +v0x584af5d663b0_0 .var "l_r_state", 1 0; +v0x584af5d66450_0 .net "l_w_7_led_seg_0", 7 0, v0x584af5d643c0_0; 1 drivers +v0x584af5d66540_0 .net "l_w_7_led_seg_1", 7 0, v0x584af5d648a0_0; 1 drivers +v0x584af5d66610_0 .net "l_w_7_led_seg_2", 7 0, v0x584af5d64d90_0; 1 drivers +v0x584af5d666e0_0 .net "l_w_7_led_seg_3", 7 0, v0x584af5d65270_0; 1 drivers +v0x584af5d667b0_0 .net "o_w_7_led_seg", 7 0, L_0x584af5d80910; alias, 1 drivers +v0x584af5d66870_0 .net "o_w_an", 7 0, L_0x584af5d80620; alias, 1 drivers +E_0x584af5d63e50/0 .event edge, v0x584af5d663b0_0, v0x584af5d4ffa0_0, v0x584af5d643c0_0, v0x584af5d648a0_0; +E_0x584af5d63e50/1 .event edge, v0x584af5d64d90_0, v0x584af5d65270_0; +E_0x584af5d63e50 .event/or E_0x584af5d63e50/0, E_0x584af5d63e50/1; +E_0x584af5d63ef0/0 .event edge, v0x584af5d663b0_0, v0x584af5d5fa30_0, v0x584af5d5c080_0, v0x584af5d51950_0; +E_0x584af5d63ef0/1 .event edge, v0x584af5d4a6d0_0; +E_0x584af5d63ef0 .event/or E_0x584af5d63ef0/0, E_0x584af5d63ef0/1; +E_0x584af5d63f60 .event edge, v0x584af5d61510_0, v0x584af5d663b0_0, v0x584af5d61eb0_0; +E_0x584af5d63fc0/0 .event negedge, v0x584af5d46910_0; +E_0x584af5d63fc0/1 .event posedge, v0x584af5d469e0_0; +E_0x584af5d63fc0 .event/or E_0x584af5d63fc0/0, E_0x584af5d63fc0/1; +L_0x584af5d80530 .shift/l 8, L_0x795a1e20d960, v0x584af5d65ee0_0; +L_0x584af5d806e0 .array/port v0x584af5d65fc0, L_0x584af5d80780; +L_0x584af5d80780 .concat [ 3 2 0 0], v0x584af5d65ee0_0, L_0x795a1e20d9a8; +S_0x584af5d64050 .scope module, "led7hex_inst_0" "led7hex" 16 243, 17 1 0, S_0x584af5d61ff0; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "l_r_led7"; + .port_info 1 /INPUT 4 "i_w_value"; +v0x584af5d66080_0 .array/port v0x584af5d66080, 0; +v0x584af5d642c0_0 .net "i_w_value", 3 0, v0x584af5d66080_0; 1 drivers +v0x584af5d643c0_0 .var "l_r_led7", 7 0; +E_0x584af5d64240 .event edge, v0x584af5d642c0_0; +S_0x584af5d64500 .scope module, "led7hex_inst_1" "led7hex" 16 248, 17 1 0, S_0x584af5d61ff0; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "l_r_led7"; + .port_info 1 /INPUT 4 "i_w_value"; +v0x584af5d66080_1 .array/port v0x584af5d66080, 1; +v0x584af5d647a0_0 .net "i_w_value", 3 0, v0x584af5d66080_1; 1 drivers +v0x584af5d648a0_0 .var "l_r_led7", 7 0; +E_0x584af5d64720 .event edge, v0x584af5d647a0_0; +S_0x584af5d649e0 .scope module, "led7hex_inst_2" "led7hex" 16 253, 17 1 0, S_0x584af5d61ff0; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "l_r_led7"; + .port_info 1 /INPUT 4 "i_w_value"; +v0x584af5d66080_2 .array/port v0x584af5d66080, 2; +v0x584af5d64c90_0 .net "i_w_value", 3 0, v0x584af5d66080_2; 1 drivers +v0x584af5d64d90_0 .var "l_r_led7", 7 0; +E_0x584af5d64c30 .event edge, v0x584af5d64c90_0; +S_0x584af5d64ed0 .scope module, "led7hex_inst_3" "led7hex" 16 258, 17 1 0, S_0x584af5d61ff0; + .timescale 0 0; + .port_info 0 /OUTPUT 8 "l_r_led7"; + .port_info 1 /INPUT 4 "i_w_value"; +v0x584af5d66080_3 .array/port v0x584af5d66080, 3; +v0x584af5d65170_0 .net "i_w_value", 3 0, v0x584af5d66080_3; 1 drivers +v0x584af5d65270_0 .var "l_r_led7", 7 0; +E_0x584af5d650f0 .event edge, v0x584af5d65170_0; + .scope S_0x584af5d2b7d0; +T_0 ; + %wait E_0x584af5bb1e10; + %load/vec4 v0x584af5cb5780_0; + %flag_set/vec4 8; + %jmp/0xz T_0.0, 8; + %load/vec4 v0x584af5cb5a10_0; + %flag_set/vec4 8; + %jmp/0xz T_0.2, 8; + %load/vec4 v0x584af5cb7d70_0; + %load/vec4 v0x584af5cb3a40_0; + %pad/u 22; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x584af5bc6cd0, 0, 4; + %load/vec4 v0x584af5cb7d70_0; + %assign/vec4 v0x584af5d46010_0, 0; + %jmp T_0.3; +T_0.2 ; + %load/vec4 v0x584af5cb3a40_0; + %pad/u 22; + %ix/vec4 4; + %load/vec4a v0x584af5bc6cd0, 4; + %assign/vec4 v0x584af5d46010_0, 0; +T_0.3 ; +T_0.0 ; + %jmp T_0; + .thread T_0; + .scope S_0x584af5d529e0; +T_1 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d53950_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d53a90_0, 0, 4; +T_1.2 ; + %load/vec4 v0x584af5d53a90_0; + %pad/u 32; + %cmpi/u 8, 0, 32; + %jmp/0xz T_1.3, 5; + %pushi/vec4 0, 0, 16; + %load/vec4 v0x584af5d53a90_0; + %pad/u 5; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x584af5d53b30, 0, 4; + %load/vec4 v0x584af5d53a90_0; + %addi 1, 0, 4; + %store/vec4 v0x584af5d53a90_0, 0, 4; + %jmp T_1.2; +T_1.3 ; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x584af5d539f0_0; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x584af5d536f0_0; + %load/vec4 v0x584af5d53880_0; + %pad/u 5; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x584af5d53b30, 0, 4; +T_1.4 ; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x584af5d56c80; +T_2 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d574c0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_2.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d57650_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0x584af5d575b0_0; + %flag_set/vec4 8; + %jmp/0xz T_2.2, 8; + %load/vec4 v0x584af5d572f0_0; + %assign/vec4 v0x584af5d57650_0, 0; +T_2.2 ; +T_2.1 ; + %jmp T_2; + .thread T_2; + .scope S_0x584af5d555b0; +T_3 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d55b80_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_3.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d55d10_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0x584af5d55c20_0; + %flag_set/vec4 8; + %jmp/0xz T_3.2, 8; + %load/vec4 v0x584af5d559c0_0; + %assign/vec4 v0x584af5d55d10_0, 0; +T_3.2 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0x584af5d53ef0; +T_4 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d54400_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_4.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d54540_0, 0; + %jmp T_4.1; +T_4.0 ; + %load/vec4 v0x584af5d544a0_0; + %flag_set/vec4 8; + %jmp/0xz T_4.2, 8; + %load/vec4 v0x584af5d54250_0; + %assign/vec4 v0x584af5d54540_0, 0; +T_4.2 ; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0x584af5d56080; +T_5 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d567b0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_5.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d56940_0, 0; + %jmp T_5.1; +T_5.0 ; + %load/vec4 v0x584af5d568a0_0; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %load/vec4 v0x584af5d565e0_0; + %assign/vec4 v0x584af5d56940_0, 0; +T_5.2 ; +T_5.1 ; + %jmp T_5; + .thread T_5; + .scope S_0x584af5d548d0; +T_6 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d55050_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_6.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d551e0_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v0x584af5d55140_0; + %flag_set/vec4 8; + %jmp/0xz T_6.2, 8; + %load/vec4 v0x584af5d54e80_0; + %assign/vec4 v0x584af5d551e0_0, 0; +T_6.2 ; +T_6.1 ; + %jmp T_6; + .thread T_6; + .scope S_0x584af5d57980; +T_7 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d58020_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_7.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d582c0_0, 0; + %jmp T_7.1; +T_7.0 ; + %load/vec4 v0x584af5d58220_0; + %flag_set/vec4 8; + %jmp/0xz T_7.2, 8; + %load/vec4 v0x584af5d57e50_0; + %assign/vec4 v0x584af5d582c0_0, 0; +T_7.2 ; +T_7.1 ; + %jmp T_7; + .thread T_7; + .scope S_0x584af5d585f0; +T_8 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d58c90_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_8.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d58e20_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v0x584af5d58d80_0; + %flag_set/vec4 8; + %jmp/0xz T_8.2, 8; + %load/vec4 v0x584af5d58ac0_0; + %assign/vec4 v0x584af5d58e20_0, 0; +T_8.2 ; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_0x584af5d50c10; +T_9 ; + %vpi_call 11 25 "$readmemh", "cram.data", v0x584af5d51720, 32'sb00000000000000000000000000000000, 32'sb00000000000000000000001111111111 {0 0 0}; + %end; + .thread T_9; + .scope S_0x584af5d50c10; +T_10 ; + %wait E_0x584af5d51010; + %load/vec4 v0x584af5d51420_0; + %flag_set/vec4 8; + %jmp/0xz T_10.0, 8; + %load/vec4 v0x584af5d51650_0; + %flag_set/vec4 8; + %jmp/0xz T_10.2, 8; + %load/vec4 v0x584af5d515b0_0; + %load/vec4 v0x584af5d51070_0; + %pad/u 12; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0x584af5d51720, 0, 4; +T_10.2 ; + %load/vec4 v0x584af5d51070_0; + %pad/u 12; + %ix/vec4 4; + %load/vec4a v0x584af5d51720, 4; + %assign/vec4 v0x584af5d51870_0, 0; +T_10.0 ; + %jmp T_10; + .thread T_10; + .scope S_0x584af5d50c10; +T_11 ; + %wait E_0x584af5d50f90; + %load/vec4 v0x584af5d51510_0; + %flag_set/vec4 8; + %jmp/0xz T_11.0, 8; + %load/vec4 v0x584af5d51170_0; + %pad/u 12; + %ix/vec4 4; + %load/vec4a v0x584af5d51720, 4; + %assign/vec4 v0x584af5d51950_0, 0; +T_11.0 ; + %jmp T_11; + .thread T_11; + .scope S_0x584af5cb5de0; +T_12 ; + %wait E_0x584af5d2e4d0; + %load/vec4 v0x584af5d486c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_12.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_12.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_12.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_12.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_12.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_12.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_12.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_12.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_12.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_12.9, 6; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.0 ; + %load/vec4 v0x584af5d483e0_0; + %pad/u 17; + %load/vec4 v0x584af5d484d0_0; + %pad/u 17; + %add; + %load/vec4 v0x584af5d48320_0; + %pad/u 17; + %add; + %split/vec4 16; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d489e0_0; + %parti/s 1, 15, 5; + %cmp/ne; + %flag_get/vec4 4; + %and; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.1 ; + %load/vec4 v0x584af5d483e0_0; + %pad/u 17; + %load/vec4 v0x584af5d484d0_0; + %pad/u 17; + %sub; + %load/vec4 v0x584af5d48320_0; + %pad/u 17; + %sub; + %split/vec4 16; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %cmp/ne; + %flag_get/vec4 4; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d489e0_0; + %parti/s 1, 15, 5; + %cmp/ne; + %flag_get/vec4 4; + %and; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.2 ; + %load/vec4 v0x584af5d484d0_0; + %pad/u 17; + %load/vec4 v0x584af5d483e0_0; + %pad/u 17; + %sub; + %load/vec4 v0x584af5d48320_0; + %pad/u 17; + %sub; + %split/vec4 16; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %cmp/ne; + %flag_get/vec4 4; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d489e0_0; + %parti/s 1, 15, 5; + %cmp/ne; + %flag_get/vec4 4; + %and; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.3 ; + %load/vec4 v0x584af5d483e0_0; + %load/vec4 v0x584af5d484d0_0; + %or; + %inv; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.4 ; + %load/vec4 v0x584af5d483e0_0; + %load/vec4 v0x584af5d484d0_0; + %and; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.5 ; + %load/vec4 v0x584af5d483e0_0; + %load/vec4 v0x584af5d484d0_0; + %or; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.6 ; + %load/vec4 v0x584af5d483e0_0; + %load/vec4 v0x584af5d484d0_0; + %xor; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.7 ; + %load/vec4 v0x584af5d483e0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %load/vec4 v0x584af5d484d0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftl 4; + %or; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %or; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %load/vec4 v0x584af5d489e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d487a0_0; + %cmp/ne; + %flag_get/vec4 4; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.8 ; + %load/vec4 v0x584af5d483e0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %load/vec4 v0x584af5d484d0_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %shiftr 4; + %or; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 0, 2; + %or; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %or; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.9 ; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d483e0_0; + %parti/s 15, 1, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 15, 5; + %load/vec4 v0x584af5d484d0_0; + %parti/s 15, 1, 2; + %concat/vec4; draw_concat_vec4 + %or; + %store/vec4 v0x584af5d489e0_0, 0, 16; + %load/vec4 v0x584af5d483e0_0; + %parti/s 1, 0, 2; + %load/vec4 v0x584af5d484d0_0; + %parti/s 1, 0, 2; + %or; + %store/vec4 v0x584af5d487a0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d48860_0, 0, 1; + %jmp T_12.11; +T_12.11 ; + %pop/vec4 1; + %load/vec4 v0x584af5d489e0_0; + %pad/u 32; + %pushi/vec4 0, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %store/vec4 v0x584af5d48b80_0, 0, 1; + %load/vec4 v0x584af5d489e0_0; + %parti/s 1, 15, 5; + %store/vec4 v0x584af5d48ac0_0, 0, 1; + %load/vec4 v0x584af5d489e0_0; + %xnor/r; + %store/vec4 v0x584af5d48920_0, 0, 1; + %jmp T_12; + .thread T_12, $push; + .scope S_0x584af5cb4710; +T_13 ; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4e6d0_0, 0, 16; + %end; + .thread T_13; + .scope S_0x584af5cb4710; +T_14 ; + %wait E_0x584af5d4cba0; + %load/vec4 v0x584af5d4dc10_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_14.0, 8; + %pushi/vec4 0, 0, 16; + %assign/vec4 v0x584af5d4e6d0_0, 0; + %jmp T_14.1; +T_14.0 ; + %load/vec4 v0x584af5d4e7b0_0; + %assign/vec4 v0x584af5d4e6d0_0, 0; + %load/vec4 v0x584af5d4e6d0_0; + %cmpi/e 32, 0, 16; + %jmp/0xz T_14.2, 4; + %load/vec4 v0x584af5d4e430_0; + %assign/vec4 v0x584af5d4e350_0, 0; + %load/vec4 v0x584af5d4def0_0; + %assign/vec4 v0x584af5d4de10_0, 0; + %load/vec4 v0x584af5d4e0b0_0; + %assign/vec4 v0x584af5d4dfd0_0, 0; + %load/vec4 v0x584af5d4e5f0_0; + %assign/vec4 v0x584af5d4e510_0, 0; + %load/vec4 v0x584af5d4dd50_0; + %assign/vec4 v0x584af5d4dcb0_0, 0; + %load/vec4 v0x584af5d4e270_0; + %assign/vec4 v0x584af5d4e190_0, 0; +T_14.2 ; +T_14.1 ; + %jmp T_14; + .thread T_14; + .scope S_0x584af5cb4710; +T_15 ; + %wait E_0x584af5b8bd70; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4e430_0, 0, 16; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4def0_0, 0, 16; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4e0b0_0, 0, 16; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4e5f0_0, 0, 16; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4dd50_0, 0, 1; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x584af5d4e270_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f8c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f980_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f140_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f200_0, 0, 1; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fb20_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fbe0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f740_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f800_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4efe0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4ef40_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f080_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f5c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f680_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f2c0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f380_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f440_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4f500_0, 0, 1; + %load/vec4 v0x584af5d4e6d0_0; + %dup/vec4; + %pushi/vec4 0, 0, 16; + %cmp/u; + %jmp/1 T_15.0, 6; + %dup/vec4; + %pushi/vec4 16, 0, 16; + %cmp/u; + %jmp/1 T_15.1, 6; + %dup/vec4; + %pushi/vec4 17, 0, 16; + %cmp/u; + %jmp/1 T_15.2, 6; + %dup/vec4; + %pushi/vec4 18, 0, 16; + %cmp/u; + %jmp/1 T_15.3, 6; + %dup/vec4; + %pushi/vec4 32, 0, 16; + %cmp/u; + %jmp/1 T_15.4, 6; + %dup/vec4; + %pushi/vec4 48, 0, 16; + %cmp/u; + %jmp/1 T_15.5, 6; + %dup/vec4; + %pushi/vec4 49, 0, 16; + %cmp/u; + %jmp/1 T_15.6, 6; + %dup/vec4; + %pushi/vec4 50, 0, 16; + %cmp/u; + %jmp/1 T_15.7, 6; + %dup/vec4; + %pushi/vec4 52, 0, 16; + %cmp/u; + %jmp/1 T_15.8, 6; + %dup/vec4; + %pushi/vec4 60, 0, 16; + %cmp/u; + %jmp/1 T_15.9, 6; + %dup/vec4; + %pushi/vec4 64, 0, 16; + %cmp/u; + %jmp/1 T_15.10, 6; + %dup/vec4; + %pushi/vec4 68, 0, 16; + %cmp/u; + %jmp/1 T_15.11, 6; + %dup/vec4; + %pushi/vec4 69, 0, 16; + %cmp/u; + %jmp/1 T_15.12, 6; + %dup/vec4; + %pushi/vec4 70, 0, 16; + %cmp/u; + %jmp/1 T_15.13, 6; + %dup/vec4; + %pushi/vec4 76, 0, 16; + %cmp/u; + %jmp/1 T_15.14, 6; + %dup/vec4; + %pushi/vec4 77, 0, 16; + %cmp/u; + %jmp/1 T_15.15, 6; + %dup/vec4; + %pushi/vec4 80, 0, 16; + %cmp/u; + %jmp/1 T_15.16, 6; + %dup/vec4; + %pushi/vec4 84, 0, 16; + %cmp/u; + %jmp/1 T_15.17, 6; + %dup/vec4; + %pushi/vec4 85, 0, 16; + %cmp/u; + %jmp/1 T_15.18, 6; + %dup/vec4; + %pushi/vec4 86, 0, 16; + %cmp/u; + %jmp/1 T_15.19, 6; + %dup/vec4; + %pushi/vec4 96, 0, 16; + %cmp/u; + %jmp/1 T_15.20, 6; + %dup/vec4; + %pushi/vec4 108, 0, 16; + %cmp/u; + %jmp/1 T_15.21, 6; + %dup/vec4; + %pushi/vec4 112, 0, 16; + %cmp/u; + %jmp/1 T_15.22, 6; + %dup/vec4; + %pushi/vec4 116, 0, 16; + %cmp/u; + %jmp/1 T_15.23, 6; + %dup/vec4; + %pushi/vec4 120, 0, 16; + %cmp/u; + %jmp/1 T_15.24, 6; + %dup/vec4; + %pushi/vec4 128, 0, 16; + %cmp/u; + %jmp/1 T_15.25, 6; + %dup/vec4; + %pushi/vec4 132, 0, 16; + %cmp/u; + %jmp/1 T_15.26, 6; + %dup/vec4; + %pushi/vec4 133, 0, 16; + %cmp/u; + %jmp/1 T_15.27, 6; + %dup/vec4; + %pushi/vec4 140, 0, 16; + %cmp/u; + %jmp/1 T_15.28, 6; + %dup/vec4; + %pushi/vec4 144, 0, 16; + %cmp/u; + %jmp/1 T_15.29, 6; + %dup/vec4; + %pushi/vec4 145, 0, 16; + %cmp/u; + %jmp/1 T_15.30, 6; + %pushi/vec4 0, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.0 ; + %pushi/vec4 16, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.1 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f740_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f680_0, 0, 1; + %pushi/vec4 17, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.2 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f5c0_0, 0, 1; + %pushi/vec4 18, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.3 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f8c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f500_0, 0, 1; + %pushi/vec4 32, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.4 ; + %load/vec4 v0x584af5d4e890_0; + %parti/s 4, 3, 3; + %cmpi/e 1, 0, 4; + %jmp/0xz T_15.33, 4; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4dd50_0, 0, 1; + %load/vec4 v0x584af5d4eb10_0; + %store/vec4 v0x584af5d4e270_0, 0, 3; + %load/vec4 v0x584af5d4ea30_0; + %cmpi/e 3, 0, 2; + %flag_mov 8, 4; + %jmp/0 T_15.35, 8; + %pushi/vec4 80, 0, 16; + %jmp/1 T_15.36, 8; +T_15.35 ; End of true expr. + %pushi/vec4 84, 0, 16; + %jmp/0 T_15.36, 8; + ; End of false expr. + %blend; +T_15.36; + %store/vec4 v0x584af5d4def0_0, 0, 16; + %load/vec4 v0x584af5d4def0_0; + %store/vec4 v0x584af5d4e430_0, 0, 16; + %pushi/vec4 112, 0, 16; + %store/vec4 v0x584af5d4e0b0_0, 0, 16; + %load/vec4 v0x584af5d4ea30_0; + %cmpi/e 3, 0, 2; + %flag_mov 8, 4; + %jmp/0 T_15.37, 8; + %pushi/vec4 128, 0, 16; + %jmp/1 T_15.38, 8; +T_15.37 ; End of true expr. + %pushi/vec4 132, 0, 16; + %jmp/0 T_15.38, 8; + ; End of false expr. + %blend; +T_15.38; + %store/vec4 v0x584af5d4e5f0_0, 0, 16; + %jmp T_15.34; +T_15.33 ; + %load/vec4 v0x584af5d4e890_0; + %parti/s 3, 4, 4; + %cmpi/e 2, 0, 3; + %jmp/0xz T_15.39, 4; + %load/vec4 v0x584af5d4e970_0; + %store/vec4 v0x584af5d4dd50_0, 0, 1; + %load/vec4 v0x584af5d4eb10_0; + %store/vec4 v0x584af5d4e270_0, 0, 3; + %load/vec4 v0x584af5d4ea30_0; + %cmpi/e 3, 0, 2; + %flag_mov 8, 4; + %load/vec4 v0x584af5d4e970_0; + %pad/u 32; + %cmpi/e 1, 0, 32; + %flag_or 4, 8; + %flag_mov 8, 4; + %jmp/0 T_15.41, 8; + %pushi/vec4 80, 0, 16; + %jmp/1 T_15.42, 8; +T_15.41 ; End of true expr. + %pushi/vec4 84, 0, 16; + %jmp/0 T_15.42, 8; + ; End of false expr. + %blend; +T_15.42; + %store/vec4 v0x584af5d4def0_0, 0, 16; + %load/vec4 v0x584af5d4ea30_0; + %cmpi/e 3, 0, 2; + %flag_mov 8, 4; + %load/vec4 v0x584af5d4e970_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %flag_or 4, 8; + %flag_mov 8, 4; + %jmp/0 T_15.43, 8; + %pushi/vec4 64, 0, 16; + %jmp/1 T_15.44, 8; +T_15.43 ; End of true expr. + %pushi/vec4 68, 0, 16; + %jmp/0 T_15.44, 8; + ; End of false expr. + %blend; +T_15.44; + %store/vec4 v0x584af5d4e430_0, 0, 16; + %pushi/vec4 116, 0, 16; + %store/vec4 v0x584af5d4e0b0_0, 0, 16; + %load/vec4 v0x584af5d4e890_0; + %parti/s 1, 3, 3; + %nor/r; + %flag_set/vec4 8; + %jmp/0 T_15.45, 8; + %pushi/vec4 144, 0, 16; + %jmp/1 T_15.46, 8; +T_15.45 ; End of true expr. + %load/vec4 v0x584af5d4ea30_0; + %cmpi/e 3, 0, 2; + %flag_mov 9, 4; + %load/vec4 v0x584af5d4e970_0; + %pad/u 32; + %cmpi/e 1, 0, 32; + %flag_or 4, 9; + %flag_mov 9, 4; + %jmp/0 T_15.47, 9; + %pushi/vec4 128, 0, 16; + %jmp/1 T_15.48, 9; +T_15.47 ; End of true expr. + %pushi/vec4 132, 0, 16; + %jmp/0 T_15.48, 9; + ; End of false expr. + %blend; +T_15.48; + %jmp/0 T_15.46, 8; + ; End of false expr. + %blend; +T_15.46; + %store/vec4 v0x584af5d4e5f0_0, 0, 16; + %jmp T_15.40; +T_15.39 ; + %load/vec4 v0x584af5d4e890_0; + %parti/s 6, 1, 2; + %cmpi/e 32, 0, 6; + %jmp/0xz T_15.49, 4; + %load/vec4 v0x584af5d4e890_0; + %parti/s 1, 0, 2; + %nor/r; + %flag_set/vec4 8; + %jmp/0 T_15.51, 8; + %pushi/vec4 1, 0, 2; + %jmp/1 T_15.52, 8; +T_15.51 ; End of true expr. + %pushi/vec4 0, 0, 2; + %jmp/0 T_15.52, 8; + ; End of false expr. + %blend; +T_15.52; + %pad/s 1; + %store/vec4 v0x584af5d4dd50_0, 0, 1; + %pushi/vec4 0, 0, 3; + %store/vec4 v0x584af5d4e270_0, 0, 3; + %load/vec4 v0x584af5d4e890_0; + %parti/s 1, 0, 2; + %nor/r; + %flag_set/vec4 8; + %jmp/0 T_15.53, 8; + %pushi/vec4 96, 0, 16; + %jmp/1 T_15.54, 8; +T_15.53 ; End of true expr. + %pushi/vec4 108, 0, 16; + %jmp/0 T_15.54, 8; + ; End of false expr. + %blend; +T_15.54; + %store/vec4 v0x584af5d4def0_0, 0, 16; + %load/vec4 v0x584af5d4e890_0; + %parti/s 1, 0, 2; + %nor/r; + %flag_set/vec4 8; + %jmp/0 T_15.55, 8; + %pushi/vec4 76, 0, 16; + %jmp/1 T_15.56, 8; +T_15.55 ; End of true expr. + %pushi/vec4 64, 0, 16; + %jmp/0 T_15.56, 8; + ; End of false expr. + %blend; +T_15.56; + %store/vec4 v0x584af5d4e430_0, 0, 16; + %pushi/vec4 120, 0, 16; + %store/vec4 v0x584af5d4e0b0_0, 0, 16; + %load/vec4 v0x584af5d4e890_0; + %parti/s 1, 0, 2; + %nor/r; + %flag_set/vec4 8; + %jmp/0 T_15.57, 8; + %pushi/vec4 128, 0, 16; + %jmp/1 T_15.58, 8; +T_15.57 ; End of true expr. + %pushi/vec4 140, 0, 16; + %jmp/0 T_15.58, 8; + ; End of false expr. + %blend; +T_15.58; + %store/vec4 v0x584af5d4e5f0_0, 0, 16; +T_15.49 ; +T_15.40 ; +T_15.34 ; + %load/vec4 v0x584af5d4e890_0; + %parti/s 1, 6, 4; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_15.59, 4; + %load/vec4 v0x584af5d4ea30_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_15.61, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_15.62, 6; + %jmp T_15.63; +T_15.61 ; + %load/vec4 v0x584af5d4ebf0_0; + %parti/s 1, 2, 3; + %flag_set/vec4 8; + %jmp/0 T_15.64, 8; + %pushi/vec4 52, 0, 16; + %jmp/1 T_15.65, 8; +T_15.64 ; End of true expr. + %pushi/vec4 48, 0, 16; + %jmp/0 T_15.65, 8; + ; End of false expr. + %blend; +T_15.65; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.63; +T_15.62 ; + %load/vec4 v0x584af5d4e430_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.63; +T_15.63 ; + %pop/vec4 1; + %jmp T_15.60; +T_15.59 ; + %load/vec4 v0x584af5d4e890_0; + %parti/s 6, 1, 2; + %cmpi/e 32, 0, 6; + %jmp/0xz T_15.66, 4; + %pushi/vec4 60, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; +T_15.66 ; +T_15.60 ; + %jmp T_15.32; +T_15.5 ; + %load/vec4 v0x584af5d4ebf0_0; + %parti/s 1, 1, 2; + %flag_set/vec4 8; + %jmp/0 T_15.68, 8; + %pushi/vec4 7, 0, 3; + %jmp/1 T_15.69, 8; +T_15.68 ; End of true expr. + %pushi/vec4 6, 0, 3; + %jmp/0 T_15.69, 8; + ; End of false expr. + %blend; +T_15.69; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fb20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %pushi/vec4 49, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.6 ; + %load/vec4 v0x584af5d4ebf0_0; + %parti/s 1, 0, 2; + %flag_set/vec4 8; + %jmp/0 T_15.70, 8; + %pushi/vec4 5, 0, 3; + %jmp/1 T_15.71, 8; +T_15.70 ; End of true expr. + %pushi/vec4 4, 0, 3; + %jmp/0 T_15.71, 8; + ; End of false expr. + %blend; +T_15.71; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fb20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %pushi/vec4 50, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.7 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %load/vec4 v0x584af5d4dcb0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.72, 8; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %jmp T_15.73; +T_15.72 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; +T_15.73 ; + %load/vec4 v0x584af5d4e350_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.8 ; + %load/vec4 v0x584af5d4ebf0_0; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fb20_0, 0, 1; + %load/vec4 v0x584af5d4dcb0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.74, 8; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %jmp T_15.75; +T_15.74 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; +T_15.75 ; + %load/vec4 v0x584af5d4e350_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.9 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f440_0, 0, 1; + %load/vec4 v0x584af5d4dcb0_0; + %flag_set/vec4 8; + %jmp/0xz T_15.76, 8; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %jmp T_15.77; +T_15.76 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; +T_15.77 ; + %load/vec4 v0x584af5d4e350_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.10 ; + %load/vec4 v0x584af5d4dcb0_0; + %flag_set/vec4 8; + %jmp/0 T_15.78, 8; + %load/vec4 v0x584af5d4ebf0_0; + %jmp/1 T_15.79, 8; +T_15.78 ; End of true expr. + %load/vec4 v0x584af5d4e190_0; + %jmp/0 T_15.79, 8; + ; End of false expr. + %blend; +T_15.79; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fb20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %load/vec4 v0x584af5d4de10_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.11 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f680_0, 0, 1; + %pushi/vec4 69, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.12 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f5c0_0, 0, 1; + %pushi/vec4 70, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.13 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f8c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %load/vec4 v0x584af5d4de10_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f380_0, 0, 1; + %pushi/vec4 77, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.15 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f2c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f140_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fee0_0, 0, 1; + %load/vec4 v0x584af5d4de10_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.16 ; + %load/vec4 v0x584af5d4dcb0_0; + %flag_set/vec4 8; + %jmp/0 T_15.80, 8; + %load/vec4 v0x584af5d4e190_0; + %jmp/1 T_15.81, 8; +T_15.80 ; End of true expr. + %load/vec4 v0x584af5d4ebf0_0; + %jmp/0 T_15.81, 8; + ; End of false expr. + %blend; +T_15.81; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fb20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %load/vec4 v0x584af5d4dfd0_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.17 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f680_0, 0, 1; + %pushi/vec4 85, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.18 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f5c0_0, 0, 1; + %pushi/vec4 86, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.19 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f8c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %load/vec4 v0x584af5d4dfd0_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.20 ; + %load/vec4 v0x584af5d4dfd0_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.21 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f380_0, 0, 1; + %load/vec4 v0x584af5d4dfd0_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.22 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %load/vec4 v0x584af5d4e890_0; + %parti/s 3, 0, 2; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_15.82, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_15.83, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_15.84, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_15.85, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_15.86, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_15.87, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_15.88, 6; + %jmp T_15.89; +T_15.82 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.83 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.84 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 2, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.85 ; + %pushi/vec4 3, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.86 ; + %pushi/vec4 7, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.87 ; + %pushi/vec4 8, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.88 ; + %pushi/vec4 9, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.89; +T_15.89 ; + %pop/vec4 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4efe0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f080_0, 0, 1; + %load/vec4 v0x584af5d4e510_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.23 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %load/vec4 v0x584af5d4e890_0; + %parti/s 3, 0, 2; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_15.90, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_15.91, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_15.92, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_15.93, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_15.94, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_15.95, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_15.96, 6; + %jmp T_15.97; +T_15.90 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.91 ; + %load/vec4 v0x584af5d4da50_0; + %parti/s 1, 0, 2; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.92 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.93 ; + %load/vec4 v0x584af5d4da50_0; + %parti/s 1, 0, 2; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 1, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.94 ; + %pushi/vec4 4, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.95 ; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.96 ; + %pushi/vec4 6, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %jmp T_15.97; +T_15.97 ; + %pop/vec4 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4efe0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f080_0, 0, 1; + %load/vec4 v0x584af5d4e510_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.24 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %load/vec4 v0x584af5d4e510_0; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.25 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %load/vec4 v0x584af5d4dcb0_0; + %flag_set/vec4 8; + %jmp/0 T_15.98, 8; + %load/vec4 v0x584af5d4e190_0; + %jmp/1 T_15.99, 8; +T_15.98 ; End of true expr. + %load/vec4 v0x584af5d4ebf0_0; + %jmp/0 T_15.99, 8; + ; End of false expr. + %blend; +T_15.99; + %store/vec4 v0x584af5d4fa40_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fbe0_0, 0, 1; + %pushi/vec4 144, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.26 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f5c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f980_0, 0, 1; + %pushi/vec4 133, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.27 ; + %pushi/vec4 144, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.28 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d4fe20_0, 0, 1; + %pushi/vec4 5, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f2c0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f200_0, 0, 1; + %pushi/vec4 144, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.29 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f740_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fd60_0, 0, 1; + %pushi/vec4 145, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.30 ; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4fca0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4f800_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4eda0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d4ecd0_0, 0, 1; + %pushi/vec4 0, 0, 4; + %store/vec4 v0x584af5d4ee70_0, 0, 4; + %pushi/vec4 16, 0, 16; + %store/vec4 v0x584af5d4e7b0_0, 0, 16; + %jmp T_15.32; +T_15.32 ; + %pop/vec4 1; + %jmp T_15; + .thread T_15, $push; + .scope S_0x584af5cb8140; +T_16 ; + %wait E_0x584af5bb23a0; + %load/vec4 v0x584af5d46910_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_16.0, 8; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x584af5d46750_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x584af5d469e0_0, 0; + %jmp T_16.1; +T_16.0 ; + %load/vec4 v0x584af5d46750_0; + %pad/u 32; + %cmpi/e 3, 0, 32; + %jmp/0xz T_16.2, 4; + %pushi/vec4 0, 0, 4; + %assign/vec4 v0x584af5d46750_0, 0; + %load/vec4 v0x584af5d469e0_0; + %inv; + %assign/vec4 v0x584af5d469e0_0, 0; + %jmp T_16.3; +T_16.2 ; + %load/vec4 v0x584af5d46750_0; + %addi 1, 0, 4; + %assign/vec4 v0x584af5d46750_0, 0; +T_16.3 ; +T_16.1 ; + %jmp T_16; + .thread T_16; + .scope S_0x584af5d5fd70; +T_17 ; + %wait E_0x584af5bb23a0; + %load/vec4 v0x584af5d601e0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_17.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d60280_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x584af5d60340_0, 0; + %jmp T_17.1; +T_17.0 ; + %load/vec4 v0x584af5d60120_0; + %load/vec4 v0x584af5d60340_0; + %cmp/e; + %jmp/0xz T_17.2, 4; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d60280_0, 0; + %jmp T_17.3; +T_17.2 ; + %load/vec4 v0x584af5d60280_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_17.4, 4; + %load/vec4 v0x584af5d60120_0; + %assign/vec4 v0x584af5d60340_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d60280_0, 0; + %jmp T_17.5; +T_17.4 ; + %load/vec4 v0x584af5d60280_0; + %addi 1, 0, 2; + %assign/vec4 v0x584af5d60280_0, 0; +T_17.5 ; +T_17.3 ; +T_17.1 ; + %jmp T_17; + .thread T_17; + .scope S_0x584af5d60480; +T_18 ; + %wait E_0x584af5bb23a0; + %load/vec4 v0x584af5d609a0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_18.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d60a40_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0x584af5d60b00_0, 0; + %jmp T_18.1; +T_18.0 ; + %load/vec4 v0x584af5d608e0_0; + %load/vec4 v0x584af5d60b00_0; + %cmp/e; + %jmp/0xz T_18.2, 4; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d60a40_0, 0; + %jmp T_18.3; +T_18.2 ; + %load/vec4 v0x584af5d60a40_0; + %pad/u 32; + %cmpi/e 0, 0, 32; + %jmp/0xz T_18.4, 4; + %load/vec4 v0x584af5d608e0_0; + %assign/vec4 v0x584af5d60b00_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d60a40_0, 0; + %jmp T_18.5; +T_18.4 ; + %load/vec4 v0x584af5d60a40_0; + %addi 1, 0, 2; + %assign/vec4 v0x584af5d60a40_0, 0; +T_18.5 ; +T_18.3 ; +T_18.1 ; + %jmp T_18; + .thread T_18; + .scope S_0x584af5d60c90; +T_19 ; + %wait E_0x584af5d610c0; + %load/vec4 v0x584af5d61380_0; + %assign/vec4 v0x584af5d61420_0, 0; + %jmp T_19; + .thread T_19; + .scope S_0x584af5d60c90; +T_20 ; + %wait E_0x584af5d54150; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; + %load/vec4 v0x584af5d61420_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_20.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_20.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_20.2, 6; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; + %jmp T_20.4; +T_20.0 ; + %load/vec4 v0x584af5d61220_0; + %flag_set/vec4 8; + %jmp/0xz T_20.5, 8; + %pushi/vec4 1, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; + %jmp T_20.6; +T_20.5 ; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; +T_20.6 ; + %jmp T_20.4; +T_20.1 ; + %pushi/vec4 2, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; + %jmp T_20.4; +T_20.2 ; + %load/vec4 v0x584af5d61220_0; + %flag_set/vec4 8; + %jmp/0xz T_20.7, 8; + %pushi/vec4 2, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; + %jmp T_20.8; +T_20.7 ; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61380_0, 0, 2; +T_20.8 ; + %jmp T_20.4; +T_20.4 ; + %pop/vec4 1; + %jmp T_20; + .thread T_20, $push; + .scope S_0x584af5d61650; +T_21 ; + %wait E_0x584af5d610c0; + %load/vec4 v0x584af5d61d00_0; + %assign/vec4 v0x584af5d61da0_0, 0; + %jmp T_21; + .thread T_21; + .scope S_0x584af5d61650; +T_22 ; + %wait E_0x584af5d619d0; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; + %load/vec4 v0x584af5d61da0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_22.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_22.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_22.2, 6; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; + %jmp T_22.4; +T_22.0 ; + %load/vec4 v0x584af5d61b50_0; + %flag_set/vec4 8; + %jmp/0xz T_22.5, 8; + %pushi/vec4 1, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; + %jmp T_22.6; +T_22.5 ; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; +T_22.6 ; + %jmp T_22.4; +T_22.1 ; + %pushi/vec4 2, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; + %jmp T_22.4; +T_22.2 ; + %load/vec4 v0x584af5d61b50_0; + %flag_set/vec4 8; + %jmp/0xz T_22.7, 8; + %pushi/vec4 2, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; + %jmp T_22.8; +T_22.7 ; + %pushi/vec4 0, 0, 2; + %store/vec4 v0x584af5d61d00_0, 0, 2; +T_22.8 ; + %jmp T_22.4; +T_22.4 ; + %pop/vec4 1; + %jmp T_22; + .thread T_22, $push; + .scope S_0x584af5d64050; +T_23 ; + %wait E_0x584af5d64240; + %load/vec4 v0x584af5d642c0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_23.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_23.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_23.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_23.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_23.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_23.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_23.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_23.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_23.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_23.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_23.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_23.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_23.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_23.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_23.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_23.15, 6; + %pushi/vec4 255, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.0 ; + %pushi/vec4 192, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.1 ; + %pushi/vec4 249, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.2 ; + %pushi/vec4 164, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.3 ; + %pushi/vec4 176, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.4 ; + %pushi/vec4 153, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.5 ; + %pushi/vec4 146, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.6 ; + %pushi/vec4 130, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.7 ; + %pushi/vec4 248, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.8 ; + %pushi/vec4 128, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.9 ; + %pushi/vec4 152, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.10 ; + %pushi/vec4 136, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.11 ; + %pushi/vec4 131, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.12 ; + %pushi/vec4 198, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.13 ; + %pushi/vec4 161, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.14 ; + %pushi/vec4 134, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.15 ; + %pushi/vec4 142, 0, 8; + %store/vec4 v0x584af5d643c0_0, 0, 8; + %jmp T_23.17; +T_23.17 ; + %pop/vec4 1; + %jmp T_23; + .thread T_23, $push; + .scope S_0x584af5d64500; +T_24 ; + %wait E_0x584af5d64720; + %load/vec4 v0x584af5d647a0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_24.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_24.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_24.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_24.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_24.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_24.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_24.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_24.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_24.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_24.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_24.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_24.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_24.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_24.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_24.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_24.15, 6; + %pushi/vec4 255, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.0 ; + %pushi/vec4 192, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.1 ; + %pushi/vec4 249, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.2 ; + %pushi/vec4 164, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.3 ; + %pushi/vec4 176, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.4 ; + %pushi/vec4 153, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.5 ; + %pushi/vec4 146, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.6 ; + %pushi/vec4 130, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.7 ; + %pushi/vec4 248, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.8 ; + %pushi/vec4 128, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.9 ; + %pushi/vec4 152, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.10 ; + %pushi/vec4 136, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.11 ; + %pushi/vec4 131, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.12 ; + %pushi/vec4 198, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.13 ; + %pushi/vec4 161, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.14 ; + %pushi/vec4 134, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.15 ; + %pushi/vec4 142, 0, 8; + %store/vec4 v0x584af5d648a0_0, 0, 8; + %jmp T_24.17; +T_24.17 ; + %pop/vec4 1; + %jmp T_24; + .thread T_24, $push; + .scope S_0x584af5d649e0; +T_25 ; + %wait E_0x584af5d64c30; + %load/vec4 v0x584af5d64c90_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_25.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_25.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_25.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_25.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_25.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_25.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_25.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_25.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_25.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_25.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_25.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_25.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_25.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_25.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_25.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_25.15, 6; + %pushi/vec4 255, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.0 ; + %pushi/vec4 192, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.1 ; + %pushi/vec4 249, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.2 ; + %pushi/vec4 164, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.3 ; + %pushi/vec4 176, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.4 ; + %pushi/vec4 153, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.5 ; + %pushi/vec4 146, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.6 ; + %pushi/vec4 130, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.7 ; + %pushi/vec4 248, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.8 ; + %pushi/vec4 128, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.9 ; + %pushi/vec4 152, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.10 ; + %pushi/vec4 136, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.11 ; + %pushi/vec4 131, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.12 ; + %pushi/vec4 198, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.13 ; + %pushi/vec4 161, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.14 ; + %pushi/vec4 134, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.15 ; + %pushi/vec4 142, 0, 8; + %store/vec4 v0x584af5d64d90_0, 0, 8; + %jmp T_25.17; +T_25.17 ; + %pop/vec4 1; + %jmp T_25; + .thread T_25, $push; + .scope S_0x584af5d64ed0; +T_26 ; + %wait E_0x584af5d650f0; + %load/vec4 v0x584af5d65170_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_26.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_26.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_26.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_26.3, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_26.4, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_26.5, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_26.6, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_26.7, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_26.8, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_26.9, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_26.10, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_26.11, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_26.12, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_26.13, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_26.14, 6; + %dup/vec4; + %pushi/vec4 15, 0, 4; + %cmp/u; + %jmp/1 T_26.15, 6; + %pushi/vec4 255, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.0 ; + %pushi/vec4 192, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.1 ; + %pushi/vec4 249, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.2 ; + %pushi/vec4 164, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.3 ; + %pushi/vec4 176, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.4 ; + %pushi/vec4 153, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.5 ; + %pushi/vec4 146, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.6 ; + %pushi/vec4 130, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.7 ; + %pushi/vec4 248, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.8 ; + %pushi/vec4 128, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.9 ; + %pushi/vec4 152, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.10 ; + %pushi/vec4 136, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.11 ; + %pushi/vec4 131, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.12 ; + %pushi/vec4 198, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.13 ; + %pushi/vec4 161, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.14 ; + %pushi/vec4 134, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.15 ; + %pushi/vec4 142, 0, 8; + %store/vec4 v0x584af5d65270_0, 0, 8; + %jmp T_26.17; +T_26.17 ; + %pop/vec4 1; + %jmp T_26; + .thread T_26, $push; + .scope S_0x584af5d61ff0; +T_27 ; + %wait E_0x584af5d63fc0; + %load/vec4 v0x584af5d65da0_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_27.0, 8; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0x584af5d663b0_0, 0; + %pushi/vec4 0, 0, 3; + %assign/vec4 v0x584af5d65ee0_0, 0; + %jmp T_27.1; +T_27.0 ; + %load/vec4 v0x584af5d65ee0_0; + %addi 1, 0, 3; + %assign/vec4 v0x584af5d65ee0_0, 0; + %load/vec4 v0x584af5d66310_0; + %assign/vec4 v0x584af5d663b0_0, 0; +T_27.1 ; + %jmp T_27; + .thread T_27; + .scope S_0x584af5d61ff0; +T_28 ; + %wait E_0x584af5d63f60; + %load/vec4 v0x584af5d65a20_0; + %flag_set/vec4 8; + %jmp/0xz T_28.0, 8; + %load/vec4 v0x584af5d663b0_0; + %addi 1, 0, 2; + %store/vec4 v0x584af5d66310_0, 0, 2; + %jmp T_28.1; +T_28.0 ; + %load/vec4 v0x584af5d65ac0_0; + %flag_set/vec4 8; + %jmp/0xz T_28.2, 8; + %load/vec4 v0x584af5d663b0_0; + %subi 1, 0, 2; + %store/vec4 v0x584af5d66310_0, 0, 2; + %jmp T_28.3; +T_28.2 ; + %load/vec4 v0x584af5d663b0_0; + %store/vec4 v0x584af5d66310_0, 0, 2; +T_28.3 ; +T_28.1 ; + %jmp T_28; + .thread T_28, $push; + .scope S_0x584af5d61ff0; +T_29 ; + %wait E_0x584af5d63ef0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 0, 0, 4; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %pushi/vec4 0, 0, 4; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %pushi/vec4 0, 0, 4; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %pushi/vec4 0, 0, 4; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d663b0_0; + %dup/vec4; + %pushi/vec4 0, 0, 2; + %cmp/u; + %jmp/1 T_29.0, 6; + %dup/vec4; + %pushi/vec4 1, 0, 2; + %cmp/u; + %jmp/1 T_29.1, 6; + %dup/vec4; + %pushi/vec4 2, 0, 2; + %cmp/u; + %jmp/1 T_29.2, 6; + %dup/vec4; + %pushi/vec4 3, 0, 2; + %cmp/u; + %jmp/1 T_29.3, 6; + %jmp T_29.4; +T_29.0 ; + %load/vec4 v0x584af5d65c00_0; + %parti/s 4, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65c00_0; + %parti/s 4, 4, 4; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65c00_0; + %parti/s 4, 8, 5; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65c00_0; + %parti/s 4, 12, 5; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %load/vec4 v0x584af5d65cd0_0; + %dup/vec4; + %pushi/vec4 0, 0, 4; + %cmp/u; + %jmp/1 T_29.5, 6; + %dup/vec4; + %pushi/vec4 1, 0, 4; + %cmp/u; + %jmp/1 T_29.6, 6; + %dup/vec4; + %pushi/vec4 2, 0, 4; + %cmp/u; + %jmp/1 T_29.7, 6; + %dup/vec4; + %pushi/vec4 3, 0, 4; + %cmp/u; + %jmp/1 T_29.8, 6; + %dup/vec4; + %pushi/vec4 4, 0, 4; + %cmp/u; + %jmp/1 T_29.9, 6; + %dup/vec4; + %pushi/vec4 5, 0, 4; + %cmp/u; + %jmp/1 T_29.10, 6; + %dup/vec4; + %pushi/vec4 6, 0, 4; + %cmp/u; + %jmp/1 T_29.11, 6; + %dup/vec4; + %pushi/vec4 7, 0, 4; + %cmp/u; + %jmp/1 T_29.12, 6; + %dup/vec4; + %pushi/vec4 8, 0, 4; + %cmp/u; + %jmp/1 T_29.13, 6; + %dup/vec4; + %pushi/vec4 9, 0, 4; + %cmp/u; + %jmp/1 T_29.14, 6; + %dup/vec4; + %pushi/vec4 10, 0, 4; + %cmp/u; + %jmp/1 T_29.15, 6; + %dup/vec4; + %pushi/vec4 11, 0, 4; + %cmp/u; + %jmp/1 T_29.16, 6; + %dup/vec4; + %pushi/vec4 12, 0, 4; + %cmp/u; + %jmp/1 T_29.17, 6; + %dup/vec4; + %pushi/vec4 13, 0, 4; + %cmp/u; + %jmp/1 T_29.18, 6; + %dup/vec4; + %pushi/vec4 14, 0, 4; + %cmp/u; + %jmp/1 T_29.19, 6; + %jmp T_29.20; +T_29.5 ; + %pushi/vec4 136, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.6 ; + %pushi/vec4 131, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.7 ; + %pushi/vec4 198, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.8 ; + %pushi/vec4 140, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.9 ; + %pushi/vec4 136, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 198, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 240, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.10 ; + %pushi/vec4 131, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 198, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 240, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.11 ; + %pushi/vec4 136, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 131, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.12 ; + %pushi/vec4 131, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 131, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.13 ; + %pushi/vec4 140, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 198, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.14 ; + %pushi/vec4 175, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 142, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.15 ; + %pushi/vec4 136, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 216, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 204, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.16 ; + %pushi/vec4 192, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.17 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 206, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 248, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.18 ; + %pushi/vec4 164, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 206, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 248, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.19 ; + %pushi/vec4 175, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.20; +T_29.20 ; + %pop/vec4 1; + %jmp T_29.4; +T_29.1 ; + %load/vec4 v0x584af5d65b60_0; + %parti/s 4, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65b60_0; + %parti/s 4, 4, 4; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65b60_0; + %parti/s 4, 8, 5; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65b60_0; + %parti/s 4, 12, 5; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %pushi/vec4 216, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 204, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 136, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.4; +T_29.2 ; + %load/vec4 v0x584af5d65870_0; + %parti/s 4, 0, 2; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65870_0; + %parti/s 4, 4, 4; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65870_0; + %parti/s 4, 8, 5; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %load/vec4 v0x584af5d65870_0; + %parti/s 4, 12, 5; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d66080, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 193, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 131, 0, 8; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.4; +T_29.3 ; + %pushi/vec4 216, 0, 8; + %ix/load 4, 4, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 204, 0, 8; + %ix/load 4, 5, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 6, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 142, 0, 8; + %ix/load 4, 7, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_29.4; +T_29.4 ; + %pop/vec4 1; + %jmp T_29; + .thread T_29, $push; + .scope S_0x584af5d61ff0; +T_30 ; + %wait E_0x584af5d63e50; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 255, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %load/vec4 v0x584af5d663b0_0; + %cmpi/e 3, 0, 2; + %jmp/0xz T_30.0, 4; + %load/vec4 v0x584af5d65e40_0; + %dup/vec4; + %pushi/vec4 0, 0, 16; + %cmp/u; + %jmp/1 T_30.2, 6; + %dup/vec4; + %pushi/vec4 16, 0, 16; + %cmp/u; + %jmp/1 T_30.3, 6; + %dup/vec4; + %pushi/vec4 17, 0, 16; + %cmp/u; + %jmp/1 T_30.4, 6; + %dup/vec4; + %pushi/vec4 18, 0, 16; + %cmp/u; + %jmp/1 T_30.5, 6; + %dup/vec4; + %pushi/vec4 32, 0, 16; + %cmp/u; + %jmp/1 T_30.6, 6; + %dup/vec4; + %pushi/vec4 48, 0, 16; + %cmp/u; + %jmp/1 T_30.7, 6; + %dup/vec4; + %pushi/vec4 49, 0, 16; + %cmp/u; + %jmp/1 T_30.8, 6; + %dup/vec4; + %pushi/vec4 50, 0, 16; + %cmp/u; + %jmp/1 T_30.9, 6; + %dup/vec4; + %pushi/vec4 52, 0, 16; + %cmp/u; + %jmp/1 T_30.10, 6; + %dup/vec4; + %pushi/vec4 60, 0, 16; + %cmp/u; + %jmp/1 T_30.11, 6; + %dup/vec4; + %pushi/vec4 64, 0, 16; + %cmp/u; + %jmp/1 T_30.12, 6; + %dup/vec4; + %pushi/vec4 68, 0, 16; + %cmp/u; + %jmp/1 T_30.13, 6; + %dup/vec4; + %pushi/vec4 69, 0, 16; + %cmp/u; + %jmp/1 T_30.14, 6; + %dup/vec4; + %pushi/vec4 70, 0, 16; + %cmp/u; + %jmp/1 T_30.15, 6; + %dup/vec4; + %pushi/vec4 76, 0, 16; + %cmp/u; + %jmp/1 T_30.16, 6; + %dup/vec4; + %pushi/vec4 77, 0, 16; + %cmp/u; + %jmp/1 T_30.17, 6; + %dup/vec4; + %pushi/vec4 80, 0, 16; + %cmp/u; + %jmp/1 T_30.18, 6; + %dup/vec4; + %pushi/vec4 84, 0, 16; + %cmp/u; + %jmp/1 T_30.19, 6; + %dup/vec4; + %pushi/vec4 85, 0, 16; + %cmp/u; + %jmp/1 T_30.20, 6; + %dup/vec4; + %pushi/vec4 86, 0, 16; + %cmp/u; + %jmp/1 T_30.21, 6; + %dup/vec4; + %pushi/vec4 96, 0, 16; + %cmp/u; + %jmp/1 T_30.22, 6; + %dup/vec4; + %pushi/vec4 108, 0, 16; + %cmp/u; + %jmp/1 T_30.23, 6; + %dup/vec4; + %pushi/vec4 112, 0, 16; + %cmp/u; + %jmp/1 T_30.24, 6; + %dup/vec4; + %pushi/vec4 116, 0, 16; + %cmp/u; + %jmp/1 T_30.25, 6; + %dup/vec4; + %pushi/vec4 120, 0, 16; + %cmp/u; + %jmp/1 T_30.26, 6; + %dup/vec4; + %pushi/vec4 128, 0, 16; + %cmp/u; + %jmp/1 T_30.27, 6; + %dup/vec4; + %pushi/vec4 132, 0, 16; + %cmp/u; + %jmp/1 T_30.28, 6; + %dup/vec4; + %pushi/vec4 133, 0, 16; + %cmp/u; + %jmp/1 T_30.29, 6; + %dup/vec4; + %pushi/vec4 140, 0, 16; + %cmp/u; + %jmp/1 T_30.30, 6; + %dup/vec4; + %pushi/vec4 144, 0, 16; + %cmp/u; + %jmp/1 T_30.31, 6; + %dup/vec4; + %pushi/vec4 145, 0, 16; + %cmp/u; + %jmp/1 T_30.32, 6; + %jmp T_30.33; +T_30.2 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.3 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 134, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 142, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.4 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 134, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 142, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.5 ; + %pushi/vec4 164, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 134, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 142, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.6 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 198, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.7 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 136, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.8 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 136, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.9 ; + %pushi/vec4 164, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 136, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.10 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 136, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.11 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 136, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.12 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.13 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.14 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.15 ; + %pushi/vec4 164, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.16 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.17 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.18 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.19 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.20 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.21 ; + %pushi/vec4 164, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 199, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.22 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 171, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.23 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 161, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 171, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.24 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 192, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 134, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.25 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 192, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 164, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 134, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.26 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 206, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 248, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 134, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.27 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 175, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.28 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.29 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 212, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.30 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 135, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 146, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.31 ; + %pushi/vec4 255, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 140, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 198, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.32 ; + %pushi/vec4 249, 0, 8; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 140, 0, 8; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 198, 0, 8; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %pushi/vec4 249, 0, 8; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %jmp T_30.33; +T_30.33 ; + %pop/vec4 1; + %jmp T_30.1; +T_30.0 ; + %load/vec4 v0x584af5d66450_0; + %ix/load 4, 0, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %load/vec4 v0x584af5d66540_0; + %ix/load 4, 1, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %load/vec4 v0x584af5d66610_0; + %ix/load 4, 2, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; + %load/vec4 v0x584af5d666e0_0; + %ix/load 4, 3, 0; + %flag_set/imm 4, 0; + %store/vec4a v0x584af5d65fc0, 4, 0; +T_30.1 ; + %jmp T_30; + .thread T_30, $push; + .scope S_0x584af5cbe910; +T_31 ; + %delay 2, 0; + %load/vec4 v0x584af5d67db0_0; + %inv; + %store/vec4 v0x584af5d67db0_0, 0, 1; + %jmp T_31; + .thread T_31; + .scope S_0x584af5cbe910; +T_32 ; + %delay 20, 0; + %load/vec4 v0x584af5d67e70_0; + %inv; + %store/vec4 v0x584af5d67e70_0, 0, 1; + %jmp T_32; + .thread T_32; + .scope S_0x584af5cbe910; +T_33 ; + %vpi_call 3 49 "$display", "Running in test mode" {0 0 0}; + %vpi_call 3 52 "$monitor", "Time = %0t, ", $time, "o_w_7_led_seg=%h, ", v0x584af5d68250_0, "o_w_an=%h, ", v0x584af5d68340_0, "o_w_sim_clk=%h ", v0x584af5d68430_0, "state_display_state=%h ", v0x584af5d663b0_0, "l_w_cpu_state=%h", v0x584af5d67500_0 {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d67db0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d67e70_0, 0, 1; + %pushi/vec4 0, 0, 10; + %store/vec4 v0x584af5d67f30_0, 0, 10; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d68070_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d681b0_0, 0, 1; + %delay 100, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d681b0_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x584af5d67fd0_0, 0, 1; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 16, 0; + %delay 1000, 0; + %delay 1000, 0; + %vpi_call 3 115 "$finish" {0 0 0}; + %end; + .thread T_33; +# The file index is used to find the file name in the following table. +:file_names 18; + "N/A"; + ""; + "../memory/block_ram.v"; + "test_cpu_debugger.v"; + "cpu_debugger.v"; + "../core/clock_divider.v"; + "cpu.v"; + "alu.v"; + "bus.v"; + "control_unit.v"; + "cram.v"; + "../memory/block_dpram.v"; + "../memory/regfile.v"; + "../memory/register.v"; + "../core/debouncer.v"; + "../core/otp_button.v"; + "state_display.v"; + "../core/led7hex.v"; diff --git a/common/verilog/labcpu/task0.xdc b/common/verilog/labcpu/cpu_debugger.xdc similarity index 75% rename from common/verilog/labcpu/task0.xdc rename to common/verilog/labcpu/cpu_debugger.xdc index b44c0a69..82302740 100644 --- a/common/verilog/labcpu/task0.xdc +++ b/common/verilog/labcpu/cpu_debugger.xdc @@ -4,30 +4,30 @@ ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock signal -#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz -#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; - +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { i_w_clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {i_w_clk}]; +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {i_w_debug_clk_IBUF}] ##Switches -#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] -#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] -#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] -#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { i_w_in[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { i_w_in[9] }]; #IO_25_34 Sch=sw[9] +# set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +# set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +# set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[12] }]; #IO_L24P_T3_35 Sch=sw[12] +# set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { i_w_in[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { i_w_reset }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { i_w_debug_clk }]; #IO_L21P_T3_DQS_14 Sch=sw[15] ## LEDs -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { o_w_sim_clk }]; #IO_L18P_T2_A24_15 Sch=led[0] #set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] #set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] #set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] @@ -53,32 +53,32 @@ #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r ##7 segment display -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[1] }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[2] }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[3] }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[6] }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { o_w_7_led_seg[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { o_w_an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] ##CPU Reset Button #set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn ##Buttons -#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc -#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu -#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr -#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +# set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { i_w_sim_clk }]; #IO_L9P_T1_DQS_14 Sch=btnc +set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { i_w_prev }]; #IO_L4N_T0_D05_14 Sch=btnu +# set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { i_w_reset }]; #IO_L12P_T1_MRCC_14 Sch=btnl +# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { i_w_next }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd ##Pmod Headers diff --git a/common/verilog/labcpu/cram.v b/common/verilog/labcpu/cram.v index 92fef067..fb0268eb 100644 --- a/common/verilog/labcpu/cram.v +++ b/common/verilog/labcpu/cram.v @@ -2,25 +2,54 @@ module cram #( parameter p_data_width = 16, parameter p_address_width = 10 )( + // `ifdef DEBUG + output wire [(p_data_width-1) : 0] o_w_disp_out, + input wire [(p_address_width-1) : 0] i_w_disp_address, + // `endif output wire [(p_data_width-1) : 0] o_w_out, input wire [(p_data_width-1) : 0] i_w_in, input wire [(p_address_width-1) : 0] i_w_address, input wire i_w_we, input wire i_w_oe, - input wire i_w_clk + input wire i_w_clk, + input wire i_w_ram_clk ); - reg [(p_data_width-1) : 0] l_r_data [2**p_address_width-1:0]; + // initial begin + // $readmemh("cram.data", l_r_data, 0, 2**p_address_width-1); + // end - initial begin - $readmemh("cram.data", l_r_data, 0, 2**p_address_width-1); - end - always @(negedge i_w_clk) begin - if( (i_w_we == 1'b1) && (i_w_oe == 1'b0) ) begin - l_r_data[i_w_address] <= i_w_in; - end - end + wire [(p_data_width-1) : 0] l_w_out; + // `ifdef DEBUG + block_dpram #( + .p_data_width(p_data_width), + .p_address_width(p_address_width) + ) block_ram_inst ( + .o_r_out_a(l_w_out), + .o_r_out_b(o_w_disp_out), + .i_w_in(i_w_in), + .i_w_address_a(i_w_address), + .i_w_address_b(i_w_disp_address), + .i_w_we(i_w_we), + .i_w_cs_a(1'b1), + .i_w_cs_b(1'b1), + .i_w_clk_a(i_w_clk), + .i_w_clk_b(i_w_ram_clk) + ); + // `else + // block_ram #( + // .p_data_width(p_data_width), + // .p_address_width(p_address_width) + // ) block_ram_inst ( + // .o_r_out(l_w_out), + // .i_w_in(i_w_in), + // .i_w_address(i_w_address), + // .i_w_we(i_w_we), + // .i_w_cs(1'b1), + // .i_w_clk(i_w_clk) + // ); + // `endif - assign o_w_out = ( (i_w_oe == 1'b1) && (i_w_we == 1'b0) ) ? l_r_data[i_w_address] : {p_data_width{1'b0}}; + assign o_w_out = ( (i_w_oe == 1'b1) && (i_w_we == 1'b0) ) ? l_w_out : {p_data_width{1'b0}}; endmodule \ No newline at end of file diff --git a/common/verilog/labcpu/latex/.gitignore b/common/verilog/labcpu/latex/.gitignore new file mode 100644 index 00000000..eed6c919 --- /dev/null +++ b/common/verilog/labcpu/latex/.gitignore @@ -0,0 +1,2 @@ +plantuml +out \ No newline at end of file diff --git a/common/verilog/labcpu/latex/cheatsheet.tex b/common/verilog/labcpu/latex/cheatsheet.tex new file mode 100644 index 00000000..7f30340c --- /dev/null +++ b/common/verilog/labcpu/latex/cheatsheet.tex @@ -0,0 +1,155 @@ +\documentclass{article} +\usepackage{graphicx} +\usepackage{array} +\usepackage{geometry} +\geometry{a4paper, margin=1in} + +\begin{document} + +\begin{figure} + \centering + \includegraphics[width=0.8\textwidth]{nexys-a7-top_mod.png} + \caption{FPGA Board Top View} + \label{fig:fpga} +\end{figure} + +\begin{table}[h!] + \centering + \begin{tabular}{|c|c|c|c|} + \hline + \textbf{State} & \textbf{Switches} & \textbf{Left 4 7-LED Segments} & \textbf{Right 4 7-LED Segments} \\ + \hline + REGS & [3:0] REG Address& Register Name (Table \ref{tab:registers}) & Register Value\\ + \hline + RAM & [9:0] RAM Address& rAM & Ram Value\\ + \hline + BUS & NA & bUS & Bus Value\\ + \hline + FSM & NA & FSM & FSM State (Table \ref{tab:fsm_states})\\ + \hline + \end{tabular} + \caption{State Display Table} + \label{tab:state_display} +\end{table} + + +\begin{table}[h!] + \centering + \begin{tabular}{|c|c|c|} + \hline + \textbf{Register Name} & \textbf{Address Value} & \textbf{7-Segment Display Name} \\ + \hline + RA & 0x0 & rrA \\ + \hline + RB & 0x1 & rrB \\ + \hline + RC & 0x2 & rrC \\ + \hline + SP & 0x3 & rSP \\ + \hline + XA & 0x4 & rXA \\ + \hline + XB & 0x5 & rXb \\ + \hline + BA & 0x6 & rbA \\ + \hline + BB & 0x7 & rbb \\ + \hline + PC & 0x8 & rPC \\ + \hline + FR & 0x9 & rFr \\ + \hline + MA & 0xA & rMA \\ + \hline + IOA & 0xB & rIO \\ + \hline + T1 & 0xC & rT1 \\ + \hline + T2 & 0xD & rT2 \\ + \hline + IR & 0xE & rIr \\ + \hline + Nothing & 0xF & \\ + \hline + \end{tabular} + \caption{Register Address and 7-Segment Display Names} + \label{tab:registers} +\end{table} + +\begin{table}[h!] + \centering + \begin{tabular}{|l|c|c|} + \hline + \textbf{FSM State} & \textbf{Hex Value} & \textbf{FSM 7-LED Segment Name} \\ + \hline + RESET & 0x00 & rSt \\ + \hline + FETCH & 0x10 & FEt \\ + \hline + FETCH1 & 0x11 & FEt1 \\ + \hline + FETCH2 & 0x12 & FEt2 \\ + \hline + DECODE & 0x20 & dCd \\ + \hline + ADDR\_SUM & 0x30 & AdS \\ + \hline + ADDR\_SUM1 & 0x31 & AdS1 \\ + \hline + ADDR\_SUM2 & 0x32 & AdS2 \\ + \hline + ADDR\_REG & 0x34 & Adr \\ + \hline + ADDR\_IO & 0x3c & AdI \\ + \hline + LOAD\_SRC\_REG & 0x40 & LSr \\ + \hline + LOAD\_SRC\_MEM & 0x44 & LSm \\ + \hline + LOAD\_SRC\_MEM1 & 0x45 & LSm1 \\ + \hline + LOAD\_SRC\_MEM2 & 0x46 & LSm2 \\ + \hline + LOAD\_SRC\_IO & 0x4c & LSI \\ + \hline + LOAD\_SRC\_IO1 & 0x4d & LSI1 \\ + \hline + LOAD\_DST\_REG & 0x50 & Ldr \\ + \hline + LOAD\_DST\_MEM & 0x54 & Ldm \\ + \hline + LOAD\_DST\_MEM1 & 0x55 & Ldm1 \\ + \hline + LOAD\_DST\_MEM2 & 0x56 & Ldm2 \\ + \hline + NO\_LOAD\_DST\_REG & 0x60 & ndr \\ + \hline + NO\_LOAD\_DST\_IO & 0x6c & ndi \\ + \hline + EXEC\_ONE\_OP & 0x70 & E10 \\ + \hline + EXEC\_TWO\_OP & 0x74 & E20 \\ + \hline + EXEC\_TRANSFER & 0x78 & ET \\ + \hline + STORE\_REG & 0x80 & Str \\ + \hline + STORE\_MEM & 0x84 & Stm \\ + \hline + STORE\_MEM1 & 0x85 & Stm1 \\ + \hline + STORE\_IO & 0x8c & StI \\ + \hline + INC\_PC & 0x90 & IPC \\ + \hline + INC\_PC1 & 0x91 & IPC1 \\ + \hline + \end{tabular} + \caption{FSM States and Corresponding Hex Values and 7-LED Segment Names} + \label{tab:fsm_states} +\end{table} + + + + +\end{document} \ No newline at end of file diff --git a/common/verilog/labcpu/latex/nexys-a7-top.png b/common/verilog/labcpu/latex/nexys-a7-top.png new file mode 100644 index 00000000..575ccb99 Binary files /dev/null and b/common/verilog/labcpu/latex/nexys-a7-top.png differ diff --git a/common/verilog/labcpu/latex/nexys-a7-top_mod.png b/common/verilog/labcpu/latex/nexys-a7-top_mod.png new file mode 100644 index 00000000..4598ec87 Binary files /dev/null and b/common/verilog/labcpu/latex/nexys-a7-top_mod.png differ diff --git a/common/verilog/labcpu/register.v b/common/verilog/labcpu/register.v deleted file mode 100644 index 6cf3c5df..00000000 --- a/common/verilog/labcpu/register.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -module register#( - parameter p_data_width = 16 -)( - output wire [(p_data_width - 1):0] o_w_out, - output wire [(p_data_width - 1):0] o_w_disp_out, - input wire i_w_clk, - input wire i_w_reset, - input wire [(p_data_width - 1):0] i_w_in, - input wire i_w_we, - input wire i_w_oe -); - - reg [(p_data_width - 1):0] l_r_data; - - always @(negedge i_w_clk) begin - if(i_w_reset == 1'b1) begin - l_r_data <= 0; - end else begin - if( (i_w_we == 1'b1) && (i_w_oe == 1'b0) ) begin - l_r_data <= i_w_in; - end - end - end - - assign o_w_out = ( (i_w_oe == 1'b1) && (i_w_we == 1'b0) ) ? l_r_data : {p_data_width{1'b0}}; - assign o_w_disp_out = l_r_data; -endmodule diff --git a/common/verilog/labcpu/registers.v b/common/verilog/labcpu/registers.v deleted file mode 100644 index c1a03dd4..00000000 --- a/common/verilog/labcpu/registers.v +++ /dev/null @@ -1,24 +0,0 @@ -`timescale 1ns / 1ps -module registers#( - parameter p_data_width = 16, - parameter p_address_width = 3 -)( - output wire [(p_data_width-1) : 0] o_w_out, - input wire [(p_data_width-1) : 0] i_w_in, - input wire [(p_address_width-1) : 0] i_w_address, - input wire i_w_we, - input wire i_w_oe, - input wire i_w_clk -); - - reg [(p_data_width-1) : 0] l_r_data [2**p_address_width-1:0]; - - always @(posedge i_w_clk) begin - if( (i_w_we == 1'b1) && (i_w_oe == 1'b0) ) begin - l_r_data[i_w_address] <= i_w_in; - end - end - - assign o_w_out = ( (i_w_oe == 1'b1) && (i_w_we == 1'b0) ) ? l_r_data[i_w_address] : {p_data_width{1'b0}}; - -endmodule diff --git a/common/verilog/labcpu/state_display.v b/common/verilog/labcpu/state_display.v new file mode 100644 index 00000000..c50db5fa --- /dev/null +++ b/common/verilog/labcpu/state_display.v @@ -0,0 +1,505 @@ +module state_display #( + parameter p_data_width = 16, + parameter p_address_width = 10, + parameter p_regs_address_width = 3 +) ( + output wire [7:0] o_w_7_led_seg, + output wire [7:0] o_w_an, + input wire [p_regs_address_width:0] i_w_regs_addr, + input wire [(p_data_width-1):0] i_w_regs, + input wire [(p_data_width-1):0] i_w_ram, + input wire [(p_data_width-1):0] i_w_state, + input wire [(p_data_width-1):0] i_w_bus, + input wire i_w_next, + input wire i_w_prev, + input wire i_w_clk, + input wire i_w_reset +); + + localparam reset = 16'h00; + localparam fetch = 16'h10; + localparam decode = 16'h20; + localparam addr_sum = 16'h30; + localparam addr_reg = 16'h34; + localparam addr_io = 16'h3c; + localparam load_src_reg = 16'h40; + localparam load_src_mem = 16'h44; + localparam load_src_io = 16'h4c; + localparam load_dst_reg = 16'h50; + localparam load_dst_mem = 16'h54; + localparam noload_dst_reg = 16'h60; + localparam noload_dst_io = 16'h6c; + localparam exec_1op = 16'h70; + localparam exec_2op = 16'h74; + localparam exec_transf = 16'h78; + localparam store_reg = 16'h80; + localparam store_mem = 16'h84; + localparam store_io = 16'h8c; + localparam inc_cp = 16'h90; + + + + localparam l_p_RA_address = 4'h0; + localparam l_p_RB_address = 4'h1; + localparam l_p_RC_address = 4'h2; + localparam l_p_SP_address = 4'h3; + localparam l_p_XA_address = 4'h4; + localparam l_p_XB_address = 4'h5; + localparam l_p_BA_address = 4'h6; + localparam l_p_BB_address = 4'h7; + localparam l_p_PC_address = 4'h8; + localparam l_p_FR_address = 4'h9; + localparam l_p_MA_address = 4'ha; + localparam l_p_IOA_address = 4'hb; + localparam l_p_T1_address = 4'hc; + localparam l_p_T2_address = 4'hd; + localparam l_p_IR_address = 4'he; + + + + // Registers state + localparam l_p_state_REGS = 2'd0; + // RAM state + localparam l_p_state_RAM = 2'd1; + // BUS state + localparam l_p_state_BUS = 2'd2; + // Control Unit FSM state + localparam l_p_state_FSM = 2'd3; + + reg [1:0] l_r_state; // current state + reg [1:0] l_r_next_state; // next state + reg [2:0] l_r_digit; // current digit to display + + // FSM - sequential logic + always @(posedge i_w_clk or negedge i_w_reset) begin + if (!i_w_reset) begin + l_r_state <= l_p_state_REGS; + l_r_digit <= 0; + end else begin + l_r_digit <= l_r_digit + 1; + l_r_state <= l_r_next_state; + end + end + + // FSM - combinational logic compute next state + always @(*) begin + if (i_w_next) begin + l_r_next_state = l_r_state + 1; + end else if (i_w_prev) begin + l_r_next_state = l_r_state - 1; + end else begin + l_r_next_state = l_r_state; + end + end + + reg [7:0] l_r_digit_7seg [7:0]; + reg [3:0] l_r_in [3:0]; + reg [3:0] index; + // FSM - output logic + + // first compute only the most significant digits from the state + always @(*) begin + l_r_digit_7seg[4] = 8'b1111_1111; + l_r_digit_7seg[5] = 8'b1111_1111; + l_r_digit_7seg[6] = 8'b1111_1111; + l_r_digit_7seg[7] = 8'b1111_1111; + l_r_in[0] = 4'b0000; + l_r_in[1] = 4'b0000; + l_r_in[2] = 4'b0000; + l_r_in[3] = 4'b0000; + + case(l_r_state) + l_p_state_REGS: begin + l_r_in[0] = i_w_regs[3:0]; + l_r_in[1] = i_w_regs[7:4]; + l_r_in[2] = i_w_regs[11:8]; + l_r_in[3] = i_w_regs[15:12]; + + l_r_digit_7seg[7] = 8'b1010_1111; // r + + // which register to display + case (i_w_regs_addr) + l_p_RA_address: begin + l_r_digit_7seg[5] = 8'b1000_1000; // A + l_r_digit_7seg[6] = 8'b1010_1111; // r + end + + l_p_RB_address: begin + l_r_digit_7seg[5] = 8'b1000_0011; // b + l_r_digit_7seg[6] = 8'b1010_1111; // r + end + + l_p_RC_address: begin + l_r_digit_7seg[5] = 8'b1100_0110; // C + l_r_digit_7seg[6] = 8'b1010_1111; // r + end + + l_p_SP_address: begin + l_r_digit_7seg[5] = 8'b1000_1100; // P + l_r_digit_7seg[6] = 8'b1001_0010; // S + end + + l_p_XA_address: begin + l_r_digit_7seg[4] = 8'b1000_1000; // A + l_r_digit_7seg[5] = 8'b1100_0110; // right half X + l_r_digit_7seg[6] = 8'b1111_0000; // left half X + end + + l_p_XB_address: begin + l_r_digit_7seg[4] = 8'b1000_0011; // b + l_r_digit_7seg[5] = 8'b1100_0110; // right half X + l_r_digit_7seg[6] = 8'b1111_0000; // left half X + end + + l_p_BA_address: begin + l_r_digit_7seg[5] = 8'b1000_1000; // A + l_r_digit_7seg[6] = 8'b1000_0011; // b + end + + l_p_BB_address: begin + l_r_digit_7seg[5] = 8'b1000_0011; // b + l_r_digit_7seg[6] = 8'b1000_0011; // b + end + + l_p_PC_address: begin + l_r_digit_7seg[5] = 8'b1100_0110; // C + l_r_digit_7seg[6] = 8'b1000_1100; // P + end + + l_p_FR_address: begin + l_r_digit_7seg[5] = 8'b1010_1111; // r + l_r_digit_7seg[6] = 8'b1000_1110; // F + end + + l_p_MA_address: begin + l_r_digit_7seg[4] = 8'b1000_1000; // A + l_r_digit_7seg[5] = 8'b1101_1000; // right half M + l_r_digit_7seg[6] = 8'b1100_1100; // left half M + end + + l_p_IOA_address: begin + l_r_digit_7seg[5] = 8'b1100_0000; // O + l_r_digit_7seg[6] = 8'b1111_1001; // I + end + + l_p_T1_address: begin + l_r_digit_7seg[4] = 8'b1111_1001; // 1 + l_r_digit_7seg[5] = 8'b1100_1110; // right half T + l_r_digit_7seg[6] = 8'b1111_1000; // left half T + end + + l_p_T2_address: begin + l_r_digit_7seg[4] = 8'b1010_0100; // 2 + l_r_digit_7seg[5] = 8'b1100_1110; // right half T + l_r_digit_7seg[6] = 8'b1111_1000; // left half T + end + + l_p_IR_address: begin + l_r_digit_7seg[5] = 8'b1010_1111; // r + l_r_digit_7seg[6] = 8'b1111_1001; // I + end + endcase + end + + l_p_state_RAM: begin + l_r_in[0] = i_w_ram[3:0]; + l_r_in[1] = i_w_ram[7:4]; + l_r_in[2] = i_w_ram[11:8]; + l_r_in[3] = i_w_ram[15:12]; + + l_r_digit_7seg[4] = 8'b1101_1000; // right half M + l_r_digit_7seg[5] = 8'b1100_1100; // left half M + l_r_digit_7seg[6] = 8'b1000_1000; // A + l_r_digit_7seg[7] = 8'b1010_1111; // r + end + + l_p_state_BUS: begin + l_r_in[0] = i_w_bus[3:0]; + l_r_in[1] = i_w_bus[7:4]; + l_r_in[2] = i_w_bus[11:8]; + l_r_in[3] = i_w_bus[15:12]; + + l_r_digit_7seg[5] = 8'b1001_0010; // S + l_r_digit_7seg[6] = 8'b1100_0001; // U + l_r_digit_7seg[7] = 8'b1000_0011; // b + end + + l_p_state_FSM: begin + l_r_digit_7seg[4] = 8'b1101_1000; // right half M + l_r_digit_7seg[5] = 8'b1100_1100; // left half M + l_r_digit_7seg[6] = 8'b1001_0010; // S + l_r_digit_7seg[7] = 8'b1000_1110; // F + end + + endcase + end + + wire [7:0] l_w_7_led_seg_0; + wire [7:0] l_w_7_led_seg_1; + wire [7:0] l_w_7_led_seg_2; + wire [7:0] l_w_7_led_seg_3; + + // instantiate 4 led7hex modules + led7hex led7hex_inst_0 ( + .l_r_led7(l_w_7_led_seg_0), + .i_w_value(l_r_in[0]) + ); + + led7hex led7hex_inst_1 ( + .l_r_led7(l_w_7_led_seg_1), + .i_w_value(l_r_in[1]) + ); + + led7hex led7hex_inst_2 ( + .l_r_led7(l_w_7_led_seg_2), + .i_w_value(l_r_in[2]) + ); + + led7hex led7hex_inst_3 ( + .l_r_led7(l_w_7_led_seg_3), + .i_w_value(l_r_in[3]) + ); + + + // FSM - output logic compute the least significant digits from the state + always @(*) begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1111_1111; + l_r_digit_7seg[2] = 8'b1111_1111; + l_r_digit_7seg[3] = 8'b1111_1111; + + if (l_r_state == l_p_state_FSM) begin + case(i_w_state) + reset: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1000_0111; // t + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1010_1111; // r + end + + fetch: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1000_0111; // t + l_r_digit_7seg[2] = 8'b1000_0110; // E + l_r_digit_7seg[3] = 8'b1000_1110; // F + end + + fetch + 'd1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1000_0111; // t + l_r_digit_7seg[2] = 8'b1000_0110; // E + l_r_digit_7seg[3] = 8'b1000_1110; // F + end + + fetch + 'd2: begin + l_r_digit_7seg[0] = 8'b1010_0100; // 2 + l_r_digit_7seg[1] = 8'b1000_0111; // t + l_r_digit_7seg[2] = 8'b1000_0110; // E + l_r_digit_7seg[3] = 8'b1000_1110; // F + end + + decode: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1010_0001; // d + l_r_digit_7seg[2] = 8'b1100_0110; // C + l_r_digit_7seg[3] = 8'b1010_0001; // d + end + + addr_sum: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1001_0010; // S + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1000_1000; // A + end + + addr_sum + 'd1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1001_0010; // S + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1000_1000; // A + end + + addr_sum + 'd2: begin + l_r_digit_7seg[0] = 8'b1010_0100; // 2 + l_r_digit_7seg[1] = 8'b1001_0010; // S + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1000_1000; // A + end + + addr_reg: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1010_1111; // r + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1000_1000; // A + end + + addr_io: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1111_1001; // I + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1000_1000; // A + end + + load_src_reg: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1010_1111; // r + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_src_mem: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_src_mem + 'd1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_src_mem + 'd2: begin + l_r_digit_7seg[0] = 8'b1010_0100; // 2 + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_src_io: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1111_1001; // I + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_src_io + 'd1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1111_1001; // I + l_r_digit_7seg[2] = 8'b1001_0010; // S + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_dst_reg: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1010_1111; // r + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_dst_mem: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_dst_mem +'d1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + load_dst_mem + 'd2: begin + l_r_digit_7seg[0] = 8'b1010_0100; // 2 + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1100_0111; // L + end + + noload_dst_reg: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1010_1111; // r + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1010_1011; // n + end + + noload_dst_io: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1111_1001; // i + l_r_digit_7seg[2] = 8'b1010_0001; // d + l_r_digit_7seg[3] = 8'b1010_1011; // n + end + + exec_1op: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1100_0000; // O + l_r_digit_7seg[2] = 8'b1111_1001; // 1 + l_r_digit_7seg[3] = 8'b1000_0110; // E + end + + exec_2op: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1100_0000; // O + l_r_digit_7seg[2] = 8'b1010_0100; // 2 + l_r_digit_7seg[3] = 8'b1000_0110; // E + end + + exec_transf: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1100_1110; // right half T + l_r_digit_7seg[2] = 8'b1111_1000; // left half T + l_r_digit_7seg[3] = 8'b1000_0110; // E + end + + store_reg: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1010_1111; // r + l_r_digit_7seg[2] = 8'b1000_0111; // t + l_r_digit_7seg[3] = 8'b1001_0010; // S + end + + store_mem: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1000_0111; // t + l_r_digit_7seg[3] = 8'b1001_0010; // S + end + + store_mem + 'd1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1101_0100; // m + l_r_digit_7seg[2] = 8'b1000_0111; // t + l_r_digit_7seg[3] = 8'b1001_0010; // S + end + + store_io: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1111_1001; // I + l_r_digit_7seg[2] = 8'b1000_0111; // t + l_r_digit_7seg[3] = 8'b1001_0010; // S + end + + inc_cp: begin + l_r_digit_7seg[0] = 8'b1111_1111; + l_r_digit_7seg[1] = 8'b1100_0110; // C + l_r_digit_7seg[2] = 8'b1000_1100; // P + l_r_digit_7seg[3] = 8'b1111_1001; // I + end + + inc_cp + 'd1: begin + l_r_digit_7seg[0] = 8'b1111_1001; // 1 + l_r_digit_7seg[1] = 8'b1100_0110; // C + l_r_digit_7seg[2] = 8'b1000_1100; // P + l_r_digit_7seg[3] = 8'b1111_1001; // I + end + + endcase + end else begin + l_r_digit_7seg[0] = l_w_7_led_seg_0; + l_r_digit_7seg[1] = l_w_7_led_seg_1; + l_r_digit_7seg[2] = l_w_7_led_seg_2; + l_r_digit_7seg[3] = l_w_7_led_seg_3; + end + + end + + // turn off the other 7 led digits + assign o_w_an = ~(1 << l_r_digit); + + assign o_w_7_led_seg = l_r_digit_7seg[l_r_digit]; + +endmodule \ No newline at end of file diff --git a/common/verilog/labcpu/task0.v b/common/verilog/labcpu/task0.v deleted file mode 100644 index 668ca437..00000000 --- a/common/verilog/labcpu/task0.v +++ /dev/null @@ -1,18 +0,0 @@ -module task0#( - parameter p_data_width = 16, - parameter p_address_width = 10, - parameter p_port_width = 8 -)( - input wire i_w_clk, - input wire i_w_reset -); - cpu #( - .p_data_width(p_data_width), - .p_address_width(p_address_width), - .p_port_width(p_port_width) - ) l_m_cpu ( - .i_w_clk(i_w_clk), - .i_w_reset(i_w_reset), - .i_w_io_out({p_data_width{1'b0}}) - ); -endmodule \ No newline at end of file diff --git a/common/verilog/labcpu/tcl_files/build.tcl b/common/verilog/labcpu/tcl_files/build.tcl deleted file mode 100644 index 62c487be..00000000 --- a/common/verilog/labcpu/tcl_files/build.tcl +++ /dev/null @@ -1,8 +0,0 @@ -create_project build build_project -part xc7a100tcsg324-1 -force -import_files -force -fileset sources_1 -norecurse alu.v bus.v cpu.v cram.v register.v registers.v uc.v cram.data task0.v -import_files -force -fileset sim_1 -norecurse test_task0.v -import_files -force -fileset constrs_1 -norecurse task0.xdc -set_property top task0 [get_fileset sources_1] -set_property top test_task0 [get_fileset sim_1] -update_compile_order -fileset sources_1 -update_compile_order -fileset sim_1 diff --git a/common/verilog/labcpu/tcl_files/run.tcl b/common/verilog/labcpu/tcl_files/run.tcl deleted file mode 100644 index c61630e0..00000000 --- a/common/verilog/labcpu/tcl_files/run.tcl +++ /dev/null @@ -1,2 +0,0 @@ -open_project build_project/build.xpr -launch_simulation \ No newline at end of file diff --git a/common/verilog/labcpu/tcl_files/simulation.tcl b/common/verilog/labcpu/tcl_files/simulation.tcl deleted file mode 100644 index 886c5676..00000000 --- a/common/verilog/labcpu/tcl_files/simulation.tcl +++ /dev/null @@ -1,3 +0,0 @@ -open_project build_project/build.xpr -start_gui -launch_simulation \ No newline at end of file diff --git a/common/verilog/labcpu/tcl_files/vivado.tcl b/common/verilog/labcpu/tcl_files/vivado.tcl new file mode 100644 index 00000000..e2d3404b --- /dev/null +++ b/common/verilog/labcpu/tcl_files/vivado.tcl @@ -0,0 +1,9 @@ +create_project build build_project -part xc7a100tcsg324-1 -force +import_files -force -fileset sources_1 -norecurse cpu_debugger.v alu.v bus.v control_unit.v cpu.v cram.data cram.v state_display.v ../core/clock_divider.v ../core/debouncer.v ../core/led7hex.v ../core/otp_button.v ../memory/block_ram.v ../memory/block_dpram.v ../memory/register.v ../memory/regfile.v +import_files -force -fileset sim_1 -norecurse test_cpu_debugger.v +import_files -force -fileset constrs_1 -norecurse cpu_debugger.xdc +set_property top cpu_debugger [get_fileset sources_1] +set_property top test_cpu_debugger [get_fileset sim_1] +update_compile_order -fileset sources_1 +update_compile_order -fileset sim_1 +start_gui \ No newline at end of file diff --git a/common/verilog/labcpu/test_cpu_debugger.v b/common/verilog/labcpu/test_cpu_debugger.v new file mode 100644 index 00000000..9528a514 --- /dev/null +++ b/common/verilog/labcpu/test_cpu_debugger.v @@ -0,0 +1,118 @@ +module test_cpu_debugger; + + // Parameters + parameter p_data_width = 16; + parameter p_address_width = 10; + parameter p_regs_address_width = 3; + + // Inputs + reg [(p_address_width-1):0] i_w_in; + reg i_w_next; + reg i_w_prev; + reg i_w_clk; + reg i_w_debug_clk; + reg i_w_reset; + + // Outputs + wire [7:0] o_w_7_led_seg; + wire [7:0] o_w_an; + wire o_w_sim_clk; + + // Instantiate the Unit Under Test (UUT) + `define SIMULATION 1 + cpu_debugger #( + .p_data_width(p_data_width), + .p_address_width(p_address_width), + .p_regs_address_width(p_regs_address_width), + .p_divisor(4), + .p_no_cycles(1) + ) uut ( + .o_w_7_led_seg(o_w_7_led_seg), + .o_w_an(o_w_an), + .o_w_sim_clk(o_w_sim_clk), + .i_w_in(i_w_in), + .i_w_next(i_w_next), + .i_w_prev(i_w_prev), + .i_w_clk(i_w_clk), + .i_w_debug_clk(i_w_debug_clk), + .i_w_reset(i_w_reset) + ); + + // Clock generation + always #2 i_w_clk = ~i_w_clk; // 100 MHz clock + + always #20 i_w_debug_clk = ~i_w_debug_clk; // 50 MHz clock + // Test sequence + initial begin + + `ifdef SIMULATION + $display("Running in test mode"); + `endif + // monitor the outputs + $monitor( + "Time = %0t, ", $time, + "o_w_7_led_seg=%h, ", o_w_7_led_seg, + "o_w_an=%h, ", o_w_an, + "o_w_sim_clk=%h ", o_w_sim_clk, + "state_display_state=%h ", uut.l_m_state_display.l_r_state, + "l_w_cpu_state=%h", uut.l_w_cpu_state + ); + + // Initialize Inputs + i_w_clk = 0; + i_w_debug_clk = 0; + + i_w_in = 0; + i_w_next = 0; + i_w_prev = 0; + i_w_reset = 0; + + // Wait for global reset to finish + #100; + i_w_reset = 1; + i_w_next = 1; + #16; + #16; + #16; + #16; + #16; + i_w_next = 0; + #16; + #16; + #16; + #16; + #16; + i_w_next = 1; + #16; + #16; + #16; + #16; + #16; + i_w_next = 0; + #16; + #16; + #16; + #16; + #16; + i_w_next = 1; + #16; + #16; + #16; + #16; + #16; + i_w_next = 0; + #16; + #16; + #16; + #16; + #16; + + + + // Add more test cases as needed + #1000; + #1000; + $finish; + end + +endmodule \ No newline at end of file diff --git a/common/verilog/labcpu/test_task0.v b/common/verilog/labcpu/test_task0.v deleted file mode 100644 index bab684bd..00000000 --- a/common/verilog/labcpu/test_task0.v +++ /dev/null @@ -1,49 +0,0 @@ -`timescale 1ns / 1ps -module test_task0; - localparam l_p_data_width = 16; - localparam l_p_address_width = 10; - localparam l_p_port_width = 8; - - //Inputs - reg l_r_clk; - reg l_r_reset; - - //Outputs - - //local variables for loop - integer i,j,k; - - //Module initialization - task0 #( - .p_data_width(l_p_data_width), - .p_address_width(l_p_address_width), - .p_port_width(l_p_port_width) - ) l_m_task0( - .i_w_clk(l_r_clk), - .i_w_reset(l_r_reset) - ); - - always #5 l_r_clk = ~l_r_clk; - - //Simulation tests - initial begin - //wave files - $dumpfile("test.vcd"); - // dumpp all variables - $dumpvars; - // monitor varibles changes in values - $monitor( - "Time = %0t, ", $time, - "l_r_clk=%0d, ", l_r_clk, - "l_r_reset=%0d, ", l_r_reset - ); - - l_r_clk = 0; - l_r_reset = 1; - #10; - l_r_reset = 0; - #1000; - //finish the simulation - $finish; - end -endmodule diff --git a/common/verilog/labcpu/uc.v b/common/verilog/labcpu/uc.v deleted file mode 100644 index 658fee7c..00000000 --- a/common/verilog/labcpu/uc.v +++ /dev/null @@ -1,500 +0,0 @@ -`timescale 1ns / 1ps -module uc#( - parameter p_data_width = 16 -) ( - output reg o_r_alu_oe, - output reg o_r_alu_carry, - output reg [3 : 0] o_r_alu_opcode, - output reg o_r_ram_oe, - output reg o_r_ram_we, - output reg o_r_io_oe, - output reg o_r_io_we, - output reg [2 : 0] o_r_regs_addr, - output reg o_r_regs_oe, - output reg o_r_regs_we, - output reg o_r_cp_oe, - output reg o_r_cp_we, - output reg o_r_ind_sel, // controls IND register input (0 = bus, 1 = alu flags) - output reg o_r_ind_oe, - output reg o_r_ind_we, - output reg o_r_am_oe, - output reg o_r_am_we, - output reg o_r_aie_oe, - output reg o_r_aie_we, - output reg o_r_t1_oe, - output reg o_r_t1_we, - output reg o_r_t2_oe, - output reg o_r_t2_we, - output reg o_r_ri_oe, // controls RI register output which generates the offset for Jcond instructions - output reg o_r_ri_we, - input wire i_w_clk, - input wire i_w_reset, - input wire [(p_data_width - 1) : 0] i_w_ri, - input wire [(p_data_width - 1) : 0] i_w_ind -); - -localparam l_p_state_width = 16; - -localparam ADC = 4'd0; -localparam SBB1 = 4'd1; -localparam SBB2 = 4'd2; -localparam NOT = 4'd3; -localparam AND = 4'd4; -localparam OR = 4'd5; -localparam XOR = 4'd6; -localparam SHL = 4'd7; -localparam SHR = 4'd8; -localparam SAR = 4'd9; - -localparam RA = 3'd0; -localparam RB = 3'd1; -localparam RC = 3'd2; -localparam IS = 3'd3; -localparam XA = 3'd4; -localparam XB = 3'd5; -localparam BA = 3'd6; -localparam BB = 3'd7; - - -wire [0:6] l_w_cop; -wire l_w_d; -wire [0:1] l_w_mod; -wire [0:2] l_w_rg; -wire [0:2] l_w_rm; - -assign l_w_cop = {i_w_ri[0], i_w_ri[1], i_w_ri[2], i_w_ri[3], i_w_ri[4], i_w_ri[5], i_w_ri[6]}; -assign l_w_d = {i_w_ri[7]}; -assign l_w_mod = {i_w_ri[8], i_w_ri[9]}; -assign l_w_rg = {i_w_ri[10], i_w_ri[11], i_w_ri[12]}; -assign l_w_rm = {i_w_ri[13], i_w_ri[14], i_w_ri[15]}; - -localparam reset = 16'h00; // reset state -localparam fetch = 16'h10; // load instruction to instruction register -localparam decode = 16'h20; // analyze loaded instruction -localparam addr_sum = 16'h30; // computes address of the form [By+Xz] with y,z in {A, B} -localparam addr_reg = 16'h34; // computes address of the form [yz] with y in {X, B} and z in {A, B} -localparam addr_io = 16'h3c; // computes address of IO port -localparam load_src_reg = 16'h40; // load source operand from register -localparam load_src_mem = 16'h44; // load source operand from memory -localparam load_src_io = 16'h4c; // load source operand from IO port -localparam load_dst_reg = 16'h50; // load destination operand from register -localparam load_dst_mem = 16'h54; // load destination operand from memory -localparam noload_dst_reg = 16'h60; // like load_dst_reg but without the loading; equals a nop -localparam noload_dst_io = 16'h6c; // like load_dst_io but without the loading; equals loading of aie -localparam exec_1op = 16'h70; // execute 1 operand instructions -localparam exec_2op = 16'h74; // execute 2 operand instructions -localparam exec_transf = 16'h78; // execute transfer instructions -localparam store_reg = 16'h80; // store result to register -localparam store_mem = 16'h84; // store result to memory -localparam store_io = 16'h8c; // store result to IO port -localparam inc_cp = 16'h90; // increment program counter - -reg [(l_p_state_width - 1) : 0] l_r_state = reset, l_r_state_next; -reg [(l_p_state_width - 1) : 0] l_r_decoded_src, l_r_decoded_src_next; // stores decoded source operand load state -reg [(l_p_state_width - 1) : 0] l_r_decoded_dst, l_r_decoded_dst_next; // stores decoded destination operand load state -reg [(l_p_state_width - 1) : 0] l_r_decoded_exec, l_r_decoded_exec_next; // stores decoded execute state -reg [(l_p_state_width - 1) : 0] l_r_decoded_store, l_r_decoded_store_next; // stores decoded store state -reg l_r_decoded_d, l_r_decoded_d_next; // stores decoded direction bit -reg [0:2] l_r_decoded_rg, l_r_decoded_rg_next; // stores decoded REG operand - -// FSM - sequential part -always @(posedge i_w_clk) begin - l_r_state <= reset; - - if(!i_w_reset) begin - l_r_state <= l_r_state_next; - - if(l_r_state == decode) begin - l_r_decoded_src <= l_r_decoded_src_next; - l_r_decoded_dst <= l_r_decoded_dst_next; - l_r_decoded_exec <= l_r_decoded_exec_next; - l_r_decoded_store <= l_r_decoded_store_next; - l_r_decoded_d <= l_r_decoded_d_next; - l_r_decoded_rg <= l_r_decoded_rg_next; - end - end -end - -// FSM - combinational part -always @(*) begin - l_r_state_next = reset; - l_r_decoded_src_next = reset; - l_r_decoded_dst_next = reset; - l_r_decoded_exec_next = reset; - l_r_decoded_store_next = reset; - l_r_decoded_d_next = 0; - l_r_decoded_rg_next = 0; - o_r_alu_oe = 0; - o_r_alu_carry = 0; - o_r_alu_opcode = 0; - o_r_ram_oe = 0; - o_r_ram_we = 0; - o_r_io_oe = 0; - o_r_io_we = 0; - o_r_regs_addr = 0; - o_r_regs_oe = 0; - o_r_regs_we = 0; - o_r_cp_oe = 0; - o_r_cp_we = 0; - o_r_ind_sel = 0; - o_r_ind_oe = 0; - o_r_ind_we = 0; - o_r_am_oe = 0; - o_r_am_we = 0; - o_r_aie_oe = 0; - o_r_aie_we = 0; - o_r_t1_oe = 0; - o_r_t1_we = 0; - o_r_t2_oe = 0; - o_r_t2_we = 0; - o_r_ri_oe = 0; - o_r_ri_we = 0; - - case(l_r_state) - reset: begin - l_r_state_next = fetch; - end - - fetch: begin - o_r_cp_oe = 1; - o_r_am_we = 1; - - l_r_state_next = fetch + 1; - end - - fetch + 'd1: begin - o_r_am_oe = 1; - - l_r_state_next = fetch + 2; - end - - fetch + 'd2: begin - o_r_ram_oe = 1; - o_r_ri_we = 1; - - l_r_state_next = decode; - end - - decode: begin - // decode location of operands and operation - if(l_w_cop[0:3] == 4'b0001) begin // one operand instructions - l_r_decoded_d_next = 0; - l_r_decoded_rg_next = l_w_rg; - l_r_decoded_dst_next = l_w_mod == 2'b11 ? load_dst_reg : load_dst_mem; - l_r_decoded_src_next = l_r_decoded_dst_next; - l_r_decoded_exec_next = exec_1op; - l_r_decoded_store_next = l_w_mod == 2'b11 ? store_reg : store_mem; - end - else if(l_w_cop[0:2] == 3'b010) begin // two operand instructions - l_r_decoded_d_next = l_w_d; - l_r_decoded_rg_next = l_w_rg; - l_r_decoded_dst_next = (l_w_mod == 2'b11) || (l_w_d == 1) ? load_dst_reg : load_dst_mem; - l_r_decoded_src_next = (l_w_mod == 2'b11) || (l_w_d == 0) ? load_src_reg : load_src_mem; - l_r_decoded_exec_next = exec_2op; - l_r_decoded_store_next = !l_w_cop[3] ? inc_cp : ((l_w_mod == 2'b11) || (l_w_d == 1) ? store_reg : store_mem); - end - else if(l_w_cop[0:5] == 6'b100000) begin // IO instructions - l_r_decoded_d_next = !l_w_cop[6] ? 1 : 0; - l_r_decoded_rg_next = RA; - l_r_decoded_dst_next = !l_w_cop[6] ? noload_dst_reg : noload_dst_io; - l_r_decoded_src_next = !l_w_cop[6] ? load_src_io : load_src_reg; - l_r_decoded_exec_next = exec_transf; - l_r_decoded_store_next = !l_w_cop[6] ? store_reg : store_io; - end - - // decode address calculation mode - if(l_w_cop[0] == 0) begin - case(l_w_mod) - 2'b00: begin - l_r_state_next = l_w_rm[0] ? addr_reg : addr_sum; - end - - 2'b11: begin - l_r_state_next = l_r_decoded_src_next; - end - endcase - end - else begin - if(l_w_cop[0:5] == 6'b100000) begin // IO instructions - l_r_state_next = addr_io; - end - end - end - - addr_sum: begin - o_r_regs_addr = l_w_rm[1] ? BB : BA; - o_r_regs_oe = 1; - o_r_t1_we = 1; - - l_r_state_next = addr_sum + 1; - end - - addr_sum + 'd1: begin - o_r_regs_addr = l_w_rm[2] ? XB : XA; - o_r_regs_oe = 1; - o_r_t2_we = 1; - - l_r_state_next = addr_sum + 2; - end - - addr_sum + 'd2: begin - o_r_t1_oe = 1; - o_r_t2_oe = 1; - o_r_alu_carry = 0; - o_r_alu_opcode = ADC; - o_r_alu_oe = 1; - if(l_r_decoded_d) - o_r_t2_we = 1; - else - o_r_t1_we = 1; - - l_r_state_next = l_r_decoded_src; - end - - addr_reg: begin - o_r_regs_addr = l_w_rm; - o_r_regs_oe = 1; - if(l_r_decoded_d) - o_r_t2_we = 1; - else - o_r_t1_we = 1; - - l_r_state_next = l_r_decoded_src; - end - - addr_io: begin - o_r_ri_oe = 1; - if(l_r_decoded_d) - o_r_t2_we = 1; - else - o_r_t1_we = 1; - - l_r_state_next = l_r_decoded_src; - end - - load_src_reg: begin - o_r_regs_addr = l_r_decoded_d ? l_w_rm : l_r_decoded_rg; - o_r_regs_oe = 1; - o_r_t2_we = 1; - - l_r_state_next = l_r_decoded_dst; - end - - load_src_mem: begin - o_r_t1_oe = 0; - o_r_t2_oe = 1; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_am_we = 1; - - l_r_state_next = load_src_mem + 1; - end - - load_src_mem + 'd1: begin - o_r_am_oe = 1; - - l_r_state_next = load_src_mem + 2; - end - - load_src_mem + 'd2: begin - o_r_ram_oe = 1; - o_r_t2_we = 1; - - l_r_state_next = l_r_decoded_dst; - end - - load_src_io: begin - o_r_t1_oe = 0; - o_r_t2_oe = 1; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_aie_we = 1; - - l_r_state_next = load_src_io + 1; - end - - load_src_io + 'd1: begin - o_r_aie_oe = 1; - o_r_io_oe = 1; - o_r_t2_we = 1; - - l_r_state_next = l_r_decoded_dst; - end - - load_dst_reg: begin - o_r_regs_addr = l_r_decoded_d ? l_r_decoded_rg : l_w_rm; - o_r_regs_oe = 1; - o_r_t1_we = 1; - - l_r_state_next = l_r_decoded_exec; - end - - load_dst_mem: begin - o_r_t1_oe = 1; - o_r_t2_oe = 0; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_am_we = 1; - - l_r_state_next = load_dst_mem + 1; - end - - load_dst_mem + 'd1: begin - o_r_am_oe = 1; - - l_r_state_next = load_dst_mem + 2; - end - - load_dst_mem + 'd2: begin - o_r_ram_oe = 1; - o_r_t1_we = 1; - - l_r_state_next = l_r_decoded_exec; - end - - noload_dst_reg: begin - l_r_state_next = l_r_decoded_exec; - end - - noload_dst_io: begin - o_r_t1_oe = 1; - o_r_t2_oe = 0; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_aie_we = 1; - - l_r_state_next = l_r_decoded_exec; - end - - exec_1op: begin - o_r_t1_oe = 1; - case(l_w_cop[4:6]) - 3'b000: begin // INC - o_r_alu_carry = 1; - o_r_alu_opcode = ADC; - end - 3'b001: begin // DEC - o_r_alu_carry = 1; - o_r_alu_opcode = SBB1; - end - 3'b010: begin // NEG - o_r_alu_carry = 0; - o_r_alu_opcode = SBB2; - end - 3'b011: begin // NOT - o_r_alu_opcode = NOT; - end - 3'b100: o_r_alu_opcode = SHL; // SHL/SAL - 3'b101: o_r_alu_opcode = SHR; // SHR - 3'b110: o_r_alu_opcode = SAR; // SAR - endcase - o_r_alu_oe = 1; - o_r_t1_we = 1; - o_r_ind_sel = 1; - o_r_ind_we = 1; - - l_r_state_next = l_r_decoded_store; - end - - exec_2op: begin - o_r_t1_oe = 1; - o_r_t2_oe = 1; - case(l_w_cop[4:6]) - 3'b000: begin // ADD - o_r_alu_carry = 0; - o_r_alu_opcode = ADC; - end - 3'b001: begin // ADC - o_r_alu_carry = i_w_ind[0]; - o_r_alu_opcode = ADC; - end - 3'b010: begin // SUB/CMP - o_r_alu_carry = 0; - o_r_alu_opcode = SBB1; - end - 3'b011: begin // SBB - o_r_alu_carry = i_w_ind[0]; - o_r_alu_opcode = SBB1; - end - 3'b100: o_r_alu_opcode = AND; // AND/TEST - 3'b101: o_r_alu_opcode = OR; // OR - 3'b110: o_r_alu_opcode = XOR; // XOR - endcase - o_r_alu_oe = 1; - o_r_t1_we = 1; - o_r_ind_sel = 1; - o_r_ind_we = 1; - - l_r_state_next = l_r_decoded_store; - end - - exec_transf: begin - o_r_t1_oe = 0; - o_r_t2_oe = 1; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_t1_we = 1; - - l_r_state_next = l_r_decoded_store; - end - - store_reg: begin - o_r_t1_oe = 1; - o_r_t2_oe = 0; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_regs_addr = l_r_decoded_d ? l_r_decoded_rg : l_w_rm; - o_r_regs_we = 1; - - l_r_state_next = inc_cp; - end - - store_mem: begin - o_r_t1_oe = 1; - o_r_t2_oe = 0; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_am_oe = 1; - o_r_ram_we = 1; - - l_r_state_next = store_mem + 1; - end - - store_mem + 'd1: begin - l_r_state_next = inc_cp; - end - - store_io: begin - o_r_t1_oe = 1; - o_r_t2_oe = 0; - o_r_alu_opcode = OR; - o_r_alu_oe = 1; - o_r_aie_oe = 1; - o_r_io_we = 1; - - l_r_state_next = inc_cp; - end - - inc_cp: begin - o_r_cp_oe = 1; - o_r_t1_we = 1; - - l_r_state_next = inc_cp + 1; - end - - inc_cp + 'd1: begin - o_r_t1_oe = 1; - o_r_cp_we = 1; - o_r_alu_oe = 1; - o_r_alu_carry = 1; - o_r_alu_opcode = ADC; - - l_r_state_next = fetch; - end - - default: l_r_state_next = reset; - endcase -end - - -endmodule diff --git a/common/verilog/memory/block_dpram.v b/common/verilog/memory/block_dpram.v new file mode 100644 index 00000000..93e24544 --- /dev/null +++ b/common/verilog/memory/block_dpram.v @@ -0,0 +1,42 @@ +// Dual-Port Block RAM Read-First Mode single Clock (recommended template) +module block_dpram #( + parameter p_data_width = 8, + parameter p_address_width = 20 +) ( + output reg [(p_data_width-1) : 0] o_r_out_a, + output reg [(p_data_width-1) : 0] o_r_out_b, + input wire [(p_data_width-1) : 0] i_w_in, + input wire [(p_address_width-1) : 0] i_w_address_a, + input wire [(p_address_width-1) : 0] i_w_address_b, + input wire i_w_we, + input wire i_w_cs_a, + input wire i_w_cs_b, + input wire i_w_clk_a, + input wire i_w_clk_b +); + // define the depth of the RAM + localparam l_p_depth = 2**p_address_width; + // set the ram_style attribute to "block" to infer block RAM + (* ram_style = "block" *) reg [(p_data_width-1) : 0] l_r_data [(l_p_depth-1):0]; + + + // init the RAM with the data from the file + initial begin + $readmemh("cram.data", l_r_data, 0, 2**p_address_width-1); + end + + always @(posedge i_w_clk_a) begin + if (i_w_cs_a) begin + if( i_w_we ) begin + l_r_data[i_w_address_a] <= i_w_in; + end + o_r_out_a <= l_r_data[i_w_address_a]; + end + end + + always @(posedge i_w_clk_b) begin + if (i_w_cs_b) begin + o_r_out_b <= l_r_data[i_w_address_b]; + end + end +endmodule \ No newline at end of file diff --git a/common/verilog/memory/regfile.v b/common/verilog/memory/regfile.v new file mode 100644 index 00000000..ee352023 --- /dev/null +++ b/common/verilog/memory/regfile.v @@ -0,0 +1,45 @@ +// Registers file +`define DEBUG 1 +module regfile #( + parameter p_data_width = 5, + parameter p_address_width = 3 +) ( + `ifdef DEBUG + output wire [(p_data_width-1) : 0] o_w_disp_out, + input wire [(p_address_width-1) : 0] i_w_disp_reg, + `endif + output wire [(p_data_width-1) : 0] o_w_out, + input wire [(p_data_width-1) : 0] i_w_in, + input wire [(p_address_width-1) : 0] i_w_reg, + input wire i_w_we, + input wire i_w_oe, + input wire i_w_reset, + input wire i_w_clk +); + + // define the depth of the RAM + localparam l_p_depth = 2**p_address_width; + // set the ram_style attribute to "block" to infer block RAM + reg [(p_data_width-1) : 0] l_r_data [(l_p_depth-1):0]; + reg[p_address_width:0] index; + + always @(posedge i_w_clk or negedge i_w_reset) begin + if (!i_w_reset) begin + for (index = 0; index < l_p_depth; index = index + 1) begin + l_r_data[index] <= 0; + end + end else begin + if (i_w_we) begin + l_r_data[i_w_reg] <= i_w_in; + end + end + end + + assign o_w_out = i_w_oe ? l_r_data[i_w_reg] : {p_data_width{1'b0}}; + + `ifdef DEBUG + assign o_w_disp_out = l_r_data[i_w_disp_reg]; + `endif + + +endmodule \ No newline at end of file diff --git a/common/verilog/memory/register.v b/common/verilog/memory/register.v index be9b3594..2cef9609 100644 --- a/common/verilog/memory/register.v +++ b/common/verilog/memory/register.v @@ -1,10 +1,11 @@ +`define DEBUG 1 module register #( parameter p_data_width = 8 ) ( - output wire [(p_data_width - 1):0] o_w_out, `ifdef DEBUG output wire [(p_data_width - 1):0] o_w_disp_out, `endif + output wire [(p_data_width - 1):0] o_w_out, input wire [(p_data_width - 1):0] i_w_in, input wire i_w_clk, input wire i_w_reset, @@ -14,7 +15,7 @@ module register #( reg [(p_data_width - 1):0] l_r_data; - always @(posedge i_w_clk) begin + always @(posedge i_w_clk or negedge i_w_reset) begin if(!i_w_reset) begin l_r_data <= 0; end else begin @@ -24,7 +25,7 @@ module register #( end end - assign o_w_out = i_w_oe ? l_r_data : {p_data_width{1'bz}}; + assign o_w_out = i_w_oe ? l_r_data : {p_data_width{1'b0}}; `ifdef DEBUG assign o_w_disp_out = l_r_data;