This repository contains a Verilog implementation of the Advanced Encryption Standard (AES) algorithm, developed as part of a first-year computer engineering course on advanced logic design.
- Flexible Key Length Support: Encrypts and decrypts data using 128-bit, 192-bit, or 256-bit keys (depending on your implementation choices).
- Debugging Assistance: Provides a log transcript that can be printed during operation to aid in debugging.
- Verification: Includes testbenches for thorough verification of encryption and decryption functionality.
Top-Level Module AES.v
- This module serves as the entry point for your AES design.
- It takes inputs such as:
- Plaintext/Ciphertext data
- Key
- Control signals (e.g., encryption/decryption mode, key length selection)
- It instantiates the following sub-modules:
keysGenerator.vwhich in turn callsCipher.vwhich in turn calls Round function modules (e.g.,SubBytes.v,ShiftRows.v,MixColumns.v,AddRoundKey.v)InvCipher.vwhich in turn calls Inverse Round function modules (e.g.,InvSubBytes.v,InvShiftRows.v,InvMixColumns.v,AddRoundKey.v)
- It performs the following operations:
- Selects the appropriate key length depending on the selected mode
- Loops through the required number of rounds (based on key length) by iterating over the round function modules.
- Provides the final encrypted/decrypted output.
- Implements a log transcript mechanism (using system tasks like
$displayor dedicated logging signals) to print intermediate values for debugging.
- Start with cloning the repo
git clone https://github.com/ahmedfathy090/AES.git
- Synthesis and Simulation
- Install Quartus Prime: Download and install the Intel Quartus Prime software from the Intel website.
- Choose the appropriate version based on your operating system.
- Create a new project and add source files.
- Compile the Design
- Run Simulation
Tip
Don't forget to make use of the debugging assistant transcript provided in the code!
Ahmed Fathy |
Habiba Ayman |
Tasneem Mohamed |
Ahmed Gamal |