PyInfra: Calculate compile order of VHDL files.

[Paebbels]

Currently, the compile order of VHDL files relies on the definition order of VHDL source files in the *.files files. The Python-based infrastructure should be able to calculate this order on its own.

Tools that require pre-ordered VHDL file lists or per-file commands executed in the right order:

• Simulators

  • Aldec Active-HDL
  • GHDL
  • Mentor Graphics ModelSim
  • Mentor Graphics QuestaSim
  • ISE Simulator if used in a per-file mode
  • Vivado Simulator if used in a per-file mode

• Compiler