GRX350/500 in-kernel support #21
Comments
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Intel’s sdk supports two kernels, 3.10 and 4.9, and does not support 4.14. |
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What's up paldier.
This is exciting stuff. I'll get back to you on a few things.
I want to mention that when I put the drivers/net dir in my own buldroot, it whined about LOGGER issues.
admittedly, when I cloned your git and tried to build, I got errors that seemed to reflect differences between 4.14 and 4.9.
someone as schooled as you could comment as to whether the existing code can be ported to 4.14?
I'm trying to consolidate mips targets.
From: paldier
Sent: Friday, 2 April 2021 6:15 PM
To: MerlinRdev/bluecave-merlin
Reply To: MerlinRdev/bluecave-merlin
Cc: gagan sidhu; Author
Subject: Re: [MerlinRdev/bluecave-merlin] GRX350/500 in-kernel support (#21)
Intel’s sdk supports two kernels, 3.10 and 4.9, and does not support 4.14.
If you want to get more information about the 4.9 kernel, you can see https://gitlab.com/prpl-foundation/intel/linux/-/tree/intel-4.9.218
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greetings you beautiful man @paldier. i can confirm i have succesfully loaded mtlkroot using your built root built against my DD-WRT 4.14 : what i found interesting is that it would not load against my v5.10.16-1 backports the only concern i have with the porting is the warning:
does this look promising enough for me to grab this clearance RAX40? my only other reservation is about the actual arch/mips/lantiq code for the GRX500 (which is what i presumably enable for the RAX40) not compiling cleanly. given this driver compiled relatively cleanly, should i be concerned? |
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RAX40? prplwrt is the best. |
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RAX40 is the netgear AX4 (see here https://wikidevi.wi-cat.ru/Netgear_RAX40_(Nighthawk_AX4)) i've never used PRPLWRT but from what i can see that is a different group of users. i'm trying to bring this platform to the mainstream. |
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I don't think openwrt will accept patches related to grx500. |
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i'm not a part of openwrt or dd-wrt. both of their leaders do not like me because i criticise their choices and call them stupid. i am curious to see if i can patch 4.14 using the prplfoundation 4.9 patches. i don't know why openwrt abandoned any lantiq support. i was surprised to see they even had patches for 4.9. their mt76 driver for the mt7615 driver is extremely poor, but they continue to plug their ears whilst making loud noises to drown out any criticisms. it seems this is how things operate with certain groups. |
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There are some lantiq developers in the prplwrt, so joining the prplwrt is the best choice. |
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I will be perusing the sources in the next few days. I'm happy I got this driver to build. Now I have to see if the changes to mips CPS/etc between 4.9 and 4.14 are tolerated by the existing grx500 arch/mips/lantiq code
From: paldier
Sent: Friday, 2 April 2021 8:39 PM
To: MerlinRdev/bluecave-merlin
Reply To: MerlinRdev/bluecave-merlin
Cc: gagan sidhu; Author
Subject: Re: [MerlinRdev/bluecave-merlin] GRX350/500 in-kernel support (#21)
There are some lantiq developers in the prplwrt, so joining the prplwrt is the best choice.
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what's up @paldier i have a question for you man, which 4.9 patches are important? i saw this list of patches: https://github.com/paldier/prplwrt/tree/master/target/linux/lantiq/patches-4.14 but i also remember seeing one directory called "patches-4.9" that had over 100 patches. some of them were hotfixes to the drivers: i want to be sure i'm using the latest and up-to-date patches. |
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hello brother @paldier. i applied all the patches, lol. my question for you is what a good configuration file would be. https://github.com/paldier/feed_target_mips/blob/ugw-8.4.2-cleanup/xrx500_4kec/config-default seems very minimal. i wanna know what ehternet driver, spi , etc i should be configuring. let's say i want to try this with TP-LINK AX50 |
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4kec is only for bootcore, useless |
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should i use this as a template? : https://github.com/paldier/feed_target_mips/blob/ugw-8.4.2-cleanup/xrx500/config-default also, in terms of kernel configuration, can we consider PXB4385/PXB4395/GRX350 as equivalent? |
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There are 6 versions of grx350, only one is not discontinued, npu is automatically configured by firmware, so it's no different to you. |
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so CONFIG_SOC_GRX500 covers all of the existing SoCs (which are "GRX350" i assume)? |
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grx500 includes all grx350 and grx550(except the first version). In fact, it’s just that their clock speeds are different. |
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thanks man. is iwlwav only for WAV654? or will it work for all 6 versions of the grx350? edit: i'm so fucking excited paldier. COHERENT DMA. like, i know this thing is going to haul fucking ass dude. i feel bad for you because it seems very difficult to maintain this platform, and it seems the entire open source effort has fallen on your shoulders. you should be lauded for being composed for this long. it's an impossible task. i've seen all the complaints about this platform and it just amazes me people even have it running on 3.10, let alone manufacturers distributing it. |
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iwlwav only supports wav600 now, the support for wav500 has not been completed, it looks like it won't be finished. |
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was wav500 support close to being finished? maybe your 3.x kernel builds are good, but a lot of the noobs who bought this SoC off the shelf are complaining about multiple reboots etc. personally i have higher hopes for my build. i know for my RALINK 4.x build it's pretty close to padavan, but i can't fully test since i don't have a 160MHz client. you say no hardware nat acceleration for 3.x. i assume hardware nat kernel is even more difficult to build? |
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iwlwav is an open source driver in 4.x kernel, the closed source driver supports wav500 and wav600 in the 3.x kernel. |
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so you mean i have to sign an NDA to get the closed source driver? no hope of an update to 4.x? hopefully iwlwav performance on 3.x isn't bad, if you're able to backport it? just curious about its performance. |
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@paldier are these defaults appropriate for all platforms? 4.9 builds no problem with it enabled ^_^ very excited lol |
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@paldier what DTS do i use? will easywan_350.dts work for the AX50? i'm so pumped. tomorrow (~16 hours) is testing day. this thing is going to haul ass brother, i "believe"!!! |
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@paldier it's so weird flashing this thing. any tips? the unaffiliated individual who acquired this device noticed that the bootloader menu is not typical, and is perplexed as to how to try a different image. they're used to the typical operation of creating a uImage from mkimage, then appending the ubinized squashfs, followed by selecting 'write to flash from TFTP' in u-boot. in comparison, this bootloader seems very different. they are excited, but confused! using this as a template: https://github.com/nirmitg/openwrt/blob/5f915c2dc4bea3d682972ce8471599d0ea1a900c/ugw/target/linux/lantiq/image/Makefile.openwrt i know you don't support AX50 but i thought you'd have some ideas. i didn't know they'd be this different. tp-link's upgrade image seems like a nightmare: |
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@paldier hello? lol. it seems i need to figure out where to get u-boot images. it must be as simple as including firmware and rootfs with u-boot images. could you please point me in the right direction? you have to know. https://github.com/MerlinRdev/bluecave-merlin/tree/master/release/src-lantiq/proprietary seems to have the gphy images, but bluecave seems slightly different. will read this makefile more closely: https://github.com/MerlinRdev/bluecave-merlin/blob/master/release/src-rt/Makefile |
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@paldier can you tell me anything about the u-boot ddr3 timings file? i'm using EVA and i need to use a newer version of the intel u-boot. but i don't have tp-link's DDR3 timings file (missing in GPL). but from what i gather, the u-boot configuration files should be there? |
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It is not a part of SDK |
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ok. i assume i can't use xrx500_phy_fw from @blogic/@openwrt, and i must use ethernet driver's gphy-fw loader? and i assume the firmware in https://github.com/paldier/ltq_fw_phy_ip/xRx5xx should work right? lol switch_api is fucking HUGE man. 500K lol wtf! |
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@paldier bro i'm getting so jacked hooking iwlwav-hostap into the DD-WRT build tree. enabling 80211AX and ACS, settings that he has never used for his builds. this thing better haul ass man!! |
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@paldier do you know if it's possible to use the iwlwav-dev backports driver with a newer backports? i'm wondering if the iwlwav-dev using backports-3.10 (instead of 4.9, which is what i'm using) may optimise performance. i know you said intel tested on a 4.9 kernel, but i haven't tried to update the backports since the tree builds with the 4.9 target kernel easily. i didn't realise until now it's using backports 3.10 |
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after using switch_cli commands, i assume your devices have the proper mac address? i will try to study your script. i found a similar one in the AX50 romfs. it is a lot of work to set it up manually, but the randomly-generated mac addresses for LTQ_ETH_XRX500 is very annoying. i should be able to use this script to make my life easier. or so i hope. and is it possible to use both XRX500_PHY_FW with switch_cli? i do not want to load the firmware manually, if i can avoid it. how did you parse your eeprom file? i tried 'strings' but that did not work. |
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@paldier, i have another question for you (sorry for inundating you with questions). this time, it's related to the value of /proc/loadavg. it seems wrong. in htop, it looks "right"
but, the value in /proc/loadavg increases to the maximum.
is the value reported by HTOP correct? originally it would show maximum load on the first core (for a very short period, under a second), before showing the values in the first picture. i am hoping this is a side-effect of the LTQ_VMB driver, which the kernel relies upon to launch the secondary processors. i am assuming VMB consumes the maximum resources available so it can offload them appropriately, as we do not have in-kernel assistance from MIPS_CPS. even if i disable LTQ_ETH_DRV_XRX500, it will have a value of 4 and eventually reduce to 1, but never lower. so i am not certain as to whether these unusual values are purely a consequence of VMB. for sureeeeeeeee bro. i checked out the stock firmware and that hting is reporting like 4x rofl. VMB is fucking WILD, dude. absolutely WILD edit: i was so worried @paldier, lol. i thought there was some errant behaviour in the drivers. PHEW |
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The normal load average value of ap mode is 3.x, the normal load average value of ap+client mode is 6.x, it is not a problem. |
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ok. man, i'm so close! now there's an issue with finalising initialisation of radios!! what do you think the problem could be for the failure to allocate the DP port? init seemed fine: is failure to allocate dp port when loading MTLK normal, when using LTQ_ETH_XRX500? i hope so. now MTLK init fails due to some message timeout |
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@paldier how do turn off port 0 then? i didn't even know it was enabled. i am not changing any settings, all are default. i tried using value 1 and same thing no matter what port is chosen, it will still fail: ooooo mi gosshhhh hhhhhh @paldier |
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@paldier is there anything special i need to do, to ensure the device has a mac address? i have to look more in-depth, but it seems a simple call of only creates the interface, with no mac address. i have to double check but that's what's happening. i find the lack of mac addresses from the hardware to be strange. this should be automated and i hope i'm overlooking a simple configuration feature or a DTS setting. |
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and also @paldier: is "fapi_wlan_daemon" required? tp-link boot shows this just wondering what exactly this program does. is it simply a daemon to manage hostapd? seems annoying to compile (https://github.com/prplfoundation/prplMesh-common) i hate CMAKE :P when i set mac address manually and run hostapd (successfully), i still cannot access 'iw iwlwav " for some reason. i am using intel's iwlwav-iw: |
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@paldier forgive me for overwhelming you with questions, i didn't realise i'm "kind of" ahead of everyone :/ it's kind of exciting. many of the have changed in 4.x :P in 3.x, this command works fine: but in 4.x it does not: i guess i'm going to have to figure out some of this stuff on my own. also i'm only looking at the TP-LINK firmware properly for the first time, and it's very strange. their log for boot is similar to mine but they have FOUR devices in IW! is my configuration wrong, or is it fine and theirs is just because of backporting very new wifi stuff to 3.x? man this is cooler than i thought it would be. i expected to have a firmware by now, but i should be happy i'm this far. this feels like fresh research |
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wlan0 wlan2 are ap, wlan1 wlan3 are client |
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@paldier thank you is there specific setting for mtlk devices in hostapd to allow connections? iw reports both radios up, hostapd running, but cannot SSID or connect to it manually: wlan0/wlan1_hostap.conf relevant log: it should work, from the above log, correct? maybe i'm missing something. |
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phy0 ap phy1 client phy2 ap phy3 client |
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AP/CLIENT mapping seems OK. cannot delete wlan0 or wlan1 after using checked /proc/net/mtlk/wlan2: so iw wlan1 is correctly sending information to MTLK wlan2. hostapd running, but cannot connect. very strange. |
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@paldier i think i know why radios are working but client' can't see SSIDS. i did not compile fapi_wlan_common these programs/libraries are necessary for the final step of wlan initialisation, right? |
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yes |
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after dd-wrt create wlan_hostap.conf files, with driver reporting: how do i use fapi_wlan_cli? i have no idea on how to use this program to complete the process. iw reports the following: is libfapi newer than fapi_wlan_common? i really want to finish this. do i use lantiq_cmd+libfapi or can i use fapi_wlan_common+libhelper? is there any way to access lantiq_cmd+libfapi sources? i am using libhelper 1.4.0.0 and fapi_wlan_common-05.04.00.131 |
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@i3roly please tell me you got further with this |
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I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
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I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
…________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
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Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
…________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
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I have TP-Link Archer AX50 (AX3000)
Thank you,
Ethersloth
…________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, October 30, 2022 9:41 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
Reply to this email directly, view it on GitHub<#21 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AITLEG6E2LIRNVHKUI6LB5TWBCUO5ANCNFSM42JIODIA>.
You are receiving this because you were mentioned.Message ID: ***@***.***>
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finished building the rootfs today, works fine.
they also shared their proprietary loading program, so i suspect i'll be able to flash from the GUI.
i just don't want to brick this on my first shot so i am going to try my best and be sure i have everything set up right.
nervous and exciting times!
…________________________________
From: ethersloth ***@***.***>
Sent: October 30, 2022 10:18 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: gagan sidhu ***@***.***>; Mention ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have TP-Link Archer AX50 (AX3000)
Thank you,
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, October 30, 2022 9:41 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
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what's up slob.
i've got everything set up.
resetbutton works. so does the WPS and SES buttons for shutting down/turning on the radios.
LEDs all work except the power button, it's strange. even though i know its gpio, it won't turn on or off.
just waiting on the people at maxlinear to give a working driver (https://prplfoundationcloud.atlassian.net/browse/PCI-21) so i can begin the flash process.
i think once i figure that out, we should be good to go.
…________________________________
From: Gagan Sidhu ***@***.***>
Sent: November 19, 2022 12:03 PM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
finished building the rootfs today, works fine.
they also shared their proprietary loading program, so i suspect i'll be able to flash from the GUI.
i just don't want to brick this on my first shot so i am going to try my best and be sure i have everything set up right.
nervous and exciting times!
________________________________
From: ethersloth ***@***.***>
Sent: October 30, 2022 10:18 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: gagan sidhu ***@***.***>; Mention ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have TP-Link Archer AX50 (AX3000)
Thank you,
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, October 30, 2022 9:41 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
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You are receiving this because you were mentioned.Message ID: ***@***.***>
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|
|
Just want to say how much I appreciate your efforts.
…-Ethersloth-
________________________________
From: gagan sidhu ***@***.***>
Sent: Saturday, November 19, 2022 1:03 PM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
finished building the rootfs today, works fine.
they also shared their proprietary loading program, so i suspect i'll be able to flash from the GUI.
i just don't want to brick this on my first shot so i am going to try my best and be sure i have everything set up right.
nervous and exciting times!
________________________________
From: ethersloth ***@***.***>
Sent: October 30, 2022 10:18 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: gagan sidhu ***@***.***>; Mention ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have TP-Link Archer AX50 (AX3000)
Thank you,
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, October 30, 2022 9:41 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
Reply to this email directly, view it on GitHub<#21 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AITLEG6E2LIRNVHKUI6LB5TWBCUO5ANCNFSM42JIODIA>.
You are receiving this because you were mentioned.Message ID: ***@***.***>
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|
check this out @etherslob @paldier @danielschwierzeck did me a solid and "left it all out there", producing the latest possible u-boot for lantiq devices. he "left it all out there". just hope i can get a working wifi-driver so that we can use it. it's sick af |
|
Sloth I may need an ax50. I am gonna try to flash this u-boot :x
bless,
g
From: ethersloth
Sent: Saturday, 3 December 2022 7:04 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Just want to say how much I appreciate your efforts.
…-Ethersloth-
________________________________
From: gagan sidhu ***@***.***>
Sent: Saturday, November 19, 2022 1:03 PM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
finished building the rootfs today, works fine.
they also shared their proprietary loading program, so i suspect i'll be able to flash from the GUI.
i just don't want to brick this on my first shot so i am going to try my best and be sure i have everything set up right.
nervous and exciting times!
________________________________
From: ethersloth ***@***.***>
Sent: October 30, 2022 10:18 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: gagan sidhu ***@***.***>; Mention ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have TP-Link Archer AX50 (AX3000)
Thank you,
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, October 30, 2022 9:41 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
Reply to this email directly, view it on GitHub<#21 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AITLEG6E2LIRNVHKUI6LB5TWBCUO5ANCNFSM42JIODIA>.
You are receiving this because you were mentioned.Message ID: ***@***.***>
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You are receiving this because you commented.Message ID: ***@***.***>
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|
|
Is there I way I can run this test? I don't mind shipping one out to you but I won't have the money for that until sometime in February. Gotta recover from Christmas.
Thank you,
…________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, December 27, 2022 4:30 PM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Sloth I may need an ax50. I am gonna try to flash this u-boot :x
bless,
g
From: ethersloth
Sent: Saturday, 3 December 2022 7:04 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Just want to say how much I appreciate your efforts.
-Ethersloth-
________________________________
From: gagan sidhu ***@***.***>
Sent: Saturday, November 19, 2022 1:03 PM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
finished building the rootfs today, works fine.
they also shared their proprietary loading program, so i suspect i'll be able to flash from the GUI.
i just don't want to brick this on my first shot so i am going to try my best and be sure i have everything set up right.
nervous and exciting times!
________________________________
From: ethersloth ***@***.***>
Sent: October 30, 2022 10:18 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: gagan sidhu ***@***.***>; Mention ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have TP-Link Archer AX50 (AX3000)
Thank you,
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, October 30, 2022 9:41 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
Which ones? I have the tplink ax90 or whatever it is.
If you have a netgear rax40 that'd be handy.
Btw I did email tplink a few weeks ago about this and they said they're making it a priority to have a GPL release that compiles the image properly.
I'm probably not going to re-do the entire tree but hopefully pull out the parts that have changed. It was a lot of work getting the iplatform source to build normally.
From: ethersloth
Sent: Sunday, 30 October 2022 7:33 AM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I have a couple of these wifi routers if you want me to send you one for testing?
Ethersloth
________________________________
From: gagan sidhu ***@***.***>
Sent: Tuesday, October 11, 2022 2:19 AM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Comment ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
I really can't do much at this time.
I have a kernel that boots and a driver that loads, but for some reason the radios aren't visible.
It could be that they only work properly when I have a build that boots off the flash instead of memory.
I was trying to make a bootable image but the danger with the lantiq is vendors rewrite the entire nand (including the bootloader).
Tplink has some weird program that runs in the background to ensure there is always a viable kernel on a partition, that's how dangerous flashing a custom Fw can be.
Nonetheless I wouldn't mind losing this router if I had something to test.
The good news is I have their GPL code building 100% right. The bad news is they fucked up something in their makefiles so it doesn't build the final image.
The plan is to make a 'stock' firmware from the GPL that flashes, so I know the flash image structure. From there I need to make sure the dd-wrt flash approach from gui will be able to rewrite the whole nand.
After that everything may be a little easier.
Give me a couple of weeks. I have to write some retarded tests the week after next.
From: ethersloth
Sent: Saturday, 1 October 2022 3:30 PM
To: SWRT-dev/bluecave-asuswrt
Reply To: SWRT-dev/bluecave-asuswrt
Cc: gagan sidhu; Mention
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
@i3roly<https://github.com/i3roly> please tell me you got further with this
—
Reply to this email directly, view it on GitHub<#21 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AITLEG6E2LIRNVHKUI6LB5TWBCUO5ANCNFSM42JIODIA>.
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it's all good slob (i realised your name is @ethersloth but whatever lol) we're in doggy. just need a wifi driver now so i can put this all together this new u-boot is so sick. i overclocked the CPU to 1 GHZ and the ram is now at DDR3 400 (x4) instead of 333. cc @paldier |
|
this is to my boy SLOB (lol whatever i know its @ethersloth). nand boot up. reset button works. everything looks good. bigger challenge will be getting this to write from the tp-link firmware (once i can figure out how to flash the stock fw back lol) and then vice-versa (in case someone, for some weird reason, wants to go back to that shit u-boot and partition setup). ready to bury that piece of shit cortex A8 and derivatives. let's go! cc @paldier |
|
Dude you're amazing. Let me know when you have an image to test, I can be a guinea pig
Thanks,
your pal slob.
…________________________________
From: gagan sidhu ***@***.***>
Sent: Sunday, January 29, 2023 2:01 PM
To: SWRT-dev/bluecave-asuswrt ***@***.***>
Cc: ethersloth ***@***.***>; Mention ***@***.***>
Subject: Re: [SWRT-dev/bluecave-asuswrt] GRX350/500 in-kernel support (#21)
this is to my boy SLOB (lol whatever i know its @ethersloth<https://github.com/ethersloth>).
nand boot up. reset button works. everything looks good.
bigger challenge will be getting this to write from the tp-link firmware (once i can figure out how to flash the stock fw back lol) and then vice-versa (in case someone, for some weird reason, wants to go back to that shit u-boot and partition setup).
ready to bury that piece of shit cortex A8 and derivatives. let's go!
ROM VER: 2.1.0
CFG 0a
B
..
.
U-Boot SPL 2016.07-g025914c9ba-dirty (Jan 28 2023 - 20:50:21)
SPL: initializing NAND flash
SPL: loading U-Boot to RAM
SPL: checking U-Boot image
SPL: decompressing U-Boot with LZO
SPL: jumping to U-Boot
U-Boot 2016.07-g025914c9ba-dirty (Jan 28 2023 - 20:50:21 -0700) easy550
CPU: InterAptiv
Board: Intel EASY550 reference boards
DRAM: 256 MiB
NAND: 128 MiB
In: serial
Out: serial
Err: serial
Net: grx550-eth
=> tftpboot 80800000 grxkernel.bin
Waiting for PHY link
Using PHY at addr 2, speed 1000, duplex 1
Using grx550-eth device
TFTP from server 192.168.2.101; our IP address is 192.168.2.1
Filename 'grxkernel.bin'.
Load address: 0x80800000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
########################################
741.2 KiB/s
done
Bytes transferred = 4194304 (400000 hex)
=> ub<INTERRUPT>
=> ubi werite kern<INTERRUPT>
=> ubi write 80800000 kernel 700000
7340032 bytes written to volume kernel
=> ubi read 80800000 kernel
Read 0 bytes from volume kernel to 80800000
No size specified -> Using max size (7364608)
=> bootm 80800000
## Booting kernel from Legacy Image at 80800000 ...
Image Name: MaxLinear GRX500 Kernel Image
Image Type: MIPS Linux Kernel Image (lzma compressed)
Data Size: 3326911 Bytes = 3.2 MiB
Load Address: 80020000
Entry Point: 80020400
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
[ 0.000000] Linux version 4.9.337 ***@***.***) (gcc version 12.2.0 (GCC) #4297 SMP PREEMPT Sun Jan 29 12:44:38 MST 2023
[ 0.000000] SoC: GRX500 rev 1.2
[ 0.000000] bootconsole [early0] enabled
[ 0.000000] CPU0 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.000000] Enhanced Virtual Addressing (EVA Legacy 512MB) activated
[ 0.000000] MIPS: machine is EASY350 ANYWAN (GRX350) Main model
[ 0.000000] Coherence Manager IOCU detected
[ 0.000000] Hardware DMA cache coherency disabled
[ 0.000000] Determined physical RAM map:
[ 0.000000] memory: 0e000000 @ 20000000 (usable)
[ 0.000000] memory: 00007fc3 @ 209f2d00 (reserved)
[ 0.000000] cma: Reserved 32 MiB at 0x2c000000
[ 0.000000] SMPCMP: CPU0: cmp_smp_setup
[ 0.000000] VPE topology {2,2} total 4
[ 0.000000] Detected 3 available secondary CPU(s)
[ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000020000000-0x0000000027ffffff]
[ 0.000000] Normal [mem 0x0000000028000000-0x000000002dffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000020000000-0x000000002dffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000020000000-0x000000002dffffff]
[ 0.000000] On node 0 totalpages: 57344
[ 0.000000] free_area_init_node: node 0, pgdat 809b9a40, node_mem_map 88000040
[ 0.000000] DMA zone: 256 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 32768 pages, LIFO batch:7
[ 0.000000] Normal zone: 192 pages used for memmap
[ 0.000000] Normal zone: 24576 pages, LIFO batch:3
[ 0.000000] percpu: Embedded 12 pages/cpu s19024 r8192 d21936 u49152
[ 0.000000] pcpu-alloc: s19024 r8192 d21936 u49152 alloc=12*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 56896
[ 0.000000] Kernel command line: console=ttyLTQ0,115200n8r nr_cpus=4 clk_ignore_unused debug ubi.mtd=ubi root=/dev/mtdblock6
[ 0.000000] log_buf_len individual max cpu contribution: 4096 bytes
[ 0.000000] log_buf_len total cpu_extra contributions: 12288 bytes
[ 0.000000] log_buf_len min size: 16384 bytes
[ 0.000000] log_buf_len: 32768 bytes
[ 0.000000] early log buf free: 13768(84%)
[ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[ 0.000000] Writing ErrCtl register=00000000
[ 0.000000] Readback ErrCtl register=00000000
[ 0.000000] Memory: 182104K/229376K available (7491K kernel code, 375K rwdata, 1956K rodata, 336K init, 1825K bss, 14504K reserved, 32768K cma-reserved)
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 32.
[ 0.000000] NR_IRQS:527
[ 0.000000] EIC is off
[ 0.000000] VINT is on
[ 0.000000] CPU Clock: 1000000000Hz mips_hpt_frequency 500000000Hz
[ 0.000000] clocksource: gptc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 9556302233 ns
[ 0.000009] sched_clock: 32 bits at 200MHz, resolution 5ns, wraps every 10737418237ns
[ 0.008318] Calibrating delay loop... 663.55 BogoMIPS (lpj=1327104)
[ 0.042613] pid_max: default: 4096 minimum: 301
[ 0.047350] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.053915] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.062038] CCA is coherent, multi-core is fine
[ 0.132140] [vmb_cpu_alloc]:[642] CPU vpet.cpu_status = 11
[ 0.137560] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[ 0.137568] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.137580] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[ 0.137819] CPU2 revision is: 0001a120 (MIPS interAptiv (multi))
[ 0.168384] Brought up 2 CPUs
[ 0.198722] devtmpfs: initialized
[ 0.210792] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.220465] futex hash table entries: 16 (order: -3, 512 bytes)
[ 0.228367] pinctrl core: initialized pinctrl subsystem
[ 0.234926] NET: Registered protocol family 16
[ 0.239324] XRX500 GPIO Driver, (C) 2014 Lantiq Deutschland Gmbh
[ 0.247360] dma-grx500 1e300000.dma: dma3 base address be300000 chained_irq 29 irq_base 30
[ 0.257268] dma-grx500 1e300000.dma: Init done - rev: a, ports: 1, channels: 64
[ 0.266089] dma-grx500 1c100000.dma: dma2tx base address bc100000 chained_irq 103 irq_base 104
[ 0.275064] dma-grx500 1c100000.dma: Init done - rev: a, ports: 1, channels: 16
[ 0.282611] dma-grx500 1c200000.dma: dma2rx base address bc200000 chained_irq 120 irq_base 121
[ 0.292008] dma-grx500 1c200000.dma: Init done - rev: a, ports: 1, channels: 32
[ 0.299819] dma-grx500 1a100000.dma: dma1tx base address ba100000 chained_irq 153 irq_base 154
[ 0.308760] dma-grx500 1a100000.dma: Init done - rev: a, ports: 1, channels: 16
[ 0.316268] dma-grx500 1a200000.dma: dma1rx base address ba200000 chained_irq 170 irq_base 171
[ 0.325123] dma-grx500 1a200000.dma: Init done - rev: a, ports: 1, channels: 12
[ 0.337570] dma0-grx500 16e00000.dma: base address b6e00000 chained_irq 228 irq_base 229
[ 0.345558] dma0-grx500 16e00000.dma: Init done - hw rev: A, ports: 4, channels: 16
[ 0.353434] intel-pinctrl 16c80000.pinctrl: pinbank id: 0, reg: 0xb6c80000, pinbase: 0, pin number: 32, pinmap: 0xf1efefff
[ 0.364367] intel-pinctrl 16c80000.pinctrl: pinbank id: 1, reg: 0xb6c80100, pinbase: 32, pin number: 32, pinmap: 0x3bff0c1f
[ 0.375767] intel-pinctrl 16c80000.pinctrl: Total 18 groups, 18 functions
[ 0.382576] intel-pinctrl 16c80000.pinctrl: gpiochip membase: 0xb6c00000
[ 0.389665] intel-pinctrl 16c80000.pinctrl: gpiochip membase: 0xb6c00100
[ 0.411300] FPU Affinity set after 5328 emulations
[ 0.428384] Lantiq MIPSInterAptiv MPS driver, version 1.0.0.0, (c) 2006-2013 Lantiq Deutschland GmbH
[ 0.437856] MPS: major Id 253
[ 0.440968] No syscon phandle specified for wan mux
[ 0.513706] [cbm] { cbm_xrx500_probe : 5205 }reserving 18874368 bytes @ 8c000000 for CBM
[ 0.552209] [cbm] { cbm_xrx500_probe : 5216 }reserving 8388608 bytes @ 8d200000 for CBM
[ 0.560160] [cbm] { cbm_xrx500_probe : 5228 }94 irq
[ 0.565268] [cbm] { cbm_xrx500_probe : 5251 }2
[ 0.569652] [drv_tmu_ll] { get_cbm_clock : 7807 }CBM Clock: 600000000Hz=600MHZ
[ 0.576927] Initializing TMU with Base Address=be700000: ...
[ 0.585659] TMU Initialization Done
[ 0.588982] 0x8c000000 0x1200000 0x800
[ 0.592799] 0x8c000000 0x1200000
[ 0.596098] 0x8d200000 0x800000 0x2000
[ 0.599901] 0x8d200000 0x800000
[ 0.603480] [cbm] { init_fsqm_buf_std : 835 }init fsqm std successfully
[ 0.609962] [cbm] { init_fsqm_buf_jumbo : 877 }init fsqm jbo successfully
[ 0.616783] [cbm] { init_fsqm : 904 }fsqm init successfully
[ 0.622426] [cbm] { init_cbm_basic : 939 }PHY ADDR STD 0x2c000000
[ 0.628589] [cbm] { init_cbm_basic : 940 }PHY ADDR JBO 0x2d200000
[ 0.634909] [cbm] { init_cbm_basic : 958 }init basic CBM successfully
[ 0.641271] [cbm] { cbm_hw_init : 1856 }CBM HW init
[ 0.646304] [cbm] { setup_DMA_p2p : 4661 }setup_DMA_p2p executed
[ 0.652294] [cbm] { reserved_ports_highest : 4720 }2 2 19 35
[ 0.658016] [cbm] { init_cbm_dqm_cpu_port : 1102 }2
[ 0.662986] [cbm] { assign_port_from_DT : 467 }0x0 2
[ 0.667998] [cbm] { assign_port_from_DT : 467 }0x20 2
[ 0.673252] [cbm] { cbm_add_to_list : 261 }1
[ 0.677463] [cbm] { reserved_ports_highest : 4720 }1 1 18 34
[ 0.683188] [cbm] { init_cbm_dqm_cpu_port : 1102 }1
[ 0.688147] [cbm] { assign_port_from_DT : 467 }0x80 1
[ 0.693260] [cbm] { reserved_ports_highest : 4720 }3 3 20 36
[ 0.698986] [cbm] { init_cbm_dqm_cpu_port : 1102 }3
[ 0.703944] [cbm] { assign_port_from_DT : 467 }0x2000000 3
[ 0.709490] [cbm] { cbm_add_to_list : 261 }1
[ 0.713831] [cbm] { reserved_ports_highest : 4720 }6 6 0 16
[ 0.719473] [cbm] { dma_port_enable : 4294 }6 0x4
[ 0.724258] [cbm] { reserved_ports_highest : 4720 }7 7 1 17
[ 0.729890] [cbm] { dma_port_enable : 4294 }7 0x4
[ 0.734684] [cbm] { reserved_ports_highest : 4720 }8 8 2 18
[ 0.740306] [cbm] { dma_port_enable : 4294 }8 0x4
[ 0.745090] [cbm] { reserved_ports_highest : 4720 }9 9 3 19
[ 0.750721] [cbm] { dma_port_enable : 4294 }9 0x4
[ 0.755506] [cbm] { reserved_ports_highest : 4720 }10 10 4 20
[ 0.761311] [cbm] { dma_port_enable : 4294 }10 0x4
[ 0.766183] [cbm] { reserved_ports_highest : 4720 }11 11 5 21
[ 0.771988] [cbm] { dma_port_enable : 4294 }11 0x4
[ 0.776859] [cbm] { reserved_ports_highest : 4720 }12 12 6 22
[ 0.782665] [cbm] { dma_port_enable : 4294 }12 0x4
[ 0.787536] [cbm] { reserved_ports_highest : 4720 }13 13 7 23
[ 0.793342] [cbm] { dma_port_enable : 4294 }13 0x4
[ 0.798213] [cbm] { reserved_ports_highest : 4720 }14 14 8 24
[ 0.804018] [cbm] { dma_port_enable : 4294 }14 0x4
[ 0.808890] [cbm] { reserved_ports_highest : 4720 }15 15 9 25
[ 0.814695] [cbm] { dma_port_enable : 4294 }15 0x4
[ 0.819566] [cbm] { reserved_ports_highest : 4720 }16 16 10 26
[ 0.825458] [cbm] { dma_port_enable : 4294 }16 0x4
[ 0.830330] [cbm] { reserved_ports_highest : 4720 }17 17 11 27
[ 0.836222] [cbm] { dma_port_enable : 4294 }17 0x4
[ 0.841094] [cbm] { reserved_ports_highest : 4720 }18 18 -16 0
[ 0.846985] [cbm] { dma_port_enable : 4294 }18 0x4
[ 0.851876] [cbm] { reserved_ports_highest : 4720 }19 19 12 28
[ 0.857749] [cbm] { dma_port_enable : 4294 }19 0x4
[ 0.862620] [cbm] { reserved_ports_highest : 4720 }20 20 13 29
[ 0.868513] [cbm] { dma_port_enable : 4294 }20 0x4
[ 0.873383] [cbm] { init_special_ports : 4727 }20
[ 0.878148] [cbm] { cbm_add_to_list : 261 }1
[ 0.882488] [cbm] { reserved_ports_highest : 4720 }21 21 14 30
[ 0.888390] [cbm] { dma_port_enable : 4294 }21 0x4
[ 0.893260] [cbm] { init_special_ports : 4727 }21
[ 0.898025] [cbm] { cbm_add_to_list : 261 }1
[ 0.902371] [cbm] { reserved_ports_highest : 4720 }22 22 25 41
[ 0.908269] [cbm] { dma_port_enable : 4294 }22 0x4
[ 0.913140] [cbm] { reserved_ports_highest : 4720 }23 23 15 31
[ 0.919033] [cbm] { init_cbm_dqm_ldma_port : 1135 }23
[ 0.924165] [cbm] { reserved_ports_highest : 4720 }5 5 21 37
[ 0.929883] [cbm] { init_cbm_dqm_scpu_port : 1116 }5
[ 0.935054] [cbm] { reserved_ports_highest : 4720 }4 4 16 32
[ 0.940646] [cbm] { init_cbm_dqm_cpu_port : 1102 }4
[ 0.945602] [cbm] { assign_port_from_DT : 467 }0x8 4
[ 0.950629] [cbm] { reserved_ports_highest : 4720 }24 24 22 38
[ 0.956529] [cbm] { init_cbm_dqm_cpu_port : 1102 }24
[ 0.961574] [cbm] { assign_port_from_DT : 467 }0x8 24
[ 0.966688] [cbm] { reserved_ports_highest : 4720 }25 25 23 39
[ 0.972588] [cbm] { init_cbm_dqm_cpu_port : 1102 }25
[ 0.977633] [cbm] { assign_port_from_DT : 467 }0x8 25
[ 0.982746] [cbm] { reserved_ports_highest : 4720 }26 26 24 40
[ 0.988646] [cbm] { init_cbm_dqm_cpu_port : 1102 }26
[ 0.993691] [cbm] { assign_port_from_DT : 467 }0x8 26
[ 0.998804] [cbm] { init_cbm_eqm_cpu_port : 965 }0
[ 1.003663] [cbm] { init_cbm_eqm_cpu_port : 965 }1
[ 1.008524] [cbm] { init_cbm_eqm_cpu_port : 965 }2
[ 1.013385] [cbm] { init_cbm_eqm_cpu_port : 965 }3
[ 1.018247] [cbm] { dma_port_enable : 4294 }5 0x1
[ 1.023025] [cbm] { dma_port_enable : 4294 }5 0x2
[ 1.027796] [cbm] { dma_port_enable : 4294 }6 0x1
[ 1.032570] [cbm] { dma_port_enable : 4294 }6 0x2
[ 1.037344] [cbm] { dma_port_enable : 4294 }7 0x1
[ 1.042118] [cbm] { dma_port_enable : 4294 }7 0x2
[ 1.046892] [cbm] { dma_port_enable : 4294 }8 0x1
[ 1.051666] [cbm] { dma_port_enable : 4294 }8 0x2
[ 1.056441] [cbm] { dma_toe_port_enable : 4321 }9 0x1
[ 1.061563] [cbm] { dma_vrx318_port_enable : 4334 }15 0x1
[ 1.067043] [cbm] { init_cbm_dqm_cpu_port : 1102 }0
[ 1.071978] [cbm] { init_cbm_dqm_cpu_port : 1102 }2
[ 1.076926] Load spreader init successfully
[ 1.081269] [cbm] { cbm_xrx500_probe : 5307 }CBM Clock: 600000000Hz
[ 1.087517] [cbm] { cbm_xrx500_probe : 5309 }EQM delay Enabled
[ 1.093419] [cbm] { igp_delay_set : 4385 }port0 delay16
[ 1.098712] [cbm] { igp_delay_set : 4385 }port1 delay16
[ 1.104007] [cbm] { igp_delay_set : 4385 }port2 delay16
[ 1.109302] [cbm] { igp_delay_set : 4385 }port3 delay16
[ 1.114597] [cbm] { igp_delay_set : 4385 }port4 delay16
[ 1.119892] [cbm] { igp_delay_set : 4385 }port5 delay16
[ 1.125187] [cbm] { igp_delay_set : 4385 }port6 delay16
[ 1.130482] [cbm] { igp_delay_set : 4385 }port7 delay16
[ 1.135777] [cbm] { igp_delay_set : 4385 }port8 delay16
[ 1.141072] [cbm] { igp_delay_set : 4385 }port9 delay16
[ 1.146367] [cbm] { igp_delay_set : 4385 }port10 delay16
[ 1.151748] [cbm] { igp_delay_set : 4385 }port11 delay16
[ 1.157130] [cbm] { igp_delay_set : 4385 }port12 delay16
[ 1.162512] [cbm] { igp_delay_set : 4385 }port13 delay16
[ 1.167894] [cbm] { igp_delay_set : 4385 }port14 delay16
[ 1.173276] [cbm] { igp_delay_set : 4385 }port15 delay16
[ 1.178661] [cbm] { enqueue_dma_port_init : 4215 }5 0x2 2 0 30
[ 1.184577] [cbm] { enqueue_dma_port_init : 4215 }5 0x1 2 14 0
[ 1.190468] [cbm] { enqueue_dma_port_init : 4215 }6 0x2 2 0 31
[ 1.196371] [cbm] { enqueue_dma_port_init : 4215 }6 0x1 2 15 0
[ 1.202273] [cbm] { enqueue_dma_port_init : 4215 }7 0x2 1 0 6
[ 1.208133] [cbm] { enqueue_dma_port_init : 4215 }7 0x1 1 0 0
[ 1.213906] [cbm] { enqueue_dma_port_init : 4215 }8 0x2 1 0 11
[ 1.219807] [cbm] { enqueue_dma_port_init : 4215 }8 0x1 1 5 0
[ 1.225621] [cbm] { cbm_xrx500_probe : 5350 }CBM: Init Done !![ 1.254228] vgaarb: loaded
[ 1.257116] SCSI subsystem initialized
[ 1.260920] usbcore: registered new interface driver usbfs
[ 1.266318] usbcore: registered new interface driver hub
[ 1.271680] usbcore: registered new device driver usb
[ 1.277864] i2c-lantiq 16a00000.i2c: version 1.01
[ 1.283168] try to register spd_mon driver[ 1.287095] spdmon 16080110.speedm: base address: 0xb6080110
[ 1.292693] spdmon 16080110.speedm: PHY base address: 0x16080110
[ 1.298960] spdmon 16080110.speedm: spd_mon driver : init done !!
[ 1.307073] spd_mon driver registered
[ 1.311955] clocksource: Switched to clocksource gptc
[ 1.318901] NET: Registered protocol family 2
[ 1.323364] IP idents hash table entries: 4096 (order: 3, 32768 bytes)
[ 1.330568] TCP established hash table entries: 2048 (order: 1, 8192 bytes)
[ 1.337440] TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
[ 1.343920] TCP: Hash tables configured (established 2048 bind 2048)
[ 1.350381] UDP hash table entries: 128 (order: 0, 4096 bytes)
[ 1.356234] UDP-Lite hash table entries: 128 (order: 0, 4096 bytes)
[ 1.362755] NET: Registered protocol family 1
[ 1.367024] PCI: CLS 0 bytes, default 32
[ 1.372606] workingset: timestamp_bits=30 max_order=16 bucket_order=0
[ 1.388619] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 1.401033] io scheduler noop registered
[ 1.405093] io scheduler cfq registered (default)
[ 1.410380] intel-pcie-slim-phy 18500000.pciephy: PCIe slim phy[0] init success!
[ 1.418082] intel-pcie-slim-phy 18000000.pciephy: PCIe slim phy[1] init success!
[ 1.425544] intel-pcie-slim-phy 18a00000.pciephy: PCIe slim phy[2] init success!
[ 1.539965] OF: PCI: host bridge ***@***.*** ranges:
[ 1.545072] OF: PCI: MEM 0xb8000000..0xbaffffff -> 0xb8000000
[ 1.551037] OF: PCI: IO 0xbb800000..0xbb80ffff -> 0xbb800000
[ 1.559186] intel-pcie-slim-phy 18500000.pciephy: PCIe LCPLL SSC Mode Enabled
[ 1.702007] intel-pcie 18900000.pcie: PCI host bridge to bus 0000:00
[ 1.708227] pci_bus 0000:00: root bus resource [bus 00-08]
[ 1.713763] pci_bus 0000:00: root bus resource [mem 0xb8000000-0xbaffffff]
[ 1.720706] pci_bus 0000:00: root bus resource [io 0xbb800000-0xbb80ffff]
[ 1.727652] pci_bus 0000:00: scanning bus
[ 1.731764] pci 0000:00:00.0: [1bef:0030] type 01 class 0x060400
[ 1.737917] pci 0000:00:00.0: supports D1 D2
[ 1.742148] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 1.748571] pci 0000:00:00.0: PME# disabled
[ 1.753039] pci_bus 0000:00: fixups for bus
[ 1.757084] pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 0
[ 1.763846] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 1.771926] pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1
[ 1.778811] pci_bus 0000:01: scanning bus
[ 1.782803] pci 0000:01:00.0: [8086:09d0] type 00 class 0x0d8000
[ 1.788869] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x01ffffff]
[ 1.795341] pci 0000:01:00.0: supports D1 D2
[ 1.799523] pci 0000:01:00.0: PME# supported from D0 D1 D3hot D3cold
[ 1.805947] pci 0000:01:00.0: PME# disabled
[ 1.810224] pci 0000:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x1 link at 0000:00:00.0 (capable of 15.752 Gb/s with 8 GT/s x2 link)
[ 1.824173] pci_bus 0000:01: fixups for bus
[ 1.828268] pci 0000:00:00.0: PCI bridge to [bus 01-08]
[ 1.833553] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
[ 1.839713] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 1.846571] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 1.853860] pci_bus 0000:01: bus scan returning with max=01
[ 1.859505] pci_bus 0000:01: busn_res: [bus 01-08] end is updated to 01
[ 1.866190] pci_bus 0000:00: bus scan returning with max=01
[ 1.871897] pci 0000:00:00.0: fixup irq: got 281
[ 1.876518] pci 0000:00:00.0: assigning IRQ 281
[ 1.881138] pci 0000:01:00.0: fixup irq: got 281
[ 1.885804] pci 0000:01:00.0: assigning IRQ 281
[ 1.890449] pci 0000:00:00.0: BAR 8: assigned [mem 0xb8000000-0xb9ffffff]
[ 1.897269] pci 0000:00:00.0: BAR 9: assigned [mem 0xba000000-0xba0fffff pref]
[ 1.904557] pci 0000:00:00.0: BAR 7: assigned [io 0xbb800000-0xbb800fff]
[ 1.911418] pci 0000:01:00.0: BAR 0: assigned [mem 0xb8000000-0xb9ffffff]
[ 1.918276] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 1.923305] pci 0000:00:00.0: bridge window [io 0xbb800000-0xbb800fff]
[ 1.930163] pci 0000:00:00.0: bridge window [mem 0xb8000000-0xb9ffffff]
[ 1.937020] pci 0000:00:00.0: bridge window [mem 0xba000000-0xba0fffff pref]
[ 1.944373] intel-pcie 18900000.pcie: Intel AXI PCIe Root Complex Port 0 Init Done
[ 2.059973] OF: PCI: host bridge ***@***.*** ranges:
[ 2.065063] OF: PCI: MEM 0xb4000000..0xb6ffffff -> 0xb4000000
[ 2.071036] OF: PCI: IO 0xb7800000..0xb780ffff -> 0xb7800000
[ 2.078059] intel-pcie-slim-phy 18000000.pciephy: SSC has been enabled, count: 2!
[ 2.193000] intel-pcie 18400000.pcie: PCI host bridge to bus 0001:00
[ 2.199216] pci_bus 0001:00: root bus resource [bus 00-08]
[ 2.204753] pci_bus 0001:00: root bus resource [mem 0xb4000000-0xb6ffffff]
[ 2.211696] pci_bus 0001:00: root bus resource [io 0xb7800000-0xb780ffff]
[ 2.218641] pci_bus 0001:00: scanning bus
[ 2.222748] pci 0001:00:00.0: [1bef:0030] type 01 class 0x060400
[ 2.228880] pci 0001:00:00.0: supports D1 D2
[ 2.233138] pci 0001:00:00.0: PME# supported from D0 D1 D3hot D3cold
[ 2.239560] pci 0001:00:00.0: PME# disabled
[ 2.244051] pci_bus 0001:00: fixups for bus
[ 2.248082] pci 0001:00:00.0: scanning [bus 00-00] behind bridge, pass 0
[ 2.254845] pci 0001:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 2.262925] pci 0001:00:00.0: scanning [bus 00-00] behind bridge, pass 1
[ 2.269797] pci_bus 0001:01: scanning bus
[ 2.273801] pci 0001:01:00.0: [8086:09d0] type 00 class 0x0d8000
[ 2.279866] pci 0001:01:00.0: reg 0x10: [mem 0x00000000-0x01ffffff]
[ 2.286353] pci 0001:01:00.0: supports D1 D2
[ 2.290523] pci 0001:01:00.0: PME# supported from D0 D1 D3hot D3cold
[ 2.297005] pci 0001:01:00.0: PME# disabled
[ 2.301224] pci 0001:01:00.0: 4.000 Gb/s available PCIe bandwidth, limited by 5 GT/s x1 link at 0001:00:00.0 (capable of 15.752 Gb/s with 8 GT/s x2 link)
[ 2.315180] pci_bus 0001:01: fixups for bus
[ 2.319259] pci 0001:00:00.0: PCI bridge to [bus 01-08]
[ 2.324560] pci 0001:00:00.0: bridge window [io 0x0000-0x0fff]
[ 2.330713] pci 0001:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 2.337570] pci 0001:00:00.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 2.344858] pci_bus 0001:01: bus scan returning with max=01
[ 2.350504] pci_bus 0001:01: busn_res: [bus 01-08] end is updated to 01
[ 2.357188] pci_bus 0001:00: bus scan returning with max=01
[ 2.362883] pci 0000:00:00.0: fixup irq: got 281
[ 2.367515] pci 0000:00:00.0: assigning IRQ 281
[ 2.372138] pci 0000:01:00.0: fixup irq: got 281
[ 2.376803] pci 0000:01:00.0: assigning IRQ 281
[ 2.381438] pci 0001:00:00.0: fixup irq: got 282
[ 2.386092] pci 0001:00:00.0: assigning IRQ 282
[ 2.390711] pci 0001:01:00.0: fixup irq: got 282
[ 2.395379] pci 0001:01:00.0: assigning IRQ 282
[ 2.400016] pci 0001:00:00.0: BAR 8: assigned [mem 0xb4000000-0xb5ffffff]
[ 2.406844] pci 0001:00:00.0: BAR 9: assigned [mem 0xb6000000-0xb60fffff pref]
[ 2.414132] pci 0001:00:00.0: BAR 7: assigned [io 0xb7800000-0xb7800fff]
[ 2.420992] pci 0001:01:00.0: BAR 0: assigned [mem 0xb4000000-0xb5ffffff]
[ 2.427851] pci 0001:00:00.0: PCI bridge to [bus 01]
[ 2.432880] pci 0001:00:00.0: bridge window [io 0xb7800000-0xb7800fff]
[ 2.439738] pci 0001:00:00.0: bridge window [mem 0xb4000000-0xb5ffffff]
[ 2.446595] pci 0001:00:00.0: bridge window [mem 0xb6000000-0xb60fffff pref]
[ 2.453951] intel-pcie 18400000.pcie: Intel AXI PCIe Root Complex Port 1 Init Done
[ 2.567970] OF: PCI: host bridge ***@***.*** ranges:
[ 2.573058] OF: PCI: MEM 0xbc000000..0xbeffffff -> 0xbc000000
[ 2.579031] OF: PCI: IO 0xbf800000..0xbf80ffff -> 0xbf800000
[ 2.586052] intel-pcie-slim-phy 18a00000.pciephy: SSC has been enabled, count: 3!
[ 3.631969] random: crng init done
[ 3.699967] intel-pcie 18e00000.pcie: intel_pcie_wait_phy_link_up port 2 timeout
[ 3.707235] intel-pcie-slim-phy 18a00000.pciephy: SSC in use, count: 2!
[ 3.713957] intel-pcie: probe of 18e00000.pcie failed with error -145
[ 3.721738] [mips_tc_init] dma_zalloc_coherent dev->name=(null) sizeof(struct mips_tc_sg_mem)=1680 shared_phy_mem=27c0c000
[ 3.732658] [mips_tc_init] dma_zalloc_coherent shared_vir_uncached_mem=a7c0c000 shared_vir_cached_mem=87c0c000 shared_working_vir_mem=87c0c000
[ 3.745715] =MIPS TC Shared memory: a7c0c000 87c0c000 87c0c000 | Data: a7c20000
[ 3.752959] UMT initialize success on processor: 0 !
[ 3.757904] HW MCPY driver: Version: 1.1.0, Init Done!
[ 3.824403] serial8250_init
[ 3.827043] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.835528] 16600000.serial: ttyLTQ0 at MMIO 0x16600000 (irq = 213, base_baud = 0) is a lantiq,asc
[ 3.848257] console [ttyLTQ0] enabled
[ 3.848257] console [ttyLTQ0] enabled
[ 3.855410] bootconsole [early0] disabled
[ 3.855410] bootconsole [early0] disabled
[ 3.864160] sysrst_init: Trying to register System Reset Driver ...
[ 3.869181] sysrst_pre_init: Detect InterAptiv CPU ...
[ 3.874232] sysrst_init: Lantiq CPE GRX500 System driver version 1.0.0
[ 3.880606] sysrst_init: GRX500 System Reset initialized successfully!
[ 3.888103] nand: device found, Manufacturer ID: 0xc8, Chip ID: 0xd1
[ 3.893453] nand: ESMT NAND 128MiB 3,3V 8-bit
[ 3.897788] nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
[ 3.908317] Bad block table found at page 65472, version 0x01
[ 3.914822] Bad block table found at page 65408, version 0x01
[ 3.919507] 3 ofpart partitions found on MTD device 17c00000.nand
[ 3.925189] Creating 3 MTD partitions on "17c00000.nand":
[ 3.930578] 0x000000000000-0x0000001c0000 : "uboot_fix"
[ 3.937314] 0x0000001c0000-0x0000002c0000 : "calibration"
[ 3.942347] 0x0000002c0000-0x000008000000 : "ubi"
[ 3.949140] ubi0: default fastmap pool size: 50
[ 3.952244] ubi0: default fastmap WL pool size: 25
[ 3.956989] ubi0: attaching mtd2
[ 4.558988] ubi0: scanning is finished
[ 4.588857] ubi0: attached mtd2 (name "ubi", size 125 MiB)
[ 4.592914] ubi0: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[ 4.599754] ubi0: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
[ 4.606526] ubi0: VID header offset: 2048 (aligned 2048), data offset: 4096
[ 4.613468] ubi0: good PEBs: 998, bad PEBs: 4, corrupted PEBs: 0
[ 4.619484] ubi0: user volume: 4, internal volumes: 1, max. volumes count: 128
[ 4.626670] ubi0: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 867754253
[ 4.635692] ubi0: available PEBs: 0, total reserved PEBs: 998, PEBs reserved for bad PEB handling: 16
[ 4.644911] ubi0: background thread "ubi_bgt0d" started, PID 74
[ 4.656028] Lantiq SoC SPI controller rev 9 (TXFS 32, RXFS 32, DMA 1)
[ 4.661394] [ltq_ssc] { ifx_ssc_init : 3819 }[ifx_ssc_init] force ifx_ssc_cs_low to PORT 1
[ 4.669371] [ltq_ssc] { ifx_ssc_init : 3820 }[ifx_ssc_init] force ifx_ssc_cs_high to PORT 1
[ 4.677775] [ltq_ssc] { ifx_ssc_init : 3824 }ifx_ssc_init ifx_ssc_init_count 1
[ 4.685120] [ltq_ssc] { ifx_ssc_init : 3947 }port name ltq_ssc1
[ 4.691122] [ltq_ssc] { ifx_ssc_init : 4041 }Lantiq SoC SSC controller rev 9 (TXFS 32, RXFS 32, DMA 1)
[ 4.700794] tun: Universal TUN/TAP device driver, 1.6
[ 4.705391] tun: (C) 1999-2004 Max Krasnyansky ***@***.***>
[ 4.722491] phy-xrx500 1c003c00.phy-xrx500: requesting ltq_fw_PHY11G_IP_xRx5xx_A21.bin
[ 4.730400] phy-xrx500 1c003c00.phy-xrx500: booting GPHY0 firmware for GRX500
[ 4.736331] phy-xrx500 1c003c00.phy-xrx500: booting GPHY1 firmware for GRX500
[ 4.743464] phy-xrx500 1c003c00.phy-xrx500: booting GPHY2 firmware for GRX500
[ 4.750370] phy-xrx500 1c003c00.phy-xrx500: booting GPHY3 firmware for GRX500
[ 4.757673] phy-xrx500 1c003c00.phy-xrx500: booting GPHY4 firmware for GRX500
[ 4.872407] lro_sram_membase_res0 from DT: a2013000
[ 4.876166] ltq_toe_membase: e2000000 and lro_sram_membase_res0: e2013000
[ 4.883192] TOE Init Done !!
[ 4.885606] PPP generic driver version 2.4.2
[ 4.890125] PPP BSD Compression module registered
[ 4.894496] PPP Deflate Compression module registered
[ 4.899541] PPP MPPE Compression module registered
[ 4.904298] NET: Registered protocol family 24
[ 5.556822] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller
[ 5.560928] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 1
[ 5.568959] xhci-hcd xhci-hcd.2.auto: hcc params 0x0220f664 hci version 0x100 quirks 0x02010010
[ 5.577270] xhci-hcd xhci-hcd.2.auto: irq 285, io mem 0x1a300000
[ 5.584236] hub 1-0:1.0: USB hub found
[ 5.586920] hub 1-0:1.0: 1 port detected
[ 5.591376] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller
[ 5.596336] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 2
[ 5.604038] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 5.612916] hub 2-0:1.0: USB hub found
[ 5.615747] hub 2-0:1.0: 1 port detected
[ 5.620580] xhci-hcd xhci-hcd.3.auto: xHCI Host Controller
[ 5.625281] xhci-hcd xhci-hcd.3.auto: new USB bus registered, assigned bus number 3
[ 5.633275] xhci-hcd xhci-hcd.3.auto: hcc params 0x0220f664 hci version 0x100 quirks 0x02010010
[ 5.641629] xhci-hcd xhci-hcd.3.auto: irq 286, io mem 0x1a500000
[ 5.648363] hub 3-0:1.0: USB hub found
[ 5.651160] hub 3-0:1.0: 1 port detected
[ 5.655707] xhci-hcd xhci-hcd.3.auto: xHCI Host Controller
[ 5.660551] xhci-hcd xhci-hcd.3.auto: new USB bus registered, assigned bus number 4
[ 5.668344] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
[ 5.677122] hub 4-0:1.0: USB hub found
[ 5.680120] hub 4-0:1.0: 1 port detected
[ 5.684823] usbcore: registered new interface driver usblp
[ 5.689720] usbcore: registered new interface driver usb-storage
[ 5.695459] usbcore: registered new interface driver usbserial
[ 5.719961] i2c-lantiq 16a00000.i2c: timeout waiting for bus ready
[ 5.724815] i2c-lantiq 16a00000.i2c: ltq_i2c_xfer: bus is busy ffffff6f
[ 5.747969] i2c-lantiq 16a00000.i2c: timeout waiting for bus ready
[ 5.752715] i2c-lantiq 16a00000.i2c: ltq_i2c_xfer: bus is busy ffffff6f
[ 5.759573] ina2xx 0-0040: pm: ina219, railname: PWR_12V, Rshunt: 10000 uOhm
[ 5.768674] grx500wdt 12000000.watchdog: [grx500wdt_probe]:[444] cpu_clk=1000000000
[ 5.775139] grx500wdt 12000000.watchdog: [grx500wdt_probe]WDT reset is Bit31, RCU_IAP_WDT_RST_STAT=0x80000008
[ 5.784958] grx500wdt 12000000.watchdog: [grx500wdt_probe]WDT reset.
[ 5.791275] grx500wdt 12000000.watchdog: [grx500wdt_probe]:[553] grx500_wdt = 881e43c4
[ 5.799553] grx500wdt 12000000.watchdog: [grx500wdt_probe]:[553] grx500_wdt = 881fc3c4
[ 5.807081] grx500wdt 12000000.watchdog: H/w Watchdog Timer: (max 4) (nowayout= 0)
[ 5.816367] Device IRQ: 26 line: 101
[ 5.818612] GlobalControl97_Capabilities_Get
[ 5.822780] EIP202: PEs=1 rings=4 64-bit=No, fill level extension=No
[ 5.822780] CF size=4 RF size=3 DMA len = 10 Align=0 HDW=0 HostIfc=3
[ 5.835877] EIP96 options:
[ 5.835877] AES: Yes with CFB/OFB: Yes Fast: Yes
[ 5.835877] DES: Yes with CFB/OFB: Yes Fast: No
[ 5.835877] ARCFOUR level: 3
[ 5.835877] MD5: Yes SHA1: Yes Fast: Yes SHA256: Yes SHA512: Yes
[ 5.835877] (X)CBC-MAC: Yes Fast: Yes All key sizes: No GHASH Yes
[ 5.862402] EIP97 options: PEs=1, In Dbuf size=6 In Tbuf size=5, Out Dbuf size=6, Out Tbuf size=4,
[ 5.862402] Token Generator: No, Transform Record Cache: No
[ 5.876890] EIP206 options: PE type=0 InClassifier=0 OutClassifier=0 MAC chans=0
[ 5.876890] InDBuf=0kB InTBuf=0kB OutDBuf=0kB OutTBuf=0kB
[ 5.890101] Adapter_PECDev_Init: CDR fetch size 0x8, thresh 0x6, HDW=0, CFsize=4
[ 5.897348] Adapter_PECDev_Init: RDR fetch size 0x8, thresh 0x2, RFsize=3
[ 5.904393] Status of CDR/RDR interface 0
[ 5.907730] CDR Status: DMA err: false, err: false: ovf/under err: false
[ 5.907730] Threshold int: false, timeout int: false, FIFO count: 16
[ 5.920948] RDR Status: DMA err: false, err: false: ovf/under err: false
[ 5.920948] Buf ovf: false, Descriptor ovf false
[ 5.920948] Threshold int: false, timeout int: false, FIFO count: 8
[ 5.938799] LTQ Crypto Hardware Initialized ..
[ 5.946482] LTQ crypto driver version: 1.4.10
[ 5.950290] usbcore: registered new interface driver usbhid
[ 5.954974] usbhid: USB HID core driver
[ 5.959678] u32 classifier
[ 5.961480] Performance counters on
[ 5.965281] Actions configured
[ 5.968871] Netfilter messages via NETLINK v0.30.
[ 5.973660] nf_conntrack version 0.5.0 (4096 buckets, 16384 max)
[ 5.979873] ctnetlink v0.93: registering with nfnetlink.
[ 5.985029] ip_set: protocol 6
[ 5.987844] ipip: IPv4 and MPLS over IPv4 tunneling driver
[ 5.994149] ip_tables: (C) 2000-2006 Netfilter Core Team
[ 5.999753] NET: Registered protocol family 10
[ 6.004842] Registeration is a success The major device number is 249.
[ 6.010282] NET: Registered protocol family 17
[ 6.014737] Bridge firewalling registered
[ 6.018346] NET4: DECnet for Linux: V.2.5.68s (C) 1995-2003 Linux DECnet Project Team
[ 6.026790] DECnet: Routing cache hash table of 1024 buckets, 8Kbytes
[ 6.032636] NET: Registered protocol family 12
[ 6.037212] 8021q: 802.1Q VLAN Support v1.8
[ 6.042018] registered taskstats version 1
[ 6.048123] Key type encrypted registered
[ 6.053413] PMAC_EG_CFG_SET for GSW-L
[ 6.055819] PMAC_IG_CFG_SET for GSW-L
[ 6.059564] PMAC_EG_CFG_SET for GSW-R
[ 6.066347] PMAC_IG_CFG_SET for GSW-R
[ 6.068814]
[ 6.068814] GSW PMAC Init Done!!!
[ 6.073555] INFO : Property mac is not defined in DT
[ 6.078455] Property intel,extra-subif not exist for if eth0_0 0
[ 6.084917] dp_sub_proc_install ok
[ 6.088375] datapath_coc: enter dp_coc_cpufreq_init
[ 6.093462] datapath_coc: Register DP to CPUFREQ successfully.
[ 6.098614] [cbm] { dp_port_alloc : 2898 }flags 0x2
[ 6.103374] [cbm] { cbm_add_to_list : 261 }2
[ 6.107623] [cbm] { dp_port_alloc : 3046 }disabling q 16 port 6
[ 6.113523] [cbm] { dp_port_alloc : 3052 }first time LOOKUP prgrm
[ 6.119855] [cbm] { dp_port_alloc : 3057 }1024
[ 6.124091] no interface attached to this interface!
[ 6.128968] xrx500_of_iface: rx csum offload is enabled !
[ 6.134383] [cbm] { dp_enable : 3386 }ep=1 tmu_port=6 queue=16 sid=0
[ 6.140711] [cbm] { dequeue_dma_port_init : 4257 }6 0x0 2 1
[ 6.146258] [cbm] { dequeue_dma_port_init : 4257 }12 0x0 2 9
[ 6.151905] [cbm] { dp_enable : 3454 }enable queue 16
[ 6.156920] [cbm] { dp_enable : 3455 }flag 1 refcnt 1024
[ 6.163340] INFO : Property mac is not defined in DT
[ 6.167204] Property intel,extra-subif not exist for if eth0_1 0
[ 6.173163] [cbm] { dp_port_alloc : 2898 }flags 0x2
[ 6.178032] [cbm] { cbm_add_to_list : 261 }2
[ 6.182271] [cbm] { dp_port_alloc : 3046 }disabling q 17 port 7
[ 6.188173] [cbm] { dp_port_alloc : 3052 }first time LOOKUP prgrm
[ 6.194497] [cbm] { dp_port_alloc : 3057 }1024
[ 6.198818] xrx500_of_iface: rx csum offload is enabled !
[ 6.204086] trying to connect: eth0_1 to device: 0:02 with irq: 287
[ 6.310635] eth0_1: attached PHY [Lantiq XWAY VR9 GPHY 11G v1.4] (phy_addr=0:02, irq=287)
[ 6.328221] [cbm] { dp_enable : 3386 }ep=2 tmu_port=7 queue=17 sid=1
[ 6.333117] [cbm] { dequeue_dma_port_init : 4257 }7 0x0 2 2
[ 6.338681] [cbm] { dequeue_dma_port_init : 4257 }13 0x0 2 10
[ 6.344417] [cbm] { dp_enable : 3454 }enable queue 17
[ 6.349434] [cbm] { dp_enable : 3455 }flag 1 refcnt 1024
[ 6.355771] INFO : Property mac is not defined in DT
[ 6.359748] Property intel,extra-subif not exist for if eth0_2 0
[ 6.365680] [cbm] { dp_port_alloc : 2898 }flags 0x2
[ 6.370541] [cbm] { cbm_add_to_list : 261 }2
[ 6.374787] [cbm] { dp_port_alloc : 3046 }disabling q 18 port 8
[ 6.380689] [cbm] { dp_port_alloc : 3052 }first time LOOKUP prgrm
[ 6.387013] [cbm] { dp_port_alloc : 3057 }1024
[ 6.391325] xrx500_of_iface: rx csum offload is enabled !
[ 6.396614] trying to connect: eth0_2 to device: 0:03 with irq: 288
[ 6.502573] eth0_2: attached PHY [Lantiq XWAY VR9 GPHY 11G v1.4] (phy_addr=0:03, irq=288)
[ 6.520157] [cbm] { dp_enable : 3386 }ep=3 tmu_port=8 queue=18 sid=2
[ 6.525049] [cbm] { dequeue_dma_port_init : 4257 }8 0x0 2 3
[ 6.530612] [cbm] { dequeue_dma_port_init : 4257 }14 0x0 2 11
[ 6.536350] [cbm] { dp_enable : 3454 }enable queue 18
[ 6.541367] [cbm] { dp_enable : 3455 }flag 1 refcnt 1024
[ 6.547659] INFO : Property mac is not defined in DT
[ 6.551635] Property intel,extra-subif not exist for if eth0_3 0
[ 6.557609] [cbm] { dp_port_alloc : 2898 }flags 0x2
[ 6.562469] [cbm] { cbm_add_to_list : 261 }2
[ 6.566717] [cbm] { dp_port_alloc : 3046 }disabling q 19 port 9
[ 6.572655] [cbm] { dp_port_alloc : 3052 }first time LOOKUP prgrm
[ 6.578950] [cbm] { dp_port_alloc : 3057 }1024
[ 6.583254] xrx500_of_iface: rx csum offload is enabled !
[ 6.588544] trying to connect: eth0_3 to device: 0:04 with irq: 289
[ 6.695188] eth0_3: attached PHY [Lantiq XWAY VR9 GPHY 11G v1.4] (phy_addr=0:04, irq=289)
[ 6.712770] [cbm] { dp_enable : 3386 }ep=4 tmu_port=9 queue=19 sid=3
[ 6.717660] [cbm] { dequeue_dma_port_init : 4257 }9 0x0 2 4
[ 6.723223] [cbm] { dequeue_dma_port_init : 4257 }15 0x0 2 12
[ 6.728960] [cbm] { dp_enable : 3454 }enable queue 19
[ 6.733977] [cbm] { dp_enable : 3455 }flag 1 refcnt 1024
[ 6.740286] INFO : Property mac is not defined in DT
[ 6.744228] Property intel,extra-subif not exist for if eth0_4 0
[ 6.750218] [cbm] { dp_port_alloc : 2898 }flags 0x2
[ 6.755079] [cbm] { cbm_add_to_list : 261 }2
[ 6.759328] [cbm] { dp_port_alloc : 3046 }disabling q 20 port 10
[ 6.765318] [cbm] { dp_port_alloc : 3052 }first time LOOKUP prgrm
[ 6.771648] [cbm] { dp_port_alloc : 3057 }1024
[ 6.775962] xrx500_of_iface: rx csum offload is enabled !
[ 6.781235] trying to connect: eth0_4 to device: 0:05 with irq: 290
[ 6.889831] eth0_4: attached PHY [Lantiq XWAY VR9 GPHY 11G v1.4] (phy_addr=0:05, irq=290)
[ 6.907411] [cbm] { dp_enable : 3386 }ep=5 tmu_port=10 queue=20 sid=4
[ 6.912389] [cbm] { dequeue_dma_port_init : 4257 }10 0x0 2 5
[ 6.918039] [cbm] { dequeue_dma_port_init : 4257 }16 0x0 2 13
[ 6.923774] [cbm] { dp_enable : 3454 }enable queue 20
[ 6.928792] [cbm] { dp_enable : 3455 }flag 1 refcnt 1024
[ 6.935032] INFO : Property mac is not defined in DT
[ 6.939074] Property intel,extra-subif not exist for if eth1 0
[ 6.944861] [cbm] { dp_port_alloc : 2898 }flags 0x4
[ 6.949719] [cbm] { cbm_add_to_list : 261 }1
[ 6.953969] [cbm] { dp_port_alloc : 3046 }disabling q 28 port 19
[ 6.959959] [cbm] { dp_port_alloc : 3052 }first time LOOKUP prgrm
[ 6.966287] [cbm] { dp_port_alloc : 3057 }1024
[ 6.973466] xrx500_of_iface: rx csum offload is enabled !
[ 6.977447] trying to connect: eth1 to device: 1:01 with irq: 291
[ 7.086229] eth1: attached PHY [Lantiq XWAY VR9 GPHY 11G v1.4] (phy_addr=1:01, irq=291)
[ 7.103810] [cbm] { dp_enable : 3386 }ep=15 tmu_port=19 queue=28 sid=12
[ 7.108965] [cbm] { dequeue_dma_port_init : 4257 }19 0x0 1 15
[ 7.114734] [cbm] { dp_enable : 3454 }enable queue 28
[ 7.119730] [cbm] { dp_enable : 3455 }flag 1 refcnt 1024
[ 7.126279] Lantiq ethernet driver for XRX500 init.
[ 7.130238] searching for nvram
[ 7.133029] nvram size = 634880
[ 7.273617] found nvram at 0
[ 7.415892] clk: Not disabling unuse[ 7.442655] VFS: Mounted root (squashfs filesystem) readonly on device 31:6.
[ 7.452523] devtmpfs: mounted
[ 7.454818] Freeing unused kernel: 336k freed
[ 7.458455] This architecture does not have kernel memory protection.
[ 7.464802] Now calling with ramdisk_execute_command...
[ 7.470007] Now calling with execute_command....
[init] : starting devinit
[ 12.583855] xrx500-eth ***@***.*** eth0_1: Link is Up - 1Gbps/Full - flow control rx/tx
starting hotplug
start MSTP Daemon
done
[init] : no previous bootfails detected! (all ok)
[init] : starting Architecture code for lantiq
[ 19.064536] xrx500-eth ***@***.*** eth0_1: Link is Down
[ 19.095561] TMU HAL Init.
[ 19.096889] [cbm] { reserved_ports_highest : 4720 }26 26 25 41
[ 19.102570] Total node : 544 and size of each node: 3016
[ 19.107859] Total allocated size=1640704
[ 19.117550] Total node : 544 and size of each node: 3016
[ 19.128237] <hal_init> Number of CPU TMU Ports are:1
[ 19.133230] <hal_init> CPU TMU resources are Port:2 ,SB:19, Q:35
[ 19.137928] <hal_init> Number of MPE TMU Ports are:1
[ 19.142947] <hal_init> MPE TMU resources are Port:3 ,SB:20, Q:36
[ 19.149521] TMU HAL Create Proc entries
[ 19.152969] Done!!
[ 19.784266] [ltq_mpe_hal_drv] { mpe_hal_run_fw : 6182 }Starting cpu
[ 19.797437] [ltq_mpe_hal_drv] { mpe_hal_set_fw_connectivity : 3142 }<mpe_hal_set_fw_connectivity> CPU TMU resources for MPE are Port:3 ,SB:20, Q:36
[ 19.811300] [ltq_mpe_hal_drv] { mpe_hal_run_fw : 6197 }MPE HAL Run FW success .
[ 19.817522] MPE Proc Creation....!!!
[ 20.186014] [cbm] { dp_port_alloc : 2898 }flags 0x40
[ 20.189639] [cbm] { cbm_add_to_list : 261 }0
[ 20.193912] <tmu_hal_setup_dp_ingress_connectivity> TMU resources for Checksum is Port:20 ,SB:13, Q:29
[ 20.203258] For Loopdev device Q:30
[ 20.253257] PPA API --- init successfully
[ 20.257693] PPA DRV --- init successfully
[ 20.933360] Loading loop_net_dev driver ...... [ 20.936389] Succeeded!
[ 21.392832] [ltq_mpe_hal_drv] { mpe_hal_generic_hook : 521 }6Init Success
[ 21.398392] SWAC Init Success
[ 21.401646] Installed the ppa netfilter hooks
[ 21.406045] ppa_netif_add Success for ifname=lite0 (netif= (null))
[ 21.411799] ppa_init - init succeeded
[ 21.597603] Loading modules backported from Linux version v5.6-7111951b8d4973bda27ff663f2cf18b663d15b48
[ 21.605568] Backport generated by backports.git v3.10.104
[ 21.765292] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 21.778824] cfg80211: Loaded X.509 cert 'iwlwav: 008ae692e70e2f248e'
[ 21.790690] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 21.915570] PKCS#7 signature not signed with a trusted key
[ 21.919698] cfg80211: loaded regulatory.db is malformed or signature is missing/invalid
[ 22.218983] [4294897780] mtlk0(mtlk_cdev_init:361): Max nodes set to 1048575
[ 22.918120] xrx500-eth ***@***.*** eth0_1: Link is Up - 1Gbps/Full - flow control rx/tx
[ 23.040229] mtlk: unknown parameter 'ahb_off' ignored
[ 23.044816] [4294897987] mtlk0(__mtlk_print_endianess:10267): The system is Big endian (0xbeadfeed, 0xedfeadbe)
[ 23.053923] [4294897989] mtlk0(__mtlk_print_driver_version:10275): Driver version: ugw-8.5.2-cleanup.b6ae17b7580b47f1295239c8c41458c2ba8d30c6.With_local_changes.PcieG6.Release
[ 23.069748] pci 0000:00:00.0: enabling device (0000 -> 0003)
[ 23.075203] mtlk 0000:01:00.0: enabling device (0000 -> 0002)
[ 23.082032] [4294897996] mtlk0(_pci_mem_get:606): PCI Memory block 0: PA: 0x(REMOVED), VA: 0x(REMOVED), Len=0x2000000
[ 23.091496] [MTLKD] PCIE bus ChipID is:0x0900 address is:0xf8220060
[ 23.097837] [4294898000] mtlk0(_pci_start:730): CID-00: Detecting DUAL PCI mode...
[ 23.105305] [MTLKD] DUAL PCI mode not detected
[ 23.109726] [4294898003] mtlk0(_pci_start:734): A0 Chip doesnot support dual PCI
[ 23.117149] [MTLKD] PCIE bus ChipID is:0x0900 address is:0xf8220060
[ 23.123387] [MTLKD] PCIE bus ChipVersion:A0 ChipID is:0x0900
[ 23.129421] [4294898008] mtlk0(_mtlk_df_fw_request_firmware:40): Request Firmware ('cal_wlan0.bin') is starting
[ 23.139500] [4294898010] mtlk0(_eeprom_parse:547): EEPROM info: ver 0x0600, cal_file_type Operational, device_id 0x0900, header size 40, data size 1024,
[ 23.152827] [4294898014] mtlk0(mtlk_cis_data_parse:553): EEPROM Card ID: type 0x61, revision 0x45 (E) production 0x41
[ 23.163521] [4294898016] mtlkW(_mtlk_cis_area_parse_g6:388): CIS TPC G6 missing
[ 23.170677] [4294898018] mtlk0(_mtlk_cis_area_parse_g6:417): EEPROM: TX antennas number 4, mask 0x0F
[ 23.179790] [4294898020] mtlk0(mtlk_cis_data_parse:606): EEPROM supported bands: 2.4 - NO, 5.2 - NO, 6.0 - NO
[ 23.189689] [4294898023] mtlk0(_mtlk_pcie_efuse_access_check:950): eFuse read: addr 0, size 128, buf 0x(REMOVED)
[ 23.200029] [4294898026] mtlk0(_mtlk_hw_fill_card_info:4047): is_asic:1, is_emul:0, is_fpga:0, is_phy_dummy:0, is_secure_boot:0
[ 23.211290] [4294898028] mtlk0(_wave_hw_cfg_platform_type_set:8054): TestPlatformType: 0
[ 23.219370] [4294898030] mtlk0(_mtlk_df_fw_request_firmware:40): Request Firmware ('PSD.bin') is starting
[ 23.335005] [4294898059] mtlk0(mtlk_psdb_file_read_and_parse:2194): Loaded 'PSD.bin' of 96072 bytes
[ 23.342686] [4294898061] mtlk0(mtlk_psdb_file_read_and_parse:2217): PSDB Info: version 131 (0x00000083), revision 5d1cff64f22b
[ 23.353981] [4294898064] mtlk0(mtlk_psdb_file_read_and_parse:2229): Look for chip_id 0x0900, hw_type 0x61, hw_rev 0x45
[ 23.364980] [4294898067] mtlk0(psdb_parse_fields_array:1849): Parsed 65 items, found 12 fields and 24 tables
[ 23.374472] [4294898069] mtlk0(psdb_parse_fields_array:1985): PSDB_FIELD_BAND_SUPPORT_2G = 1
[ 23.382884] [4294898071] mtlk0(psdb_parse_fields_array:1988): PSDB_FIELD_BAND_SUPPORT_5G = 1
[ 23.391957] [4294898074] mtlk0(psdb_parse_fields_array:1935): Regd Table: nrows = 118, ncols = 5
[ 23.400394] [4294898076] mtlk0(_mtlk_psdb_parse_cca_th_table:1496): CCA Thresholds table: nrows = 5, ncols = 2
[ 23.410059] [4294898078] mtlk0(_mtlk_psdb_parse_cca_th_table:1508): CCA_TH[0]: 2G: -62, 5G: -62, 6G: -62
[ 23.419611] [4294898080] mtlk0(_mtlk_psdb_parse_cca_th_table:1508): CCA_TH[1]: 2G: -72, 5G: -72, 6G: -72
[ 23.429152] [4294898083] mtlk0(_mtlk_psdb_parse_cca_th_table:1508): CCA_TH[2]: 2G: 0, 5G: 0, 6G: 0
[ 23.438182] [4294898085] mtlk0(_mtlk_psdb_parse_cca_th_table:1508): CCA_TH[3]: 2G: -72, 5G: -72, 6G: -72
[ 23.447730] [4294898087] mtlk0(_mtlk_psdb_parse_cca_th_table:1508): CCA_TH[4]: 2G: -72, 5G: -72, 6G: -72
[ 23.459159] [4294898090] mtlk0(psdb_parse_fields_array:1948): psdb->cdb_cfg_table.cca_th_is_filled = 1
[ 23.467665] [4294898092] mtlk0(_mtlk_psdb_parse_ant_mask_per_chan_table:1721): Channel until 35 (including) mask is 0x05
[ 23.477941] [4294898095] mtlk0(_mtlk_psdb_parse_ant_mask_per_chan_table:1721): Channel until 255 (including) mask is 0x0A
[ 23.488890] [4294898098] mtlk0(_mtlk_psdb_parse_cdb_cfg_table:1463): CDB config[0] = 1 (CDB_CFG_2G)
[ 23.497915] [4294898100] mtlk0(_mtlk_psdb_parse_cdb_cfg_table:1463): CDB config[1] = 2 (CDB_CFG_5G)
[ 23.506949] [4294898102] mtlk0(psdb_parse_fields_array:2009): PSDB: TX/RX antennas number 4/4, mask 0x0F/0x0F
[ 23.516847] [4294898105] mtlk0(_mtlk_psdb_update_cdb_cfg_table:1648): [0] band 1, channels 1 ... 14
[ 23.525862] [4294898107] mtlk0(_mtlk_psdb_update_cdb_cfg_table:1651): [0] Antennas number 2, mask 05, sel_mask 11, factor 24
[ 23.537057] [4294898110] mtlk0(_mtlk_psdb_update_cdb_cfg_table:1648): [1] band 0, channels 36 ... 165
[ 23.546259] [4294898112] mtlk0(_mtlk_psdb_update_cdb_cfg_table:1651): [1] Antennas number 2, mask 0A, sel_mask 44, factor 24
[ 23.557460] [4294898115] mtlk0(psdb_parse_regd_table:994): PSD: band_support_2g = 1, band_support_5g =1, band_support_6g = 0, nrows = 118, ncols = 5
[ 23.570741] [4294898118] mtlk0(psdb_parse_regd_table:1014): [ 0] = regd 0x10, chan 1 (2412 MHz)
[ 23.579593] [4294898120] mtlk0(psdb_parse_regd_table:1016): chan_idx 1, bw 20, mode 1, pw 160
[ 23.588363] [4294898123] mtlk0(psdb_parse_regd_table:1014): [ 1] = regd 0x10, chan 2 (2417 MHz)
[ 23.597215] [4294898125] mtlk0(psdb_parse_regd_table:1016): chan_idx 2, bw 20, mode 1, pw 160
[ 23.605983] [4294898127] mtlk0(psdb_parse_regd_table:1014): [ 2] = regd 0x10, chan 3 (2422 MHz)
[ 23.614837] [4294898129] mtlk0(psdb_parse_regd_table:1016): chan_idx 3, bw 20, mode 1, pw 208
[ 23.623611] [4294898131] mtlk0(psdb_parse_regd_table:1014): [ 3] = regd 0x10, chan 4 (2427 MHz)
[ 23.632464] [4294898134] mtlk0(psdb_parse_regd_table:1016): chan_idx 4, bw 20, mode 1, pw 208
[ 23.641228] [4294898136] mtlk0(psdb_parse_regd_table:1014): [ 4] = regd 0x10, chan 5 (2432 MHz)
[ 23.650081] [4294898138] mtlk0(psdb_parse_regd_table:1016): chan_idx 5, bw 20, mode 1, pw 208
[ 23.658849] [4294898140] mtlk0(psdb_parse_regd_table:1014): [ 5] = regd 0x10, chan 6 (2437 MHz)
[ 23.667703] [4294898142] mtlk0(psdb_parse_regd_table:1016): chan_idx 6, bw 20, mode 1, pw 208
[ 23.676471] [4294898145] mtlk0(psdb_parse_regd_table:1014): [ 6] = regd 0x10, chan 7 (2442 MHz)
[ 23.685325] [4294898147] mtlk0(psdb_parse_regd_table:1016): chan_idx 7, bw 20, mode 1, pw 208
[ 23.694093] [4294898149] mtlk0(psdb_parse_regd_table:1014): [ 7] = regd 0x10, chan 8 (2447 MHz)
[ 23.702947] [4294898151] mtlk0(psdb_parse_regd_table:1016): chan_idx 8, bw 20, mode 1, pw 208
[ 23.711715] [4294898153] mtlk0(psdb_parse_regd_table:1014): [ 8] = regd 0x10, chan 9 (2452 MHz)
[ 23.720569] [4294898156] mtlk0(psdb_parse_regd_table:1016): chan_idx 9, bw 20, mode 1, pw 208
[ 23.729337] [4294898158] mtlk0(psdb_parse_regd_table:1014): [ 9] = regd 0x10, chan 10 (2457 MHz)
[ 23.738191] [4294898160] mtlk0(psdb_parse_regd_table:1016): chan_idx 10, bw 20, mode 1, pw 172
[ 23.746959] [4294898162] mtlk0(psdb_parse_regd_table:1014): [10] = regd 0x10, chan 11 (2462 MHz)
[ 23.755813] [4294898164] mtlk0(psdb_parse_regd_table:1016): chan_idx 11, bw 20, mode 1, pw 172
[ 23.764650] [4294898167] mtlk0(psdb_parse_regd_table:1014): [11] = regd 0x10, chan 3 (2422 MHz)
[ 23.773441] [4294898169] mtlk0(psdb_parse_regd_table:1016): chan_idx 3, bw 40, mode 1, pw 142
[ 23.782204] [4294898171] mtlk0(psdb_parse_regd_table:1014): [12] = regd 0x10, chan 4 (2427 MHz)
[ 23.791058] [4294898173] mtlk0(psdb_parse_regd_table:1016): chan_idx 4, bw 40, mode 1, pw 142
[ 23.799825] [4294898175] mtlk0(psdb_parse_regd_table:1014): [13] = regd 0x10, chan 5 (2432 MHz)
[ 23.808680] [4294898178] mtlk0(psdb_parse_regd_table:1016): chan_idx 5, bw 40, mode 1, pw 161
[ 23.817447] [4294898180] mtlk0(psdb_parse_regd_table:1014): [14] = regd 0x10, chan 6 (2437 MHz)
[ 23.826302] [4294898182] mtlk0(psdb_parse_regd_table:1016): chan_idx 6, bw 40, mode 1, pw 161
[ 23.835069] [4294898184] mtlk0(psdb_parse_regd_table:1014): [15] = regd 0x10, chan 7 (2442 MHz)
[ 23.843924] [4294898186] mtlk0(psdb_parse_regd_table:1016): chan_idx 7, bw 40, mode 1, pw 161
[ 23.852690] [4294898189] mtlk0(psdb_parse_regd_table:1014): [16] = regd 0x10, chan 8 (2447 MHz)
[ 23.861546] [4294898191] mtlk0(psdb_parse_regd_table:1016): chan_idx 8, bw 40, mode 1, pw 164
[ 23.870314] [4294898193] mtlk0(psdb_parse_regd_table:1014): [17] = regd 0x10, chan 9 (2452 MHz)
[ 23.879168] [4294898195] mtlk0(psdb_parse_regd_table:1016): chan_idx 9, bw 40, mode 1, pw 164
[ 23.887949] [4294898198] mtlk0(psdb_parse_regd_table:1014): [18] = regd 0x30, chan 1 (2412 MHz)
[ 23.896796] [4294898200] mtlk0(psdb_parse_regd_table:1016): chan_idx 1, bw 20, mode 1, pw 112
[ 23.905562] [4294898202] mtlk0(psdb_parse_regd_table:1014): [19] = regd 0x30, chan 2 (2417 MHz)
[ 23.914416] [4294898204] mtlk0(psdb_parse_regd_table:1016): chan_idx 2, bw 20, mode 1, pw 112
[ 23.923180] [4294898206] mtlk0(psdb_parse_regd_table:1014): [20] = regd 0x30, chan 3 (2422 MHz)
[ 23.932034] [4294898209] mtlk0(psdb_parse_regd_table:1016): chan_idx 3, bw 20, mode 1, pw 112
[ 23.940802] [4294898211] mtlk0(psdb_parse_regd_table:1014): [21] = regd 0x30, chan 4 (2427 MHz)
[ 23.949656] [4294898213] mtlk0(psdb_parse_regd_table:1016): chan_idx 4, bw 20, mode 1, pw 112
[ 23.958424] [4294898215] mtlk0(psdb_parse_regd_table:1014): [22] = regd 0x30, chan 5 (2432 MHz)
[ 23.967278] [4294898217] mtlk0(psdb_parse_regd_table:1016): chan_idx 5, bw 20, mode 1, pw 112
[ 23.976046] [4294898220] mtlk0(psdb_parse_regd_table:1014): [23] = regd 0x30, chan 6 (2437 MHz)
[ 23.984900] [4294898222] mtlk0(psdb_parse_regd_table:1016): chan_idx 6, bw 20, mode 1, pw 112
[ 23.993668] [4294898224] mtlk0(psdb_parse_regd_table:1014): [24] = regd 0x30, chan 7 (2442 MHz)
[ 24.002522] [4294898226] mtlk0(psdb_parse_regd_table:1016): chan_idx 7, bw 20, mode 1, pw 112
[ 24.011290] [4294898228] mtlk0(psdb_parse_regd_table:1014): [25] = regd 0x30, chan 8 (2447 MHz)
[ 24.020144] [4294898231] mtlk0(psdb_parse_regd_table:1016): chan_idx 8, bw 20, mode 1, pw 112
[ 24.028917] [4294898233] mtlk0(psdb_parse_regd_table:1014): [26] = regd 0x30, chan 9 (2452 MHz)
[ 24.037768] [4294898235] mtlk0(psdb_parse_regd_table:1016): chan_idx 9, bw 20, mode 1, pw 112
[ 24.046534] [4294898237] mtlk0(psdb_parse_regd_table:1014): [27] = regd 0x30, chan 10 (2457 MHz)
[ 24.055389] [4294898239] mtlk0(psdb_parse_regd_table:1016): chan_idx 10, bw 20, mode 1, pw 112
[ 24.064157] [4294898242] mtlk0(psdb_parse_regd_table:1014): [28] = regd 0x30, chan 11 (2462 MHz)
[ 24.073010] [4294898244] mtlk0(psdb_parse_regd_table:1016): chan_idx 11, bw 20, mode 1, pw 112
[ 24.081778] [4294898246] mtlk0(psdb_parse_regd_table:1014): [29] = regd 0x30, chan 12 (2467 MHz)
[ 24.090666] [4294898248] mtlk0(psdb_parse_regd_table:1016): chan_idx 12, bw 20, mode 1, pw 112
[ 24.099406] [4294898250] mtlk0(psdb_parse_regd_table:1014): [30] = regd 0x30, chan 13 (2472 MHz)
[ 24.108255] [4294898253] mtlk0(psdb_parse_regd_table:1016): chan_idx 13, bw 20, mode 1, pw 113
[ 24.117023] [4294898255] mtlk0(psdb_parse_regd_table:1014): [31] = regd 0x30, chan 3 (2422 MHz)
[ 24.125877] [4294898257] mtlk0(psdb_parse_regd_table:1016): chan_idx 3, bw 40, mode 1, pw 114
[ 24.134645] [4294898259] mtlk0(psdb_parse_regd_table:1014): [32] = regd 0x30, chan 4 (2427 MHz)
[ 24.143499] [4294898261] mtlk0(psdb_parse_regd_table:1016): chan_idx 4, bw 40, mode 1, pw 114
[ 24.152662] [4294898264] mtlk0(psdb_parse_regd_table:1014): [33] = regd 0x30, chan 5 (2432 MHz)
[ 24.161129] [4294898266] mtlk0(psdb_parse_regd_table:1016): chan_idx 5, bw 40, mode 1, pw 115
[ 24.169890] [4294898268] mtlk0(psdb_parse_regd_table:1014): [34] = regd 0x30, chan 6 (2437 MHz)
[ 24.178743] [4294898270] mtlk0(psdb_parse_regd_table:1016): chan_idx 6, bw 40, mode 1, pw 115
[ 24.187511] [4294898272] mtlk0(psdb_parse_regd_table:1014): [35] = regd 0x30, chan 7 (2442 MHz)
[ 24.196365] [4294898275] mtlk0(psdb_parse_regd_table:1016): chan_idx 7, bw 40, mode 1, pw 115
[ 24.205133] [4294898277] mtlk0(psdb_parse_regd_table:1014): [36] = regd 0x30, chan 8 (2447 MHz)
[ 24.213987] [4294898279] mtlk0(psdb_parse_regd_table:1016): chan_idx 8, bw 40, mode 1, pw 115
[ 24.222755] [4294898281] mtlk0(psdb_parse_regd_table:1014): [37] = regd 0x30, chan 9 (2452 MHz)
[ 24.231616] [4294898283] mtlk0(psdb_parse_regd_table:1016): chan_idx 9, bw 40, mode 1, pw 115
[ 24.240377] [4294898286] mtlk0(psdb_parse_regd_table:1014): [38] = regd 0x30, chan 10 (2457 MHz)
[ 24.249231] [4294898288] mtlk0(psdb_parse_regd_table:1016): chan_idx 10, bw 40, mode 1, pw 115
[ 24.257999] [4294898290] mtlk0(psdb_parse_regd_table:1014): [39] = regd 0x30, chan 11 (2462 MHz)
[ 24.266853] [4294898292] mtlk0(psdb_parse_regd_table:1016): chan_idx 11, bw 40, mode 1, pw 115
[ 24.275621] [4294898294] mtlk0(psdb_parse_regd_table:1014): [40] = regd 0x10, chan 36 (5180 MHz)
[ 24.284475] [4294898297] mtlk0(psdb_parse_regd_table:1016): chan_idx 16, bw 20, mode 1, pw 182
[ 24.293249] [4294898299] mtlk0(psdb_parse_regd_table:1014): [41] = regd 0x10, chan 40 (5200 MHz)
[ 24.302098] [4294898301] mtlk0(psdb_parse_regd_table:1016): chan_idx 18, bw 20, mode 1, pw 211
[ 24.310866] [4294898303] mtlk0(psdb_parse_regd_table:1014): [42] = regd 0x10, chan 44 (5220 MHz)
[ 24.319720] [4294898305] mtlk0(psdb_parse_regd_table:1016): chan_idx 20, bw 20, mode 1, pw 211
[ 24.328487] [4294898308] mtlk0(psdb_parse_regd_table:1014): [43] = regd 0x10, chan 48 (5240 MHz)
[ 24.337342] [4294898310] mtlk0(psdb_parse_regd_table:1016): chan_idx 22, bw 20, mode 1, pw 212
[ 24.346110] [4294898312] mtlk0(psdb_parse_regd_table:1014): [44] = regd 0x10, chan 52 (5260 MHz)
[ 24.354964] [4294898314] mtlk0(psdb_parse_regd_table:1016): chan_idx 23, bw 20, mode 1, pw 163
[ 24.363732] [4294898316] mtlk0(psdb_parse_regd_table:1014): [45] = regd 0x10, chan 56 (5280 MHz)
[ 24.372586] [4294898319] mtlk0(psdb_parse_regd_table:1016): chan_idx 24, bw 20, mode 1, pw 163
[ 24.381354] [4294898321] mtlk0(psdb_parse_regd_table:1014): [46] = regd 0x10, chan 60 (5300 MHz)
[ 24.390208] [4294898323] mtlk0(psdb_parse_regd_table:1016): chan_idx 25, bw 20, mode 1, pw 163
[ 24.398976] [4294898325] mtlk0(psdb_parse_regd_table:1014): [47] = regd 0x10, chan 64 (5320 MHz)
[ 24.407830] [4294898327] mtlk0(psdb_parse_regd_table:1016): chan_idx 26, bw 20, mode 1, pw 162
[ 24.416598] [4294898330] mtlk0(psdb_parse_regd_table:1014): [48] = regd 0x10, chan 100 (5500 MHz)
[ 24.425457] [4294898332] mtlk0(psdb_parse_regd_table:1016): chan_idx 27, bw 20, mode 1, pw 162
[ 24.434221] [4294898334] mtlk0(psdb_parse_regd_table:1014): [49] = regd 0x10, chan 104 (5520 MHz)
[ 24.443074] [4294898336] mtlk0(psdb_parse_regd_table:1016): chan_idx 28, bw 20, mode 1, pw 162
[ 24.451842] [4294898338] mtlk0(psdb_parse_regd_table:1014): [50] = regd 0x10, chan 108 (5540 MHz)
[ 24.460696] [4294898341] mtlk0(psdb_parse_regd_table:1016): chan_idx 29, bw 20, mode 1, pw 162
[ 24.469465] [4294898343] mtlk0(psdb_parse_regd_table:1014): [51] = regd 0x10, chan 112 (5560 MHz)
[ 24.480001] [4294898346] mtlk0(psdb_parse_regd_table:1016): chan_idx 30, bw 20, mode 1, pw 162
[ 24.487335] [4294898347] mtlk0(psdb_parse_regd_table:1014): [52] = regd 0x10, chan 116 (5580 MHz)
[ 24.496181] [4294898350] mtlk0(psdb_parse_regd_table:1016): chan_idx 31, bw 20, mode 1, pw 164
[ 24.504949] [4294898352] mtlk0(psdb_parse_regd_table:1014): [53] = regd 0x10, chan 120 (5600 MHz)
[ 24.513802] [4294898354] mtlk0(psdb_parse_regd_table:1016): chan_idx 32, bw 20, mode 1, pw 164
[ 24.522570] [4294898356] mtlk0(psdb_parse_regd_table:1014): [54] = regd 0x10, chan 124 (5620 MHz)
[ 24.531424] [4294898358] mtlk0(psdb_parse_regd_table:1016): chan_idx 33, bw 20, mode 1, pw 164
[ 24.540192] [4294898361] mtlk0(psdb_parse_regd_table:1014): [55] = regd 0x10, chan 128 (5640 MHz)
[ 24.549068] [4294898363] mtlk0(psdb_parse_regd_table:1016): chan_idx 34, bw 20, mode 1, pw 164
[ 24.557843] [4294898365] mtlk0(psdb_parse_regd_table:1014): [56] = regd 0x10, chan 132 (5660 MHz)
[ 24.566671] [4294898367] mtlk0(psdb_parse_regd_table:1016): chan_idx 35, bw 20, mode 1, pw 164
[ 24.575437] [4294898369] mtlk0(psdb_parse_regd_table:1014): [57] = regd 0x10, chan 136 (5680 MHz)
[ 24.584291] [4294898372] mtlk0(psdb_parse_regd_table:1016): chan_idx 36, bw 20, mode 1, pw 164
[ 24.593058] [4294898374] mtlk0(psdb_parse_regd_table:1014): [58] = regd 0x10, chan 140 (5700 MHz)
[ 24.601912] [4294898376] mtlk0(psdb_parse_regd_table:1016): chan_idx 37, bw 20, mode 1, pw 165
[ 24.610681] [4294898378] mtlk0(psdb_parse_regd_table:1014): [59] = regd 0x10, chan 149 (5745 MHz)
[ 24.619535] [4294898380] mtlk0(psdb_parse_regd_table:1016): chan_idx 39, bw 20, mode 1, pw 211
[ 24.628302] [4294898383] mtlk0(psdb_parse_regd_table:1014): [60] = regd 0x10, chan 153 (5765 MHz)
[ 24.637157] [4294898385] mtlk0(psdb_parse_regd_table:1016): chan_idx 40, bw 20, mode 1, pw 211
[ 24.645925] [4294898387] mtlk0(psdb_parse_regd_table:1014): [61] = regd 0x10, chan 157 (5785 MHz)
[ 24.654779] [4294898389] mtlk0(psdb_parse_regd_table:1016): chan_idx 41, bw 20, mode 1, pw 211
[ 24.663561] [4294898391] mtlk0(psdb_parse_regd_table:1014): [62] = regd 0x10, chan 161 (5805 MHz)
[ 24.672404] [4294898394] mtlk0(psdb_parse_regd_table:1016): chan_idx 42, bw 20, mode 1, pw 209
[ 24.681175] [4294898396] mtlk0(psdb_parse_regd_table:1014): [63] = regd 0x10, chan 165 (5825 MHz)
[ 24.690047] [4294898398] mtlk0(psdb_parse_regd_table:1016): chan_idx 43, bw 20, mode 1, pw 209
[ 24.698794] [4294898400] mtlk0(psdb_parse_regd_table:1014): [64] = regd 0x10, chan 38 (5190 MHz)
[ 24.707645] [4294898402] mtlk0(psdb_parse_regd_table:1016): chan_idx 17, bw 40, mode 1, pw 172
[ 24.716413] [4294898405] mtlk0(psdb_parse_regd_table:1014): [65] = regd 0x10, chan 46 (5230 MHz)
[ 24.725267] [4294898407] mtlk0(psdb_parse_regd_table:1016): chan_idx 21, bw 40, mode 1, pw 212
[ 24.734035] [4294898409] mtlk0(psdb_parse_regd_table:1014): [66] = regd 0x10, chan 54 (5270 MHz)
[ 24.742889] [4294898411] mtlk0(psdb_parse_regd_table:1016): chan_idx 48, bw 40, mode 1, pw 166
[ 24.751657] [4294898413] mtlk0(psdb_parse_regd_table:1014): [67] = regd 0x10, chan 62 (5310 MHz)
[ 24.760511] [4294898416] mtlk0(psdb_parse_regd_table:1016): chan_idx 49, bw 40, mode 1, pw 166
[ 24.769294] [4294898418] mtlk0(psdb_parse_regd_table:1014): [68] = regd 0x10, chan 102 (5510 MHz)
[ 24.778136] [4294898420] mtlk0(psdb_parse_regd_table:1016): chan_idx 50, bw 40, mode 1, pw 164
[ 24.786901] [4294898422] mtlk0(psdb_parse_regd_table:1014): [69] = regd 0x10, chan 110 (5550 MHz)
[ 24.795755] [4294898424] mtlk0(psdb_parse_regd_table:1016): chan_idx 51, bw 40, mode 1, pw 164
[ 24.804523] [4294898427] mtlk0(psdb_parse_regd_table:1014): [70] = regd 0x10, chan 118 (5590 MHz)
[ 24.813383] [4294898429] mtlk0(psdb_parse_regd_table:1016): chan_idx 52, bw 40, mode 1, pw 164
[ 24.822170] [4294898431] mtlk0(psdb_parse_regd_table:1014): [71] = regd 0x10, chan 126 (5630 MHz)
[ 24.831002] [4294898433] mtlk0(psdb_parse_regd_table:1016): chan_idx 53, bw 40, mode 1, pw 164
[ 24.839768] [4294898435] mtlk0(psdb_parse_regd_table:1014): [72] = regd 0x10, chan 134 (5670 MHz)
[ 24.848622] [4294898438] mtlk0(psdb_parse_regd_table:1016): chan_idx 54, bw 40, mode 1, pw 164
[ 24.857390] [4294898440] mtlk0(psdb_parse_regd_table:1014): [73] = regd 0x10, chan 151 (5755 MHz)
[ 24.866244] [4294898442] mtlk0(psdb_parse_regd_table:1016): chan_idx 56, bw 40, mode 1, pw 204
[ 24.875011] [4294898444] mtlk0(psdb_parse_regd_table:1014): [74] = regd 0x10, chan 159 (5795 MHz)
[ 24.883880] [4294898446] mtlk0(psdb_parse_regd_table:1016): chan_idx 57, bw 40, mode 1, pw 211
[ 24.892637] [4294898449] mtlk0(psdb_parse_regd_table:1014): [75] = regd 0x10, chan 42 (5210 MHz)
[ 24.901487] [4294898451] mtlk0(psdb_parse_regd_table:1016): chan_idx 19, bw 80, mode 1, pw 175
[ 24.910256] [4294898453] mtlk0(psdb_parse_regd_table:1014): [76] = regd 0x10, chan 58 (5290 MHz)
[ 24.919110] [4294898455] mtlk0(psdb_parse_regd_table:1016): chan_idx 58, bw 80, mode 1, pw 165
[ 24.927878] [4294898457] mtlk0(psdb_parse_regd_table:1014): [77] = regd 0x10, chan 106 (5530 MHz)
[ 24.936732] [4294898460] mtlk0(psdb_parse_regd_table:1016): chan_idx 59, bw 80, mode 1, pw 162
[ 24.945506] [4294898462] mtlk0(psdb_parse_regd_table:1014): [78] = regd 0x10, chan 122 (5610 MHz)
[ 24.954378] [4294898464] mtlk0(psdb_parse_regd_table:1016): chan_idx 60, bw 80, mode 1, pw 164
[ 24.963125] [4294898466] mtlk0(psdb_parse_regd_table:1014): [79] = regd 0x10, chan 138 (5690 MHz)
[ 24.971977] [4294898469] mtlk0(psdb_parse_regd_table:1016): chan_idx 61, bw 80, mode 1, pw 164
[ 24.980744] [4294898471] mtlk0(psdb_parse_regd_table:1014): [80] = regd 0x10, chan 155 (5775 MHz)
[ 24.989613] [4294898473] mtlk0(psdb_parse_regd_table:1016): chan_idx 62, bw 80, mode 1, pw 187
[ 24.998369] [4294898475] mtlk0(psdb_parse_regd_table:1014): [81] = regd 0x10, chan 50 (5250 MHz)
[ 25.007220] [4294898477] mtlk0(psdb_parse_regd_table:1016): chan_idx 63, bw 160, mode 1, pw 166
[ 25.016076] [4294898480] mtlk0(psdb_parse_regd_table:1014): [82] = regd 0x10, chan 114 (5570 MHz)
[ 25.024929] [4294898482] mtlk0(psdb_parse_regd_table:1016): chan_idx 64, bw 160, mode 1, pw 164
[ 25.033784] [4294898484] mtlk0(psdb_parse_regd_table:1014): [83] = regd 0x30, chan 36 (5180 MHz)
[ 25.042638] [4294898486] mtlk0(psdb_parse_regd_table:1016): chan_idx
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hi,
i saw this repository in my perusal of sources that support the GRX350/550 processors.
does this kernel work for the dual core intel interaptiv mips devices?
if so, i'm very intrigued and want to determine if i can merge the changes from the GPL into 4.14 for my own build.
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