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Fix default wire mapping and QPU program compilation and add support for parallel execution #124
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MarquessV
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PennyLaneAI:master
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MarquessV:123-fix-default-qc-wire-map
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231ed94
let the qc define the wire map
MarquessV c5ac75a
use pyquil measure_all
MarquessV 2e80946
use protoquil
MarquessV a560017
use protoquil flag for compiling on QPU devices only
MarquessV 387104a
measure only used qubit indices into their expected index in the readout
MarquessV 3552699
1 measure per qubit used
MarquessV eef2d6d
fix ro size
MarquessV 9b78119
codecheck and black fmt
MarquessV 7cf1ad9
changelog entry
MarquessV 63f33dc
support parameter broadcasting
MarquessV 4bc4fa1
support parallel execution of batched circuits
MarquessV 1e75d92
black formatting
MarquessV 4a8e002
Merge branch 'master' into 123-fix-default-qc-wire-map
MarquessV e844ccf
test fixes
MarquessV 74c16b4
docstring
MarquessV 06fbbe1
docstring
MarquessV 3074be5
update CHANGELOG
MarquessV c933173
[EMPTY] trigger CI
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To make sure I understand, does this mean that the user can pass any wires and they'll be mapped to the device wires, or that the user must use the appropriate wires for the device?