1.III ¦Support for a subset of MIPS Instructions

[PandaEden]

'Necessary to show basic architecture functionality'

Related

1.III.I ¦ C: Support for pseudo-Instructions - converted to assembly instructions at runtime.
1.III.I.I ¦ *W: highlighting of original pseudo code in Code window next to converted instructions.

1.III.II ¦ *W: Keyboard Input/Terminal Interaction. (Print to terminal)
1.III.II.I ¦ *W: Support for Full MIPS Instruction Set, including system calls necessary to draw graphics. (Display bitmap graphics)

Instruction Format Reference
Pseudo-Instructions Reference
OpCodes & Addressing Modes
Control Signals
ALU_Op

ALUOp[1:0]=00: always do addition (for addi, lw, sw, etc.)
ALUOp[1:0]=01: always do subtraction (for beq, bne, etc.)
ALUOp[1:0]=1x: operation determined by the function field of IR func[5:0] (for all R-type instructions)

ALUCtrl[2:0]=010: add
ALUCtrl[2:0]=110: sub
ALUCtrl[2:0]=111: slt

Instructions 32 Bit (4 Bytes)

(ps) < means pseudo instruction

R-Type : Register

R-Type	OpCode	RS	RT	RD	Shift	Function
Bits	6	5	5	5	5	6
Range	[31:26]	[25:21]	[20:16]	[15:11]	[10:6]	[5:0]

Unless specified, Shift Amount is always 0

• add $rd, $rs, $rt Opcode:[000000] Func:[100000]
• sub $rd, $rs, $rt Opcode:[000000] Func:[100010]
• halt # (ps) li $v0, 10& systemcall Opcode:[000000] Func:[011000]

---

I-Type : Immediate

I-Type	OpCode	RS	RT	Immediate
Bits	6	5	5	16
Range	[31:26]	[25:21]	[20:16]	[15:0]

• addi $rt, $rs, Imm Opcode:[001000]
• lw $rt, label # (ps) lw $rt, off($rd)
• sw $rt, label # (ps) st $rt, off($rd)
• lw $rt, off($rd) Opcode:[100011] - load prefix [100###]
• sw $rt, off($rd) Opcode:[101011] - store prefix [101###]
• la $rt, Imm # (ps) same as li
• li $rt, Imm # (ps) of lui $rt, Imm& ori $rt, Imm

---

Branches

• beq $rs, $rt, Imm Opcode: [000100]
• bne $rs, $rt, Imm Opcode: [000101]
• blez $rs, Imm # $rt = 0 Opcode: [000110]
• bgtz $rs, Imm # $rt = 0 Opcode: [000111]

---

J-Type : Jump

R-Type	OpCode	Address
Bits	6	26
Range	[31:26]	[25:0]

• J address Opcode:[000010]
• Jal address # Overwrites $ra Opcode:[000011]

---

Additional References:
https://www.d.umn.edu/~gshute/mips/itype.xhtml - Branch Instr $rt value
https://stackoverflow.com/a/48315588 - li la Instr difference
https://chortle.ccsu.edu/AssemblyTutorial/Chapter-26/ass26_4.html (Jal PC+8)
https://www.math.unipd.it/~sperduti/ARCHITETTURE-1/mips32.pdf

Floating Point: Double

• l.d $ft, label
• l.d $ft, off($fs) # ldc1 Opcode:[110001]
• s.d $ft, label
• s.d $ft, off($fs) # sdc1 Opcode:[111001]
  Opcode:[001011] Rs:[001011]
• add.d $fd, $fs, $ft Func:[000000]
• sub.d $fd, $fs, $ft Func:[000001]
• mul.d $fd, $fs, $ft Func:[000010]
• div.d $fd, $fs, $ft Func:[000011]

Directives

• .data
• .word <int>
• .word <int>:<int>
• .word <int>,<int>,<int>,....<int
• .text
• .code
• .double <df>
• .double <df>, <df>, <df>,...<df>

Possible Instructions to Add in the future:
R_type:
[ ] Jr $rs Opcode:[000000] Func:[001000]
[ ] slt $rd, $rs, $rt Opcode:[000000] Func:[101010]
[ ] nop # (ps) sll $zero, $zero, 0 Opcode:[000000] Func:[000000]
[ ] Jalr $rd, $rs Opcode:[000000] Func:[001001]

I_type:
[ ] ori $rt, $rs, Imm Opcode:[001101]
[ ] xori $rt, $rs, Imm Opcode:[001110]
[ ] slti $rt, $rs, Imm Opcode:[001010]

[ ] bgt # (ps)
[ ] blt # (ps)
[ ] bge # (ps)
[ ] ble # (ps)
[ ] beqz # (ps) $rt = 1

Extra R_Type:
[ ] mfhi $rd
[ ] mflo $rs
[ ] mult $rs, $rt
[ ] div $rs, $rt
[ ] and $rd, $rs, $rt
[ ] or $rd, $rs, $rt
[ ] xor $rd, $rs, $rt
[ ] nor $rd, $rs, $rt
[ ] not $rt, $rs # (ps) nor $rt, $rs, $zero
[ ] move $rt, $rs # (ps) or $rt, $rs, $zero

[PandaEden]

Win DLX instructions:
https://www.computing.dcu.ie/~ray/teaching/CA226/mips/winmips64.html

Instructions are based on 64Bit registers DoubleWords, and double precision floating point.

Because of this, you try to only use Even numbered registers only.

Does not support system calls. Instead it uses halt to terminate.
and Memory-Mapped IO

[PandaEden]

lw/sw using a label is a pseudo instruction. until 1.III.I Pseudo instruction conversion is implemented, I_Type ins , Immediate value, will be used to hold the address.