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My risc-v device only support --march=rv64imafdc.
So the compilation of .S file in "/source/device/cpu/op/conv/risc-v/lp64dv" will fail because my device cannot support vector operation.
How to compile with only rv64imafdc support ?
The text was updated successfully, but these errors were encountered:
I'm facing the same problem, but seems like Tengine can only support rv64gcvxthead becase v(vector) module seem important to the riscv support on this project.
My risc-v device only support --march=rv64imafdc.
So the compilation of .S file in "/source/device/cpu/op/conv/risc-v/lp64dv" will fail because my device cannot support vector operation.
How to compile with only rv64imafdc support ?
The text was updated successfully, but these errors were encountered: