RDIR is a dataflow intermediate representation for optimizing
compilers for parallel programming models. This compiler plug-in adds
RDIR support to Regent, a compiler for task-based parallel programs,
with a translator (both AST->RDIR and RDIR->AST) and a number of
sample optimizations which demonstrate how to use the plug-in.
1. Install LLVM *with headers*. (Tested with LLVM 3.5.)
2. Download and install Regent:
git clone https://github.com/StanfordLegion/legion.git
cd legion/language
git checkout -b rdir regent-0.0
./install.py --debug
export REGENT=$PWD
Note: In some cases, Terra may fail to auto-detect CUDA. If so
(and assuming you want to use CUDA), recompile Terra with CUDA
enabled.
cd terra
make clean
CUDA_HOME=.../path/to/cuda ENABLE_CUDA=1 make
3. Install RDIR plug-in:
git clone .../rdir.git
cd rdir
cp -r plugin/src $REGENT
The following test is included which exercises the optimizations
included with RDIR. Both CPU and GPU code paths should be
working. (GPUs are enabled with the flag -ll:gpu N where N is the
number of GPUs to use.)
Running the following commands will produce output reporting bandwidth
and compute throughput on a simple streaming benchmark. In general,
inc1 and inc2 should achieve roughly the same bandwidth. When the RDIR
optimizations are functioning propertly, inc2 will achieve 2x the
compute throughput as inc1 (due to loop and task fusion).
$REGENT/regent.py examples/inc.rg -fcuda 1 -ll:csize 4096
$REGENT/regent.py examples/inc.rg -fcuda 1 -ll:gpu 1 -ll:csize 4096 -ll:fsize 4096
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