Merge pull request #7 from DylanVanAssche/feature/application

Application layer (sender)

application/application.vhd

@@ -0,0 +1,95 @@
+--*******************************
+--* TITLE: Application (sender) *
+--* TYPE: Component		*
+--* AUTHOR: Dylan Van Assche 	*
+--* DATE: 01/10/2017 		*
+--*******************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Application layer API.
+--2)Principle:
+-- Provide an API as application layer
+--3)Ingangen:
+-- cha, rst, clk, clk_en
+--4)Uitgangen:
+-- output, display_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+ENTITY application IS
+	PORT
+	(
+		clk       : IN std_logic;
+		clk_en    : IN std_logic;
+		rst       : IN std_logic;
+		up        : IN std_logic;
+		down      : IN std_logic;
+		output    : OUT std_logic_vector(3 DOWNTO 0);
+		display_b : OUT std_logic_vector(6 DOWNTO 0)
+	);
+END application;
+ARCHITECTURE behavior OF application IS
+	SIGNAL counter_output : std_logic_vector(3 DOWNTO 0);
+	SIGNAL btn_up_deb_s   : std_logic;
+	SIGNAL btn_down_deb_s : std_logic;
+	SIGNAL btn_up_edg_s   : std_logic;
+	SIGNAL btn_down_edg_s : std_logic;
+BEGIN
+	output <= counter_output;
+	decoder : ENTITY work.decoder(behavior)
+	PORT MAP
+	(
+		bin    => counter_output,
+		disp_b => display_b
+	);
+	edge1 : ENTITY work.edgedetector(behavior)
+	PORT MAP
+	(
+		data   => btn_up_deb_s,
+		puls   => btn_up_edg_s,
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst
+	);
+	edge2 : ENTITY work.edgedetector(behavior)
+	PORT MAP
+	(
+		data   => btn_down_deb_s,
+		puls   => btn_down_edg_s,
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst
+	);
+	debounce1 : ENTITY work.debouncer(behavior)
+	PORT MAP
+	(
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst,
+		cha    => up,
+		syncha => btn_up_deb_s
+	);
+	debounce2 : ENTITY work.debouncer(behavior)
+	PORT MAP
+	(
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst,
+		cha    => down,
+		syncha => btn_down_deb_s
+	);
+	counter : ENTITY work.counter(behavior)
+	PORT MAP
+	(
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst,
+		up     => btn_up_edg_s,
+		down   => btn_down_edg_s,
+		output => counter_output
+	);
+END behavior;

application/application_test.vhd

@@ -0,0 +1,102 @@
+--******************************************************************************
+--* TITLE: Application TESTBENCH (sender) *
+--* TYPE: Component *
+--* AUTHOR: Dylan Van Assche *
+--* DATE: 01/10/2017 *
+--******************************************************************************
+--********************
+--* DESCRIPTION *
+--********************
+--1)Purpose:
+-- TESTBENCH: Application layer API.
+--2)Principle:
+-- Provide an API as application layer
+--3)Ingangen:
+-- cha, rst, clk, clk_en
+--4)Uitgangen:
+-- output, display_b
+--***************************
+--* LIBRARIES & ENTITY *
+--***************************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY application_test IS
+END application_test;
+--**************************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--**************************************************
+ARCHITECTURE structural OF application_test IS
+	--initialize signals & constants
+	CONSTANT period   : TIME := 100 ns;
+	CONSTANT delay    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL clk        : std_logic := '0';
+	SIGNAL clk_en     : std_logic := '1';
+	SIGNAL rst        : std_logic := '0';
+	SIGNAL up         : std_logic := '0';
+	SIGNAL down       : std_logic := '0';
+	SIGNAL output     : std_logic_vector(3 DOWNTO 0);
+	SIGNAL display_b  : std_logic_vector(6 DOWNTO 0);
+BEGIN
+--***********
+--* MAPPING *
+--***********
+uut : ENTITY work.application(behavior)
+	PORT MAP
+	(
+		clk       => clk,
+		clk_en    => clk_en,
+		rst       => rst,
+		up        => up,
+		down      => down,
+		output    => output,
+		display_b => display_b
+	);
+-- Only for synchronous components
+clock : PROCESS
+BEGIN
+	clk <= '0';
+	WAIT FOR period/2;
+	LOOP
+		clk <= '0';
+		WAIT FOR period/2;
+		clk <= '1';
+		WAIT FOR period/2;
+		EXIT WHEN end_of_sim;
+	END LOOP;
+	WAIT;
+	END PROCESS clock;
+-- Testbench
+tb : PROCESS
+	-- Reset procedure to initialize the component
+	PROCEDURE reset IS
+	BEGIN
+		rst <= '1';
+		WAIT FOR period * 2;
+		rst <= '0';
+		WAIT FOR period;
+	END reset;
+	-- Test data procedure
+	PROCEDURE test (CONSTANT testdata : IN std_logic_vector(1 DOWNTO 0)) IS
+	BEGIN
+		up   <= testdata(0);
+		down <= testdata(1);
+		WAIT FOR period * 5;
+	END test;
+BEGIN
+	-- Reset at startup
+	reset;
+	-- Test data
+	test("01"); -- up=1, down=0
+	test("00"); -- nothing
+	test("11"); -- nothing
+	test("10"); -- up=0, down=1
+	test("00");
+	clk_en <= '0'; -- disable clock
+	test("10");
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;

application/debouncer/debouncer.vhd

@@ -0,0 +1,63 @@
+--*******************************
+--* TITLE: Debouncer (sender) 	*
+--* TYPE: Component 		*
+--* AUTHOR: Dylan Van Assche 	*
+--* DATE: 28/09/2017 		*
+--*******************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Debouncing the input buttons.
+--2)Principle:
+-- When detecting 4 clock cycles the same input, data is valid.
+--3)Ingangen:
+-- cha, rst, clk
+--4)Uitgangen:
+-- syncha
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY debouncer IS
+	PORT
+	(
+		cha, clk, clk_en, rst : IN std_logic;
+		syncha                : OUT std_logic
+	);
+END debouncer;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF debouncer IS
+	SIGNAL reg      : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
+	SIGNAL reg_next : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
+	SIGNAL sh_ldb   : std_logic;
+BEGIN
+-- output of the shiftreg asigned to syncha (signal -> output)
+syncha <= reg(0);
+-- exor
+sh_ldb <= reg(0) XOR cha;
+-- 2-Process: synchronous part
+sync_debouncer : PROCESS (clk)
+BEGIN
+	IF (rising_edge(clk) AND clk_en = '1') THEN
+		IF (rst = '1') THEN -- reset line high, go to initial state
+			reg <= (OTHERS => '0');
+		ELSE -- normal operation
+			reg <= reg_next;
+		END IF;
+	END IF;
+END PROCESS sync_debouncer;
+-- 2-Process: combinatoric part
+comb_debouncer : PROCESS (reg, sh_ldb, cha)
+BEGIN
+	IF (sh_ldb = '1') THEN
+		reg_next <= cha & reg(3 DOWNTO 1);
+	ELSE
+		reg_next <= (OTHERS => reg(0));
+	END IF;
+END PROCESS comb_debouncer;
+END behavior;

application/debouncer/debouncer_test.vhd

@@ -0,0 +1,96 @@
+--******************************************************************************
+--* TITLE: Debouncer TESTBENCH (sender) *
+--* TYPE: Component *
+--* AUTHOR: Dylan Van Assche *
+--* DATE: 01/10/2017 *
+--******************************************************************************
+--********************
+--* DESCRIPTION *
+--********************
+--1)Purpose:
+-- TESTBENCH: Debouncing the input buttons.
+--2)Principle:
+-- When detecting 4 clock cycles the same input, data is valid.
+--3)Ingangen:
+-- cha, rst, clk
+--4)Uitgangen:
+-- syncha
+--***************************
+--* LIBRARIES & ENTITY *
+--***************************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY debouncer_test IS
+END debouncer_test;
+--**************************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--**************************************************
+ARCHITECTURE structural OF debouncer_test IS
+	--initialize signals & constants
+	CONSTANT period   : TIME := 100 ns;
+	CONSTANT delay    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL clk        : std_logic;
+	SIGNAL clk_en     : std_logic := '1';
+	SIGNAL rst        : std_logic;
+	SIGNAL cha        : std_logic;
+	SIGNAL syncha     : std_logic;
+BEGIN
+--***********
+--* MAPPING *
+--***********
+-- Connect ports to signals (PORT => SIGNAL)
+uut : ENTITY work.debouncer(behavior)
+	PORT MAP
+	(
+		clk    => clk,
+		clk_en => clk_en,
+		rst    => rst,
+		cha    => cha,
+		syncha => syncha
+	);
+
+-- Only for synchronous components
+clock : PROCESS
+BEGIN
+	clk <= '0';
+	WAIT FOR period/2;
+	LOOP
+	clk <= '0';
+	WAIT FOR period/2;
+	clk <= '1';
+	WAIT FOR period/2;
+	EXIT WHEN end_of_sim;
+	END LOOP;
+	WAIT;
+END PROCESS clock;
+-- Testbench
+tb : PROCESS
+	-- Reset procedure to initialize the component
+	PROCEDURE reset IS
+	BEGIN
+		rst <= '1';
+		WAIT FOR period * 2;
+		rst <= '0';
+		WAIT FOR period;
+	END reset;
+	-- Test data procedure
+	PROCEDURE test (CONSTANT testdata : IN std_logic) IS
+	BEGIN
+		cha <= testdata;
+		WAIT FOR period * 4;
+	END test;
+BEGIN
+	-- Reset at startup
+	reset;
+	-- Test data
+	test('0');
+	test('1');
+	test('0');
+	test('1');
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;