Merge pull request #22 from DylanVanAssche/bug/ISSUE-21

Fixed lab notes

README.md

@@ -2,10 +2,15 @@
 This repository contains the VHDL files for the course "Digital Synthese: practica" by Jan Meel (KU Leuven, Campus De Nayer).
 
 ## Files
-- Sender (top file)
-- access layer: PNGenerator, MUX
-- datalink layer: SequenceController, DataRegister
-- application layer: EdgeDetector, UpDownCounter, Debouncer, SegDecoder 
+- Transmitter (top file)
+	- access layer: PNGenerator, MUX
+	- datalink layer: SequenceController, DataRegister
+	- application layer: EdgeDetector, UpDownCounter, Debouncer, SegDecoder 
+
+- Receiver (top file)
+	- access layer
+	- datalink layer
+	- application layer
 
 ## License
 Everything in this repository is available under the GPLv3 License.

receiver/application/datalatch/datalatch.vhd

@@ -0,0 +1,68 @@
+--***************************************
+--* TITLE: Datalatch (receiver)	*
+--* TYPE: Component 			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 26/10/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Read the serial data stream from the access layer and keep it for a limited time in a register.
+-- Application layer will 'ask' if the preamble is in the register before it reads from it
+--2)Principle:
+-- When the shift signal is received, data is shifted out (1 place).
+--3)Inputs:
+-- sh, serialdata, clk, clk_en, rst
+--4)Outputs:
+-- preamble, value
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+
+ENTITY datareg IS
+  PORT (
+		sh         : IN  std_logic;
+		clk        : IN  std_logic;
+		clk_en     : IN  std_logic;
+		rst        : IN  std_logic;
+		serialdata : IN std_logic;
+		value      : OUT std_logic_vector(3 DOWNTO 0);
+		preamble   : OUT std_logic_logic(6 DOWNTO 0)
+    	 );
+END datareg;
+
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF datareg IS
+	SIGNAL reg: std_logic_vector(9 DOWNTO 0);
+	SIGNAL reg_next: std_logic_vector(9 DOWNTO 0);
+BEGIN
+-- connect signal to output
+preamble <= reg(9 DOWNTO 4);
+value <= reg(3 DOWNTO 0);
+-- 2-Process: synchronous part
+reg_sync : PROCESS (clk)
+BEGIN
+	IF (rising_edge(clk) AND clk_en = '1') THEN
+		IF (rst = '1') THEN -- rst line high, go to initial state
+			reg <= (OTHERS => '0');
+		ELSE -- normal operation
+			reg <= reg_next;
+		END IF;
+	END IF;
+END PROCESS reg_sync;
+-- 2-Process: combinatoric part
+reg_comb : PROCESS(reg, sh)
+BEGIN
+	IF sh = '1' THEN -- shift data with serialdata as input
+		reg_next <= reg(9 DOWNTO 1) & serialdata;
+	ELSE -- Input signals wrong!
+		reg_next <= reg;
+	END IF;
+END PROCESS reg_comb;
+END behavior;

receiver/application/datalatch/datalatch_test.vhd

@@ -0,0 +1,110 @@
+--***********************************************
+--* TITLE: Dataregister TESTBENCH (receiver)	*
+--* TYPE: Component 			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 26/10/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Read the serial data stream from the access layer and keep it for a limited time in a register.
+-- Application layer will 'ask' if the preamble is in the register before it reads from it
+--2)Principle:
+-- When the shift signal is received, data is shifted out (1 place).
+--3)Inputs:
+-- sh, serialdata, clk, clk_en, rst
+--4)Outputs:
+-- preamble, value
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY datareg_test IS
+END datareg_test;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE structural OF datareg_test IS
+	--initialize signals & constants
+	CONSTANT PERIOD   : TIME := 100 ns;
+	CONSTANT DELAY    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL clk        : std_logic := '0';
+	SIGNAL clk_en     : std_logic := '1';
+	SIGNAL rst        : std_logic := '0';
+	SIGNAL sh	        : std_logic := '0';
+	SIGNAL value	     : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); -- counter value part register
+	SIGNAL preamble	  : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); -- preamble part register
+BEGIN
+--***********
+--* MAPPING *
+--***********
+uut : ENTITY work.datareg(behavior)
+	PORT MAP
+	(
+		clk        => clk,
+		clk_en     => clk_en,
+		rst        => rst,
+		sh         => sh,
+		serialdata => serialdata,
+		value      => value,
+		preamble   => preamble
+	);
+-- Only for synchronous components
+clock : PROCESS
+BEGIN
+	clk <= '0';
+	WAIT FOR PERIOD/2;
+	LOOP
+		clk <= '0';
+		WAIT FOR PERIOD/2;
+		clk <= '1';
+		WAIT FOR PERIOD/2;
+		EXIT WHEN end_of_sim;
+	END LOOP;
+	WAIT;
+END PROCESS clock;
+-- Testbench
+tb : PROCESS
+	-- Reset procedure to initialize the component
+	PROCEDURE reset IS
+	BEGIN
+		rst <= '1';
+		WAIT FOR PERIOD * 2;
+		rst <= '0';
+		WAIT FOR PERIOD;
+	END reset;
+	-- Test data procedure
+	PROCEDURE test (CONSTANT TESTDATA : IN std_logic_vector(1 DOWNTO 0)) IS
+	BEGIN
+		data <= TESTDATA(0);
+		sh <= TESTDATA(1);
+		WAIT FOR PERIOD * 1;
+		sh <= '0';
+		WAIT FOR PERIOD * 5; -- normally 31 clock cycles for sequence controller (PN_START)
+	END test;
+BEGIN
+	-- Reset at startup
+	reset;
+	-- Test data TO DO
+	FOR counter IN 0 TO 3 LOOP -- 3 cycles with 3 different counter values
+		FOR i IN 0 TO 10 LOOP -- imitate sequencecontroller
+			IF(i = 0) THEN -- load
+				test(CONV_STD_LOGIC_VECTOR(counter, 4) & "01");
+			ELSE -- shift
+				test(CONV_STD_LOGIC_VECTOR(counter, 4) & "10");
+			END IF;
+		END LOOP;
+	END LOOP;
+	clk_en <= '0'; -- disable clock
+	test(CONV_STD_LOGIC_VECTOR(5, 4) & "10");
+	test(CONV_STD_LOGIC_VECTOR(6, 4) & "01");
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;
+

receiver/application/segdecoder/segdecoder.vhd

@@ -0,0 +1,58 @@
+--***************************************************************
+--* TITLE: Binary-To-7-Segment-Display decoder (receiver)	*
+--* TYPE: Component 						*
+--* AUTHOR: Dylan Van Assche 					*
+--* DATE: 01/10/2017 						*
+--***************************************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low)
+--2)Principle:
+-- Switch statement converts the binary data to HEX values which are understand by the 7 segment display
+--3)Inputs:
+-- bin
+--4)Outputs:
+-- disp_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+ENTITY decoder IS
+	PORT
+	(
+		bin    : IN std_logic_vector(3 DOWNTO 0);
+		disp_b : OUT std_logic_vector(6 DOWNTO 0)
+	);
+END decoder;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE behavior OF decoder IS
+BEGIN
+decode : PROCESS (bin)
+BEGIN
+	CASE bin IS
+		WHEN "0000" => disp_b  <= "0000001"; -- '0'
+		WHEN "0001" => disp_b  <= "1001111"; -- '1'
+		WHEN "0010" => disp_b  <= "0010010"; -- '2'
+		WHEN "0011" => disp_b  <= "0000110"; -- '3'
+		WHEN "0100" => disp_b  <= "1001100"; -- '4'
+		WHEN "0101" => disp_b <= "0100100"; -- '5'
+		WHEN "0110" => disp_b <= "0100000"; -- '6'
+		WHEN "0111" => disp_b <= "0001111"; -- '7'
+		WHEN "1000" => disp_b <= "0000000"; -- '8'
+		WHEN "1001" => disp_b <= "0000100"; -- '9'
+		WHEN "1010" => disp_b <= "0000010"; -- 'A'
+		WHEN "1011" => disp_b <= "1100000"; -- 'B'
+		WHEN "1100" => disp_b <= "0110001"; -- 'C'
+		WHEN "1101" => disp_b <= "1000010"; -- 'D'
+		WHEN "1110" => disp_b <= "0010000"; -- 'E'
+		WHEN "1111" => disp_b <= "0111000"; -- 'F'
+		WHEN OTHERS => disp_b     <= "0000000";
+	END CASE;
+END PROCESS decode;
+END behavior;

receiver/application/segdecoder/segdecoder_test.vhd

@@ -0,0 +1,58 @@
+--***********************************************************************
+--* TITLE: Binary-To-7-Segment-Display decoder TESTBENCH (receiver)	*
+--* TYPE: Component 							*
+--* AUTHOR: Dylan Van Assche						*
+--* DATE: 01/10/2017 							*
+--***********************************************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- TESTBENCH: Convert a 4 bit STD_LOGIC_VECTOR to a 7 segment display output (active low)
+--2)Principle:
+-- Switch statement converts the binary data to HEX values which are understand by the 7 segment display
+--3)Inputs:
+-- bin
+--4)Outputs:
+-- disp_b
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.ALL;
+USE ieee.std_logic_arith.ALL;
+ENTITY decoder_test IS
+END decoder_test;
+--*********************************************
+--* ARCHITECTURE, SIGNALS, TYPES & COMPONENTS *
+--*********************************************
+ARCHITECTURE structural OF decoder_test IS
+	-- Initialize signals & constants
+	CONSTANT period   : TIME := 100 ns;
+	CONSTANT delay    : TIME := 10 ns;
+	SIGNAL end_of_sim : BOOLEAN := false;
+	SIGNAL bin        : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
+	SIGNAL disp_b     : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
+BEGIN
+--***********
+--* MAPPING *
+--***********
+uut : ENTITY work.decoder(behavior)
+	PORT MAP
+	(
+		bin    => bin,
+		disp_b => disp_b
+	);
+
+-- Testbench
+tb : PROCESS
+BEGIN
+	FOR i IN 0 TO 15 LOOP
+		bin <= CONV_STD_LOGIC_VECTOR(i, 4);
+		WAIT FOR period;
+	END LOOP;
+	end_of_sim <= true;
+	WAIT;
+END PROCESS;
+END;

transmitter.vhd

@@ -0,0 +1,74 @@
+--***************************************
+--* TITLE: Transmitter (transmitter) 	*
+--* TYPE: Top File			*
+--* AUTHOR: Dylan Van Assche 		*
+--* DATE: 25/10/2017 			*
+--***************************************
+--***************
+--* DESCRIPTION *
+--***************
+--1)Purpose:
+-- Connect all the layers into 1 VHDL file.
+--2)Principle:
+-- Connect every layer API.
+--3)Inputs:
+-- up, down, pn_select, rst, clk, clk_en
+--4)Outputs:
+-- tx
+--**********************
+--* LIBRARIES & ENTITY *
+--**********************
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+ENTITY transmitter IS
+	PORT
+	(
+		clk       : IN std_logic;
+		clk_en    : IN std_logic;
+		rst       : IN std_logic;
+		up	  : IN std_logic;
+		down	  : IN std_logic;
+		pn_select : IN std_logic_vector(1 DOWNTO 0);
+		display_b : OUT std_logic_vector(6 DOWNTO 0);
+		tx	  : OUT std_logic
+	);
+END transmitter ;
+ARCHITECTURE behavior OF transmitter IS
+	SIGNAL counter : std_logic_vector(3 DOWNTO 0);
+	SIGNAL pn_start : std_logic;
+	SIGNAL payload : std_logic;
+BEGIN
+--layers
+application_layer : ENTITY work.application_layer(behavior)
+PORT MAP
+(
+	clk        => clk,
+	clk_en     => clk_en,
+	rst        => rst,
+	up 	   => up,
+	down       => down,
+	display_b  => display_b,
+	output     => counter
+);
+datalink_layer : ENTITY work.datalink_layer(behavior)
+PORT MAP
+(
+	clk      => clk,
+	clk_en   => clk_en,
+	rst      => rst,
+	pn_start => pn_start,
+	output   => payload,
+	data     => counter         
+);
+access_layer : ENTITY work.access_layer(behavior)
+PORT MAP
+(
+	clk       => clk,
+	clk_en    => clk_en,
+	rst       => rst,
+	pn_select => pn_select,
+	pn_start  => pn_start,
+	tx        => tx,
+	data      => payload         
+);
+END behavior;