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atm_bancar.drc
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atm_bancar.drc
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Release 14.7 Drc P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sun May 17 18:07:21 2020
drc -z ATM_BANCAR.ncd ATM_BANCAR.pcf
WARNING:PhysDesignRules:372 - Gated clock. Clock net P1/Mram__n00386 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
P3/Mram_d[3]_GND_129_o_Mux_5_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
P2/Mram_d[3]_GND_120_o_Mux_5_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net pi is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<7>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<8>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<5>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<4>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
DRC detected 0 errors and 13 warnings. Please see the previously displayed
individual error or warning messages for more details.