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ATM_BANCAR_map.map
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ATM_BANCAR_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'ATM_BANCAR'
Design Information
------------------
Command Line : map -intstyle ise -p xc7a100t-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off
-power off -o ATM_BANCAR_map.ncd ATM_BANCAR.ngd ATM_BANCAR.pcf
Target Device : xc7a100t
Target Package : csg324
Target Speed : -3
Mapper Version : artix7 -- $Revision: 1.55 $
Mapped Date : Sun May 17 18:06:12 2020
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 15 secs
Total CPU time at the beginning of Placer: 15 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:80c77cc1) REAL time: 16 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:80c77cc1) REAL time: 16 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:80c77cc1) REAL time: 16 secs
Phase 4.2 Initial Placement for Architecture Specific Features
.......
WARNING:Place:1399 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <clk1> is placed at site <T16>. The corresponding BUFGCTRL
component <clk1_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y31>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <clk1.PAD> allowing
your design to continue. This constraint disables all clock placer rules
related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
WARNING:Place:1399 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <clk2> is placed at site <R10>. The corresponding BUFGCTRL
component <clk2_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y2>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <clk2.PAD> allowing
your design to continue. This constraint disables all clock placer rules
related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
WARNING:Place:1399 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <clk4> is placed at site <V10>. The corresponding BUFGCTRL
component <clk4_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y24>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <clk4.PAD> allowing
your design to continue. This constraint disables all clock placer rules
related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
WARNING:Place:1399 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <clk5> is placed at site <E16>. The corresponding BUFGCTRL
component <clk5_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y26>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <clk5.PAD> allowing
your design to continue. This constraint disables all clock placer rules
related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:172c3aeb) REAL time: 18 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:172c3aeb) REAL time: 18 secs
Phase 6.3 Local Placement Optimization
Phase 6.3 Local Placement Optimization (Checksum:172c3aeb) REAL time: 18 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:172c3aeb) REAL time: 18 secs
Phase 8.8 Global Placement
........................................
.
...................................
....................................................................................................................................................................................................................
.....................................................................................................................................................................
Phase 8.8 Global Placement (Checksum:766084a1) REAL time: 22 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:766084a1) REAL time: 22 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:5252d6b3) REAL time: 23 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:5252d6b3) REAL time: 23 secs
Phase 12.34 Placement Validation
Phase 12.34 Placement Validation (Checksum:5252d6b3) REAL time: 23 secs
Total REAL time to Placer completion: 24 secs
Total CPU time to Placer completion: 24 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net P1/Mram__n00386 is sourced
by a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
P3/Mram_d[3]_GND_129_o_Mux_5_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
P2/Mram_d[3]_GND_120_o_Mux_5_o is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net pi is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<7>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<8>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<5>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<4>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <bancnota_introdusa<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 17
Slice Logic Utilization:
Number of Slice Registers: 169 out of 126,800 1%
Number used as Flip Flops: 119
Number used as Latches: 37
Number used as Latch-thrus: 0
Number used as AND/OR logics: 13
Number of Slice LUTs: 1,918 out of 63,400 3%
Number used as logic: 1,907 out of 63,400 3%
Number using O6 output only: 804
Number using O5 output only: 76
Number using O5 and O6: 1,027
Number used as ROM: 0
Number used as Memory: 0 out of 19,000 0%
Number used exclusively as route-thrus: 11
Number with same-slice register load: 0
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 626 out of 15,850 3%
Number of LUT Flip Flop pairs used: 1,926
Number with an unused Flip Flop: 1,767 out of 1,926 91%
Number with an unused LUT: 8 out of 1,926 1%
Number of fully used LUT-FF pairs: 151 out of 1,926 7%
Number of unique control sets: 15
Number of slice register sites lost
to control set restrictions: 60 out of 126,800 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 34 out of 210 16%
Number of LOCed IOBs: 34 out of 34 100%
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 0 out of 135 0%
Number of RAMB18E1/FIFO18E1s: 0 out of 270 0%
Number of BUFG/BUFGCTRLs: 7 out of 32 21%
Number used as BUFGs: 7
Number used as BUFGCTRLs: 0
Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 300 0%
Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 300 0%
Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0
Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 300 0%
Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 24 0%
Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 24 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 96 0%
Number of BUFRs: 0 out of 24 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DNA_PORTs: 0 out of 1 0%
Number of DSP48E1s: 3 out of 240 1%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of IBUFDS_GTE2s: 0 out of 4 0%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 0 out of 6 0%
Number of IN_FIFOs: 0 out of 24 0%
Number of MMCME2_ADVs: 0 out of 6 0%
Number of OUT_FIFOs: 0 out of 24 0%
Number of PCIE_2_1s: 0 out of 1 0%
Number of PHASER_REFs: 0 out of 6 0%
Number of PHY_CONTROLs: 0 out of 6 0%
Number of PLLE2_ADVs: 0 out of 6 0%
Number of STARTUPs: 0 out of 1 0%
Number of XADCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 5011 MB
Total REAL time to MAP completion: 26 secs
Total CPU time to MAP completion: 25 secs
Mapping completed.
See MAP report file "ATM_BANCAR_map.mrp" for details.