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ATM_BANCAR.twr
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ATM_BANCAR.twr
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
D:\ISE\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n 3
-fastpaths -xml ATM_BANCAR.twx ATM_BANCAR.ncd -o ATM_BANCAR.twr ATM_BANCAR.pcf
-ucf ATM_bancar.ucf
Design file: ATM_BANCAR.ncd
Physical constraint file: ATM_BANCAR.pcf
Device,package,speed: xc7a100t,csg324,C,-3 (PRODUCTION 1.10 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
--------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
--------------+------------+------------+------------+------------+------------------+--------+
adresa_card<0>| 0.501(R)| FAST | 1.595(R)| SLOW |clk_BUFGP | 0.000|
adresa_card<1>| 0.361(R)| FAST | 1.562(R)| SLOW |clk_BUFGP | 0.000|
adresa_card<2>| 0.667(R)| FAST | 1.822(R)| SLOW |clk_BUFGP | 0.000|
op<0> | 0.815(R)| FAST | 1.475(R)| SLOW |clk_BUFGP | 0.000|
op<1> | 0.852(R)| FAST | 1.628(R)| SLOW |clk_BUFGP | 0.000|
--------------+------------+------------+------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 2.551| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk1 | 1.783| | | |
clk5 | 2.527| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk2
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk2 | 1.690| | | |
clk5 | 2.745| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk3
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk3 | 1.642| | | |
clk5 | 3.508| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk4
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk4 | 1.644| | | |
clk5 | 3.333| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk5
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk5 | 0.778| | | |
---------------+---------+---------+---------+---------+
Analysis completed Sun May 17 18:07:12 2020
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 4977 MB