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ATM_BANCAR.syr
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ATM_BANCAR.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.07 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.07 secs
--> Reading design: ATM_BANCAR.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "ATM_BANCAR.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "ATM_BANCAR"
Output Format : NGC
Target Device : xc7a100t-3-csg324
---- Source Options
Top Module Name : ATM_BANCAR
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Dec_sute.vhd" into library work
Parsing entity <conv_test>.
Parsing architecture <Behavioral> of entity <conv_test>.
Parsing entity <decodificator_sute>.
Parsing architecture <comp> of entity <decodificator_sute>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Sumator_RAM.vhd" into library work
Parsing entity <Sumator_Sold>.
Parsing architecture <comp> of entity <sumator_sold>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Scazator_RAM.vhd" into library work
Parsing entity <scazator_sold>.
Parsing architecture <comp> of entity <scazator_sold>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_zeci.vhd" into library work
Parsing entity <Pin_zeci>.
Parsing architecture <comp> of entity <pin_zeci>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_unit.vhd" into library work
Parsing entity <Pin_unit>.
Parsing architecture <comp> of entity <pin_unit>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_sute.vhd" into library work
Parsing entity <Pin_sute>.
Parsing architecture <comp> of entity <pin_sute>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_mii.vhd" into library work
Parsing entity <Pin_mii>.
Parsing architecture <comp> of entity <pin_mii>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Num_500.vhd" into library work
Parsing entity <Num_500>.
Parsing architecture <comp> of entity <num_500>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Num_50.vhd" into library work
Parsing entity <Num_50>.
Parsing architecture <comp> of entity <num_50>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Num_20.vhd" into library work
Parsing entity <Num_20>.
Parsing architecture <comp> of entity <num_20>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Num_100.vhd" into library work
Parsing entity <Num_100>.
Parsing architecture <comp> of entity <num_100>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Num_10.vhd" into library work
Parsing entity <Num_10>.
Parsing architecture <comp> of entity <num_10>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Numarator_5.vhd" into library work
Parsing entity <Num_5>.
Parsing architecture <comp> of entity <num_5>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_ROM_exp_card.vhd" into library work
Parsing entity <ROM_EXP>.
Parsing architecture <comp> of entity <rom_exp>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_RAM_SOLD.vhd" into library work
Parsing entity <RAM_SOLD>.
Parsing architecture <comp> of entity <ram_sold>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_RAM_PIN.vhd" into library work
Parsing entity <RAM_PIN>.
Parsing architecture <comp> of entity <ram_pin>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Formare_PIN.vhd" into library work
Parsing entity <asamblare_pin>.
Parsing architecture <comp> of entity <asamblare_pin>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Dmux_PIN_PIN_NOU_SUMA.vhd" into library work
Parsing entity <Selectare_PIN_SUME>.
Parsing architecture <comp> of entity <selectare_pin_sume>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Demux_OP.vhd" into library work
Parsing entity <DMUX_OP>.
Parsing architecture <comp> of entity <dmux_op>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Demux_Bancnote.vhd" into library work
Parsing entity <DMUX_BANC>.
Parsing architecture <comp> of entity <dmux_banc>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Decod_zeci.vhd" into library work
Parsing entity <conv_test>.
Parsing architecture <Behavioral> of entity <conv_test>.
Parsing entity <decodificator_zeci>.
Parsing architecture <comp> of entity <decodificator_zeci>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Decod_unit.vhd" into library work
Parsing entity <conv_test>.
Parsing architecture <Behavioral> of entity <conv_test>.
Parsing entity <decodificator_unit>.
Parsing architecture <comp> of entity <decodificator_unit>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Decod_Mii.vhd" into library work
Parsing entity <conv_test>.
Parsing architecture <Behavioral> of entity <conv_test>.
Parsing entity <decodificator_mii>.
Parsing architecture <comp> of entity <decodificator_mii>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Decodificator_bancnote.vhd" into library work
Parsing entity <Decod_Banc>.
Parsing architecture <comp> of entity <decod_banc>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_SUME.vhd" into library work
Parsing entity <COMP_SUMA>.
Parsing architecture <comp> of entity <comp_suma>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_PIN.vhd" into library work
Parsing entity <COMP_PIN>.
Parsing architecture <comp> of entity <comp_pin>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_DATA.vhd" into library work
Parsing entity <COMP_DATA>.
Parsing architecture <comp> of entity <comp_data>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_cu_1000.vhd" into library work
Parsing entity <COMP_1000>.
Parsing architecture <comp> of entity <comp_1000>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_Bancnote.vhd" into library work
Parsing entity <Comp_BANC>.
Parsing architecture <comp> of entity <comp_banc>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Afisare_sold.vhd" into library work
Parsing entity <afisare_sold>.
Parsing architecture <arh> of entity <afisare_sold>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Afisare_PIN_schimbat.vhd" into library work
Parsing entity <afisare_pin_schimbat>.
Parsing architecture <arh> of entity <afisare_pin_schimbat>.
Parsing VHDL file "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" into library work
Parsing entity <ATM_BANCAR>.
Parsing architecture <STRUCTURALA> of entity <atm_bancar>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <ATM_BANCAR> (architecture <STRUCTURALA>) from library <work>.
Elaborating entity <ROM_EXP> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_ROM_exp_card.vhd" Line 13: Using initial value ("11111100100","11111100101","11111100110","11111100101","11111100011") for an_mem since it is never assigned
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_ROM_exp_card.vhd" Line 14: Using initial value ("1100","1001","1010","1001","1000") for luna_mem since it is never assigned
Elaborating entity <COMP_DATA> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_DATA.vhd" Line 10: Using initial value "0100" for luna_curenta since it is never assigned
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_DATA.vhd" Line 11: Using initial value "11111100100" for an_curent since it is never assigned
WARNING:HDLCompiler:92 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_DATA.vhd" Line 22: luna_curenta should be on the sensitivity list of the process
Elaborating entity <RAM_PIN> (architecture <comp>) from library <work>.
Elaborating entity <Selectare_PIN_SUME> (architecture <comp>) from library <work>.
Elaborating entity <Pin_unit> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:92 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_unit.vhd" Line 19: num should be on the sensitivity list of the process
Elaborating entity <Pin_zeci> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:92 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_zeci.vhd" Line 19: num should be on the sensitivity list of the process
Elaborating entity <Pin_sute> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:92 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_sute.vhd" Line 19: num should be on the sensitivity list of the process
Elaborating entity <Pin_mii> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:92 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_mii.vhd" Line 19: num should be on the sensitivity list of the process
Elaborating entity <asamblare_pin> (architecture <comp>) from library <work>.
Elaborating entity <COMP_PIN> (architecture <comp>) from library <work>.
Elaborating entity <DMUX_OP> (architecture <comp>) from library <work>.
Elaborating entity <RAM_SOLD> (architecture <comp>) from library <work>.
Elaborating entity <decodificator_mii> (architecture <comp>) from library <work>.
Elaborating entity <conv_test> (architecture <Behavioral>) from library <work>.
Elaborating entity <decodificator_sute> (architecture <comp>) from library <work>.
Elaborating entity <decodificator_zeci> (architecture <comp>) from library <work>.
Elaborating entity <decodificator_unit> (architecture <comp>) from library <work>.
Elaborating entity <afisare_sold> (architecture <arh>) from library <work>.
WARNING:HDLCompiler:92 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Afisare_sold.vhd" Line 32: enable should be on the sensitivity list of the process
Elaborating entity <afisare_pin_schimbat> (architecture <arh>) from library <work>.
Elaborating entity <COMP_1000> (architecture <comp>) from library <work>.
Elaborating entity <COMP_SUMA> (architecture <comp>) from library <work>.
Elaborating entity <Num_5> (architecture <comp>) from library <work>.
Elaborating entity <Num_10> (architecture <comp>) from library <work>.
Elaborating entity <Num_20> (architecture <comp>) from library <work>.
Elaborating entity <Num_50> (architecture <comp>) from library <work>.
Elaborating entity <Num_100> (architecture <comp>) from library <work>.
Elaborating entity <Num_500> (architecture <comp>) from library <work>.
Elaborating entity <Comp_BANC> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_Bancnote.vhd" Line 15: Using initial value ("0000000000000101","0000000000001010","0000000000010100","0000000000110010","0000000001100100","0000000111110100") for banc_plus since it is never assigned
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_Bancnote.vhd" Line 21: Using initial value "00000001" for s since it is never assigned
Elaborating entity <scazator_sold> (architecture <comp>) from library <work>.
Elaborating entity <Decod_Banc> (architecture <comp>) from library <work>.
Elaborating entity <Sumator_Sold> (architecture <comp>) from library <work>.
WARNING:HDLCompiler:871 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Sumator_RAM.vhd" Line 14: Using initial value ("0000000000000101","0000000000001010","0000000000010100","0000000000110010","0000000001100100","0000000111110100") for banc_plus since it is never assigned
Elaborating entity <DMUX_BANC> (architecture <comp>) from library <work>.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 263. All outputs of instance <P4> of block <decodificator_unit> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 265. All outputs of instance <C8> of block <RAM_PIN> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 277. All outputs of instance <C20> of block <Num_5> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 278. All outputs of instance <C21> of block <Num_10> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 279. All outputs of instance <C22> of block <Num_20> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 280. All outputs of instance <C23> of block <Num_50> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 281. All outputs of instance <C24> of block <Num_100> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 282. All outputs of instance <C25> of block <Num_500> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 284. All outputs of instance <C27> of block <RAM_SOLD> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 285. All outputs of instance <C28> of block <Decod_Banc> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 286. All outputs of instance <C29> of block <RAM_SOLD> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 287. All outputs of instance <C30> of block <Sumator_Sold> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 288. All outputs of instance <C31> of block <RAM_SOLD> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 289. All outputs of instance <C32> of block <DMUX_BANC> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 290. All outputs of instance <C33> of block <Num_5> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 291. All outputs of instance <C34> of block <Num_10> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 292. All outputs of instance <C35> of block <Num_20> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 293. All outputs of instance <C36> of block <Num_50> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 294. All outputs of instance <C37> of block <Num_100> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 295. All outputs of instance <C38> of block <Num_500> are unconnected in block <ATM_BANCAR>. Underlying logic will be removed.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ATM_BANCAR>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd".
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 263: Output port <nr_decodificat> of the instance <P4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 265: Output port <pin_dat> of the instance <C8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 277: Output port <Q> of the instance <C20> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 278: Output port <Q> of the instance <C21> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 279: Output port <Q> of the instance <C22> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 280: Output port <Q> of the instance <C23> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 281: Output port <Q> of the instance <C24> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 282: Output port <Q> of the instance <C25> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 284: Output port <suma_exist> of the instance <C27> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 285: Output port <banc_ok> of the instance <C28> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 288: Output port <suma_exist> of the instance <C31> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 290: Output port <Q> of the instance <C33> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 291: Output port <Q> of the instance <C34> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 292: Output port <Q> of the instance <C35> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 293: Output port <Q> of the instance <C36> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 294: Output port <Q> of the instance <C37> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/ATM.vhd" line 295: Output port <Q> of the instance <C38> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <ATM_BANCAR> synthesized.
Synthesizing Unit <ROM_EXP>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_ROM_exp_card.vhd".
Found 8x15-bit Read Only RAM for signal <_n0047>
Summary:
inferred 1 RAM(s).
Unit <ROM_EXP> synthesized.
Synthesizing Unit <COMP_DATA>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_DATA.vhd".
Found 11-bit comparator greater for signal <an_exp[10]_PWR_6_o_LessThan_2_o> created at line 18
Found 11-bit comparator greater for signal <PWR_6_o_an_exp[10]_LessThan_3_o> created at line 20
Found 4-bit comparator greater for signal <GND_20_o_luna_exp[3]_LessThan_4_o> created at line 22
Summary:
inferred 3 Comparator(s).
inferred 3 Multiplexer(s).
Unit <COMP_DATA> synthesized.
Synthesizing Unit <RAM_PIN>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_RAM_PIN.vhd".
Found 16-bit register for signal <PIN_MEM<0>>.
Found 16-bit register for signal <PIN_MEM<1>>.
Found 16-bit register for signal <PIN_MEM<2>>.
Found 16-bit register for signal <PIN_MEM<3>>.
Found 1-bit register for signal <cs_clk_DFF_17>.
Found 1-bit register for signal <cs_clk_DFF_18>.
Found 1-bit register for signal <cs_clk_DFF_19>.
Found 1-bit register for signal <cs_clk_DFF_20>.
Found 1-bit register for signal <cs_clk_DFF_21>.
Found 1-bit register for signal <cs_clk_DFF_22>.
Found 1-bit register for signal <cs_clk_DFF_23>.
Found 1-bit register for signal <cs_clk_DFF_24>.
Found 1-bit register for signal <cs_clk_DFF_25>.
Found 1-bit register for signal <cs_clk_DFF_26>.
Found 1-bit register for signal <cs_clk_DFF_27>.
Found 1-bit register for signal <cs_clk_DFF_28>.
Found 1-bit register for signal <cs_clk_DFF_29>.
Found 1-bit register for signal <cs_clk_DFF_30>.
Found 1-bit register for signal <cs_clk_DFF_31>.
Found 1-bit register for signal <cs_clk_DFF_32>.
Found 16-bit register for signal <pin_dat[15]_dff_16_OUT>.
Found 16-bit 4-to-1 multiplexer for signal <_n0139> created at line 28.
Found 1-bit tristate buffer for signal <pin_dat<15>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<14>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<13>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<12>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<11>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<10>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<9>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<8>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<7>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<6>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<5>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<4>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<3>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<2>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<1>> created at line 15
Found 1-bit tristate buffer for signal <pin_dat<0>> created at line 15
Summary:
inferred 96 D-type flip-flop(s).
inferred 2 Multiplexer(s).
inferred 16 Tristate(s).
Unit <RAM_PIN> synthesized.
Synthesizing Unit <Selectare_PIN_SUME>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Dmux_PIN_PIN_NOU_SUMA.vhd".
Found 2-bit register for signal <op>.
Found 2-bit adder for signal <op[1]_op[1]_mux_1_OUT> created at line 19.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 2 D-type flip-flop(s).
Unit <Selectare_PIN_SUME> synthesized.
Synthesizing Unit <Pin_unit>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_unit.vhd".
Found 32-bit register for signal <num>.
Found 32-bit adder for signal <num[31]_GND_58_o_add_0_OUT> created at line 16.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
Unit <Pin_unit> synthesized.
Synthesizing Unit <Pin_zeci>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_zeci.vhd".
Found 32-bit register for signal <num>.
Found 32-bit adder for signal <num[31]_GND_59_o_add_0_OUT> created at line 16.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
Unit <Pin_zeci> synthesized.
Synthesizing Unit <Pin_sute>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_sute.vhd".
Found 32-bit register for signal <unit>.
Found 32-bit register for signal <num>.
Found 32-bit adder for signal <num[31]_GND_60_o_add_0_OUT> created at line 16.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 64 D-type flip-flop(s).
Unit <Pin_sute> synthesized.
Synthesizing Unit <Pin_mii>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Pin_mii.vhd".
Found 32-bit register for signal <num>.
Found 32-bit adder for signal <num[31]_GND_61_o_add_0_OUT> created at line 16.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 32 D-type flip-flop(s).
Unit <Pin_mii> synthesized.
Synthesizing Unit <asamblare_pin>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Formare_PIN.vhd".
Found 32-bit adder for signal <n0036> created at line 19.
Found 32-bit adder for signal <n0039> created at line 19.
Found 32-bit adder for signal <n0031> created at line 19.
Found 32x5-bit multiplier for signal <n0026> created at line 19.
Found 32x8-bit multiplier for signal <n0028> created at line 19.
Found 32x11-bit multiplier for signal <n0030> created at line 19.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <pin<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 3 Multiplier(s).
inferred 3 Adder/Subtractor(s).
inferred 16 Latch(s).
Unit <asamblare_pin> synthesized.
Synthesizing Unit <COMP_PIN>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_PIN.vhd".
Found 16-bit comparator equal for signal <pin_ok> created at line 14
Summary:
inferred 1 Comparator(s).
Unit <COMP_PIN> synthesized.
Synthesizing Unit <DMUX_OP>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Demux_OP.vhd".
Summary:
no macro.
Unit <DMUX_OP> synthesized.
Synthesizing Unit <RAM_SOLD>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Memorie_RAM_SOLD.vhd".
Found 16-bit register for signal <SOLD_MEM<0>>.
Found 16-bit register for signal <SOLD_MEM<1>>.
Found 16-bit register for signal <SOLD_MEM<2>>.
Found 16-bit register for signal <SOLD_MEM<3>>.
Found 16-bit register for signal <suma_exist>.
Found 16-bit 5-to-1 multiplexer for signal <adresa_card[2]_GND_85_o_wide_mux_0_OUT> created at line 18.
Summary:
inferred 80 D-type flip-flop(s).
inferred 5 Multiplexer(s).
Unit <RAM_SOLD> synthesized.
Synthesizing Unit <decodificator_mii>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Decod_Mii.vhd".
Found 16x8-bit Read Only RAM for signal <_n0038>
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 1 RAM(s).
inferred 7 Latch(s).
Unit <decodificator_mii> synthesized.
Synthesizing Unit <conv_test>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Dec_sute.vhd".
Summary:
no macro.
Unit <conv_test> synthesized.
Synthesizing Unit <div_32s_11s>.
Related source file is "".
Found 32-bit subtractor for signal <a[31]_unary_minus_1_OUT> created at line 0.
Found 33-bit adder for signal <GND_105_o_BUS_0001_add_70_OUT[32:0]> created at line 0.
Found 43-bit adder for signal <GND_105_o_b[10]_add_5_OUT> created at line 0.
Found 42-bit adder for signal <GND_105_o_b[10]_add_7_OUT> created at line 0.
Found 41-bit adder for signal <GND_105_o_b[10]_add_9_OUT> created at line 0.
Found 40-bit adder for signal <GND_105_o_b[10]_add_11_OUT> created at line 0.
Found 39-bit adder for signal <GND_105_o_b[10]_add_13_OUT> created at line 0.
Found 38-bit adder for signal <GND_105_o_b[10]_add_15_OUT> created at line 0.
Found 37-bit adder for signal <GND_105_o_b[10]_add_17_OUT> created at line 0.
Found 36-bit adder for signal <GND_105_o_b[10]_add_19_OUT> created at line 0.
Found 35-bit adder for signal <GND_105_o_b[10]_add_21_OUT> created at line 0.
Found 34-bit adder for signal <GND_105_o_b[10]_add_23_OUT> created at line 0.
Found 33-bit adder for signal <GND_105_o_b[10]_add_25_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_b[10]_add_27_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_29_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_31_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_33_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_35_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_37_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_39_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_41_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_43_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_45_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_47_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_49_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_51_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_53_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_55_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_57_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_59_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_61_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_63_OUT[31:0]> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_65_OUT[31:0]> created at line 0.
Found 32-bit adder for signal <a[31]_GND_105_o_add_67_OUT[31:0]> created at line 0.
Found 43-bit comparator greater for signal <BUS_0001_INV_1441_o> created at line 0
Found 42-bit comparator greater for signal <BUS_0002_INV_1440_o> created at line 0
Found 41-bit comparator greater for signal <BUS_0003_INV_1439_o> created at line 0
Found 40-bit comparator greater for signal <BUS_0004_INV_1438_o> created at line 0
Found 39-bit comparator greater for signal <BUS_0005_INV_1437_o> created at line 0
Found 38-bit comparator greater for signal <BUS_0006_INV_1436_o> created at line 0
Found 37-bit comparator greater for signal <BUS_0007_INV_1435_o> created at line 0
Found 36-bit comparator greater for signal <BUS_0008_INV_1434_o> created at line 0
Found 35-bit comparator greater for signal <BUS_0009_INV_1433_o> created at line 0
Found 34-bit comparator greater for signal <BUS_0010_INV_1432_o> created at line 0
Found 33-bit comparator greater for signal <BUS_0011_INV_1431_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0012_INV_1430_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0013_INV_1429_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0014_INV_1428_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0015_INV_1427_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0016_INV_1426_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0017_INV_1425_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0018_INV_1424_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0019_INV_1423_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0020_INV_1422_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0021_INV_1421_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0022_INV_1420_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0023_INV_1419_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0024_INV_1418_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0025_INV_1417_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0026_INV_1416_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0027_INV_1415_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0028_INV_1414_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0029_INV_1413_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0030_INV_1412_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0031_INV_1411_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0032_INV_1410_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0033_INV_1409_o> created at line 0
Summary:
inferred 34 Adder/Subtractor(s).
inferred 33 Comparator(s).
inferred 933 Multiplexer(s).
Unit <div_32s_11s> synthesized.
Synthesizing Unit <mod_32s_5s>.
Related source file is "".
Found 32-bit subtractor for signal <a[31]_unary_minus_1_OUT> created at line 0.
Found 5-bit subtractor for signal <b[4]_unary_minus_3_OUT> created at line 0.
Found 37-bit adder for signal <n2449> created at line 0.
Found 37-bit adder for signal <GND_108_o_b[4]_add_5_OUT> created at line 0.
Found 36-bit adder for signal <n2453> created at line 0.
Found 36-bit adder for signal <GND_108_o_b[4]_add_7_OUT> created at line 0.
Found 35-bit adder for signal <n2457> created at line 0.
Found 35-bit adder for signal <GND_108_o_b[4]_add_9_OUT> created at line 0.
Found 34-bit adder for signal <n2461> created at line 0.
Found 34-bit adder for signal <GND_108_o_b[4]_add_11_OUT> created at line 0.
Found 33-bit adder for signal <n2465> created at line 0.
Found 33-bit adder for signal <GND_108_o_b[4]_add_13_OUT> created at line 0.
Found 32-bit adder for signal <n2469> created at line 0.
Found 32-bit adder for signal <a[31]_b[4]_add_15_OUT> created at line 0.
Found 32-bit adder for signal <n2473> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_17_OUT> created at line 0.
Found 32-bit adder for signal <n2477> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_19_OUT> created at line 0.
Found 32-bit adder for signal <n2481> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_21_OUT> created at line 0.
Found 32-bit adder for signal <n2485> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_23_OUT> created at line 0.
Found 32-bit adder for signal <n2489> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_25_OUT> created at line 0.
Found 32-bit adder for signal <n2493> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_27_OUT> created at line 0.
Found 32-bit adder for signal <n2497> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_29_OUT> created at line 0.
Found 32-bit adder for signal <n2501> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_31_OUT> created at line 0.
Found 32-bit adder for signal <n2505> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_33_OUT> created at line 0.
Found 32-bit adder for signal <n2509> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_35_OUT> created at line 0.
Found 32-bit adder for signal <n2513> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_37_OUT> created at line 0.
Found 32-bit adder for signal <n2517> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_39_OUT> created at line 0.
Found 32-bit adder for signal <n2521> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_41_OUT> created at line 0.
Found 32-bit adder for signal <n2525> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_43_OUT> created at line 0.
Found 32-bit adder for signal <n2529> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_45_OUT> created at line 0.
Found 32-bit adder for signal <n2533> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_47_OUT> created at line 0.
Found 32-bit adder for signal <n2537> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_49_OUT> created at line 0.
Found 32-bit adder for signal <n2541> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_51_OUT> created at line 0.
Found 32-bit adder for signal <n2545> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_53_OUT> created at line 0.
Found 32-bit adder for signal <n2549> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_55_OUT> created at line 0.
Found 32-bit adder for signal <n2553> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_57_OUT> created at line 0.
Found 32-bit adder for signal <n2557> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_59_OUT> created at line 0.
Found 32-bit adder for signal <n2561> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_61_OUT> created at line 0.
Found 32-bit adder for signal <n2565> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_63_OUT> created at line 0.
Found 32-bit adder for signal <n2569> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_65_OUT> created at line 0.
Found 32-bit adder for signal <n2573> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_67_OUT> created at line 0.
Found 32-bit adder for signal <n2577> created at line 0.
Found 32-bit adder for signal <a[31]_GND_108_o_add_69_OUT> created at line 0.
Found 5-bit adder for signal <n2581> created at line 0.
Found 5-bit adder for signal <b[4]_a[31]_add_71_OUT> created at line 0.
Found 5-bit adder for signal <GND_108_o_a[31]_add_72_OUT[4:0]> created at line 0.
Found 37-bit comparator lessequal for signal <BUS_0001> created at line 0
Found 36-bit comparator lessequal for signal <BUS_0002> created at line 0
Found 35-bit comparator lessequal for signal <BUS_0003> created at line 0
Found 34-bit comparator lessequal for signal <BUS_0004> created at line 0
Found 33-bit comparator lessequal for signal <BUS_0005> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0006> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0007> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0008> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0009> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0010> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0011> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0012> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0013> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0014> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0015> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0016> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0017> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0018> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0019> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0020> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0021> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0022> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0023> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0024> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0025> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0026> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0027> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0028> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0029> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0030> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0031> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0032> created at line 0
Found 32-bit comparator lessequal for signal <BUS_0033> created at line 0
Summary:
inferred 71 Adder/Subtractor(s).
inferred 33 Comparator(s).
inferred 1037 Multiplexer(s).
Unit <mod_32s_5s> synthesized.
Synthesizing Unit <decodificator_sute>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Dec_sute.vhd".
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[6]_Mux_4_o>
Found 16x1-bit Read Only RAM for signal <d[3]_GND_120_o_Mux_5_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[5]_Mux_6_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[4]_Mux_8_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[3]_Mux_10_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[2]_Mux_12_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[1]_Mux_14_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[0]_Mux_16_o>
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 8 RAM(s).
inferred 7 Latch(s).
Unit <decodificator_sute> synthesized.
Synthesizing Unit <div_32s_8s>.
Related source file is "".
Found 32-bit subtractor for signal <a[31]_unary_minus_1_OUT> created at line 0.
Found 33-bit adder for signal <GND_118_o_BUS_0001_add_70_OUT[32:0]> created at line 0.
Found 40-bit adder for signal <GND_118_o_b[7]_add_5_OUT> created at line 0.
Found 39-bit adder for signal <GND_118_o_b[7]_add_7_OUT> created at line 0.
Found 38-bit adder for signal <GND_118_o_b[7]_add_9_OUT> created at line 0.
Found 37-bit adder for signal <GND_118_o_b[7]_add_11_OUT> created at line 0.
Found 36-bit adder for signal <GND_118_o_b[7]_add_13_OUT> created at line 0.
Found 35-bit adder for signal <GND_118_o_b[7]_add_15_OUT> created at line 0.
Found 34-bit adder for signal <GND_118_o_b[7]_add_17_OUT> created at line 0.
Found 33-bit adder for signal <GND_118_o_b[7]_add_19_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_b[7]_add_21_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_23_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_25_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_27_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_29_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_31_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_33_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_35_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_37_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_39_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_41_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_43_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_45_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_47_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_49_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_51_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_53_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_55_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_57_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_59_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_61_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_63_OUT[31:0]> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_65_OUT[31:0]> created at line 0.
Found 32-bit adder for signal <a[31]_GND_118_o_add_67_OUT[31:0]> created at line 0.
Found 40-bit comparator greater for signal <BUS_0001_INV_3726_o> created at line 0
Found 39-bit comparator greater for signal <BUS_0002_INV_3725_o> created at line 0
Found 38-bit comparator greater for signal <BUS_0003_INV_3724_o> created at line 0
Found 37-bit comparator greater for signal <BUS_0004_INV_3723_o> created at line 0
Found 36-bit comparator greater for signal <BUS_0005_INV_3722_o> created at line 0
Found 35-bit comparator greater for signal <BUS_0006_INV_3721_o> created at line 0
Found 34-bit comparator greater for signal <BUS_0007_INV_3720_o> created at line 0
Found 33-bit comparator greater for signal <BUS_0008_INV_3719_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0009_INV_3718_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0010_INV_3717_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0011_INV_3716_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0012_INV_3715_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0013_INV_3714_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0014_INV_3713_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0015_INV_3712_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0016_INV_3711_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0017_INV_3710_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0018_INV_3709_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0019_INV_3708_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0020_INV_3707_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0021_INV_3706_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0022_INV_3705_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0023_INV_3704_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0024_INV_3703_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0025_INV_3702_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0026_INV_3701_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0027_INV_3700_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0028_INV_3699_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0029_INV_3698_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0030_INV_3697_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0031_INV_3696_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0032_INV_3695_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0033_INV_3694_o> created at line 0
Summary:
inferred 34 Adder/Subtractor(s).
inferred 33 Comparator(s).
inferred 933 Multiplexer(s).
Unit <div_32s_8s> synthesized.
Synthesizing Unit <decodificator_zeci>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Decod_zeci.vhd".
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[6]_Mux_4_o>
Found 16x1-bit Read Only RAM for signal <d[3]_GND_129_o_Mux_5_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[5]_Mux_6_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[4]_Mux_8_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[3]_Mux_10_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[2]_Mux_12_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[1]_Mux_14_o>
Found 16x1-bit Read Only RAM for signal <d[3]_nr_decodificat[0]_Mux_16_o>
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <nr_decodificat<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Summary:
inferred 8 RAM(s).
inferred 7 Latch(s).
Unit <decodificator_zeci> synthesized.
Synthesizing Unit <div_32s_5s>.
Related source file is "".
Found 32-bit subtractor for signal <a[31]_unary_minus_1_OUT> created at line 0.
Found 33-bit adder for signal <GND_128_o_BUS_0001_add_70_OUT[32:0]> created at line 0.
Found 37-bit adder for signal <GND_128_o_b[4]_add_5_OUT> created at line 0.
Found 36-bit adder for signal <GND_128_o_b[4]_add_7_OUT> created at line 0.
Found 35-bit adder for signal <GND_128_o_b[4]_add_9_OUT> created at line 0.
Found 34-bit adder for signal <GND_128_o_b[4]_add_11_OUT> created at line 0.
Found 33-bit adder for signal <GND_128_o_b[4]_add_13_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_b[4]_add_15_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_17_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_19_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_21_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_23_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_25_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_27_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_29_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_31_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_33_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_35_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_37_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_39_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_41_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_43_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_45_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_47_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_49_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_51_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_53_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_55_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_57_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_59_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_61_OUT> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_63_OUT[31:0]> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_65_OUT[31:0]> created at line 0.
Found 32-bit adder for signal <a[31]_GND_128_o_add_67_OUT[31:0]> created at line 0.
Found 37-bit comparator greater for signal <BUS_0001_INV_4863_o> created at line 0
Found 36-bit comparator greater for signal <BUS_0002_INV_4862_o> created at line 0
Found 35-bit comparator greater for signal <BUS_0003_INV_4861_o> created at line 0
Found 34-bit comparator greater for signal <BUS_0004_INV_4860_o> created at line 0
Found 33-bit comparator greater for signal <BUS_0005_INV_4859_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0006_INV_4858_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0007_INV_4857_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0008_INV_4856_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0009_INV_4855_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0010_INV_4854_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0011_INV_4853_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0012_INV_4852_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0013_INV_4851_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0014_INV_4850_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0015_INV_4849_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0016_INV_4848_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0017_INV_4847_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0018_INV_4846_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0019_INV_4845_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0020_INV_4844_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0021_INV_4843_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0022_INV_4842_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0023_INV_4841_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0024_INV_4840_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0025_INV_4839_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0026_INV_4838_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0027_INV_4837_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0028_INV_4836_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0029_INV_4835_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0030_INV_4834_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0031_INV_4833_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0032_INV_4832_o> created at line 0
Found 32-bit comparator greater for signal <BUS_0033_INV_4831_o> created at line 0
Summary:
inferred 34 Adder/Subtractor(s).
inferred 33 Comparator(s).
inferred 933 Multiplexer(s).
Unit <div_32s_5s> synthesized.
Synthesizing Unit <afisare_sold>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Afisare_sold.vhd".
Found 1-bit register for signal <PWR_121_o_cclk_DFF_89>.
Found 7-bit register for signal <dec_zeci[6]_dff_15_OUT>.
Found 32-bit register for signal <i>.
Found 11-bit register for signal <clkdiv>.
Found 4-bit register for signal <PWR_120_o_dff_14_OUT>.
Found finite state machine <FSM_0> for signal <i>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 11 |
| Inputs | 2 |
| Outputs | 6 |
| Clock | cclk (rising_edge) |
| Power Up State | 00000000000000000000000000000011 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 11-bit adder for signal <clkdiv[10]_GND_144_o_add_0_OUT> created at line 24.
Found 1-bit tristate buffer for signal <anod<3>> created at line 29
Found 1-bit tristate buffer for signal <anod<2>> created at line 29
Found 1-bit tristate buffer for signal <anod<1>> created at line 29
Found 1-bit tristate buffer for signal <anod<0>> created at line 29
Found 1-bit tristate buffer for signal <catod<6>> created at line 29
Found 1-bit tristate buffer for signal <catod<5>> created at line 29
Found 1-bit tristate buffer for signal <catod<4>> created at line 29
Found 1-bit tristate buffer for signal <catod<3>> created at line 29
Found 1-bit tristate buffer for signal <catod<2>> created at line 29
Found 1-bit tristate buffer for signal <catod<1>> created at line 29
Found 1-bit tristate buffer for signal <catod<0>> created at line 29
Summary:
inferred 1 Adder/Subtractor(s).
inferred 23 D-type flip-flop(s).
inferred 11 Tristate(s).
inferred 1 Finite State Machine(s).
Unit <afisare_sold> synthesized.
Synthesizing Unit <afisare_pin_schimbat>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Afisare_PIN_schimbat.vhd".
Found 1-bit register for signal <PWR_134_o_cclk_DFF_100>.
Found 7-bit register for signal <GND_157_o_dff_15_OUT>.
Found 32-bit register for signal <i>.
Found 11-bit register for signal <clkdiv>.
Found 4-bit register for signal <PWR_133_o_dff_14_OUT>.
Found finite state machine <FSM_1> for signal <i>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 11 |
| Inputs | 2 |
| Outputs | 9 |
| Clock | cclk (rising_edge) |
| Power Up State | 00000000000000000000000000000011 |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 11-bit adder for signal <clkdiv[10]_GND_157_o_add_0_OUT> created at line 20.
Found 1-bit tristate buffer for signal <anod<3>> created at line 26
Found 1-bit tristate buffer for signal <anod<2>> created at line 26
Found 1-bit tristate buffer for signal <anod<1>> created at line 26
Found 1-bit tristate buffer for signal <anod<0>> created at line 26
Found 1-bit tristate buffer for signal <catod<6>> created at line 26
Found 1-bit tristate buffer for signal <catod<5>> created at line 26
Found 1-bit tristate buffer for signal <catod<4>> created at line 26
Found 1-bit tristate buffer for signal <catod<3>> created at line 26
Found 1-bit tristate buffer for signal <catod<2>> created at line 26
Found 1-bit tristate buffer for signal <catod<1>> created at line 26
Found 1-bit tristate buffer for signal <catod<0>> created at line 26
Summary:
inferred 1 Adder/Subtractor(s).
inferred 23 D-type flip-flop(s).
inferred 11 Tristate(s).
inferred 1 Finite State Machine(s).
Unit <afisare_pin_schimbat> synthesized.
Synthesizing Unit <COMP_1000>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_cu_1000.vhd".
WARNING:Xst:647 - Input <suma_ceruta<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:737 - Found 1-bit latch for signal <suma_ok>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Found 12-bit comparator greater for signal <suma_ceruta[15]_GND_171_o_LessThan_1_o> created at line 17
Summary:
inferred 1 Latch(s).
inferred 1 Comparator(s).
Unit <COMP_1000> synthesized.
Synthesizing Unit <COMP_SUMA>.
Related source file is "C:/My_Designs/Proiect_PSN/Automat_Bancar/src/Comparator_SUME.vhd".
Found 16-bit comparator lessequal for signal <n0000> created at line 14
Summary:
inferred 1 Comparator(s).
Unit <COMP_SUMA> synthesized.