Revocation 3.0 PTE bits #18

nwf · 2020-05-15T14:37:33Z

First stab at adjusting PTW for capability load generation bits.

src/cheri_pte.sail

nwf · 2020-05-15T16:44:05Z

For FETT, I think we want to just have SC and LC, taking the other two (LC_Mod and LC_CLG) to be constant 0s.

Speaking of those bits, I'm not elated with the current names... I thought about LC_CLG and LC_LCLG but those aren't great either. Open to suggestions.

pmundkur

generally lgtm, though i haven't checked against the cheri spec.

src/cheri_sys_regs.sail

src/cheri_pte.sail

nwf · 2020-05-15T22:36:20Z

I have added a little more commentary and shuffled the different behaviours so that LC_Mod is more obviously a modification to the LC behaviour and LC_LCLG is now just the LCLG until we have other need for it.

At the moment the code throws if an invalid state is found, but perhaps there's a more correct in-model thing to do. What happens if the RWX bits are set to W or WX, for example?

nwf · 2020-05-27T19:14:18Z

This batch of commits moves us to LoadCapInhibit and StoreCapInhibit bits and shuffles things a bit more so that, again, all-zeros should be what we want. The Load side is more fully fleshed out than the Store side, which, right now, defines but does not use a "fast" capability-dirtying path.

nwf · 2020-06-05T01:52:19Z

This is atop #19 and #20 and should, I think, get both the load and store sides.

nwf · 2020-06-17T23:16:38Z

Orthogonality of commits is hard; where'd those pullbacks of patches go, anyway? This PR now also includes fixes to cheri_insts to pass virtual, not physical, address to handle_mem_exception as well.

src/cheri_pte.sail

bsdjhb · 2020-06-19T20:15:28Z

src/cheri_types.sail

@@ -94,7 +93,7 @@ function CapExCode(ex) : CapEx -> bits(5) =
    CapEx_ReturnTrap                    => 0b00110,
    CapEx_TSSUnderFlow                  => 0b00111,
    CapEx_UserDefViolation              => 0b01000,
-    CapEx_TLBNoStoreCap                 => 0b01001,


At some point we will want to annotate this CHERI exception code as MIPS-only in the ISA doc.

src/cheri_sys_regs.sail

nwf · 2021-04-27T08:25:19Z

Rebased. These continue to pass https://gist.github.com/nwf/cd4d760247ee54e3c9e136ba53d9fdbf ("pte-bits.S")

nwf · 2021-06-17T13:36:09Z

As per CTSRD-CHERI/qemu#150 (comment), @jrtc27 makes an argument that the behaviour of CLoadTags should rather be that it doesn't trap but instead clears tags if the PTW says PTW_LC_CLEAR. Data dependence for the PTW_LC_TRAP case seems perhaps a bridge too far, but could be warranted as well.

nwf · 2021-10-26T22:05:22Z

Renamed CR_Mod to CR_Trap as per @jrtc27's suggestion.

PeterRugg

Looks good to me (I must admit I'd thought this was merged already because I remember testing against it!)

src/cheri_insts.sail

src/cheri_addr_checks.sail

src/cheri_pte.sail

jrtc27 · 2021-11-01T13:36:11Z

src/cheri_sys_regs.sail

  d       :  1,      /* dirty  */
  e       :  0       /* enable */
 }

-register mccsr : ccsr
-register sccsr : ccsr
+register sccsr : ccsr /* mccsr aliases sccsr */
 register uccsr : ccsr


Bit weird to still have uccsr... I kinda get why, but that's primarily because uccsr currently serves no purpose. Also, if mccsr and sccsr alias then normally you'd have the definition be mccsr and sccsr be an alias for (or view into) it, not the other way round.

Well, it "serves no purpose" because the d and e bits are not meaningfully implemented in sail, but they're still defined...

Though maybe that does argue against making sccsr and mccsr alias.

I'm not particularly happy with what I have just written in cheri_pte.sail -- "use sccsr if haveSupMode() and mccsr otherwise" -- but it might be viable. I'm quite open to suggestions.

@jrtc27 Opinions?

Pull up to riscv/sail-riscv@2265a25 Some upstream changes apply to files in this repository as well: - Following along with riscv/sail-riscv@b1db5b9 add ext_check_phys_mem_read and ext_check_phys_mem_write implementations. - Following along with riscv/sail-riscv@9b38e33 always use riscv_flen_D.sail rather than riscv_flen_F.sail on RV32. - Following along with riscv/sail-riscv@ffea7a3 use -fcommon in C_FLAGS.

The cap-store instructions now look at the data being stored to decide whether they issue Write(Cap) or Write(Data) requests on "the bus". This allows the PTW logic (and update_PTE_Bits) in particular to not fast-cap-dirty a page that's being targeted by the store of an untagged capability. This is not, however, viable for AMOCAS and so additional changes may be required if we are to avoid considering AMOCAS as always capability-dirtying. Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

Use Either-monadic style Eliminate ext_ptw_sc / PTW_SC_* as we now simply test the error cases in priority order, so there's no need to explicitly pass this information forward in checkPTEPermission. ext_ptw_lc / PTW_LC_* persist as the extended PTW information is analysed by instructions. Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

arichardson · 2022-12-21T14:22:56Z

src/cheri_pte.sail

+ *                   used if the machine has Supervisor mode, otherwise mccsr.
+ *
+ * Sv32: There are no extension bits available, so we hard-code the result to
+ * CW=1 CR=1 CD=1 CRT=0 CRG=0
 */
 type extPte = bits(10)

 bitfield Ext_PTE_Bits : extPte = {
  CapWrite     : 9, /* Permit capability stores */


This is pre-existing, but bits 9 and 8 conflict with “Svpbmt” Standard Extension for Page-Based Memory Types. I wonder if we should shift everything down by two as part of this change series or start from zero (since upstream started from the top)?

Ouch. I guess that's not the worst possible flag day, it'd just touch sail, the cores, and the CheriBSD kernel.

nwf requested review from pmundkur, jrtc27, jonwoodruff and PeterRugg May 15, 2020 14:37

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nwf force-pushed the clg branch from d14889f to 995e484 Compare May 15, 2020 22:34

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nwf referenced this pull request in CTSRD-CHERI/Flute Jun 3, 2020

Initial implementation of cap PTE bits

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nwf force-pushed the clg branch from daa4b25 to 46b3279 Compare June 5, 2020 01:51

nwf changed the title ~~Introduce capability load generation traps~~ Revocation 3.0 PTE bits Jun 5, 2020

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nwf mentioned this pull request Jun 20, 2020

Fix PTE exceptions #23

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nwf mentioned this pull request Jul 2, 2020

More RISC-V CHERI PTE bits CTSRD-CHERI/qemu#117

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Report CHERI exceptions in xTVAL #40

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Indirect Sentries #51

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Revert to f126dbe

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nwf-msr and others added 5 commits August 19, 2022 23:47

xccsr: pass legalizer the privilege level

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Introduce load-capability generation traps

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Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>

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Revocation 3.0 PTE bits #18

Revocation 3.0 PTE bits #18

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Revocation 3.0 PTE bits #18

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Revocation 3.0 PTE bits #18

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