Add experimental instructions support for riscv

CTSRD-CHERI · Apr 4, 2023 · 017b298 · qwattash · Apr 4, 2023 · qwattash
1 parent c27dd7d
commit 017b298
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Showing 4 changed files with 219 additions and 108 deletions.
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
@@ -77,6 +77,8 @@ DEF_HELPER_3(lr_c_cap, void, env, i32, i32)
 DEF_HELPER_3(sc_c_modedep, tl, env, i32, i32)
 DEF_HELPER_3(sc_c_ddc, tl, env, i32, i32)
 DEF_HELPER_3(sc_c_cap, tl, env, i32, i32)
+/* experimental instruction helpers*/
+DEF_HELPER_2(ctestdereferenceable, tl, env, i32)
 #endif
 
 #ifdef CONFIG_TCG_LOG_INSTR
@@ -271,30 +273,30 @@ DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
 #ifdef TARGET_RISCV64
 DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddd_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxord_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandd_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_d,   void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoord_v_d,   void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomind_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_d,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxd_v_d,  void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
 #endif
 DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_w,   void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_w,  void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
 

diff --git a/target/riscv/insn32-cheri.decode b/target/riscv/insn32-cheri.decode
@@ -57,6 +57,8 @@ ccopytype   0011110  ..... ..... 000 ..... 1011011 @r
 ccseal      0011111  ..... ..... 000 ..... 1011011 @r
 ctestsubset 0100000  ..... ..... 000 ..... 1011011 @r
 cseqx       0100001  ..... ..... 000 ..... 1011011 @r
+candaddr    0100010  ..... ..... 000 ..... 1011011 @r
+
 # 1111011 unused
 # 1111100 Used for Stores (see below)
 # 1111101 Used for Loads (see below)
@@ -85,9 +87,9 @@ cgetaddr    1111111  01111 ..... 000 ..... 1011011 @r2
 # fpclear   1111111  10000 ..... 000 ..... 1011011 @r2
 csealentry  1111111  10001 ..... 000 ..... 1011011 @r2
 cloadtags   1111111  10010 ..... 000 ..... 1011011 @r2
+ctestdereferenceable 1111111  10011 ..... 000 ..... 1011011 @r2
 jalr_pcc    1111111  10100 ..... 000 ..... 1011011 @r2
-
-
+candpermuserdata 1111111  10101 ..... 000 ..... 1011011 @r2
 
 # There is an existing @sfence_vma format with rs1+rs2 fields, but let's define a new name
 @r_2source ....... ..... .....   ... ..... ....... %rs2 %rs1

diff --git a/target/riscv/insn_trans/trans_cheri.c.inc b/target/riscv/insn_trans/trans_cheri.c.inc
@@ -41,7 +41,7 @@
 
 typedef void(cheri_int_cap_helper)(TCGv, TCGv_env, TCGv_i32);
 static inline bool gen_cheri_int_cap(DisasContext *ctx, int rd, int cs,
-                                 cheri_int_cap_helper *gen_func)
+                                     cheri_int_cap_helper *gen_func)
 {
     TCGv_i32 source_regnum = tcg_const_i32(cs);
     TCGv result = tcg_temp_new();
@@ -166,6 +166,9 @@ TRANSLATE_INT_CAP(cgetsealed)
 
 TRANSLATE_INT_CAP(cloadtags)
 
+// experimental ctestdereferenceable
+TRANSLATE_INT_CAP(ctestdereferenceable)
+
 // Two operand (int int)
 static inline bool trans_crrl(DisasContext *ctx, arg_crrl *a)
 {
@@ -181,6 +184,40 @@ TRANSLATE_CAP_CAP(ccleartag)
 TRANSLATE_CAP_CAP(cmove)
 TRANSLATE_CAP_CAP(csealentry)
 
+// experimental candpermuserdata
+
+/* User-defined permission bits. */
+#define CAP_PERM_SW0     (1 << 15) /* 0x00008000 */
+#define CAP_PERM_SW1     (1 << 16) /* 0x00010000 */
+#define CAP_PERM_SW2     (1 << 17) /* 0x00020000 */
+#define CAP_PERM_SW3     (1 << 18) /* 0x00040000 */
+#define CAP_PERM_SW_VMEM CAP_PERM_SW1
+
+#define CAP_PERMS_SWALL                                                        \
+    (CAP_PERM_SW0 | CAP_PERM_SW1 | CAP_PERM_SW2 | CAP_PERM_SW3)
+
+#define CAP_PERMS_USERSPACE                                                    \
+    (CAP_PERM_GLOBAL | CAP_PERM_LOAD | CAP_PERM_LOAD_CAP | CAP_PERM_CINVOKE |  \
+     (CAP_PERMS_SWALL & ~CAP_PERM_SW_VMEM))
+
+#define CAP_PERMS_USERSPACE_DATA                                               \
+    (CAP_PERMS_USERSPACE | CAP_PERM_STORE | CAP_PERM_STORE_CAP |               \
+     CAP_PERM_STORE_LOCAL)
+
+static inline bool trans_candpermuserdata(DisasContext *ctx,
+                                          arg_candpermuserdata *a)
+{
+    TCGv_i32 source_regnum = tcg_const_i32(a->rs1);
+    TCGv_i32 dest_regnum = tcg_const_i32(a->rd);
+    TCGv gpr = tcg_temp_new();
+    gen_set_gpr(gpr, CAP_PERMS_USERSPACE_DATA & ~CAP_PERM_SW_VMEM);
+    gen_helper_candperm(cpu_env, dest_regnum, source_regnum, gpr);
+    tcg_temp_free(gpr);
+    tcg_temp_free_i32(dest_regnum);
+    tcg_temp_free_i32(source_regnum);
+    return true;
+}
+
 // Three operand (cap cap cap)
 TRANSLATE_CAP_CAP_CAP(cbuildcap)
 TRANSLATE_CAP_CAP_CAP(ccopytype)
@@ -215,6 +252,9 @@ TRANSLATE_CAP_CAP_INT(csetboundsexact)
 TRANSLATE_CAP_CAP_INT(csetflags)
 TRANSLATE_CAP_CAP_INT(csetoffset)
 
+// Add experimental CAndAddr instruction
+TRANSLATE_CAP_CAP_INT(candaddr)
+
 // Three operand (int cap cap)
 TRANSLATE_INT_CAP_CAP(csub)
 TRANSLATE_INT_CAP_CAP(ctestsubset)
@@ -268,7 +308,8 @@ static void gen_cjal(DisasContext *ctx, int rd, target_ulong imm)
     tcg_temp_free(new_cursor);
     tcg_temp_free_i32(dst);
 
-    gen_goto_tb(ctx, 0, ctx->base.pc_next + imm, /*bounds_check=*/true); /* must use this for safety */
+    gen_goto_tb(ctx, 0, ctx->base.pc_next + imm,
+                /*bounds_check=*/true); /* must use this for safety */
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -345,7 +386,7 @@ static inline bool gen_cap_load_mem_idx(DisasContext *ctx, int32_t rd,
 }
 
 static inline bool gen_cap_load(DisasContext *ctx, int32_t rd, int32_t cs,
-    target_long offset, MemOp op)
+                                target_long offset, MemOp op)
 {
     return gen_cap_load_mem_idx(ctx, rd, cs, offset, ctx->mem_idx, op);
 }