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<!DOCTYPE html>
<html>
<head>
<title>Cloud V</title>
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<h2><a href=''>Skyus</a> / RiscBEE</h2>
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<p>A Barry good RISC-V RV32i Verilog implementation.</p>
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<div style='left: 20%; top: 20%;'><span><b>1/17</b> - 1043 lines</span></div>
<div style='left: 40%; top: 30%;'><span><b>2/17</b> - 886 lines</span></div>
<div style='left: 60%; top: 75%;'><span><b>3/17</b> - 412 lines</span></div>
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<h3>RiscBEE</h3>
<p>A Barry good RISC-V RV32i Verilog implementation.
(You can blame @KarimIO for the name and the slogan.)
It's a single-cycle RISC-V CPU with completely unaligned byte-addressable memory I/O.
(Though the program ROM is only word addressable and so is memory-mapped I/O).
The Core and parts of the Computer are platform-agnostic, but the final product was implemented on a Xilinx Nexys 3 FPGA.</p>
<p>RiscBEE is a sister project of Oak.js.</p>
<h3>Usage</h3>
<p>You can generate machine code with Oak.js.</p>
<h3>Simulators</h3>
<p>For all simulators, you just wanna use the files in Core. Simulate CPU_tb.v.</p>
<h4>CloudV</h4>
<p>CloudV is a cloud-based simulator and (WIP synthesizer) our CSCE department is working on. To use it, upload all files in Core and comment out all `include statements, then simulate CPU_tb.v.</p>
<h3>FPGA Toolchains</h3>
<p>Comment out all `include statements.</p>
<h4>Xilinx ISE</h4>
<p>Comment out all `include statements, pool all files in Computer, Core and Xilinx FPGA-specific.
You will want to create a ucf file, as well.
To create a coe file easily, you can use the file Scripts/xilinxcoe.js.</p>
<h4>Other</h4>
<p>Not sure what you should do about the `include statements, but you want to use Computer, Core and modify Xilinx FPGA-specific code to code that interfaces with your FPGA's memory resources and I/O.</p>
<h3>License</h3>
<p>Mozilla Public License 2.0. Check 'LICENSE'.</p>
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